70691 lines
4.7 MiB
70691 lines
4.7 MiB
; --------------------------------------------------------------------------------
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; @Title: Kinetis L On-Chip Peripherals
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; @Props: Released
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; @Author: BIC, KAP, KBR, KRW, PBU, JRK, DPR, TRJ
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; @Changelog: 2012-08-28 BIC
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; 2013-10-28 KAP
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; 2015-06-23 PBU
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; 2016-02-08 JRK
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; 2018-11-07 TRJ
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; @Manufacturer: NXP
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; @Doc: KL02P20M48SF0.pdf (Rev.2.1)
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; KL02P20M48SF0RM.pdf (Rev.2.1)
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; KL02P32M48SF0.pdf (Rev.2.1)
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; KL02P32M48SF0RM.pdf (Rev.3.1)
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; KL02P20M48SF0.pdf (Rev.4, 2014-08)
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; KL02P32M48SF0RM.pdf (Rev.3.1, 2013-07)
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; KL02P20M48SF0.pdf (Rev.5, 2017-08)
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; KL02P32M48SF0.pdf (Rev.5, 2017-08)
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; KL03P24M48SF0.pdf (Rev.4, 2014-08)
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; KL03P24M48SF0RM.pdf (Rev.4, 2014-08)
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; KL04RM_Rev.1.pdf
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; KL04P48M48SF1.pdf (Rev.3)
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; KL04P48M48SF1RM.pdf (Rev.3)
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; KL04P48M48SF1.pdf (Rev.4)
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; KL05P48M48SF1.pdf (Rev.4)
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; KL05RM_Rev.1.pdf
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; KL05P48M48SF1.pdf (Rev.3)
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; KL05P48M48SF1RM.pdf (Rev.3)
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; KL14RM_Rev.1.pdf
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; KL14P80M48SF0.pdf (Rev.3)
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; KL14P80M48SF0RM.pdf (Rev.3)
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; KL15RM_Rev.1.pdf
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; KL15P35M48SF0.pdf (Rev.5, 2014-08)
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; KL15P35M48SF0RM.pdf (Rev.2, 2013-12)
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; KL15P80M48SF0.pdf (Rev.3)
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; KL15P80M48SF0RM.pdf (Rev.3)
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; KL16P64M48SF4.pdf (Rev.2)
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; KL16P64M48SF5.pdf (Rev.2)
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; KL16P80M48SF4RM.pdf (Rev.3.2)
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; KL17P64M48SF2.pdf (Rev.4.1, 2015-02)
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; KL17P64M48SF2RM.pdf (Rev.2, 2015-01)
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; KL17P64M48SF6.pdf (Rev.4, 2015-03)
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; KL17P64M48SF6.pdf (Rev.6)
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; KL17P64M48SF2.pdf (Rev.5)
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; KL13P80M48SF3.pdf (Rev.2)
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; KL17P64M48SF6RM.pdf (Rev.4, 2014-09)
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; KL24RM_Rev.1.pdf
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; KL17P64M48SF6RM.pdf (Rev.5.1 2016-07)
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; KL13P80M48SF3RM.pdf (Rev.2.1 2016-07)
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; KL24P80M48SF0.pdf (Rev.3)
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; KL24P80M48SF0RM.pdf (Rev.3)
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; KL25RM_Rev.1.pdf;
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; KL25P80M48SF0.pdf (Rev.3)
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; KL25P80M48SF0RM.pdf (Rev.3)
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; KL26P36M48SF5.pdf (Rev.2, 2014-08)
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; KL26P64M48SF5.pdf (Rev.2)
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; KL26P121M48SF4.pdf (Rev.5, 2014-08)
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; KL26P121M48SF4RM.pdf (Rev.3.3, 2015-04)
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; KL27P64M48SF2.pdf (Rev.4.1, 2015-02)
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; KL27P64M48SF2RM.pdf (Rev.2, 2015-01)
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; KL27P64M48SF2.pdf (Rev. 5, 2015-04)
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; KL27P64M48SF6.pdf (Rev.4, 2015-03)
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; KL27P64M48SF6RM.pdf (Rev 4, 2014-09)
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; KL27P64M48SF6.pdf (Rev. 5,2015-08)
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; KL33P64M48SF6.pdf (Rev.4, 2015-03)
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; KL33P64M48SF6RM.pdf (Rev.4, 2014-09)
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; KL33P64M48SF6RM.pdf (Rev. 5.1,2016-07)
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; KL33P80M48SF3RM.pdf (Rev.2.1, 2016-07)
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; KL33P80M48SF3.pdf (Rev.2, 2015-03)
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; KL33P64M48SF6.pdf (Rev.5,2015-08)
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; KL34P100M48SF4.pdf (Rev.1)
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; KL34P100M48SF4RM.pdf (Rev.3)
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; KL36P121M48SF4.pdf (Rev.1)
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; KL36P121M48SF4RM.pdf (Rev.3)
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; KL36P121M48SF4.pdf (Rev.5 2014-08)
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; KL43P64M48SF6.pdf (Rev.4, 2015-03)
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; KL43P64M48SF6RM.pdf (Rev.4, 2014-09)
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; KL46P121M48SF4.pdf (Rev.1)
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; KL46P121M48SF4RM.pdf (Rev.3)
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; KL82P121M72SF0RM.pdf (Rev.3 2016-08)
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; KL82P121M72SF0.pdf (Rev.4 2016-12)
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; MKL28ZRM.pdf (Rev. 4 2016-06)
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; @Core: Cortex-M0P
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; @Chip: KKL03Z32CAF4R, KKL03Z32CBF4R, KKL15Z128CAD4R, KKL17Z256CAL4R,
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; MKL02Z8VFG4, MKL02Z16VFG4, MKL02Z16VFK4, MKL02Z16VFM4,
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; MKL02Z32VFG4, MKL02Z32VFK4, MKL02Z32VFM4, MKL02Z32CAF4,
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; MKL02Z32CAF4R, MKL03Z8VFG4, MKL03Z8VFK4, MKL03Z16VFG4,
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; MKL03Z16VFK4, MKL03Z32VFG4, MKL03Z32VFK4, MKL03Z32CAF4R,
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; MKL04Z8VFK4, MKL04Z8VFM4, MKL04Z8VLC4, MKL04Z16VFK4,
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; MKL04Z16VFM4, MKL04Z16VLC4, MKL04Z16VLF4, MKL04Z32VFK4,
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; MKL04Z32VFM4, MKL04Z32VLC4, MKL04Z32VLF4, MKL05Z8VFK4,
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; MKL05Z8VFM4, MKL05Z8VLC4, MKL05Z16VFK4, MKL05Z16VFM4,
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; MKL05Z16VLC4, MKL05Z16VLF4, MKL05Z32VFK4, MKL05Z32VFM4,
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; MKL05Z32VLC4, MKL05Z32VLF4, MKL13Z32VLH4, MKL13Z32VLK4,
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; MKL13Z64VLH4, MKL13Z64VLK4, MK14LN32VLH4, MK14LN32VLK4,
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; MK14LN32VFM4, MK14LN32VFT4, MK14LN64VLH4, MK14LN64VLK4,
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; MK14LN64VFM4, MK14LN64VFT4, MKL14Z32VLH4, MKL14Z32VLK4,
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; MKL14Z32VFM4, MKL14Z32VFT4, MKL14Z64VLH4, MKL14Z64VLK4,
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; MKL14Z64VFM4, MKL14Z64VFT4, MK15LN32VLH4, MK15LN32VLK4,
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; MK15LN32VFM4, MK15LN32VFT4, MK15LN64VLH4, MK15LN64VLK4,
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; MK15LN64VFM4, MK15LN64VFT4, MK15LN128VLH4, MK15LN128VLK4,
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; MK15LN128VFM4, MK15LN128VFT4, MKL15Z32VLH4, MKL15Z32VLK4,
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; MKL15Z32VFM4, MKL15Z32VFT4, MKL15Z64VLH4, MKL15Z64VLK4,
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; MKL15Z64VFM4, MKL15Z64VFT4, MKL15Z128VLH4, MKL15Z128VLK4,
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; MKL15Z128VFM4, MKL15Z128VFT4, MKL15Z128CAD4R, MKL16Z32VFM4,
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; MKL16Z32VFT4, MKL16Z32VLH4, MKL16Z64VFM4, MKL16Z64VFT4,
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; MKL16Z64VLH4, MKL16Z128VFM4, MKL16Z128VFT4, MKL16Z128VLH4,
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; MKL16Z256VLH4, MKL16Z256VLK4, MKL16Z256VMP4, MKL17Z32VDA4,
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; MKL17Z32VFM4, MKL17Z32VFT4, MKL17Z32VLH4, MKL17Z32VMP4,
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; MKL17Z64VDA4, MKL17Z64VFM4, MKL17Z64VFT4, MKL17Z64VLH4,
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; MKL17Z64VMP4, MKL17Z128VFM4, MKL17Z128VFT4, MKL17Z128VLH4,
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; MKL17Z128VMP4, MKL17Z256VFM4, MKL17Z256VFT4, MKL17Z256VLH4,
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; MKL17Z256VMP4, MKL24Z32VFM4, MKL24Z32VFT4, MKL24Z32VLH4,
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; MKL24Z32VLK4, MKL24Z64VFM4, MKL24Z64VFT4, MKL24Z64VLH4,
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; MKL24Z64VLK4, MKL25Z32VFM4, MKL25Z32VFT4, MKL25Z32VLH4,
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; MKL25Z32VLK4, MKL25Z64VFM4, MKL25Z64VFT4, MKL25Z64VLH4,
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; MKL25Z64VLK4, MKL25Z128VFM4, MKL25Z128VFT4, MKL25Z128VLH4,
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; MKL25Z128VLK4, MKL26Z32VFM4, MKL26Z32VFT4, MKL26Z32VLH4,
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; MKL26Z64VFM4, MKL26Z64VFT4, MKL26Z64VLH4, MKL26Z128VFM4,
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; MKL26Z128VFT4, MKL26Z128VLH4, MKL26Z128VLL4, MKL26Z128VMC4,
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; MKL26Z128VMP4, MKL26Z128CAL4, MKL26Z256VLH4, MKL26Z256VLL4,
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; MKL26Z256VMC4, MKL26Z256VMP4, MKL27Z32VDA4, MKL27Z32VFM4,
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; MKL27Z32VFT4, MKL27Z32VLH4, MKL27Z32VMP4, MKL27Z64VDA4,
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; MKL27Z64VFM4, MKL27Z64VFT4, MKL27Z64VMP4, MKL27Z64VLH4,
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; MKL27Z128VFM4, MKL27Z128VFT4, MKL27Z128VLH4, MKL27Z128VMP4,
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; MKL27Z256VFM4, MKL27Z256VFT4, MKL27Z256VLH4, MKL27Z256VMP4,
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; MKL33Z128VLH4, MKL33Z128VMP4, MKL33Z256VLH4, MKL33Z256VMP4,
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; MKL34Z64VLH4, MKL34Z64VLL4, MKL36Z64VLH4, MKL36Z64VLL4,
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; MKL36Z128VLH4, MKL36Z128VLL4, MKL36Z128VMC4, MKL36Z256VLH4,
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; MKL36Z256VLL4, MKL36Z256VMC4, MKL36Z256VMP4, MKL43Z128VLH4,
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; MKL43Z128VMP4, MKL43Z256VLH4, MKL43Z256VMP4, MKL46Z128VLH4,
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; MKL46Z128VLL4, MKL46Z128VMC4, MKL46Z256VLH4, MKL46Z256VLL4,
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; MKL46Z256VMC4, MKL46Z256VMP4, MKL82Z128VLK7, MKL82Z128VMC7
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; MKL02Z16VFG4R, MKL02Z32VFG4R, MKL02Z32VFK4R, MKL02Z32VFM4R,
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; MKL02Z8VFG4R, MKL03Z16VFG4R, MKL03Z16VFK4R, MKL03Z32CBF4R,
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; MKL03Z32VFG4R, MKL03Z32VFK4R, MKL03Z8VFG4R, MKL04Z16VLC4R,
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; MKL04Z32VFK4R, MKL04Z32VFM4R, MKL04Z32VLC4R, MKL04Z32VLF4R,
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; MKL04Z8VLC4R, MKL05Z32VFK4R, MKL05Z32VFM4R, MKL05Z32VLC4R,
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; MKL05Z32VLF4R, MKL14Z32VFM4R, MKL14Z64VFM4R, MKL14Z64VFT4R,
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; MKL14Z64VLK4R, MKL15Z128VFM4R, MKL15Z128VLH4R, MKL15Z128VLK4R,
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; MKL15Z32VFM4R, MKL15Z64VFM4R, MKL16Z128VFM4R, MKL16Z128VFT4R,
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; MKL16Z128VLH4R, MKL16Z256VLH4R, MKL16Z256VMP4R, MKL16Z32VFT4R,
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; MKL16Z64VFM4R, MKL16Z64VFT4R, MKL16Z64VLH4R, MKL17Z128VFM4R,
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; MKL17Z128VLH4R, MKL17Z128VMP4R, MKL17Z256CAL4R, MKL17Z256VFT4R,
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; MKL17Z256VLH4R, MKL17Z256VMP4R, MKL17Z32VDA4R, MKL17Z32VFM4R,
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; MKL17Z64VDA4R, MKL17Z64VFM4R, MKL26Z128CAL4R, MKL26Z128VLH4R,
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; MKL26Z256VMC4R, MKL26Z64VFT4R, MKL27Z128VFM4R, MKL27Z128VLH4R,
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; MKL27Z256VFM4R, MKL27Z64VDA4R, MKL27Z64VLH4R, MKL28Z512VLL7,
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; MKL33Z128VLH4R, MKL33Z32VLH4, MKL33Z32VLK4, MKL33Z64VLH4,
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; MKL33Z64VLK4, MKL36Z128VLL4R, MKL36Z256VLL4R, MKL81Z128CBH7R,
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; MKL81Z128VLK7, MKL81Z128VMC7, MKL81Z128VMC7R, MKL82Z128VLK7R
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; @Copyright: (C) 1989-2018 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perkinetisl.per 12107 2020-07-06 08:51:09Z kwitkowski $
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config 16. 8.
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tree.close "Core Registers (Cortex-M0+)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 0x8
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if (CORENAME()=="CORTEXM1")
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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else
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
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bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
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else
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
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endif
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
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hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
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textline " "
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hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
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hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
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group.long 0xd04++0x03
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
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bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
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bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
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bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
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hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
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textline " "
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hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
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if (CORENAME()=="CORTEXM0+")
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group.long 0xd08++0x03
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line.long 0x00 "VTOR,Vector Table Offset Register"
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hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
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else
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textline " "
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endif
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group.long 0xd0c++0x03
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line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
|
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hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
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bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
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textline " "
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bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
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bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
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group.long 0xd10++0x03
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line.long 0x00 "SCR,System Control Register"
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bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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rgroup.long 0xd14++0x03
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line.long 0x00 "CCR,Configuration and Control Register"
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bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
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bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
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group.long 0xd1c++0x0b
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
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bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
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if (CORENAME()=="CORTEXM0+")
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hgroup.long 0x08++0x03
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hide.long 0x00 "ACTLR,Auxiliary Control Register"
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else
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textline " "
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|
endif
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit (MPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
tree.end
|
|
width 6.
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x00 "INT0,Interrupt Priority Register"
|
|
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
|
|
line.long 0x04 "INT1,Interrupt Priority Register"
|
|
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
|
|
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
|
|
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
|
|
line.long 0x08 "INT2,Interrupt Priority Register"
|
|
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
|
|
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
|
|
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
|
|
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
|
|
line.long 0x0C "INT3,Interrupt Priority Register"
|
|
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
|
|
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
|
|
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
|
|
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
|
|
line.long 0x10 "INT4,Interrupt Priority Register"
|
|
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
|
|
line.long 0x14 "INT5,Interrupt Priority Register"
|
|
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
|
|
line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree.open "PORT (Port control and interrupts)"
|
|
base ad:0x40049000
|
|
sif cpuis("MKL02*")||cpuis("MKL04*")||cpuis("MKL05*")||cpuis("MKL03*")
|
|
width 14.
|
|
sif cpuis("MKL0*VFG*")
|
|
width 14.
|
|
tree "PORT_A"
|
|
tree "Pin Control Registers"
|
|
group.long 0x00++0x27
|
|
line.long 0x00 "PORT_A_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL03Z8VFG4")||cpuis("MKL03Z16VFG4")||cpuis("MKL03Z32VFG4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE15/CMP0_IN2,PTA0/IRQ_0/LLWU_P7,TPM1_CH0,SWD_CLK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE12/CMP0_IN2,PTA0/IRQ_0,TPM1_CH0,SWD_CLK,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA1/IRQ_1/LPTMR0_ALT1,TPM_CLKIN0,Reset_b,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA2,CMP0_OUT,SWD_DIO,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL03Z8VFG4")||cpuis("MKL03Z16VFG4")||cpuis("MKL03Z32VFG4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA3,I2C0_SCL,I2C1_SDA,LPUART0_TX,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA3,I2C0_SCL,I2C1_SDA,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL03Z8VFG4")||cpuis("MKL03Z16VFG4")||cpuis("MKL03Z32VFG4")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "XTAL0,PTA4,I2C0_SDA,I2C1_SCL,LPUART0_RX,CLK_OUT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "XTAL0,PTA4,I2C0_SDA,I2C1_SCL,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_A_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL03Z8VFG4")||cpuis("MKL03Z16VFG4")||cpuis("MKL03Z32VFG4")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA5/RTC_CLK_IN,TPM0_CH1,Spi0_ss_b,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA5,TPM0_CH1,Spi0_ss_b,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_A_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Disabled,PTA6,TPM0_CH0,SPI0_MISO,?..."
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_A_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL03Z8VFG4")||cpuis("MKL03Z16VFG4")||cpuis("MKL03Z32VFG4")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "Disabled,PTA7/IRQ_4,SPI0_MISO,SPI0_MOSI,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "ADC0_SE7,PTA7/IRQ_4,SPI0_MISO,SPI0_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x80++0x03
|
|
line.long 0x00 "PORT_A_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x84++0x03
|
|
hide.long 0x00 "PORT_A_GPCHR,Global Pin Control High Register"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORT_A_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_B"
|
|
tree "Pin Control Registers"
|
|
group.long 0x1000++0x1F
|
|
line.long 0x00 "PORT_B_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL03Z8VFG4")||cpuis("MKL03Z16VFG4")||cpuis("MKL03Z32VFG4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE9,PTB0/IRQ_5/LLWU_P4,EXTRG_IN,SPI0_SCK,I2C0_SCL,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE6,PTB0/IRQ_5,EXTRG_IN,SPI0_SCK,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL03Z8VFG4")||cpuis("MKL03Z16VFG4")||cpuis("MKL03Z32VFG4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE8/CMP0_IN3,PTB1/IRQ_6,LPUART0_TX,LPUART0_RX,I2C0_SDA,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE5/CMP0_IN3,PTB1/IRQ_6,UART0_TX,UART0_RX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL03Z8VFG4")||cpuis("MKL03Z16VFG4")||cpuis("MKL03Z32VFG4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "VREF_OUT/CMP0_IN5,PTB2/IRQ_7,LPUART0_RX,LPUART0_TX,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE4,PTB2/IRQ_7,UART0_RX,UART0_TX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL03Z8VFG4")||cpuis("MKL03Z16VFG4")||cpuis("MKL03Z32VFG4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTB3/IRQ_10,I2C0_SCL,LPUART0_TX,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTB3/IRQ_10,I2C0_SCL,UART0_TX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_B_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL03Z8VFG4")||cpuis("MKL03Z16VFG4")||cpuis("MKL03Z32VFG4")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTB4/IRQ_11,I2C0_SDA,LPUART0_RX,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTB4/IRQ_11,I2C0_SDA,UART0_RX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_B_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "ADC0_SE1/CMP0_IN1,PTB5/IRQ_12,TPM1_CH1,Nmi_b,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x1080++0x03
|
|
line.long 0x00 "PORT_B_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x1084++0x03
|
|
hide.long 0x00 "PORT_B_GPCHR,Global Pin Control High Register"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "PORT_B_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL0*CAF*")
|
|
width 14.
|
|
tree "PORT_A"
|
|
tree "Pin Control Registers"
|
|
group.long 0x00++0x27
|
|
line.long 0x00 "PORT_A_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE12/CMP0_IN2,PTA0/IRQ_0/LLWU_P7,TPM1_CH0,SWD_CLK,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA1/IRQ_1/LPTMR0_ALT1,TPM_CLKIN0,Reset_b,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA2,CMP0_OUT,SWD_DIO,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL03Z32CAF4R")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA3,I2C0_SCL,I2C1_SDA,LPUART0_TX,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA3,I2C0_SCL,I2C1_SDA,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL03Z32CAF4R")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "XTAL0,PTA4,I2C0_SDA,I2C1_SCL,LPUART0_RX,CLK_OUT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "XTAL0,PTA4,I2C0_SDA,I2C1_SCL,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_A_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL03Z32CAF4R")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA5/RTC_CLK_IN,TPM0_CH1,Spi0_ss_b,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA5,TPM0_CH1,Spi0_ss_b,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_A_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Disabled,PTA6,TPM0_CH0,SPI0_MISO,?..."
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_A_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "ADC0_SE7,PTA7/IRQ_4,SPI0_MISO,SPI0_MOSI,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x20 "PORT_A_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x20 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL03Z32CAF4R")
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "ADC0_SE3,PTA8,I2C0_SCL,SPI0_MOSI,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "ADC0_SE3,PTA8,I2C1_SCL,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x20 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x20 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x20 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x24 "PORT_A_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x24 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL03Z32CAF4R")
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "ADC0_SE2,PTA9,I2C0_SDA,SPI0_SCK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "ADC0_SE2,PTA9,I2C1_SDA,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x24 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x24 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x24 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PORT_A_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL03Z32CAF4R")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE0/CMP0_IN0,PTA12/IRQ_13/LPTMR0_ALT2,TPM1_CH0,TPM_CLKIN0,,CLK_OUT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE0/CMP0_IN0,PTA12/IRQ_13/LPTMR0_ALT2,TPM1_CH0,TPM_CLKIN0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x80++0x03
|
|
line.long 0x00 "PORT_A_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 28. " GPWE12 ,Global pin 12 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x84++0x03
|
|
hide.long 0x00 "PORT_A_GPCHR,Global Pin Control High Register"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORT_A_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 12. " ISF12 ,Interrupt status flag 12 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_B"
|
|
tree "Pin Control Registers"
|
|
group.long 0x1000++0x1F
|
|
line.long 0x00 "PORT_B_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL03Z32CAF4R")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE6,PTB0/IRQ_5,EXTRG_IN,SPI0_SCK,I2C0_SCL,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE6,PTB0/IRQ_5,EXTRG_IN,SPI0_SCK,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL03Z32CAF4R")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE5/CMP0_IN3,PTB1/IRQ_6,UART0_TX,UART0_RX,I2C0_SDA,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE5/CMP0_IN3,PTB1/IRQ_6,UART0_TX,UART0_RX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL03Z32CAF4R")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "VREF_OUT/CMP0_IN5,PTB2/IRQ_7,LPUART0_RX,LPUART0_TX,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE4,PTB2/IRQ_7,UART0_RX,UART0_TX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTB3/IRQ_10,I2C0_SCL,UART0_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_B_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL03Z32CAF4R")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTB4/IRQ_11,I2C0_SDA,LPUART0_RX,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTB4/IRQ_11,I2C0_SDA,UART0_RX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_B_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "ADC0_SE1/CMP0_IN1,PTB5/IRQ_12,TPM1_CH1,Nmi_b,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x1034++0x03
|
|
line.long 0x00 "PORT_B_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL03Z32CAF4R")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTB13/CLKOUT32K,TPM1_CH1,RTC_CLK_OUT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE13,PTB13,TPM1_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x1080++0x03
|
|
line.long 0x00 "PORT_B_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 29. " GPWE13 ,Global pin 13 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x1084++0x03
|
|
hide.long 0x00 "PORT_B_GPCHR,Global Pin Control High Register"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "PORT_B_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 13. " ISF13 ,Interrupt status flag 13 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL0*VFK*")
|
|
width 14.
|
|
tree "PORT_A"
|
|
tree "Pin Control Registers"
|
|
group.long 0x00++0x27
|
|
line.long 0x00 "PORT_A_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")||cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")||(cpu()=="MKL02Z32VFK4R")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE12/CMP0_IN2,PTA0/IRQ_0,TPM1_CH0,SWD_CLK,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL03*")||(cpu()=="MKL04*")||(cpu()=="MKL05*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE12/CMP0_IN2,PTA0/IRQ_0/LLWU_P7,TPM1_CH0,SWD_CLK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE12/CMP0_IN2,PTA0/IRQ_0/LLWU_P7,TPM1_CH0,SWD_CLK,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")||cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA1/IRQ_1/LPTMR0_ALT1,TPM_CLKIN0,Reset_b,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")||cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA2,CMP0_OUT,SWD_DIO,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")||cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA3,I2C0_SCL,I2C1_SDA,?..."
|
|
textline " "
|
|
elif cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA3,I2C0_SCL,I2C0_SDA,LPUART0_TX,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA3,I2C0_SCL,I2C0_SDA,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")||cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "XTAL0,PTA4,I2C0_SDA,I2C1_SCL,?..."
|
|
textline " "
|
|
elif cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "XTAL0,PTA4,I2C0_SDA,I2C0_SCL,LPUART0_RX,CLK_OUT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "XTAL0,PTA4/LLWU_P0,I2C0_SDA,I2C0_SCL,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_A_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")||cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA5,TPM0_CH1,Spi0_ss_b,?..."
|
|
textline " "
|
|
elif cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA5/RTC_CLK_IN,TPM0_CH1,Spi0_ss_b,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA5/LLWU_P1/RTC_CLK_IN,TPM0_CH5,Spi0_ss_b,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_A_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")||cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")||cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Disabled,PTA6,TPM0_CH0,SPI0_MISO,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Disabled,PTA6/LLWU_P2,TPM0_CH4,SPI0_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_A_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")||cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL04Z32VFK4")||(cpu()=="MKL04Z16VFK4")||(cpu()=="MKL04Z8VFK4")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "ADC0_SE7,PTA7/IRQ_7/LLWU_P3,SPI0_MISO,SPI0_MOSI,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")||cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "Disabled,PTA7/IRQ_4,SPI0_MISO,SPI0_MOSI,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "ADC0_SE7/TSI0_IN5,PTA7/IRQ_7/LLWU_P3,SPI0_MISO,SPI0_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x20 "PORT_A_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x20 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")||cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x20 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x20 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL04Z32VFK4")||(cpu()=="MKL04Z16VFK4")||(cpu()=="MKL04Z8VFK4")
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "ADC0_SE3,PTA8,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "ADC0_SE3,PTA8,I2C1_SCL,?..."
|
|
textline " "
|
|
elif cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "ADC0_SE3,PTA8,I2C0_SCL,SPI0_MOSI,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "ADC0_SE3/TSI0_IN1,PTA8,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x20 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x20 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x20 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x24 "PORT_A_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x24 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")||cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x24 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x24 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL04Z32VFK4")||(cpu()=="MKL04Z16VFK4")||(cpu()=="MKL04Z8VFK4")
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "ADC0_SE2,PTA9,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "ADC0_SE2,PTA9,I2C1_SDA,?..."
|
|
textline " "
|
|
elif cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "ADC0_SE2,PTA9,I2C0_SDA,SPI0_SCK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "ADC0_SE2/TSI0_IN0,PTA9,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x24 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x24 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x24 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PORT_A_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")||cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE0/CMP0_IN0,PTA12/IRQ_13/LPTMR0_ALT2,TPM1_CH0,TPM_CLKIN0,?..."
|
|
textline " "
|
|
elif cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE0/CMP0_IN0,PTA12/IRQ_13/LPTMR0_ALT2,TPM1_CH0,TPM_CLKIN0,,CLK_OUT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE0/CMP0_IN0,PTA12/IRQ_17/LPTMR0_ALT2,TPM1_CH0,TPM_CLKIN0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x80++0x03
|
|
line.long 0x00 "PORT_A_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 28. " GPWE12 ,Global pin 12 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x84++0x03
|
|
hide.long 0x00 "PORT_A_GPCHR,Global Pin Control High Register"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORT_A_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 12. " ISF12 ,Interrupt status flag 12 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_B"
|
|
tree "Pin Control Registers"
|
|
group.long 0x1000++0x1F
|
|
line.long 0x00 "PORT_B_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")||cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL04Z32VFK4")||(cpu()=="MKL04Z16VFK4")||(cpu()=="MKL04Z8VFK4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE6,PTB0/IRQ_8/LLWU_P4,EXTRG_IN,SPI0_SCK,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE6,PTB0/IRQ_5,EXTRG_IN,SPI0_SCK,?..."
|
|
textline " "
|
|
elif cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE9,PTB0/IRQ_5/LLWU_P4,EXTRG_IN,SPI0_SCK,I2C0_SCL,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE6/TSI0_IN4,PTB0/IRQ_8/LLWU_P4,EXTRG_IN,SPI0_SCK,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")||cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL04Z32VFK4")||(cpu()=="MKL04Z16VFK4")||(cpu()=="MKL04Z8VFK4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE5/CMP0_IN3,PTB1/IRQ_9,UART0_TX,UART0_RX,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE5/CMP0_IN3,PTB1/IRQ_6,UART0_TX,UART0_RX,?..."
|
|
textline " "
|
|
elif cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE8/CMP0_IN3,PTB1/IRQ_6,LPUART0_TX,LPUART0_RX,I2C0_SDA,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE5/TSI0_IN3/DAC0_OUT/CMP0_IN3,PTB1/IRQ_9,UART0_TX,UART0_RX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")||cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL04Z32VFK4")||(cpu()=="MKL04Z16VFK4")||(cpu()=="MKL04Z8VFK4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE4,PTB2/IRQ_10/LLWU_P5,UART0_RX,UART0_TX,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE4,PTB2/IRQ_7,UART0_RX,UART0_TX,?..."
|
|
textline " "
|
|
elif cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "VREF_OUT/CMP0_IN5,PTB2/IRQ_7,LPUART0_RX,LPUART0_TX,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE4/TSI0_IN2,PTB2/IRQ_10/LLWU_P5,UART0_RX,UART0_TX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")||cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTB3/IRQ_10,I2C0_SCL,UART0_TX,?..."
|
|
textline " "
|
|
elif cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTB3/IRQ_10,I2C0_SCL,LPUART0_TX,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTB3/IRQ_14,I2C0_SCL,UART0_TX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_B_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")||cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTB4/IRQ_11,I2C0_SDA,UART0_RX,?..."
|
|
textline " "
|
|
elif cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTB4/IRQ_11,I2C0_SDA,LPUART0_RX,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTB4/IRQ_15/LLWU_P6,I2C0_SDA,UART0_RX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_B_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")||cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "ADC0_SE1/CMP0_IN1,PTB5/IRQ_12,TPM1_CH1,Nmi_b,?..."
|
|
textline " "
|
|
elif cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "ADC0_SE1/CMP0_IN1,PTB5/IRQ_12,TPM1_CH1,Nmi_b,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "ADC0_SE1/CMP0_IN1,PTB5/IRQ_16,TPM1_CH1,Nmi_b,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_B_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")||cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")||cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Disabled,PTB6/IRQ_2/LPTMR0_ALT3,TPM1_CH1,TPM_CLKIN1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Disabled,PTB6/IRQ_2/LPTMR0_ALT3,TPM0_CH3,TPM_CLKIN1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_B_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")||cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")||cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "Disabled,PTB7/IRQ_3,TPM1_CH0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "Disabled,PTB7/IRQ_3,TPM0_CH2,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x1028++0x07
|
|
line.long 0x00 "PORT_B_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")||cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL04Z32VFK4")||(cpu()=="MKL04Z16VFK4")||(cpu()=="MKL04Z8VFK4")||(cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE9,PTB10,TPM0_CH1,?..."
|
|
textline " "
|
|
elif cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTB10,TPM0_CH1,Spi0_ss_b,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE9/TSI0_IN7,PTB10,TPM0_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")||cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL04Z32VFK4")||(cpu()=="MKL04Z16VFK4")||(cpu()=="MKL04Z8VFK4")||(cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE8,PTB11,TPM0_CH0,?..."
|
|
textline " "
|
|
elif cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTB11,TPM0_CH0,SPI0_MISO,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE8/TSI0_IN6,PTB11,TPM0_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x1034++0x03
|
|
line.long 0x00 "PORT_B_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")||cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL02Z16VFK4")||(cpu()=="MKL02Z32VFK4")||(cpu()=="MKL02Z32VFK4R")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE13,PTB13,TPM1_CH1,?..."
|
|
textline " "
|
|
elif cpuis("MKL03Z8VFK4")||cpuis("MKL03Z16VFK4")||cpuis("MKL03Z32VFK4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTB13/CLK_OUT_32K,TPM1_CH1,RTC_CLKOUT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE13,PTB13,TPM1_CH1,RTC_CLKOUT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x1080++0x03
|
|
line.long 0x00 "PORT_B_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 29. " GPWE13 ,Global pin 13 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x1084++0x03
|
|
hide.long 0x00 "PORT_B_GPCHR,Global Pin Control High Register"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "PORT_B_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 13. " ISF13 ,Interrupt status flag 13 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL0*VLC*")
|
|
width 14.
|
|
tree "PORT_A"
|
|
tree "Pin Control Registers"
|
|
group.long 0x00++0x37
|
|
line.long 0x00 "PORT_A_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE12/CMP0_IN2,PTA0/IRQ_0/LLWU_P7,TPM1_CH0,SWD_CLK,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA1/IRQ_1/LPTMR0_ALT1,TPM_CLKIN0,Reset_b,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA2,CMP0_OUT,SWD_DIO,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA3,I2C0_SCL,I2C0_SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "XTAL0,PTA4/LLWU_P0,I2C0_SDA,I2C0_SCL,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_A_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA5/LLWU_P1/RTC_CLK_IN,TPM0_CH5,Spi0_ss_b,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_A_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Disabled,PTA6/LLWU_P2,TPM0_CH4,SPI0_MISO,?..."
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_A_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL04Z32VLC4")||(cpu()=="MKL04Z16VLC4")||(cpu()=="MKL04Z8VLC4")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "ADC0_SE7,PTA7/IRQ_7/LLWU_P3,SPI0_MISO,SPI0_MOSI,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "ADC0_SE7/TSI0_IN5,PTA7/IRQ_7/LLWU_P3,SPI0_MISO,SPI0_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x20 "PORT_A_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x20 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL04Z32VLC4")||(cpu()=="MKL04Z16VLC4")||(cpu()=="MKL04Z8VLC4")
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "ADC0_SE3,PTA8,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "ADC0_SE3/TSI0_IN1,PTA8,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x20 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x20 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x20 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x24 "PORT_A_PCR9,Pin Control Register 9"
|
|
bitfld.long 0x24 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL04Z32VLC4")||(cpu()=="MKL04Z16VLC4")||(cpu()=="MKL04Z8VLC4")
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "ADC0_SE2,PTA9,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "ADC0_SE2/TSI0_IN0,PTA9,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x24 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x24 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x24 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x28 "PORT_A_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x28 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x28 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL04Z32VLC4")||(cpu()=="MKL04Z16VLC4")||(cpu()=="MKL04Z8VLC4")
|
|
bitfld.long 0x28 8.--10. " MUX ,Pin mux control" "Disabled,PTA10/IRQ_12,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x28 8.--10. " MUX ,Pin mux control" "TSI0_IN11,PTA10/IRQ_12,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x28 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x28 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x28 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x2C "PORT_A_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x2C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL04Z32VLC4")||(cpu()=="MKL04Z16VLC4")||(cpu()=="MKL04Z8VLC4")
|
|
bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" "Disabled,PTA11/IRQ_13,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" "TSI0_IN10,PTA11/IRQ_13,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x2C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x2C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x2C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x30 "PORT_A_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x30 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x30 8.--10. " MUX ,Pin mux control" "ADC0_SE0/CMP0_IN0,PTA12/IRQ_17/LPTMR0_ALT2,TPM1_CH0,TPM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x30 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x30 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x30 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x30 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x30 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x34 "PORT_A_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x34 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL05Z32VLC4")||(cpu()=="MKL05Z16VLC4")||(cpu()=="MKL05Z8VLC4")
|
|
bitfld.long 0x34 8.--10. " MUX ,Pin mux control" "TSI0_IN9,PTA13,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x34 8.--10. " MUX ,Pin mux control" "Disabled,PTA13,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x34 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x34 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x34 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x34 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x34 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x80++0x03
|
|
line.long 0x00 "PORT_A_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 29. " GPWE13 ,Global pin 13 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 28. " GPWE12 ,Global pin 12 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x84++0x03
|
|
hide.long 0x00 "PORT_A_GPCHR,Global Pin Control High Register"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORT_A_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 13. " ISF13 ,Interrupt status flag 13 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " ISF12 ,Interrupt status flag 12 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_B"
|
|
tree "Pin Control Registers"
|
|
group.long 0x1000++0x37
|
|
line.long 0x00 "PORT_B_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL04Z32VLC4")||(cpu()=="MKL04Z16VLC4")||(cpu()=="MKL04Z8VLC4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE6,PTB0/IRQ_8/LLWU_P4,EXTRG_IN,SPI0_SCK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE6/TSI0_IN4,PTB0/IRQ_8/LLWU_P4,EXTRG_IN,SPI0_SCK,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL04Z32VLC4")||(cpu()=="MKL04Z16VLC4")||(cpu()=="MKL04Z8VLC4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE5/CMP0_IN3,PTB1/IRQ_9,UART0_TX,UART0_RX,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE5/TSI0_IN3/DAC0_OUT/CMP0_IN3,PTB1/IRQ_9,UART0_TX,UART0_RX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL04Z32VLC4")||(cpu()=="MKL04Z16VLC4")||(cpu()=="MKL04Z8VLC4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE4,PTB2/IRQ_10/LLWU_P5,UART0_RX,UART0_TX,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE4/TSI0_IN2,PTB2/IRQ_10/LLWU_P5,UART0_RX,UART0_TX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTB3/IRQ_14,I2C0_SCL,UART0_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_B_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTB4/IRQ_15/LLWU_P6,I2C0_SDA,UART0_RX,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_B_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "ADC0_SE1/CMP0_IN1,PTB5/IRQ_16,TPM1_CH1,Nmi_b,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_B_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Disabled,PTB6/IRQ_2/LPTMR0_ALT3,TPM0_CH3,TPM_CLKIN1,?..."
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_B_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "Disabled,PTB7/IRQ_3,TPM0_CH2,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x20 "PORT_B_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x20 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "ADC0_SE11,PTB8,TPM0_CH3,?..."
|
|
textline " "
|
|
bitfld.long 0x20 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x20 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x20 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x24 "PORT_B_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x24 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "ADC0_SE10,PTB9,TPM0_CH2,?..."
|
|
textline " "
|
|
bitfld.long 0x24 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x24 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x24 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x28 "PORT_B_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x28 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x28 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL04Z32VLC4")||(cpu()=="MKL04Z16VLC4")||(cpu()=="MKL04Z8VLC4")
|
|
bitfld.long 0x28 8.--10. " MUX ,Pin mux control" "ADC0_SE9,PTB10,TPM0_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x28 8.--10. " MUX ,Pin mux control" "ADC0_SE9/TSI0_IN7,PTB10,TPM0_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x28 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x28 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x28 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x2C "PORT_B_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x2C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL04Z32VLC4")||(cpu()=="MKL04Z16VLC4")||(cpu()=="MKL04Z8VLC4")
|
|
bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" "ADC0_SE8,PTB11,TPM0_CH0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" "ADC0_SE8/TSI0_IN6,PTB11,TPM0_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x2C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x2C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x2C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x30 "PORT_B_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x30 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL05Z32VLC4")||(cpu()=="MKL05Z16VLC4")||(cpu()=="MKL05Z8VLC4")
|
|
bitfld.long 0x30 8.--10. " MUX ,Pin mux control" "TSI0_IN8,PTB12,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x30 8.--10. " MUX ,Pin mux control" "Disabled,PTB12,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x30 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x30 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x30 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x30 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x30 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x34 "PORT_B_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x34 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x34 8.--10. " MUX ,Pin mux control" "ADC0_SE13,PTB13,TPM1_CH1,RTC_CLKOUT,?..."
|
|
textline " "
|
|
bitfld.long 0x34 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x34 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x34 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x34 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x34 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x1080++0x03
|
|
line.long 0x00 "PORT_B_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 29. " GPWE13 ,Global pin 13 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 28. " GPWE12 ,Global pin 12 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x1084++0x03
|
|
hide.long 0x00 "PORT_B_GPCHR,Global Pin Control High Register"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "PORT_B_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 13. " ISF13 ,Interrupt status flag 13 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " ISF12 ,Interrupt status flag 12 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL0*VFM*")
|
|
width 14.
|
|
tree "PORT_A"
|
|
tree "Pin Control Registers"
|
|
group.long 0x00++0x37
|
|
line.long 0x00 "PORT_A_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE12/CMP0_IN2,PTA0/IRQ_0,TPM1_CH0,SWD_CLK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE12/CMP0_IN2,PTA0/IRQ_0/LLWU_P7,TPM1_CH0,SWD_CLK,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA1/IRQ_1/LPTMR0_ALT1,TPM_CLKIN0,Reset_b,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA2,CMP0_OUT,SWD_DIO,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA3,I2C0_SCL,I2C1_SDA,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA3,I2C0_SCL,I2C0_SDA,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "XTAL0,PTA4,I2C0_SDA,I2C1_SCL,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "XTAL0,PTA4/LLWU_P0,I2C0_SDA,I2C0_SCL,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_A_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA5,TPM0_CH1,Spi0_ss_b,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA5/LLWU_P1/RTC_CLK_IN,TPM0_CH5,Spi0_ss_b,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_A_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Disabled,PTA6,TPM0_CH0,SPI0_MISO,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Disabled,PTA6/LLWU_P2,TPM0_CH4,SPI0_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_A_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL04*")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "ADC0_SE7,PTA7/IRQ_7/LLWU_P3,SPI0_MISO,SPI0_MOSI,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL02*")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "ADC0_SE7,PTA7/IRQ_4,SPI0_MISO,SPI0_MOSI,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "ADC0_SE7/TSI0_IN5,PTA7/IRQ_7/LLWU_P3,SPI0_MISO,SPI0_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x20 "PORT_A_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x20 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x20 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x20 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL04*")
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "ADC0_SE3,PTA8,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL02*")
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "ADC0_SE3,PTA8,I2C1_SCL,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "ADC0_SE3/TSI0_IN1,PTA8,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x20 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x20 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x20 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x24 "PORT_A_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x24 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x24 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x24 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL04*")
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "ADC0_SE2,PTA9,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL02*")
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "ADC0_SE2,PTA9,I2C1_SDA,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "ADC0_SE2/TSI0_IN0,PTA9,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x24 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x24 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x24 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x28 "PORT_A_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x28 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x28 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x28 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL04*")
|
|
bitfld.long 0x28 8.--10. " MUX ,Pin mux control" "Disabled,PTA10/IRQ_12,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL02*")
|
|
bitfld.long 0x28 8.--10. " MUX ,Pin mux control" "Disabled,PTA10/IRQ_8,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x28 8.--10. " MUX ,Pin mux control" "TSI0_IN11,PTA10/IRQ_12,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x28 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x28 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x28 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x2C "PORT_A_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x2C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x2C 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x2C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL04*")
|
|
bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" "Disabled,PTA11/IRQ_13,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL02*")
|
|
bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" "Disabled,PTA11/IRQ_9,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" "TSI0_IN10,PTA11/IRQ_13,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x2C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x2C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x2C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x30 "PORT_A_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x30 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x30 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x30 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x30 8.--10. " MUX ,Pin mux control" "ADC0_SE0/CMP0_IN0,PTA12/IRQ_13/LPTMR0_ALT2,TPM1_CH0,TPM_CLKIN0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x30 8.--10. " MUX ,Pin mux control" "ADC0_SE0/CMP0_IN0,PTA12/IRQ_17/LPTMR0_ALT2,TPM1_CH0,TPM_CLKIN0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x30 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x30 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x30 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x30 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x30 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x34 "PORT_A_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x34 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x34 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x34 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL05Z32VFM4")||(cpu()=="MKL05Z16VFM4")||(cpu()=="MKL05Z8VFM4")
|
|
bitfld.long 0x34 8.--10. " MUX ,Pin mux control" "TSI0_IN9,PTA13,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x34 8.--10. " MUX ,Pin mux control" "Disabled,PTA13,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x34 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x34 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x34 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x34 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x34 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
width 14.
|
|
textline " "
|
|
wgroup.long 0x80++0x03
|
|
line.long 0x00 "PORT_A_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 29. " GPWE13 ,Global pin 13 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 28. " GPWE12 ,Global pin 12 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x84++0x03
|
|
hide.long 0x00 "PORT_A_GPCHR,Global Pin Control High Register"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORT_A_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 13. " ISF13 ,Interrupt status flag 13 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " ISF12 ,Interrupt status flag 12 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_B"
|
|
tree "Pin Control Registers"
|
|
group.long 0x1000++0x37
|
|
line.long 0x00 "PORT_B_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL04*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE6,PTB0/IRQ_8/LLWU_P4,EXTRG_IN,SPI0_SCK,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL02*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE6,PTB0/IRQ_5,EXTRG_IN,SPI0_SCK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE6/TSI0_IN4,PTB0/IRQ_8/LLWU_P4,EXTRG_IN,SPI0_SCK,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL04*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE5/CMP0_IN3,PTB1/IRQ_9,UART0_TX,UART0_RX,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL02*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE5/CMP0_IN3,PTB1/IRQ_6,UART0_TX,UART0_RX,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE5/TSI0_IN3/DAC0_OUT/CMP0_IN3,PTB1/IRQ_9,UART0_TX,UART0_RX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL04*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE4,PTB2/IRQ_10/LLWU_P5,UART0_RX,UART0_TX,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL02*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE4,PTB2/IRQ_7,UART0_RX,UART0_TX,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE4/TSI0_IN2,PTB2/IRQ_10/LLWU_P5,UART0_RX,UART0_TX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTB3/IRQ_10,I2C0_SCL,UART0_TX,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTB3/IRQ_14,I2C0_SCL,UART0_TX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_B_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTB4/IRQ_11,I2C0_SDA,UART0_RX,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTB4/IRQ_15/LLWU_P6,I2C0_SDA,UART0_RX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_B_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "ADC0_SE1/CMP0_IN1,PTB5/IRQ_12,TPM1_CH1,Nmi_b,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "ADC0_SE1/CMP0_IN1,PTB5/IRQ_16,TPM1_CH1,Nmi_b,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_B_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Disabled,PTB6/IRQ_2/LPTMR0_ALT3,TPM1_CH1,TPM_CLKIN1,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL05Z8VFM4")||(cpu()=="MKL05Z16VFM4")||(cpu()=="MKL05Z32VFM4")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Disabled,PTB6/IRQ_2/LPTMR0_ALT3,TPM0_CH3,TPM_CLKIN1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Disabled,PTB6/IRQ_2/LPTMR0_ALT3,TPM1_CH1,TPM_CLKIN1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_B_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "Disabled,PTB7/IRQ_3,TPM1_CH0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "Disabled,PTB7/IRQ_3,TPM0_CH2,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x20 "PORT_B_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x20 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x20 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x20 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "ADC0_SE11,PTB8,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "ADC0_SE11,PTB8,TPM0_CH3,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x20 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x20 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x20 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x24 "PORT_B_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x24 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x24 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x24 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "ADC0_SE10,PTB9,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "ADC0_SE10,PTB9,TPM0_CH2,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x24 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x24 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x24 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x28 "PORT_B_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x28 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x28 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x28 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL04*")||(cpu()=="MKL02*")
|
|
bitfld.long 0x28 8.--10. " MUX ,Pin mux control" "ADC0_SE9,PTB10,TPM0_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x28 8.--10. " MUX ,Pin mux control" "ADC0_SE9/TSI0_IN7,PTB10,TPM0_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x28 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x28 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x28 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x2C "PORT_B_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x2C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x2C 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x2C 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL04*")||(cpu()=="MKL02*")
|
|
bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" "ADC0_SE8,PTB11,TPM0_CH0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" "ADC0_SE8/TSI0_IN6,PTB11,TPM0_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x2C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x2C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x2C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x30 "PORT_B_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x30 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x30 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x30 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL05Z32VFM4")||(cpu()=="MKL05Z16VFM4")||(cpu()=="MKL05Z8VFM4")
|
|
bitfld.long 0x30 8.--10. " MUX ,Pin mux control" "TSI0_IN8,PTB12,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x30 8.--10. " MUX ,Pin mux control" "Disabled,PTB12,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x30 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x30 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x30 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x30 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x30 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x34 "PORT_B_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x34 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x34 16.--19. " IRQC ,Interrupt configuration" "Disabled,,,,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x34 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="MKL02*")
|
|
bitfld.long 0x34 8.--10. " MUX ,Pin mux control" "ADC0_SE13,PTB13,TPM1_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x34 8.--10. " MUX ,Pin mux control" "ADC0_SE13,PTB13,TPM1_CH1,RTC_CLKOUT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x34 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x34 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x34 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x34 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x34 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
width 14.
|
|
wgroup.long 0x1080++0x03
|
|
line.long 0x00 "PORT_B_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 29. " GPWE13 ,Global pin 13 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 28. " GPWE12 ,Global pin 12 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x1084++0x03
|
|
hide.long 0x00 "PORT_B_GPCHR,Global Pin Control High Register"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "PORT_B_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 13. " ISF13 ,Interrupt status flag 13 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " ISF12 ,Interrupt status flag 12 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL0*VLF*")
|
|
width 14.
|
|
tree "PORT_A"
|
|
tree "Pin Control Registers"
|
|
group.long 0x00++0x4F
|
|
line.long 0x00 "PORT_A_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE12/CMP0_IN2,PTA0/IRQ_0/LLWU_P7,TPM1_CH0,SWD_CLK,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA1/IRQ_1/LPTMR0_ALT1,TPM_CLKIN0,Reset_b,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA2,CMP0_OUT,SWD_DIO,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA3,I2C0_SCL,I2C0_SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "XTAL0,PTA4/LLWU_P0,I2C0_SDA,I2C0_SCL,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_A_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA5/LLWU_P1/RTC_CLK_IN,TPM0_CH5,Spi0_ss_b,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_A_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Disabled,PTA6/LLWU_P2,TPM0_CH4,SPI0_MISO,?..."
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_A_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL04Z32VLF4")||(cpu()=="MKL04Z16VLF4")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "ADC0_SE7,PTA7/IRQ_7/LLWU_P3,SPI0_MISO,SPI0_MOSI,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "ADC0_SE7/TSI0_IN5,PTA7/IRQ_7/LLWU_P3,SPI0_MISO,SPI0_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x20 "PORT_A_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x20 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL04Z32VLF4")||(cpu()=="MKL04Z16VLF4")
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "ADC0_SE3,PTA8,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "ADC0_SE3/TSI0_IN1,PTA8,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x20 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x20 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x20 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x24 "PORT_A_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x24 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL04Z32VLF4")||(cpu()=="MKL04Z16VLF4")
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "ADC0_SE2,PTA9,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "ADC0_SE2/TSI0_IN0,PTA9,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x24 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x24 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x24 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x28 "PORT_A_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x28 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x28 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL04Z32VLF4")||(cpu()=="MKL04Z16VLF4")
|
|
bitfld.long 0x28 8.--10. " MUX ,Pin mux control" "Disabled,PTA10/IRQ_12,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x28 8.--10. " MUX ,Pin mux control" "TSI0_IN11,PTA10/IRQ_12,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x28 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x28 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x28 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x2C "PORT_A_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x2C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL04Z32VLF4")||(cpu()=="MKL04Z16VLF4")
|
|
bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" "Disabled,PTA11/IRQ_13,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" "TSI0_IN10,PTA11/IRQ_13,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x2C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x2C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x2C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x30 "PORT_A_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x30 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x30 8.--10. " MUX ,Pin mux control" "ADC0_SE0/CMP0_IN0,PTA12/IRQ_17/LPTMR0_ALT2,TPM1_CH0,TPM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x30 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x30 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x30 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x30 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x30 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x34 "PORT_A_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x34 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL05Z32VLF4")||(cpu()=="MKL05Z16VLF4")
|
|
bitfld.long 0x34 8.--10. " MUX ,Pin mux control" "TSI0_IN9,PTA13,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x34 8.--10. " MUX ,Pin mux control" "Disabled,PTA13,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x34 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x34 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x34 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x34 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x34 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x38 "PORT_A_PCR14,Pin Control Register 14"
|
|
eventfld.long 0x38 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x38 8.--10. " MUX ,Pin mux control" "Disabled,PTA14,,TPM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x38 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x38 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x38 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x38 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x38 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x3C "PORT_A_PCR15,Pin Control Register 15"
|
|
eventfld.long 0x3C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x3C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x3C 8.--10. " MUX ,Pin mux control" "Disabled,PTA15,,CLKOUT,?..."
|
|
textline " "
|
|
bitfld.long 0x3C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x3C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x3C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x3C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x3C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x40 "PORT_A_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x40 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x40 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x40 8.--10. " MUX ,Pin mux control" "Disabled,PTA16/IRQ_4,?..."
|
|
textline " "
|
|
bitfld.long 0x40 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x40 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x40 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x40 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x40 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x44 "PORT_A_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x44 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x44 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x44 8.--10. " MUX ,Pin mux control" "Disabled,PTA17/IRQ_5,?..."
|
|
textline " "
|
|
bitfld.long 0x44 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x44 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x44 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x44 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x44 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x48 "PORT_A_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x48 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x48 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x48 8.--10. " MUX ,Pin mux control" "Disabled,PTA18/IRQ_6,?..."
|
|
textline " "
|
|
bitfld.long 0x48 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x48 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x48 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x48 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x48 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x4C "PORT_A_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x4C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x4C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x4C 8.--10. " MUX ,Pin mux control" "Disabled,PTA19,,Spi0_ss_b,?..."
|
|
textline " "
|
|
bitfld.long 0x4C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x4C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x4C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x4C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x4C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x80++0x07
|
|
line.long 0x00 "PORT_A_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 31. " GPWE15 ,Global pin 15 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 30. " GPWE14 ,Global pin 14 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 29. " GPWE13 ,Global pin 13 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GPWE12 ,Global pin 12 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_A_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORT_A_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 15. " ISF15 ,Interrupt status flag 15 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " ISF14 ,Interrupt status flag 14 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " ISF13 ,Interrupt status flag 13 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " ISF12 ,Interrupt status flag 12 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_B"
|
|
tree "Pin Control Registers"
|
|
group.long 0x1000++0x53
|
|
line.long 0x00 "PORT_B_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL04Z32VLF4")||(cpu()=="MKL04Z16VLF4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE6,PTB0/IRQ_8/LLWU_P4,EXTRG_IN,SPI0_SCK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE6/TSI0_IN4,PTB0/IRQ_8/LLWU_P4,EXTRG_IN,SPI0_SCK,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL04Z32VLF4")||(cpu()=="MKL04Z16VLF4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE5/CMP0_IN3,PTB1/IRQ_9,UART0_TX,UART0_RX,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE5/TSI0_IN3/DAC0_OUT/CMP0_IN3,PTB1/IRQ_9,UART0_TX,UART0_RX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL04Z32VLF4")||(cpu()=="MKL04Z16VLF4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE4,PTB2/IRQ_10/LLWU_P5,UART0_RX,UART0_TX,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE4/TSI0_IN2,PTB2/IRQ_10/LLWU_P5,UART0_RX,UART0_TX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTB3/IRQ_14,I2C0_SCL,UART0_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_B_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTB4/IRQ_15/LLWU_P6,I2C0_SDA,UART0_RX,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_B_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "ADC0_SE1/CMP0_IN1,PTB5/IRQ_16,TPM1_CH1,Nmi_b,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_B_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Disabled,PTB6/IRQ_2/LPTMR0_ALT3,TPM0_CH3,TPM_CLKIN1,?..."
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_B_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "Disabled,PTB7/IRQ_3,TPM0_CH2,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x20 "PORT_B_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x20 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "ADC0_SE11,PTB8,TPM0_CH3,?..."
|
|
textline " "
|
|
bitfld.long 0x20 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x20 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x20 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x24 "PORT_B_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x24 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "ADC0_SE10,PTB9,TPM0_CH2,?..."
|
|
textline " "
|
|
bitfld.long 0x24 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x24 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x24 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x28 "PORT_B_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x28 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x28 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL04Z32VLF4")||(cpu()=="MKL04Z16VLF4")
|
|
bitfld.long 0x28 8.--10. " MUX ,Pin mux control" "ADC0_SE9,PTB10,TPM0_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x28 8.--10. " MUX ,Pin mux control" "ADC0_SE9/TSI0_IN7,PTB10,TPM0_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x28 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x28 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x28 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x2C "PORT_B_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x2C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL04Z32VLF4")||(cpu()=="MKL04Z16VLF4")
|
|
bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" "ADC0_SE8,PTB11,TPM0_CH0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" "ADC0_SE8/TSI0_IN6,PTB11,TPM0_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x2C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x2C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x2C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x30 "PORT_B_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x30 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL05Z32VLF4")||(cpu()=="MKL05Z16VLF4")
|
|
bitfld.long 0x30 8.--10. " MUX ,Pin mux control" "TSI0_IN8,PTB12,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x30 8.--10. " MUX ,Pin mux control" "Disabled,PTB12,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x30 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x30 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x30 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x30 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x30 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x34 "PORT_B_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x34 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x34 8.--10. " MUX ,Pin mux control" "ADC0_SE13,PTB13,TPM1_CH1,RTC_CLKOUT,?..."
|
|
textline " "
|
|
bitfld.long 0x34 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x34 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x34 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x34 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x34 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x38 "PORT_B_PCR14,Pin Control Register 14"
|
|
eventfld.long 0x38 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x38 8.--10. " MUX ,Pin mux control" "Disabled,PTB14/IRQ_11,EXTRG_IN,?..."
|
|
textline " "
|
|
bitfld.long 0x38 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x38 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x38 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x38 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x38 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x3C "PORT_B_PCR15,Pin Control Register 15"
|
|
eventfld.long 0x3C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x3C 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x3C 8.--10. " MUX ,Pin mux control" "Disabled,PTB15,SPI0_MOSI,SPI0_MISO,?..."
|
|
textline " "
|
|
bitfld.long 0x3C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x3C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x3C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x3C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x3C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x40 "PORT_B_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x40 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x40 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x40 8.--10. " MUX ,Pin mux control" "Disabled,PTB16,SPI0_MISO,SPI0_MOSI,?..."
|
|
textline " "
|
|
bitfld.long 0x40 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x40 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x40 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x40 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x40 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x44 "PORT_B_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x44 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x44 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x44 8.--10. " MUX ,Pin mux control" "Disabled,PTB17,TPM_CLKIN1,SPI0_SCK,?..."
|
|
textline " "
|
|
bitfld.long 0x44 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x44 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x44 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x44 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x44 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x48 "PORT_B_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x48 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x48 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x48 8.--10. " MUX ,Pin mux control" "Disabled,PTB18,?..."
|
|
textline " "
|
|
bitfld.long 0x48 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x48 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x48 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x48 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x48 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x4C "PORT_B_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x4C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x4C 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x4C 8.--10. " MUX ,Pin mux control" "Disabled,PTB19,?..."
|
|
textline " "
|
|
bitfld.long 0x4C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x4C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x4C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x4C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x4C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x50 "PORT_B_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x50 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x50 16.--19. " IRQC ,Interrupt/dma request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x50 8.--10. " MUX ,Pin mux control" "Disabled,PTB20,?..."
|
|
textline " "
|
|
bitfld.long 0x50 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x50 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x50 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x50 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x50 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x1080++0x07
|
|
line.long 0x00 "PORT_B_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 31. " GPWE15 ,Global pin 15 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 30. " GPWE14 ,Global pin 14 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 29. " GPWE13 ,Global pin 13 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GPWE12 ,Global pin 12 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_B_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "PORT_B_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 15. " ISF15 ,Interrupt status flag 15 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 14. " ISF14 ,Interrupt status flag 14 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " ISF13 ,Interrupt status flag 13 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " ISF12 ,Interrupt status flag 12 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
width 0x0B
|
|
endif
|
|
width 0x0B
|
|
elif cpuis("MKL14*")||cpuis("MK14LN*")||cpuis("MKL15*")||cpuis("MK15LN*")||cpuis("MKL16*")||cpuis("MKL17Z*")
|
|
width 12.
|
|
sif cpuis("MK?1*VFM*")
|
|
width 14.
|
|
tree "PORT_A"
|
|
tree "Pin Control Registers"
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "PORT_A_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFM4")||(cpu()=="MKL14Z32VFM4")||(cpu()=="MK14LN32VFM4")||(cpu()=="MKL14Z64VFM4")||cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTA0,,TPM0_CH5,,,,SWD_CLK"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH1,PTA0,,TPM0_CH5,,,,SWD_CLK"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFM4")||(cpu()=="MKL14Z32VFM4")||(cpu()=="MK14LN32VFM4")||(cpu()=="MKL14Z64VFM4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA1,UART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA1,LPUART0_RX,TPM2_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH2,PTA1,UART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFM4")||(cpu()=="MKL14Z32VFM4")||(cpu()=="MK14LN32VFM4")||(cpu()=="MKL14Z64VFM4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA2,UART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA1,LPUART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "TSI0_CH3,PTA2,UART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTA3,I2C1_SCL,TPM0_CH0,,,,SWD_DIO"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "TSI0_CH4,PTA3,I2C1_SCL,TPM0_CH0,,,,SWD_DIO"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFM4")||(cpu()=="MKL14Z32VFM4")||(cpu()=="MK14LN32VFM4")||(cpu()=="MKL14Z64VFM4")||cpuis("MKL17Z32VFM4")||cpuis("MKL17Z64VFM4")||cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTA4,I2C1_SDA,TPM0_CH1,,,,Nmi_b"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "TSI0_CH5,PTA4,I2C1_SDA,TPM0_CH1,,,,Nmi_b"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x48++0x0B
|
|
line.long 0x00 "PORT_A_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,LPUART1_RX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,UART1_RX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,,LPUART1_TX,TPM_CLKIN1,,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,,UART1_TX,TPM_CLKIN1,,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL16Z32VFM4")||(cpu()=="MKL16Z64VFM4")||(cpu()=="MKL16Z128VFM4")||cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA20,,,,,,Reset_b"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA20,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x80++0x07
|
|
line.long 0x00 "PORT_A_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_A_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORT_A_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_B"
|
|
tree "Pin Control Registers"
|
|
group.long 0x1000++0x07
|
|
line.long 0x00 "PORT_B_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFM4")||(cpu()=="MKL14Z32VFM4")||(cpu()=="MK14LN32VFM4")||(cpu()=="MKL14Z64VFM4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z32V*")||cpuis("MKL17Z64V*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,SPI1_MOSI,SPI1_MISO,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8/TSI0_CH0,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFM4")||(cpu()=="MKL14Z32VFM4")||(cpu()=="MK14LN32VFM4")||(cpu()=="MKL14Z64VFM4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9,PTB1,I2C0_SDA,TPM1_CH1,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z32V*")||cpuis("MKL17Z64V*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9,PTB1,I2C0_SDA,TPM1_CH1,SPI1_MISO,SPI1_MOSI,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9/TSI0_CH6,PTB1,I2C0_SDA,TPM1_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x1080++0x03
|
|
line.long 0x00 "PORT_B_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x1084++0x03
|
|
hide.long 0x00 "PORT_B_GPCHR,Global Pin Control High Register"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "PORT_B_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_C"
|
|
tree "Pin Control Registers"
|
|
group.long 0x2004++0x1B
|
|
line.long 0x00 "PORT_C_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFM4")||(cpu()=="MKL14Z32VFM4")||(cpu()=="MK14LN32VFM4")||(cpu()=="MKL14Z64VFM4")||cpuis("MKL13Z*")||cpuis("MKL17Z32V*")||cpuis("MKL17Z64V*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE15,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL16Z32VFM4")||(cpu()=="MKL16Z64VFM4")||(cpu()=="MKL16Z128VFM4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE15/TSI0_CH14,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,,I2S0_TXD0,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")||cpuis("MKL17Z256CAL4R")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE15,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,,I2S0_TXD0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE15/TSI0_CH14,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_C_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFM4")||(cpu()=="MKL14Z32VFM4")||(cpu()=="MK14LN32VFM4")||(cpu()=="MKL14Z64VFM4")||cpuis("MKL17Z32V*")||cpuis("MKL17Z64V*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE11,PTC2,I2C1_SDA,,TPM0_CH1,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE11,PTC2,I2C1_SDA,,TPM0_CH1,,I2S0_TX_FS,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL16Z32VFM4")||(cpu()=="MKL16Z64VFM4")||(cpu()=="MKL16Z128VFM4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE11/TSI0_CH15,PTC2,I2C1_SDA,,TPM0_CH1,,I2S0_TX_FS,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE11/TSI0_CH15,PTC2,I2C1_SDA,,TPM0_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_C_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL16Z32VFM4")||(cpu()=="MKL16Z64VFM4")||(cpu()=="MKL16Z128VFM4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTC3/LLWU_P7,,UART1_RX,TPM0_CH2,CLKOUT,I2S0_TX_BCLK,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTC3/LLWU_P7,SPI1_SCK,LPUART1_RX,TPM0_CH2,CLKOUT,I2S0_TX_BCLK,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z32VFM4")||cpuis("MKL17Z64VFM4")||cpuis("MKL13Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTC3/LLWU_P7,SPI1_SCK,LPUART1_RX,TPM0_CH2,CLKOUT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTC3/LLWU_P7,,UART1_RX,TPM0_CH2,CLKOUT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_C_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL16Z32VFM4")||(cpu()=="MKL16Z64VFM4")||(cpu()=="MKL16Z128VFM4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTC4/LLWU_P8,SPI0_PCS0,UART1_TX,TPM0_CH3,I2S0_MCLK,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTC4/LLWU_P8,SPI0_SS,LPUART1_TX,TPM0_CH3,I2S0_MCLK,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z32V*")||cpuis("MKL17Z64V*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTC4/LLWU_P8,SPI0_PCS0,LPUART1_TX,TPM0_CH3,SPI1_PCS0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTC4/LLWU_P8,SPI0_PCS0,UART1_TX,TPM0_CH3,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_C_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL16Z32VFM4")||(cpu()=="MKL16Z64VFM4")||(cpu()=="MKL16Z128VFM4")||cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,I2S0_RXD0,,CMP0_OUT,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z32VFM4")||cpuis("MKL17Z64VFM4")||cpuis("MKL13Z*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,,,CMP0_OUT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,,,CMP0_OUT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_C_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "CMP0_IN0,PTC6/LLWU_P10,SPI0_MOSI,EXTRG_IN,I2S0_RX_BCLK,SPI0_MISO,I2S0_MCLK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "CMP0_IN0,PTC6/LLWU_P10,SPI0_MOSI,EXTRG_IN,,SPI0_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_C_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL16Z32VFM4")||(cpu()=="MKL16Z64VFM4")||(cpu()=="MKL16Z128VFM4")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,SPI0_MISO,,I2S0_RX_FS,SPI0_MOSI,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,SPI0_MISO,Audiousb_sof_out,I2S0_RX_FS,SPI0_MOSI,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,SPI0_MISO,,,SPI0_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x2080++0x03
|
|
line.long 0x00 "PORT_C_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x2084++0x03
|
|
hide.long 0x00 "PORT_C_GPCHR,Global Pin Control High Register"
|
|
group.long 0x20A0++0x03
|
|
line.long 0x00 "PORT_C_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_D"
|
|
tree "Pin Control Registers"
|
|
group.long 0x3010++0x0F
|
|
line.long 0x00 "PORT_D_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z32V*")||cpuis("MKL17Z64V*")||cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTD4/LLWU_P14,SPI1_PCS0,UART2_RX,TPM0_CH4,,FXIO0_D4,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTD4/LLWU_P14,SPI1_PCS0,UART2_RX,TPM0_CH4,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_D_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_se6b,PTD5,SPI1_SCK,UART2_TX,TPM0_CH5,,FXIO0_D5,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_se6b,PTD5,SPI1_SCK,UART2_TX,TPM0_CH5,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_D_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,LPUART0_RX,,SPI1_MISO,FXIO0_D6,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z32V*")||cpuis("MKL17Z64V*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,LPUART0_RX,I2C1_SDA,SPI1_MISO,FXIO0_D6,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,UART0_RX,,SPI1_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_D_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTD7,SPI1_MISO,LPUART0_TX,,SPI1_MOSI,FXIO0_D7,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z32V*")||cpuis("MKL17Z64V*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTD7,SPI1_MISO,LPUART0_TX,I2C1_SCL,SPI1_MOSI,FXIO0_D7,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTD7,SPI1_MISO,UART0_TX,,SPI1_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x3080++0x03
|
|
line.long 0x00 "PORT_D_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x3084++0x03
|
|
hide.long 0x00 "PORT_D_GPCHR,Global Pin Control High Register"
|
|
group.long 0x30A0++0x03
|
|
line.long 0x00 "PORT_D_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_E"
|
|
tree "Pin Control Registers"
|
|
group.long 0x4000++0x07
|
|
line.long 0x00 "PORT_E_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL16Z32VFM4")||(cpu()=="MKL16Z64VFM4")||(cpu()=="MKL16Z128VFM4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTE0,SPI1_MISO,UART1_TX,RTC_CLKOUT,CMP0_OUT,I2C1_SDA,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTE0,SPI1_MISO,LPUART1_TX,RTC_CLKOUT,CMP0_OUT,I2C1_SDA,?..."
|
|
textline " "
|
|
elif cpuis("MKL13Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTE0/CLKOUT32K,SPI1_MISO,LPUART1_TX,RTC_CLKOUT,CMP0_OUT,I2C1_SDA,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTE0,,UART1_TX,RTC_CLKOUT,CMP0_OUT,I2C1_SDA,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17*")||cpuis("MKL13*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTE1,SPI1_MOSI,LPUART1_RX,,SPI1_MISO,I2C1_SCL,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTE1,SPI1_MOSI,UART1_RX,,SPI1_MISO,I2C1_SCL,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4040++0x0F
|
|
line.long 0x00 "PORT_E_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFM4")||(cpu()=="MKL14Z32VFM4")||(cpu()=="MK14LN32VFM4")||(cpu()=="MKL14Z64VFM4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE1,PTE16,SPI0_PCS0,UART2_TX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")||cpuis("MKL17Z32V*")||cpuis("MKL17Z64V*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_DP1/ADC0_SE1,PTE16,SPI0_PCS0,UART2_TX,TPM_CLKIN0,,FXIO0_D0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_DP1/ADC0_SE1,PTE16,SPI0_PCS0,UART2_TX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFM4")||(cpu()=="MKL14Z32VFM4")||(cpu()=="MK14LN32VFM4")||(cpu()=="MKL14Z64VFM4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_se5a,PTE17,SPI0_SCK,UART2_RX,TPM_CLKIN1,,LPTMR0_ALT3,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_dm1/adc0_se5a,PTE17,SPI0_SCK,UART2_RX,TPM_CLKIN1,LPTMR0_ALT3,FXIO0_D1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_dm1/adc0_se5a,PTE17,SPI0_SCK,UART2_RX,TPM_CLKIN1,,LPTMR0_ALT3,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFM4")||(cpu()=="MKL14Z32VFM4")||(cpu()=="MK14LN32VFM4")||(cpu()=="MKL14Z64VFM4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE2,PTE18,SPI0_MOSI,,I2C0_SDA,SPI0_MISO,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_DP2/ADC0_SE2,PTE18,SPI0_MOSI,,I2C0_SDA,SPI0_MISO,FXIO0_D2,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_DP2/ADC0_SE2,PTE18,SPI0_MOSI,,I2C0_SDA,SPI0_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_E_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFM4")||(cpu()=="MKL14Z32VFM4")||(cpu()=="MK14LN32VFM4")||(cpu()=="MKL14Z64VFM4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_se6a,PTE19,SPI0_MISO,,I2C0_SCL,SPI0_MOSI,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_dm2/adc0_se6a,PTE19,SPI0_MISO,,I2C0_SCL,SPI0_MOSI,FXIO0_D3,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_dm2/adc0_se6a,PTE19,SPI0_MISO,,I2C0_SCL,SPI0_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4078++0x03
|
|
line.long 0x00 "PORT_E_PCR30,Pin Control Register 30"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFM4")||(cpu()=="MKL14Z32VFM4")||(cpu()=="MK14LN32VFM4")||(cpu()=="MKL14Z64VFM4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DAC0_OUT/ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,LPUART1_TX,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z32V*")||cpuis("MKL17Z64V*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,LPUART1_TX,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DAC0_OUT/ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x4080++0x07
|
|
line.long 0x00 "PORT_E_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 16 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_E_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 30. " GPWE30 ,Global pin 30 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x40A0++0x03
|
|
line.long 0x00 "PORT_E_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 30. " ISF30 ,Interrupt status flag 30 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF0 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MK?1*CAD*")
|
|
width 14.
|
|
tree "PORT_A"
|
|
tree "Pin Control Registers"
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "PORT_A_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH1,PTA0,,TPM0_CH5,,,,SWD_CLK"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH2,PTA1,UART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "TSI0_CH3,PTA2,UART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "TSI0_CH4,PTA3,I2C1_SCL,TPM0_CH0,,,,SWD_DIO"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "TSI0_CH5,PTA4,I2C1_SDA,TPM0_CH1,,,,Nmi_b"
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x48++0x0B
|
|
line.long 0x00 "PORT_A_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,UART1_RX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,,UART1_TX,TPM_CLKIN1,,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA20,,,,,,Reset_b"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x80++0x07
|
|
line.long 0x00 "PORT_A_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_A_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORT_A_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_B"
|
|
tree "Pin Control Registers"
|
|
group.long 0x1000++0x07
|
|
line.long 0x00 "PORT_B_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8/TSI0_CH0,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9/TSI0_CH6,PTB1,I2C0_SDA,TPM1_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x1080++0x03
|
|
line.long 0x00 "PORT_B_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x1084++0x03
|
|
hide.long 0x00 "PORT_B_GPCHR,Global Pin Control High Register"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "PORT_B_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_C"
|
|
tree "Pin Control Registers"
|
|
group.long 0x2004++0x1B
|
|
line.long 0x00 "PORT_C_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE15/TSI0_CH14,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_C_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE11/TSI0_CH15,PTC2,I2C1_SDA,,TPM0_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_C_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTC3/LLWU_P7,,UART1_RX,TPM0_CH2,CLKOUT,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_C_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTC4/LLWU_P8,SPI0_PCS0,UART1_TX,TPM0_CH3,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_C_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,,,CMP0_OUT,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_C_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "CMP0_IN0,PTC6/LLWU_P10,SPI0_MOSI,EXTRG_IN,,SPI0_MISO,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_C_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,SPI0_MISO,,,SPI0_MOSI,?..."
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x2080++0x03
|
|
line.long 0x00 "PORT_C_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x2084++0x03
|
|
hide.long 0x00 "PORT_C_GPCHR,Global Pin Control High Register"
|
|
group.long 0x20A0++0x03
|
|
line.long 0x00 "PORT_C_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_D"
|
|
tree "Pin Control Registers"
|
|
group.long 0x3010++0x0F
|
|
line.long 0x00 "PORT_D_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTD4/LLWU_P14,SPI1_PCS0,UART2_RX,TPM0_CH4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_D_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_se6b,PTD5,SPI1_SCK,UART2_TX,TPM0_CH5,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_D_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,UART0_RX,,SPI1_MISO,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_D_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTD7,SPI1_MISO,UART0_TX,,SPI1_MOSI,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x3080++0x03
|
|
line.long 0x00 "PORT_D_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x3084++0x03
|
|
hide.long 0x00 "PORT_D_GPCHR,Global Pin Control High Register"
|
|
group.long 0x30A0++0x03
|
|
line.long 0x00 "PORT_D_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_E"
|
|
tree "Pin Control Registers"
|
|
group.long 0x4000++0x07
|
|
line.long 0x00 "PORT_E_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTE0,,UART1_TX,RTC_CLKOUT,CMP0_OUT,I2C1_SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTE1,SPI1_MOSI,UART1_RX,,SPI1_MISO,I2C1_SCL,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4040++0x17
|
|
line.long 0x00 "PORT_E_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_DP1/ADC0_SE1,PTE16,SPI0_PCS0,UART2_TX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_dm1/adc0_se5a,PTE17,SPI0_SCK,UART2_RX,TPM_CLKIN1,,LPTMR0_ALT3,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_DP2/ADC0_SE2,PTE18,SPI0_MOSI,,I2C0_SDA,SPI0_MISO,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_E_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_dm2/adc0_se6a,PTE19,SPI0_MISO,,I2C0_SCL,SPI0_MOSI,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_E_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "ADC0_DP0/ADC0_SE0,PTE20,,TPM1_CH0,UART0_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_E_PCR21,Pin Control Register 21"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Adc0_dm0/adc0_se4a,PTE21,,TPM1_CH1,UART0_RX,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4074++0x07
|
|
line.long 0x00 "PORT_E_PCR29,Pin Control Register 29"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Cmp0_in5/adc0_se4b,PTE29,,TPM0_CH2,TPM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR30,Pin Control Register 30"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DAC0_OUT/ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x4080++0x07
|
|
line.long 0x00 "PORT_E_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_E_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 30. " GPWE30 ,Global pin 30 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 29. " GPWE29 ,Global pin 29 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 21. " GPWE21 ,Global pin 21 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x40A0++0x03
|
|
line.long 0x00 "PORT_E_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 30. " ISF30 ,Interrupt status flag 30 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 29. " ISF29 ,Interrupt status flag 29 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " ISF21 ,Interrupt status flag 21 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MK?1*VDA*")||cpuis("MK?1*CAL*")
|
|
width 14.
|
|
tree "PORT_A"
|
|
tree "Pin Control Registers"
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "PORT_A_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTA0,,TPM0_CH5,,,,SWD_CLK"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA1,LPUART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA2,UART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTA3,I2C1_SCL,TPM0_CH0,,,,SWD_DIO"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTA4,I2C1_SDA,TPM0_CH1,,,,Nmi_b"
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x48++0x0B
|
|
line.long 0x00 "PORT_A_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,LPUART1_RX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,,LPUART1_TX,TPM_CLKIN1,,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA20,,,,,,Reset_b"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x80++0x07
|
|
line.long 0x00 "PORT_A_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_A_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORT_A_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_B"
|
|
tree "Pin Control Registers"
|
|
group.long 0x1000++0x07
|
|
line.long 0x00 "PORT_B_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z32VMP4")||cpuis("MKL17Z64VMP4")||cpuis("MKL17Z32VLH4")||cpuis("MKL17Z64VLH4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,SPI1_MOSI,SPI1_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z128*")||cpuis("MKL17Z256V*")||cpuis("MKL17Z256CAL4R")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9,PTB1,I2C0_SDA,TPM1_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9,PTB1,I2C0_SDA,TPM1_CH1,SPI1_MISO,SPI1_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x1080++0x03
|
|
line.long 0x00 "PORT_B_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x1084++0x03
|
|
hide.long 0x00 "PORT_B_GPCHR,Global Pin Control High Register"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "PORT_B_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_C"
|
|
tree "Pin Control Registers"
|
|
group.long 0x2004++0x1B
|
|
line.long 0x00 "PORT_C_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE15,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_C_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE11,PTC2,I2C1_SDA,,TPM0_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_C_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTC3/LLWU_P7,SPI1_SCK,LPUART1_RX,TPM0_CH2,CLKOUT,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_C_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z32V*")||cpuis("MKL17Z64V*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTC4/LLWU_P8,SPI0_SS,LPUART1_TX,TPM0_CH3,SPI1_PCS0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTC4/LLWU_P8,SPI0_SS,LPUART1_TX,TPM0_CH3,I2S0_MCLK,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_C_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,,,CMP0_OUT,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_C_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "CMP0_IN0,PTC6/LLWU_P10,SPI0_MOSI,EXTRG_IN,,SPI0_MISO,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_C_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,SPI0_MISO,,,SPI0_MOSI,?..."
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x2080++0x03
|
|
line.long 0x00 "PORT_C_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x2084++0x03
|
|
hide.long 0x00 "PORT_C_GPCHR,Global Pin Control High Register"
|
|
group.long 0x20A0++0x03
|
|
line.long 0x00 "PORT_C_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_D"
|
|
tree "Pin Control Registers"
|
|
group.long 0x3010++0x0F
|
|
line.long 0x00 "PORT_D_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTD4/LLWU_P14,SPI1_PCS0,UART2_RX,TPM0_CH4,,FXIO0_D4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_D_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_se6b,PTD5,SPI1_SCK,UART2_TX,TPM0_CH5,,FXIO0_D5,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_D_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,LPUART0_RX,I2C1_SDA,SPI1_MISO,FXIO0_D6,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_D_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTD7,SPI1_MISO,LPUART0_TX,I2C1_SCL,SPI1_MOSI,FXIO0_D7,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x3080++0x03
|
|
line.long 0x00 "PORT_D_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x3084++0x03
|
|
hide.long 0x00 "PORT_D_GPCHR,Global Pin Control High Register"
|
|
group.long 0x30A0++0x03
|
|
line.long 0x00 "PORT_D_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_E"
|
|
tree "Pin Control Registers"
|
|
group.long 0x4000++0x07
|
|
line.long 0x00 "PORT_E_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTE0,SPI1_MISO,LPUART1_TX,RTC_CLKOUT,CMP0_OUT,I2C1_SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTE1,SPI1_MOSI,LPUART1_RX,,SPI1_MISO,I2C1_SCL,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4040++0x1F
|
|
line.long 0x00 "PORT_E_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_DP1/ADC0_SE1,PTE16,SPI0_PCS0,UART2_TX,TPM_CLKIN0,,FXIO0_D0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_dm1/adc0_se5a,PTE17,SPI0_SCK,UART2_RX,TPM_CLKIN1,LPTMR0_ALT3,FXIO0_D1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_DP2/ADC0_SE2,PTE18,SPI0_MOSI,,I2C0_SDA,SPI0_MISO,FXIO0_D2,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_E_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_dm2/adc0_se6a,PTE19,SPI0_MISO,,I2C0_SCL,SPI0_MOSI,FXIO0_D3,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_E_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "ADC0_DP0/ADC0_SE0,PTE20,,TPM1_CH0,LPUART0_TX,,FXIO0_D4,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_E_PCR21,Pin Control Register 21"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Adc0_dm0/adc0_se4a,PTE21,,TPM1_CH1,LPUART0_RX,,FXIO0_D5,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_E_PCR22,Pin Control Register 22"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "ADC0_DP3/ADC0_SE3,PTE22,,TPM2_CH0,UART2_TX,,FXIO0_D6,?..."
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_E_PCR23,Pin Control Register 23"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "Adc0_dm3/adc0_se7a,PTE23,,TPM2_CH1,UART2_RX,,FXIO0_D7,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4078++0x03
|
|
line.long 0x00 "PORT_E_PCR30,Pin Control Register 30"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z64V*")||cpuis("MKL17Z32V*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,LPUART1_TX,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DAC0_OUT/ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,LPUART1_TX,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x4080++0x07
|
|
line.long 0x00 "PORT_E_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_E_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 30. " GPWE30 ,Global pin 30 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 23. " GPWE23 ,Global pin 23 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 22. " GPWE22 ,Global pin 22 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 21. " GPWE21 ,Global pin 21 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x40A0++0x03
|
|
line.long 0x00 "PORT_E_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 30. " ISF30 ,Interrupt status flag 30 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 23. " ISF23 ,Interrupt status flag 23 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " ISF22 ,Interrupt status flag 22 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 21. " ISF21 ,Interrupt status flag 21 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MK?1*VFT*")
|
|
width 14.
|
|
tree "PORT_A"
|
|
tree "Pin Control Registers"
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "PORT_A_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFT4")||(cpu()=="MK14LN32VFT4")||(cpu()=="MKL14Z32VFT4")||(cpu()=="MKL14Z64VFT4")||cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTA0,,TPM0_CH5,,,,SWD_CLK"
|
|
textline " "
|
|
elif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTA1,LPUART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH1,PTA0,,TPM0_CH5,,,,SWD_CLK"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFT4")||(cpu()=="MK14LN32VFT4")||(cpu()=="MKL14Z32VFT4")||(cpu()=="MKL14Z64VFT4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA1,UART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA1,LPUART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH2,PTA1,UART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFT4")||(cpu()=="MK14LN32VFT4")||(cpu()=="MKL14Z32VFT4")||(cpu()=="MKL14Z64VFT4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA2,UART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA2,LPUART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "TSI0_CH3,PTA2,UART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFT4")||(cpu()=="MK14LN32VFT4")||(cpu()=="MKL14Z32VFT4")||(cpu()=="MKL14Z64VFT4")||cpuis("MKL17Z*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTA3,I2C1_SCL,TPM0_CH0,,,,SWD_DIO"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "TSI0_CH4,PTA3,I2C1_SCL,TPM0_CH0,,,,SWD_DIO"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFT4")||(cpu()=="MK14LN32VFT4")||(cpu()=="MKL14Z32VFT4")||(cpu()=="MKL14Z64VFT4")||cpuis("MKL17Z*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTA4,I2C1_SDA,TPM0_CH1,,,,Nmi_b"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "TSI0_CH5,PTA4,I2C1_SDA,TPM0_CH1,,,,Nmi_b"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x48++0x0B
|
|
line.long 0x00 "PORT_A_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,LPUART1_RX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,UART1_RX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,,LPUART1_TX,TPM_CLKIN1,,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,,UART1_TX,TPM_CLKIN1,,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA20,,,,,,Reset_b"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA20,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x80++0x07
|
|
line.long 0x00 "PORT_A_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_A_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORT_A_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_B"
|
|
tree "Pin Control Registers"
|
|
group.long 0x1000++0x0F
|
|
line.long 0x00 "PORT_B_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFT4")||(cpu()=="MK14LN32VFT4")||(cpu()=="MKL14Z32VFT4")||(cpu()=="MKL14Z64VFT4")||cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z32V*")||cpuis("MKL17Z64V*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,SPI1_MOSI,SPI1_MISO,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8/TSI0_CH0,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFT4")||(cpu()=="MK14LN32VFT4")||(cpu()=="MKL14Z32VFT4")||(cpu()=="MKL14Z64VFT4")||cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9,PTB1,I2C0_SDA,TPM1_CH1,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z64V*")||cpuis("MKL17Z32V*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9,PTB1,I2C0_SDA,TPM1_CH1,SPI1_MISO,SPI1_MOSI,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9/TSI0_CH6,PTB1,I2C0_SDA,TPM1_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFT4")||(cpu()=="MK14LN32VFT4")||(cpu()=="MKL14Z32VFT4")||(cpu()=="MKL14Z64VFT4")||cpuis("MKL17Z*")||cpuis("MKL13Z*")||cpuis("MKL17Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE12,PTB2,I2C0_SCL,TPM2_CH0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE12/TSI0_CH7,PTB2,I2C0_SCL,TPM2_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFT4")||(cpu()=="MK14LN32VFT4")||(cpu()=="MKL14Z32VFT4")||(cpu()=="MKL14Z64VFT4")||cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_SE13,PTB3,I2C0_SDA,TPM2_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_SE13/TSI0_CH8,PTB3,I2C0_SDA,TPM2_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x1040++0x07
|
|
line.long 0x00 "PORT_B_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFT4")||(cpu()=="MK14LN32VFT4")||(cpu()=="MKL14Z32VFT4")||(cpu()=="MKL14Z64VFT4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTB16,SPI1_MOSI,UART0_RX,TPM_CLKIN0,SPI1_MISO,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z*")||cpuis("MKL137Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTB16,SPI1_MOSI,LPUART0_RX,TPM_CLKIN0,SPI1_MISO,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH9,PTB16,SPI1_MOSI,UART0_RX,TPM_CLKIN0,SPI1_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFT4")||(cpu()=="MK14LN32VFT4")||(cpu()=="MKL14Z32VFT4")||(cpu()=="MKL14Z64VFT4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTB17,SPI1_MISO,UART0_TX,TPM_CLKIN1,SPI1_MOSI,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTB17,SPI1_MISO,LPUART0_TX,TPM_CLKIN1,SPI1_MOSI,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH10,PTB17,SPI1_MISO,UART0_TX,TPM_CLKIN1,SPI1_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x1080++0x07
|
|
line.long 0x00 "PORT_B_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_B_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "PORT_B_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_C"
|
|
tree "Pin Control Registers"
|
|
group.long 0x2000++0x1F
|
|
line.long 0x00 "PORT_C_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFT4")||(cpu()=="MK14LN32VFT4")||(cpu()=="MKL14Z32VFT4")||(cpu()=="MKL14Z64VFT4")||cpuis("MKL17Z64V*")||cpuis("MKL17Z32V*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE14,PTC0,,EXTRG_IN,,CMP0_OUT,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE14/TSI0_CH13,PTC0,,EXTRG_IN,Audiousb_sof_out,CMP0_OUT,I2S0_TXD0,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL16Z32VFT4")||(cpu()=="MKL16Z64VFT4")||(cpu()=="MKL16Z128VFT4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE14/TSI0_CH13,PTC0,,EXTRG_IN,,CMP0_OUT,I2S0_TXD0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE14/TSI0_CH13,PTC0,,EXTRG_IN,,CMP0_OUT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_C_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFT4")||(cpu()=="MK14LN32VFT4")||(cpu()=="MKL14Z32VFT4")||(cpu()=="MKL14Z64VFT4")||cpuis("MKL17Z64V*")||cpuis("MKL17Z32V*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE15,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE15,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,,I2S0_TXD0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE15/TSI0_CH14,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_C_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFT4")||(cpu()=="MK14LN32VFT4")||(cpu()=="MKL14Z32VFT4")||(cpu()=="MKL14Z64VFT4")||cpuis("MKL17Z64V*")||cpuis("MKL17Z32V*")||cpuis("MKL137Z*")||cpuis("MKL17Z64V*")||cpuis("MKL17Z32V*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE11,PTC2,I2C1_SDA,,TPM0_CH1,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE11,PTC2,I2C1_SDA,,TPM0_CH1,,I2S0_TX_FS,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL16Z32VFT4")||(cpu()=="MKL16Z64VFT4")||(cpu()=="MKL16Z128VFT4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE11/TSI0_CH15,PTC2,I2C1_SDA,,TPM0_CH1,,I2S0_TX_FS,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE11/TSI0_CH15,PTC2,I2C1_SDA,,TPM0_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_C_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL16Z32VFT4")||(cpu()=="MKL16Z64VFT4")||(cpu()=="MKL16Z128VFT4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTC3/LLWU_P7,,UART1_RX,TPM0_CH2,CLKOUT,I2S0_TX_BCLK,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z64V*")||cpuis("MKL17Z32V*")||cpuis("MKL137Z*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTC3/LLWU_P7,SPI1_SCK,LPUART1_RX,TPM0_CH2,CLKOUT,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTC3/LLWU_P7,SPI1_SCK,LPUART1_RX,TPM0_CH2,CLKOUT,I2S0_TX_BCLK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTC3/LLWU_P7,,UART1_RX,TPM0_CH2,CLKOUT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_C_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL16Z32VFT4")||(cpu()=="MKL16Z64VFT4")||(cpu()=="MKL16Z128VFT4")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTC4/LLWU_P8,SPI0_PCS0,UART1_TX,TPM0_CH3,I2S0_MCLK,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z64V*")||cpuis("MKL17Z32V*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTC4/LLWU_P8,SPI0_PCS0,UART1_TX,TPM0_CH3,SPI1_PCS0,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTC4/LLWU_P8,SPI0_SS,LPUART1_TX,TPM0_CH3,I2S0_MCLK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTC4/LLWU_P8,SPI0_PCS0,UART1_TX,TPM0_CH3,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_C_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL16Z32VFT4")||(cpu()=="MKL16Z64VFT4")||(cpu()=="MKL16Z128VFT4")||cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,I2S0_RXD0,,CMP0_OUT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,,,CMP0_OUT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_C_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL16Z32VFT4")||(cpu()=="MKL16Z64VFT4")||(cpu()=="MKL16Z128VFT4")||cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")||cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "CMP0_IN0,PTC6/LLWU_P10,SPI0_MOSI,EXTRG_IN,I2S0_RX_BCLK,SPI0_MISO,I2S0_MCLK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "CMP0_IN0,PTC6/LLWU_P10,SPI0_MOSI,EXTRG_IN,,SPI0_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_C_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL16Z32VFT4")||(cpu()=="MKL16Z64VFT4")||(cpu()=="MKL16Z128VFT4")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,SPI0_MISO,,I2S0_RX_FS,SPI0_MOSI,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,SPI0_MISO,Audiousb_sof_out,I2S0_RX_FS,SPI0_MOSI,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,SPI0_MISO,,,SPI0_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x2080++0x03
|
|
line.long 0x00 "PORT_C_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x2084++0x03
|
|
hide.long 0x00 "PORT_C_GPCHR,Global Pin Control High Register"
|
|
group.long 0x20A0++0x03
|
|
line.long 0x00 "PORT_C_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_D"
|
|
tree "Pin Control Registers"
|
|
group.long 0x3000++0x07
|
|
line.long 0x00 "PORT_D_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")||cpuis("MKL17Z64V*")||cpuis("MKL17Z32V*")||cpuis("MKL137Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTD0,SPI0_PCS0,,TPM0_CH0,,FXIO0_D0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTD0,SPI0_PCS0,,TPM0_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_D_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_se5b,PTD1,SPI0_SCK,,TPM0_CH1,,FXIO0_D1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_se5b,PTD1,SPI0_SCK,,TPM0_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x3008++0x03
|
|
line.long 0x00 "PORT_D_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTD2,SPI0_MOSI,UART2_RX,TPM0_CH2,SPI0_MISO,FXIO0_D2,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTD2,SPI0_MOSI,UART2_RX,TPM0_CH2,SPI0_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x300C++0x13
|
|
line.long 0x00 "PORT_D_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTD3,SPI0_MISO,UART2_TX,TPM0_CH3,SPI0_MOSI,FXIO0_D3,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTD3,SPI0_MISO,UART2_TX,TPM0_CH3,SPI0_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_D_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z64V*")||cpuis("MKL17Z32V*")||cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTD4/LLWU_P14,SPI1_PCS0,UART2_RX,TPM0_CH4,,FXIO0_D4,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTD4/LLWU_P14,SPI1_PCS0,UART2_RX,TPM0_CH4,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_D_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Adc0_se6b,PTD5,SPI1_SCK,UART2_TX,TPM0_CH5,,FXIO0_D5,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Adc0_se6b,PTD5,SPI1_SCK,UART2_TX,TPM0_CH5,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_D_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z64V*")||cpuis("MKL17Z32V*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,LPUART0_RX,I2C1_SDA,SPI1_MISO,FXIO0_D6,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,LPUART0_RX,,SPI1_MISO,FXIO0_D6,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,UART0_RX,,SPI1_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_D_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z64V*")||cpuis("MKL17Z32V*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTD7,SPI1_MISO,LPUART0_TX,I2C1_SCL,SPI1_MOSI,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTD7,SPI1_MISO,LPUART0_TX,,SPI1_MOSI,FXIO0_D7,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTD7,SPI1_MISO,UART0_TX,,SPI1_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x3080++0x03
|
|
line.long 0x00 "PORT_D_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE1 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x3084++0x03
|
|
hide.long 0x00 "PORT_D_GPCHR,Global Pin Control High Register"
|
|
group.long 0x30A0++0x03
|
|
line.long 0x00 "PORT_D_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_E"
|
|
tree "Pin Control Registers"
|
|
group.long 0x4040++0x17
|
|
line.long 0x00 "PORT_E_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFT4")||(cpu()=="MK14LN32VFT4")||(cpu()=="MKL14Z32VFT4")||(cpu()=="MKL14Z64VFT4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE1,PTE16,SPI0_PCS0,UART2_TX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE1,PTE16,SPI0_PCS0,UART2_TX,TPM_CLKIN0,,FXIO0_D0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_DP1/ADC0_SE1,PTE16,SPI0_PCS0,UART2_TX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFT4")||(cpu()=="MK14LN32VFT4")||(cpu()=="MKL14Z32VFT4")||(cpu()=="MKL14Z64VFT4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_se5a,PTE17,SPI0_SCK,UART2_RX,TPM_CLKIN1,,LPTMR0_ALT3,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_dm1/adc0_se5a,PTE17,SPI0_SCK,UART2_RX,TPM_CLKIN1,LPTMR0_ALT3,FXIO0_D1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_dm1/adc0_se5a,PTE17,SPI0_SCK,UART2_RX,TPM_CLKIN1,,LPTMR0_ALT3,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFT4")||(cpu()=="MK14LN32VFT4")||(cpu()=="MKL14Z32VFT4")||(cpu()=="MKL14Z64VFT4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE2,PTE18,SPI0_MOSI,,I2C0_SDA,SPI0_MISO,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_DP2/ADC0_SE2,PTE18,SPI0_MOSI,,I2C0_SDA,SPI0_MISO,FXIO0_D2,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_DP2/ADC0_SE2,PTE18,SPI0_MOSI,,I2C0_SDA,SPI0_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_E_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFT4")||(cpu()=="MK14LN32VFT4")||(cpu()=="MKL14Z32VFT4")||(cpu()=="MKL14Z64VFT4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_se6a,PTE19,SPI0_MISO,,I2C0_SCL,SPI0_MOSI,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_dm2/adc0_se6a,PTE19,SPI0_MISO,,I2C0_SCL,SPI0_MOSI,FXIO0_D3,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_dm2/adc0_se6a,PTE19,SPI0_MISO,,I2C0_SCL,SPI0_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_E_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFT4")||(cpu()=="MK14LN32VFT4")||(cpu()=="MKL14Z32VFT4")||(cpu()=="MKL14Z64VFT4")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "ADC0_SE0,PTE20,,TPM1_CH0,UART0_TX,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "ADC0_DP0/ADC0_SE0,PTE20,,TPM1_CH0,LPUART0_TX,,FXIO0_D4,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "ADC0_DP0/ADC0_SE0,PTE20,,TPM1_CH0,UART0_TX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_E_PCR21,Pin Control Register 21"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFT4")||(cpu()=="MK14LN32VFT4")||(cpu()=="MKL14Z32VFT4")||(cpu()=="MKL14Z64VFT4")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Adc0_se4a,PTE21,,TPM1_CH1,UART0_RX,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Adc0_dm0/adc0_se4a,PTE21,,TPM1_CH1,LPUART0_RX,,FXIO0_D5,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Adc0_dm0/adc0_se4a,PTE21,,TPM1_CH1,UART0_RX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4060++0x07
|
|
line.long 0x00 "PORT_E_PCR24,Pin Control Register 24"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTE24,,TPM0_CH0,,I2C0_SCL,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR25,Pin Control Register 25"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTE25,,TPM0_CH1,,I2C0_SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4074++0x07
|
|
line.long 0x00 "PORT_E_PCR29,Pin Control Register 29"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Cmp0_in5/adc0_se4b,PTE29,,TPM0_CH2,TPM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR30,Pin Control Register 30"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VFT4")||(cpu()=="MK14LN32VFT4")||(cpu()=="MKL14Z32VFT4")||(cpu()=="MKL14Z64VFT4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z64V*")||cpuis("MKL17Z32V*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,LPUART1_TX,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DAC0_OUT/ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,LPUART1_TX,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DAC0_OUT/ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x4080++0x07
|
|
line.long 0x00 "PORT_E_GPCLR,Global Pin Control Low Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_E_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 30. " GPWE30 ,Global pin 30 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 29. " GPWE29 ,Global pin 29 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 25. " GPWE25 ,Global pin 25 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 24. " GPWE24 ,Global pin 24 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 21. " GPWE21 ,Global pin 21 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x40A0++0x03
|
|
line.long 0x00 "PORT_E_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 30. " ISF30 ,Interrupt status flag 30 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 29. " ISF29 ,Interrupt status flag 29 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 25. " ISF25 ,Interrupt status flag 25 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 24. " ISF24 ,Interrupt status flag 24 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " ISF21 ,Interrupt status flag 21 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MK?1*VLH*")||cpuis("MKL?*VMP*")
|
|
width 14.
|
|
tree "PORT_A"
|
|
tree "Pin Control Registers"
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "PORT_A_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLH4")||(cpu()=="MK14LN32VLH4")||(cpu()=="MKL14Z32VLH4")||(cpu()=="MKL14Z64VLH4")||cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTA0,,TPM0_CH5,,,,SWD_CLK"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH1,PTA0,,TPM0_CH5,,,,SWD_CLK"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLH4")||(cpu()=="MK14LN32VLH4")||(cpu()=="MKL14Z32VLH4")||(cpu()=="MKL14Z64VLH4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA1,UART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA1,LPUART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH2,PTA1,UART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLH4")||(cpu()=="MK14LN32VLH4")||(cpu()=="MKL14Z32VLH4")||(cpu()=="MKL14Z64VLH4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA2,UART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA2,LPUART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "TSI0_CH3,PTA2,UART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLH4")||(cpu()=="MK14LN32VLH4")||(cpu()=="MKL14Z32VLH4")||(cpu()=="MKL14Z64VLH4")||cpuis("MKL17Z*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTA3,I2C1_SCL,TPM0_CH0,,,,SWD_DIO"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "TSI0_CH4,PTA3,I2C1_SCL,TPM0_CH0,,,,SWD_DIO"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLH4")||(cpu()=="MK14LN32VLH4")||(cpu()=="MKL14Z32VLH4")||(cpu()=="MKL14Z64VLH4")||cpuis("MKL17Z*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTA4,I2C1_SDA,TPM0_CH1,,,,Nmi_b"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "TSI0_CH5,PTA4,I2C1_SDA,TPM0_CH1,,,,Nmi_b"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_A_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL16Z256VLH4")||(cpu()=="MKL16Z256VMP4")||(cpu()=="MKL16Z32VLH4")||(cpu()=="MKL16Z64VLH4")||(cpu()=="MKL16Z128VLH4")||cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA5,,TPM0_CH2,,,I2S0_TX_BCLK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA5,,TPM0_CH2,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "PORT_A_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL16Z256VLH4")||(cpu()=="MKL16Z256VMP4")||(cpu()=="MKL16Z32VLH4")||(cpu()=="MKL16Z64VLH4")||(cpu()=="MKL16Z128VLH4")||cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTA12,,TPM1_CH0,,,I2S0_TXD0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTA12,,TPM1_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL16Z256VLH4")||(cpu()=="MKL16Z256VMP4")||(cpu()=="MKL16Z32VLH4")||(cpu()=="MKL16Z64VLH4")||(cpu()=="MKL16Z128VLH4")||cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA13,,TPM1_CH1,,,I2S0_TX_FS,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA13,,TPM1_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x48++0x0B
|
|
line.long 0x00 "PORT_A_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,LPUART1_RX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,UART1_RX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,,LPUART1_TX,TPM_CLKIN1,,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,,UART1_TX,TPM_CLKIN1,,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL16Z256VLH4")||(cpu()=="MKL16Z256VMP4")||(cpu()=="MKL16Z32VLH4")||(cpu()=="MKL16Z64VLH4")||(cpu()=="MKL16Z128VLH4")||cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA20,,,,,,Reset_b"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA20,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x80++0x07
|
|
line.long 0x00 "PORT_A_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 29. " GPWE13 ,Global pin 13 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 28. " GPWE12 ,Global pin 12 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_A_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORT_A_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " ISF13 ,Interrupt status flag 13 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " ISF12 ,Interrupt status flag 12 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_B"
|
|
tree "Pin Control Registers"
|
|
group.long 0x1000++0x0F
|
|
line.long 0x00 "PORT_B_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLH4")||(cpu()=="MK14LN32VLH4")||(cpu()=="MKL14Z32VLH4")||(cpu()=="MKL14Z64VLH4")||cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z64V*")||cpuis("MKL17Z32V*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,SPI1_MOSI,SPI1_MISO,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8/TSI0_CH0,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLH4")||(cpu()=="MK14LN32VLH4")||(cpu()=="MKL14Z32VLH4")||(cpu()=="MKL14Z64VLH4")||cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9,PTB1,I2C0_SDA,TPM1_CH1,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z32V*")||cpuis("MKL17Z64V*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9,PTB1,I2C0_SDA,TPM1_CH1,SPI1_MISO,SPI1_MOSI,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9/TSI0_CH6,PTB1,I2C0_SDA,TPM1_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLH4")||(cpu()=="MK14LN32VLH4")||(cpu()=="MKL14Z32VLH4")||(cpu()=="MKL14Z64VLH4")||cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE12,PTB2,I2C0_SCL,TPM2_CH0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE12/TSI0_CH7,PTB2,I2C0_SCL,TPM2_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLH4")||(cpu()=="MK14LN32VLH4")||(cpu()=="MKL14Z32VLH4")||(cpu()=="MKL14Z64VLH4")||cpuis("MKL17Z*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_SE13,PTB3,I2C0_SDA,TPM2_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_SE13/TSI0_CH8,PTB3,I2C0_SDA,TPM2_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x1040++0x0F
|
|
line.long 0x00 "PORT_B_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLH4")||(cpu()=="MK14LN32VLH4")||(cpu()=="MKL14Z32VLH4")||(cpu()=="MKL14Z64VLH4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTB16,SPI1_MOSI,UART0_RX,TPM_CLKIN0,SPI1_MISO,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTB16,SPI1_MOSI,LPUART0_RX,TPM_CLKIN0,SPI1_MISO,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH9,PTB16,SPI1_MOSI,UART0_RX,TPM_CLKIN0,SPI1_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLH4")||(cpu()=="MK14LN32VLH4")||(cpu()=="MKL14Z32VLH4")||(cpu()=="MKL14Z64VLH4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTB17,SPI1_MISO,UART0_TX,TPM_CLKIN1,SPI1_MOSI,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTB17,SPI1_MISO,LPUART0_TX,TPM_CLKIN1,SPI1_MOSI,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH10,PTB17,SPI1_MISO,UART0_TX,TPM_CLKIN1,SPI1_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLH4")||(cpu()=="MK14LN32VLH4")||(cpu()=="MKL14Z32VLH4")||(cpu()=="MKL14Z64VLH4")||cpuis("MKL17Z64V*")||cpuis("MKL17Z32V*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTB18,,TPM2_CH0,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL16Z256VLH4")||(cpu()=="MKL16Z256VMP4")||(cpu()=="MKL16Z32VLH4")||(cpu()=="MKL16Z64VLH4")||(cpu()=="MKL16Z128VLH4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "TSI0_CH11,PTB18,,TPM2_CH0,I2S0_TX_BCLK,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTB18,,TPM2_CH0,I2S0_TX_BCLK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "TSI0_CH11,PTB18,,TPM2_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLH4")||(cpu()=="MK14LN32VLH4")||(cpu()=="MKL14Z32VLH4")||(cpu()=="MKL14Z64VLH4")||cpuis("MKL17Z64V*")||cpuis("MKL17Z32V*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTB19,,TPM2_CH1,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTB19,,TPM2_CH1,I2S0_TX_FS,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL16Z256VLH4")||(cpu()=="MKL16Z256VMP4")||(cpu()=="MKL16Z32VLH4")||(cpu()=="MKL16Z64VLH4")||(cpu()=="MKL16Z128VLH4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "TSI0_CH12,PTB19,,TPM2_CH1,I2S0_TX_FS,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "TSI0_CH12,PTB19,,TPM2_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x1080++0x07
|
|
line.long 0x00 "PORT_B_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_B_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "PORT_B_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_C"
|
|
tree "Pin Control Registers"
|
|
group.long 0x2000++0x2F
|
|
line.long 0x00 "PORT_C_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLH4")||(cpu()=="MK14LN32VLH4")||(cpu()=="MKL14Z32VLH4")||(cpu()=="MKL14Z64VLH4")||cpuis("MKL17Z64V*")||cpuis("MKL17Z32V*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE14,PTC0,,EXTRG_IN,,CMP0_OUT,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE14,PTC0,,EXTRG_IN,Audiousb_sof_out,CMP0_OUT,I2S0_TXD0,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL16Z256VLH4")||(cpu()=="MKL16Z256VMP4")||(cpu()=="MKL16Z32VLH4")||(cpu()=="MKL16Z64VLH4")||(cpu()=="MKL16Z128VLH4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE14/TSI0_CH13,PTC0,,EXTRG_IN,,CMP0_OUT,I2S0_TXD0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE14/TSI0_CH13,PTC0,,EXTRG_IN,,CMP0_OUT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_C_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLH4")||(cpu()=="MK14LN32VLH4")||(cpu()=="MKL14Z32VLH4")||(cpu()=="MKL14Z64VLH4")||cpuis("MKL13Z*")||cpuis("MKL17Z32V*")||cpuis("MKL17Z64V*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE15,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE15,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,,I2S0_TXD0,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL16Z256VLH4")||(cpu()=="MKL16Z256VMP4")||(cpu()=="MKL16Z32VLH4")||(cpu()=="MKL16Z64VLH4")||(cpu()=="MKL16Z128VLH4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE15/TSI0_CH14,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,,I2S0_TXD0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE15/TSI0_CH14,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_C_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLH4")||(cpu()=="MK14LN32VLH4")||(cpu()=="MKL14Z32VLH4")||(cpu()=="MKL14Z64VLH4")||cpuis("MKL17Z64V*")||cpuis("MKL17Z32V*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE11,PTC2,I2C1_SDA,,TPM0_CH1,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE11,PTC2,I2C1_SDA,,TPM0_CH1,,I2S0_TX_FS,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL16Z256VLH4")||(cpu()=="MKL16Z256VMP4")||(cpu()=="MKL16Z32VLH4")||(cpu()=="MKL16Z64VLH4")||(cpu()=="MKL16Z128VLH4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE11/TSI0_CH15,PTC2,I2C1_SDA,,TPM0_CH1,,I2S0_TX_FS,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE11/TSI0_CH15,PTC2,I2C1_SDA,,TPM0_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_C_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL16Z256VLH4")||(cpu()=="MKL16Z256VMP4")||(cpu()=="MKL16Z32VLH4")||(cpu()=="MKL16Z64VLH4")||(cpu()=="MKL16Z128VLH4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTC3/LLWU_P7,,UART1_RX,TPM0_CH2,CLKOUT,I2S0_TX_BCLK,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z64V*")||cpuis("MKL17Z32V*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTC3/LLWU_P7,SPI1_SCK,LPUART1_RX,TPM0_CH2,CLKOUT,,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTC3/LLWU_P7,SPI1_SCK,LPUART1_RX,TPM0_CH2,CLKOUT,I2S0_TX_BCLK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTC3/LLWU_P7,,UART1_RX,TPM0_CH2,CLKOUT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_C_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL16Z256VLH4")||(cpu()=="MKL16Z256VMP4")||(cpu()=="MKL16Z32VLH4")||(cpu()=="MKL16Z64VLH4")||(cpu()=="MKL16Z128VLH4")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTC4/LLWU_P8,SPI0_PCS0,UART1_TX,TPM0_CH3,I2S0_MCLK,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z64V*")||cpuis("MKL17Z32V*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTC4/LLWU_P8,SPI0_PCS0,LPUART1_TX,TPM0_CH3,SPI1_PCS0,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z128VMP4")||cpuis("MKL17Z256V*")||cpuis("MKL17Z128V*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTC4/LLWU_P8,SPI0_SS,LPUART1_TX,TPM0_CH3,I2S0_MCLK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTC4/LLWU_P8,SPI0_PCS0,UART1_TX,TPM0_CH3,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_C_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL16Z256VLH4")||(cpu()=="MKL16Z256VMP4")||(cpu()=="MKL16Z32VLH4")||(cpu()=="MKL16Z64VLH4")||(cpu()=="MKL16Z128VLH4")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,I2S0_RXD0,,CMP0_OUT,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z64V*")||cpuis("MKL17Z32V*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,,,CMP0_OUT,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,I2S0_RXD0,,CMP0_OUT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,,,CMP0_OUT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_C_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL16Z256VLH4")||(cpu()=="MKL16Z256VMP4")||(cpu()=="MKL16Z32VLH4")||(cpu()=="MKL16Z64VLH4")||(cpu()=="MKL16Z128VLH4")||cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "CMP0_IN0,PTC6/LLWU_P10,SPI0_MOSI,EXTRG_IN,I2S0_RX_BCLK,SPI0_MISO,I2S0_MCLK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "CMP0_IN0,PTC6/LLWU_P10,SPI0_MOSI,EXTRG_IN,,SPI0_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_C_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL16Z256VLH4")||(cpu()=="MKL16Z256VMP4")||(cpu()=="MKL16Z32VLH4")||(cpu()=="MKL16Z64VLH4")||(cpu()=="MKL16Z128VLH4")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,SPI0_MISO,,I2S0_RX_FS,SPI0_MOSI,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,SPI0_MISO,Audiousb_sof_out,I2S0_RX_FS,SPI0_MOSI,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,SPI0_MISO,,,SPI0_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x20 "PORT_C_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x20 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL16Z256VLH4")||(cpu()=="MKL16Z256VMP4")||(cpu()=="MKL16Z32VLH4")||(cpu()=="MKL16Z64VLH4")||(cpu()=="MKL16Z128VLH4")||cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "CMP0_IN2,PTC8,I2C0_SCL,TPM0_CH4,I2S0_MCLK,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z64V*")||cpuis("MKL17Z32V*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "CMP0_IN2,PTC8,I2C0_SCL,TPM0_CH4,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "CMP0_IN2,PTC8,I2C0_SCL,TPM0_CH4,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x20 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x20 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x20 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x24 "PORT_C_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x24 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL16Z256VLH4")||(cpu()=="MKL16Z256VMP4")||(cpu()=="MKL16Z32VLH4")||(cpu()=="MKL16Z64VLH4")||(cpu()=="MKL16Z128VLH4")||cpuis("MKL17Z*")
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "CMP0_IN3,PTC9,I2C0_SDA,TPM0_CH5,I2S0_RX_BCLK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "CMP0_IN3,PTC9,I2C0_SDA,TPM0_CH5,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x24 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x24 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x24 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x28 "PORT_C_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x28 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x28 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL16Z256VLH4")||(cpu()=="MKL16Z256VMP4")||(cpu()=="MKL16Z32VLH4")||(cpu()=="MKL16Z64VLH4")||(cpu()=="MKL16Z128VLH4")||cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x28 8.--10. " MUX ,Pin mux control" "Disabled,PTC10,I2C1_SCL,,I2S0_RX_FS,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x28 8.--10. " MUX ,Pin mux control" "Disabled,PTC10,I2C1_SCL,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x28 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x28 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x28 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x2C "PORT_C_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x2C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL16Z256VLH4")||(cpu()=="MKL16Z256VMP4")||(cpu()=="MKL16Z32VLH4")||(cpu()=="MKL16Z64VLH4")||(cpu()=="MKL16Z128VLH4")||cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" "Disabled,PTC11,I2C1_SDA,,I2S0_RXD0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" "Disabled,PTC11,I2C1_SDA,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x2C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x2C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x2C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x2080++0x03
|
|
line.long 0x00 "PORT_C_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x2084++0x03
|
|
hide.long 0x00 "PORT_C_GPCHR,Global Pin Control High Register"
|
|
group.long 0x20A0++0x03
|
|
line.long 0x00 "PORT_C_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_D"
|
|
tree "Pin Control Registers"
|
|
group.long 0x3000++0x1F
|
|
line.long 0x00 "PORT_D_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")||cpuis("MKL17Z64V*")||cpuis("MKL17Z32V*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTD0,SPI0_PCS0,,TPM0_CH0,,FXIO0_D0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTD0,SPI0_PCS0,,TPM0_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_D_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_se5b,PTD1,SPI0_SCK,,TPM0_CH1,,FXIO0_D1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_se5b,PTD1,SPI0_SCK,,TPM0_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_D_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTD2,SPI0_MOSI,UART2_RX,TPM0_CH2,SPI0_MISO,FXIO0_D2,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTD2,SPI0_MOSI,UART2_RX,TPM0_CH2,SPI0_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_D_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTD3,SPI0_MISO,UART2_TX,TPM0_CH3,SPI0_MOSI,FXIO0_D3,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTD3,SPI0_MISO,UART2_TX,TPM0_CH3,SPI0_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_D_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z64V*")||cpuis("MKL17Z32V*")||cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTD4/LLWU_P14,SPI1_PCS0,UART2_RX,TPM0_CH4,,FXIO0_D4,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTD4/LLWU_P14,SPI1_PCS0,UART2_RX,TPM0_CH4,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_D_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Adc0_se6b,PTD5,SPI1_SCK,UART2_TX,TPM0_CH5,,FXIO0_D5,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Adc0_se6b,PTD5,SPI1_SCK,UART2_TX,TPM0_CH5,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_D_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z64V*")||cpuis("MKL17Z32V*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,LPUART0_RX,I2C1_SDA,SPI1_MISO,FXIO0_D6,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,LPUART0_RX,,SPI1_MISO,FXIO0_D6,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,UART0_RX,,SPI1_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_D_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z64V*")||cpuis("MKL17Z32V*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "Disabled,PTD7,SPI1_MISO,LPUART0_TX,I2C1_SCL,SPI1_MOSI,FXIO0_D7,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "Disabled,PTD7,SPI1_MISO,LPUART0_TX,,SPI1_MOSI,FXIO0_D7,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "Disabled,PTD7,SPI1_MISO,UART0_TX,,SPI1_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x3080++0x03
|
|
line.long 0x00 "PORT_D_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x3084++0x03
|
|
hide.long 0x00 "PORT_D_GPCHR,Global Pin Control High Register"
|
|
group.long 0x30A0++0x03
|
|
line.long 0x00 "PORT_D_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_E"
|
|
tree "Pin Control Registers"
|
|
group.long 0x4000++0x07
|
|
line.long 0x00 "PORT_E_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTE0,SPI1_MISO,LPUART1_TX,RTC_CLKOUT,CMP0_OUT,I2C1_SDA,?..."
|
|
textline " "
|
|
elif cpuis("MKL13Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTE0/CLKOUT32K,SPI1_MISO,LPUART1_TX,RTC_CLKOUT,CMP0_OUT,I2C1_SDA,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTE0,,UART1_TX,RTC_CLKOUT,CMP0_OUT,I2C1_SDA,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTE1,SPI1_MOSI,LPUART1_RX,,SPI1_MISO,I2C1_SCL,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTE1,SPI1_MOSI,UART1_RX,,SPI1_MISO,I2C1_SCL,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4040++0x27
|
|
line.long 0x00 "PORT_E_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLH4")||(cpu()=="MK14LN32VLH4")||(cpu()=="MKL14Z32VLH4")||(cpu()=="MKL14Z64VLH4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE1,PTE16,SPI0_PCS0,UART2_TX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_DP1/ADC0_SE1,PTE16,SPI0_PCS0,UART2_TX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_DP1/ADC0_SE1,PTE16,SPI0_PCS0,UART2_TX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLH4")||(cpu()=="MK14LN32VLH4")||(cpu()=="MKL14Z32VLH4")||(cpu()=="MKL14Z64VLH4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_se5a,PTE17,SPI0_SCK,UART2_RX,TPM_CLKIN1,,LPTMR0_ALT3,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_se5a,PTE17,SPI0_SCK,UART2_RX,TPM_CLKIN1,LPTMR0_ALT3,FXIO0_D1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_dm1/adc0_se5a,PTE17,SPI0_SCK,UART2_RX,TPM_CLKIN1,,LPTMR0_ALT3,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLH4")||(cpu()=="MK14LN32VLH4")||(cpu()=="MKL14Z32VLH4")||(cpu()=="MKL14Z64VLH4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE2,PTE18,SPI0_MOSI,,I2C0_SDA,SPI0_MISO,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE2,PTE18,SPI0_MOSI,,I2C0_SDA,SPI0_MISO,FXIO0_D2,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_DP2/ADC0_SE2,PTE18,SPI0_MOSI,,I2C0_SDA,SPI0_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_E_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLH4")||(cpu()=="MK14LN32VLH4")||(cpu()=="MKL14Z32VLH4")||(cpu()=="MKL14Z64VLH4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_se6a,PTE19,SPI0_MISO,,I2C0_SCL,SPI0_MOSI,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_se6a,PTE19,SPI0_MISO,,I2C0_SCL,SPI0_MOSI,FXIO0_D3,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_dm2/adc0_se6a,PTE19,SPI0_MISO,,I2C0_SCL,SPI0_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_E_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLH4")||(cpu()=="MK14LN32VLH4")||(cpu()=="MKL14Z32VLH4")||(cpu()=="MKL14Z64VLH4")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "ADC0_SE0,PTE20,,TPM1_CH0,UART0_TX,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "ADC0_SE0,PTE20,,TPM1_CH0,LPUART0_TX,,FXIO0_D4,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "ADC0_DP0/ADC0_SE0,PTE20,,TPM1_CH0,UART0_TX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_E_PCR21,Pin Control Register 21"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLH4")||(cpu()=="MK14LN32VLH4")||(cpu()=="MKL14Z32VLH4")||(cpu()=="MKL14Z64VLH4")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Adc0_se4a,PTE21,,TPM1_CH1,UART0_RX,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Adc0_se4a,PTE21,,TPM1_CH1,LPUART0_RX,,FXIO0_D5,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Adc0_dm0/adc0_se4a,PTE21,,TPM1_CH1,UART0_RX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_E_PCR22,Pin Control Register 22"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLH4")||(cpu()=="MK14LN32VLH4")||(cpu()=="MKL14Z32VLH4")||(cpu()=="MKL14Z64VLH4")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "ADC0_SE3,PTE22,,TPM2_CH0,UART2_TX,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "ADC0_SE3,PTE22,,TPM2_CH0,UART2_TX,,FXIO0_D6,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "ADC0_DP3/ADC0_SE3,PTE22,,TPM2_CH0,UART2_TX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_E_PCR23,Pin Control Register 23"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLH4")||(cpu()=="MK14LN32VLH4")||(cpu()=="MKL14Z32VLH4")||(cpu()=="MKL14Z64VLH4")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "Adc0_se7a,PTE23,,TPM2_CH1,UART2_RX,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "Adc0_se7a,PTE23,,TPM2_CH1,UART2_RX,,FXIO0_D7,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "Adc0_dm3/adc0_se7a,PTE23,,TPM2_CH1,UART2_RX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x20 "PORT_E_PCR24,Pin Control Register 24"
|
|
eventfld.long 0x20 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "Disabled,PTE24,,TPM0_CH0,,I2C0_SCL,?..."
|
|
textline " "
|
|
bitfld.long 0x20 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x20 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x20 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x24 "PORT_E_PCR25,Pin Control Register 25"
|
|
eventfld.long 0x24 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "Disabled,PTE25,,TPM0_CH1,,I2C0_SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x24 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x24 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x24 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4074++0x0B
|
|
line.long 0x00 "PORT_E_PCR29,Pin Control Register 29"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Cmp0_in5/adc0_se4b,PTE29,,TPM0_CH2,TPM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR30,Pin Control Register 30"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLH4")||(cpu()=="MK14LN32VLH4")||(cpu()=="MKL14Z32VLH4")||(cpu()=="MKL14Z64VLH4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z64V*")||cpuis("MKL17Z32V*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,LPUART1_TX,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z128V*")||cpuis("MKL17Z256V*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DAC0_OUT/ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,LPUART1_TX,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DAC0_OUT/ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR31,Pin Control Register 31"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTE31,,TPM0_CH4,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x4080++0x07
|
|
line.long 0x00 "PORT_E_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_E_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 31. " GPWE31 ,Global pin 31 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 30. " GPWE30 ,Global pin 30 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 29. " GPWE29 ,Global pin 29 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 25. " GPWE25 ,Global pin 25 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 24. " GPWE24 ,Global pin 24 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 23. " GPWE23 ,Global pin 23 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 22. " GPWE22 ,Global pin 22 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 21. " GPWE21 ,Global pin 21 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x40A0++0x03
|
|
line.long 0x00 "PORT_E_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 31. " ISF31 ,Interrupt status flag 31 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " ISF30 ,Interrupt status flag 30 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 29. " ISF29 ,Interrupt status flag 29 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " ISF25 ,Interrupt status flag 25 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " ISF24 ,Interrupt status flag 24 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 23. " ISF23 ,Interrupt status flag 23 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 22. " ISF22 ,Interrupt status flag 22 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " ISF21 ,Interrupt status flag 21 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MK?1*VLK*")
|
|
width 14.
|
|
tree "PORT_A"
|
|
tree "Pin Control Registers"
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "PORT_A_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLK4")||(cpu()=="MK14LN32VLK4")||(cpu()=="MKL14Z32VLK4")||(cpu()=="MKL14Z64VLK4")||cpuis("MKL13Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTA0,,TPM0_CH5,,,,SWD_CLK"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH1,PTA0,,TPM0_CH5,,,,SWD_CLK"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLK4")||(cpu()=="MK14LN32VLK4")||(cpu()=="MKL14Z32VLK4")||(cpu()=="MKL14Z64VLK4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA1,UART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
elif cpuis("MKL13Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA1,LPUART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH2,PTA1,UART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLK4")||(cpu()=="MK14LN32VLK4")||(cpu()=="MKL14Z32VLK4")||(cpu()=="MKL14Z64VLK4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA2,UART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "TSI0_CH3,PTA2,UART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLK4")||(cpu()=="MK14LN32VLK4")||(cpu()=="MKL14Z32VLK4")||(cpu()=="MKL14Z64VLK4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTA3,I2C1_SCL,TPM0_CH0,,,,SWD_DIO"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "TSI0_CH4,PTA3,I2C1_SCL,TPM0_CH0,,,,SWD_DIO"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLK4")||(cpu()=="MK14LN32VLK4")||(cpu()=="MKL14Z32VLK4")||(cpu()=="MKL14Z64VLK4")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTA4,I2C1_SDA,TPM0_CH1,,,,Nmi_b"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "TSI0_CH5,PTA4,I2C1_SDA,TPM0_CH1,,,,Nmi_b"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_A_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA5,,TPM0_CH2,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x30++0x23
|
|
line.long 0x00 "PORT_A_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTA12,,TPM1_CH0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA13,,TPM1_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR14,Pin Control Register 14"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA14,SPI0_PCS0,LAUART0_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR15,Pin Control Register 15"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTA15,SPI0_SCK,LPUART0_RX,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTA16,SPI0_MOSI,,,SPI0_MISO,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_A_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA17,SPI0_MISO,,,SPI0_MOSI,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_A_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL13Z*")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,LPUART1_RX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,UART1_RX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_A_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,,LPUART1_TX,TPM_CLKIN1,,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,,UART1_TX,TPM_CLKIN1,,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x20 "PORT_A_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x20 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "Disabled,PTA20,,,,,,Reset_b"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "Disabled,PTA20,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x20 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x20 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x20 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x80++0x07
|
|
line.long 0x00 "PORT_A_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 31. " GPWE15 ,Global pin 15 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 30. " GPWE14 ,Global pin 14 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 29. " GPWE13 ,Global pin 13 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GPWE12 ,Global pin 12 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_A_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORT_A_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 15. " ISF15 ,Interrupt status flag 15 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 14. " ISF14 ,Interrupt status flag 14 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " ISF13 ,Interrupt status flag 13 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " ISF12 ,Interrupt status flag 12 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_B"
|
|
tree "Pin Control Registers"
|
|
group.long 0x1000++0x0F
|
|
line.long 0x00 "PORT_B_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLK4")||(cpu()=="MK14LN32VLK4")||(cpu()=="MKL14Z32VLK4")||(cpu()=="MKL14Z64VLK4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,?..."
|
|
textline " "
|
|
elif cpuis("MKL13Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,SPI1_MOSI,SPI1_MISO,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8/TSI0_CH0,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLK4")||(cpu()=="MK14LN32VLK4")||(cpu()=="MKL14Z32VLK4")||(cpu()=="MKL14Z64VLK4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9,PTB1,I2C0_SDA,TPM1_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9/TSI0_CH6,PTB1,I2C0_SDA,TPM1_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLK4")||(cpu()=="MK14LN32VLK4")||(cpu()=="MKL14Z32VLK4")||(cpu()=="MKL14Z64VLK4")||cpuis("MKL13Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE12,PTB2,I2C0_SCL,TPM2_CH0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE12/TSI0_CH7,PTB2,I2C0_SCL,TPM2_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLK4")||(cpu()=="MK14LN32VLK4")||(cpu()=="MKL14Z32VLK4")||(cpu()=="MKL14Z64VLK4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_SE13,PTB3,I2C0_SDA,TPM2_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_SE13/TSI0_CH8,PTB3,I2C0_SDA,TPM2_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x1020++0x0F
|
|
line.long 0x00 "PORT_B_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DISABLED,PTB8,,EXTRG_IN,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DISABLED,PTB9,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "DISABLED,PTB10,SPI1_PCS0,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "DISABLED,PTB11,SPI1_SCK,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x1040++0x0F
|
|
line.long 0x00 "PORT_B_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLK4")||(cpu()=="MK14LN32VLK4")||(cpu()=="MKL14Z32VLK4")||(cpu()=="MKL14Z64VLK4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DISABLED,PTB16,SPI1_MOSI,UART0_RX,TPM_CLKIN0,SPI1_MISO,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTB16,SPI1_MOSI,LPUART0_RX,TPM_CLKIN0,SPI1_MISO,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH9,PTB16,SPI1_MOSI,UART0_RX,TPM_CLKIN0,SPI1_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLK4")||(cpu()=="MK14LN32VLK4")||(cpu()=="MKL14Z32VLK4")||(cpu()=="MKL14Z64VLK4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DISABLED,PTB17,SPI1_MISO,UART0_TX,TPM_CLKIN1,SPI1_MOSI,?..."
|
|
textline " "
|
|
elif cpuis("MKL17Z*")||cpuis("MKL13Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTB17,SPI1_MISO,LPUART0_TX,TPM_CLKIN1,SPI1_MOSI,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH10,PTB17,SPI1_MISO,UART0_TX,TPM_CLKIN1,SPI1_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLK4")||(cpu()=="MK14LN32VLK4")||(cpu()=="MKL14Z32VLK4")||(cpu()=="MKL14Z64VLK4")||cpuis("MKL13Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "DISABLED,PTB18,,TPM2_CH0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "TSI0_CH11,PTB18,,TPM2_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR19,Pin Control Register 19"
|
|
bitfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLK4")||(cpu()=="MK14LN32VLK4")||(cpu()=="MKL14Z32VLK4")||(cpu()=="MKL14Z64VLK4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "DISABLED,PTB19,,TPM2_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "TSI0_CH12,PTB19,,TPM2_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x1080++0x07
|
|
line.long 0x00 "PORT_B_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_B_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "PORT_B_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_C"
|
|
tree "Pin Control Registers"
|
|
group.long 0x2000++0x37
|
|
line.long 0x00 "PORT_C_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLK4")||(cpu()=="MK14LN32VLK4")||(cpu()=="MKL14Z32VLK4")||(cpu()=="MKL14Z64VLK4")||cpuis("MKL13Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE14,PTC0,,EXTRG_IN,,CMP0_OUT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE14/TSI0_CH13,PTC0,,EXTRG_IN,,CMP0_OUT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_C_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLK4")||(cpu()=="MK14LN32VLK4")||(cpu()=="MKL14Z32VLK4")||(cpu()=="MKL14Z64VLK4")||cpuis("MKL13Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE15,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE15/TSI0_CH14,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_C_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLK4")||(cpu()=="MK14LN32VLK4")||(cpu()=="MKL14Z32VLK4")||(cpu()=="MKL14Z64VLK4")||cpuis("MKL13Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE11,PTC2,I2C1_SDA,,TPM0_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE11/TSI0_CH15,PTC2,I2C1_SDA,,TPM0_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_C_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL17Z32VFM4")||cpuis("MKL17Z64VFM4")||cpuis("MKL13Z*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTC3/LLWU_P7,SPI1_SCK,LPUART1_RX,TPM0_CH2,CLKOUT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "DISABLED,PTC3/LLWU_P7,,UART1_RX,TPM0_CH2,CLKOUT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_C_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL13Z*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTC4/LLWU_P8,SPI0_PCS0,LPUART1_TX,TPM0_CH3,SPI1_PCS0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "DISABLED,PTC4/LLWU_P8,SPI0_PCS0,UART1_TX,TPM0_CH3,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_C_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "DISABLED,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,,,CMP0_OUT,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_C_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "CMP0_IN0,PTC6/LLWU_P10,SPI0_MOSI,EXTRG_IN,,SPI0_MISO,?..."
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_C_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,SPI0_MISO,,,SPI0_MOSI,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x20 "PORT_C_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x20 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "CMP0_IN2,PTC8,I2C0_SCL,TPM0_CH4,?..."
|
|
textline " "
|
|
bitfld.long 0x20 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x20 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x20 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x24 "PORT_C_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x24 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "CMP0_IN3,PTC9,I2C0_SDA,TPM0_CH5,?..."
|
|
textline " "
|
|
bitfld.long 0x24 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x24 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x24 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x28 "PORT_C_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x28 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x28 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x28 8.--10. " MUX ,Pin mux control" "DISABLED,PTC10,I2C1_SCL,?..."
|
|
textline " "
|
|
bitfld.long 0x28 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x28 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x28 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x2C "PORT_C_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x2C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" "DISABLED,PTC11,I2C1_SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x2C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x2C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x2C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x30 "PORT_C_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x30 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x30 8.--10. " MUX ,Pin mux control" "DISABLED,PTC12,,,TPM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x30 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x30 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x30 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x30 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x30 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x34 "PORT_A_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x34 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x34 8.--10. " MUX ,Pin mux control" "DISABLED,PTC13,,,TPM_CLKIN1,?..."
|
|
textline " "
|
|
bitfld.long 0x34 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x34 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x34 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x34 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x34 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x2040++0x07
|
|
line.long 0x00 "PORT_A_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DISABLED,PTC16,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DISABLED,PTC17,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x2080++0x07
|
|
line.long 0x00 "PORT_C_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 29. " GPWE13 ,Global pin 13 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 28. " GPWE12 ,Global pin 12 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_C_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x20A0++0x03
|
|
line.long 0x00 "PORT_C_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " ISF13 ,Interrupt status flag 13 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 12. " ISF12 ,Interrupt status flag 12 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_D"
|
|
tree "Pin Control Registers"
|
|
group.long 0x3000++0x1F
|
|
line.long 0x00 "PORT_D_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL13Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTD0,SPI0_PCS0,,TPM0_CH0,,FXIO0_D0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DISABLED,PTD0,SPI0_PCS0,,TPM0_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_D_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL13Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_se5b,PTD1,SPI0_SCK,,TPM0_CH1,,FXIO0_D1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_se5b,PTD1,SPI0_SCK,,TPM0_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_D_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL13Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTD2,SPI0_MOSI,UART2_RX,TPM0_CH2,SPI0_MISO,FXIO0_D2,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "DISABLED,PTD2,SPI0_MOSI,UART2_RX,TPM0_CH2,SPI0_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_D_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL13Z*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTD3,SPI0_MISO,UART2_TX,TPM0_CH3,SPI0_MOSI,FXIO0_D3,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "DISABLED,PTD3,SPI0_MISO,UART2_TX,TPM0_CH3,SPI0_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_D_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL13Z*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTD4/LLWU_P14,SPI1_PCS0,UART2_RX,TPM0_CH4,,FXIO0_D4,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "DISABLED,PTD4/LLWU_P14,SPI1_PCS0,UART2_RX,TPM0_CH4,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_D_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL13Z*")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Adc0_se6b,PTD5,SPI1_SCK,UART2_TX,TPM0_CH5,,FXIO0_D5,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Adc0_se6b,PTD5,SPI1_SCK,UART2_TX,TPM0_CH5,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_D_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL13Z*")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,LPUART0_RX,I2C1_SDA,SPI1_MISO,FXIO0_D6,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,UART0_RX,,SPI1_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_D_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL13Z*")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "Disabled,PTD7,SPI1_MISO,LPUART0_TX,I2C1_SCL,SPI1_MOSI,FXIO0_D7,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "DISABLED,PTD7,SPI1_MISO,UART0_TX,,SPI1_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x3080++0x03
|
|
line.long 0x00 "PORT_D_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x3084++0x03
|
|
hide.long 0x00 "PORT_D_GPCHR,Global Pin Control High Register"
|
|
group.long 0x30A0++0x03
|
|
line.long 0x00 "PORT_D_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_E"
|
|
tree "Pin Control Registers"
|
|
group.long 0x4000++0x17
|
|
line.long 0x00 "PORT_E_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL13Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTE0/CLKOUT32K,SPI1_MISO,LPUART1_TX,RTC_CLKOUT,CMP0_OUT,I2C1_SDA,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DISABLED,PTE0,,UART1_TX,RTC_CLKOUT,CMP0_OUT,I2C1_SDA,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL13Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTE1,SPI1_MOSI,LPUART1_RX,,SPI1_MISO,I2C1_SCL,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DISABLED,PTE1,SPI1_MOSI,UART1_RX,,SPI1_MISO,I2C1_SCL,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "DISABLED,PTE2,SPI1_SCK,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_E_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "DISABLED,PTE3,SPI1_MISO,,,SPI1_MOSI,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_E_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "DISABLED,PTE4,SPI1_PCS0,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_E_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "DISABLED,PTE5,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4040++0x27
|
|
line.long 0x00 "PORT_E_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLK4")||(cpu()=="MK14LN32VLK4")||(cpu()=="MKL14Z32VLK4")||(cpu()=="MKL14Z64VLK4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE1,PTE16,SPI0_PCS0,UART2_TX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
elif cpuis("MKL13Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_DP1/ADC0_SE1,PTE16,SPI0_PCS0,UART2_TX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_DP1/ADC0_SE1,PTE16,SPI0_PCS0,UART2_TX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLK4")||(cpu()=="MK14LN32VLK4")||(cpu()=="MKL14Z32VLK4")||(cpu()=="MKL14Z64VLK4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_se5a,PTE17,SPI0_SCK,UART2_RX,TPM_CLKIN1,,LPTMR0_ALT3,?..."
|
|
textline " "
|
|
elif cpuis("MKL13Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_se5a,PTE17,SPI0_SCK,UART2_RX,TPM_CLKIN1,LPTMR0_ALT3,FXIO0_D1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_dm1/adc0_se5a,PTE17,SPI0_SCK,UART2_RX,TPM_CLKIN1,,LPTMR0_ALT3,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLK4")||(cpu()=="MK14LN32VLK4")||(cpu()=="MKL14Z32VLK4")||(cpu()=="MKL14Z64VLK4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE2,PTE18,SPI0_MOSI,,I2C0_SDA,SPI0_MISO,?..."
|
|
textline " "
|
|
elif cpuis("MKL13Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE2,PTE18,SPI0_MOSI,,I2C0_SDA,SPI0_MISO,FXIO0_D2,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_DP2/ADC0_SE2,PTE18,SPI0_MOSI,,I2C0_SDA,SPI0_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_E_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLK4")||(cpu()=="MK14LN32VLK4")||(cpu()=="MKL14Z32VLK4")||(cpu()=="MKL14Z64VLK4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_se6a,PTE19,SPI0_MISO,,I2C0_SCL,SPI0_MOSI,?..."
|
|
textline " "
|
|
elif cpuis("MKL13Z*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_se6a,PTE19,SPI0_MISO,,I2C0_SCL,SPI0_MOSI,FXIO0_D3,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_dm2/adc0_se6a,PTE19,SPI0_MISO,,I2C0_SCL,SPI0_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_E_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLK4")||(cpu()=="MK14LN32VLK4")||(cpu()=="MKL14Z32VLK4")||(cpu()=="MKL14Z64VLK4")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "ADC0_SE0,PTE20,,TPM1_CH0,UART0_TX,?..."
|
|
textline " "
|
|
elif cpuis("MKL13Z*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "ADC0_SE0,PTE20,,TPM1_CH0,LPUART0_TX,,FXIO0_D4,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "ADC0_DP0/ADC0_SE0,PTE20,,TPM1_CH0,UART0_TX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_E_PCR21,Pin Control Register 21"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLK4")||(cpu()=="MK14LN32VLK4")||(cpu()=="MKL14Z32VLK4")||(cpu()=="MKL14Z64VLK4")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Adc0_se4a,PTE21,,TPM1_CH1,UART0_RX,?..."
|
|
textline " "
|
|
elif cpuis("MKL13Z*")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Adc0_se4a,PTE21,,TPM1_CH1,LPUART0_RX,,FXIO0_D5,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Adc0_dm0/adc0_se4a,PTE21,,TPM1_CH1,UART0_RX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_E_PCR22,Pin Control Register 22"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLK4")||(cpu()=="MK14LN32VLK4")||(cpu()=="MKL14Z32VLK4")||(cpu()=="MKL14Z64VLK4")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "ADC0_SE3,PTE22,,TPM2_CH0,UART2_TX,?..."
|
|
textline " "
|
|
elif cpuis("MKL13Z*")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "ADC0_SE3,PTE22,,TPM2_CH0,UART2_TX,,FXIO0_D6,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "ADC0_DP3/ADC0_SE3,PTE22,,TPM2_CH0,UART2_TX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_E_PCR23,Pin Control Register 23"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLK4")||(cpu()=="MK14LN32VLK4")||(cpu()=="MKL14Z32VLK4")||(cpu()=="MKL14Z64VLK4")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "Adc0_se7a,PTE23,,TPM2_CH1,UART2_RX,?..."
|
|
textline " "
|
|
elif cpuis("MKL13Z*")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "Adc0_se7a,PTE23,,TPM2_CH1,UART2_RX,,FXIO0_D7,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "Adc0_dm3/adc0_se7a,PTE23,,TPM2_CH1,UART2_RX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x20 "PORT_E_PCR24,Pin Control Register 24"
|
|
eventfld.long 0x20 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "DISABLED,PTE24,,TPM0_CH0,,I2C0_SCL,?..."
|
|
textline " "
|
|
bitfld.long 0x20 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x20 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x20 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x24 "PORT_E_PCR25,Pin Control Register 25"
|
|
eventfld.long 0x24 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "DISABLED,PTE25,,TPM0_CH1,,I2C0_SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x24 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x24 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x24 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4074++0x0B
|
|
line.long 0x00 "PORT_E_PCR29,Pin Control Register 29"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Cmp0_in5/adc0_se4b,PTE29,,TPM0_CH2,TPM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR30,Pin Control Register 30"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MK14LN64VLK4")||(cpu()=="MK14LN32VLK4")||(cpu()=="MKL14Z32VLK4")||(cpu()=="MKL14Z64VLK4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,?..."
|
|
textline " "
|
|
elif cpuis("MKL13Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DAC0_OUT/ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,LPUART1_TX,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DAC0_OUT/ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR31,Pin Control Register 31"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "DISABLED,PTE31,,TPM0_CH4,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x4080++0x07
|
|
line.long 0x00 "PORT_E_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_E_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 31. " GPWE31 ,Global pin 31 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 30. " GPWE30 ,Global pin 30 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 29. " GPWE29 ,Global pin 29 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 25. " GPWE25 ,Global pin 25 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 24. " GPWE24 ,Global pin 24 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 23. " GPWE23 ,Global pin 23 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 22. " GPWE22 ,Global pin 22 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 21. " GPWE21 ,Global pin 21 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x40A0++0x03
|
|
line.long 0x00 "PORT_E_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 31. " ISF31 ,Interrupt status flag 31 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " ISF30 ,Interrupt status flag 30 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 29. " ISF29 ,Interrupt status flag 29 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " ISF25 ,Interrupt status flag 25 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " ISF24 ,Interrupt status flag 24 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 23. " ISF23 ,Interrupt status flag 23 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 22. " ISF22 ,Interrupt status flag 22 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " ISF21 ,Interrupt status flag 21 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
width 0x0B
|
|
endif
|
|
width 0x0B
|
|
elif cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL27Z*")||cpuis("MKL28Z*")
|
|
width 12.
|
|
sif cpuis("MKL2*VFM*")
|
|
width 14.
|
|
tree "PORT_A"
|
|
tree "Pin Control Registers"
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "PORT_A_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VFM4")||(cpu()=="MKL24Z32VFM4")||cpuis("MKL27Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTA0,,TPM0_CH5,,,,SWD_CLK"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH1,PTA0,,TPM0_CH5,,,,SWD_CLK"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VFM4")||(cpu()=="MKL24Z32VFM4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA1,UART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA1,LPUART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH2,PTA1,UART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VFM4")||(cpu()=="MKL24Z32VFM4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA2,UART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA2,LPUART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "TSI0_CH3,PTA2,UART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VFM4")||(cpu()=="MKL24Z32VFM4")||cpuis("MKL27Z*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTA3,I2C1_SCL,TPM0_CH0,,,,SWD_DIO"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "TSI0_CH4,PTA3,I2C1_SCL,TPM0_CH0,,,,SWD_DIO"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VFM4")||(cpu()=="MKL24Z32VFM4")||cpuis("MKL27Z*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTA4,I2C1_SDA,TPM0_CH1,,,,Nmi_b"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "TSI0_CH5,PTA4,I2C1_SDA,TPM0_CH1,,,,Nmi_b"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x48++0x0B
|
|
line.long 0x00 "PORT_A_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL27Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,LPUART1_RX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,UART1_RX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL27Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,,LPUART1_TX,TPM_CLKIN1,,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,,UART1_TX,TPM_CLKIN1,,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL26Z32VFM4")||(cpu()=="MKL26Z64VFM4")||(cpu()=="MKL26Z128VFM4")||cpuis("MKL27Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA20,,,,,,Reset_b"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA20,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x80++0x07
|
|
line.long 0x00 "PORT_A_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_A_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORT_A_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_B"
|
|
tree "Pin Control Registers"
|
|
group.long 0x1000++0x07
|
|
line.long 0x00 "PORT_B_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VFM4")||(cpu()=="MKL24Z32VFM4")||cpuis("MKL27Z128VFM4")||cpuis("MKL27Z256VFM4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z32VFM4")||cpuis("MKL27Z64VFM4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,SPI1_MOSI,SPI1_MISO,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8/TSI0_CH0,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VFM4")||(cpu()=="MKL24Z32VFM4")||cpuis("MKL27Z128VFM4")||cpuis("MKL27Z256VFM4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9,PTB1,I2C0_SDA,TPM1_CH1,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z32VFM4")||cpuis("MKL27Z64VFM4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9,PTB1,I2C0_SDA,TPM1_CH1,SPI1_MISO,SPI1_MOSI,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9/TSI0_CH6,PTB1,I2C0_SDA,TPM1_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x1080++0x03
|
|
line.long 0x00 "PORT_B_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x1084++0x03
|
|
hide.long 0x00 "PORT_B_GPCHR,Global Pin Control High Register"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "PORT_B_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_C"
|
|
tree "Pin Control Registers"
|
|
group.long 0x2004++0x1B
|
|
line.long 0x00 "PORT_C_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VFM4")||(cpu()=="MKL24Z32VFM4")||cpuis("MKL27Z32VFM4")||cpuis("MKL27Z64VFM4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE15,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL26Z32VFM4")||(cpu()=="MKL26Z64VFM4")||(cpu()=="MKL26Z128VFM4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE15/TSI0_CH14,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,,I2S0_TXD0,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z128VFM4")||cpuis("MKL27Z256VFM4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE15,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,,I2S0_TXD0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE15/TSI0_CH14,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_C_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VFM4")||(cpu()=="MKL24Z32VFM4")||cpuis("MKL27Z32VFM4")||cpuis("MKL27Z64VFM4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE11,PTC2,I2C1_SDA,,TPM0_CH1,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z128VFM4")||cpuis("MKL27Z256VFM4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE11,PTC2,I2C1_SDA,,TPM0_CH1,,I2S0_TX_FS,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL26Z32VFM4")||(cpu()=="MKL26Z64VFM4")||(cpu()=="MKL26Z128VFM4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE11/TSI0_CH15,PTC2,I2C1_SDA,,TPM0_CH1,,I2S0_TX_FS,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE11/TSI0_CH15,PTC2,I2C1_SDA,,TPM0_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_C_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL26Z32VFM4")||(cpu()=="MKL26Z64VFM4")||(cpu()=="MKL26Z128VFM4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTC3/LLWU_P7,,UART1_RX,TPM0_CH2,CLKOUT,I2S0_TX_BCLK,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z128VFM4")||cpuis("MKL27Z256VFM4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTC3/LLWU_P7,SPI1_SCK,LPUART1_RX,TPM0_CH2,CLKOUT,I2S0_TX_BCLK,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z32VFM4")||cpuis("MKL27Z64VFM4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTC3/LLWU_P7,SPI1_SCK,LPUART1_RX,TPM0_CH2,CLKOUT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTC3/LLWU_P7,,UART1_RX,TPM0_CH2,CLKOUT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_C_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL26Z32VFM4")||(cpu()=="MKL26Z64VFM4")||(cpu()=="MKL26Z128VFM4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTC4/LLWU_P8,SPI0_PCS0,UART1_TX,TPM0_CH3,I2S0_MCLK,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z32VFM4")||cpuis("MKL27Z64VFM4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTC4/LLWU_P8,SPI0_PCS0,LPUART1_TX,TPM0_CH3,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z128VFM4")||cpuis("MKL27Z256VFM4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTC4/LLWU_P8,SPI0_SS,LPUART1_TX,TPM0_CH3,I2S0_MCLK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTC4/LLWU_P8,SPI0_PCS0,UART1_TX,TPM0_CH3,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_C_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL26Z32VFM4")||(cpu()=="MKL26Z64VFM4")||(cpu()=="MKL26Z128VFM4")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,I2S0_RXD0,,CMP0_OUT,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z32VFM4")||cpuis("MKL27Z64VFM4")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,,,CMP0_OUT,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z128VFM4")||cpuis("MKL27Z256VFM4")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,I2S0_RXD0,,CMP0_OUT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,,,CMP0_OUT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_C_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL26Z32VFM4")||(cpu()=="MKL26Z64VFM4")||(cpu()=="MKL26Z128VFM4")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "CMP0_IN0,PTC6/LLWU_P10,SPI0_MOSI,EXTRG_IN,I2S0_RX_BCLK,SPI0_MISO,I2S0_MCLK,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z32VFM4")||cpuis("MKL27Z64VFM4")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "CMP0_IN0,PTC6/LLWU_P10,SPI0_MOSI,EXTRG_IN,,SPI0_MISO,,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z128VFM4")||cpuis("MKL27Z256VFM4")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "CMP0_IN0,PTC6/LLWU_P10,SPI0_MOSI,EXTRG_IN,I2S0_RX_BCLK,SPI0_MISO,I2S0_MCLK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "CMP0_IN0,PTC6/LLWU_P10,SPI0_MOSI,EXTRG_IN,,SPI0_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_C_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL26Z32VFM4")||(cpu()=="MKL26Z64VFM4")||(cpu()=="MKL26Z128VFM4")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,SPI0_MISO,Audiousb_sof_out,I2S0_RX_FS,SPI0_MOSI,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z32VFM4")||cpuis("MKL27Z64VFM4")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,SPI0_MISO,Audiousb_sof_out,,SPI0_MOSI,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z128VFM4")||cpuis("MKL27Z256VFM4")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,SPI0_MISO,Audiousb_sof_out,I2S0_RX_FS,SPI0_MOSI,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,SPI0_MISO,,,SPI0_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x2080++0x03
|
|
line.long 0x00 "PORT_C_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x2084++0x03
|
|
hide.long 0x00 "PORT_C_GPCHR,Global Pin Control High Register"
|
|
group.long 0x20A0++0x03
|
|
line.long 0x00 "PORT_C_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_D"
|
|
tree "Pin Control Registers"
|
|
group.long 0x3010++0x0F
|
|
line.long 0x00 "PORT_D_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL27Z32VFM4")||cpuis("MKL27Z64VFM4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTD4/LLWU_P14,SPI1_PCS0,UART2_RX,TPM0_CH4,,FXIO0_D4,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z128VFM4")||cpuis("MKL27Z256VFM4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTD4/LLWU_P14,SPI1_SS,UART2_RX,TPM0_CH4,,FXIO0_D4,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTD4/LLWU_P14,SPI1_PCS0,UART2_RX,TPM0_CH4,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_D_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL27Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_se6b,PTD5,SPI1_SCK,UART2_TX,TPM0_CH5,,FXIO0_D5,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_se6b,PTD5,SPI1_SCK,UART2_TX,TPM0_CH5,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_D_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL27Z32VFM4")||cpuis("MKL27Z64VFM4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,LPUART0_RX,I2C1_SDA,SPI1_MISO,FXIO0_D6,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z128VFM4")||cpuis("MKL27Z256VFM4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,LPUART0_RX,,SPI1_MISO,FXIO0_D6,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,UART0_RX,,SPI1_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_D_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL27Z32VFM4")||cpuis("MKL27Z64VFM4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTD7,SPI1_MISO,UART0_TX,I2C1_SCL,SPI1_MOSI,FXIO0_D7,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z128VFM4")||cpuis("MKL27Z256VFM4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTD7,SPI1_MISO,UART0_TX,,SPI1_MOSI,FXIO0_D7,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTD7,SPI1_MISO,UART0_TX,,SPI1_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x3080++0x03
|
|
line.long 0x00 "PORT_D_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x3084++0x03
|
|
hide.long 0x00 "PORT_D_GPCHR,Global Pin Control High Register"
|
|
group.long 0x30A0++0x03
|
|
line.long 0x00 "PORT_D_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_E"
|
|
tree "Pin Control Registers"
|
|
group.long 0x4000++0x03
|
|
line.long 0x00 "PORT_E_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL26Z32VFM4")||(cpu()=="MKL26Z64VFM4")||(cpu()=="MKL26Z128VFM4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTE0,SPI1_MISO,UART1_TX,RTC_CLKOUT,CMP0_OUT,I2C1_SDA,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTE0/CLKOUT32K,SPI1_MISO,LPUART1_TX,RTC_CLKOUT,CMP0_OUT,I2C1_SDA,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTE0,,UART1_TX,RTC_CLKOUT,CMP0_OUT,I2C1_SDA,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4078++0x03
|
|
line.long 0x00 "PORT_E_PCR30,Pin Control Register 30"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VFM4")||(cpu()=="MKL24Z32VFM4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DAC0_OUT/ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,LPUART1_TX,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DAC0_OUT/ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x4080++0x07
|
|
line.long 0x00 "PORT_E_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_E_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 30. " GPWE30 ,Global pin 30 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x40A0++0x03
|
|
line.long 0x00 "PORT_E_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 30. " ISF30 ,Interrupt status flag 30 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL2*CAL*")
|
|
width 14.
|
|
tree "PORT_A"
|
|
tree "Pin Control Registers"
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "PORT_A_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH1,PTA0,,TPM0_CH5,,,,SWD_CLK"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH2,PTA1,UART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "TSI0_CH3,PTA2,UART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "TSI0_CH4,PTA3,I2C1_SCL,TPM0_CH0,,,,SWD_DIO"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "TSI0_CH5,PTA4,I2C1_SDA,TPM0_CH1,,,,Nmi_b"
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x48++0x0B
|
|
line.long 0x00 "PORT_A_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,UART1_RX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,,UART1_TX,TPM_CLKIN1,,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA20,,,,,,Reset_b"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x80++0x07
|
|
line.long 0x00 "PORT_A_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_A_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORT_A_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_B"
|
|
tree "Pin Control Registers"
|
|
group.long 0x1000++0x07
|
|
line.long 0x00 "PORT_B_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8/TSI0_CH0,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9/TSI0_CH6,PTB1,I2C0_SDA,TPM1_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x1080++0x03
|
|
line.long 0x00 "PORT_B_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x1084++0x03
|
|
hide.long 0x00 "PORT_B_GPCHR,Global Pin Control High Register"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "PORT_B_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_C"
|
|
tree "Pin Control Registers"
|
|
group.long 0x2004++0x1B
|
|
line.long 0x00 "PORT_C_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE15/TSI0_CH14,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,,I2S0_TXD0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_C_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE11/TSI0_CH15,PTC2,I2C1_SDA,,TPM0_CH1,,I2S0_TX_FS,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_C_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTC3/LLWU_P7,,UART1_RX,TPM0_CH2,CLKOUT,I2S0_TX_BCLK,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_C_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTC4/LLWU_P8,SPI0_PCS0,UART1_TX,TPM0_CH3,I2S0_MCLK,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_C_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,I2S0_RXD0,,CMP0_OUT,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_C_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "CMP0_IN0,PTC6/LLWU_P10,SPI0_MOSI,EXTRG_IN,I2S0_RX_BCLK,SPI0_MISO,I2S0_MCLK,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_C_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,SPI0_MISO,Audiousb_sof_out,I2S0_RX_FS,SPI0_MOSI,?..."
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x2080++0x03
|
|
line.long 0x00 "PORT_C_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x2084++0x03
|
|
hide.long 0x00 "PORT_C_GPCHR,Global Pin Control High Register"
|
|
group.long 0x20A0++0x03
|
|
line.long 0x00 "PORT_C_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_D"
|
|
tree "Pin Control Registers"
|
|
group.long 0x3010++0x0F
|
|
line.long 0x00 "PORT_D_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTD4/LLWU_P14,SPI1_PCS0,UART2_RX,TPM0_CH4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_D_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_se6b,PTD5,SPI1_SCK,UART2_TX,TPM0_CH5,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_D_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,UART0_RX,,SPI1_MISO,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_D_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTD7,SPI1_MISO,UART0_TX,,SPI1_MOSI,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x3080++0x03
|
|
line.long 0x00 "PORT_D_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x3084++0x03
|
|
hide.long 0x00 "PORT_D_GPCHR,Global Pin Control High Register"
|
|
group.long 0x30A0++0x03
|
|
line.long 0x00 "PORT_D_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_E"
|
|
tree "Pin Control Registers"
|
|
group.long 0x4000++0x03
|
|
line.long 0x00 "PORT_E_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTE0,SPI1_MISO,UART1_TX,RTC_CLKOUT,CMP0_OUT,I2C1_SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4040++0x0F
|
|
line.long 0x00 "PORT_E_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_DP1/ADC0_SE1,PTE16,SPI0_PCS0,UART2_TX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_dm1/adc0_se5a,PTE17,SPI0_SCK,UART2_RX,TPM_CLKIN1,,LPTMR0_ALT3,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_DP2/ADC0_SE2,PTE18,SPI0_MOSI,,I2C0_SDA,SPI0_MISO,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_E_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_dm2/adc0_se6a,PTE19,SPI0_MISO,,I2C0_SCL,SPI0_MOSI,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4074++0x07
|
|
line.long 0x00 "PORT_E_PCR30,Pin Control Register 30"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DAC0_OUT/ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x4080++0x07
|
|
line.long 0x00 "PORT_E_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_E_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 30. " GPWE30 ,Global pin 30 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x40A0++0x03
|
|
line.long 0x00 "PORT_E_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 30. " ISF30 ,Interrupt status flag 30 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL2*VDA*")
|
|
width 14.
|
|
tree "PORT_A"
|
|
tree "Pin Control Registers"
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "PORT_A_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTA0,,TPM0_CH5,,,,SWD_CLK"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA1,LPUART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA2,LPUART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTA3,I2C1_SCL,TPM0_CH0,,,,SWD_DIO"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTA4,I2C1_SDA,TPM0_CH1,,,,Nmi_b"
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x48++0x0B
|
|
line.long 0x00 "PORT_A_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,LPUART1_RX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,,LPUART1_TX,TPM_CLKIN1,,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA20,,,,,,Reset_b"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x80++0x07
|
|
line.long 0x00 "PORT_A_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_A_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORT_A_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_B"
|
|
tree "Pin Control Registers"
|
|
group.long 0x1000++0x07
|
|
line.long 0x00 "PORT_B_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,SPI1_MOSI,SPI1_MISO,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9,PTB1,I2C0_SDA,TPM1_CH1,SPI1_MISO,SPI1_MOSI,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x1080++0x03
|
|
line.long 0x00 "PORT_B_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x1084++0x03
|
|
hide.long 0x00 "PORT_B_GPCHR,Global Pin Control High Register"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "PORT_B_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_C"
|
|
tree "Pin Control Registers"
|
|
group.long 0x2004++0x1B
|
|
line.long 0x00 "PORT_C_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE15,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_C_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE11,PTC2,I2C1_SDA,,TPM0_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_C_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTC3/LLWU_P7,SPI1_SCK,LPUART1_RX,TPM0_CH2,CLKOUT,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_C_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTC4/LLWU_P8,SPI0_PCS0,LPUART1_TX,TPM0_CH3,SPI1_PCS0,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_C_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,,,CMP0_OUT,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_C_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "CMP0_IN0,PTC6/LLWU_P10,SPI0_MOSI,EXTRG_IN,,SPI0_MISO,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_C_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,SPI0_MISO,Audiousb_sof_out,,SPI0_MOSI,?..."
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x2080++0x03
|
|
line.long 0x00 "PORT_C_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x2084++0x03
|
|
hide.long 0x00 "PORT_C_GPCHR,Global Pin Control High Register"
|
|
group.long 0x20A0++0x03
|
|
line.long 0x00 "PORT_C_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_D"
|
|
tree "Pin Control Registers"
|
|
group.long 0x3010++0x0F
|
|
line.long 0x00 "PORT_D_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTD4/LLWU_P14,SPI1_PCS0,UART2_RX,TPM0_CH4,,FXIO0_D4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_D_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_se6b,PTD5,SPI1_SCK,UART2_TX,TPM0_CH5,,FXIO0_D5,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_D_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,LPUART0_RX,I2C1_SDA,SPI1_MISO,FXIO0_D6,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_D_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTD7,SPI1_MISO,LPUART0_TX,I2C1_SCL,SPI1_MOSI,FXIO0_D7,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x3080++0x03
|
|
line.long 0x00 "PORT_D_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x3084++0x03
|
|
hide.long 0x00 "PORT_D_GPCHR,Global Pin Control High Register"
|
|
group.long 0x30A0++0x03
|
|
line.long 0x00 "PORT_D_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_E"
|
|
tree "Pin Control Registers"
|
|
group.long 0x4000++0x03
|
|
line.long 0x00 "PORT_E_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTE0/CLKOUT32K,SPI1_MISO,LPUART1_TX,RTC_CLKOUT,CMP0_OUT,I2C1_SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4040++0x0B
|
|
line.long 0x00 "PORT_E_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_DP1/ADC0_SE1,PTE16,SPI0_PCS0,UART2_TX,TPM_CLKIN0,,FXIO0_D0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_dm1/adc0_se5a,PTE17,SPI0_SCK,UART2_RX,TPM_CLKIN1,LPTMR0_ALT3,FXIO0_D1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Adc0_dp2/adc0_se2a,PTE18,SPI0_MOSI,,I2C0_SDA,SPI0_MISO,FXIO0_D2,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4050++0x0F
|
|
line.long 0x00 "PORT_E_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_DP0/ADC0_SE0,PTE20,,TPM1_CH0,LPUART0_TX,,FXIO0_D4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR21,Pin Control Register 21"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_dm0/adc0_se4a,PTE21,,TPM1_CH1,LPUART0_RX,,FXIO0_D5,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR22,Pin Control Register 22"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_DP3/ADC0_SE3,PTE22,,TPM2_CH0,UART2_TX,,FXIO0_D6,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_E_PCR23,Pin Control Register 23"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_dm3/adc0_se7a,PTE23,,TPM2_CH1,UART2_RX,,FXIO0_D7,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4078++0x03
|
|
line.long 0x00 "PORT_E_PCR30,Pin Control Register 30"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,LPUART1_TX,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x4080++0x07
|
|
line.long 0x00 "PORT_E_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_E_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 30. " GPWE30 ,Global pin 30 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 23. " GPWE23 ,Global pin 23 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 22. " GPWE22 ,Global pin 22 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 21. " GPWE21 ,Global pin 21 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x40A0++0x03
|
|
line.long 0x00 "PORT_E_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 30. " ISF30 ,Interrupt status flag 30 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 23. " ISF23 ,Interrupt status flag 23 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " ISF22 ,Interrupt status flag 22 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 21. " ISF21 ,Interrupt status flag 21 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL2*VFT*")
|
|
width 14.
|
|
tree "PORT_A"
|
|
tree "Pin Control Registers"
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "PORT_A_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VFT4")||(cpu()=="MKL24Z32VFT4")||cpuis("MKL27Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTA0,,TPM0_CH5,,,,SWD_CLK"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH1,PTA0,,TPM0_CH5,,,,SWD_CLK"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VFT4")||(cpu()=="MKL24Z32VFT4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA1,UART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA1,LPUART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH2,PTA1,UART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VFT4")||(cpu()=="MKL24Z32VFT4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA2,UART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA2,LPUART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "TSI0_CH3,PTA2,UART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VFT4")||(cpu()=="MKL24Z32VFT4")||cpuis("MKL27Z*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTA3,I2C1_SCL,TPM0_CH0,,,,SWD_DIO"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "TSI0_CH4,PTA3,I2C1_SCL,TPM0_CH0,,,,SWD_DIO"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VFT4")||(cpu()=="MKL24Z32VFT4")||cpuis("MKL27Z*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTA4,I2C1_SDA,TPM0_CH1,,,,Nmi_b"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "TSI0_CH5,PTA4,I2C1_SDA,TPM0_CH1,,,,Nmi_b"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x48++0x0B
|
|
line.long 0x00 "PORT_A_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL27Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,LPUART1_RX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,UART1_RX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL27Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,,LPUART1_TX,TPM_CLKIN1,,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,,UART1_TX,TPM_CLKIN1,,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL27Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA20,,,,,,Reset_b"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA20,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x80++0x07
|
|
line.long 0x00 "PORT_A_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_A_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORT_A_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_B"
|
|
tree "Pin Control Registers"
|
|
group.long 0x1000++0x0F
|
|
line.long 0x00 "PORT_B_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VFT4")||(cpu()=="MKL24Z32VFT4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z32VFT4")||cpuis("MKL27Z64VFT4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,,SPI1_MOSI,SPI1_MISO,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z128VFT4")||cpuis("MKL27Z256VFT4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8/TSI0_CH0,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VFT4")||(cpu()=="MKL24Z32VFT4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9,PTB1,I2C0_SDA,TPM1_CH1,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z32VFT4")||cpuis("MKL27Z64VFT4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9,PTB1,I2C0_SDA,TPM1_CH1,SPI1_MISO,SPI1_MOSI,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z128VFT4")||cpuis("MKL27Z256VFT4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9,PTB1,I2C0_SDA,TPM1_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9/TSI0_CH6,PTB1,I2C0_SDA,TPM1_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VFT4")||(cpu()=="MKL24Z32VFT4")||cpuis("MKL27Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE12,PTB2,I2C0_SCL,TPM2_CH0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE12/TSI0_CH7,PTB2,I2C0_SCL,TPM2_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VFT4")||(cpu()=="MKL24Z32VFT4")||cpuis("MKL27Z*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_SE13,PTB3,I2C0_SDA,TPM2_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_SE13/TSI0_CH8,PTB3,I2C0_SDA,TPM2_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x1040++0x07
|
|
line.long 0x00 "PORT_B_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VFT4")||(cpu()=="MKL24Z32VFT4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTB16,SPI1_MOSI,UART0_RX,TPM_CLKIN0,SPI1_MISO,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTB16,SPI1_MOSI,LPUART0_RX,TPM_CLKIN0,SPI1_MISO,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH9,PTB16,SPI1_MOSI,UART0_RX,TPM_CLKIN0,SPI1_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VFT4")||(cpu()=="MKL24Z32VFT4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTB17,SPI1_MISO,UART0_TX,TPM_CLKIN1,SPI1_MOSI,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTB17,SPI1_MISO,LPUART0_TX,TPM_CLKIN1,SPI1_MOSI,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH10,PTB17,SPI1_MISO,UART0_TX,TPM_CLKIN1,SPI1_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x1080++0x07
|
|
line.long 0x00 "PORT_B_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_B_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "PORT_B_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_C"
|
|
tree "Pin Control Registers"
|
|
group.long 0x2000++0x1F
|
|
line.long 0x00 "PORT_C_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VFT4")||(cpu()=="MKL24Z32VFT4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE14,PTC0,,EXTRG_IN,,CMP0_OUT,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL26Z32VFT4")||(cpu()=="MKL26Z64VFT4")||(cpu()=="MKL26Z128VFT4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE14/TSI0_CH13,PTC0,,EXTRG_IN,Audiousb_sof_out,CMP0_OUT,I2S0_TXD0,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z32VFT4")||cpuis("MKL27Z64VFT4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE14,PTC0,,EXTRG_IN,Audiousb_sof_out,CMP0_OUT,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z128VFT4")||cpuis("MKL27Z256VFT4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE14,PTC0,,EXTRG_IN,Audiousb_sof_out,CMP0_OUT,I2S0_TXD0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE14/TSI0_CH13,PTC0,,EXTRG_IN,,CMP0_OUT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_C_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VFT4")||(cpu()=="MKL24Z32VFT4")||cpuis("MKL27Z32VFT4")||cpuis("MKL27Z64VFT4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE15,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z128VFT4")||cpuis("MKL27Z256VFT4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE15,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,,I2S0_TXD0,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL26Z32VFT4")||(cpu()=="MKL26Z64VFT4")||(cpu()=="MKL26Z128VFT4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE15/TSI0_CH14,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,,I2S0_TXD0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE15/TSI0_CH14,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_C_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VFT4")||(cpu()=="MKL24Z32VFT4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE11,PTC2,I2C1_SDA,,TPM0_CH1,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z128VFT4")||cpuis("MKL27Z256VFT4")||cpuis("MKL27Z32VFT4")||cpuis("MKL27Z64VFT4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE11,PTC2,I2C1_SDA,,TPM0_CH1,,I2S0_TX_FS,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL26Z32VFT4")||(cpu()=="MKL26Z64VFT4")||(cpu()=="MKL26Z128VFT4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE11/TSI0_CH15,PTC2,I2C1_SDA,,TPM0_CH1,,I2S0_TX_FS,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE11/TSI0_CH15,PTC2,I2C1_SDA,,TPM0_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_C_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL26Z32VFT4")||(cpu()=="MKL26Z64VFT4")||(cpu()=="MKL26Z128VFT4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTC3/LLWU_P7,,UART1_RX,TPM0_CH2,CLKOUT,I2S0_TX_BCLK,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z32VFT4")||cpuis("MKL27Z64VFT4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTC3/LLWU_P7,SPI1_SCK,LPUART1_RX,TPM0_CH2,CLKOUT,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z128VFT4")||cpuis("MKL27Z256VFT4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTC3/LLWU_P7,SPI1_SCK,LPUART1_RX,TPM0_CH2,CLKOUT,I2S0_TX_BCLK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTC3/LLWU_P7,,UART1_RX,TPM0_CH2,CLKOUT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_C_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL26Z32VFT4")||(cpu()=="MKL26Z64VFT4")||(cpu()=="MKL26Z128VFT4")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTC4/LLWU_P8,SPI0_PCS0,UART1_TX,TPM0_CH3,I2S0_MCLK,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z32VFT4")||cpuis("MKL27Z64VFT4")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTC4/LLWU_P8,SPI0_PCS0,LPUART1_TX,TPM0_CH3,SPI1_PCS0,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z128VFT4")||cpuis("MKL27Z256VFT4")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTC4/LLWU_P8,SPI0_SS,LPUART1_TX,TPM0_CH3,I2S0_MCLK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTC4/LLWU_P8,SPI0_PCS0,UART1_TX,TPM0_CH3,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_C_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL26Z32VFT4")||(cpu()=="MKL26Z64VFT4")||(cpu()=="MKL26Z128VFT4")||cpuis("MKL27Z128VFT4")||cpuis("MKL27Z256VFT4")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,I2S0_RXD0,,CMP0_OUT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,,,CMP0_OUT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_C_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL26Z32VFT4")||(cpu()=="MKL26Z64VFT4")||(cpu()=="MKL26Z128VFT4")||cpuis("MKL27Z128VFT4")||cpuis("MKL27Z256VFT4")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "CMP0_IN0,PTC6/LLWU_P10,SPI0_MOSI,EXTRG_IN,I2S0_RX_BCLK,SPI0_MISO,I2S0_MCLK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "CMP0_IN0,PTC6/LLWU_P10,SPI0_MOSI,EXTRG_IN,,SPI0_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_C_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL26Z32VFT4")||(cpu()=="MKL26Z64VFT4")||(cpu()=="MKL26Z128VFT4")||cpuis("MKL27Z128VFT4")||cpuis("MKL27Z256VFT4")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,SPI0_MISO,Audiousb_sof_out,I2S0_RX_FS,SPI0_MOSI,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z32VFT4")||cpuis("MKL27Z64VFT4")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,SPI0_MISO,Audiousb_sof_out,,SPI0_MOSI,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,SPI0_MISO,,,SPI0_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x2080++0x03
|
|
line.long 0x00 "PORT_C_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x2084++0x03
|
|
hide.long 0x00 "PORT_C_GPCHR,Global Pin Control High Register"
|
|
group.long 0x20A0++0x03
|
|
line.long 0x00 "PORT_C_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_D"
|
|
tree "Pin Control Registers"
|
|
group.long 0x3000++0x1F
|
|
line.long 0x00 "PORT_D_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL27Z128VFT4")||cpuis("MKL27Z256VFT4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTD0,SPI0_SS,,TPM0_CH0,,FXIO0_D0,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z32VFT4")||cpuis("MKL27Z64VFT4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTD0,SPI0_PCS0,,TPM0_CH0,,FXIO0_D0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTD0,SPI0_PCS0,,TPM0_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_D_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL27Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_se5b,PTD1,SPI0_SCK,,TPM0_CH1,,FXIO0_D1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_se5b,PTD1,SPI0_SCK,,TPM0_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_D_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL27Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTD2,SPI0_MOSI,UART2_RX,TPM0_CH2,SPI0_MISO,FXIO0_D2,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTD2,SPI0_MOSI,UART2_RX,TPM0_CH2,SPI0_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_D_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL27Z*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTD3,SPI0_MISO,UART2_TX,TPM0_CH3,SPI0_MOSI,FXIO0_D3,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTD3,SPI0_MISO,UART2_TX,TPM0_CH3,SPI0_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_D_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL27Z32VFT4")||cpuis("MKL27Z64VFT4")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTD4/LLWU_P14,SPI1_PCS0,UART2_RX,TPM0_CH4,,FXIO0_D4,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z128VFT4")||cpuis("MKL27Z256VFT4")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTD4/LLWU_P14,SPI1_SS,UART2_RX,TPM0_CH4,,FXIO0_D4,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTD4/LLWU_P14,SPI1_PCS0,UART2_RX,TPM0_CH4,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_D_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL27Z*")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Adc0_se6b,PTD5,SPI1_SCK,UART2_TX,TPM0_CH5,,FXIO0_D5,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Adc0_se6b,PTD5,SPI1_SCK,UART2_TX,TPM0_CH5,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_D_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL27Z32VFT4")||cpuis("MKL27Z64VFT4")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,LPUART0_RX,I2C1_SDA,SPI1_MISO,FXIO0_D6,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z128VFT4")||cpuis("MKL27Z256VFT4")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,LPUART0_RX,,SPI1_MISO,FXIO0_D6,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,UART0_RX,,SPI1_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_D_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL27Z32VFT4")||cpuis("MKL27Z64VFT4")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "Disabled,PTD7,SPI1_MISO,LPUART0_TX,I2C1_SCL,SPI1_MOSI,FXIO0_D7,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z128VFT4")||cpuis("MKL27Z256VFT4")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "Disabled,PTD7,SPI1_MISO,LPUART0_TX,,SPI1_MOSI,FXIO0_D7,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "Disabled,PTD7,SPI1_MISO,UART0_TX,,SPI1_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x3080++0x03
|
|
line.long 0x00 "PORT_D_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x3084++0x03
|
|
hide.long 0x00 "PORT_D_GPCHR,Global Pin Control High Register"
|
|
group.long 0x30A0++0x03
|
|
line.long 0x00 "PORT_D_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_E"
|
|
tree "Pin Control Registers"
|
|
sif cpuis("MKL27Z32VFT4")||cpuis("MKL27Z64VFT4")
|
|
group.long 0x4040++0x03
|
|
line.long 0x00 "PORT_E_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_DP1/ADC0_SE1,PTE16,SPI0_PCS0,LPUART2_TX,TPM_CLKIN0,,FXIO0_D0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
endif
|
|
group.long 0x4050++0x07
|
|
line.long 0x00 "PORT_E_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VFT4")||(cpu()=="MKL24Z32VFT4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE0,PTE20,,TPM1_CH0,UART0_TX,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_DP0/ADC0_SE0,PTE20,,TPM1_CH0,LPUART0_TX,,FXIO0_D4,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_DP0/ADC0_SE0,PTE20,,TPM1_CH0,UART0_TX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR21,Pin Control Register 21"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VFT4")||(cpu()=="MKL24Z32VFT4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_se4a,PTE21,,TPM1_CH1,UART0_RX,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_se4a,PTE21,,TPM1_CH1,LPUART0_RX,,FXIO0_D5,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_dm0/adc0_se4a,PTE21,,TPM1_CH1,UART0_RX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4060++0x07
|
|
line.long 0x00 "PORT_E_PCR24,Pin Control Register 24"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTE24,,TPM0_CH0,,I2C0_SCL,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR25,Pin Control Register 25"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTE25,,TPM0_CH1,,I2C0_SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4074++0x07
|
|
line.long 0x00 "PORT_E_PCR29,Pin Control Register 29"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Cmp0_in5/adc0_se4b,PTE29,,TPM0_CH2,TPM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR30,Pin Control Register 30"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VFT4")||(cpu()=="MKL24Z32VFT4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,LPUART1_TX,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DAC0_OUT/ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x4080++0x07
|
|
line.long 0x00 "PORT_E_GPCLR,Global Pin Control Low Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_E_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 30. " GPWE30 ,Global pin 30 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 29. " GPWE29 ,Global pin 29 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 25. " GPWE25 ,Global pin 25 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 24. " GPWE24 ,Global pin 24 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 21. " GPWE21 ,Global pin 21 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
sif cpuis("MKL27Z32VFT4")||cpuis("MKL27Z64VFT4")
|
|
textline " "
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x40A0++0x03
|
|
line.long 0x00 "PORT_E_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 30. " ISF30 ,Interrupt status flag 30 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 29. " ISF29 ,Interrupt status flag 29 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 25. " ISF25 ,Interrupt status flag 25 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 24. " ISF24 ,Interrupt status flag 24 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " ISF21 ,Interrupt status flag 21 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
sif cpuis("MKL27Z32VFT4")||cpuis("MKL27Z64VFT4")
|
|
textline " "
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 161 (in digital modes only)" "No interrupt,Interrupt"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL2*VLH*")||cpuis("MKL2*VMP*")
|
|
width 14.
|
|
tree "PORT_A"
|
|
tree "Pin Control Registers"
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "PORT_A_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLH4")||(cpu()=="MKL24Z32VLH4")||cpuis("MKL27Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTA0,,TPM0_CH5,,,,SWD_CLK"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH1,PTA0,,TPM0_CH5,,,,SWD_CLK"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLH4")||(cpu()=="MKL24Z32VLH4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA1,UART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA1,LPUART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH2,PTA1,UART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLH4")||(cpu()=="MKL24Z32VLH4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA2,UART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA2,LPUART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "TSI0_CH3,PTA2,UART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLH4")||(cpu()=="MKL24Z32VLH4")||cpuis("MKL27Z*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTA3,I2C1_SCL,TPM0_CH0,,,,SWD_DIO"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "TSI0_CH4,PTA3,I2C1_SCL,TPM0_CH0,,,,SWD_DIO"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLH4")||(cpu()=="MKL24Z32VLH4")||cpuis("MKL27Z*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTA4,I2C1_SDA,TPM0_CH1,,,,Nmi_b"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "TSI0_CH5,PTA4,I2C1_SDA,TPM0_CH1,,,,Nmi_b"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_A_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL26Z128VMP4")||cpuis("MKL27Z128VMP4")||cpuis("MKL27Z256VMP4")||cpuis("MKL27Z128VLH4")||cpuis("MKL27Z256VLH4")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA5,USB_CLKIN,TPM0_CH2,,,I2S0_TX_BCLK,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z32VMP4")||cpuis("MKL27Z64VMP4")||cpuis("MKL27Z32VLH4")||cpuis("MKL27Z64VLH4")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA5,USB_CLKIN,TPM0_CH2,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA5,USB_CLKIN,TPM0_CH2,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "PORT_A_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL26Z128VMP4")||cpuis("MKL27Z128VMP4")||cpuis("MKL27Z256VMP4")||cpuis("MKL27Z128VLH4")||cpuis("MKL27Z256VLH4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTA12,,TPM1_CH0,,,I2S0_TXD0,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z32VMP4")||cpuis("MKL27Z64VMP4")||cpuis("MKL27Z32VLH4")||cpuis("MKL27Z64VLH4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTA12,,TPM1_CH0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTA12,,TPM1_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL26Z128VMP4")||cpuis("MKL27Z128VMP4")||cpuis("MKL27Z256VMP4")||cpuis("MKL27Z128VLH4")||cpuis("MKL27Z256VLH4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA13,,TPM1_CH1,,,I2S0_TX_FS,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z32VMP4")||cpuis("MKL27Z64VMP4")||cpuis("MKL27Z32VLH4")||cpuis("MKL27Z64VLH4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA13,,TPM1_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA13,,TPM1_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x48++0x0B
|
|
line.long 0x00 "PORT_A_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL27Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,LPUART1_RX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,UART1_RX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL27Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,,LPUART1_TX,TPM_CLKIN1,,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,,UART1_TX,TPM_CLKIN1,,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL26Z128VMP4")||cpuis("MKL27Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA20,,,,,,Reset_b"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA20,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x80++0x07
|
|
line.long 0x00 "PORT_A_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 29. " GPWE13 ,Global pin 13 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 28. " GPWE12 ,Global pin 12 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_A_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORT_A_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " ISF13 ,Interrupt status flag 13 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " ISF12 ,Interrupt status flag 12 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_B"
|
|
tree "Pin Control Registers"
|
|
group.long 0x1000++0x0F
|
|
line.long 0x00 "PORT_B_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLH4")||(cpu()=="MKL24Z32VLH4")||cpuis("MKL27Z128VMP4")||cpuis("MKL27Z256VMP4")||cpuis("MKL27Z128VLH4")||cpuis("MKL27Z256VLH4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z32VMP4")||cpuis("MKL27Z64VMP4")||cpuis("MKL27Z32VLH4")||cpuis("MKL27Z64VLH4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,SPI1_MOSI,SPI1_MISO,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8/TSI0_CH0,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLH4")||(cpu()=="MKL24Z32VLH4")||cpuis("MKL27Z128VMP4")||cpuis("MKL27Z256VMP4")||cpuis("MKL27Z128VLH4")||cpuis("MKL27Z256VLH4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9,PTB1,I2C0_SDA,TPM1_CH1,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z32VMP4")||cpuis("MKL27Z64VMP4")||cpuis("MKL27Z32VLH4")||cpuis("MKL27Z64VLH4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9,PTB1,I2C0_SDA,TPM1_CH1,SPI1_MISO,SPI1_MOSI,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9/TSI0_CH6,PTB1,I2C0_SDA,TPM1_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLH4")||(cpu()=="MKL24Z32VLH4")||cpuis("MKL27Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE12,PTB2,I2C0_SCL,TPM2_CH0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE12/TSI0_CH7,PTB2,I2C0_SCL,TPM2_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLH4")||(cpu()=="MKL24Z32VLH4")||cpuis("MKL27Z*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_SE13,PTB3,I2C0_SDA,TPM2_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_SE13/TSI0_CH8,PTB3,I2C0_SDA,TPM2_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x1040++0x0F
|
|
line.long 0x00 "PORT_B_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLH4")||(cpu()=="MKL24Z32VLH4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTB16,SPI1_MOSI,UART0_RX,TPM_CLKIN0,SPI1_MISO,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTB16,SPI1_MOSI,LPUART0_RX,TPM_CLKIN0,SPI1_MISO,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH9,PTB16,SPI1_MOSI,UART0_RX,TPM_CLKIN0,SPI1_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLH4")||(cpu()=="MKL24Z32VLH4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTB17,SPI1_MISO,UART0_TX,TPM_CLKIN1,SPI1_MOSI,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTB17,SPI1_MISO,LPUART0_TX,TPM_CLKIN1,SPI1_MOSI,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH10,PTB17,SPI1_MISO,UART0_TX,TPM_CLKIN1,SPI1_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLH4")||(cpu()=="MKL24Z32VLH4")||cpuis("MKL27Z32VMP4")||cpuis("MKL27Z64VMP4")||cpuis("MKL27Z32VLH4")||cpuis("MKL27Z64VLH4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTB18,,TPM2_CH0,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z128VMP4")||cpuis("MKL27Z256VMP4")||cpuis("MKL27Z128VLH4")||cpuis("MKL27Z256VLH4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTB18,,TPM2_CH0,I2S0_TX_BCLK,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL26Z32VLH4")||(cpu()=="MKL26Z64VLH4")||(cpu()=="MKL26Z128VLH4")||(cpu()=="MKL26Z256VLH4")||cpuis("MKL26Z128VMP4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "TSI0_CH11,PTB18,,TPM2_CH0,I2S0_TX_BCLK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "TSI0_CH11,PTB18,,TPM2_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLH4")||(cpu()=="MKL24Z32VLH4")||cpuis("MKL27Z32VMP4")||cpuis("MKL27Z64VMP4")||cpuis("MKL27Z32VLH4")||cpuis("MKL27Z64VLH4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTB19,,TPM2_CH1,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z128VMP4")||cpuis("MKL27Z256VMP4")||cpuis("MKL27Z128VLH4")||cpuis("MKL27Z256VLH4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTB19,,TPM2_CH1,I2S0_TX_FS,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL26Z32VLH4")||(cpu()=="MKL26Z64VLH4")||(cpu()=="MKL26Z128VLH4")||(cpu()=="MKL26Z256VLH4")||cpuis("MKL26Z128VMP4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "TSI0_CH12,PTB19,,TPM2_CH1,I2S0_TX_FS,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "TSI0_CH12,PTB19,,TPM2_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x1080++0x07
|
|
line.long 0x00 "PORT_B_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_B_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "PORT_B_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_C"
|
|
tree "Pin Control Registers"
|
|
group.long 0x2000++0x2F
|
|
line.long 0x00 "PORT_C_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLH4")||(cpu()=="MKL24Z32VLH4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE14,PTC0,,EXTRG_IN,,CMP0_OUT,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL26Z32VLH4")||(cpu()=="MKL26Z64VLH4")||(cpu()=="MKL26Z128VLH4")||(cpu()=="MKL26Z256VLH4")||cpuis("MKL26Z128VMP4")||cpuis("MKL27Z128VMP4")||cpuis("MKL27Z256VMP4")||cpuis("MKL27Z128VLH4")||cpuis("MKL27Z256VLH4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE14/TSI0_CH13,PTC0,,EXTRG_IN,Audiousb_sof_out,CMP0_OUT,I2S0_TXD0,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z32VMP4")||cpuis("MKL27Z64VMP4")||cpuis("MKL27Z32VLH4")||cpuis("MKL27Z64VLH4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE14/TSI0_CH13,PTC0,,EXTRG_IN,Audiousb_sof_out,CMP0_OUT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE14/TSI0_CH13,PTC0,,EXTRG_IN,,CMP0_OUT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_C_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLH4")||(cpu()=="MKL24Z32VLH4")||cpuis("MKL27Z32VMP4")||cpuis("MKL27Z64VMP4")||cpuis("MKL27Z32VLH4")||cpuis("MKL27Z64VLH4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE15,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z128VMP4")||cpuis("MKL27Z256VMP4")||cpuis("MKL27Z128VLH4")||cpuis("MKL27Z256VLH4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE15,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,,I2S0_TXD0,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL26Z32VLH4")||(cpu()=="MKL26Z64VLH4")||(cpu()=="MKL26Z128VLH4")||(cpu()=="MKL26Z256VLH4")||cpuis("MKL26Z128VMP4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE15/TSI0_CH14,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,,I2S0_TXD0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE15/TSI0_CH14,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_C_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLH4")||(cpu()=="MKL24Z32VLH4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE11,PTC2,I2C1_SDA,,TPM0_CH1,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z128VMP4")||cpuis("MKL27Z256VMP4")||cpuis("MKL27Z128VLH4")||cpuis("MKL27Z256VLH4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE11,PTC2,I2C1_SDA,,TPM0_CH1,,I2S0_TX_FS,?..."
|
|
textline " "
|
|
elif (cpu()=="MKL26Z32VLH4")||(cpu()=="MKL26Z64VLH4")||(cpu()=="MKL26Z128VLH4")||(cpu()=="MKL26Z256VLH4")||cpuis("MKL26Z128VMP4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE11/TSI0_CH15,PTC2,I2C1_SDA,,TPM0_CH1,,I2S0_TX_FS,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE11/TSI0_CH15,PTC2,I2C1_SDA,,TPM0_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_C_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL26Z32VLH4")||(cpu()=="MKL26Z64VLH4")||(cpu()=="MKL26Z128VLH4")||(cpu()=="MKL26Z256VLH4")||cpuis("MKL26Z128VMP4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTC3/LLWU_P7,,UART1_RX,TPM0_CH2,CLKOUT,I2S0_TX_BCLK,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z128VMP4")||cpuis("MKL27Z256VMP4")||cpuis("MKL27Z128VLH4")||cpuis("MKL27Z256VLH4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTC3/LLWU_P7,SPI1_SCK,LPUART1_RX,TPM0_CH2,CLKOUT,I2S0_TX_BCLK,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z32VMP4")||cpuis("MKL27Z64VMP4")||cpuis("MKL27Z32VLH4")||cpuis("MKL27Z64VLH4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTC3/LLWU_P7,SPI1_SCK,LPUART1_RX,TPM0_CH2,CLKOUT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTC3/LLWU_P7,,UART1_RX,TPM0_CH2,CLKOUT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_C_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL26Z128VMP4")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTC4/LLWU_P8,SPI0_PCS0,UART1_TX,TPM0_CH3,I2S0_MCLK,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z32VMP4")||cpuis("MKL27Z64VMP4")||cpuis("MKL27Z32VLH4")||cpuis("MKL27Z64VLH4")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTC4/LLWU_P8,SPI0_PCS0,LPUART1_TX,TPM0_CH3,SPI1_PCS0,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z128VMP4")||cpuis("MKL27Z256VMP4")||cpuis("MKL27Z128VLH4")||cpuis("MKL27Z256VLH4")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTC4/LLWU_P8,SPI0_SS,LPUART1_TX,TPM0_CH3,I2S0_MCLK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTC4/LLWU_P8,SPI0_PCS0,UART1_TX,TPM0_CH3,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_C_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL26Z32VLH4")||(cpu()=="MKL26Z64VLH4")||(cpu()=="MKL26Z128VLH4")||(cpu()=="MKL26Z256VLH4")||cpuis("MKL26Z128VMP4")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,I2S0_RXD0,,CMP0_OUT,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z128VMP4")||cpuis("MKL27Z256VMP4")||cpuis("MKL27Z128VLH4")||cpuis("MKL27Z256VLH4")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,I2S0_RXD0,,CMP0_OUT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,,,CMP0_OUT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_C_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL26Z32VLH4")||(cpu()=="MKL26Z64VLH4")||(cpu()=="MKL26Z128VLH4")||(cpu()=="MKL26Z256VLH4")||cpuis("MKL26Z128VMP4")||cpuis("MKL27Z128VMP4")||cpuis("MKL27Z256VMP4")||cpuis("MKL27Z128VLH4")||cpuis("MKL27Z256VLH4")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "CMP0_IN0,PTC6/LLWU_P10,SPI0_MOSI,EXTRG_IN,I2S0_RX_BCLK,SPI0_MISO,I2S0_MCLK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "CMP0_IN0,PTC6/LLWU_P10,SPI0_MOSI,EXTRG_IN,,SPI0_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_C_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL26Z32VLH4")||(cpu()=="MKL26Z64VLH4")||(cpu()=="MKL26Z128VLH4")||(cpu()=="MKL26Z256VLH4")||cpuis("MKL26Z128VMP4")||cpuis("MKL27Z128VMP4")||cpuis("MKL27Z256VMP4")||cpuis("MKL27Z128VLH4")||cpuis("MKL27Z256VLH4")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,SPI0_MISO,Audiousb_sof_out,I2S0_RX_FS,SPI0_MOSI,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z32VMP4")||cpuis("MKL27Z64VMP4")||cpuis("MKL27Z32VLH4")||cpuis("MKL27Z64VLH4")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,SPI0_MISO,Audiousb_sof_out,,SPI0_MOSI,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,SPI0_MISO,,,SPI0_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x20 "PORT_C_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x20 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL26Z32VLH4")||(cpu()=="MKL26Z64VLH4")||(cpu()=="MKL26Z128VLH4")||(cpu()=="MKL26Z256VLH4")||cpuis("MKL26Z128VMP4")||cpuis("MKL27Z128VMP4")||cpuis("MKL27Z256VMP4")||cpuis("MKL27Z128VLH4")||cpuis("MKL27Z256VLH4")
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "CMP0_IN2,PTC8,I2C0_SCL,TPM0_CH4,I2S0_MCLK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "CMP0_IN2,PTC8,I2C0_SCL,TPM0_CH4,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x20 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x20 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x20 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x24 "PORT_C_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x24 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL26Z32VLH4")||(cpu()=="MKL26Z64VLH4")||(cpu()=="MKL26Z128VLH4")||(cpu()=="MKL26Z256VLH4")||cpuis("MKL26Z128VMP4")||cpuis("MKL27Z128VMP4")||cpuis("MKL27Z256VMP4")||cpuis("MKL27Z128VLH4")||cpuis("MKL27Z256VLH4")
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "CMP0_IN3,PTC9,I2C0_SDA,TPM0_CH5,I2S0_RX_BCLK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "CMP0_IN3,PTC9,I2C0_SDA,TPM0_CH5,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x24 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x24 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x24 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x28 "PORT_C_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x28 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x28 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL26Z32VLH4")||(cpu()=="MKL26Z64VLH4")||(cpu()=="MKL26Z128VLH4")||(cpu()=="MKL26Z256VLH4")||cpuis("MKL26Z128VMP4")||cpuis("MKL27Z128VMP4")||cpuis("MKL27Z256VMP4")||cpuis("MKL27Z128VLH4")||cpuis("MKL27Z256VLH4")
|
|
bitfld.long 0x28 8.--10. " MUX ,Pin mux control" "Disabled,PTC10,I2C1_SCL,,I2S0_RX_FS,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x28 8.--10. " MUX ,Pin mux control" "Disabled,PTC10,I2C1_SCL,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x28 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x28 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x28 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x2C "PORT_C_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x2C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL26Z32VLH4")||(cpu()=="MKL26Z64VLH4")||(cpu()=="MKL26Z128VLH4")||(cpu()=="MKL26Z256VLH4")||cpuis("MKL26Z128VMP4")||cpuis("MKL27Z128VMP4")||cpuis("MKL27Z256VMP4")||cpuis("MKL27Z128VLH4")||cpuis("MKL27Z256VLH4")
|
|
bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" "Disabled,PTC11,I2C1_SDA,,I2S0_RXD0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" "Disabled,PTC11,I2C1_SDA,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x2C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x2C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x2C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x2080++0x03
|
|
line.long 0x00 "PORT_C_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x2084++0x03
|
|
hide.long 0x00 "PORT_C_GPCHR,Global Pin Control High Register"
|
|
group.long 0x20A0++0x03
|
|
line.long 0x00 "PORT_C_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_D"
|
|
tree "Pin Control Registers"
|
|
group.long 0x3000++0x1F
|
|
line.long 0x00 "PORT_D_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL27Z128VMP4")||cpuis("MKL27Z256VMP4")||cpuis("MKL27Z128VLH4")||cpuis("MKL27Z256VLH4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTD0,SPI0_SS,,TPM0_CH0,,FXIO0_D0,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z32VMP4")||cpuis("MKL27Z64VMP4")||cpuis("MKL27Z32VLH4")||cpuis("MKL27Z64VLH4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTD0,SPI0_PCS0,,TPM0_CH0,,FXIO0_D0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTD0,SPI0_PCS0,,TPM0_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_D_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL27Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_se5b,PTD1,SPI0_SCK,,TPM0_CH1,,FXIO0_D1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_se5b,PTD1,SPI0_SCK,,TPM0_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_D_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL27Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTD2,SPI0_MOSI,UART2_RX,TPM0_CH2,SPI0_MISO,FXIO0_D2,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTD2,SPI0_MOSI,UART2_RX,TPM0_CH2,SPI0_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_D_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL27Z*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTD3,SPI0_MISO,UART2_TX,TPM0_CH3,SPI0_MOSI,FXIO0_D3,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTD3,SPI0_MISO,UART2_TX,TPM0_CH3,SPI0_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_D_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL27Z32VMP4")||cpuis("MKL27Z64VMP4")||cpuis("MKL27Z32VLH4")||cpuis("MKL27Z64VLH4")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTD4/LLWU_P14,SPI1_PCS0,UART2_RX,TPM0_CH4,,FXIO0_D4,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z128VMP4")||cpuis("MKL27Z256VMP4")||cpuis("MKL27Z128VLH4")||cpuis("MKL27Z256VLH4")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTD4/LLWU_P14,SPI1_SS,UART2_RX,TPM0_CH4,,FXIO0_D4,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTD4/LLWU_P14,SPI1_PCS0,UART2_RX,TPM0_CH4,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_D_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL27Z*")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Adc0_se6b,PTD5,SPI1_SCK,UART2_TX,TPM0_CH5,,FXIO0_D5,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Adc0_se6b,PTD5,SPI1_SCK,UART2_TX,TPM0_CH5,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_D_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL27Z32VMP4")||cpuis("MKL27Z64VMP4")||cpuis("MKL27Z32VLH4")||cpuis("MKL27Z64VLH4")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,UART0_RX,I2C1_SDA,SPI1_MISO,FXIO0_D6,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z128VMP4")||cpuis("MKL27Z256VMP4")||cpuis("MKL27Z128VLH4")||cpuis("MKL27Z256VLH4")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,UART0_RX,,SPI1_MISO,FXIO0_D6,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,UART0_RX,,SPI1_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_D_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL27Z32VMP4")||cpuis("MKL27Z64VMP4")||cpuis("MKL27Z32VLH4")||cpuis("MKL27Z64VLH4")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "Disabled,PTD7,SPI1_MISO,UART0_TX,I2C0_SCL,SPI1_MOSI,FXIO0_D7,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z128VMP4")||cpuis("MKL27Z256VMP4")||cpuis("MKL27Z128VLH4")||cpuis("MKL27Z256VLH4")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "Disabled,PTD7,SPI1_MISO,UART0_TX,,SPI1_MOSI,FXIO0_D7,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "Disabled,PTD7,SPI1_MISO,UART0_TX,,SPI1_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x3080++0x03
|
|
line.long 0x00 "PORT_D_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x3084++0x03
|
|
hide.long 0x00 "PORT_D_GPCHR,Global Pin Control High Register"
|
|
group.long 0x30A0++0x03
|
|
line.long 0x00 "PORT_D_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_E"
|
|
tree "Pin Control Registers"
|
|
group.long 0x4000++0x07
|
|
line.long 0x00 "PORT_E_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL26Z32VLH4")||(cpu()=="MKL26Z64VLH4")||(cpu()=="MKL26Z128VLH4")||(cpu()=="MKL26Z256VLH4")||cpuis("MKL26Z128VMP4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTE0,SPI1_MISO,UART1_TX,RTC_CLKOUT,CMP0_OUT,I2C1_SDA,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTE0,SPI1_MISO,LPUART1_TX,RTC_CLKOUT,CMP0_OUT,I2C1_SDA,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTE0,,UART1_TX,RTC_CLKOUT,CMP0_OUT,I2C1_SDA,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL27Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTE1,SPI1_MOSI,LPUART1_RX,,SPI1_MISO,I2C1_SCL,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTE1,SPI1_MOSI,UART1_RX,,SPI1_MISO,I2C1_SCL,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
sif cpuis("MKL27Z32VMP4")||cpuis("MKL27Z64VMP4")||cpuis("MKL27Z32VLH4")||cpuis("MKL27Z64VLH4")
|
|
group.long 0x4040++0x03
|
|
line.long 0x00 "PORT_E_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_DP1/ADC0_SE1,PTE16,SPI0_PCS0,LPUART2_TX,TPM_CLKIN0,,FXIO0_D0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
endif
|
|
group.long 0x4050++0x17
|
|
line.long 0x00 "PORT_E_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLH4")||(cpu()=="MKL24Z32VLH4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE0,PTE20,,TPM1_CH0,UART0_TX,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_DP0/ADC0_SE0,PTE20,,TPM1_CH0,LPUART0_TX,,FXIO0_D4,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_DP0/ADC0_SE0,PTE20,,TPM1_CH0,UART0_TX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR21,Pin Control Register 21"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLH4")||(cpu()=="MKL24Z32VLH4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_se4a,PTE21,,TPM1_CH1,UART0_RX,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_dm0/adc0_se4a,PTE21,,TPM1_CH1,LPUART0_RX,,FXIO0_D5,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_dm0/adc0_se4a,PTE21,,TPM1_CH1,UART0_RX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR22,Pin Control Register 22"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLH4")||(cpu()=="MKL24Z32VLH4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE3,PTE22,,TPM2_CH0,UART2_TX,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_DP3/ADC0_SE3,PTE22,,TPM2_CH0,UART2_TX,,FXIO0_D6,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_DP3/ADC0_SE3,PTE22,,TPM2_CH0,UART2_TX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_E_PCR23,Pin Control Register 23"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLH4")||(cpu()=="MKL24Z32VLH4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_se7a,PTE23,,TPM2_CH1,UART2_RX,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_dm3/adc0_se7a,PTE23,,TPM2_CH1,UART2_RX,,FXIO0_D7,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_dm3/adc0_se7a,PTE23,,TPM2_CH1,UART2_RX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_E_PCR24,Pin Control Register 24"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTE24,,TPM0_CH0,,I2C0_SCL,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_E_PCR25,Pin Control Register 25"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTE25,,TPM0_CH1,,I2C0_SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4074++0x0B
|
|
line.long 0x00 "PORT_E_PCR29,Pin Control Register 29"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Cmp0_in5/adc0_se4b,PTE29,,TPM0_CH2,TPM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR30,Pin Control Register 30"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLH4")||(cpu()=="MKL24Z32VLH4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,?..."
|
|
textline " "
|
|
elif cpuis("MKL27Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,LPUART1_TX,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DAC0_OUT/ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR31,Pin Control Register 31"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTE31,,TPM0_CH4,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x4080++0x07
|
|
line.long 0x00 "PORT_E_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_E_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 31. " GPWE31 ,Global pin 31 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 30. " GPWE30 ,Global pin 30 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 29. " GPWE29 ,Global pin 29 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 25. " GPWE25 ,Global pin 25 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 24. " GPWE24 ,Global pin 24 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 23. " GPWE23 ,Global pin 23 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 22. " GPWE22 ,Global pin 22 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 21. " GPWE21 ,Global pin 21 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
sif cpuis("MKL27Z32VMP4")||cpuis("MKL27Z64VMP4")||cpuis("MKL27Z32VLH4")||cpuis("MKL27Z64VLH4")
|
|
textline " "
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x40A0++0x03
|
|
line.long 0x00 "PORT_E_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 31. " ISF31 ,Interrupt status flag 31 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " ISF30 ,Interrupt status flag 30 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 29. " ISF29 ,Interrupt status flag 29 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " ISF25 ,Interrupt status flag 25 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " ISF24 ,Interrupt status flag 24 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 23. " ISF23 ,Interrupt status flag 23 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 22. " ISF22 ,Interrupt status flag 22 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " ISF21 ,Interrupt status flag 21 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
sif cpuis("MKL27Z32VMP4")||cpuis("MKL27Z64VMP4")||cpuis("MKL27Z32VLH4")||cpuis("MKL27Z64VLH4")
|
|
textline " "
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
else
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL2*VLK*")
|
|
width 14.
|
|
tree "PORT_A"
|
|
tree "Pin Control Registers"
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "PORT_A_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLK4")||(cpu()=="MKL24Z32VLK4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DISABLED,PTA0,,TPM0_CH5,,,,SWD_CLK"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH1,PTA0,,TPM0_CH5,,,,SWD_CLK"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLK4")||(cpu()=="MKL24Z32VLK4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA1,UART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH2,PTA1,UART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLK4")||(cpu()=="MKL24Z32VLK4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA2,UART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "TSI0_CH3,PTA2,UART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLK4")||(cpu()=="MKL24Z32VLK4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTA3,I2C1_SCL,TPM0_CH0,,,,SWD_DIO"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "TSI0_CH4,PTA3,I2C1_SCL,TPM0_CH0,,,,SWD_DIO"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLK4")||(cpu()=="MKL24Z32VLK4")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTA4,I2C1_SDA,TPM0_CH1,,,,Nmi_b"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "TSI0_CH5,PTA4,I2C1_SDA,TPM0_CH1,,,,Nmi_b"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_A_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA5,USB_CLKIN,TPM0_CH2,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x30++0x23
|
|
line.long 0x00 "PORT_A_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTA12,,TPM1_CH0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA13,,TPM1_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR14,Pin Control Register 14"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA14,SPI0_PCS0,UART0_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR15,Pin Control Register 15"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTA15,SPI0_SCK,UART0_RX,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTA16,SPI0_MOSI,,,SPI0_MISO,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_A_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA17,SPI0_MISO,,,SPI0_MOSI,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_A_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,UART1_RX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_A_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,,UART1_TX,TPM_CLKIN1,,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x20 "PORT_A_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x20 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "Disabled,PTA20,?..."
|
|
textline " "
|
|
bitfld.long 0x20 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x20 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x20 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x80++0x07
|
|
line.long 0x00 "PORT_A_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 31. " GPWE15 ,Global pin 15 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 30. " GPWE14 ,Global pin 14 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 29. " GPWE13 ,Global pin 13 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GPWE12 ,Global pin 12 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_A_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORT_A_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 15. " ISF15 ,Interrupt status flag 15 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 14. " ISF14 ,Interrupt status flag 14 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " ISF13 ,Interrupt status flag 13 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " ISF12 ,Interrupt status flag 12 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_B"
|
|
tree "Pin Control Registers"
|
|
group.long 0x1000++0x0F
|
|
line.long 0x00 "PORT_B_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLK4")||(cpu()=="MKL24Z32VLK4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8/TSI0_CH0,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLK4")||(cpu()=="MKL24Z32VLK4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9,PTB1,I2C0_SDA,TPM1_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9/TSI0_CH6,PTB1,I2C0_SDA,TPM1_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLK4")||(cpu()=="MKL24Z32VLK4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE12,PTB2,I2C0_SCL,TPM2_CH0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE12/TSI0_CH7,PTB2,I2C0_SCL,TPM2_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLK4")||(cpu()=="MKL24Z32VLK4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_SE13,PTB3,I2C0_SDA,TPM2_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_SE13/TSI0_CH8,PTB3,I2C0_SDA,TPM2_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x1020++0x0F
|
|
line.long 0x00 "PORT_B_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DISABLED,PTB8,,EXTRG_IN,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DISABLED,PTB9,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "DISABLED,PTB10,SPI1_PCS0,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "DISABLED,PTB11,SPI1_SCK,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x1040++0x0F
|
|
line.long 0x00 "PORT_B_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLK4")||(cpu()=="MKL24Z32VLK4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DISABLED,PTB16,SPI1_MOSI,UART0_RX,TPM_CLKIN0,SPI1_MISO,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH9,PTB16,SPI1_MOSI,UART0_RX,TPM_CLKIN0,SPI1_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLK4")||(cpu()=="MKL24Z32VLK4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DISABLED,PTB17,SPI1_MISO,UART0_TX,TPM_CLKIN1,SPI1_MOSI,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH10,PTB17,SPI1_MISO,UART0_TX,TPM_CLKIN1,SPI1_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLK4")||(cpu()=="MKL24Z32VLK4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "DISABLED,PTB18,,TPM2_CH0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "TSI0_CH11,PTB18,,TPM2_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLK4")||(cpu()=="MKL24Z32VLK4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "DISABLED,PTB19,,TPM2_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "TSI0_CH12,PTB19,,TPM2_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x1080++0x07
|
|
line.long 0x00 "PORT_B_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_B_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "PORT_B_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_C"
|
|
tree "Pin Control Registers"
|
|
group.long 0x2000++0x37
|
|
line.long 0x00 "PORT_C_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLK4")||(cpu()=="MKL24Z32VLK4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE14,PTC0,,EXTRG_IN,,CMP0_OUT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE14/TSI0_CH13,PTC0,,EXTRG_IN,,CMP0_OUT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_C_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLK4")||(cpu()=="MKL24Z32VLK4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE15,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE15/TSI0_CH14,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_C_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLK4")||(cpu()=="MKL24Z32VLK4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE11,PTC2,I2C1_SDA,,TPM0_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE11/TSI0_CH15,PTC2,I2C1_SDA,,TPM0_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_C_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "DISABLED,PTC3/LLWU_P7,,UART1_RX,TPM0_CH2,CLKOUT,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_C_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "DISABLED,PTC4/LLWU_P8,SPI0_PCS0,UART1_TX,TPM0_CH3,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_C_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "DISABLED,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,,,CMP0_OUT,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_C_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "CMP0_IN0,PTC6/LLWU_P10,SPI0_MOSI,EXTRG_IN,,SPI0_MISO,?..."
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_C_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,SPI0_MISO,,,SPI0_MOSI,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x20 "PORT_C_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x20 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "CMP0_IN2,PTC8,I2C0_SCL,TPM0_CH4,?..."
|
|
textline " "
|
|
bitfld.long 0x20 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x20 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x20 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x24 "PORT_C_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x24 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "CMP0_IN3,PTC9,I2C0_SDA,TPM0_CH5,?..."
|
|
textline " "
|
|
bitfld.long 0x24 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x24 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x24 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x28 "PORT_C_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x28 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x28 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x28 8.--10. " MUX ,Pin mux control" "DISABLED,PTC10,I2C1_SCL,?..."
|
|
textline " "
|
|
bitfld.long 0x28 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x28 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x28 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x2C "PORT_C_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x2C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" "DISABLED,PTC11,I2C1_SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x2C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x2C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x2C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x30 "PORT_C_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x30 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x30 8.--10. " MUX ,Pin mux control" "DISABLED,PTC12,,,TPM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x30 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x30 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x30 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x30 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x30 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x34 "PORT_A_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x34 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x34 8.--10. " MUX ,Pin mux control" "DISABLED,PTC13,,,TPM_CLKIN1,?..."
|
|
textline " "
|
|
bitfld.long 0x34 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x34 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x34 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x34 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x34 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x2040++0x07
|
|
line.long 0x00 "PORT_A_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DISABLED,PTC16,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DISABLED,PTC17,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x2080++0x07
|
|
line.long 0x00 "PORT_C_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 29. " GPWE13 ,Global pin 13 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 28. " GPWE12 ,Global pin 12 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_C_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x20A0++0x03
|
|
line.long 0x00 "PORT_C_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " ISF13 ,Interrupt status flag 13 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 12. " ISF12 ,Interrupt status flag 12 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_D"
|
|
tree "Pin Control Registers"
|
|
group.long 0x3000++0x1F
|
|
line.long 0x00 "PORT_D_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DISABLED,PTD0,SPI0_PCS0,,TPM0_CH0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_D_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_se5b,PTD1,SPI0_SCK,,TPM0_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_D_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "DISABLED,PTD2,SPI0_MOSI,UART2_RX,TPM0_CH2,SPI0_MISO,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_D_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "DISABLED,PTD3,SPI0_MISO,UART2_TX,TPM0_CH3,SPI0_MOSI,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_D_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "DISABLED,PTD4/LLWU_P14,SPI1_PCS0,UART2_RX,TPM0_CH4,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_D_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Adc0_se6b,PTD5,SPI1_SCK,UART2_TX,TPM0_CH5,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_D_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,UART0_RX,,SPI1_MISO,?..."
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_D_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "DISABLED,PTD7,SPI1_MISO,UART0_TX,,SPI1_MOSI,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x3080++0x03
|
|
line.long 0x00 "PORT_D_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x3084++0x03
|
|
hide.long 0x00 "PORT_D_GPCHR,Global Pin Control High Register"
|
|
group.long 0x30A0++0x03
|
|
line.long 0x00 "PORT_D_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_E"
|
|
tree "Pin Control Registers"
|
|
group.long 0x4000++0x17
|
|
line.long 0x00 "PORT_E_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DISABLED,PTE0,,UART1_TX,RTC_CLKOUT,CMP0_OUT,I2C1_SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DISABLED,PTE1,SPI1_MOSI,UART1_RX,,SPI1_MISO,I2C1_SCL,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "DISABLED,PTE2,SPI1_SCK,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_E_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "DISABLED,PTE3,SPI1_MISO,,,SPI1_MOSI,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_E_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "DISABLED,PTE4,SPI1_PCS0,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_E_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "DISABLED,PTE5,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4050++0x17
|
|
line.long 0x00 "PORT_E_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLK4")||(cpu()=="MKL24Z32VLK4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE0,PTE20,,TPM1_CH0,UART0_TX,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_DP0/ADC0_SE0,PTE20,,TPM1_CH0,UART0_TX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR21,Pin Control Register 21"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLK4")||(cpu()=="MKL24Z32VLK4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_se4a,PTE21,,TPM1_CH1,UART0_RX,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_dm0/adc0_se4a,PTE21,,TPM1_CH1,UART0_RX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR22,Pin Control Register 22"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLK4")||(cpu()=="MKL24Z32VLK4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE3,PTE22,,TPM2_CH0,UART2_TX,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_DP3/ADC0_SE3,PTE22,,TPM2_CH0,UART2_TX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_E_PCR23,Pin Control Register 23"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLK4")||(cpu()=="MKL24Z32VLK4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_se7a,PTE23,,TPM2_CH1,UART2_RX,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_dm3/adc0_se7a,PTE23,,TPM2_CH1,UART2_RX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_E_PCR24,Pin Control Register 24"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "DISABLED,PTE24,,TPM0_CH0,,I2C0_SCL,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_E_PCR25,Pin Control Register 25"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "DISABLED,PTE25,,TPM0_CH1,,I2C0_SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4074++0x0B
|
|
line.long 0x00 "PORT_E_PCR29,Pin Control Register 29"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Cmp0_in5/adc0_se4b,PTE29,,TPM0_CH2,TPM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR30,Pin Control Register 30"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL24Z64VLK4")||(cpu()=="MKL24Z32VLK4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DAC0_OUT/ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR31,Pin Control Register 31"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "DISABLED,PTE31,,TPM0_CH4,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x4080++0x07
|
|
line.long 0x00 "PORT_E_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_E_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 31. " GPWE31 ,Global pin 31 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 30. " GPWE30 ,Global pin 30 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 29. " GPWE29 ,Global pin 29 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 25. " GPWE25 ,Global pin 25 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 24. " GPWE24 ,Global pin 24 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 23. " GPWE23 ,Global pin 23 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 22. " GPWE22 ,Global pin 22 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 21. " GPWE21 ,Global pin 21 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x40A0++0x03
|
|
line.long 0x00 "PORT_E_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 31. " ISF31 ,Interrupt status flag 31 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " ISF30 ,Interrupt status flag 30 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 29. " ISF29 ,Interrupt status flag 29 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " ISF25 ,Interrupt status flag 25 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " ISF24 ,Interrupt status flag 24 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 23. " ISF23 ,Interrupt status flag 23 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 22. " ISF22 ,Interrupt status flag 22 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " ISF21 ,Interrupt status flag 21 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL2*VLL*")||cpuis("MKL2*VMC*")||cpuis("MKL2*VDC*")
|
|
width 14.
|
|
tree "PORT_A"
|
|
tree "Pin Control Registers"
|
|
group.long 0x00++0x1F
|
|
line.long 0x00 "PORT_A_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH1,PTA0,LPUART0_CTS_b,TPM0_CH5,,LPI2C0_SDAS,,SWD_CLK"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH1,PTA0,,TPM0_CH5,,,,SWD_CLK"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH2,PTA1,LPUART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH2,PTA1,UART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "TSI0_CH3,PTA2,LPUART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "TSI0_CH3,PTA2,UART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "TSI0_CH4,PTA3,LPI2C1_SCL,TPM0_CH0,LPUART0_RTS_b,,,SWD_DIO"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "TSI0_CH4,PTA3,I2C1_SCL,TPM0_CH0,,,,SWD_DIO"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "TSI0_CH5,PTA4/LLWU_P3,LPI2C1_SDA,TPM0_CH1,,,,Nmi_b"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "TSI0_CH5,PTA4,I2C1_SDA,TPM0_CH1,,,,Nmi_b"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_A_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA5,USB_CLKIN,TPM0_CH2,,LPI2C2_HREQ,I2S0_TX_BCLK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA5,USB_CLKIN,TPM0_CH2,,,I2S0_TX_BCLK,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_A_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Disabled,PTA6,,TPM0_CH3,?..."
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_A_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "Disabled,PTA7,LPSPI0_PCS3,TPM0_CH4,,LPI2C2_SDAS,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "Disabled,PTA7,,TPM0_CH4,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
sif cpuis("MKL28Z512VDC7")
|
|
group.long 0x28++0x7
|
|
line.long 0x00 "PORT_A_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTA10/LLWU_P22,LPSPI0_PCS2,TPM2_CH0,,LPI2C2_SCLS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA11/LLWU_P23,LPSPI0_PCS1,TPM2_CH1,,LPI2C2_SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
endif
|
|
group.long 0x30++0x17
|
|
line.long 0x00 "PORT_A_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTA12,,TPM1_CH0,,LPI2C2_SCL,I2S0_TXD0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTA12,,TPM1_CH0,,,I2S0_TXD0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA13/LLWU_P4,,TPM1_CH1,,LPI2C2_SDA,I2S0_TX_FS,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA13,,TPM1_CH1,,,I2S0_TX_FS,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR14,Pin Control Register 14"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA14,LPSPI0_PCS0,LPUART0_TX,,LPI2C2_SCL,I2S0_RX_BCLK,I2S0_TXD0"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA14,SPI0_PCS0,UART0_TX,,,I2S0_RX_BCLK,I2S0_TXD0"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR15,Pin Control Register 15"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTA15,LPSPI0_SCK,LPUART0_RX,,,I2S0_RXD0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTA15,SPI0_SCK,UART0_RX,,,I2S0_RXD0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTA16,LPSPI0_SOUT,LPUART0_CTS_b,,,I2S0_RX_FS,I2S0_RXD0"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTA16,SPI0_MOSI,,,SPI0_MISO,I2S0_RX_FS,I2S0_RXD0"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_A_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "ADC0_SE22,PTA17,LPSPI0_SIN,LPUART0_RTS_b,,,I2S0_MCLK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA17,SPI0_MISO,,,SPI0_MOSI,I2S0_MCLK,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x48++0x0B
|
|
line.long 0x00 "PORT_A_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,LPUART1_RX,TPM0_CLKIN,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,UART1_RX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,,LPUART1_TX,TPM1_CLKIN,,LPTMR0_ALT1/LPTMR1_ALT1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,,UART1_TX,TPM_CLKIN1,,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA20,LPI2C0_SCLS,,TPM2_CLKIN,,,Reset_b"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA20,,,,,,Reset_b"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x80++0x07
|
|
line.long 0x00 "PORT_A_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 31. " GPWE15 ,Global pin 15 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 30. " GPWE14 ,Global pin 14 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 29. " GPWE13 ,Global pin 13 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GPWE12 ,Global pin 12 write enable" "Disable,Enable"
|
|
sif cpuis("MKL28Z512VDC7")
|
|
bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_A_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORT_A_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 15. " ISF15 ,Interrupt status flag 15 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 14. " ISF14 ,Interrupt status flag 14 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " ISF13 ,Interrupt status flag 13 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " ISF12 ,Interrupt status flag 12 (in digital modes only)" "No interrupt,Interrupt"
|
|
sif cpuis("MKL28Z512VDC7")
|
|
eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10 (in digital modes only)" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_B"
|
|
tree "Pin Control Registers"
|
|
group.long 0x1000++0x0F
|
|
line.long 0x00 "PORT_B_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8/TSI0_CH0,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,,,FXIO0_D8,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8/TSI0_CH0,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9/TSI0_CH6,PTB1,LPI2C0_SDA,TPM1_CH1,,,FXIO0_D9,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9/TSI0_CH6,PTB1,I2C0_SDA,TPM1_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE12/TSI0_CH7,PTB2,LPI2C0_SCL,TPM2_CH0,,LPUART0_RTS_b,FXIO0_D10,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE12/TSI0_CH7,PTB2,I2C0_SCL,TPM2_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_SE13/TSI0_CH8,PTB3,LPI2C0_SDA,TPM2_CH1,LPSPI1_PCS3,LPUART0_CTS_b,FXIO0_D11,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_SE13/TSI0_CH8,PTB3,I2C0_SDA,TPM2_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
sif cpuis("MKL28Z512VDC7")
|
|
group.long 0x1018++0x03
|
|
line.long 0x00 "PORT_B_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DISABLED,PTB6,LPSPI1_PCS2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
endif
|
|
group.long 0x101C++0x13
|
|
line.long 0x00 "PORT_B_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTB7,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTB7,LPSPI1_PCS1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTB8,LPSPI1_PCS0,,,,FXIO0_D12,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTB8,SPI1_PCS0,EXTRG_IN,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTB9,LPSPI1_SCK,,,,FXIO0_D13,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTB9,SPI1_SCK,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTB10,LPSPI1_PCS0,,,,FXIO0_D14,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTB10,SPI1_PCS0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_B_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTB11,LPSPI1_SCK,,TPM2_CLKIN,,FXIO0_D15,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTB11,SPI1_SCK,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x1040++0x1F
|
|
line.long 0x00 "PORT_B_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH9,PTB16,LPSPI1_SOUT,LPUART0_RX,TPM0_CLKIN,LPSPI2_PCS3,FXIO0_D16,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH9,PTB16,SPI1_MOSI,UART0_RX,TPM_CLKIN0,SPI1_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH10,PTB17,LPSPI1_SIN,LPUART0_TX,TPM1_CLKIN,LPSPI2_PCS2,FXIO0_D17,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH10,PTB17,SPI1_MISO,UART0_TX,TPM_CLKIN1,SPI1_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "TSI0_CH11,PTB18,,TPM2_CH0,I2S0_TX_BCLK,LPI2C1_HREQ,FXIO0_D18,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "TSI0_CH11,PTB18,,TPM2_CH0,I2S0_TX_BCLK,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "TSI0_CH12,PTB19,,TPM2_CH1,I2S0_TX_FS,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "TSI0_CH12,PTB19,,TPM2_CH1,I2S0_TX_FS,LPSPI2_PCS1,FXIO0_D19,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_B_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTB20,LPSPI2_PCS0,,,,CMP0_OUT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTB20,,,,,CMP0_OUT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_B_PCR21,Pin Control Register 21"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTB21,LPSPI2_SCK,,,,CMP1_OUT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTB21,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_B_PCR22,Pin Control Register 22"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Disabled,PTB22,LPSPI2_SOUT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Disabled,PTB22,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_B_PCR23,Pin Control Register 23"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "Disabled,PTB23,LPSPI2_SIN,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "Disabled,PTB23,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x1080++0x07
|
|
line.long 0x00 "PORT_B_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
textline " "
|
|
sif cpuis("MKL28Z512VDC7")
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_B_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 23. " GPWE23 ,Global pin 23 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 22. " GPWE22 ,Global pin 22 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 21. " GPWE21 ,Global pin 21 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "PORT_B_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 23. " ISF1 ,Interrupt status flag 23 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " ISF1 ,Interrupt status flag 22 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " ISF1 ,Interrupt status flag 21 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 20. " ISF1 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
sif cpuis("MKL28Z512VDC7")
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
endif
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_C"
|
|
tree "Pin Control Registers"
|
|
group.long 0x2000++0x37
|
|
line.long 0x00 "PORT_C_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE14/TSI0_CH13,PTC0,LPSPI2_PCS1,,USB_SOF_OUT,CMP0_OUT,I2S0_TXD0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE14/TSI0_CH13,PTC0,,EXTRG_IN,Audiousb_sof_out,CMP0_OUT,I2S0_TXD0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_C_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE15/TSI0_CH14,PTC1/LLWU_P6,LPI2C1_SCL,LPUART1_RTS_b,TPM0_CH0,,I2S0_TXD0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE15/TSI0_CH14,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,,I2S0_TXD0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_C_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE11/CMP1_IN0/TSI0_CH15,PTC2,I2C1_SDA,,TPM0_CH1,,I2S0_TX_FS,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE11/TSI0_CH15,PTC2,LPI2C1_SDA,LPUART1_CTS_b,TPM0_CH1,,I2S0_TX_FS,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_C_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "CMP1_IN1,PTC3/LLWU_P7,CMP1_IN1,CMP1_IN1,TPM0_CH2,CLKOUT,I2S0_TX_BCLK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "DISABLED,PTC3/LLWU_P7,,UART1_RX,TPM0_CH2,CLKOUT,I2S0_TX_BCLK,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_C_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "DISABLED,PTC4/LLWU_P8,LPSPI0_PCS0,LPUART1_TX,TPM0_CH3,I2S0_MCLK,CMP1_OUT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "DISABLED,PTC4/LLWU_P8,SPI0_PCS0,UART1_TX,TPM0_CH3,I2S0_MCLK,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_C_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "DISABLED,PTC5/LLWU_P9,LPSPI0_SCK,LPTMR0_ALT2/LPTMR1_ALT2,I2S0_RXD0,,CMP0_OUT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "DISABLED,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,I2S0_RXD0,,CMP0_OUT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_C_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "CMP0_IN0,PTC6/LLWU_P10,LPSPI0_SOUT,,I2S0_RX_BCLK,,I2S0_MCLK,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "CMP0_IN0,PTC6/LLWU_P10,SPI0_MOSI,EXTRG_IN,I2S0_RX_BCLK,SPI0_MISO,I2S0_MCLK,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_C_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,LPSPI0_SIN,USB_SOF_OUT,I2S0_RX_FS,,FXIO0_D20,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,SPI0_MISO,Audiousb_sof_out,I2S0_RX_FS,SPI0_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x20 "PORT_C_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x20 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "CMP0_IN2,PTC8,LPI2C0_SCL,TPM0_CH4,I2S0_MCLK,,LPI2C0_SCL,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "CMP0_IN2,PTC8,I2C0_SCL,TPM0_CH4,I2S0_MCLK,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x20 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x20 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x20 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x24 "PORT_C_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x24 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "CMP0_IN3,PTC9,LPI2C0_SDA,TPM0_CH5,I2S0_RX_BCLK,,FXIO0_D22,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "CMP0_IN3,PTC9,I2C0_SDA,TPM0_CH5,I2S0_RX_BCLK,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x24 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x24 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x24 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x28 "PORT_C_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x28 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x28 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x28 8.--10. " MUX ,Pin mux control" "DISABLED,PTC10,LPI2C1_SCL,,I2S0_RX_FS,,FXIO0_D23,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x28 8.--10. " MUX ,Pin mux control" "DISABLED,PTC10,I2C1_SCL,,I2S0_RX_FS,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x28 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x28 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x28 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x2C "PORT_C_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x2C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" "DISABLED,PTC11/LLWU_P11,LPI2C1_SDA,,I2S0_RXD0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" "DISABLED,PTC11,I2C1_SDA,,I2S0_RXD0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x2C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x2C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x2C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x30 "PORT_C_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x30 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x30 8.--10. " MUX ,Pin mux control" "DISABLED,PTC12,LPI2C1_SCLS,,TPM_CLKIN0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x30 8.--10. " MUX ,Pin mux control" "DISABLED,PTC12,,,TPM_CLKIN0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x30 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x30 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x30 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x30 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x30 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x34 "PORT_C_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x34 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x34 8.--10. " MUX ,Pin mux control" "DISABLED,PTC13,LPI2C1_SDAS,,TPM_CLKIN1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x34 8.--10. " MUX ,Pin mux control" "DISABLED,PTC13,,,TPM_CLKIN1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x34 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x34 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x34 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x34 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x34 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
sif cpuis("MKL28Z512V*")
|
|
group.long 0x2038++0x07
|
|
line.long 0x00 "PORT_C_PCR14,Pin Control Register 14"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DISABLED,PTC14,EMVSIM0_CLK,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_C_PCR15,Pin Control Register 15"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DISABLED,PTC15,EMVSIM0_RST,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
endif
|
|
group.long 0x2040++0x0B
|
|
line.long 0x00 "PORT_C_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DISABLED,PTC16,EMVSIM0_VCCEN,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DISABLED,PTC16,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_C_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DISABLED,PTC17,EMVSIM0_IO,LPSPI0_PCS3,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DISABLED,PTC17,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_C_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "DISABLED,PTC18,EMVSIM0_PD,LPSPI0_PCS2,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "DISABLED,PTC18,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
sif cpuis("MKL28Z512VDC7")
|
|
group.long 0x204C++0x03
|
|
line.long 0x00 "PORT_C_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DISABLED,PTC19,LPSPI0_PCS1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
endif
|
|
sif (cpu()=="MKL26Z128VMC4")||(cpu()=="MKL26Z256VMC4")
|
|
group.long 0x2050++0x0F
|
|
line.long 0x00 "PORT_C_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DISABLED,PTC20,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_C_PCR21,Pin Control Register 21"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DISABLED,PTC21,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_C_PCR22,Pin Control Register 22"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "DISABLED,PTC22,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_C_PCR23,Pin Control Register 23"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "DISABLED,PTC23,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
elif cpuis("MKL28Z512VDC7")
|
|
group.long 0x2058++0x07
|
|
line.long 0x00 "PORT_C_PCR22,Pin Control Register 22"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DISABLED,PTC22,LPSPI0_PCS3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_C_PCR23,Pin Control Register 23"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DISABLED,PTC23,LPSPI0_PCS3,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
endif
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x2080++0x07
|
|
line.long 0x00 "PORT_C_GPCLR,Global Pin Control Low Register"
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x00 31. " GPWE15 ,Global pin 15 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 30. " GPWE14 ,Global pin 14 write enable" "Disable,Enable"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 29. " GPWE13 ,Global pin 13 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 28. " GPWE12 ,Global pin 12 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_C_GPCHR,Global Pin Control High Register"
|
|
sif (cpu()=="MKL26Z128VMC4")||(cpu()=="MKL26Z256VMC4")
|
|
bitfld.long 0x04 23. " GPWE23 ,Global pin 23 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 22. " GPWE22 ,Global pin 22 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 21. " GPWE21 ,Global pin 21 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
elif cpuis("MKL28Z512VDC7")
|
|
bitfld.long 0x04 23. " GPWE23 ,Global pin 23 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 22. " GPWE22 ,Global pin 22 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
else
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x20A0++0x03
|
|
line.long 0x00 "PORT_C_ISFR,Interrupt Status Flag Register"
|
|
sif (cpu()=="MKL26Z128VMC4")||(cpu()=="MKL26Z256VMC4")
|
|
eventfld.long 0x00 23. " ISF23 ,Interrupt status flag 23 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " ISF22 ,Interrupt status flag 22 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " ISF21 ,Interrupt status flag 21 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
elif cpuis("MKL28Z512VDC7")
|
|
eventfld.long 0x00 23. " ISF23 ,Interrupt status flag 23 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " ISF22 ,Interrupt status flag 22 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
else
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " ISF13 ,Interrupt status flag 13 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " ISF12 ,Interrupt status flag 12 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_D"
|
|
tree "Pin Control Registers"
|
|
group.long 0x3000++0x1F
|
|
line.long 0x00 "PORT_D_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DISABLED,PTD0/LLWU_P12,LPSPI0_PCS0,LPUART2_RTS_b,TPM0_CH0,,FXIO0_D0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DISABLED,PTD0,SPI0_PCS0,,TPM0_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_D_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_se5b,PTD1,LPSPI0_SCK,LPUART2_CTS_b,TPM0_CH1,,FXIO0_D1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_se5b,PTD1,SPI0_SCK,,TPM0_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_D_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "DISABLED,PTD2/LLWU_P13,LPSPI0_SOUT,LPUART2_RX,TPM0_CH2,,FXIO0_D2,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "DISABLED,PTD2,SPI0_MOSI,UART2_RX,TPM0_CH2,SPI0_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_D_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "DISABLED,PTD3,LPSPI0_SIN,LPUART2_TX,TPM0_CH3,,FXIO0_D3,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "DISABLED,PTD3,SPI0_MISO,UART2_TX,TPM0_CH3,SPI0_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_D_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "DISABLED,PTD4/LLWU_P14,LPSPI1_PCS0,LPUART2_RX,TPM0_CH4,LPUART0_RTS_b,FXIO0_D4,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "DISABLED,PTD4/LLWU_P14,SPI1_PCS0,UART2_RX,TPM0_CH4,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_D_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Adc0_se6b,PTD5,LPSPI1_SCK,LPUART2_TX,TPM0_CH5,LPUART0_CTS_b,FXIO0_D5,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Adc0_se6b,PTD5,SPI1_SCK,UART2_TX,TPM0_CH5,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_D_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Adc0_se7b,PTD6/LLWU_P15,LPSPI1_SOUT,LPUART0_RX,,,FXIO0_D6,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,UART0_RX,,SPI1_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_D_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "DISABLED,PTD7,LPSPI1_SIN,LPUART0_TX,,,FXIO0_D7,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "DISABLED,PTD7,SPI1_MISO,UART0_TX,,SPI1_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
sif cpuis("MKL28Z512VDC7")
|
|
group.long 0x3020++0x1F
|
|
line.long 0x00 "PORT_D_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DISABLED,PTD8/LLWU_P24,LPI2C0_SCL,LPSPI1_PCS1,,,FXIO0_D24,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_D_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DISABLED,PTD9,LPI2C0_SDA,LPSPI2_PCS3,,,FXIO0_D25,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_D_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "DISABLED,PTD10,LPSPI2_PCS2,LPI2C0_SCLS,,FXIO0_D26,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_D_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "DISABLED,PTD11/LLWU_P25,LPSPI2_PCS0,LPI2C0_SDAS,,,FXIO0_D27,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_D_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "DISABLED,PTD12,LPSPI2_SCK,,,,FXIO0_D28,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_D_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "DISABLED,PTD13,LPSPI2_SOUT,,,,FXIO0_D29,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_D_PCR14,Pin Control Register 14"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "DISABLED,PTD14,LPSPI2_SIN,,,,FXIO0_D30,?..."
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_D_PCR15,Pin Control Register 15"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "DISABLED,PTD15,LPSPI2_PCS1,,,,FXIO0_D31,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
endif
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x3080++0x03
|
|
line.long 0x00 "PORT_D_GPCLR,Global Pin Control Low Register"
|
|
sif cpuis("MKL28Z512VDC7")
|
|
bitfld.long 0x00 31. " GPWE15 ,Global pin 15 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 30. " GPWE14 ,Global pin 14 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 29. " GPWE13 ,Global pin 13 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 28. " GPWE12 ,Global pin 12 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x3084++0x03
|
|
hide.long 0x00 "PORT_D_GPCHR,Global Pin Control High Register"
|
|
group.long 0x30A0++0x03
|
|
line.long 0x00 "PORT_D_ISFR,Interrupt Status Flag Register"
|
|
sif cpuis("MKL28Z512VDC7")
|
|
eventfld.long 0x00 15. " ISF15 ,Interrupt status flag 15 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " ISF14 ,Interrupt status flag 14 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " ISF13 ,Interrupt status flag 13 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 12. " ISF12 ,Interrupt status flag 12 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8 (in digital modes only)" "No interrupt,Interrupt"
|
|
endif
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_E"
|
|
tree "Pin Control Registers"
|
|
group.long 0x4000++0x1B
|
|
line.long 0x00 "PORT_E_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE16,PTE0/RTC_CLKOUT,LPSPI1_SIN,LPSPI1_SIN,,CMP0_OUT,LPI2C1_SDA,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DISABLED,PTE0,SPI1_MISO,UART1_TX,RTC_CLKOUT,CMP0_OUT,I2C1_SDA,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE17,PTE1/LLWU_P0,LPSPI1_SOUT,LPUART1_RX,,,LPI2C1_SCL,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DISABLED,PTE1,SPI1_MOSI,UART1_RX,,SPI1_MISO,I2C1_SCL,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE18,PTE2/LLWU_P1,LPSPI1_SCK,LPUART1_CTS_b,,,LPI2C1_SDAS,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "DISABLED,PTE2,SPI1_SCK,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_E_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_SE19,PTE3,LPSPI1_SIN,LPUART1_RTS_b,,,LPI2C1_SCLS,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "DISABLED,PTE3,SPI1_MISO,,,SPI1_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_E_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "DISABLED,PTE4/LLWU_P2,LPSPI1_PCS0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "DISABLED,PTE4,SPI1_PCS0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_E_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "DISABLED,PTE5,LPSPI1_PCS1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "DISABLED,PTE5,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_E_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "DISABLED,PTE6/LLWU_P16,LPSPI1_PCS2,,I2S0_MCLK,USB_SOF_OUT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "DISABLED,PTE6,,,I2S0_MCLK,Audiousb_sof_out,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4040++0x0F
|
|
line.long 0x00 "PORT_E_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_DP1/ADC0_SE1,PTE16,LPSPI0_PCS0,LPUART2_TX,TPM0_CLKIN,LPSPI1_PCS3,LPSPI1_PCS3,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_DP1/ADC0_SE1,PTE16,SPI0_PCS0,UART2_TX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_dm1/adc0_se5a,PTE17/LLWU_P19,LPSPI0_SCK,LPUART2_RX,TPM1_CLKIN,LPTMR0_ALT3/LPTMR1_ALT3,FXIO0_D1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_dm1/adc0_se5a,PTE17,SPI0_SCK,UART2_RX,TPM_CLKIN1,,LPTMR0_ALT3,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_DP2/ADC0_SE2,PTE18/LLWU_P20,LPSPI0_SOUT,LPUART2_CTS_b,LPI2C0_SDA,,FXIO0_D2,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Adc0_dp2/adc0_se2a,PTE18,SPI0_MOSI,,I2C0_SDA,SPI0_MISO,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_E_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_dm2/adc0_se6a,PTE19,LPSPI0_SIN,LPUART2_RTS_b,LPI2C0_SCL,,FXIO0_D3,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_dm2/adc0_se6a,PTE19,SPI0_MISO,,I2C0_SCL,SPI0_MOSI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4050++0x1B
|
|
line.long 0x00 "PORT_E_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_DP0/ADC0_SE0,PTE20,LPSPI2_SCK,TPM1_CH0,LPUART0_TX,,FXIO0_D4,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_DP0/ADC0_SE0,PTE20,,TPM1_CH0,UART0_TX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR21,Pin Control Register 21"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_dm0/adc0_se4a,PTE21,LPSPI2_SOUT,TPM1_CH1,LPUART0_RX,,FXIO0_D5,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_dm0/adc0_se4a,PTE21,,TPM1_CH1,UART0_RX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR22,Pin Control Register 22"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_DP3/ADC0_SE3,PTE22,LPSPI2_SIN,TPM2_CH0,LPUART2_TX,,FXIO0_D6,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_DP3/ADC0_SE3,PTE22,,TPM2_CH0,UART2_TX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_E_PCR23,Pin Control Register 23"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_dm3/adc0_se7a,PTE23,LPSPI2_PCS0,TPM2_CH1,LPUART2_RX,,FXIO0_D7,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_dm3/adc0_se7a,PTE23,,TPM2_CH1,UART2_RX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_E_PCR24,Pin Control Register 24"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "ADC0_SE20,PTE24,EMVSIM0_IO,TPM0_CH0,,LPI2C0_SCL,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "DISABLED,PTE24,,TPM0_CH0,,I2C0_SCL,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_E_PCR25,Pin Control Register 25"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "ADC0_SE21,PTE25/LLWU_P21,EMVSIM0_PD,TPM0_CH1,,LPI2C0_SDA,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "DISABLED,PTE25,,TPM0_CH1,,I2C0_SDA,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_E_PCR26,Pin Control Register 26"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "DISABLED,PTE26/RTC_CLKOUT,,TPM0_CH5,,LPI2C0_SCLS,,USB_CLKIN"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "DISABLED,PTE26,,TPM0_CH5,,,RTC_CLKOUT,USB_CLKIN"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4074++0x0B
|
|
line.long 0x00 "PORT_E_PCR29,Pin Control Register 29"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "CMP1_IN5/CMP0_IN5/ADC0_SE4b,PTE29,EMVSIM0_CLK,TPM0_CH2,TPM0_CLKIN,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Cmp0_in5/adc0_se4b,PTE29,,TPM0_CH2,TPM_CLKIN0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR30,Pin Control Register 30"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DAC0_OUT/CMP1_IN3/ADC0_SE23/CMP0_IN4,PTE30,EMVSIM0_RST,TPM0_CH3,TPM1_CLKIN,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DAC0_OUT/ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR31,Pin Control Register 31"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL28Z512V*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "DISABLED,PTE31,EMVSIM0_VCCEN,TPM0_CH4,TPM2_CLKIN,LPI2C0_HREQ,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "DISABLED,PTE31,,TPM0_CH4,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x4080++0x07
|
|
line.long 0x00 "PORT_E_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_E_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 31. " GPWE31 ,Global pin 31 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 30. " GPWE30 ,Global pin 30 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 29. " GPWE29 ,Global pin 29 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 26. " GPWE26 ,Global pin 26 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 25. " GPWE25 ,Global pin 25 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 24. " GPWE24 ,Global pin 24 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 23. " GPWE23 ,Global pin 23 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 22. " GPWE22 ,Global pin 22 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 21. " GPWE21 ,Global pin 21 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x40A0++0x03
|
|
line.long 0x00 "PORT_E_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 31. " ISF31 ,Interrupt status flag 31 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " ISF30 ,Interrupt status flag 30 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 29. " ISF29 ,Interrupt status flag 29 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 26. " ISF26 ,Interrupt status flag 26 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 25. " ISF25 ,Interrupt status flag 25 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " ISF24 ,Interrupt status flag 24 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 23. " ISF23 ,Interrupt status flag 23 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " ISF22 ,Interrupt status flag 22 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " ISF21 ,Interrupt status flag 21 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
width 0x0B
|
|
endif
|
|
width 0x0B
|
|
elif cpuis("MKL34*")||cpuis("MKL36*")||cpuis("MKL33Z*")
|
|
width 12.
|
|
sif cpuis("MKL3*VMP*")||cpuis("MKL3*VLH*")
|
|
width 14.
|
|
tree "PORT_A"
|
|
tree "Pin Control Registers"
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "PORT_A_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLH4")||cpuis("MKL33Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTA0,,TPM0_CH5,,,,SWD_CLK"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH1,PTA0,,TPM0_CH5,,,,SWD_CLK"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLH4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA1,UART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
elif cpuis("MKL33Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA1,LPUART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH2,PTA1,UART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLH4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA2,UART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
elif cpuis("MKL33Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTA2,LPUART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "TSI0_CH3,PTA2,UART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLH4")||cpuis("MKL33Z*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTA3,I2C1_SCL,TPM0_CH0,,,,SWD_DIO"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "TSI0_CH4,PTA3,I2C1_SCL,TPM0_CH0,,,,SWD_DIO"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLH4")||cpuis("MKL33Z*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" ",PTA4,I2C1_SDA,TPM0_CH1,,,,Nmi_b"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "TSI0_CH5,PTA4,I2C1_SDA,TPM0_CH1,,,,Nmi_b"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_A_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLH4")||cpuis("MKL33Z*")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA5,,TPM0_CH2,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA5,,TPM0_CH2,,,I2S0_TX_BCLK,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "PORT_A_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLH4")||cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTA12,,TPM1_CH0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTA12,,TPM1_CH0,,,I2S0_TXD0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLH4")||cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA13,,TPM1_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA13,,TPM1_CH1,,,I2S0_TX_FS,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x48++0x0B
|
|
line.long 0x00 "PORT_A_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL33Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,LPUART1_RX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,UART1_RX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL33Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,,LPUART1_TX,TPM_CLKIN1,,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,,UART1_TX,TPM_CLKIN1,,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL33Z*")||cpuis("MKL36Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTA20,,,,,,Reset_b"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA20,,,,,,Reset_b"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x80++0x07
|
|
line.long 0x00 "PORT_A_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 29. " GPWE13 ,Global pin 13 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 28. " GPWE12 ,Global pin 12 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_A_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORT_A_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " ISF13 ,Interrupt status flag 13 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " ISF12 ,Interrupt status flag 12 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_B"
|
|
tree "Pin Control Registers"
|
|
group.long 0x1000++0x0F
|
|
line.long 0x00 "PORT_B_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P0/ADC0_SE8,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,SPI1_MOSI,SPI1_MISO,,LCD_P0"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P0/ADC0_SE8/TSI0_CH0,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,,,,LCD_P0"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLH4")||cpuis("MKL36Z*")||cpuis("MKL33Z128*")||cpuis("MKL33Z256*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P1/ADC0_SE9,PTB1,I2C0_SDA,TPM1_CH1,,,,LCD_P1"
|
|
textline " "
|
|
elif cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P1/ADC0_SE9,PTB1,I2C0_SDA,TPM1_CH1,SPI1_MISO,SPI1_MOSI,,LCD_P1"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P1/ADC0_SE9/TSI0_CH6,PTB1,I2C0_SDA,TPM1_CH1,,,,LCD_P1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLH4")||cpuis("MKL33Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P2/ADC0_SE12,PTB2,I2C0_SCL,TPM2_CH0,,,,LCD_P2"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P2/ADC0_SE12/TSI0_CH7,PTB2,I2C0_SCL,TPM2_CH0,,,,LCD_P2"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLH4")||cpuis("MKL33Z*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P3/ADC0_SE13,PTB3,I2C0_SDA,TPM2_CH1,,,,LCD_P3"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P3/ADC0_SE13/TSI0_CH8,PTB3,I2C0_SDA,TPM2_CH1,,,,LCD_P3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x1040++0x0F
|
|
line.long 0x00 "PORT_B_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLH4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P12,PTB16,SPI1_MOSI,UART0_RX,TPM_CLKIN0,SPI1_MISO,,LCD_P12"
|
|
textline " "
|
|
elif cpuis("MKL33Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P12,PTB16,SPI1_MOSI,LPUART0_RX,TPM_CLKIN0,SPI1_MISO,,LCD_P12"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P12/TSI0_CH9,PTB16,SPI1_MOSI,UART0_RX,TPM_CLKIN0,SPI1_MISO,,LCD_P12"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLH4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P13,PTB17,SPI1_MISO,UART0_TX,TPM_CLKIN1,SPI1_MOSI,,LCD_P13"
|
|
textline " "
|
|
elif cpuis("MKL33Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P13,PTB17,SPI1_MISO,LPUART0_TX,TPM_CLKIN1,SPI1_MOSI,,LCD_P13"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P13/TSI0_CH10,PTB17,SPI1_MISO,UART0_TX,TPM_CLKIN1,SPI1_MOSI,,LCD_P13"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLH4")||cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P14,PTB18,,TPM2_CH0,,,,LCD_P14"
|
|
textline " "
|
|
elif cpuis("MKL33Z128*")||cpuis("MKL33Z256*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P14,PTB18,,TPM2_CH0,I2S0_TX_BCLK,,,LCD_P14"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P14/TSI0_CH11,PTB18,,TPM2_CH0,I2S0_TX_BCLK,,,LCD_P14"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLH4")||cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P15,PTB19,,TPM2_CH1,,,,LCD_P15"
|
|
textline " "
|
|
elif cpuis("MKL33Z128*")||cpuis("MKL33Z256*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P15,PTB19,,TPM2_CH1,I2S0_TX_FS,,,LCD_P15"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P15/TSI0_CH12,PTB19,,TPM2_CH1,I2S0_TX_FS,,,LCD_P15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x1080++0x07
|
|
line.long 0x00 "PORT_B_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_B_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "PORT_B_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_C"
|
|
tree "Pin Control Registers"
|
|
group.long 0x2000++0x1F
|
|
line.long 0x00 "PORT_C_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLH4")||cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P20/ADC0_SE14,PTC0,,EXTRG_IN,,CMP0_OUT,,LCD_P20"
|
|
textline " "
|
|
elif cpuis("MKL33Z128*")||cpuis("MKL33Z256*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P20/ADC0_SE14,PTC0,,EXTRG_IN,Audiousb_sof_out,CMP0_OUT,I2S0_TXD0,LCD_P20"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P20/ADC0_SE14/TSI0_CH13,PTC0,,EXTRG_IN,Audiousb_sof_out,CMP0_OUT,I2S0_TXD0,LCD_P20"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_C_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLH4")||cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P21/ADC0_SE15,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,,,LCD_P21"
|
|
textline " "
|
|
elif cpuis("MKL33Z128*")||cpuis("MKL33Z256*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P21/ADC0_SE15,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,,I2S0_TXD0,LCD_P21"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P21/ADC0_SE15/TSI0_CH14,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,,I2S0_TXD0,LCD_P21"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_C_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLH4")||cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P22/ADC0_SE11,PTC2,I2C1_SDA,,TPM0_CH1,,,LCD_P22"
|
|
textline " "
|
|
elif cpuis("MKL33Z128*")||cpuis("MKL33Z256*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P22/ADC0_SE11,PTC2,I2C1_SDA,,TPM0_CH1,,I2S0_TX_FS,LCD_P22"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P22/ADC0_SE11/TSI0_CH15,PTC2,I2C1_SDA,,TPM0_CH1,,I2S0_TX_FS,LCD_P22"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_C_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLH4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P23,PTC3/LLWU_P7,,UART1_RX,TPM0_CH2,CLKOUT,,LCD_P23"
|
|
textline " "
|
|
elif cpuis("MKL33Z32*")||cpuis("MKL33Z32*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P23,PTC3/LLWU_P7,SPI1_SCK,LPUART1_RX,TPM0_CH2,CLKOUT,,LCD_P23"
|
|
textline " "
|
|
elif cpuis("MKL33Z128*")||cpuis("MKL33Z256*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P23,PTC3/LLWU_P7,SPI1_SCK,LPUART1_RX,TPM0_CH2,CLKOUT,I2S0_TX_BCLK,LCD_P23"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P23,PTC3/LLWU_P7,,UART1_RX,TPM0_CH2,CLKOUT,I2S0_TX_BCLK,LCD_P23"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_C_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLH4")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD_P24,PTC4/LLWU_P8,SPI0_PCS0,UART1_TX,TPM0_CH3,,,LCD_P24"
|
|
textline " "
|
|
elif cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD_P24,PTC4/LLWU_P8,SPI0_PCS0,LPUART1_TX,TPM0_CH3,SPI1_PCS0,,LCD_P24"
|
|
textline " "
|
|
elif cpuis("MKL33Z128*")||cpuis("MKL33Z256*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD_P24,PTC4/LLWU_P8,SPI0_SS,LPUART1_TX,TPM0_CH3,I2S0_MCLK,,LCD_P24"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD_P24,PTC4/LLWU_P8,SPI0_PCS0,UART1_TX,TPM0_CH3,I2S0_MCLK,,LCD_P24"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_C_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLH4")||cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "LCD_P25,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,,,CMP0_OUT,LCD_P25"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "LCD_P25,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,I2S0_RXD0,,CMP0_OUT,LCD_P25"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_C_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLH4")||cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "LCD_P26/CMP0_IN0,PTC6/LLWU_P10,SPI0_MOSI,EXTRG_IN,,SPI0_MISO,,LCD_P26"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "LCD_P26/CMP0_IN0,PTC6/LLWU_P10,SPI0_MOSI,EXTRG_IN,I2S0_RX_BCLK,SPI0_MISO,I2S0_MCLK,LCD_P26"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_C_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLH4")||cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "LCD_P27/CMP0_IN1,PTC7,SPI0_MISO,,,SPI0_MOSI,,LCD_P27"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "LCD_P27/CMP0_IN1,PTC7,SPI0_MISO,Audiousb_sof_out,I2S0_RX_FS,SPI0_MOSI,,LCD_P27"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x2080++0x03
|
|
line.long 0x00 "PORT_C_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x2084++0x03
|
|
hide.long 0x00 "PORT_C_GPCHR,Global Pin Control High Register"
|
|
group.long 0x20A0++0x03
|
|
line.long 0x00 "PORT_C_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_D"
|
|
tree "Pin Control Registers"
|
|
group.long 0x3000++0x1F
|
|
line.long 0x00 "PORT_D_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL33Z128*")||cpuis("MKL33Z256*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P40,PTD0,SPI0_SS,,TPM0_CH0,,FXIO0_D0,LCD_P40"
|
|
textline " "
|
|
elif cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P40,PTD0,SPI0_PCS0,,TPM0_CH0,,FXIO0_D0,LCD_P40"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P40,PTD0,SPI0_PCS0,,TPM0_CH0,,,LCD_P40"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_D_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL33Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Lcd_p41/adc0_se5b,PTD1,SPI0_SCK,,TPM0_CH1,,FXIO0_D1,LCD_P41"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Lcd_p41/adc0_se5b,PTD1,SPI0_SCK,,TPM0_CH1,,,LCD_P41"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_D_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL33Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P42,PTD2,SPI0_MOSI,UART2_RX,TPM0_CH2,SPI0_MISO,FXIO0_D2,LCD_P42"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P42,PTD2,SPI0_MOSI,UART2_RX,TPM0_CH2,SPI0_MISO,,LCD_P42"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_D_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL33Z*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P43,PTD3,SPI0_MISO,UART2_TX,TPM0_CH3,SPI0_MOSI,FXIO0_D3,LCD_P43"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P43,PTD3,SPI0_MISO,UART2_TX,TPM0_CH3,SPI0_MOSI,,LCD_P43"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_D_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL33Z128*")||cpuis("MKL33Z256*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD_P44,PTD4/LLWU_P14,SPI1_SS,UART2_RX,TPM0_CH4,,FXIO0_D4,LCD_P44"
|
|
textline " "
|
|
elif cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD_P44,PTD4/LLWU_P14,SPI1_PCS0,UART2_RX,TPM0_CH4,,FXIO0_D4,LCD_P44"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD_P44,PTD4/LLWU_P14,SPI1_PCS0,UART2_RX,TPM0_CH4,,,LCD_P44"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_D_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL33Z*")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Lcd_p45/adc0_se6b,PTD5,SPI1_SCK,UART2_TX,TPM0_CH5,,FXIO0_D5,LCD_P45"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Lcd_p45/adc0_se6b,PTD5,SPI1_SCK,UART2_TX,TPM0_CH5,,,LCD_P45"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_D_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL33Z128*")||cpuis("MKL33Z256*")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Lcd_p46/adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,LPUART0_RX,,SPI1_MISO,FXIO0_D6,LCD_P46"
|
|
textline " "
|
|
elif cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Lcd_p46/adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,LPUART0_RX,I2C1_SDA,SPI1_MISO,FXIO0_D6,LCD_P46"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Lcd_p46/adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,UART0_RX,,SPI1_MISO,,LCD_P46"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_D_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL33Z128*")||cpuis("MKL33Z256*")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "LCD_P47,PTD7,SPI1_MISO,LPUART0_TX,,SPI1_MOSI,FXIO0_D7,LCD_P47"
|
|
textline " "
|
|
elif cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "LCD_P47,PTD7,SPI1_MISO,LPUART0_TX,I2C1_SCL,SPI1_MOSI,FXIO0_D7,LCD_P47"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "LCD_P47,PTD7,SPI1_MISO,UART0_TX,,SPI1_MOSI,,LCD_P47"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x3080++0x03
|
|
line.long 0x00 "PORT_D_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x3084++0x03
|
|
hide.long 0x00 "PORT_D_GPCHR,Global Pin Control High Register"
|
|
group.long 0x30A0++0x03
|
|
line.long 0x00 "PORT_D_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_E"
|
|
tree "Pin Control Registers"
|
|
group.long 0x4000++0x07
|
|
line.long 0x00 "PORT_E_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL33Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P48,PTE0,SPI1_MISO,LPUART1_TX,RTC_CLKOUT,CMP0_OUT,I2C1_SDA,LCD_P48"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P48,PTE0,SPI1_MISO,UART1_TX,RTC_CLKOUT,CMP0_OUT,I2C1_SDA,LCD_P48"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL33Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P49,PTE1,SPI1_MOSI,LPUART1_RX,,SPI1_MISO,I2C1_SCL,LCD_P49"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P49,PTE1,SPI1_MOSI,UART1_RX,,SPI1_MISO,I2C1_SCL,LCD_P49"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4040++0x0F
|
|
line.long 0x00 "PORT_E_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLH4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P55/ADC0_SE1,PTE16,SPI0_PCS0,UART2_TX,TPM_CLKIN0,,,LCD_P55"
|
|
textline " "
|
|
elif cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P55/ADC0_DP1/ADC0_SE1,PTE16,SPI0_PCS0,UART2_TX,TPM_CLKIN0,,FXIO0_D0,LCD_P55"
|
|
textline " "
|
|
elif cpuis("MKL33Z128*")||cpuis("MKL33Z256*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P55/ADC0_DP1/ADC0_SE1,PTE16,SPI0_SS,UART2_TX,TPM_CLKIN0,,FXIO0_D0,LCD_P55"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P55/ADC0_DP1/ADC0_SE1,PTE16,SPI0_PCS0,UART2_TX,TPM_CLKIN0,,,LCD_P55"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLH4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Lcd_p56/adc0_se5a,PTE17,SPI0_SCK,UART2_RX,TPM_CLKIN1,,LPTMR0_ALT3,LCD_P56"
|
|
textline " "
|
|
elif cpuis("MKL33Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Lcd_p56/adc0_dm1/adc0_se5a,PTE17,SPI0_SCK,UART2_RX,TPM_CLKIN1,LPTMR0_ALT3,FXIO0_D1,LCD_P56"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Lcd_p56/adc0_dm1/adc0_se5a,PTE17,SPI0_SCK,UART2_RX,TPM_CLKIN1,,LPTMR0_ALT3,LCD_P56"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLH4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P57/ADC0_SE2,PTE18,SPI0_MOSI,,I2C0_SDA,SPI0_MISO,,LCD_P57"
|
|
textline " "
|
|
elif cpuis("MKL33Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P57/ADC0_DP2/ADC0_SE2,PTE18,SPI0_MOSI,,I2C0_SDA,SPI0_MISO,FXIO0_D2,LCD_P57"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P57/ADC0_DP2/ADC0_SE2,PTE18,SPI0_MOSI,,I2C0_SDA,SPI0_MISO,,LCD_P57"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_E_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLH4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Lcd_p58/adc0_se6a,PTE19,SPI0_MISO,,I2C0_SCL,SPI0_MOSI,,LCD_P58"
|
|
textline " "
|
|
elif cpuis("MKL33Z*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Lcd_p58/adc0_dm2/adc0_se6a,PTE19,SPI0_MISO,,I2C0_SCL,SPI0_MOSI,FXIO0_D3,LCD_P58"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Lcd_p58/adc0_dm2/adc0_se6a,PTE19,SPI0_MISO,,I2C0_SCL,SPI0_MOSI,,LCD_P58"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4050++0x17
|
|
line.long 0x00 "PORT_E_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLH4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P59/ADC0_SE0,PTE20,,TPM1_CH0,UART0_TX,,,LCD_P59"
|
|
textline " "
|
|
elif cpuis("MKL33Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P59/ADC0_DP0/ADC0_SE0,PTE20,,TPM1_CH0,LPUART0_TX,,FXIO0_D4,LCD_P59"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P59/ADC0_DP0/ADC0_SE0,PTE20,,TPM1_CH0,UART0_TX,,,LCD_P59"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR21,Pin Control Register 21"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLH4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Lcd_p60/adc0_se4a,PTE21,,TPM1_CH1,UART0_RX,,,LCD_P60"
|
|
textline " "
|
|
elif cpuis("MKL33Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Lcd_p60/adc0_dm0/adc0_se4a,PTE21,,TPM1_CH1,LPUART0_RX,,FXIO0_D5,LCD_P60"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Lcd_p60/adc0_dm0/adc0_se4a,PTE21,,TPM1_CH1,UART0_RX,,,LCD_P60"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR22,Pin Control Register 22"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLH4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE3,PTE22,,TPM2_CH0,UART2_TX,?..."
|
|
textline " "
|
|
elif cpuis("MKL33Z*")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_DP3/ADC0_SE3,PTE22,,TPM2_CH0,UART2_TX,,FXIO0_D6,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_DP3/ADC0_SE3,PTE22,,TPM2_CH0,UART2_TX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_E_PCR23,Pin Control Register 23"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLH4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_se7a,PTE23,,TPM2_CH1,UART2_RX,?..."
|
|
textline " "
|
|
elif cpuis("MKL33Z*")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_dm3/adc0_se7a,PTE23,,TPM2_CH1,UART2_RX,,FXIO0_D7,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_dm3/adc0_se7a,PTE23,,TPM2_CH1,UART2_RX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_E_PCR24,Pin Control Register 24"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTE24,,TPM0_CH0,,I2C0_SCL,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_E_PCR25,Pin Control Register 25"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTE25,,TPM0_CH1,,I2C0_SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4074++0x0B
|
|
line.long 0x00 "PORT_E_PCR29,Pin Control Register 29"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Cmp0_in5/adc0_se4b,PTE29,,TPM0_CH2,TPM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR30,Pin Control Register 30"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLH4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,?..."
|
|
textline " "
|
|
elif cpuis("MKL33Z*")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DAC0_OUT/ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,LPUART1_TX,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DAC0_OUT/ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR31,Pin Control Register 31"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTE31,,TPM0_CH4,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x4080++0x07
|
|
line.long 0x00 "PORT_E_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_E_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 31. " GPWE31 ,Global pin 31 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 30. " GPWE30 ,Global pin 30 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 29. " GPWE29 ,Global pin 29 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 25. " GPWE25 ,Global pin 25 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 24. " GPWE24 ,Global pin 24 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 23. " GPWE23 ,Global pin 23 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 22. " GPWE22 ,Global pin 22 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 21. " GPWE21 ,Global pin 21 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x40A0++0x03
|
|
line.long 0x00 "PORT_E_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 31. " ISF31 ,Interrupt status flag 31 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " ISF30 ,Interrupt status flag 30 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 29. " ISF29 ,Interrupt status flag 29 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " ISF25 ,Interrupt status flag 25 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " ISF24 ,Interrupt status flag 24 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 23. " ISF23 ,Interrupt status flag 23 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 22. " ISF22 ,Interrupt status flag 22 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " ISF21 ,Interrupt status flag 21 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL3*VLL*")||cpuis("MKL3*VMC*")
|
|
width 14.
|
|
tree "PORT_A"
|
|
tree "Pin Control Registers"
|
|
group.long 0x00++0x1F
|
|
line.long 0x00 "PORT_A_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")||cpuis("MKL33Z*")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTA0,,TPM0_CH5,,,,SWD_CLK"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH1,PTA0,,TPM0_CH5,,,,SWD_CLK"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTA1,UART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH2,PTA1,UART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTA2,UART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "TSI0_CH3,PTA2,UART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTA3,I2C1_SCL,TPM0_CH0,,,,SWD_DIO"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "TSI0_CH4,PTA3,I2C1_SCL,TPM0_CH0,,,,SWD_DIO"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" ",PTA4,I2C1_SDA,TPM0_CH1,,,,Nmi_b"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "TSI0_CH5,PTA4,I2C1_SDA,TPM0_CH1,,,,Nmi_b"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_A_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA5,,TPM0_CH2,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA5,,TPM0_CH2,,,I2S0_TX_BCLK,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_A_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Disabled,PTA6,,TPM0_CH3,?..."
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_A_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "Disabled,PTA7,,TPM0_CH4,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x30++0x17
|
|
line.long 0x00 "PORT_A_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTA12,,TPM1_CH0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTA12,,TPM1_CH0,,,I2S0_TXD0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA13,,TPM1_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA13,,TPM1_CH1,,,I2S0_TX_FS,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR14,Pin Control Register 14"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA14,SPI0_PCS0,UART0_TX,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA14,SPI0_PCS0,UART0_TX,,,I2S0_RX_BCLK,I2S0_TXD0"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR15,Pin Control Register 15"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTA15,SPI0_SCK,UART0_RX,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTA15,SPI0_SCK,UART0_RX,,,I2S0_RXD0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTA16,SPI0_MOSI,,,SPI0_MISO,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTA16,SPI0_MOSI,,,SPI0_MISO,I2S0_RX_FS,I2S0_RXD0"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_A_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA17,SPI0_MISO,,,SPI0_MOSI,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA17,SPI0_MISO,,,SPI0_MOSI,I2S0_MCLK,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x48++0x0B
|
|
line.long 0x00 "PORT_A_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,UART1_RX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,,UART1_TX,TPM_CLKIN1,,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA20,,,,,,Reset_b"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x80++0x07
|
|
line.long 0x00 "PORT_A_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 31. " GPWE15 ,Global pin 15 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 30. " GPWE14 ,Global pin 14 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 29. " GPWE13 ,Global pin 13 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GPWE12 ,Global pin 12 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_A_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORT_A_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 15. " ISF15 ,Interrupt status flag 15 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 14. " ISF14 ,Interrupt status flag 14 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " ISF13 ,Interrupt status flag 13 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " ISF12 ,Interrupt status flag 12 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_B"
|
|
tree "Pin Control Registers"
|
|
group.long 0x1000++0x0F
|
|
line.long 0x00 "PORT_B_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P0/ADC0_SE8,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,,,,LCD_P0"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P0/ADC0_SE8/TSI0_CH0,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,,,,LCD_P0"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P1/ADC0_SE9,PTB1,I2C0_SDA,TPM1_CH1,,,,LCD_P1"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P1/ADC0_SE9/TSI0_CH6,PTB1,I2C0_SDA,TPM1_CH1,,,,LCD_P1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P2/ADC0_SE12,PTB2,I2C0_SCL,TPM2_CH0,,,,LCD_P2"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P2/ADC0_SE12/TSI0_CH7,PTB2,I2C0_SCL,TPM2_CH0,,,,LCD_P2"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P3/ADC0_SE13,PTB3,I2C0_SDA,TPM2_CH1,,,,LCD_P3"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P3/ADC0_SE13/TSI0_CH8,PTB3,I2C0_SDA,TPM2_CH1,,,,LCD_P3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x101C++0x13
|
|
line.long 0x00 "PORT_B_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P7,PTB7,,,,,,LCD_P7"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P8,PTB8,SPI1_PCS0,EXTRG_IN,,,,LCD_P8"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P9,PTB9,SPI1_SCK,,,,,LCD_P9"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P10,PTB10,SPI1_PCS0,,,,,LCD_P10"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_B_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD_P11,PTB11,SPI1_SCK,,,,,LCD_P11"
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x1040++0x1F
|
|
line.long 0x00 "PORT_B_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P12,PTB16,SPI1_MOSI,UART0_RX,TPM_CLKIN0,SPI1_MISO,,LCD_P12"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P12/TSI0_CH9,PTB16,SPI1_MOSI,UART0_RX,TPM_CLKIN0,SPI1_MISO,,LCD_P12"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P13,PTB17,SPI1_MISO,UART0_TX,TPM_CLKIN1,SPI1_MOSI,,LCD_P13"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P13/TSI0_CH10,PTB17,SPI1_MISO,UART0_TX,TPM_CLKIN1,SPI1_MOSI,,LCD_P13"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P14,PTB18,,TPM2_CH0,,,,LCD_P14"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P14/TSI0_CH11,PTB18,,TPM2_CH0,I2S0_TX_BCLK,,,LCD_P14"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P15,PTB19,,TPM2_CH1,,,,LCD_P15"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P15/TSI0_CH12,PTB19,,TPM2_CH1,I2S0_TX_FS,,,LCD_P15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_B_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD_P16,PTB20,,,,,CMP0_OUT,LCD_P16"
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_B_PCR21,Pin Control Register 21"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "LCD_P17,PTB21,,,,,,LCD_P17"
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_B_PCR22,Pin Control Register 22"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "LCD_P18,PTB22,,,,,,LCD_P18"
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_B_PCR23,Pin Control Register 23"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "LCD_P19,PTB23,,,,,,LCD_P19"
|
|
textline " "
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x1080++0x07
|
|
line.long 0x00 "PORT_B_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_B_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 23. " GPWE23 ,Global pin 23 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 22. " GPWE22 ,Global pin 22 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 21. " GPWE21 ,Global pin 21 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "PORT_B_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 23. " ISF23 ,Interrupt status flag 23 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " ISF22 ,Interrupt status flag 22 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " ISF21 ,Interrupt status flag 21 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_C"
|
|
tree "Pin Control Registers"
|
|
group.long 0x2000++0x37
|
|
line.long 0x00 "PORT_C_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P20/ADC0_SE14,PTC0,,EXTRG_IN,,CMP0_OUT,,LCD_P20"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P20/ADC0_SE14/TSI0_CH13,PTC0,,EXTRG_IN,Audiousb_sof_out,CMP0_OUT,I2S0_TXD0,LCD_P20"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_C_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P21/ADC0_SE15,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,,,LCD_P21"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P21/ADC0_SE15/TSI0_CH14,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,,I2S0_TXD0,LCD_P21"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_C_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P22/ADC0_SE11,PTC2,I2C1_SDA,,TPM0_CH1,,,LCD_P22"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P22/ADC0_SE11/TSI0_CH15,PTC2,I2C1_SDA,,TPM0_CH1,,I2S0_TX_FS,LCD_P22"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_C_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P23,PTC3/LLWU_P7,,UART1_RX,TPM0_CH2,CLKOUT,,LCD_P23"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P23,PTC3/LLWU_P7,,UART1_RX,TPM0_CH2,CLKOUT,I2S0_TX_BCLK,LCD_P23"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_C_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD_P24,PTC4/LLWU_P8,SPI0_PCS0,UART1_TX,TPM0_CH3,,,LCD_P24"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD_P24,PTC4/LLWU_P8,SPI0_PCS0,UART1_TX,TPM0_CH3,I2S0_MCLK,,LCD_P24"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_C_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "LCD_P25,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,,,CMP0_OUT,LCD_P25"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "LCD_P25,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,I2S0_RXD0,,CMP0_OUT,LCD_P25"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_C_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "LCD_P26/CMP0_IN0,PTC6/LLWU_P10,SPI0_MOSI,EXTRG_IN,,SPI0_MISO,,LCD_P26"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "LCD_P26/CMP0_IN0,PTC6/LLWU_P10,SPI0_MOSI,EXTRG_IN,I2S0_RX_BCLK,SPI0_MISO,I2S0_MCLK,LCD_P26"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_C_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "LCD_P27/CMP0_IN1,PTC7,SPI0_MISO,,,SPI0_MOSI,,LCD_P27"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "LCD_P27/CMP0_IN1,PTC7,SPI0_MISO,Audiousb_sof_out,I2S0_RX_FS,SPI0_MOSI,,LCD_P27"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x20 "PORT_C_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x20 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "LCD_P28/CMP0_IN2,PTC8,I2C0_SCL,TPM0_CH4,,,,LCD_P28"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "LCD_P28/CMP0_IN2,PTC8,I2C0_SCL,TPM0_CH4,I2S0_MCLK,,,LCD_P28"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x20 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x20 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x20 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x24 "PORT_C_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x24 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "LCD_P29/CMP0_IN3,PTC9,I2C0_SDA,TPM0_CH5,,,,LCD_P29"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "LCD_P29/CMP0_IN3,PTC9,I2C0_SDA,TPM0_CH5,I2S0_RX_BCLK,,,LCD_P29"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x24 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x24 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x24 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x28 "PORT_C_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x28 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x28 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x28 8.--10. " MUX ,Pin mux control" "LCD_P30,PTC10,I2C1_SCL,,,,,LCD_P30"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x28 8.--10. " MUX ,Pin mux control" "LCD_P30,PTC10,I2C1_SCL,,I2S0_RX_FS,,,LCD_P30"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x28 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x28 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x28 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x2C "PORT_C_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x2C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" "LCD_P31,PTC11,I2C1_SDA,,,,,LCD_P31"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" "LCD_P31,PTC11,I2C1_SDA,,I2S0_RXD0,,,LCD_P31"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x2C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x2C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x2C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x30 "PORT_C_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x30 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x30 8.--10. " MUX ,Pin mux control" "LCD_P32,PTC12,,,TPM_CLKIN0,,,LCD_P32"
|
|
textline " "
|
|
bitfld.long 0x30 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x30 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x30 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x30 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x30 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x34 "PORT_C_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x34 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x34 8.--10. " MUX ,Pin mux control" "LCD_P33,PTC13,,,TPM_CLKIN1,,,LCD_P33"
|
|
textline " "
|
|
bitfld.long 0x34 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x34 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x34 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x34 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x34 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x2040++0x0B
|
|
line.long 0x00 "PORT_C_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P36,PTC16,,,,,,LCD_P36"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_C_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P37,PTC17,,,,,,LCD_P37"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_C_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P38,PTC18,,,,,,LCD_P38"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x2080++0x07
|
|
line.long 0x00 "PORT_C_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 29. " GPWE13 ,Global pin 13 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 28. " GPWE12 ,Global pin 12 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_C_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x20A0++0x03
|
|
line.long 0x00 "PORT_C_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " ISF13 ,Interrupt status flag 13 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " ISF12 ,Interrupt status flag 12 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_D"
|
|
tree "Pin Control Registers"
|
|
group.long 0x3000++0x1F
|
|
line.long 0x00 "PORT_D_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P40,PTD0,SPI0_PCS0,,TPM0_CH0,,,LCD_P40"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_D_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Lcd_p41/adc0_se5b,PTD1,SPI0_SCK,,TPM0_CH1,,,LCD_P41"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_D_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P42,PTD2,SPI0_MOSI,UART2_RX,TPM0_CH2,SPI0_MISO,,LCD_P42"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_D_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P43,PTD3,SPI0_MISO,UART2_TX,TPM0_CH3,SPI0_MOSI,,LCD_P43"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_D_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD_P44,PTD4/LLWU_P14,SPI1_PCS0,UART2_RX,TPM0_CH4,,,LCD_P44"
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_D_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Lcd_p45/adc0_se6b,PTD5,SPI1_SCK,UART2_TX,TPM0_CH5,,,LCD_P45"
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_D_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Lcd_p46/adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,UART0_RX,,SPI1_MISO,,LCD_P46"
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_D_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "LCD_P47,PTD7,SPI1_MISO,UART0_TX,,SPI1_MOSI,,LCD_P47"
|
|
textline " "
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x3080++0x03
|
|
line.long 0x00 "PORT_D_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x3084++0x03
|
|
hide.long 0x00 "PORT_D_GPCHR,Global Pin Control High Register"
|
|
group.long 0x30A0++0x03
|
|
line.long 0x00 "PORT_D_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_E"
|
|
tree "Pin Control Registers"
|
|
group.long 0x4000++0x1B
|
|
line.long 0x00 "PORT_E_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P48,PTE0,SPI1_MISO,UART1_TX,RTC_CLKOUT,CMP0_OUT,I2C1_SDA,LCD_P48"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P49,PTE1,SPI1_MOSI,UART1_RX,,SPI1_MISO,I2C1_SCL,LCD_P49"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P50,PTE2,SPI1_SCK,,,,,LCD_P50"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_E_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P51,PTE3,SPI1_MISO,,,SPI1_MOSI,,LCD_P51"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_E_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD_P52,PTE4,SPI1_PCS0,,,,,LCD_P52"
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_E_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "LCD_P53,PTE5,,,,,,LCD_P53"
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_E_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "LCD_P54,PTE6,,,,,,LCD_P54"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "LCD_P54,PTE6,,,I2S0_MCLK,Audiousb_sof_out,,LCD_P54"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4040++0x0F
|
|
line.long 0x00 "PORT_E_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P55/ADC0_SE1,PTE16,SPI0_PCS0,UART2_TX,TPM_CLKIN0,,,LCD_P55"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P55/ADC0_DP1/ADC0_SE1,PTE16,SPI0_PCS0,UART2_TX,TPM_CLKIN0,,,LCD_P55"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Lcd_p56/adc0_se5a,PTE17,SPI0_SCK,UART2_RX,TPM_CLKIN1,,LPTMR0_ALT3,LCD_P56"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Lcd_p56/adc0_dm1/adc0_se5a,PTE17,SPI0_SCK,UART2_RX,TPM_CLKIN1,,LPTMR0_ALT3,LCD_P56"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Lcd_p57/adc0_se2a,PTE18,SPI0_MOSI,,I2C0_SDA,SPI0_MISO,,LCD_P57"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P57/ADC0_DP2/ADC0_SE2,PTE18,SPI0_MOSI,,I2C0_SDA,SPI0_MISO,,LCD_P57"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_E_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Lcd_p58/adc0_se6a,PTE19,SPI0_MISO,,I2C0_SCL,SPI0_MOSI,,LCD_P58"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Lcd_p58/adc0_dm2/adc0_se6a,PTE19,SPI0_MISO,,I2C0_SCL,SPI0_MOSI,,LCD_P58"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4050++0x1B
|
|
line.long 0x00 "PORT_E_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P59/ADC0_SE0,PTE20,,TPM1_CH0,UART0_TX,,,LCD_P59"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P59/ADC0_DP0/ADC0_SE0,PTE20,,TPM1_CH0,UART0_TX,,,LCD_P59"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR21,Pin Control Register 21"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Lcd_p60/adc0_se4a,PTE21,,TPM1_CH1,UART0_RX,,,LCD_P60"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Lcd_p60/adc0_dm0/adc0_se4a,PTE21,,TPM1_CH1,UART0_RX,,,LCD_P60"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR22,Pin Control Register 22"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE3,PTE22,,TPM2_CH0,UART2_TX,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_DP3/ADC0_SE3,PTE22,,TPM2_CH0,UART2_TX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_E_PCR23,Pin Control Register 23"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_se7a,PTE23,,TPM2_CH1,UART2_RX,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_dm3/adc0_se7a,PTE23,,TPM2_CH1,UART2_RX,?..."
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_E_PCR24,Pin Control Register 24"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "DISABLED,PTE24,,TPM0_CH0,,I2C0_SCL,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_E_PCR25,Pin Control Register 25"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "DISABLED,PTE25,,TPM0_CH1,,I2C0_SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_E_PCR26,Pin Control Register 26"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "DISABLED,PTE26,,TPM0_CH5,,,RTC_CLKOUT,?..."
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4074++0x0B
|
|
line.long 0x00 "PORT_E_PCR29,Pin Control Register 29"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Cmp0_in5/adc0_se4b,PTE29,,TPM0_CH2,TPM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR30,Pin Control Register 30"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif (cpu()=="MKL34Z64VLL4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DAC0_OUT/ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR31,Pin Control Register 31"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "DISABLED,PTE31,,TPM0_CH4,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x4080++0x07
|
|
line.long 0x00 "PORT_E_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_E_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 31. " GPWE31 ,Global pin 31 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 30. " GPWE30 ,Global pin 30 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 29. " GPWE29 ,Global pin 29 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 26. " GPWE26 ,Global pin 26 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 25. " GPWE25 ,Global pin 25 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 24. " GPWE24 ,Global pin 24 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 23. " GPWE23 ,Global pin 23 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 22. " GPWE22 ,Global pin 22 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 21. " GPWE21 ,Global pin 21 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x40A0++0x03
|
|
line.long 0x00 "PORT_E_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 31. " ISF31 ,Interrupt status flag 31 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " ISF30 ,Interrupt status flag 30 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 29. " ISF29 ,Interrupt status flag 29 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 26. " ISF26 ,Interrupt status flag 26 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 25. " ISF25 ,Interrupt status flag 25 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " ISF24 ,Interrupt status flag 24 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 23. " ISF23 ,Interrupt status flag 23 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " ISF22 ,Interrupt status flag 22 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " ISF21 ,Interrupt status flag 21 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL3*VLK*")
|
|
width 14.
|
|
tree "PORT_A"
|
|
tree "Pin Control Registers"
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "PORT_A_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTA0,,TPM0_CH5,,,,SWD_CLK"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTA1,LPUART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTA2,LPUART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTA3,I2C1_SCL,TPM0_CH0,,,,SWD_DIO"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" ",PTA4,I2C1_SDA,TPM0_CH1,,,,Nmi_b"
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_A_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" ",PTA5,,TPM0_CH2,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x30++0x23
|
|
line.long 0x00 "PORT_A_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTA12,,TPM1_CH0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA13,,TPM1_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR14,Pin Control Register 14"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA14,SPI0_PCS0,LPUART0_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR15,Pin Control Register 15"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTA15,SPI0_SCK,LPUART0_RX,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTA16,SPI0_MOSI,,,SPI0_MISO,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_A_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA17,SPI0_MISO,,,SPI0_MOSI,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_A_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,LPUART1_RX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_A_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,,LPUART1_TX,TPM_CLKIN1,,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x20 "PORT_A_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x20 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" ",PTA20,,,,,,Reset_b"
|
|
textline " "
|
|
bitfld.long 0x20 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x20 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x20 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x80++0x07
|
|
line.long 0x00 "PORT_A_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 31. " GPWE15 ,Global pin 15 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 30. " GPWE14 ,Global pin 14 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 29. " GPWE13 ,Global pin 13 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GPWE12 ,Global pin 12 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_A_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORT_A_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 15. " ISF15 ,Interrupt status flag 15 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 14. " ISF14 ,Interrupt status flag 14 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " ISF13 ,Interrupt status flag 13 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " ISF12 ,Interrupt status flag 12 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_B"
|
|
tree "Pin Control Registers"
|
|
group.long 0x1000++0x0F
|
|
line.long 0x00 "PORT_B_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P0/ADC0_SE8,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,SPI1_MOSI,SPI1_MISO,,LCD_P0"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P1/ADC0_SE9,PTB1,I2C0_SDA,TPM1_CH1,SPI1_MISO,SPI1_MOSI,,LCD_P1"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P2/ADC0_SE12,PTB2,I2C0_SCL,TPM2_CH0,,,,LCD_P2"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P3/ADC0_SE13,PTB3,I2C0_SDA,TPM2_CH1,,,,LCD_P3"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x1020++0x0F
|
|
line.long 0x00 "PORT_B_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P8,PTB8,SPI1_PCS0,EXTRG_IN,,,,LCD_P8"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P9,PTB9,SPI1_SCK,,,,,LCD_P9"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P10,PTB10,SPI1_PCS0,,,,,LCD_P10"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P11,PTB11,SPI1_SCK,,,,,LCD_P11"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x1040++0x0F
|
|
line.long 0x00 "PORT_B_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P12,PTB16,SPI1_MOSI,LPUART0_RX,TPM_CLKIN0,SPI1_MISO,,LCD_P12"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P13,PTB17,SPI1_MISO,LPUART0_TX,TPM_CLKIN1,SPI1_MOSI,,LCD_P13"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P14,PTB18,,TPM2_CH0,,,,LCD_P14"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P15,PTB19,,TPM2_CH1,,,,LCD_P15"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x1080++0x07
|
|
line.long 0x00 "PORT_B_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_B_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "PORT_B_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_C"
|
|
tree "Pin Control Registers"
|
|
group.long 0x2000++0x37
|
|
line.long 0x00 "PORT_C_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P20/ADC0_SE14,PTC0,,EXTRG_IN,,CMP0_OUT,,LCD_P20"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_C_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P21/ADC0_SE15,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,,,LCD_P21"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_C_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P22/ADC0_SE11,PTC2,I2C1_SDA,,TPM0_CH1,,,LCD_P22"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_C_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P23,PTC3/LLWU_P7,SPI1_SCK,LPUART1_RX,TPM0_CH2,CLKOUT,,LCD_P23"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_C_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD_P24,PTC4/LLWU_P8,SPI0_PCS0,LPUART1_TX,TPM0_CH3,SPI1_PCS0,,LCD_P24"
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_C_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "LCD_P25,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,,,CMP0_OUT,LCD_P25"
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_C_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "LCD_P26/CMP0_IN0,PTC6/LLWU_P10,SPI0_MOSI,EXTRG_IN,,SPI0_MISO,,LCD_P26"
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_C_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "LCD_P27/CMP0_IN1,PTC7,SPI0_MISO,,,SPI0_MOSI,,LCD_P27"
|
|
textline " "
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x20 "PORT_C_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x20 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "LCD_P28/CMP0_IN2,PTC8,I2C0_SCL,TPM0_CH4,,,,LCD_P28"
|
|
textline " "
|
|
bitfld.long 0x20 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x20 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x20 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x24 "PORT_C_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x24 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "LCD_P29/CMP0_IN3,PTC9,I2C0_SDA,TPM0_CH5,,,,LCD_P29"
|
|
textline " "
|
|
bitfld.long 0x24 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x24 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x24 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x28 "PORT_C_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x28 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x28 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x28 8.--10. " MUX ,Pin mux control" "LCD_P30,PTC10,I2C1_SCL,,,,,LCD_P30"
|
|
textline " "
|
|
bitfld.long 0x28 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x28 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x28 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x2C "PORT_C_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x2C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" "LCD_P31,PTC11,I2C1_SDA,,,,,LCD_P31"
|
|
textline " "
|
|
bitfld.long 0x2C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x2C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x2C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x2080++0x07
|
|
line.long 0x00 "PORT_C_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_C_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x20A0++0x03
|
|
line.long 0x00 "PORT_C_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_D"
|
|
tree "Pin Control Registers"
|
|
group.long 0x3000++0x1F
|
|
line.long 0x00 "PORT_D_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P40,PTD0,SPI0_PCS0,,TPM0_CH0,,FXIO0_D0,LCD_P40"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_D_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Lcd_p41/adc0_se5b,PTD1,SPI0_SCK,,TPM0_CH1,,FXIO0_D1,LCD_P41"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_D_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P42,PTD2,SPI0_MOSI,UART2_RX,TPM0_CH2,SPI0_MISO,FXIO0_D2,LCD_P42"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_D_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P43,PTD3,SPI0_MISO,UART2_TX,TPM0_CH3,SPI0_MOSI,FXIO0_D3,LCD_P43"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_D_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD_P44,PTD4/LLWU_P14,SPI1_PCS0,UART2_RX,TPM0_CH4,,FXIO0_D4,LCD_P44"
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_D_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Lcd_p45/adc0_se6b,PTD5,SPI1_SCK,UART2_TX,TPM0_CH5,,FXIO0_D5,LCD_P45"
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_D_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Lcd_p46/adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,LPUART0_RX,I2C1_SDA,SPI1_MISO,FXIO0_D6,LCD_P46"
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_D_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "LCD_P47,PTD7,SPI1_MISO,LPUART0_TX,I2C1_SCL,SPI1_MOSI,FXIO0_D7,LCD_P47"
|
|
textline " "
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x3080++0x03
|
|
line.long 0x00 "PORT_D_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x3084++0x03
|
|
hide.long 0x00 "PORT_D_GPCHR,Global Pin Control High Register"
|
|
group.long 0x30A0++0x03
|
|
line.long 0x00 "PORT_D_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_E"
|
|
tree "Pin Control Registers"
|
|
group.long 0x4000++0x17
|
|
line.long 0x00 "PORT_E_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P48,PTE0,SPI1_MISO,LPUART1_TX,RTC_CLKOUT,CMP0_OUT,I2C1_SDA,LCD_P48"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P49,PTE1,SPI1_MOSI,LPUART1_RX,,SPI1_MISO,I2C1_SCL,LCD_P49"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P50,PTE2,SPI1_SCK,,,,,LCD_P50"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_E_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P51,PTE3,SPI1_MISO,,,SPI1_MOSI,,LCD_P51"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_E_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD_P52,PTE4,SPI1_PCS0,,,,,LCD_P52"
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_E_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "LCD_P53,PTE5,,,,,,LCD_P53"
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4040++0x0F
|
|
line.long 0x00 "PORT_E_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P55/ADC0_DP1/ADC0_SE1,PTE16,SPI0_PCS0,UART2_TX,TPM_CLKIN0,,FXIO0_D0,LCD_P55"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Lcd_p56/adc0_dm1/adc0_se5a,PTE17,SPI0_SCK,UART2_RX,TPM_CLKIN1,LPTMR0_ALT3,FXIO0_D1,LCD_P56"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P57/ADC0_DP2/ADC0_SE2,PTE18,SPI0_MOSI,,I2C0_SDA,SPI0_MISO,FXIO0_D2,LCD_P57"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_E_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Lcd_p58/adc0_dm2/adc0_se6a,PTE19,SPI0_MISO,,I2C0_SCL,SPI0_MOSI,FXIO0_D3,LCD_P58"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4050++0x17
|
|
line.long 0x00 "PORT_E_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P59/ADC0_DP0/ADC0_SE0,PTE20,,TPM1_CH0,LPUART0_TX,,FXIO0_D4,LCD_P59"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR21,Pin Control Register 21"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Lcd_p60/adc0_dm0/adc0_se4a,PTE21,,TPM1_CH1,LPUART0_RX,,FXIO0_D5,LCD_P60"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR22,Pin Control Register 22"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_DP3/ADC0_SE3,PTE22,,TPM2_CH0,UART2_TX,,FXIO0_D6,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_E_PCR23,Pin Control Register 23"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_dm3/adc0_se7a,PTE23,,TPM2_CH1,UART2_RX,,FXIO0_D7,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_E_PCR24,Pin Control Register 24"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "DISABLED,PTE24,,TPM0_CH0,,I2C0_SCL,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_E_PCR25,Pin Control Register 25"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "DISABLED,PTE25,,TPM0_CH1,,I2C0_SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4074++0x0B
|
|
line.long 0x00 "PORT_E_PCR29,Pin Control Register 29"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Cmp0_in5/adc0_se4b,PTE29,,TPM0_CH2,TPM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR30,Pin Control Register 30"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DAC0_OUT/ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,LPUART1_TX,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR31,Pin Control Register 31"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "DISABLED,PTE31,,TPM0_CH4,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x4080++0x07
|
|
line.long 0x00 "PORT_E_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_E_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 31. " GPWE31 ,Global pin 31 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 30. " GPWE30 ,Global pin 30 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 29. " GPWE29 ,Global pin 29 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 25. " GPWE25 ,Global pin 25 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 24. " GPWE24 ,Global pin 24 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 23. " GPWE23 ,Global pin 23 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 22. " GPWE22 ,Global pin 22 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 21. " GPWE21 ,Global pin 21 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x40A0++0x03
|
|
line.long 0x00 "PORT_E_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 31. " ISF31 ,Interrupt status flag 31 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " ISF30 ,Interrupt status flag 30 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 29. " ISF29 ,Interrupt status flag 29 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " ISF25 ,Interrupt status flag 25 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " ISF24 ,Interrupt status flag 24 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 23. " ISF23 ,Interrupt status flag 23 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 22. " ISF22 ,Interrupt status flag 22 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " ISF21 ,Interrupt status flag 21 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL3*VFT*")
|
|
width 14.
|
|
tree "PORT_A"
|
|
tree "Pin Control Registers"
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "PORT_A_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTA0,,TPM0_CH5,,,,SWD_CLK"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTA1,LPUART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTA2,LPUART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTA3,I2C1_SCL,TPM0_CH0,,,,SWD_DIO"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" ",PTA4,I2C1_SDA,TPM0_CH1,,,,Nmi_b"
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x48++0x0B
|
|
line.long 0x00 "PORT_A_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,LPUART1_RX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,,LPUART1_TX,TPM_CLKIN1,,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTA20,,,,,,Reset_b"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x80++0x07
|
|
line.long 0x00 "PORT_A_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_A_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORT_A_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_B"
|
|
tree "Pin Control Registers"
|
|
group.long 0x1000++0x0F
|
|
line.long 0x00 "PORT_B_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P0/ADC0_SE8,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,SPI1_MOSI,SPI1_MISO,,LCD_P0"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P1/ADC0_SE9,PTB1,I2C0_SDA,TPM1_CH1,SPI1_MISO,SPI1_MOSI,,LCD_P1"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P2/ADC0_SE12,PTB2,I2C0_SCL,TPM2_CH0,,,,LCD_P2"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P3/ADC0_SE13,PTB3,I2C0_SDA,TPM2_CH1,,,,LCD_P3"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x1080++0x07
|
|
line.long 0x00 "PORT_B_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_B_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "PORT_B_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_C"
|
|
tree "Pin Control Registers"
|
|
group.long 0x2000++0x1F
|
|
line.long 0x00 "PORT_C_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P20/ADC0_SE14,PTC0,,EXTRG_IN,,CMP0_OUT,,LCD_P20"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_C_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P21/ADC0_SE15,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,,,LCD_P21"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_C_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P22/ADC0_SE11,PTC2,I2C1_SDA,,TPM0_CH1,,,LCD_P22"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_C_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P23,PTC3/LLWU_P7,SPI1_SCK,LPUART1_RX,TPM0_CH2,CLKOUT,,LCD_P23"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_C_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD_P24,PTC4/LLWU_P8,SPI0_PCS0,LPUART1_TX,TPM0_CH3,SPI1_PCS0,,LCD_P24"
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_C_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "LCD_P25,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,,,CMP0_OUT,LCD_P25"
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_C_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "LCD_P26/CMP0_IN0,PTC6/LLWU_P10,SPI0_MOSI,EXTRG_IN,,SPI0_MISO,,LCD_P26"
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_C_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "LCD_P27/CMP0_IN1,PTC7,SPI0_MISO,,,SPI0_MOSI,,LCD_P27"
|
|
textline " "
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x2080++0x03
|
|
line.long 0x00 "PORT_C_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x2084++0x03
|
|
hide.long 0x00 "PORT_C_GPCHR,Global Pin Control High Register"
|
|
group.long 0x20A0++0x03
|
|
line.long 0x00 "PORT_C_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_D"
|
|
tree "Pin Control Registers"
|
|
group.long 0x3010++0x0F
|
|
line.long 0x00 "PORT_D_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P44,PTD4/LLWU_P14,SPI1_PCS0,UART2_RX,TPM0_CH4,,FXIO0_D4,LCD_P44"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_D_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Lcd_p45/adc0_se6b,PTD5,SPI1_SCK,UART2_TX,TPM0_CH5,,FXIO0_D5,LCD_P45"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_D_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Lcd_p46/adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,LPUART0_RX,I2C1_SDA,SPI1_MISO,FXIO0_D6,LCD_P46"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_D_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P47,PTD7,SPI1_MISO,LPUART0_TX,I2C1_SCL,SPI1_MOSI,FXIO0_D7,LCD_P47"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x3080++0x03
|
|
line.long 0x00 "PORT_D_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x3084++0x03
|
|
hide.long 0x00 "PORT_D_GPCHR,Global Pin Control High Register"
|
|
group.long 0x30A0++0x03
|
|
line.long 0x00 "PORT_D_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_E"
|
|
tree "Pin Control Registers"
|
|
group.long 0x4000++0x17
|
|
line.long 0x00 "PORT_E_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P48,PTE0,SPI1_MISO,LPUART1_TX,RTC_CLKOUT,CMP0_OUT,I2C1_SDA,LCD_P48"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P49,PTE1,SPI1_MOSI,LPUART1_RX,,SPI1_MISO,I2C1_SCL,LCD_P49"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4040++0x0F
|
|
line.long 0x00 "PORT_E_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P55/ADC0_DP1/ADC0_SE1,PTE16,SPI0_PCS0,UART2_TX,TPM_CLKIN0,,FXIO0_D0,LCD_P55"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Lcd_p56/adc0_dm1/adc0_se5a,PTE17,SPI0_SCK,UART2_RX,TPM_CLKIN1,LPTMR0_ALT3,FXIO0_D1,LCD_P56"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P57/ADC0_DP2/ADC0_SE2,PTE18,SPI0_MOSI,,I2C0_SDA,SPI0_MISO,FXIO0_D2,LCD_P57"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_E_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Lcd_p58/adc0_dm2/adc0_se6a,PTE19,SPI0_MISO,,I2C0_SCL,SPI0_MOSI,FXIO0_D3,LCD_P58"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4050++0x07
|
|
line.long 0x00 "PORT_E_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P59/ADC0_DP0/ADC0_SE0,PTE20,,TPM1_CH0,LPUART0_TX,,FXIO0_D4,LCD_P59"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR21,Pin Control Register 21"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Lcd_p60/adc0_dm0/adc0_se4a,PTE21,,TPM1_CH1,LPUART0_RX,,FXIO0_D5,LCD_P60"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4060++0x07
|
|
line.long 0x00 "PORT_E_PCR24,Pin Control Register 24"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTE24,,TPM0_CH0,,I2C0_SCL,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR25,Pin Control Register 25"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTE25,,TPM0_CH1,,I2C0_SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4074++0x07
|
|
line.long 0x00 "PORT_E_PCR29,Pin Control Register 29"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Cmp0_in5/adc0_se4b,PTE29,,TPM0_CH2,TPM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR30,Pin Control Register 30"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DAC0_OUT/ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,LPUART1_TX,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x4080++0x07
|
|
line.long 0x00 "PORT_E_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_E_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 30. " GPWE30 ,Global pin 30 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 29. " GPWE29 ,Global pin 29 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 25. " GPWE25 ,Global pin 25 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 24. " GPWE24 ,Global pin 24 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 21. " GPWE21 ,Global pin 21 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x40A0++0x03
|
|
line.long 0x00 "PORT_E_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 30. " ISF30 ,Interrupt status flag 30 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 29. " ISF29 ,Interrupt status flag 29 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 25. " ISF25 ,Interrupt status flag 25 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 24. " ISF24 ,Interrupt status flag 24 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " ISF21 ,Interrupt status flag 21 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 161 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
width 0x0B
|
|
endif
|
|
width 0x0B
|
|
elif cpuis("MKL46*")||cpuis("MKL43Z*")
|
|
width 12.
|
|
sif cpuis("MKL4*VLH*")||cpuis("MKL4*VMP*")
|
|
width 14.
|
|
tree "PORT_A"
|
|
tree "Pin Control Registers"
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "PORT_A_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTA0,,TPM0_CH5,,,,SWD_CLK"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH1,PTA0,,TPM0_CH5,,,,SWD_CLK"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTA1,LPUART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH2,PTA1,UART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTA2,LPUART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "TSI0_CH3,PTA2,UART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTA3,I2C1_SCL,TPM0_CH0,,,,SWD_DIO"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "TSI0_CH4,PTA3,I2C1_SCL,TPM0_CH0,,,,SWD_DIO"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" ",PTA4,I2C1_SDA,TPM0_CH1,,,,Nmi_b"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "TSI0_CH5,PTA4,I2C1_SDA,TPM0_CH1,,,,Nmi_b"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_A_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA5,USB_CLKIN,TPM0_CH2,,,I2S0_TX_BCLK,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "PORT_A_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTA12,,TPM1_CH0,,,I2S0_TXD0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA13,,TPM1_CH1,,,I2S0_TX_FS,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x48++0x0B
|
|
line.long 0x00 "PORT_A_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,LPUART1_RX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,UART1_RX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,,LPUART1_TX,TPM_CLKIN1,,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,,UART1_TX,TPM_CLKIN1,,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA20,,,,,,Reset_b"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x80++0x07
|
|
line.long 0x00 "PORT_A_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 29. " GPWE13 ,Global pin 13 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 28. " GPWE12 ,Global pin 12 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_A_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORT_A_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " ISF13 ,Interrupt status flag 13 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " ISF12 ,Interrupt status flag 12 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_B"
|
|
tree "Pin Control Registers"
|
|
group.long 0x1000++0x0F
|
|
line.long 0x00 "PORT_B_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P0/ADC0_SE8,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,,,,LCD_P0"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P0/ADC0_SE8/TSI0_CH0,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,,,,LCD_P0"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P1/ADC0_SE9,PTB1,I2C0_SDA,TPM1_CH1,,,,LCD_P1"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P1/ADC0_SE9/TSI0_CH6,PTB1,I2C0_SDA,TPM1_CH1,,,,LCD_P1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P2/ADC0_SE12,PTB2,I2C0_SCL,TPM2_CH0,,,,LCD_P2"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P2/ADC0_SE12/TSI0_CH7,PTB2,I2C0_SCL,TPM2_CH0,,,,LCD_P2"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P3/ADC0_SE13,PTB3,I2C0_SDA,TPM2_CH1,,,,LCD_P3"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P3/ADC0_SE13/TSI0_CH8,PTB3,I2C0_SDA,TPM2_CH1,,,,LCD_P3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x1040++0x0F
|
|
line.long 0x00 "PORT_B_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P12,PTB16,SPI1_MOSI,LPUART0_RX,TPM_CLKIN0,SPI1_MISO,,LCD_P12"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P12/TSI0_CH9,PTB16,SPI1_MOSI,UART0_RX,TPM_CLKIN0,SPI1_MISO,,LCD_P12"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P13,PTB17,SPI1_MISO,LPUART0_TX,TPM_CLKIN1,SPI1_MOSI,,LCD_P13"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P13/TSI0_CH10,PTB17,SPI1_MISO,UART0_TX,TPM_CLKIN1,SPI1_MOSI,,LCD_P13"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P14,PTB18,,TPM2_CH0,I2S0_TX_BCLK,,,LCD_P14"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P14/TSI0_CH11,PTB18,,TPM2_CH0,I2S0_TX_BCLK,,,LCD_P14"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P15,PTB19,,TPM2_CH1,I2S0_TX_FS,,,LCD_P15"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P15/TSI0_CH12,PTB19,,TPM2_CH1,I2S0_TX_FS,,,LCD_P15"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x1080++0x07
|
|
line.long 0x00 "PORT_B_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_B_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "PORT_B_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_C"
|
|
tree "Pin Control Registers"
|
|
group.long 0x2000++0x1F
|
|
line.long 0x00 "PORT_C_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P20/ADC0_SE14,PTC0,,EXTRG_IN,Audiousb_sof_out,CMP0_OUT,I2S0_TXD0,LCD_P20"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P20/ADC0_SE14/TSI0_CH13,PTC0,,EXTRG_IN,Audiousb_sof_out,CMP0_OUT,I2S0_TXD0,LCD_P20"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_C_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P21/ADC0_SE15,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,,I2S0_TXD0,LCD_P21"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P21/ADC0_SE15/TSI0_CH14,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,,I2S0_TXD0,LCD_P21"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_C_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P22/ADC0_SE11,PTC2,I2C1_SDA,,TPM0_CH1,,I2S0_TX_FS,LCD_P22"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P22/ADC0_SE11/TSI0_CH15,PTC2,I2C1_SDA,,TPM0_CH1,,I2S0_TX_FS,LCD_P22"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_C_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P23,PTC3/LLWU_P7,SPI1_SCK,LPUART1_RX,TPM0_CH2,CLKOUT,I2S0_TX_BCLK,LCD_P23"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P23,PTC3/LLWU_P7,,UART1_RX,TPM0_CH2,CLKOUT,I2S0_TX_BCLK,LCD_P23"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_C_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD_P24,PTC4/LLWU_P8,SPI0_SS,LPUART1_TX,TPM0_CH3,I2S0_MCLK,,LCD_P24"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD_P24,PTC4/LLWU_P8,SPI0_PCS0,UART1_TX,TPM0_CH3,I2S0_MCLK,,LCD_P24"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_C_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "LCD_P25,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,I2S0_RXD0,,CMP0_OUT,LCD_P25"
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_C_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "LCD_P26/CMP0_IN0,PTC6/LLWU_P10,SPI0_MOSI,EXTRG_IN,I2S0_RX_BCLK,SPI0_MISO,I2S0_MCLK,LCD_P26"
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_C_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "LCD_P27/CMP0_IN1,PTC7,SPI0_MISO,Audiousb_sof_out,I2S0_RX_FS,SPI0_MOSI,,LCD_P27"
|
|
textline " "
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x2080++0x03
|
|
line.long 0x00 "PORT_C_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x2084++0x03
|
|
hide.long 0x00 "PORT_C_GPCHR,Global Pin Control High Register"
|
|
group.long 0x20A0++0x03
|
|
line.long 0x00 "PORT_C_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_D"
|
|
tree "Pin Control Registers"
|
|
group.long 0x3000++0x1F
|
|
line.long 0x00 "PORT_D_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P40,PTD0,SPI0_SS,,TPM0_CH0,,FXIO0_D0,LCD_P40"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P40,PTD0,SPI0_PCS0,,TPM0_CH0,,,LCD_P40"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_D_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Lcd_p41/adc0_se5b,PTD1,SPI0_SCK,,TPM0_CH1,,FXIO0_D1,LCD_P41"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Lcd_p41/adc0_se5b,PTD1,SPI0_SCK,,TPM0_CH1,,,LCD_P41"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_D_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P42,PTD2,SPI0_MOSI,UART2_RX,TPM0_CH2,SPI0_MISO,FXIO0_D2,LCD_P42"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P42,PTD2,SPI0_MOSI,UART2_RX,TPM0_CH2,SPI0_MISO,,LCD_P42"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_D_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P43,PTD3,SPI0_MISO,UART2_TX,TPM0_CH3,SPI0_MOSI,FXIO0_D3,LCD_P43"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P43,PTD3,SPI0_MISO,UART2_TX,TPM0_CH3,SPI0_MOSI,,LCD_P43"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_D_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD_P44,PTD4/LLWU_P14,SPI1_SS,UART2_RX,TPM0_CH4,,FXIO0_D4,LCD_P44"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD_P44,PTD4/LLWU_P14,SPI1_PCS0,UART2_RX,TPM0_CH4,,,LCD_P44"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_D_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Lcd_p45/adc0_se6b,PTD5,SPI1_SCK,UART2_TX,TPM0_CH5,,FXIO0_D5,LCD_P45"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Lcd_p45/adc0_se6b,PTD5,SPI1_SCK,UART2_TX,TPM0_CH5,,,LCD_P45"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_D_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Lcd_p46/adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,LPUART0_RX,,SPI1_MISO,FXIO0_D6,LCD_P46"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Lcd_p46/adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,UART0_RX,,SPI1_MISO,,LCD_P46"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_D_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "LCD_P47,PTD7,SPI1_MISO,LPUART0_TX,,SPI1_MOSI,FXIO0_D7,LCD_P47"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "LCD_P47,PTD7,SPI1_MISO,UART0_TX,,SPI1_MOSI,,LCD_P47"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x3080++0x03
|
|
line.long 0x00 "PORT_D_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x3084++0x03
|
|
hide.long 0x00 "PORT_D_GPCHR,Global Pin Control High Register"
|
|
group.long 0x30A0++0x03
|
|
line.long 0x00 "PORT_D_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_E"
|
|
tree "Pin Control Registers"
|
|
group.long 0x4000++0x07
|
|
line.long 0x00 "PORT_E_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P48,PTE0/CLKOUT32K,SPI1_MISO,LPUART1_TX,RTC_CLKOUT,CMP0_OUT,I2C1_SDA,LCD_P48"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P48,PTE0,SPI1_MISO,UART1_TX,RTC_CLKOUT,CMP0_OUT,I2C1_SDA,LCD_P48"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P49,PTE1,SPI1_MOSI,LPUART1_RX,,SPI1_MISO,I2C1_SCL,LCD_P49"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P49,PTE1,SPI1_MOSI,UART1_RX,,SPI1_MISO,I2C1_SCL,LCD_P49"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4050++0x17
|
|
line.long 0x00 "PORT_E_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P59/ADC0_DP0/ADC0_SE0,PTE20,,TPM1_CH0,LPUART0_TX,,FXIO0_D4,LCD_P59"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P59/ADC0_DP0/ADC0_SE0,PTE20,,TPM1_CH0,UART0_TX,,,LCD_P59"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR21,Pin Control Register 21"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Lcd_p60/adc0_dm0/adc0_se4a,PTE21,,TPM1_CH1,LPUART0_RX,,FXIO0_D5,LCD_P60"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Lcd_p60/adc0_dm0/adc0_se4a,PTE21,,TPM1_CH1,UART0_RX,,,LCD_P60"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR22,Pin Control Register 22"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_DP3/ADC0_SE3,PTE22,,TPM2_CH0,UART2_TX,,FXIO0_D6,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_DP3/ADC0_SE3,PTE22,,TPM2_CH0,UART2_TX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_E_PCR23,Pin Control Register 23"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_dm3/adc0_se7a,PTE23,,TPM2_CH1,UART2_RX,,FXIO0_D7,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_dm3/adc0_se7a,PTE23,,TPM2_CH1,UART2_RX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_E_PCR24,Pin Control Register 24"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTE24,,TPM0_CH0,,I2C0_SCL,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_E_PCR25,Pin Control Register 25"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTE25,,TPM0_CH1,,I2C0_SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4074++0x0B
|
|
line.long 0x00 "PORT_E_PCR29,Pin Control Register 29"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Cmp0_in5/adc0_se4b,PTE29,,TPM0_CH2,TPM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR30,Pin Control Register 30"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
sif cpuis("MKL43Z*MP4")||cpuis("MKL43Z*LH4")
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DAC0_OUT/ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,LPUART1_TX,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DAC0_OUT/ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR31,Pin Control Register 31"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTE31,,TPM0_CH4,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x4080++0x07
|
|
line.long 0x00 "PORT_E_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_E_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 31. " GPWE31 ,Global pin 31 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 30. " GPWE30 ,Global pin 30 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 29. " GPWE29 ,Global pin 29 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 25. " GPWE25 ,Global pin 25 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 24. " GPWE24 ,Global pin 24 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 23. " GPWE23 ,Global pin 23 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 22. " GPWE22 ,Global pin 22 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 21. " GPWE21 ,Global pin 21 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x40A0++0x03
|
|
line.long 0x00 "PORT_E_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 31. " ISF31 ,Interrupt status flag 31 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " ISF30 ,Interrupt status flag 30 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 29. " ISF29 ,Interrupt status flag 29 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " ISF25 ,Interrupt status flag 25 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " ISF24 ,Interrupt status flag 24 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 23. " ISF23 ,Interrupt status flag 23 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 22. " ISF22 ,Interrupt status flag 22 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " ISF21 ,Interrupt status flag 21 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL4*VLL*")||cpuis("MKL4*VMC*")
|
|
width 14.
|
|
tree "PORT_A"
|
|
tree "Pin Control Registers"
|
|
group.long 0x00++0x1F
|
|
line.long 0x00 "PORT_A_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH1,PTA0,,TPM0_CH5,,,,SWD_CLK"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH2,PTA1,UART0_RX,TPM2_CH0,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "TSI0_CH3,PTA2,UART0_TX,TPM2_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "TSI0_CH4,PTA3,I2C1_SCL,TPM0_CH0,,,,SWD_DIO"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "TSI0_CH5,PTA4,I2C1_SDA,TPM0_CH1,,,,Nmi_b"
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_A_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA5,USB_CLKIN,TPM0_CH2,,,I2S0_TX_BCLK,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_A_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Disabled,PTA6,,TPM0_CH3,?..."
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_A_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "Disabled,PTA7,,TPM0_CH4,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x30++0x17
|
|
line.long 0x00 "PORT_A_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTA12,,TPM1_CH0,,,I2S0_TXD0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA13,,TPM1_CH1,,,I2S0_TX_FS,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR14,Pin Control Register 14"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA14,SPI0_PCS0,UART0_TX,,,I2S0_RX_BCLK,I2S0_TXD0"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR15,Pin Control Register 15"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTA15,SPI0_SCK,UART0_RX,,,I2S0_RXD0,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTA16,SPI0_MOSI,,,SPI0_MISO,I2S0_RX_FS,I2S0_RXD0"
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_A_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA17,SPI0_MISO,,,SPI0_MOSI,I2S0_MCLK,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x48++0x0B
|
|
line.long 0x00 "PORT_A_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,UART1_RX,TPM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,,UART1_TX,TPM_CLKIN1,,LPTMR0_ALT1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA20,,,,,,Reset_b"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x80++0x07
|
|
line.long 0x00 "PORT_A_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 31. " GPWE15 ,Global pin 15 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 30. " GPWE14 ,Global pin 14 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 29. " GPWE13 ,Global pin 13 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GPWE12 ,Global pin 12 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_A_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORT_A_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 15. " ISF15 ,Interrupt status flag 15 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 14. " ISF14 ,Interrupt status flag 14 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " ISF13 ,Interrupt status flag 13 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " ISF12 ,Interrupt status flag 12 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_B"
|
|
tree "Pin Control Registers"
|
|
group.long 0x1000++0x0F
|
|
line.long 0x00 "PORT_B_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P0/ADC0_SE8/TSI0_CH0,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,,,,LCD_P0"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P1/ADC0_SE9/TSI0_CH6,PTB1,I2C0_SDA,TPM1_CH1,,,,LCD_P1"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P2/ADC0_SE12/TSI0_CH7,PTB2,I2C0_SCL,TPM2_CH0,,,,LCD_P2"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P3/ADC0_SE13/TSI0_CH8,PTB3,I2C0_SDA,TPM2_CH1,,,,LCD_P3"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x101C++0x13
|
|
line.long 0x00 "PORT_B_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P7,PTB7,,,,,,LCD_P7"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P8,PTB8,SPI1_PCS0,EXTRG_IN,,,,LCD_P8"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P9,PTB9,SPI1_SCK,,,,,LCD_P9"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P10,PTB10,SPI1_PCS0,,,,,LCD_P10"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_B_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD_P11,PTB11,SPI1_SCK,,,,,LCD_P11"
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x1040++0x1F
|
|
line.long 0x00 "PORT_B_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P12/TSI0_CH9,PTB16,SPI1_MOSI,UART0_RX,TPM_CLKIN0,SPI1_MISO,,LCD_P12"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P13/TSI0_CH10,PTB17,SPI1_MISO,UART0_TX,TPM_CLKIN1,SPI1_MOSI,,LCD_P13"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P14/TSI0_CH11,PTB18,,TPM2_CH0,I2S0_TX_BCLK,,,LCD_P14"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P15/TSI0_CH12,PTB19,,TPM2_CH1,I2S0_TX_FS,,,LCD_P15"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_B_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD_P16,PTB20,,,,,CMP0_OUT,LCD_P16"
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_B_PCR21,Pin Control Register 21"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "LCD_P17,PTB21,,,,,,LCD_P17"
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_B_PCR22,Pin Control Register 22"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "LCD_P18,PTB22,,,,,,LCD_P18"
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_B_PCR23,Pin Control Register 23"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "LCD_P19,PTB23,,,,,,LCD_P19"
|
|
textline " "
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x1080++0x07
|
|
line.long 0x00 "PORT_B_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_B_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 23. " GPWE23 ,Global pin 23 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 22. " GPWE22 ,Global pin 22 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 21. " GPWE21 ,Global pin 21 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "PORT_B_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 23. " ISF23 ,Interrupt status flag 23 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " ISF22 ,Interrupt status flag 22 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " ISF21 ,Interrupt status flag 21 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_C"
|
|
tree "Pin Control Registers"
|
|
group.long 0x2000++0x37
|
|
line.long 0x00 "PORT_C_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P20/ADC0_SE14/TSI0_CH13,PTC0,,EXTRG_IN,Audiousb_sof_out,CMP0_OUT,I2S0_TXD0,LCD_P20"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_C_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P21/ADC0_SE15/TSI0_CH14,PTC1/LLWU_P6/RTC_CLKIN,I2C1_SCL,,TPM0_CH0,,I2S0_TXD0,LCD_P21"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_C_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P22/ADC0_SE11/TSI0_CH15,PTC2,I2C1_SDA,,TPM0_CH1,,I2S0_TX_FS,LCD_P22"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_C_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P23,PTC3/LLWU_P7,,UART1_RX,TPM0_CH2,CLKOUT,I2S0_TX_BCLK,LCD_P23"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_C_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD_P24,PTC4/LLWU_P8,SPI0_PCS0,UART1_TX,TPM0_CH3,I2S0_MCLK,,LCD_P24"
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_C_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "LCD_P25,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,I2S0_RXD0,,CMP0_OUT,LCD_P25"
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_C_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "LCD_P26/CMP0_IN0,PTC6/LLWU_P10,SPI0_MOSI,EXTRG_IN,I2S0_RX_BCLK,SPI0_MISO,I2S0_MCLK,LCD_P26"
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_C_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "LCD_P27/CMP0_IN1,PTC7,SPI0_MISO,Audiousb_sof_out,I2S0_RX_FS,SPI0_MOSI,,LCD_P27"
|
|
textline " "
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x20 "PORT_C_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x20 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "LCD_P28/CMP0_IN2,PTC8,I2C0_SCL,TPM0_CH4,I2S0_MCLK,,,LCD_P28"
|
|
textline " "
|
|
bitfld.long 0x20 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x20 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x20 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x24 "PORT_C_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x24 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "LCD_P29/CMP0_IN3,PTC9,I2C0_SDA,TPM0_CH5,I2S0_RX_BCLK,,,LCD_P29"
|
|
textline " "
|
|
bitfld.long 0x24 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x24 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x24 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x28 "PORT_C_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x28 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x28 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x28 8.--10. " MUX ,Pin mux control" "LCD_P30,PTC10,I2C1_SCL,,I2S0_RX_FS,,,LCD_P30"
|
|
textline " "
|
|
bitfld.long 0x28 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x28 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x28 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x2C "PORT_C_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x2C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" "LCD_P31,PTC11,I2C1_SDA,,I2S0_RXD0,,,LCD_P31"
|
|
textline " "
|
|
bitfld.long 0x2C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x2C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x2C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x30 "PORT_C_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x30 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x30 8.--10. " MUX ,Pin mux control" "LCD_P32,PTC12,,,TPM_CLKIN0,,,LCD_P32"
|
|
textline " "
|
|
bitfld.long 0x30 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x30 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x30 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x30 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x30 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x34 "PORT_C_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x34 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x34 8.--10. " MUX ,Pin mux control" "LCD_P33,PTC13,,,TPM_CLKIN1,,,LCD_P33"
|
|
textline " "
|
|
bitfld.long 0x34 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x34 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x34 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x34 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x34 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x2040++0x0B
|
|
line.long 0x00 "PORT_C_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P36,PTC16,,,,,,LCD_P36"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_C_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P37,PTC17,,,,,,LCD_P37"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_C_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P38,PTC18,,,,,,LCD_P38"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x2080++0x07
|
|
line.long 0x00 "PORT_C_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 29. " GPWE13 ,Global pin 13 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 28. " GPWE12 ,Global pin 12 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_C_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x20A0++0x03
|
|
line.long 0x00 "PORT_C_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " ISF13 ,Interrupt status flag 13 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " ISF12 ,Interrupt status flag 12 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_D"
|
|
tree "Pin Control Registers"
|
|
group.long 0x3000++0x1F
|
|
line.long 0x00 "PORT_D_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P40,PTD0,SPI0_PCS0,,TPM0_CH0,,,LCD_P40"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_D_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Lcd_p41/adc0_se5b,PTD1,SPI0_SCK,,TPM0_CH1,,,LCD_P41"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_D_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P42,PTD2,SPI0_MOSI,UART2_RX,TPM0_CH2,SPI0_MISO,,LCD_P42"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_D_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P43,PTD3,SPI0_MISO,UART2_TX,TPM0_CH3,SPI0_MOSI,,LCD_P43"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_D_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD_P44,PTD4/LLWU_P14,SPI1_PCS0,UART2_RX,TPM0_CH4,,,LCD_P44"
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_D_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Lcd_p45/adc0_se6b,PTD5,SPI1_SCK,UART2_TX,TPM0_CH5,,,LCD_P45"
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_D_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Lcd_p46/adc0_se7b,PTD6/LLWU_P15,SPI1_MOSI,UART0_RX,,SPI1_MISO,,LCD_P46"
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_D_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "LCD_P47,PTD7,SPI1_MISO,UART0_TX,,SPI1_MOSI,,LCD_P47"
|
|
textline " "
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x3080++0x03
|
|
line.long 0x00 "PORT_D_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x3084++0x03
|
|
hide.long 0x00 "PORT_D_GPCHR,Global Pin Control High Register"
|
|
group.long 0x30A0++0x03
|
|
line.long 0x00 "PORT_D_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_E"
|
|
tree "Pin Control Registers"
|
|
group.long 0x4000++0x1B
|
|
line.long 0x00 "PORT_E_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P48,PTE0,SPI1_MISO,UART1_TX,RTC_CLKOUT,CMP0_OUT,I2C1_SDA,LCD_P48"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P49,PTE1,SPI1_MOSI,UART1_RX,,SPI1_MISO,I2C1_SCL,LCD_P49"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P50,PTE2,SPI1_SCK,,,,,LCD_P50"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_E_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P51,PTE3,SPI1_MISO,,,SPI1_MOSI,,LCD_P51"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_E_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD_P52,PTE4,SPI1_PCS0,,,,,LCD_P52"
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_E_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "LCD_P53,PTE5,,,,,,LCD_P53"
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_E_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "LCD_P54,PTE6,,,I2S0_MCLK,Audiousb_sof_out,,LCD_P54"
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4040++0x0F
|
|
line.long 0x00 "PORT_E_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P55/ADC0_DP1/ADC0_SE1,PTE16,SPI0_PCS0,UART2_TX,TPM_CLKIN0,,,LCD_P55"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Lcd_p56/adc0_dm1/adc0_se5a,PTE17,SPI0_SCK,UART2_RX,TPM_CLKIN1,,LPTMR0_ALT3,LCD_P56"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P57/ADC0_DP2/ADC0_SE2,PTE18,SPI0_MOSI,,I2C0_SDA,SPI0_MISO,,LCD_P57"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_E_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Lcd_p58/adc0_dm2/adc0_se6a,PTE19,SPI0_MISO,,I2C0_SCL,SPI0_MOSI,,LCD_P58"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4050++0x1B
|
|
line.long 0x00 "PORT_E_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P59/ADC0_DP0/ADC0_SE0,PTE20,,TPM1_CH0,UART0_TX,,,LCD_P59"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR21,Pin Control Register 21"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Lcd_p60/adc0_dm0/adc0_se4a,PTE21,,TPM1_CH1,UART0_RX,,,LCD_P60"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR22,Pin Control Register 22"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_DP3/ADC0_SE3,PTE22,,TPM2_CH0,UART2_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_E_PCR23,Pin Control Register 23"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Adc0_dm3/adc0_se7a,PTE23,,TPM2_CH1,UART2_RX,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_E_PCR24,Pin Control Register 24"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "DISABLED,PTE24,,TPM0_CH0,,I2C0_SCL,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_E_PCR25,Pin Control Register 25"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "DISABLED,PTE25,,TPM0_CH1,,I2C0_SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_E_PCR26,Pin Control Register 26"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "DISABLED,PTE26,,TPM0_CH5,,,RTC_CLKOUT,USB_CLKIN"
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x4074++0x0B
|
|
line.long 0x00 "PORT_E_PCR29,Pin Control Register 29"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Cmp0_in5/adc0_se4b,PTE29,,TPM0_CH2,TPM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR30,Pin Control Register 30"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DAC0_OUT/ADC0_SE23/CMP0_IN4,PTE30,,TPM0_CH3,TPM_CLKIN1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR31,Pin Control Register 31"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "DISABLED,PTE31,,TPM0_CH4,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x4080++0x07
|
|
line.long 0x00 "PORT_E_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_E_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 31. " GPWE31 ,Global pin 31 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 30. " GPWE30 ,Global pin 30 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 29. " GPWE29 ,Global pin 29 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 26. " GPWE26 ,Global pin 26 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 25. " GPWE25 ,Global pin 25 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 24. " GPWE24 ,Global pin 24 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 23. " GPWE23 ,Global pin 23 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 22. " GPWE22 ,Global pin 22 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 21. " GPWE21 ,Global pin 21 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x40A0++0x03
|
|
line.long 0x00 "PORT_E_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 31. " ISF31 ,Interrupt status flag 31 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " ISF30 ,Interrupt status flag 30 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 29. " ISF29 ,Interrupt status flag 29 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 26. " ISF26 ,Interrupt status flag 26 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 25. " ISF25 ,Interrupt status flag 25 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " ISF24 ,Interrupt status flag 24 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 23. " ISF23 ,Interrupt status flag 23 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " ISF22 ,Interrupt status flag 22 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " ISF21 ,Interrupt status flag 21 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
width 0x0B
|
|
endif
|
|
width 0x0B
|
|
elif cpuis("MKL81*")||cpuis("MKL82Z*")
|
|
width 12.
|
|
sif cpuis("MKL8*VLK*")
|
|
width 14.
|
|
tree "PORT_A"
|
|
tree "Pin Control Registers"
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "PORT_A_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH1,PTA0,LPUART0_CTS_b,TPM0_CH5,,FXIO0_D10,EMVSIM0_CLK,SWD_CLK"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH2,PTA1,LPUART0_RX,,,FXIO0_D11,EMVSIM0_IO,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "TSI0_CH3,PTA2,LPUART0_TX,,,FXIO0_D12,EMVSIM0_PD,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "TSI0_CH4,PTA3,LPUART0_RTS_b,TPM0_CH0,,FXIO0_D13,EMVSIM0_RST,SWD_DIO"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "TSI0_CH5,PTA4/LLWU_P3,,TPM0_CH1,,FXIO0_D14,EMVSIM0_VCCEN,Nmi_b"
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x38++0x0F
|
|
line.long 0x00 "PORT_A_PCR14,Pin Control Register 14"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTA14,SPI0_PCS0,LPUART0_TX,,FXIO0_D20,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR15,Pin Control Register 15"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA15,SPI0_SCK,LPUART0_RX,,LPUART0_RX,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA16,SPI0_SOUT,LPUART0_CTS_b,,FXIO0_D22,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTA17,SPI0_SIN,LPUART0_RTS_b,,FXIO0_D23,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x48++0x0B
|
|
line.long 0x00 "PORT_A_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,,TPM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,,,TPM_CLKIN1,,LPTMR0_ALT1/LPTMR1_ALT1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA20,,,,,,Reset_b"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x80++0x07
|
|
line.long 0x00 "PORT_A_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 31. " GPWE15 ,Global pin 15 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 30. " GPWE14 ,Global pin 14 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_A_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORT_A_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 15. " ISF15 ,Interrupt status flag 15 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " ISF14 ,Interrupt status flag 14 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_B"
|
|
tree "Pin Control Registers"
|
|
group.long 0x1000++0x07
|
|
line.long 0x00 "PORT_B_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8/TSI0_CH0,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,,,,FXIO0_D0"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9/TSI0_CH6,PTB1,I2C0_SDA,TPM1_CH1,,,,FXIO0_D1"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x0010++0x13
|
|
line.long 0x00 "PORT_B_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DISABLED,PTB4,EMVSIM1_IO,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DISABLED,PTB5,EMVSIM1_CLK,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "DISABLED,PTB6,EMVSIM1_VCCEN,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "DISABLED,PTB7,EMVSIM1_PD,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_B_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "DISABLED,PTB8,EMVSIM1_RST,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x002C++0x03
|
|
line.long 0x00 "PORT_B_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DISABLED,PTB11,SPI1_SCK,,,,,FXIO0_D5"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x1040++0x0F
|
|
line.long 0x00 "PORT_B_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH9,PTB16,SPI1_SOUT,LPUART0_RX,TPM_CLKIN0,,EWM_IN,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH10,PTB17,SPI1_SIN,LPUART0_TX,TPM_CLKIN1,,EWM_OUT_b,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "TSI0_CH11,PTB18,,TPM2_CH0,,,,FXIO0_D6"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "TSI0_CH12,PTB19,,TPM2_CH1,,,,FXIO0_D7"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x1080++0x07
|
|
line.long 0x00 "PORT_B_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_B_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "PORT_B_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_C"
|
|
tree "Pin Control Registers"
|
|
group.long 0x2000++0x37
|
|
line.long 0x00 "PORT_C_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE14/TSI0_CH13,PTC0,SPI0_PCS4,EXTRG_IN,USB0_SOF_OUT,,,FXIO0_D12"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_C_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE15/TSI0_CH14,PTC1/LLWU_P6,SPI0_PCS3,LPUART1_RTS_b,TPM0_CH0,,,FXIO0_D13"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_C_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE4b/TSI0_CH15,PTC2,SPI0_PCS2,LPUART1_CTS_b,TPM0_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_C_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "DISABLED,PTC3/LLWU_P7,SPI0_PCS1,LPUART1_RX,TPM0_CH2,CLKOUT,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_C_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "DISABLED,PTC4/LLWU_P8,SPI0_PCS0,LPUART1_TX,TPM0_CH3,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_C_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "DISABLED,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2/LPTMR1_ALT2,,,CMP0_OUT,TPM0_CH2"
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_C_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "CMP0_IN0,PTC6/LLWU_P10,SPI0_SOUT,EXTRG_IN,,,,FXIO0_D14"
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_C_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,SPI0_SIN,USB0_SOF_OUT,,,,FXIO0_D15"
|
|
textline " "
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x20 "PORT_C_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x20 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "CMP0_IN2,PTC8,,,,,,FXIO0_D16"
|
|
textline " "
|
|
bitfld.long 0x20 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x20 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x20 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x24 "PORT_C_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x24 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "CMP0_IN3,PTC9,,,,,,FXIO0_D17"
|
|
textline " "
|
|
bitfld.long 0x24 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x24 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x24 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x28 "PORT_C_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x28 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x28 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x28 8.--10. " MUX ,Pin mux control" "DISABLED,PTC10,I2C1_SCL,,,,,FXIO0_D18"
|
|
textline " "
|
|
bitfld.long 0x28 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x28 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x28 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x2C "PORT_C_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x2C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" "DISABLED,PTC11/LLWU_P11,I2C1_SDA,,,,,FXIO0_D19"
|
|
textline " "
|
|
bitfld.long 0x2C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x2C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x2C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x30 "PORT_C_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x30 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x30 8.--10. " MUX ,Pin mux control" "DISABLED,PTC12,,,TPM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x30 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x30 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x30 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x30 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x30 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x34 "PORT_C_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x34 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x34 8.--10. " MUX ,Pin mux control" "DISABLED,PTC13,,,TPM_CLKIN1,?..."
|
|
textline " "
|
|
bitfld.long 0x34 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x34 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x34 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x34 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x34 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x2040++0x07
|
|
line.long 0x00 "PORT_C_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DISABLED,PTC16,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_C_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DISABLED,PTC17,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x2080++0x03
|
|
line.long 0x00 "PORT_C_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 29. " GPWE13 ,Global pin 13 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 28. " GPWE12 ,Global pin 12 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x2084++0x03
|
|
hide.long 0x00 "PORT_C_GPCHR,Global Pin Control High Register"
|
|
group.long 0x20A0++0x03
|
|
line.long 0x00 "PORT_C_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " ISF13 ,Interrupt status flag 13 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " ISF12 ,Interrupt status flag 12 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_D"
|
|
tree "Pin Control Registers"
|
|
group.long 0x3000++0x1F
|
|
line.long 0x00 "PORT_D_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DISABLED,PTD0/LLWU_P12,SPI0_PCS0,LPUART2_RTS_b,,,,FXIO0_D22"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_D_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_se5b,PTD1,SPI0_SCK,LPUART2_CTS_b,,,,FXIO0_D23"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_D_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "DISABLED,PTD2/LLWU_P13,SPI0_SOUT,LPUART2_RX,,,,I2C0_SCL"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_D_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "DISABLED,PTD3,SPI0_SIN,LPUART2_TX,,,,I2C0_SDA"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_D_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "DISABLED,PTD4/LLWU_P14,SPI1_PCS1,LPUART0_RTS_b,TPM0_CH4,,EWM_IN,SPI1_PCS0"
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_D_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Adc0_se6b,PTD5,SPI0_PCS2,LPUART0_CTS_b,TPM0_CH5,,EWM_OUT_b,SPI1_SCK"
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_D_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Adc0_se7b,PTD6/LLWU_P15,SPI0_PCS3,LPUART0_RX,,,,SPI1_SOUT"
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_D_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "DISABLED,PTD7,,LPUART0_TX,,,,SPI1_SIN"
|
|
textline " "
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x3080++0x03
|
|
line.long 0x00 "PORT_D_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x3084++0x03
|
|
hide.long 0x00 "PORT_D_GPCHR,Global Pin Control High Register"
|
|
group.long 0x30A0++0x03
|
|
line.long 0x00 "PORT_D_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_E"
|
|
tree "Pin Control Registers"
|
|
group.long 0x4000++0x17
|
|
line.long 0x00 "PORT_E_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DISABLED,PTE0,SPI1_PCS1,LPUART1_TX,,QSPI0A_DATA3,I2C1_SDA,RTC_CLKOUT"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DISABLED,PTE1/LLWU_P0,SPI1_SCK,LPUART1_RX,,QSPI0A_SCLK,I2C1_SCL,SPI1_SIN"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "DISABLED,PTE2/LLWU_P1,SPI1_SOUT,LPUART1_CTS_b,,QSPI0A_DATA0,,SPI1_SCK"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_E_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "DISABLED,PTE3,SPI1_PCS2,LPUART1_RTS_b,,QSPI0A_DATA2,,SPI1_SOUT"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_E_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "DISABLED,PTE4/LLWU_P2,SPI1_SIN,,,QSPI0A_DATA1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_E_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "DISABLED,PTE5,SPI1_PCS0,,,QSPI0A_SS0_B,,USB0_SOF_OUT"
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x401C++0x07
|
|
line.long 0x00 "PORT_E_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DISABLED,PTE7,,,,QSPI0B_SCLK,,QSPI0A_SS1_B"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DISABLED,PTE8,,,,QSPI0B_DATA0,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
group.long 0x402C++0x03
|
|
line.long 0x00 "PORT_E_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DISABLED,PTE11,,,,QSPI0B_SS0_B,,QSPI0A_DQS"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x4080++0x07
|
|
line.long 0x00 "PORT_E_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_E_GPCHR,Global Pin Control High Register"
|
|
group.long 0x40A0++0x03
|
|
line.long 0x00 "PORT_E_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (in digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (in digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (in digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL8*VMC*")
|
|
width 14.
|
|
tree "PORT_A"
|
|
tree "Pin Control Registers"
|
|
group.long 0x00++0x1F
|
|
line.long 0x00 "PORT_A_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH1,PTA0,Lpuart0_cts_b,TPM0_CH5,,FXIO0_D10,EMVSIM0_CLK,SWD_CLK"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH2,PTA1,LPUART0_RX,,,FXIO0_D11,EMVSIM0_IO,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "TSI0_CH3,PTA2,LPUART0_TX,,,FXIO0_D12,EMVSIM0_PD,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "TSI0_CH4,PTA3,Lpuart0_rts_b,TPM0_CH0,,FXIO0_D13,EMVSIM0_RST,SWD_DIO"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "TSI0_CH5,PTA4/LLWU_P3,,TPM0_CH1,,FXIO0_D14,EMVSIM0_VCCEN,Nmi_b"
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_A_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA5,USB_CLKIN,TPM0_CH2,,FXIO0_D15,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
group.long 0x28++0x1F
|
|
line.long 0x00 "PORT_A_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTA10/LLWU_P22,,TPM2_CH0,EMVSIM1_VCCEN,FXIO0_D16,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Disabled,PTA11/LLWU_P23,,TPM2_CH1,,FXIO0_D17,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA12,,TPM1_CH0,,FXIO0_D18,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_A_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "Disabled,PTA13/LLWU_P4,,TPM1_CH1,,FXIO0_D19,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_A_PCR14,Pin Control Register 14"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "Disabled,PTA14,SPI0_PCS0,LPUART0_TX,,FXIO0_D20,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_A_PCR15,Pin Control Register 15"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Disabled,PTA15,SPI0_SCK,LPUART0_RX,,LPUART0_RX,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_A_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Disabled,PTA16,SPI0_SOUT,Lpuart0_cts_b,,FXIO0_D22,?..."
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_A_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "Disabled,PTA17,SPI0_SIN,Lpuart0_rts_b,,FXIO0_D23,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
group.long 0x48++0x0B
|
|
line.long 0x00 "PORT_A_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,,TPM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_A_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,,,TPM_CLKIN1,,LPTMR0_ALT1/LPTMR1_ALT1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_A_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Disabled,PTA20,,,,,,Reset_b"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "PORT_A_PCR18,Pin Control Register 29"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,PTA29,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x80++0x07
|
|
line.long 0x00 "PORT_A_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 31. " GPWE15 ,Global pin 15 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 30. " GPWE14 ,Global pin 14 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 29. " GPWE13 ,Global pin 13 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GPWE12 ,Global pin 12 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_A_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PORT_A_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 29. " ISF29 ,Interrupt status flag 29 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (In digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 15. " ISF15 ,Interrupt status flag 15 (In digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 14. " ISF14 ,Interrupt status flag 14 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " ISF13 ,Interrupt status flag 13 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " ISF12 ,Interrupt status flag 12 (In digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (In digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (In digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (In digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_B"
|
|
tree "Pin Control Registers"
|
|
group.long 0x1000++0x1B
|
|
line.long 0x00 "PORT_B_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8/TSI0_CH0,PTB0/LLWU_P5,I2C0_SCL,TPM1_CH0,,,,FXIO0_D0"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9/TSI0_CH6,PTB1,I2C0_SDA,TPM1_CH1,,,,FXIO0_D1"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE12/TSI0_CH7,PTB2,I2C0_SCL,Lpuart0_rts_b,,,,FXIO0_D2"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_SE13/TSI0_CH8,PTB3,I2C0_SDA,Lpuart0_cts_b,,,,FXIO0_D3"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_B_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "DISABLED,PTB4,EMVSIM1_IO,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_B_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "DISABLED,PTB5,EMVSIM1_CLK,?..."
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_B_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "DISABLED,PTB6,EMVSIM1_VCCEN,?..."
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
group.long 0x101C++0x13
|
|
line.long 0x00 "PORT_B_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DISABLED,PTB7,EMVSIM1_PD,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DISABLED,PTB8,EMVSIM1_RST,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "DISABLED,PTB9,SPI1_PCS1,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "DISABLED,PTB10,SPI1_PCS0,,,,,FXIO0_D4"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_B_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "DISABLED,PTB11,SPI1_SCK,,,,,FXIO0_D5"
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
group.long 0x1040++0x1F
|
|
line.long 0x00 "PORT_B_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "TSI0_CH9,PTB16,SPI1_SOUT,LPUART0_RX,TPM_CLKIN0,,EWM_IN,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_B_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "TSI0_CH10,PTB17,SPI1_SIN,LPUART0_TX,TPM_CLKIN1,,Ewm_out_b,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_B_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "TSI0_CH11,PTB18,,TPM2_CH0,,,,FXIO0_D6"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_B_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "TSI0_CH12,PTB19,,TPM2_CH1,,,,FXIO0_D7"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_B_PCR20,Pin Control Register 20"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "DISABLED,PTB20,,,,,CMP0_OUT,FXIO0_D8"
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_B_PCR21,Pin Control Register 21"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "DISABLED,PTB21,,,,,,FXIO0_D9"
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_B_PCR22,Pin Control Register 22"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "DISABLED,PTB22,,,,,,FXIO0_D10"
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_B_PCR23,Pin Control Register 23"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "DISABLED,PTB23,,SPI0_PCS5,,,,FXIO0_D11"
|
|
textline " "
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x1080++0x07
|
|
line.long 0x00 "PORT_B_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_B_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 23. " GPWE23 ,Global pin 23 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 22. " GPWE22 ,Global pin 22 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 21. " GPWE21 ,Global pin 21 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "PORT_B_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 23. " ISF23 ,Interrupt status flag 23 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " ISF22 ,Interrupt status flag 22 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " ISF21 ,Interrupt status flag 21 (In digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (In digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11 (In digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8 (In digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (In digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (In digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (In digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_C"
|
|
tree "Pin Control Registers"
|
|
group.long 0x2000++0x3F
|
|
line.long 0x00 "PORT_C_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE14/TSI0_CH13,PTC0,SPI0_PCS4,EXTRG_IN,USB0_SOF_OUT,,,FXIO0_D12"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_C_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE15/TSI0_CH14,PTC1/LLWU_P6,SPI0_PCS3,Lpuart1_rts_b,TPM0_CH0,,,FXIO0_D13"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_C_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "Adc0_se4b/tsi0_ch15,PTC2,SPI0_PCS2,Lpuart1_cts_b,TPM0_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_C_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "DISABLED,PTC3/LLWU_P7,SPI0_PCS1,LPUART1_RX,TPM0_CH2,CLKOUT,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_C_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "DISABLED,PTC4/LLWU_P8,SPI0_PCS0,LPUART1_TX,TPM0_CH3,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_C_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "DISABLED,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2/LPTMR1_ALT2,,,CMP0_OUT,TPM0_CH2"
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_C_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "CMP0_IN0,PTC6/LLWU_P10,SPI0_SOUT,EXTRG_IN,,,,FXIO0_D14"
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_C_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,SPI0_SIN,USB0_SOF_OUT,,,,FXIO0_D15"
|
|
textline " "
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x20 "PORT_C_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x20 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "CMP0_IN2,PTC8,,,,,,FXIO0_D16"
|
|
textline " "
|
|
bitfld.long 0x20 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x20 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x20 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x24 "PORT_C_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x24 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "CMP0_IN3,PTC9,,,,,,FXIO0_D17"
|
|
textline " "
|
|
bitfld.long 0x24 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x24 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x24 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x28 "PORT_C_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x28 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x28 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x28 8.--10. " MUX ,Pin mux control" "DISABLED,PTC10,I2C1_SCL,,,,,FXIO0_D18"
|
|
textline " "
|
|
bitfld.long 0x28 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x28 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x28 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x2C "PORT_C_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x2C 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" "DISABLED,PTC11/LLWU_P11,I2C1_SDA,,,,,FXIO0_D19"
|
|
textline " "
|
|
bitfld.long 0x2C 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x2C 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x2C 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x30 "PORT_C_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x30 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x30 8.--10. " MUX ,Pin mux control" "DISABLED,PTC12,,,TPM_CLKIN0,?..."
|
|
textline " "
|
|
bitfld.long 0x30 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x30 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x30 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x30 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x30 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x34 "PORT_C_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x34 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x34 8.--10. " MUX ,Pin mux control" "DISABLED,PTC13,,,TPM_CLKIN1,?..."
|
|
textline " "
|
|
bitfld.long 0x34 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x34 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x34 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x34 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x34 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x38 "PORT_C_PCR14,Pin Control Register 14"
|
|
eventfld.long 0x38 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x38 8.--10. " MUX ,Pin mux control" "DISABLED,PTC14,,,,,,FXIO0_D20"
|
|
textline " "
|
|
bitfld.long 0x38 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x38 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x38 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x38 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x38 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x3C "PORT_C_PCR15,Pin Control Register 15"
|
|
eventfld.long 0x3C 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x3C 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x3C 8.--10. " MUX ,Pin mux control" "DISABLED,PTC15,,,,,,FXIO0_D21"
|
|
textline " "
|
|
bitfld.long 0x3C 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x3C 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x3C 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x3C 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x3C 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
group.long 0x2040++0x0F
|
|
line.long 0x00 "PORT_C_PCR16,Pin Control Register 16"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DISABLED,PTC16,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_C_PCR17,Pin Control Register 17"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DISABLED,PTC17,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_C_PCR18,Pin Control Register 18"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "DISABLED,PTC18,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_C_PCR19,Pin Control Register 19"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "DISABLED,PTC19,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x2080++0x07
|
|
line.long 0x00 "PORT_C_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 31. " GPWE15 ,Global pin 15 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 30. " GPWE14 ,Global pin 14 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 29. " GPWE13 ,Global pin 13 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 28. " GPWE12 ,Global pin 12 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_C_GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable"
|
|
bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data"
|
|
group.long 0x20A0++0x03
|
|
line.long 0x00 "PORT_C_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18 (In digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 15. " ISF15 ,Interrupt status flag 15 (In digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 14. " ISF14 ,Interrupt status flag 14 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " ISF13 ,Interrupt status flag 13 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " ISF12 ,Interrupt status flag 12 (In digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9 (In digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (In digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (In digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (In digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_D"
|
|
tree "Pin Control Registers"
|
|
group.long 0x3000++0x3F
|
|
line.long 0x00 "PORT_D_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DISABLED,PTD0/LLWU_P12,SPI0_PCS0,Lpuart2_rts_b,,,,FXIO0_D22"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_D_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "Adc0_se5b,PTD1,SPI0_SCK,Lpuart2_cts_b,,,,FXIO0_D23"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_D_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "DISABLED,PTD2/LLWU_P13,SPI0_SOUT,LPUART2_RX,,,,I2C0_SCL"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_D_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "DISABLED,PTD3,SPI0_SIN,LPUART2_TX,,,,I2C0_SDA"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_D_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "DISABLED,PTD4/LLWU_P14,SPI1_PCS1,Lpuart0_rts_b,TPM0_CH4,,EWM_IN,SPI1_PCS0"
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_D_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "Adc0_se6b,PTD5,SPI0_PCS2,Lpuart0_cts_b,TPM0_CH5,,Ewm_out_b,SPI1_SCK"
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_D_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "Adc0_se7b,PTD6/LLWU_P15,SPI0_PCS3,LPUART0_RX,,,,SPI1_SOUT"
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_D_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "DISABLED,PTD7,,LPUART0_TX,,,,SPI1_SIN"
|
|
textline " "
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x20 "PORT_D_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x20 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "DISABLED,PTD8/LLWU_P24,I2C0_SCL,,,,,FXIO0_D24"
|
|
textline " "
|
|
bitfld.long 0x20 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x20 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x20 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x24 "PORT_D_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x24 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "DISABLED,PTD9,I2C0_SDA,,,,,FXIO0_D25"
|
|
textline " "
|
|
bitfld.long 0x24 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x24 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x24 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x28 "PORT_D_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x28 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x28 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x28 8.--10. " MUX ,Pin mux control" "DISABLED,PTD10,,,,,,FXIO0_D26"
|
|
textline " "
|
|
bitfld.long 0x28 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x28 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x28 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x2C "PORT_D_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x2C 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" "DISABLED,PTD11/LLWU_P25,,,,,,FXIO0_D27"
|
|
textline " "
|
|
bitfld.long 0x2C 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x2C 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x2C 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x30 "PORT_D_PCR12,Pin Control Register 12"
|
|
eventfld.long 0x30 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x30 8.--10. " MUX ,Pin mux control" "DISABLED,PTD12,,,,,,FXIO0_D28"
|
|
textline " "
|
|
bitfld.long 0x30 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x30 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x30 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x30 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x30 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x34 "PORT_D_PCR13,Pin Control Register 13"
|
|
eventfld.long 0x34 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x34 8.--10. " MUX ,Pin mux control" "DISABLED,PTD13,,,,,,FXIO0_D29"
|
|
textline " "
|
|
bitfld.long 0x34 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x34 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x34 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x34 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x34 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x38 "PORT_D_PCR14,Pin Control Register 14"
|
|
eventfld.long 0x38 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x38 8.--10. " MUX ,Pin mux control" "DISABLED,PTD14,,,,,,FXIO0_D30"
|
|
textline " "
|
|
bitfld.long 0x38 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x38 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x38 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x38 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x38 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x3C "PORT_D_PCR15,Pin Control Register 15"
|
|
eventfld.long 0x3C 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x3C 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x3C 8.--10. " MUX ,Pin mux control" "DISABLED,PTD15,,,,,,FXIO0_D31"
|
|
textline " "
|
|
bitfld.long 0x3C 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x3C 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x3C 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x3C 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x3C 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x3080++0x03
|
|
line.long 0x00 "PORT_D_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 31. " GPWE15 ,Global pin 15 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 30. " GPWE14 ,Global pin 14 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 29. " GPWE13 ,Global pin 13 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 28. " GPWE12 ,Global pin 12 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
hgroup.long 0x3084++0x03
|
|
hide.long 0x00 "PORT_D_GPCHR,Global Pin Control High Register"
|
|
group.long 0x30A0++0x03
|
|
line.long 0x00 "PORT_D_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 15. " ISF15 ,Interrupt status flag 15 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " ISF14 ,Interrupt status flag 14 (In digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " ISF13 ,Interrupt status flag 13 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " ISF12 ,Interrupt status flag 12 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11 (In digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8 (In digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (In digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (In digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (In digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "PORT_E"
|
|
tree "Pin Control Registers"
|
|
group.long 0x4000++0x2F
|
|
line.long 0x00 "PORT_E_PCR0,Pin Control Register 0"
|
|
eventfld.long 0x00 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "DISABLED,PTE0,SPI1_PCS1,LPUART1_TX,,QSPI0A_DATA3,I2C1_SDA,RTC_CLKOUT"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x00 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x04 "PORT_E_PCR1,Pin Control Register 1"
|
|
eventfld.long 0x04 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DISABLED,PTE1/LLWU_P0,SPI1_SCK,LPUART1_RX,,QSPI0A_SCLK,I2C1_SCL,SPI1_SIN"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x04 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x08 "PORT_E_PCR2,Pin Control Register 2"
|
|
eventfld.long 0x08 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "DISABLED,PTE2/LLWU_P1,SPI1_SOUT,Lpuart1_cts_b,,QSPI0A_DATA0,,SPI1_SCK"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x08 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x0C "PORT_E_PCR3,Pin Control Register 3"
|
|
eventfld.long 0x0C 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "DISABLED,PTE3,SPI1_PCS2,Lpuart1_rts_b,,QSPI0A_DATA2,,SPI1_SOUT"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x0C 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x10 "PORT_E_PCR4,Pin Control Register 4"
|
|
eventfld.long 0x10 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "DISABLED,PTE4/LLWU_P2,SPI1_SIN,,,QSPI0A_DATA1,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x10 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x14 "PORT_E_PCR5,Pin Control Register 5"
|
|
eventfld.long 0x14 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "DISABLED,PTE5,SPI1_PCS0,,,QSPI0A_SS0_B,,USB0_SOF_OUT"
|
|
textline " "
|
|
bitfld.long 0x14 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x14 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x14 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x18 "PORT_E_PCR6,Pin Control Register 6"
|
|
eventfld.long 0x18 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "DISABLED,PTE6/LLWU_P16,SPI1_PCS3,,,QSPI0B_DATA3,?..."
|
|
textline " "
|
|
bitfld.long 0x18 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x18 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x18 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x1C "PORT_E_PCR7,Pin Control Register 7"
|
|
eventfld.long 0x1C 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "DISABLED,PTE7,,,,QSPI0B_SCLK,QSPI0A_SS1_B,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x1C 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x20 "PORT_E_PCR8,Pin Control Register 8"
|
|
eventfld.long 0x20 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x20 8.--10. " MUX ,Pin mux control" "DISABLED,PTE8,,,,QSPI0B_DATA0,?..."
|
|
textline " "
|
|
bitfld.long 0x20 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x20 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x20 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x24 "PORT_E_PCR9,Pin Control Register 9"
|
|
eventfld.long 0x24 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x24 8.--10. " MUX ,Pin mux control" "DISABLED,PTE9/LLWU_P17,,,,QSPI0B_DATA2,?..."
|
|
textline " "
|
|
bitfld.long 0x24 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x24 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x24 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x28 "PORT_E_PCR10,Pin Control Register 10"
|
|
eventfld.long 0x28 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x28 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x28 8.--10. " MUX ,Pin mux control" "DISABLED,PTE10/LLWU_P18,,,,QSPI0B_DATA1,?..."
|
|
textline " "
|
|
bitfld.long 0x28 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x28 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x28 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x28 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
line.long 0x2C "PORT_E_PCR11,Pin Control Register 11"
|
|
eventfld.long 0x2C 24. " ISF ,Interrupt status flag (In digital modes only)" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 16.--19. " IRQC ,Interrupt / DMA request configuration (In digital modes only)" "Disabled,DMA req on rising edge,DMA req on falling edge,DMA req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..."
|
|
textline " "
|
|
bitfld.long 0x2C 8.--10. " MUX ,Pin mux control" "DISABLED,PTE11,,,,QSPI0B_SS0_B,,QSPI0A_DQS"
|
|
textline " "
|
|
bitfld.long 0x2C 6. " DSE ,Drive strength enable (In digital modes only)" "Low,High"
|
|
bitfld.long 0x2C 4. " PFE ,Passive filter enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 2. " SRE ,Slew rate enable (In digital modes only)" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x2C 1. " PE ,Pull enable (In digital modes only)" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0. " PS ,Pull select (In digital modes only)" "Down,Up"
|
|
tree.end
|
|
textline " "
|
|
wgroup.long 0x4080++0x07
|
|
line.long 0x00 "PORT_E_GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable"
|
|
bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data"
|
|
line.long 0x04 "PORT_E_GPCHR,Global Pin Control High Register"
|
|
group.long 0x40A0++0x03
|
|
line.long 0x00 "PORT_E_ISFR,Interrupt Status Flag Register"
|
|
eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9 (In digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6 (In digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3 (In digital modes only)" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1 (In digital modes only)" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0 (In digital modes only)" "No interrupt,Interrupt"
|
|
tree.end
|
|
width 0x0B
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
tree "SIM (System Integration Module)"
|
|
sif cpuis("MKL28*")
|
|
base ad:0x40074000
|
|
width 10.
|
|
sif !cpuis("MKL02*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SOPT1,System Options Register"
|
|
sif cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL43Z*")||cpuis("MKL46*")||cpuis("MKL27Z128*")||cpuis("MKL27Z256*")||cpuis("MKL28*")
|
|
bitfld.long 0x00 31. " USBREGEN ,USB voltage regulator enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " USBSSTBY ,USB voltage regulator during stop" "No standby,Standby"
|
|
bitfld.long 0x00 29. " USBVSTBY ,USB voltage regulator during VLPR and VLPW modes" "No standby,Standby"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18.--19. " OSC32KSEL ,32K oscillator clock select" "OSC32KCLK,,RTC_CLKIN,LPO 1khz"
|
|
sif cpuis("MKL03*")
|
|
newline
|
|
bitfld.long 0x00 16.--17. " OSC32KOUT ,32K oscillator clock output" "No output,PTB13,?..."
|
|
elif cpuis("MKL17Z32*")||cpuis("MKL17Z64*")||cpuis("MKL27Z32*")||cpuis("MKL27Z64*")||cpuis("MKL13*")||cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
newline
|
|
bitfld.long 0x00 16.--17. " OSC32KOUT ,32K oscillator clock output" "No output,PTE0,?..."
|
|
elif cpuis("MKL17Z*")||cpuis("MKL27Z128*")||cpuis("MKL27Z256*")||cpuis("MKL33Z128*")||cpuis("MKL33Z256*")
|
|
newline
|
|
bitfld.long 0x00 16.--17. " OSC32KOUT ,32K oscillator clock output" "No output,PTE0,PTE26,?..."
|
|
elif cpuis("MKL82Z*")
|
|
newline
|
|
bitfld.long 0x00 12.--15. " RAMSIZE ,System RAM Size" ",8KB,,16KB,24KB,32KB,48KB,64KB,96KB,128KB,256KB,?..."
|
|
endif
|
|
sif !cpuis("MKL82*")
|
|
sif cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL27Z128*")||cpuis("MKL27Z256*")||cpuis("MKL28*")||cpuis("MKL43Z*")||cpuis("MKL46*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SOPT1CFG,SOPT1 Configuration Register"
|
|
bitfld.long 0x00 26. " USSWE ,USB voltage regulator stop standby write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " UVSWE ,USB voltage regulator VLP standby write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " URWE ,USB voltage regulator enable write enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "SOPT1CFG,SOPT1 Configuration Register"
|
|
endif
|
|
endif
|
|
endif
|
|
base ad:0x40075000
|
|
sif !cpuis("MKL28*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SOPT2,System Options Register"
|
|
sif cpuis("MKL82Z*")
|
|
bitfld.long 0x00 30.--31. " EMVSIMSRC ,EMVSIM Module Clock Source Select" "Disabled,MCGFLLCLK MCGPLLCLK or IRC48M/2,OSCERCLK,MCGIRCLK"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL13*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")
|
|
bitfld.long 0x00 28.--29. " LPUART1SRC ,LPUART1 clock source select" "Disabled,IRC48M,OSCERCLK,MCGIRCLK"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL46*")
|
|
bitfld.long 0x00 26.--27. " UART0SRC ,UART0 clock source select" "Disabled,MCGFLLCLK or MCGPLLCLK/2,OSCERCLK,MCGIRCLK"
|
|
bitfld.long 0x00 24.--25. " TPMSRC ,TPM clock source select" "Disabled,MCGFLLCLK or MCGPLLCLK/2,OSCERCLK,MCGIRCLK"
|
|
newline
|
|
bitfld.long 0x00 18. " USBSRC ,USB clock source select" "USB_CLKIN,MCGPLLCLK/2 or MCGFLLCLK"
|
|
bitfld.long 0x00 16. " PLLFLLSEL ,PLL/FLL clock select" "MCGFLLCLK,MCGPLLCLK/2"
|
|
newline
|
|
elif cpuis("MKL82Z*")
|
|
bitfld.long 0x00 26.--27. " UART0SRC ,UART0 clock source select" "Disabled,MCGFLLCLK or MCGPLLCLK/2,OSCERCLK,MCGIRCLK"
|
|
bitfld.long 0x00 24.--25. " TPMSRC ,TPM clock source select" "Disabled,MCGFLLCLK or MCGPLLCLK/2,OSCERCLK,MCGIRCLK"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " FLEXIOSRC ,Flexio module clock source select" "Disabled,MCGFLLCLK or MCGPLLCLK or IRC48M/2,OSCERCLK,MCGIRCLK"
|
|
bitfld.long 0x00 18. " USBSRC ,USB clock source select" "USB_CLKIN,MCGFLLCLK MCGPLLCLK or IRC48M/2"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " PLLFLLSEL ,PLL/FLL clock select" "MCGFLLCLK,MCGPLLCLK,,IRC48M"
|
|
newline
|
|
elif cpuis("MKL03*")||cpuis("MKL13*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")
|
|
bitfld.long 0x00 26.--27. " LPUART0SRC ,LPUART0 clock source select" "Disabled,IRC48M,OSCERCLK,MCGIRCLK"
|
|
bitfld.long 0x00 24.--25. " TPMSRC ,TPM clock source select" "Disabled,IRC48M,OSCERCLK,MCGIRCLK"
|
|
newline
|
|
elif cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL34*")||cpuis("MKL36*")
|
|
bitfld.long 0x00 26.--27. " UART0SRC ,UART0 clock source select" "Disabled,MCGFLLCLK,OSCERCLK,MCGIRCLK"
|
|
bitfld.long 0x00 24.--25. " TPMSRC ,TPM clock source select" "Disabled,MCGFLLCLK,OSCERCLK,MCGIRCLK"
|
|
newline
|
|
bitfld.long 0x00 16. " PLLFLLSEL ,PLL/FLL clock select" "MCGFLLCLK,MCGPLLCLK/2"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 26.--27. " UART0SRC ,UART0 clock source select" "Disabled,MCGFLLCLK,OSCERCLK,MCGIRCLK"
|
|
bitfld.long 0x00 24.--25. " TPMSRC ,TPM clock source select" "Disabled,MCGFLLCLK,OSCERCLK,MCGIRCLK"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL13*")||cpuis("MKL17Z*")||cpuis("MKL33Z*")
|
|
bitfld.long 0x00 22.--23. " FLEXIOSRC ,Flexio module clock source select" "Disabled,IRC48M,OSCERCLK,MCGIRCLK"
|
|
bitfld.long 0x00 5.--7. " CLKOUTSEL ,CLKOUT select" ",,Bus clock,LPO clock,LIRC_CLK,,OSCERCLK,IRC48M"
|
|
newline
|
|
bitfld.long 0x00 4. " RTCCLKOUTSEL ,RTC clock out select" "RTC 1 hz,OSCERCLK"
|
|
newline
|
|
elif cpuis("MKL27Z*")||cpuis("MKL43Z*")
|
|
bitfld.long 0x00 22.--23. " FLEXIOSRC ,Flexio module clock source select" "Disabled,IRC48M,OSCERCLK,MCGIRCLK"
|
|
bitfld.long 0x00 18. " USBSRC ,USB clock source select" "USB_CLKIN,IRC48M"
|
|
newline
|
|
bitfld.long 0x00 5.--7. " CLKOUTSEL ,CLKOUT select" ",,Bus clock,LPO clock,LIRC_CLK,,OSCERCLK,IRC48M"
|
|
bitfld.long 0x00 4. " RTCCLKOUTSEL ,RTC clock out select" "RTC 1 hz,OSCERCLK"
|
|
newline
|
|
elif cpuis("MKL82Z*")
|
|
bitfld.long 0x00 5.--7. " CLKOUTSEL ,CLKOUT select" ",,Flash clock,LPO clock,MCGIRCLK,RTC 32.768kHz clock,OSCERCLK,IRC48M"
|
|
bitfld.long 0x00 4. " RTCCLKOUTS ,RTC clock out select" "RTC 1 Hz,RTC 32.768kHz"
|
|
newline
|
|
elif !cpuis("MKL02*")&&!cpuis("MKL03*")
|
|
bitfld.long 0x00 5.--7. " CLKOUTSEL ,CLKOUT select" ",,Bus clock,LPO clock,MCGIRCLK,,OSCERCLK,?..."
|
|
bitfld.long 0x00 4. " RTCCLKOUTSEL ,RTC clock out select" "RTC 1 hz,RTC 32.768kHz clock"
|
|
newline
|
|
elif cpuis("MKL03*")
|
|
bitfld.long 0x00 5.--7. " CLKOUTSEL ,CLKOUT select" ",,Bus clock,LPO clock,LIRC_CLK,,OSCERCLK,IRC48M"
|
|
bitfld.long 0x00 4. " RTCCLKOUTSEL ,RTC clock out select" "RTC 1 hz,OSCERCLK"
|
|
newline
|
|
endif
|
|
group.long 0x0C++0x07
|
|
sif !cpuis("MKL82Z*")
|
|
line.long 0x00 "SOPT4,System Options Register 4"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03*")&&!cpuis("MKL04*")&&!cpuis("MKL05*")
|
|
bitfld.long 0x00 26. " TPM2CLKSEL ,TPM2 external clock pin select" "TPM_CLKIN0 pin,TPM_CLKIN1 pin"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 25. " TPM1CLKSEL ,TPM1 external clock pin select" "TPM_CLKIN0 pin,TPM_CLKIN1 pin"
|
|
bitfld.long 0x00 24. " TPM0CLKSEL ,TPM0 external clock pin select" "TPM_CLKIN0 pin,TPM_CLKIN1 pin"
|
|
newline
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03*")&&!cpuis("MKL04*")&&!cpuis("MKL05*")
|
|
bitfld.long 0x00 20. " TPM2CH0SRC ,TPM2 channel 0 input capture source select" "TPM2_CH0 signal,CMP0 output"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL26*")||cpuis("MKL36*")||cpuis("MKL46*")||cpuis("MKL27Z*")||cpuis("MKL43Z*")
|
|
bitfld.long 0x00 18.--19. " TPM1CH0SRC ,TPM1 channel 0 input capture source select" "TPM1_CH0 signal,CMP0 output,,USB sof pulse"
|
|
newline
|
|
elif cpuis("MKL16*")||cpuis("MKL17Z*")||cpuis("MKL33Z*")
|
|
bitfld.long 0x00 18.--19. " TPM1CH0SRC ,TPM1 channel 0 input capture source select" "TPM1_CH0 signal,CMP0 output,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 18. " TPM1CH0SRC ,TPM1 channel 0 input capture source select" "TPM1_CH0 signal,CMP0 output"
|
|
newline
|
|
endif
|
|
endif
|
|
line.long 0x04 "SOPT5,System Options Register 5"
|
|
sif cpuis("MKL82Z*")
|
|
bitfld.long 0x04 22.--23. " LPUART1RXSRC ,LPUART1 receive data source select" "LPUART1_RX pin,CMP0,?..."
|
|
bitfld.long 0x04 20.--21. " LPUART1TXSRC ,LPUART1 transmit data source select" "LPUART1_TX pin,LPUART1_TX mod with TMP1 ch#0 out,LPUART1_TX mod with TMP2 ch#0 out,?..."
|
|
newline
|
|
endif
|
|
sif cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")
|
|
bitfld.long 0x04 18. " UART2ODE ,UART2 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " LPUART1ODE ,LPUART1 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
elif cpuis("MKL82Z*")
|
|
bitfld.long 0x04 18.--19. " LPUART0RXSRC ,LPUART0 receive data source select" "LPUART0_RX pin,CMP0 output,?..."
|
|
bitfld.long 0x04 16.--17. " LPUART0TXSRC ,LPUART0 transmit data source select" "LPUART0_TX,TPM1,TPM2,?..."
|
|
newline
|
|
elif !cpuis("MKL02*")&&!cpuis("MKL03*")&&!cpuis("MKL04*")&&!cpuis("MKL05*")
|
|
bitfld.long 0x04 18. " UART2ODE ,UART2 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " UART1ODE ,UART1 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL03*")||cpuis("MKL13*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")
|
|
bitfld.long 0x04 16. " LPUART0ODE ,LPUART0 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
elif !cpuis("MKL82Z*")
|
|
bitfld.long 0x04 16. " UART0ODE ,UART0 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL13*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")
|
|
bitfld.long 0x04 6. " LPUART1RXSRC ,LPUART1 receive data source select" "LPUART1_RX pin,CMP0 output"
|
|
bitfld.long 0x04 4.--5. " LPUART1TXSRC ,LPUART1 transmit data source select" "LPUART1_TX pin,LPUART1_TX mod with TMP1 ch#0 out,LPUART1_TX mod with TMP2 ch#0 out,?..."
|
|
newline
|
|
elif !cpuis("MKL02*")&&!cpuis("MKL03*")&&!cpuis("MKL04*")&&!cpuis("MKL05*")&&!cpuis("MKL82Z*")
|
|
bitfld.long 0x04 6. " UART1RXSRC ,UART1 receive data source select" "UART1_RX pin,CMP0 output"
|
|
bitfld.long 0x04 4.--5. " UART1TXSRC ,UART1 transmit data source select" "UART1_TX pin,UART1_TX mod with TMP1 ch#0 out,UART1_TX mod with TMP2 ch#0 out,?..."
|
|
newline
|
|
endif
|
|
sif cpuis("MKL03*")||cpuis("MKL13*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")
|
|
bitfld.long 0x04 2. " LPUART0RXSRC ,LPUART0 receive data source select" "LPUART0_RX pin,CMP0 output"
|
|
newline
|
|
elif !cpuis("MKL82Z*")
|
|
bitfld.long 0x04 2. " UART0RXSRC ,UART0 receive data source select" "UART0_RX pin,CMP0 output"
|
|
newline
|
|
endif
|
|
sif !cpuis("MKL82*")
|
|
sif cpuis("MKL03*")
|
|
bitfld.long 0x04 0. " LPUART0TXSRC ,LPUART0 transmit data source select" "LPUART0_TX pin,LPUART0_TX mod with TMP1 ch#0 out"
|
|
newline
|
|
elif cpuis("MKL13*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")
|
|
bitfld.long 0x04 0.--1. " LPUART0TXSRC ,LPUART0 transmit data source select" "LPUART0_TX pin,LPUART0_TX mod with TMP1 ch#0 out,LPUART0_TX mod with TMP2 ch#0 out,?..."
|
|
newline
|
|
elif !cpuis("MKL02*")&&!cpuis("MKL03*")&&!cpuis("MKL04*")&&!cpuis("MKL05*")
|
|
bitfld.long 0x04 0.--1. " UART0TXSRC ,UART0 transmit data source select" "UART0_TX pin,UART0_TX mod with TMP1 ch#0 out,UART0_TX mod with TMP2 ch#0 out,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x04 0. " UART0TXSRC ,UART0 transmit data source select" "UART0_TX pin,UART0_TX mod with TMP1 ch#0 out"
|
|
newline
|
|
endif
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SOPT7,System Options Register 7"
|
|
sif !cpuis("MKL82*")
|
|
bitfld.long 0x00 7. " ADC0ALTTRGEN ,ADC0 alternate trigger enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 4. " ADC0PRETRGSEL ,ADC0 pretrigger select" "Pre-trigger A,Pre-trigger B"
|
|
newline
|
|
sif cpuis("MKL04*")||cpuis("MKL05*")
|
|
bitfld.long 0x00 0.--3. " ADC0TRGSEL ,ADC0 trigger select" "EXTRG_IN,CMP0 output,,,PIT trigger 0,PIT trigger 1,,,TPM0 overflow,TPM1 overflow,,,RTC alarm,RTC seconds,LPTMR0 trigger,?..."
|
|
newline
|
|
elif cpuis("MKL02*")
|
|
bitfld.long 0x00 0.--3. " ADC0TRGSEL ,ADC0 trigger select" "EXTRG_IN,CMP0 output,,,,,,,TPM0 overflow,TPM1 overflow,,,,,LPTMR0 trigger,?..."
|
|
newline
|
|
elif cpuis("MKL03*")
|
|
bitfld.long 0x00 0.--3. " ADC0TRGSEL ,ADC0 trigger select" "EXTRG_IN,CMP0 output,,,,,,,TPM0 overflow,TPM1 overflow,,,RTC alarm,RTC seconds,LPTMR0 trigger,?..."
|
|
newline
|
|
elif cpuis("MKL82*")
|
|
bitfld.long 0x00 0.--3. " ADC0TRGSEL ,ADC0 trigger select" "EXTRG_IN,CMP0 output,,,PIT trigger 0,PIT trigger 1,PIT trigger 2,PIT trigger 3,TPM0 trigger,TPM1 trigger,TPM2 trigger,LPTMR1 trigger,RTC alarm,RTC seconds,LPTMR0 trigger,TPM1"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 0.--3. " ADC0TRGSEL ,ADC0 trigger select" "EXTRG_IN,CMP0 output,,,PIT trigger 0,PIT trigger 1,,,TPM0 overflow,TPM1 overflow,TPM2 overflow,,RTC alarm,RTC seconds,LPTMR0 trigger,?..."
|
|
newline
|
|
endif
|
|
sif cpuis("MKL82Z*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SOPT9,System Options Register 9"
|
|
bitfld.long 0x00 26. " TPM2CLKSEL ,TPM2 External Clock Pin Select" "TPM_CLKIN0 pin,TPM_CLKIN1 pin"
|
|
bitfld.long 0x00 25. " TPM1CLKSEL ,TPM1 External Clock Pin Select" "TPM_CLKIN0 pin,TPM_CLKIN1 pin"
|
|
newline
|
|
bitfld.long 0x00 24. " TPM0CLKSEL ,TPM0 External Clock Pin Select" "TPM_CLKIN0 pin,TPM_CLKIN1 pin"
|
|
bitfld.long 0x00 20.--21. " TPM2CH0SRC ,TPM2 channel 0 input capture source select" "TPM2_CH0 signal,CMP0 output,?..."
|
|
newline
|
|
bitfld.long 0x00 18.--19. " TPM1CH0SRC ,TPM1 channel 0 input capture source select" "TPM1_CH0 signal,CMP0 output,?..."
|
|
endif
|
|
endif
|
|
width 10.
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "SDID,System Device Identification Register"
|
|
sif cpuis("MKL13*")||cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
bitfld.long 0x00 28.--31. " FAMID ,Kinetis family ID" ",KL13,,Kl33,?..."
|
|
newline
|
|
elif cpuis("MKL17*")||cpuis("MKL33Z128*")||cpuis("MKL33Z256*")
|
|
bitfld.long 0x00 28.--31. " FAMID ,Kinetis family ID" ",KL17,KL27,KL33,KL43,?..."
|
|
newline
|
|
elif cpuis("MKL28*")
|
|
bitfld.long 0x00 28.--31. " FAMID ,Kinetis family ID" ",,KL2x,?..."
|
|
newline
|
|
elif cpuis("MKL82*")
|
|
bitfld.long 0x00 28.--31. " FAMILYID ,Kinetis family ID" "Kl0x,Kl1x,Kl2x,Kl3x,Kl4x,Kl6x,Kl7x,Kl8x,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 28.--31. " FAMID ,Kinetis family ID" "Kl0x,Kl1x,Kl2x,Kl3x,Kl4x,?..."
|
|
newline
|
|
endif
|
|
sif cpuis("MKL05*")
|
|
bitfld.long 0x00 24.--27. " SUBFAMID ,Kinetis sub-family ID" ",,Klx2,Klx3,Klx4,Klx5,Klx6,?..."
|
|
newline
|
|
elif cpuis("MKL13*")||cpuis("MKL17*")||cpuis("MKL33Z*")
|
|
bitfld.long 0x00 24.--27. " SUBFAMID ,Kinetis sub-family ID" ",,,Klx3,?..."
|
|
newline
|
|
elif cpuis("MKL28*")
|
|
bitfld.long 0x00 24.--27. " SUBFAMID ,Kinetis sub-family ID" ",,Klx2,Klx3,Klx4,Klx5,Klx6,Klx7,Klx8,Klx9,?..."
|
|
newline
|
|
elif cpuis("MKL82*")
|
|
bitfld.long 0x00 24.--27. " SUBFAMID ,Kinetis sub-family ID" "Klx0,Klx1,Klx2,Klx3,Klx4,Klx5,Klx6,Klx7,Klx8,Klx9,?..."
|
|
newline
|
|
elif cpuis("MKL02*")
|
|
bitfld.long 0x00 24.--27. " SUBFAMID ,Kinetis sub-family ID" ",,Klx2,,Klx4,Klx5,Klx6,Klx7,?..."
|
|
newline
|
|
elif cpuis("MKL14*")
|
|
bitfld.long 0x00 24.--27. " SUBFAMID ,Kinetis sub-family ID" ",,Klx2,,Klx4,Klx5,Klx6,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 24.--27. " SUBFAMID ,Kinetis sub-family ID" ",,Klx2,Klx3,Klx4,Klx5,Klx6,Klx7,?..."
|
|
newline
|
|
endif
|
|
sif !cpuis("MKL82*")
|
|
bitfld.long 0x00 20.--23. " SERIESID ,Kinetis series ID" ",KL,?..."
|
|
newline
|
|
endif
|
|
sif cpuis("MKL17*")||cpuis("MKL33Z128*")||cpuis("MKL33Z256*")
|
|
bitfld.long 0x00 16.--19. " SRAMSIZE ,System SRAM size" ",,,,,16 kb,32 kb,?..."
|
|
newline
|
|
elif cpuis("MKL28*")
|
|
bitfld.long 0x00 16.--19. " SRAMSIZE ,System SRAM size" ",,,,,,,,96 kb,128 kb,?..."
|
|
newline
|
|
elif cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
bitfld.long 0x00 16.--19. " SRAMSIZE ,System SRAM size" ",,,4 kb,8 kb,?..."
|
|
newline
|
|
elif !cpuis("MKL82*")
|
|
bitfld.long 0x00 16.--19. " SRAMSIZE ,System SRAM size" "0.5kb,1 kb,2 kb,4 kb,8 kb,16 kb,32 kb,64 kb,?..."
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 12.--15. " REVID ,Device revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
sif !cpuis("MKL13*")&&!cpuis("MKL33Z*")
|
|
bitfld.long 0x00 7.--11. " DIEID ,Device die number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL28*")
|
|
bitfld.long 0x00 4.--6. " KEYATT ,Core configuration of the device" "Cortex CM0+ Core,?..."
|
|
newline
|
|
elif cpuis("MKL82*")
|
|
bitfld.long 0x00 4.--6. " FAMID ,Kinetis family ID" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL05*")
|
|
bitfld.long 0x00 0.--3. " PINID ,Pincount identification" "16-pin,24-pin,32-pin,,48-pin,64-pin,80-pin,,100-pin,?..."
|
|
newline
|
|
elif cpuis("MKL13*")||cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
bitfld.long 0x00 0.--3. " PINID ,Pincount identification" ",,32-pin,,48-pin,64-pin,80-pin,,,,,WLCSP,?..."
|
|
newline
|
|
elif cpuis("MKL17*")||cpuis("MKL33Z128*")||cpuis("MKL33Z256*")
|
|
bitfld.long 0x00 0.--3. " PINID ,Pincount identification" ",,32-pin,,48-pin,64-pin,,,,,,WLCSP,?..."
|
|
newline
|
|
elif cpuis("MKL28*")
|
|
bitfld.long 0x00 0.--3. " PINID ,Pincount identification" ",,,,,,,,100-pin,121-pin,?..."
|
|
newline
|
|
elif cpuis("MKL82*")
|
|
bitfld.long 0x00 0.--3. " PINID ,Pincount identification" ",,,,,64-pin,80-pin,,100-pin,121-pin,,WLCSP,?..."
|
|
newline
|
|
elif cpuis("MKL14*")
|
|
bitfld.long 0x00 0.--3. " PINID ,Pincount identification" "16-pin,24-pin,32-pin,,48-pin,64-pin,80-pin,,100-pin,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 0.--3. " PINID ,Pincount identification" "16-pin,24-pin,32-pin,36-pin,48-pin,64-pin,80-pin,,100-pin,,,WLCSP,?..."
|
|
newline
|
|
endif
|
|
sif !cpuis("MKL28*")
|
|
group.long 0x34++0x0B
|
|
line.long 0x00 "SCGC4,System Clock Gating Control Register 4"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03*")&&!cpuis("MKL04*")&&!cpuis("MKL05*")&&!cpuis("MKL82*")
|
|
bitfld.long 0x00 23. " SPI1 ,SPI1 clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL03*")||cpuis("MKL13*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")
|
|
bitfld.long 0x00 22. " SPI0 ,SPI0 clock gate control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " VREF ,VREF clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CMP0 ,Comparator clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
elif cpuis("MKL82*")
|
|
bitfld.long 0x00 20. " VREF ,VREF clock gate control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CMP0 ,Comparator clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 22. " SPI0 ,SPI0 clock gate control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CMP0 ,Comparator clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL46*")||cpuis("MKL82*")
|
|
bitfld.long 0x00 18. " USBOTG ,USB clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
elif cpuis("MKL27Z*")||cpuis("MKL43Z*")
|
|
bitfld.long 0x00 18. " USBFS ,USB clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL13*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")
|
|
bitfld.long 0x00 12. " UART2 ,UART2 clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
elif !cpuis("MKL02*")&&!cpuis("MKL03*")&&!cpuis("MKL04*")&&!cpuis("MKL05*")
|
|
bitfld.long 0x00 12. " UART2 ,UART2 clock gate control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " UART1 ,UART1 clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif !cpuis("MKL03*")&&!cpuis("MKL13*")&&!cpuis("MKL17Z*")&&!cpuis("MKL27Z*")&&!cpuis("MKL33Z*")&&!cpuis("MKL43Z*")
|
|
bitfld.long 0x00 10. " UART0 ,UART0 clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif !cpuis("MKL04*")&&!cpuis("MKL05*")&&!cpuis("MKL03*")
|
|
bitfld.long 0x00 7. " I2C1 ,I2C1 clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 6. " I2C0 ,I2C0 clock gate control enable" "Disabled,Enabled"
|
|
sif cpuis("MKL82*")
|
|
bitfld.long 0x00 1. " EWM ,EWM Clock Gate Control" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "SCGC5,System Clock Gating Control Register 5"
|
|
sif cpuis("MKL13*")||cpuis("MKL17*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")
|
|
bitfld.long 0x04 31. " FLEXIO ,FLEXIO clock gate control" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " LPUART1 ,LPUART1 clock gate control" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " LPUART0 ,LPUART0 clock gate control" "Disabled,Enabled"
|
|
newline
|
|
elif cpuis("MKL82Z*")
|
|
bitfld.long 0x04 31. " FLEXIO ,FLEXIO clock gate control" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " QSPI0 ,QSPI0 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " LPUART2 ,LPUART2 Clock Gate Control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 21. " LPUART1 ,LPUART1 clock gate control" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " LPUART0 ,LPUART0 clock gate control" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " LTC ,LTC Clock Gate Control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 15. " EMVSIM1 ,EMVSIM1 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " EMVSIM0 ,EMVSIM0 Clock Gate Control" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL03*")
|
|
bitfld.long 0x04 20. " LPUART0 ,LPUART0 clock gate control" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL33Z*")||cpuis("MKL34*")||cpuis("MKL36*")||cpuis("MKL43Z*")||cpuis("MKL46*")
|
|
bitfld.long 0x04 19. " SLCD ,Segment LCD clock gate control" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03*")&&!cpuis("MKL04*")&&!cpuis("MKL05*")
|
|
bitfld.long 0x04 13. " PORTE ,Port E clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 12. " PORTD ,Port D clock gate control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " PORTC ,Port C clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 10. " PORTB ,Port B clock gate control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " PORTA ,Port A clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("MKL05*")||cpuis("MK15LN*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL36*")||cpuis("MKL46*")
|
|
bitfld.long 0x04 5. " TSI ,TSI access control enable" "Disabled,Enabled"
|
|
newline
|
|
elif cpuis("MKL82Z*")
|
|
bitfld.long 0x04 5. " TSI ,TSI access control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " LPTMR1 ,LPTMR1 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " SECREG ,SECREG Clock Gate Control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0. " LPTMR0 ,LPTMR0 Clock Gate Control" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif !cpuis("MKL82Z*")
|
|
bitfld.long 0x04 0. " LPTMR ,Low power timer access control enable" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x08 "SCGC6,System Clock Gating Control Register 6"
|
|
sif cpuis("MKL05*")||cpuis("MKL13*")||cpuis("MK15LN*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL27Z128*")||cpuis("MKL27Z256*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL33Z*")||cpuis("MKL34*")||cpuis("MKL36*")||cpuis("MKL43Z*")||cpuis("MKL46*")
|
|
bitfld.long 0x08 31. " DAC0 ,DAC0 clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
elif cpuis("MKL82*")
|
|
bitfld.long 0x08 31. " DAC0 ,DAC0 clock gate control enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " RTC_RF ,RTC_RF Clock Gate Control" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif !cpuis("MKL02*")
|
|
bitfld.long 0x08 29. " RTC ,RTC access control enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 27. " ADC0 ,ADC0 clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x08 27. " ADC0 ,ADC0 clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03*")&&!cpuis("MKL04*")&&!cpuis("MKL05*")
|
|
bitfld.long 0x08 26. " TPM2 ,TPM2 clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x08 25. " TPM1 ,TPM1 clock gate control enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " TPM0 ,TPM0 clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03*")
|
|
bitfld.long 0x08 23. " PIT ,PIT clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL13*")||cpuis("MKL17Z64*")||cpuis("MKL17Z32*")||cpuis("MKL27Z64*")||cpuis("MKL27Z32*")||cpuis("MKL33Z32*")||cpuis("MKL33Z64*")||cpuis("MKL82*")
|
|
bitfld.long 0x08 18. " CRC ,CRC clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL16*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL26*")||cpuis("MKL36*")||cpuis("MKL43Z*")||cpuis("MKL46*")||cpuis("MK27Z128*")||cpuis("MK27Z256*")||cpuis("MKL33Z128*")||cpuis("MKL33Z256*")
|
|
bitfld.long 0x08 15. " I2S ,I2S clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
elif cpuis("MKL82*")
|
|
bitfld.long 0x08 13. " SPI1 ,SPI1 Clock Gate Control enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " SPI0 ,SPI0 Clock Gate Control enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 5. " TRNG ,TRNG Clock Gate Control enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " INTMUX0 ,INTMUX0 Clock Gate Control enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03*")
|
|
bitfld.long 0x08 1. " DMAMUX ,DMA mux clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL82*")
|
|
bitfld.long 0x08 0. " NVM ,NVM Clock Gate Control enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x08 0. " FTF ,Flash memory clock gate control enable" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03*")
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SCGC7,System Clock Gating Control Register 7"
|
|
sif cpuis("MKL82*")
|
|
bitfld.long 0x00 2. " MPU ,MPU Clock Gate Control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMA ,DMA clock gate control enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 8. " DMA ,DMA clock gate control enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CLKDIV1,System Clock Divider Register 1"
|
|
sif cpuis("MKL82*")
|
|
bitfld.long 0x00 28.--31. " OUTDIV1 ,Clock 1 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 24.--27. " OUTDIV2 ,Clock 2 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " OUTDIV4 ,Clock 4 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 12.--15. " OUTDIV5 ,Clock 5 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
else
|
|
bitfld.long 0x00 28.--31. " OUTDIV1 ,Clock 1 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 16.--18. " OUTDIV4 ,Clock 4 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
endif
|
|
sif cpuis("MKL82*")
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CLKDIV2,System Clock Divider Register 2"
|
|
bitfld.long 0x00 1.--3. " USBDIV ,USB clock divider divisor" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " USBFRAC ,USB clock divider fraction" "0,1"
|
|
endif
|
|
endif
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "FCFG1,Flash Configuration Register 1"
|
|
sif cpuis("MKL17Z32*")||cpuis("MKL17Z64*")||cpuis("MKL27Z32*")||cpuis("MKL27Z64*")
|
|
bitfld.long 0x00 24.--27. " PFSIZE ,Program flash memory/protection region" "8 KB/1 KB,16 KB/1 KB,,32 KB/1 KB,,64 KB/2 KB,,128 KB/4 KB,,256 KB/8 KB,,,,,,64 KB/2 KB"
|
|
elif cpuis("MKL13*")||cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
bitfld.long 0x00 24.--27. " PFSIZE ,Program flash memory/protection region" "8 KB/1 KB,16 KB/1 KB,,32 KB/1 KB,,64 KB/2 KB,,,,,,,,,,64 KB/2 KB"
|
|
elif cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL27Z128*")||cpuis("MKL27Z256*")||cpuis("MKL33Z128*")||cpuis("MKL33Z256*")||cpuis("MKL43Z*")
|
|
bitfld.long 0x00 24.--27. " PFSIZE ,Program flash memory/protection region" "8 KB/1 KB,16 KB/1 KB,,32 KB/1 KB,,64 KB/2 KB,,128 KB/4 KB,,256 KB/8 KB,,,,,,256 KB/8 KB"
|
|
elif cpuis("MKL28Z*")
|
|
bitfld.long 0x00 24.--27. " PFSIZE ,Program flash memory/protection region" ",,,,,64 KB/2 KB,,128 KB/4 KB,,256 KB/8 KB,,512 KB/16 KB,?..."
|
|
elif cpuis("MKL82Z*")
|
|
bitfld.long 0x00 24.--27. " PFSIZE ,Program flash memory/protection region" ",,,32 KB,,64 KB,,128 KB,,256 KB,,512 KB,,1024 KB,,128 KB"
|
|
elif !cpuis("MKL02*")&&!cpuis("MKL03*")&&!cpuis("MKL04*")&&!cpuis("MKL05*")
|
|
sif cpuis("MKL36*")||cpuis("MKL34*")||cpuis("MKL46*")||cpuis("MKL16*")||cpuis("MKL26*")
|
|
bitfld.long 0x00 24.--27. " PFSIZE ,Program flash memory/protection region" "8 KB/0.25 KB,16 KB/0.5 KB,,32 KB/1 KB,,64 KB/2 KB,,128 KB/4 KB,,256 KB/8 KB,,,,,,256 KB/8 KB"
|
|
else
|
|
bitfld.long 0x00 24.--27. " PFSIZE ,Program flash memory/protection region" "8 KB/0.25 KB,16 KB/0.5 KB,,32 KB/1 KB,,64 KB/2 KB,,128 KB/4 KB,,256 KB/4 KB,,,,,,128 KB/4 KB"
|
|
endif
|
|
else
|
|
bitfld.long 0x00 24.--27. " PFSIZE ,Program flash memory/protection region" "8 KB/0.25 KB,16 KB/0.5 KB,,32 KB/1 KB,,64 KB/2 KB,,128 KB/4 KB,,256 KB/4 KB,,,,,,32 KB/1 KB"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 1. " FLASHDOZE ,Flash doze" "Flash enabled,Flash disabled"
|
|
bitfld.long 0x00 0. " FLASHDIS ,Flash disable" "No,Yes"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FCFG2,Flash Configuration Register 2"
|
|
sif cpuis("MKL36*")||cpuis("MKL34*")||cpuis("MKL43Z*")||cpuis("MKL46*")||cpuis("MKL16*")||cpuis("MKL26*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL27Z128*")||cpuis("MKL27Z256*")||cpuis("MKL33Z128*")||cpuis("MKL33Z256*")
|
|
hexmask.long.byte 0x00 24.--30. 1. " MAXADDR0 ,Max address block"
|
|
hexmask.long.byte 0x00 16.--22. 1. " MAXADDR1 ,Max address block"
|
|
else
|
|
hexmask.long.byte 0x00 24.--30. 1. " MAXADDR0 ,Max address block"
|
|
endif
|
|
rgroup.long 0x58++0x0B
|
|
line.long 0x00 "UIDMH,Unique Identification Register Mid-high"
|
|
sif !cpuis("MKL82Z*")
|
|
hexmask.long.word 0x00 0.--15. 1. " UID ,Unique identification"
|
|
endif
|
|
line.long 0x04 "UIDML,Unique Identification Register Mid Low"
|
|
line.long 0x08 "UIDL,Unique Identification Register Low"
|
|
sif !cpuis("MKL28Z*")&&!cpuis("MKL82Z*")
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "COPC,COP Control Register"
|
|
sif cpuis("MKL03*")||cpuis("MKL13*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")
|
|
bitfld.long 0x00 6.--7. " COPCLKSEL ,COP clock select" "LPO,MCGIRCLK,OSCERCLK,Bus clock"
|
|
newline
|
|
bitfld.long 0x00 5. " COPDBGEN ,COP debug enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " COPSTPEN ,COP stop enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 2.--3. " COPT ,COP watchdog timeout" "Disabled,2^5 LPO cycles/2^13 bus clock cycles,2^8 LPO cycles/2^16 bus clock cycles,2^10 LPO cycles/2^18 bus clock cycles"
|
|
newline
|
|
bitfld.long 0x00 1. " COPCLKS ,COP clock select" "Internal 1 khz clock,Bus clock"
|
|
newline
|
|
bitfld.long 0x00 0. " COPW ,COP windowed mode" "Normal,Windowed"
|
|
wgroup.long 0x104++0x03
|
|
line.long 0x00 "SRVCOP,Service COP Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SRVCOP ,Service COP register"
|
|
endif
|
|
sif cpuis("MKL28Z*")
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "PCSR,Peripheral Clock Status Register"
|
|
bitfld.long 0x00 7. " CS7 ,Clock Source 7 (Peripheral PLL) Status" "Not ready,Ready"
|
|
bitfld.long 0x00 6. " CS6 ,Clock Source 6 (System PLL) Status" "Not ready,Ready"
|
|
newline
|
|
bitfld.long 0x00 5. " CS5 ,Clock Source 5 (System FLL) Status" "Not ready,Ready"
|
|
bitfld.long 0x00 4. " CS4 ,Clock Source 4 (RTC Oscillator) Status" "Not ready,Ready"
|
|
newline
|
|
bitfld.long 0x00 3. " CS3 ,Clock Source 3 (Fast IRC Clock) Status" "Not ready,Ready"
|
|
bitfld.long 0x00 2. " CS2 ,Clock Source 2 (Slow IRC Clock) Status" "Not ready,Ready"
|
|
newline
|
|
bitfld.long 0x00 1. " CS1 ,Clock Source 1 (System Oscillator) Status" "Not ready,Ready"
|
|
endif
|
|
sif cpuis("MKL82Z*")
|
|
group.long 0x64++0x07
|
|
line.long 0x00 "CLKDIV3,System Clock Divider Register 3"
|
|
bitfld.long 0x00 1.--3. " PLLFLLDIV ,PLLFLL clock divider divisor" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " PLLFLLFRAC ,PLLFLL clock divider fraction" "0,1"
|
|
line.long 0x04 "MISCCTRL,Misc Control Register"
|
|
bitfld.long 0x04 16. " LTCEN ,LTC Status" "Not available,Available"
|
|
bitfld.long 0x04 3. " DMAINTSEL3 ,DMA channel 7 in vector 19 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " DMAINTSEL2 ,DMA channel 6 in vector 18 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " DMAINTSEL1 ,DMA channel 5 in vector 17 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0. " DMAINTSEL0 ,DMA channel 4 in vector 16 enable" "Disabled,Enabled"
|
|
rgroup.long 0x90++0x0F
|
|
line.long 0x00 "SECKEY0,Secure Key Register 0"
|
|
line.long 0x04 "SECKEY1,Secure Key Register 1"
|
|
line.long 0x08 "SECKEY2,Secure Key Register 2"
|
|
line.long 0x0C "SECKEY3,Secure Key Register 3"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
base ad:0x40047000
|
|
width 10.
|
|
sif !cpuis("MKL02*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SOPT1,System Options Register"
|
|
sif cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL43Z*")||cpuis("MKL46*")||cpuis("MKL27Z128*")||cpuis("MKL27Z256*")||cpuis("MKL28*")
|
|
bitfld.long 0x00 31. " USBREGEN ,USB voltage regulator enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " USBSSTBY ,USB voltage regulator during stop" "No standby,Standby"
|
|
bitfld.long 0x00 29. " USBVSTBY ,USB voltage regulator during VLPR and VLPW modes" "No standby,Standby"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18.--19. " OSC32KSEL ,32K oscillator clock select" "OSC32KCLK,,RTC_CLKIN,LPO 1khz"
|
|
sif cpuis("MKL03*")
|
|
newline
|
|
bitfld.long 0x00 16.--17. " OSC32KOUT ,32K oscillator clock output" "No output,PTB13,?..."
|
|
elif cpuis("MKL17Z32*")||cpuis("MKL17Z64*")||cpuis("MKL27Z32*")||cpuis("MKL27Z64*")||cpuis("MKL13*")||cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
newline
|
|
bitfld.long 0x00 16.--17. " OSC32KOUT ,32K oscillator clock output" "No output,PTE0,?..."
|
|
elif cpuis("MKL17Z*")||cpuis("MKL27Z128*")||cpuis("MKL27Z256*")||cpuis("MKL33Z128*")||cpuis("MKL33Z256*")
|
|
newline
|
|
bitfld.long 0x00 16.--17. " OSC32KOUT ,32K oscillator clock output" "No output,PTE0,PTE26,?..."
|
|
elif cpuis("MKL82Z*")
|
|
newline
|
|
bitfld.long 0x00 12.--15. " RAMSIZE ,System RAM Size" ",8KB,,16KB,24KB,32KB,48KB,64KB,96KB,128KB,256KB,?..."
|
|
endif
|
|
sif !cpuis("MKL82*")
|
|
sif cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL27Z128*")||cpuis("MKL27Z256*")||cpuis("MKL28*")||cpuis("MKL43Z*")||cpuis("MKL46*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SOPT1CFG,SOPT1 Configuration Register"
|
|
bitfld.long 0x00 26. " USSWE ,USB voltage regulator stop standby write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " UVSWE ,USB voltage regulator VLP standby write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " URWE ,USB voltage regulator enable write enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "SOPT1CFG,SOPT1 Configuration Register"
|
|
endif
|
|
endif
|
|
endif
|
|
base ad:0x40048000
|
|
sif !cpuis("MKL28*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SOPT2,System Options Register"
|
|
sif cpuis("MKL82Z*")
|
|
bitfld.long 0x00 30.--31. " EMVSIMSRC ,EMVSIM Module Clock Source Select" "Disabled,MCGFLLCLK MCGPLLCLK or IRC48M/2,OSCERCLK,MCGIRCLK"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL13*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")
|
|
bitfld.long 0x00 28.--29. " LPUART1SRC ,LPUART1 clock source select" "Disabled,IRC48M,OSCERCLK,MCGIRCLK"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL46*")
|
|
bitfld.long 0x00 26.--27. " UART0SRC ,UART0 clock source select" "Disabled,MCGFLLCLK or MCGPLLCLK/2,OSCERCLK,MCGIRCLK"
|
|
bitfld.long 0x00 24.--25. " TPMSRC ,TPM clock source select" "Disabled,MCGFLLCLK or MCGPLLCLK/2,OSCERCLK,MCGIRCLK"
|
|
newline
|
|
bitfld.long 0x00 18. " USBSRC ,USB clock source select" "USB_CLKIN,MCGPLLCLK/2 or MCGFLLCLK"
|
|
bitfld.long 0x00 16. " PLLFLLSEL ,PLL/FLL clock select" "MCGFLLCLK,MCGPLLCLK/2"
|
|
newline
|
|
elif cpuis("MKL82Z*")
|
|
bitfld.long 0x00 26.--27. " UART0SRC ,UART0 clock source select" "Disabled,MCGFLLCLK or MCGPLLCLK/2,OSCERCLK,MCGIRCLK"
|
|
bitfld.long 0x00 24.--25. " TPMSRC ,TPM clock source select" "Disabled,MCGFLLCLK or MCGPLLCLK/2,OSCERCLK,MCGIRCLK"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " FLEXIOSRC ,Flexio module clock source select" "Disabled,MCGFLLCLK or MCGPLLCLK or IRC48M/2,OSCERCLK,MCGIRCLK"
|
|
bitfld.long 0x00 18. " USBSRC ,USB clock source select" "USB_CLKIN,MCGFLLCLK MCGPLLCLK or IRC48M/2"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " PLLFLLSEL ,PLL/FLL clock select" "MCGFLLCLK,MCGPLLCLK,,IRC48M"
|
|
newline
|
|
elif cpuis("MKL03*")||cpuis("MKL13*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")
|
|
bitfld.long 0x00 26.--27. " LPUART0SRC ,LPUART0 clock source select" "Disabled,IRC48M,OSCERCLK,MCGIRCLK"
|
|
bitfld.long 0x00 24.--25. " TPMSRC ,TPM clock source select" "Disabled,IRC48M,OSCERCLK,MCGIRCLK"
|
|
newline
|
|
elif cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL34*")||cpuis("MKL36*")
|
|
bitfld.long 0x00 26.--27. " UART0SRC ,UART0 clock source select" "Disabled,MCGFLLCLK,OSCERCLK,MCGIRCLK"
|
|
bitfld.long 0x00 24.--25. " TPMSRC ,TPM clock source select" "Disabled,MCGFLLCLK,OSCERCLK,MCGIRCLK"
|
|
newline
|
|
bitfld.long 0x00 16. " PLLFLLSEL ,PLL/FLL clock select" "MCGFLLCLK,MCGPLLCLK/2"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 26.--27. " UART0SRC ,UART0 clock source select" "Disabled,MCGFLLCLK,OSCERCLK,MCGIRCLK"
|
|
bitfld.long 0x00 24.--25. " TPMSRC ,TPM clock source select" "Disabled,MCGFLLCLK,OSCERCLK,MCGIRCLK"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL13*")||cpuis("MKL17Z*")||cpuis("MKL33Z*")
|
|
bitfld.long 0x00 22.--23. " FLEXIOSRC ,Flexio module clock source select" "Disabled,IRC48M,OSCERCLK,MCGIRCLK"
|
|
bitfld.long 0x00 5.--7. " CLKOUTSEL ,CLKOUT select" ",,Bus clock,LPO clock,LIRC_CLK,,OSCERCLK,IRC48M"
|
|
newline
|
|
bitfld.long 0x00 4. " RTCCLKOUTSEL ,RTC clock out select" "RTC 1 hz,OSCERCLK"
|
|
newline
|
|
elif cpuis("MKL27Z*")||cpuis("MKL43Z*")
|
|
bitfld.long 0x00 22.--23. " FLEXIOSRC ,Flexio module clock source select" "Disabled,IRC48M,OSCERCLK,MCGIRCLK"
|
|
bitfld.long 0x00 18. " USBSRC ,USB clock source select" "USB_CLKIN,IRC48M"
|
|
newline
|
|
bitfld.long 0x00 5.--7. " CLKOUTSEL ,CLKOUT select" ",,Bus clock,LPO clock,LIRC_CLK,,OSCERCLK,IRC48M"
|
|
bitfld.long 0x00 4. " RTCCLKOUTSEL ,RTC clock out select" "RTC 1 hz,OSCERCLK"
|
|
newline
|
|
elif cpuis("MKL82Z*")
|
|
bitfld.long 0x00 5.--7. " CLKOUTSEL ,CLKOUT select" ",,Flash clock,LPO clock,MCGIRCLK,RTC 32.768kHz clock,OSCERCLK,IRC48M"
|
|
bitfld.long 0x00 4. " RTCCLKOUTS ,RTC clock out select" "RTC 1 Hz,RTC 32.768kHz"
|
|
newline
|
|
elif !cpuis("MKL02*")&&!cpuis("MKL03*")
|
|
bitfld.long 0x00 5.--7. " CLKOUTSEL ,CLKOUT select" ",,Bus clock,LPO clock,MCGIRCLK,,OSCERCLK,?..."
|
|
bitfld.long 0x00 4. " RTCCLKOUTSEL ,RTC clock out select" "RTC 1 hz,RTC 32.768kHz clock"
|
|
newline
|
|
elif cpuis("MKL03*")
|
|
bitfld.long 0x00 5.--7. " CLKOUTSEL ,CLKOUT select" ",,Bus clock,LPO clock,LIRC_CLK,,OSCERCLK,IRC48M"
|
|
bitfld.long 0x00 4. " RTCCLKOUTSEL ,RTC clock out select" "RTC 1 hz,OSCERCLK"
|
|
newline
|
|
endif
|
|
group.long 0x0C++0x07
|
|
sif !cpuis("MKL82Z*")
|
|
line.long 0x00 "SOPT4,System Options Register 4"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03*")&&!cpuis("MKL04*")&&!cpuis("MKL05*")
|
|
bitfld.long 0x00 26. " TPM2CLKSEL ,TPM2 external clock pin select" "TPM_CLKIN0 pin,TPM_CLKIN1 pin"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 25. " TPM1CLKSEL ,TPM1 external clock pin select" "TPM_CLKIN0 pin,TPM_CLKIN1 pin"
|
|
bitfld.long 0x00 24. " TPM0CLKSEL ,TPM0 external clock pin select" "TPM_CLKIN0 pin,TPM_CLKIN1 pin"
|
|
newline
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03*")&&!cpuis("MKL04*")&&!cpuis("MKL05*")
|
|
bitfld.long 0x00 20. " TPM2CH0SRC ,TPM2 channel 0 input capture source select" "TPM2_CH0 signal,CMP0 output"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL26*")||cpuis("MKL36*")||cpuis("MKL46*")||cpuis("MKL27Z*")||cpuis("MKL43Z*")
|
|
bitfld.long 0x00 18.--19. " TPM1CH0SRC ,TPM1 channel 0 input capture source select" "TPM1_CH0 signal,CMP0 output,,USB sof pulse"
|
|
newline
|
|
elif cpuis("MKL16*")||cpuis("MKL17Z*")||cpuis("MKL33Z*")
|
|
bitfld.long 0x00 18.--19. " TPM1CH0SRC ,TPM1 channel 0 input capture source select" "TPM1_CH0 signal,CMP0 output,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 18. " TPM1CH0SRC ,TPM1 channel 0 input capture source select" "TPM1_CH0 signal,CMP0 output"
|
|
newline
|
|
endif
|
|
endif
|
|
line.long 0x04 "SOPT5,System Options Register 5"
|
|
sif cpuis("MKL82Z*")
|
|
bitfld.long 0x04 22.--23. " LPUART1RXSRC ,LPUART1 receive data source select" "LPUART1_RX pin,CMP0,?..."
|
|
bitfld.long 0x04 20.--21. " LPUART1TXSRC ,LPUART1 transmit data source select" "LPUART1_TX pin,LPUART1_TX mod with TMP1 ch#0 out,LPUART1_TX mod with TMP2 ch#0 out,?..."
|
|
newline
|
|
endif
|
|
sif cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")
|
|
bitfld.long 0x04 18. " UART2ODE ,UART2 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " LPUART1ODE ,LPUART1 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
elif cpuis("MKL82Z*")
|
|
bitfld.long 0x04 18.--19. " LPUART0RXSRC ,LPUART0 receive data source select" "LPUART0_RX pin,CMP0 output,?..."
|
|
bitfld.long 0x04 16.--17. " LPUART0TXSRC ,LPUART0 transmit data source select" "LPUART0_TX,TPM1,TPM2,?..."
|
|
newline
|
|
elif !cpuis("MKL02*")&&!cpuis("MKL03*")&&!cpuis("MKL04*")&&!cpuis("MKL05*")
|
|
bitfld.long 0x04 18. " UART2ODE ,UART2 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " UART1ODE ,UART1 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL03*")||cpuis("MKL13*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")
|
|
bitfld.long 0x04 16. " LPUART0ODE ,LPUART0 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
elif !cpuis("MKL82Z*")
|
|
bitfld.long 0x04 16. " UART0ODE ,UART0 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL13*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")
|
|
bitfld.long 0x04 6. " LPUART1RXSRC ,LPUART1 receive data source select" "LPUART1_RX pin,CMP0 output"
|
|
bitfld.long 0x04 4.--5. " LPUART1TXSRC ,LPUART1 transmit data source select" "LPUART1_TX pin,LPUART1_TX mod with TMP1 ch#0 out,LPUART1_TX mod with TMP2 ch#0 out,?..."
|
|
newline
|
|
elif !cpuis("MKL02*")&&!cpuis("MKL03*")&&!cpuis("MKL04*")&&!cpuis("MKL05*")&&!cpuis("MKL82Z*")
|
|
bitfld.long 0x04 6. " UART1RXSRC ,UART1 receive data source select" "UART1_RX pin,CMP0 output"
|
|
bitfld.long 0x04 4.--5. " UART1TXSRC ,UART1 transmit data source select" "UART1_TX pin,UART1_TX mod with TMP1 ch#0 out,UART1_TX mod with TMP2 ch#0 out,?..."
|
|
newline
|
|
endif
|
|
sif cpuis("MKL03*")||cpuis("MKL13*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")
|
|
bitfld.long 0x04 2. " LPUART0RXSRC ,LPUART0 receive data source select" "LPUART0_RX pin,CMP0 output"
|
|
newline
|
|
elif !cpuis("MKL82Z*")
|
|
bitfld.long 0x04 2. " UART0RXSRC ,UART0 receive data source select" "UART0_RX pin,CMP0 output"
|
|
newline
|
|
endif
|
|
sif !cpuis("MKL82*")
|
|
sif cpuis("MKL03*")
|
|
bitfld.long 0x04 0. " LPUART0TXSRC ,LPUART0 transmit data source select" "LPUART0_TX pin,LPUART0_TX mod with TMP1 ch#0 out"
|
|
newline
|
|
elif cpuis("MKL13*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")
|
|
bitfld.long 0x04 0.--1. " LPUART0TXSRC ,LPUART0 transmit data source select" "LPUART0_TX pin,LPUART0_TX mod with TMP1 ch#0 out,LPUART0_TX mod with TMP2 ch#0 out,?..."
|
|
newline
|
|
elif !cpuis("MKL02*")&&!cpuis("MKL03*")&&!cpuis("MKL04*")&&!cpuis("MKL05*")
|
|
bitfld.long 0x04 0.--1. " UART0TXSRC ,UART0 transmit data source select" "UART0_TX pin,UART0_TX mod with TMP1 ch#0 out,UART0_TX mod with TMP2 ch#0 out,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x04 0. " UART0TXSRC ,UART0 transmit data source select" "UART0_TX pin,UART0_TX mod with TMP1 ch#0 out"
|
|
newline
|
|
endif
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SOPT7,System Options Register 7"
|
|
sif !cpuis("MKL82*")
|
|
bitfld.long 0x00 7. " ADC0ALTTRGEN ,ADC0 alternate trigger enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 4. " ADC0PRETRGSEL ,ADC0 pretrigger select" "Pre-trigger A,Pre-trigger B"
|
|
newline
|
|
sif cpuis("MKL04*")||cpuis("MKL05*")
|
|
bitfld.long 0x00 0.--3. " ADC0TRGSEL ,ADC0 trigger select" "EXTRG_IN,CMP0 output,,,PIT trigger 0,PIT trigger 1,,,TPM0 overflow,TPM1 overflow,,,RTC alarm,RTC seconds,LPTMR0 trigger,?..."
|
|
newline
|
|
elif cpuis("MKL02*")
|
|
bitfld.long 0x00 0.--3. " ADC0TRGSEL ,ADC0 trigger select" "EXTRG_IN,CMP0 output,,,,,,,TPM0 overflow,TPM1 overflow,,,,,LPTMR0 trigger,?..."
|
|
newline
|
|
elif cpuis("MKL03*")
|
|
bitfld.long 0x00 0.--3. " ADC0TRGSEL ,ADC0 trigger select" "EXTRG_IN,CMP0 output,,,,,,,TPM0 overflow,TPM1 overflow,,,RTC alarm,RTC seconds,LPTMR0 trigger,?..."
|
|
newline
|
|
elif cpuis("MKL82*")
|
|
bitfld.long 0x00 0.--3. " ADC0TRGSEL ,ADC0 trigger select" "EXTRG_IN,CMP0 output,,,PIT trigger 0,PIT trigger 1,PIT trigger 2,PIT trigger 3,TPM0 trigger,TPM1 trigger,TPM2 trigger,LPTMR1 trigger,RTC alarm,RTC seconds,LPTMR0 trigger,TPM1"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 0.--3. " ADC0TRGSEL ,ADC0 trigger select" "EXTRG_IN,CMP0 output,,,PIT trigger 0,PIT trigger 1,,,TPM0 overflow,TPM1 overflow,TPM2 overflow,,RTC alarm,RTC seconds,LPTMR0 trigger,?..."
|
|
newline
|
|
endif
|
|
sif cpuis("MKL82Z*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SOPT9,System Options Register 9"
|
|
bitfld.long 0x00 26. " TPM2CLKSEL ,TPM2 External Clock Pin Select" "TPM_CLKIN0 pin,TPM_CLKIN1 pin"
|
|
bitfld.long 0x00 25. " TPM1CLKSEL ,TPM1 External Clock Pin Select" "TPM_CLKIN0 pin,TPM_CLKIN1 pin"
|
|
newline
|
|
bitfld.long 0x00 24. " TPM0CLKSEL ,TPM0 External Clock Pin Select" "TPM_CLKIN0 pin,TPM_CLKIN1 pin"
|
|
bitfld.long 0x00 20.--21. " TPM2CH0SRC ,TPM2 channel 0 input capture source select" "TPM2_CH0 signal,CMP0 output,?..."
|
|
newline
|
|
bitfld.long 0x00 18.--19. " TPM1CH0SRC ,TPM1 channel 0 input capture source select" "TPM1_CH0 signal,CMP0 output,?..."
|
|
endif
|
|
endif
|
|
width 10.
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "SDID,System Device Identification Register"
|
|
sif cpuis("MKL13*")||cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
bitfld.long 0x00 28.--31. " FAMID ,Kinetis family ID" ",KL13,,Kl33,?..."
|
|
newline
|
|
elif cpuis("MKL17*")||cpuis("MKL33Z128*")||cpuis("MKL33Z256*")
|
|
bitfld.long 0x00 28.--31. " FAMID ,Kinetis family ID" ",KL17,KL27,KL33,KL43,?..."
|
|
newline
|
|
elif cpuis("MKL28*")
|
|
bitfld.long 0x00 28.--31. " FAMID ,Kinetis family ID" ",,KL2x,?..."
|
|
newline
|
|
elif cpuis("MKL82*")
|
|
bitfld.long 0x00 28.--31. " FAMILYID ,Kinetis family ID" "Kl0x,Kl1x,Kl2x,Kl3x,Kl4x,Kl6x,Kl7x,Kl8x,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 28.--31. " FAMID ,Kinetis family ID" "Kl0x,Kl1x,Kl2x,Kl3x,Kl4x,?..."
|
|
newline
|
|
endif
|
|
sif cpuis("MKL05*")
|
|
bitfld.long 0x00 24.--27. " SUBFAMID ,Kinetis sub-family ID" ",,Klx2,Klx3,Klx4,Klx5,Klx6,?..."
|
|
newline
|
|
elif cpuis("MKL13*")||cpuis("MKL17*")||cpuis("MKL33Z*")
|
|
bitfld.long 0x00 24.--27. " SUBFAMID ,Kinetis sub-family ID" ",,,Klx3,?..."
|
|
newline
|
|
elif cpuis("MKL28*")
|
|
bitfld.long 0x00 24.--27. " SUBFAMID ,Kinetis sub-family ID" ",,Klx2,Klx3,Klx4,Klx5,Klx6,Klx7,Klx8,Klx9,?..."
|
|
newline
|
|
elif cpuis("MKL82*")
|
|
bitfld.long 0x00 24.--27. " SUBFAMID ,Kinetis sub-family ID" "Klx0,Klx1,Klx2,Klx3,Klx4,Klx5,Klx6,Klx7,Klx8,Klx9,?..."
|
|
newline
|
|
elif cpuis("MKL02*")
|
|
bitfld.long 0x00 24.--27. " SUBFAMID ,Kinetis sub-family ID" ",,Klx2,,Klx4,Klx5,Klx6,Klx7,?..."
|
|
newline
|
|
elif cpuis("MKL14*")
|
|
bitfld.long 0x00 24.--27. " SUBFAMID ,Kinetis sub-family ID" ",,Klx2,,Klx4,Klx5,Klx6,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 24.--27. " SUBFAMID ,Kinetis sub-family ID" ",,Klx2,Klx3,Klx4,Klx5,Klx6,Klx7,?..."
|
|
newline
|
|
endif
|
|
sif !cpuis("MKL82*")
|
|
bitfld.long 0x00 20.--23. " SERIESID ,Kinetis series ID" ",KL,?..."
|
|
newline
|
|
endif
|
|
sif cpuis("MKL17*")||cpuis("MKL33Z128*")||cpuis("MKL33Z256*")
|
|
bitfld.long 0x00 16.--19. " SRAMSIZE ,System SRAM size" ",,,,,16 kb,32 kb,?..."
|
|
newline
|
|
elif cpuis("MKL28*")
|
|
bitfld.long 0x00 16.--19. " SRAMSIZE ,System SRAM size" ",,,,,,,,96 kb,128 kb,?..."
|
|
newline
|
|
elif cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
bitfld.long 0x00 16.--19. " SRAMSIZE ,System SRAM size" ",,,4 kb,8 kb,?..."
|
|
newline
|
|
elif !cpuis("MKL82*")
|
|
bitfld.long 0x00 16.--19. " SRAMSIZE ,System SRAM size" "0.5kb,1 kb,2 kb,4 kb,8 kb,16 kb,32 kb,64 kb,?..."
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 12.--15. " REVID ,Device revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
sif !cpuis("MKL13*")&&!cpuis("MKL33Z*")
|
|
bitfld.long 0x00 7.--11. " DIEID ,Device die number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL28*")
|
|
bitfld.long 0x00 4.--6. " KEYATT ,Core configuration of the device" "Cortex CM0+ Core,?..."
|
|
newline
|
|
elif cpuis("MKL82*")
|
|
bitfld.long 0x00 4.--6. " FAMID ,Kinetis family ID" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL05*")
|
|
bitfld.long 0x00 0.--3. " PINID ,Pincount identification" "16-pin,24-pin,32-pin,,48-pin,64-pin,80-pin,,100-pin,?..."
|
|
newline
|
|
elif cpuis("MKL13*")||cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
bitfld.long 0x00 0.--3. " PINID ,Pincount identification" ",,32-pin,,48-pin,64-pin,80-pin,,,,,WLCSP,?..."
|
|
newline
|
|
elif cpuis("MKL17*")||cpuis("MKL33Z128*")||cpuis("MKL33Z256*")
|
|
bitfld.long 0x00 0.--3. " PINID ,Pincount identification" ",,32-pin,,48-pin,64-pin,,,,,,WLCSP,?..."
|
|
newline
|
|
elif cpuis("MKL28*")
|
|
bitfld.long 0x00 0.--3. " PINID ,Pincount identification" ",,,,,,,,100-pin,121-pin,?..."
|
|
newline
|
|
elif cpuis("MKL82*")
|
|
bitfld.long 0x00 0.--3. " PINID ,Pincount identification" ",,,,,64-pin,80-pin,,100-pin,121-pin,,WLCSP,?..."
|
|
newline
|
|
elif cpuis("MKL14*")
|
|
bitfld.long 0x00 0.--3. " PINID ,Pincount identification" "16-pin,24-pin,32-pin,,48-pin,64-pin,80-pin,,100-pin,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 0.--3. " PINID ,Pincount identification" "16-pin,24-pin,32-pin,36-pin,48-pin,64-pin,80-pin,,100-pin,,,WLCSP,?..."
|
|
newline
|
|
endif
|
|
sif !cpuis("MKL28*")
|
|
group.long 0x34++0x0B
|
|
line.long 0x00 "SCGC4,System Clock Gating Control Register 4"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03*")&&!cpuis("MKL04*")&&!cpuis("MKL05*")&&!cpuis("MKL82*")
|
|
bitfld.long 0x00 23. " SPI1 ,SPI1 clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL03*")||cpuis("MKL13*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")
|
|
bitfld.long 0x00 22. " SPI0 ,SPI0 clock gate control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " VREF ,VREF clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CMP0 ,Comparator clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
elif cpuis("MKL82*")
|
|
bitfld.long 0x00 20. " VREF ,VREF clock gate control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CMP0 ,Comparator clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 22. " SPI0 ,SPI0 clock gate control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CMP0 ,Comparator clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL46*")||cpuis("MKL82*")
|
|
bitfld.long 0x00 18. " USBOTG ,USB clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
elif cpuis("MKL27Z*")||cpuis("MKL43Z*")
|
|
bitfld.long 0x00 18. " USBFS ,USB clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL13*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")
|
|
bitfld.long 0x00 12. " UART2 ,UART2 clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
elif !cpuis("MKL02*")&&!cpuis("MKL03*")&&!cpuis("MKL04*")&&!cpuis("MKL05*")
|
|
bitfld.long 0x00 12. " UART2 ,UART2 clock gate control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " UART1 ,UART1 clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif !cpuis("MKL03*")&&!cpuis("MKL13*")&&!cpuis("MKL17Z*")&&!cpuis("MKL27Z*")&&!cpuis("MKL33Z*")&&!cpuis("MKL43Z*")
|
|
bitfld.long 0x00 10. " UART0 ,UART0 clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif !cpuis("MKL04*")&&!cpuis("MKL05*")&&!cpuis("MKL03*")
|
|
bitfld.long 0x00 7. " I2C1 ,I2C1 clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 6. " I2C0 ,I2C0 clock gate control enable" "Disabled,Enabled"
|
|
sif cpuis("MKL82*")
|
|
bitfld.long 0x00 1. " EWM ,EWM Clock Gate Control" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "SCGC5,System Clock Gating Control Register 5"
|
|
sif cpuis("MKL13*")||cpuis("MKL17*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")
|
|
bitfld.long 0x04 31. " FLEXIO ,FLEXIO clock gate control" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " LPUART1 ,LPUART1 clock gate control" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " LPUART0 ,LPUART0 clock gate control" "Disabled,Enabled"
|
|
newline
|
|
elif cpuis("MKL82Z*")
|
|
bitfld.long 0x04 31. " FLEXIO ,FLEXIO clock gate control" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " QSPI0 ,QSPI0 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " LPUART2 ,LPUART2 Clock Gate Control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 21. " LPUART1 ,LPUART1 clock gate control" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " LPUART0 ,LPUART0 clock gate control" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " LTC ,LTC Clock Gate Control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 15. " EMVSIM1 ,EMVSIM1 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " EMVSIM0 ,EMVSIM0 Clock Gate Control" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL03*")
|
|
bitfld.long 0x04 20. " LPUART0 ,LPUART0 clock gate control" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL33Z*")||cpuis("MKL34*")||cpuis("MKL36*")||cpuis("MKL43Z*")||cpuis("MKL46*")
|
|
bitfld.long 0x04 19. " SLCD ,Segment LCD clock gate control" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03*")&&!cpuis("MKL04*")&&!cpuis("MKL05*")
|
|
bitfld.long 0x04 13. " PORTE ,Port E clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 12. " PORTD ,Port D clock gate control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " PORTC ,Port C clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 10. " PORTB ,Port B clock gate control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " PORTA ,Port A clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("MKL05*")||cpuis("MK15LN*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL36*")||cpuis("MKL46*")
|
|
bitfld.long 0x04 5. " TSI ,TSI access control enable" "Disabled,Enabled"
|
|
newline
|
|
elif cpuis("MKL82Z*")
|
|
bitfld.long 0x04 5. " TSI ,TSI access control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " LPTMR1 ,LPTMR1 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " SECREG ,SECREG Clock Gate Control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0. " LPTMR0 ,LPTMR0 Clock Gate Control" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif !cpuis("MKL82Z*")
|
|
bitfld.long 0x04 0. " LPTMR ,Low power timer access control enable" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x08 "SCGC6,System Clock Gating Control Register 6"
|
|
sif cpuis("MKL05*")||cpuis("MKL13*")||cpuis("MK15LN*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL27Z128*")||cpuis("MKL27Z256*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL33Z*")||cpuis("MKL34*")||cpuis("MKL36*")||cpuis("MKL43Z*")||cpuis("MKL46*")
|
|
bitfld.long 0x08 31. " DAC0 ,DAC0 clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
elif cpuis("MKL82*")
|
|
bitfld.long 0x08 31. " DAC0 ,DAC0 clock gate control enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " RTC_RF ,RTC_RF Clock Gate Control" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif !cpuis("MKL02*")
|
|
bitfld.long 0x08 29. " RTC ,RTC access control enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 27. " ADC0 ,ADC0 clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x08 27. " ADC0 ,ADC0 clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03*")&&!cpuis("MKL04*")&&!cpuis("MKL05*")
|
|
bitfld.long 0x08 26. " TPM2 ,TPM2 clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x08 25. " TPM1 ,TPM1 clock gate control enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " TPM0 ,TPM0 clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03*")
|
|
bitfld.long 0x08 23. " PIT ,PIT clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL13*")||cpuis("MKL17Z64*")||cpuis("MKL17Z32*")||cpuis("MKL27Z64*")||cpuis("MKL27Z32*")||cpuis("MKL33Z32*")||cpuis("MKL33Z64*")||cpuis("MKL82*")
|
|
bitfld.long 0x08 18. " CRC ,CRC clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL16*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL26*")||cpuis("MKL36*")||cpuis("MKL43Z*")||cpuis("MKL46*")||cpuis("MK27Z128*")||cpuis("MK27Z256*")||cpuis("MKL33Z128*")||cpuis("MKL33Z256*")
|
|
bitfld.long 0x08 15. " I2S ,I2S clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
elif cpuis("MKL82*")
|
|
bitfld.long 0x08 13. " SPI1 ,SPI1 Clock Gate Control enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " SPI0 ,SPI0 Clock Gate Control enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 5. " TRNG ,TRNG Clock Gate Control enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " INTMUX0 ,INTMUX0 Clock Gate Control enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03*")
|
|
bitfld.long 0x08 1. " DMAMUX ,DMA mux clock gate control enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL82*")
|
|
bitfld.long 0x08 0. " NVM ,NVM Clock Gate Control enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x08 0. " FTF ,Flash memory clock gate control enable" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03*")
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SCGC7,System Clock Gating Control Register 7"
|
|
sif cpuis("MKL82*")
|
|
bitfld.long 0x00 2. " MPU ,MPU Clock Gate Control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMA ,DMA clock gate control enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 8. " DMA ,DMA clock gate control enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CLKDIV1,System Clock Divider Register 1"
|
|
sif cpuis("MKL82*")
|
|
bitfld.long 0x00 28.--31. " OUTDIV1 ,Clock 1 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 24.--27. " OUTDIV2 ,Clock 2 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " OUTDIV4 ,Clock 4 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 12.--15. " OUTDIV5 ,Clock 5 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
else
|
|
bitfld.long 0x00 28.--31. " OUTDIV1 ,Clock 1 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 16.--18. " OUTDIV4 ,Clock 4 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
endif
|
|
sif cpuis("MKL82*")
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CLKDIV2,System Clock Divider Register 2"
|
|
bitfld.long 0x00 1.--3. " USBDIV ,USB clock divider divisor" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " USBFRAC ,USB clock divider fraction" "0,1"
|
|
endif
|
|
endif
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "FCFG1,Flash Configuration Register 1"
|
|
sif cpuis("MKL17Z32*")||cpuis("MKL17Z64*")||cpuis("MKL27Z32*")||cpuis("MKL27Z64*")
|
|
bitfld.long 0x00 24.--27. " PFSIZE ,Program flash memory/protection region" "8 KB/1 KB,16 KB/1 KB,,32 KB/1 KB,,64 KB/2 KB,,128 KB/4 KB,,256 KB/8 KB,,,,,,64 KB/2 KB"
|
|
elif cpuis("MKL13*")||cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
bitfld.long 0x00 24.--27. " PFSIZE ,Program flash memory/protection region" "8 KB/1 KB,16 KB/1 KB,,32 KB/1 KB,,64 KB/2 KB,,,,,,,,,,64 KB/2 KB"
|
|
elif cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL27Z128*")||cpuis("MKL27Z256*")||cpuis("MKL33Z128*")||cpuis("MKL33Z256*")||cpuis("MKL43Z*")
|
|
bitfld.long 0x00 24.--27. " PFSIZE ,Program flash memory/protection region" "8 KB/1 KB,16 KB/1 KB,,32 KB/1 KB,,64 KB/2 KB,,128 KB/4 KB,,256 KB/8 KB,,,,,,256 KB/8 KB"
|
|
elif cpuis("MKL28Z*")
|
|
bitfld.long 0x00 24.--27. " PFSIZE ,Program flash memory/protection region" ",,,,,64 KB/2 KB,,128 KB/4 KB,,256 KB/8 KB,,512 KB/16 KB,?..."
|
|
elif cpuis("MKL82Z*")
|
|
bitfld.long 0x00 24.--27. " PFSIZE ,Program flash memory/protection region" ",,,32 KB,,64 KB,,128 KB,,256 KB,,512 KB,,1024 KB,,128 KB"
|
|
elif !cpuis("MKL02*")&&!cpuis("MKL03*")&&!cpuis("MKL04*")&&!cpuis("MKL05*")
|
|
sif cpuis("MKL36*")||cpuis("MKL34*")||cpuis("MKL46*")||cpuis("MKL16*")||cpuis("MKL26*")
|
|
bitfld.long 0x00 24.--27. " PFSIZE ,Program flash memory/protection region" "8 KB/0.25 KB,16 KB/0.5 KB,,32 KB/1 KB,,64 KB/2 KB,,128 KB/4 KB,,256 KB/8 KB,,,,,,256 KB/8 KB"
|
|
else
|
|
bitfld.long 0x00 24.--27. " PFSIZE ,Program flash memory/protection region" "8 KB/0.25 KB,16 KB/0.5 KB,,32 KB/1 KB,,64 KB/2 KB,,128 KB/4 KB,,256 KB/4 KB,,,,,,128 KB/4 KB"
|
|
endif
|
|
else
|
|
bitfld.long 0x00 24.--27. " PFSIZE ,Program flash memory/protection region" "8 KB/0.25 KB,16 KB/0.5 KB,,32 KB/1 KB,,64 KB/2 KB,,128 KB/4 KB,,256 KB/4 KB,,,,,,32 KB/1 KB"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 1. " FLASHDOZE ,Flash doze" "Flash enabled,Flash disabled"
|
|
bitfld.long 0x00 0. " FLASHDIS ,Flash disable" "No,Yes"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FCFG2,Flash Configuration Register 2"
|
|
sif cpuis("MKL36*")||cpuis("MKL34*")||cpuis("MKL43Z*")||cpuis("MKL46*")||cpuis("MKL16*")||cpuis("MKL26*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL27Z128*")||cpuis("MKL27Z256*")||cpuis("MKL33Z128*")||cpuis("MKL33Z256*")
|
|
hexmask.long.byte 0x00 24.--30. 1. " MAXADDR0 ,Max address block"
|
|
hexmask.long.byte 0x00 16.--22. 1. " MAXADDR1 ,Max address block"
|
|
else
|
|
hexmask.long.byte 0x00 24.--30. 1. " MAXADDR0 ,Max address block"
|
|
endif
|
|
rgroup.long 0x58++0x0B
|
|
line.long 0x00 "UIDMH,Unique Identification Register Mid-high"
|
|
sif !cpuis("MKL82Z*")
|
|
hexmask.long.word 0x00 0.--15. 1. " UID ,Unique identification"
|
|
endif
|
|
line.long 0x04 "UIDML,Unique Identification Register Mid Low"
|
|
line.long 0x08 "UIDL,Unique Identification Register Low"
|
|
sif !cpuis("MKL28Z*")&&!cpuis("MKL82Z*")
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "COPC,COP Control Register"
|
|
sif cpuis("MKL03*")||cpuis("MKL13*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")
|
|
bitfld.long 0x00 6.--7. " COPCLKSEL ,COP clock select" "LPO,MCGIRCLK,OSCERCLK,Bus clock"
|
|
newline
|
|
bitfld.long 0x00 5. " COPDBGEN ,COP debug enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " COPSTPEN ,COP stop enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 2.--3. " COPT ,COP watchdog timeout" "Disabled,2^5 LPO cycles/2^13 bus clock cycles,2^8 LPO cycles/2^16 bus clock cycles,2^10 LPO cycles/2^18 bus clock cycles"
|
|
newline
|
|
bitfld.long 0x00 1. " COPCLKS ,COP clock select" "Internal 1 khz clock,Bus clock"
|
|
newline
|
|
bitfld.long 0x00 0. " COPW ,COP windowed mode" "Normal,Windowed"
|
|
wgroup.long 0x104++0x03
|
|
line.long 0x00 "SRVCOP,Service COP Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SRVCOP ,Service COP register"
|
|
endif
|
|
sif cpuis("MKL28Z*")
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "PCSR,Peripheral Clock Status Register"
|
|
bitfld.long 0x00 7. " CS7 ,Clock Source 7 (Peripheral PLL) Status" "Not ready,Ready"
|
|
bitfld.long 0x00 6. " CS6 ,Clock Source 6 (System PLL) Status" "Not ready,Ready"
|
|
newline
|
|
bitfld.long 0x00 5. " CS5 ,Clock Source 5 (System FLL) Status" "Not ready,Ready"
|
|
bitfld.long 0x00 4. " CS4 ,Clock Source 4 (RTC Oscillator) Status" "Not ready,Ready"
|
|
newline
|
|
bitfld.long 0x00 3. " CS3 ,Clock Source 3 (Fast IRC Clock) Status" "Not ready,Ready"
|
|
bitfld.long 0x00 2. " CS2 ,Clock Source 2 (Slow IRC Clock) Status" "Not ready,Ready"
|
|
newline
|
|
bitfld.long 0x00 1. " CS1 ,Clock Source 1 (System Oscillator) Status" "Not ready,Ready"
|
|
endif
|
|
sif cpuis("MKL82Z*")
|
|
group.long 0x64++0x07
|
|
line.long 0x00 "CLKDIV3,System Clock Divider Register 3"
|
|
bitfld.long 0x00 1.--3. " PLLFLLDIV ,PLLFLL clock divider divisor" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " PLLFLLFRAC ,PLLFLL clock divider fraction" "0,1"
|
|
line.long 0x04 "MISCCTRL,Misc Control Register"
|
|
bitfld.long 0x04 16. " LTCEN ,LTC Status" "Not available,Available"
|
|
bitfld.long 0x04 3. " DMAINTSEL3 ,DMA channel 7 in vector 19 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " DMAINTSEL2 ,DMA channel 6 in vector 18 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " DMAINTSEL1 ,DMA channel 5 in vector 17 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0. " DMAINTSEL0 ,DMA channel 4 in vector 16 enable" "Disabled,Enabled"
|
|
rgroup.long 0x90++0x0F
|
|
line.long 0x00 "SECKEY0,Secure Key Register 0"
|
|
line.long 0x04 "SECKEY1,Secure Key Register 1"
|
|
line.long 0x08 "SECKEY2,Secure Key Register 2"
|
|
line.long 0x0C "SECKEY3,Secure Key Register 3"
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
tree "SMC (System Mode Controller)"
|
|
base ad:0x4007E000
|
|
width 10.
|
|
sif cpuis("MKL28*")
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "VERID,SMC Version ID Register "
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number"
|
|
line.long 0x04 "PARAM,SMC Parameter Register"
|
|
bitfld.long 0x04 6. " EVLLS0 ,Existence of VLLS0 feature" "Not available,Available"
|
|
bitfld.long 0x04 5. " ELLS2 ,Existence of LLS2 feature" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x04 3. " ELLS ,Existence of LLS feature" "Not available,Available"
|
|
bitfld.long 0x04 0. " EHSRUN ,Existence of HSRUN feature" "Not available,Available"
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "PMPROT,Power Mode Protection Register"
|
|
bitfld.long 0x00 7. " AHSRUN ,Allow High Speed Run mode" "Not allowed,Allowed"
|
|
bitfld.long 0x00 5. " AVLP ,Allow very-low-power modes" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ALLS ,Allow low-leakage stop mode" "Not allowed,Allowed"
|
|
bitfld.long 0x00 1. " AVLLS ,Allow very-low-leakage stop mode" "Not allowed,Allowed"
|
|
line.long 0x04 "PMCTRL,Power Mode Control Register"
|
|
bitfld.long 0x04 5.--6. " RUNM ,Run mode enable" "Normal,,Very low power,High speed run"
|
|
rbitfld.long 0x04 3. " STOPA ,Stop aborted" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " STOPM ,Stop mode control" "Normal stop,,VLPS,LLS,VLLSX,?..."
|
|
if ((per.b(ad:0x4007E000+0x1)&0x7)==0x4)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "STOPCTRL,Stop Control Register"
|
|
bitfld.long 0x00 6.--7. " PSTOPO ,Partial stop option" "STOP,PSTOP1,PSTOP2,?..."
|
|
bitfld.long 0x00 5. " PORPO ,POR power option" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LPOPO ,LPO power option" "Enabled,Disabled"
|
|
bitfld.long 0x00 0.--2. " VLLSM ,VLLS mode control" "VLLS0,VLLS1,VLLS2,VLLS3,?..."
|
|
else
|
|
group.long 0x010++0x03
|
|
line.long 0x00 "STOPCTRL,Stop Control Register"
|
|
bitfld.long 0x00 6.--7. " PSTOPO ,Partial stop option" "STOP,PSTOP1,PSTOP2,?..."
|
|
bitfld.long 0x00 5. " PORPO ,POR power option" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LPOPO ,LPO power option" "Enabled,Disabled"
|
|
bitfld.long 0x00 0.--2. " LLSM ,LLS mode control" ",,LLS2,LLS3,?..."
|
|
endif
|
|
rgroup.byte 0x14++0x03
|
|
line.byte 0x00 "PMSTAT,Power Mode Status Register"
|
|
bitfld.byte 0x00 7. " HSRUN ,Current power mode is HSRUN" "Off,On"
|
|
bitfld.byte 0x00 6. " VLLS ,Current power mode is VLLS" "Off,On"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " LLS ,Current power mode is LLS" "Off,On"
|
|
bitfld.byte 0x00 4. " VLPS ,Current power mode is VLPS" "Off,On"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " VLPW ,Current power mode is VLPW" "Off,On"
|
|
bitfld.byte 0x00 2. " VLPR ,Current power mode is VLPR" "Off,On"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " STOP ,Current power mode is STOP" "Off,On"
|
|
bitfld.byte 0x00 0. " RUN ,Current power mode is RUN" "Off,On"
|
|
else
|
|
group.byte 0x00++0x01
|
|
line.byte 0x00 "PMPROT,Power Mode Protection Register"
|
|
sif cpuis("MKL82*")
|
|
bitfld.byte 0x00 7. " AHSRUN ,Allow High Speed Run mode" "Not allowed,Allowed"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 5. " AVLP ,Allow very-low-power modes" "Not allowed,Allowed"
|
|
textline " "
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03*")
|
|
bitfld.byte 0x00 3. " ALLS ,Allow low-leakage stop mode" "Not allowed,Allowed"
|
|
bitfld.byte 0x00 1. " AVLLS ,Allow very-low-leakage stop mode" "Not allowed,Allowed"
|
|
else
|
|
bitfld.byte 0x00 1. " AVLLS ,Allow very-low-leakage stop mode" "Not allowed,Allowed"
|
|
endif
|
|
line.byte 0x01 "PMCTRL,Power Mode Control Register"
|
|
sif cpuis("MKL82*")
|
|
bitfld.byte 0x01 5.--6. " RUNM ,Run mode enable" "Normal,,Very low power,High speed run"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x01 5.--6. " RUNM ,Run mode enable" "Normal,,Very low power,?..."
|
|
textline " "
|
|
endif
|
|
rbitfld.byte 0x01 3. " STOPA ,Stop aborted" "Not aborted,Aborted"
|
|
textline " "
|
|
sif cpuis("MKL02*")||cpuis("MKL03*")
|
|
bitfld.byte 0x01 0.--2. " STOPM ,Stop mode control" "Normal stop,,VLPS,,VLLSX,?..."
|
|
else
|
|
bitfld.byte 0x01 0.--2. " STOPM ,Stop mode control" "Normal stop,,VLPS,LLS,VLLSX,?..."
|
|
endif
|
|
sif cpuis("MK14LN*")||cpuis("MKL14*")||cpuis("MK15LN*")||cpuis("MKL15Z*V*")
|
|
if ((per.b(ad:0x4007E000+0x1)&0x7)==0x4)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "VLLSCTRL,VLLS Control Register"
|
|
bitfld.byte 0x00 5. " PORPO ,POR power option" "Enabled,Disabled"
|
|
bitfld.byte 0x00 0.--2. " VLLSM ,VLLS mode control" "VLLS0,VLLS1,VLLS2,VLLS3,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "VLLSCTRL,VLLS Control Register"
|
|
bitfld.byte 0x00 5. " PORPO ,POR power option" "Enabled,Disabled"
|
|
endif
|
|
else
|
|
if ((per.b(ad:0x4007E000+0x1)&0x7)==0x4)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "STOPCTRL,Stop Control Register"
|
|
bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "STOP,PSTOP1,PSTOP2,?..."
|
|
bitfld.byte 0x00 5. " PORPO ,POR power option" "Enabled,Disabled"
|
|
textline " "
|
|
sif cpuis("MKL03Z*")||cpuis("MKL13Z*")||cpuis("MKL17Z32*")||cpuis("MKL17Z64*")||cpuis("MKL27Z32*")||cpuis("MKL27Z64*")||cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
bitfld.byte 0x00 3. " LPOPO ,LPO power option" "Enabled,Disabled"
|
|
bitfld.byte 0x00 0.--2. " VLLSM ,VLLS mode control" "VLLS0,VLLS1,,VLLS3,?..."
|
|
elif cpuis("MKL82Z*")
|
|
bitfld.byte 0x00 3. " LPOPO ,LPO power option" "Enabled,Disabled"
|
|
bitfld.byte 0x00 0.--2. " VLLSM ,VLLS mode control" "VLLS0,VLLS1,VLLS2,VLLS3,?..."
|
|
else
|
|
bitfld.byte 0x00 0.--2. " VLLSM ,VLLS mode control" "VLLS0,VLLS1,,VLLS3,?..."
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "STOPCTRL,Stop Control Register"
|
|
bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "STOP,PSTOP1,PSTOP2,?..."
|
|
bitfld.byte 0x00 5. " PORPO ,POR power option" "Enabled,Disabled"
|
|
textline " "
|
|
sif cpuis("MKL03Z*")||cpuis("MKL13Z*")||cpuis("MKL17Z32*")||cpuis("MKL17Z64*")||cpuis("MKL27Z32*")||cpuis("MKL27Z64*")||cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LPOPO ,LPO power option" "Enabled,Disabled"
|
|
elif cpuis("MKL82Z*")
|
|
bitfld.byte 0x00 3. " LPOPO ,LPO power option" "Enabled,Disabled"
|
|
bitfld.byte 0x00 0.--2. " LLSM ,LLS mode control" ",,LLS2,LLS3,?..."
|
|
endif
|
|
endif
|
|
endif
|
|
sif cpuis("MKL02Z*")||cpuis("MKL03Z*")
|
|
rgroup.byte 0x03++0x00
|
|
line.byte 0x00 "PMSTAT,Power Mode Status Register"
|
|
bitfld.byte 0x00 6. " VLLS ,Current power mode is VLLS" "Off,On"
|
|
bitfld.byte 0x00 4. " VLPS ,Current power mode is VLPS" "Off,On"
|
|
bitfld.byte 0x00 3. " VLPW ,Current power mode is VLPW" "Off,On"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " VLPR ,Current power mode is VLPR" "Off,On"
|
|
bitfld.byte 0x00 1. " STOP ,Current power mode is STOP" "Off,On"
|
|
bitfld.byte 0x00 0. " RUN ,Current power mode is RUN" "Off,On"
|
|
elif cpuis("MKL82Z*")
|
|
rgroup.byte 0x03++0x00
|
|
line.byte 0x00 "PMSTAT,Power Mode Status Register"
|
|
bitfld.byte 0x00 7. " HSRUN ,Current power mode is HSRUN" "Off,On"
|
|
bitfld.byte 0x00 6. " VLLS ,Current power mode is VLLS" "Off,On"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " LLS ,Current power mode is LLS" "Off,On"
|
|
bitfld.byte 0x00 4. " VLPS ,Current power mode is VLPS" "Off,On"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " VLPW ,Current power mode is VLPW" "Off,On"
|
|
bitfld.byte 0x00 2. " VLPR ,Current power mode is VLPR" "Off,On"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " STOP ,Current power mode is STOP" "Off,On"
|
|
bitfld.byte 0x00 0. " RUN ,Current power mode is RUN" "Off,On"
|
|
else
|
|
rgroup.byte 0x03++0x00
|
|
line.byte 0x00 "PMSTAT,Power Mode Status Register"
|
|
bitfld.byte 0x00 6. " VLLS ,Current power mode is VLLS" "Off,On"
|
|
bitfld.byte 0x00 5. " LLS ,Current power mode is LLS" "Off,On"
|
|
bitfld.byte 0x00 4. " VLPS ,Current power mode is VLPS" "Off,On"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " VLPW ,Current power mode is VLPW" "Off,On"
|
|
bitfld.byte 0x00 2. " VLPR ,Current power mode is VLPR" "Off,On"
|
|
bitfld.byte 0x00 1. " STOP ,Current power mode is STOP" "Off,On"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " RUN ,Current power mode is RUN" "Off,On"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "PMC (Power Management Controller)"
|
|
base ad:0x4007D000
|
|
width 8.
|
|
sif cpuis("MKL28*")
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number"
|
|
line.long 0x04 "PARAM,Parameter Register"
|
|
bitfld.long 0x04 1. " HVDE ,HVD Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " VLPOE ,VLPO Enabled" "Disabled,Enabled"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "LVDSC1,Low Voltage Detect Status And Control 1 Register"
|
|
rbitfld.long 0x00 7. " LVDF ,Low-voltage detect flag" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " LVDACK ,Low-voltage detect acknowledge" "NACK,ACK"
|
|
bitfld.long 0x00 5. " LVDIE ,Low-voltage detect interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LVDRE ,Low-voltage detect reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " LVDV ,Low-voltage detect voltage select" "Low point,High point,?..."
|
|
line.long 0x04 "LVDSC2,Low Voltage Detect Status And Control 2 Register"
|
|
rbitfld.long 0x04 7. " LVWF ,Low-voltage warning flag" "Not detected,Detected"
|
|
bitfld.long 0x04 6. " LVWACK ,Low-voltage warning acknowledge" "NACK,ACK"
|
|
bitfld.long 0x04 5. " LVWIE ,Low-voltage warning interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " LVWV ,Low-voltage warning voltage select" "Low point,Mid 1 point,Mid 2 point,High point"
|
|
line.long 0x08 "REGSC,Regulator Status And Control Register"
|
|
bitfld.long 0x08 6. " VLPO ,Vlpx option. Allows additional clock sources and higher frequency operation to be selected during vlpx modes" "Not allowed,Allowed"
|
|
bitfld.long 0x08 4. " BGEN ,Bandgap enable" "Disabled,Enabled"
|
|
eventfld.long 0x08 3. " ACKISO ,Acknowledge isolation" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x08 2. " REGONS ,Regulator in run regulation status" "Stop,Run"
|
|
bitfld.long 0x08 0. " BGBE ,Bandgap buffer enable" "Disabled,Enabled"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "HVDSC1,High Voltage Detect Status And Control 1 Register"
|
|
rbitfld.long 0x00 7. " HVDF ,High-Voltage detect flag" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " HVDACK ,High-Voltage Detect Acknowledge" "HVDF,ACK"
|
|
bitfld.long 0x00 5. " HVDIE ,High-Voltage Detect Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HVDRE ,High-Voltage Detect Reset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " HVDV ,High-Voltage Detect Voltage Select" "Low,High"
|
|
else
|
|
group.byte 0x00++0x02
|
|
line.byte 0x00 "LVDSC1,Low Voltage Detect Status And Control 1 Register"
|
|
rbitfld.byte 0x00 7. " LVDF ,Low-voltage detect flag" "Not detected,Detected"
|
|
bitfld.byte 0x00 6. " LVDACK ,Low-voltage detect acknowledge" "NACK,ACK"
|
|
bitfld.byte 0x00 5. " LVDIE ,Low-voltage detect interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " LVDRE ,Low-voltage detect reset enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " LVDV ,Low-voltage detect voltage select" "Low point,High point,?..."
|
|
line.byte 0x01 "LVDSC2,Low Voltage Detect Status And Control 2 Register"
|
|
rbitfld.byte 0x01 7. " LVWF ,Low-voltage warning flag" "Not detected,Detected"
|
|
bitfld.byte 0x01 6. " LVWACK ,Low-voltage warning acknowledge" "NACK,ACK"
|
|
bitfld.byte 0x01 5. " LVWIE ,Low-voltage warning interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 0.--1. " LVWV ,Low-voltage warning voltage select" "Low point,Mid 1 point,Mid 2 point,High point"
|
|
sif cpuis("MKL13*")||cpuis("MKL17Z32*")||cpuis("MKL17Z64*")||cpuis("MKL27Z32*")||cpuis("MKL27Z64*")||cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
line.byte 0x02 "REGSC,Regulator Status And Control Register"
|
|
bitfld.byte 0x02 6. " VLPO ,Vlpx option. Allows additional clock sources and higher frequency operation to be selected during vlpx modes" "Not allowed,Allowed"
|
|
bitfld.byte 0x02 4. " BGEN ,Bandgap enable" "Disabled,Enabled"
|
|
eventfld.byte 0x02 3. " ACKISO ,Acknowledge isolation" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x02 2. " REGONS ,Regulator in run regulation status" "Stop,Run"
|
|
bitfld.byte 0x02 0. " BGBE ,Bandgap buffer enable" "Disabled,Enabled"
|
|
else
|
|
line.byte 0x02 "REGSC,Regulator Status And Control Register"
|
|
bitfld.byte 0x02 4. " BGEN ,Bandgap enable" "Disabled,Enabled"
|
|
eventfld.byte 0x02 3. " ACKISO ,Acknowledge isolation" "Disabled,Enabled"
|
|
rbitfld.byte 0x02 2. " REGONS ,Regulator in run regulation status" "Stop,Run"
|
|
textline " "
|
|
bitfld.byte 0x02 0. " BGBE ,Bandgap buffer enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif !cpuis("MKL02*")
|
|
tree "LLWU (Low-Leakage Wake-up Unit)"
|
|
sif cpuis("MKL28*")
|
|
base ad:0x40061000
|
|
width 9.
|
|
sif cpuis("MKL03*")||cpuis("MKL04*")||cpuis("MKL05*")
|
|
group.byte 0x00++0x02
|
|
line.byte 0x00 "PE1,LLWU Pin Enable 1 Register"
|
|
bitfld.byte 0x00 6.--7. " WUPE3 ,Wakeup pin enable for LLWU_P3" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x00 4.--5. " WUPE2 ,Wakeup pin enable for LLWU_P2" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x00 2.--3. " WUPE1 ,Wakeup pin enable for LLWU_P1" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x00 0.--1. " WUPE0 ,Wakeup pin enable for LLWU_P0" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
line.byte 0x01 "PE2,LLWU Pin Enable 2 Register"
|
|
bitfld.byte 0x01 6.--7. " WUPE7 ,Wakeup pin enable for LLWU_P7" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x01 4.--5. " WUPE6 ,Wakeup pin enable for LLWU_P6" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x01 2.--3. " WUPE5 ,Wakeup pin enable for LLWU_P5" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x01 0.--1. " WUPE4 ,Wakeup pin enable for LLWU_P4" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
line.byte 0x02 "ME,LLWU Module Enable Register"
|
|
bitfld.byte 0x02 7. " WUME7 ,Wakeup module enable for module 7" "Disabled,Enabled"
|
|
bitfld.byte 0x02 6. " WUME6 ,Wakeup module enable for module 6" "Disabled,Enabled"
|
|
bitfld.byte 0x02 5. " WUME5 ,Wakeup module enable for module 5" "Disabled,Enabled"
|
|
bitfld.byte 0x02 4. " WUME4 ,Wakeup module enable for module 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x02 3. " WUME3 ,Wakeup module enable for module 3" "Disabled,Enabled"
|
|
bitfld.byte 0x02 2. " WUME2 ,Wakeup module enable for module 2" "Disabled,Enabled"
|
|
bitfld.byte 0x02 1. " WUME1 ,Wakeup module enable for module 1" "Disabled,Enabled"
|
|
bitfld.byte 0x02 0. " WUME0 ,Wakeup module enable for module 1" "Disabled,Enabled"
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "F1,LLWU Flag 1 Register"
|
|
eventfld.byte 0x00 7. " WUF7 ,Wakeup flag for LLWU_P7" "Disabled,Enabled"
|
|
eventfld.byte 0x00 6. " WUF6 ,Wakeup flag for LLWU_P6" "Disabled,Enabled"
|
|
eventfld.byte 0x00 5. " WUF5 ,Wakeup flag for LLWU_P5" "Disabled,Enabled"
|
|
eventfld.byte 0x00 4. " WUF4 ,Wakeup flag for LLWU_P4" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.byte 0x00 3. " WUF3 ,Wakeup flag for LLWU_P3" "Disabled,Enabled"
|
|
eventfld.byte 0x00 2. " WUF2 ,Wakeup flag for LLWU_P2" "Disabled,Enabled"
|
|
eventfld.byte 0x00 1. " WUF1 ,Wakeup flag for LLWU_P1" "Disabled,Enabled"
|
|
eventfld.byte 0x00 0. " WUF0 ,Wakeup flag for LLWU_P0" "Disabled,Enabled"
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "F3,LLWU Flag 3 Register"
|
|
sif cpuis("MKL05*")||cpuis("MKL03*")
|
|
bitfld.byte 0x00 7. " MWUF7 ,Wakeup flag for module 7" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 6. " MWUF6 ,Wakeup flag for module 6" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 5. " MWUF5 ,Wakeup flag for module 5" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " MWUF4 ,Wakeup flag for module 4" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MWUF3 ,Wakeup flag for module 3" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " MWUF2 ,Wakeup flag for module 2" "Not occurred,Occurred"
|
|
else
|
|
bitfld.byte 0x00 7. " MWUF7 ,Wakeup flag for RTC seconds" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 5. " MWUF5 ,Wakeup flag for RTC alarm" "Not occurred,Occurred"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " MWUF1 ,Wakeup flag for module 1" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " MWUF0 ,Wakeup flag for module 0" "Not occurred,Occurred"
|
|
group.byte 0x05++0x01
|
|
line.byte 0x00 "FILT1,LLWU Pin Filter 1 Register"
|
|
eventfld.byte 0x00 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup"
|
|
bitfld.byte 0x00 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
sif cpuis("MKL03Z*")||cpuis("MKL05*")
|
|
bitfld.byte 0x00 0.--3. " FILTSEL ,Filter pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15"
|
|
else
|
|
bitfld.byte 0x00 0.--3. " FILTSEL ,Filter pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,?..."
|
|
endif
|
|
line.byte 0x01 "FILT2,LLWU Pin Filter 2 Register"
|
|
eventfld.byte 0x01 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup"
|
|
bitfld.byte 0x01 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
sif cpuis("MKL03Z*")||cpuis("MKL05*")
|
|
bitfld.byte 0x01 0.--3. " FILTSEL ,Filter pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15"
|
|
else
|
|
bitfld.byte 0x01 0.--3. " FILTSEL ,Filter pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,?..."
|
|
endif
|
|
elif cpuis("MKL28Z*")
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number"
|
|
line.long 0x04 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " PINS ,Pin number"
|
|
hexmask.long.byte 0x04 16.--23. 1. " MODULES ,Module number"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " DMAS ,DMA number"
|
|
hexmask.long.byte 0x04 0.--7. 1. " FILTERS ,Filter number"
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "PE1,LLWU Pin Enable 1 Register"
|
|
bitfld.long 0x00 30.--31. " WUPE15 ,Wakeup pin enable for LLWU_P15" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x00 28.--29. " WUPE14 ,Wakeup pin enable for LLWU_P14" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x00 26.--27. " WUPE13 ,Wakeup pin enable for LLWU_P13" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x00 24.--25. " WUPE12 ,Wakeup pin enable for LLWU_P12" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " WUPE11 ,Wakeup pin enable for LLWU_P11" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x00 20.--21. " WUPE10 ,Wakeup pin enable for LLWU_P10" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x00 18.--19. " WUPE9 ,Wakeup pin enable for LLWU_P9" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x00 16.--17. " WUPE8 ,Wakeup pin enable for LLWU_P8" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " WUPE7 ,Wakeup pin enable for LLWU_P7" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x00 12.--13. " WUPE6 ,Wakeup pin enable for LLWU_P6" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x00 10.--11. " WUPE5 ,Wakeup pin enable for LLWU_P5" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x00 8.--9. " WUPE4 ,Wakeup pin enable for LLWU_P4" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " WUPE3 ,Wakeup pin enable for LLWU_P3" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x00 4.--5. " WUPE2 ,Wakeup pin enable for LLWU_P2" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x00 2.--3. " WUPE1 ,Wakeup pin enable for LLWU_P1" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x00 0.--1. " WUPE0 ,Wakeup pin enable for LLWU_P0" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
line.long 0x04 "PE2,LLWU Pin Enable 2 Register"
|
|
bitfld.long 0x04 30.--31. " WUPE31 ,Wakeup pin enable for LLWU_P31" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x04 28.--29. " WUPE30 ,Wakeup pin enable for LLWU_P30" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x04 26.--27. " WUPE29 ,Wakeup pin enable for LLWU_P29" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x04 24.--25. " WUPE28 ,Wakeup pin enable for LLWU_P28" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
textline " "
|
|
bitfld.long 0x04 22.--23. " WUPE27 ,Wakeup pin enable for LLWU_P27" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x04 20.--21. " WUPE26 ,Wakeup pin enable for LLWU_P26" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x04 18.--19. " WUPE25 ,Wakeup pin enable for LLWU_P25" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x04 16.--17. " WUPE24 ,Wakeup pin enable for LLWU_P24" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " WUPE23 ,Wakeup pin enable for LLWU_P23" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x04 12.--13. " WUPE22 ,Wakeup pin enable for LLWU_P22" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x04 10.--11. " WUPE21 ,Wakeup pin enable for LLWU_P21" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x04 8.--9. " WUPE20 ,Wakeup pin enable for LLWU_P20" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " WUPE19 ,Wakeup pin enable for LLWU_P19" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x04 4.--5. " WUPE18 ,Wakeup pin enable for LLWU_P18" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x04 2.--3. " WUPE17 ,Wakeup pin enable for LLWU_P17" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x04 0.--1. " WUPE16 ,Wakeup pin enable for LLWU_P16" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
group.long 0x18++0x0B
|
|
line.long 0x00 "ME,LLWU Module Interrupt Enable Register"
|
|
bitfld.long 0x00 7. " WUME7 ,Wakeup module enable for module 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " WUME6 ,Wakeup module enable for module 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " WUME5 ,Wakeup module enable for module 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " WUME4 ,Wakeup module enable for module 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " WUME3 ,Wakeup module enable for module 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " WUME2 ,Wakeup module enable for module 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " WUME1 ,Wakeup module enable for module 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " WUME0 ,Wakeup module enable for module 0" "Disabled,Enabled"
|
|
line.long 0x04 "DE,LLWU Module DMA Enable Register"
|
|
bitfld.long 0x04 7. " WUDE7 ,DMA wakeup enable for module 7" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " WUDE6 ,DMA wakeup enable for module 6" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " WUDE5 ,DMA wakeup enable for module 5" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " WUDE4 ,DMA wakeup enable for module 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " WUDE3 ,DMA wakeup enable for module 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " WUDE2 ,DMA wakeup enable for module 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " WUDE1 ,DMA wakeup enable for module 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " WUDE0 ,DMA wakeup enable for module 0" "Disabled,Enabled"
|
|
line.long 0x08 "PF,LLWU Pin Flag Register"
|
|
eventfld.long 0x08 31. " WUF31 ,Wakeup flag for LLWU_P31" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 30. " WUF30 ,Wakeup flag for LLWU_P30" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 29. " WUF29 ,Wakeup flag for LLWU_P29" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 28. " WUF28 ,Wakeup flag for LLWU_P28" "No wakeup,Wakeup"
|
|
textline " "
|
|
eventfld.long 0x08 27. " WUF27 ,Wakeup flag for LLWU_P27" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 26. " WUF26 ,Wakeup flag for LLWU_P26" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 25. " WUF25 ,Wakeup flag for LLWU_P25" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 24. " WUF24 ,Wakeup flag for LLWU_P24" "No wakeup,Wakeup"
|
|
textline " "
|
|
eventfld.long 0x08 23. " WUF23 ,Wakeup flag for LLWU_P23" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 22. " WUF22 ,Wakeup flag for LLWU_P22" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 21. " WUF21 ,Wakeup flag for LLWU_P21" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 20. " WUF20 ,Wakeup flag for LLWU_P20" "No wakeup,Wakeup"
|
|
textline " "
|
|
eventfld.long 0x08 19. " WUF19 ,Wakeup flag for LLWU_P19" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 18. " WUF18 ,Wakeup flag for LLWU_P18" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 17. " WUF17 ,Wakeup flag for LLWU_P17" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 16. " WUF16 ,Wakeup flag for LLWU_P16" "No wakeup,Wakeup"
|
|
textline " "
|
|
eventfld.long 0x08 15. " WUF15 ,Wakeup flag for LLWU_P15" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 14. " WUF14 ,Wakeup flag for LLWU_P14" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 13. " WUF13 ,Wakeup flag for LLWU_P13" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 12. " WUF12 ,Wakeup flag for LLWU_P12" "No wakeup,Wakeup"
|
|
textline " "
|
|
eventfld.long 0x08 11. " WUF11 ,Wakeup flag for LLWU_P11" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 10. " WUF10 ,Wakeup flag for LLWU_P10" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 9. " WUF9 ,Wakeup flag for LLWU_P9" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 8. " WUF8 ,Wakeup flag for LLWU_P8" "No wakeup,Wakeup"
|
|
textline " "
|
|
eventfld.long 0x08 7. " WUF7 ,Wakeup flag for LLWU_P7" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 6. " WUF6 ,Wakeup flag for LLWU_P6" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 5. " WUF5 ,Wakeup flag for LLWU_P5" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 4. " WUF4 ,Wakeup flag for LLWU_P4" "No wakeup,Wakeup"
|
|
textline " "
|
|
eventfld.long 0x08 3. " WUF3 ,Wakeup flag for LLWU_P3" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 2. " WUF2 ,Wakeup flag for LLWU_P2" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 1. " WUF1 ,Wakeup flag for LLWU_P1" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 0. " WUF0 ,Wakeup flag for LLWU_P0" "No wakeup,Wakeup"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "MF,LLWU Module Interrupt Flag Register"
|
|
bitfld.long 0x00 7. " MWUF7 ,Wakeup flag for module 7" "No error,Error"
|
|
bitfld.long 0x00 6. " MWUF6 ,Wakeup flag for module 6" "No error,Error"
|
|
bitfld.long 0x00 5. " MWUF5 ,Wakeup flag for module 5" "No error,Error"
|
|
bitfld.long 0x00 4. " MWUF4 ,Wakeup flag for module 4" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MWUF3 ,Wakeup flag for module 3" "No error,Error"
|
|
bitfld.long 0x00 2. " MWUF2 ,Wakeup flag for module 2" "No error,Error"
|
|
bitfld.long 0x00 1. " MWUF1 ,Wakeup flag for module 1" "No error,Error"
|
|
bitfld.long 0x00 0. " MWUF0 ,Wakeup flag for module 0" "No error,Error"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "FILT,LLWU Pin Filter Register"
|
|
eventfld.long 0x00 31. " FILTF4 ,Filter 4 flag" "No wakeup,Wakeup"
|
|
bitfld.long 0x00 29.--30. " FILTE4 ,Filter 4 enable" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x00 24.--28. " FILTSEL4 ,Filter 4 pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,LLWU_P16,LLWU_P17,LLWU_P18,LLWU_P19,LLWU_P20,LLWU_P21,LLWU_P22,LLWU_P23,LLWU_P24,LLWU_P25,LLWU_P26,LLWU_P27,LLWU_P28,LLWU_P29,LLWU_P30,LLWU_P31"
|
|
textline " "
|
|
eventfld.long 0x00 23. " FILTF3 ,Filter 3 flag" "No wakeup,Wakeup"
|
|
bitfld.long 0x00 21.--22. " FILTE3 ,Filter 3 enable" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x00 16.--20. " FILTSEL3 ,Filter 3 pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,LLWU_P16,LLWU_P17,LLWU_P18,LLWU_P19,LLWU_P20,LLWU_P21,LLWU_P22,LLWU_P23,LLWU_P24,LLWU_P25,LLWU_P26,LLWU_P27,LLWU_P28,LLWU_P29,LLWU_P30,LLWU_P31"
|
|
textline " "
|
|
eventfld.long 0x00 15. " FILTF2 ,Filter 2 flag" "No wakeup,Wakeup"
|
|
bitfld.long 0x00 13.--14. " FILTE2 ,Filter 2 enable" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x00 8.--12. " FILTSEL2 ,Filter 2 pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,LLWU_P16,LLWU_P17,LLWU_P18,LLWU_P19,LLWU_P20,LLWU_P21,LLWU_P22,LLWU_P23,LLWU_P24,LLWU_P25,LLWU_P26,LLWU_P27,LLWU_P28,LLWU_P29,LLWU_P30,LLWU_P31"
|
|
textline " "
|
|
eventfld.long 0x00 7. " FILTF1 ,Filter 1 flag" "No wakeup,Wakeup"
|
|
bitfld.long 0x00 5.--6. " FILTE1 ,Filter 1 enable" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x00 0.--4. " FILTSEL1 ,Filter 1 pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,LLWU_P16,LLWU_P17,LLWU_P18,LLWU_P19,LLWU_P20,LLWU_P21,LLWU_P22,LLWU_P23,LLWU_P24,LLWU_P25,LLWU_P26,LLWU_P27,LLWU_P28,LLWU_P29,LLWU_P30,LLWU_P31"
|
|
else
|
|
sif cpuis("MKL13Z*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL17Z256*")||cpuis("MKL33Z*")||cpuis("MKL82Z*")
|
|
group.byte 0x00++0x02
|
|
line.byte 0x00 "PE1,LLWU Pin Enable 1 Register"
|
|
bitfld.byte 0x00 6.--7. " WUPE3 ,Wakeup pin enable for LLWU_P3" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x00 4.--5. " WUPE2 ,Wakeup pin enable for LLWU_P2" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x00 2.--3. " WUPE1 ,Wakeup pin enable for LLWU_P1" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x00 0.--1. " WUPE0 ,Wakeup pin enable for LLWU_P0" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
endif
|
|
group.byte 0x01++0x02
|
|
line.byte 0x00 "PE2,LLWU Pin Enable 2 Register"
|
|
bitfld.byte 0x00 6.--7. " WUPE7 ,Wakeup pin enable for LLWU_P7" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x00 4.--5. " WUPE6 ,Wakeup pin enable for LLWU_P6" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x00 2.--3. " WUPE5 ,Wakeup pin enable for LLWU_P5" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
textline " "
|
|
sif cpuis("MKL13Z*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL17Z256*")||cpuis("MKL33Z*")||cpuis("MKL82Z*")
|
|
bitfld.byte 0x00 0.--1. " WUPE4 ,Wakeup pin enable for LLWU_P4" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
endif
|
|
line.byte 0x01 "PE3,LLWU Pin Enable 3 Register"
|
|
sif cpuis("MKL13Z*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL17Z256*")||cpuis("MKL33Z*")||cpuis("MKL82Z*")
|
|
bitfld.byte 0x01 6.--7. " WUPE11 ,Wakeup pin enable for LLWU_P11" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x01 4.--5. " WUPE10 ,Wakeup pin enable for LLWU_P10" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x01 2.--3. " WUPE9 ,Wakeup pin enable for LLWU_P9" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x01 0.--1. " WUPE8 ,Wakeup pin enable for LLWU_P8" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
line.byte 0x02 "PE4,LLWU Pin Enable 4 Register"
|
|
bitfld.byte 0x02 6.--7. " WUPE15 ,Wakeup pin enable for LLWU_P15" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x02 4.--5. " WUPE14 ,Wakeup pin enable for LLWU_P14" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
textline " "
|
|
sif cpuis("MKL13Z*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL17Z256*")||cpuis("MKL33Z*")||cpuis("MKL82Z*")
|
|
bitfld.byte 0x02 2.--3. " WUPE13 ,Wakeup pin enable for LLWU_P13" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x02 0.--1. " WUPE12 ,Wakeup pin enable for LLWU_P12" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
endif
|
|
sif cpuis("MKL82Z*")
|
|
group.byte 0x04++0x0D
|
|
line.byte 0x00 "PE5,LLWU Pin Enable 5 Register"
|
|
bitfld.byte 0x00 6.--7. " WUPE19 ,Wakeup pin enable for LLWU_P19" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x00 4.--5. " WUPE18 ,Wakeup pin enable for LLWU_P18" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x00 2.--3. " WUPE17 ,Wakeup pin enable for LLWU_P17" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x00 0.--1. " WUPE16 ,Wakeup pin enable for LLWU_P16" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
line.byte 0x01 "PE6,LLWU Pin Enable 6 Register"
|
|
bitfld.byte 0x01 6.--7. " WUPE23 ,Wakeup pin enable for LLWU_P23" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x01 4.--5. " WUPE22 ,Wakeup pin enable for LLWU_P22" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x01 2.--3. " WUPE21 ,Wakeup pin enable for LLWU_P21" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x01 0.--1. " WUPE20 ,Wakeup pin enable for LLWU_P20" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
line.byte 0x02 "PE7,LLWU Pin Enable 7 Register"
|
|
bitfld.byte 0x02 6.--7. " WUPE27 ,Wakeup pin enable for LLWU_P27" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x02 4.--5. " WUPE26 ,Wakeup pin enable for LLWU_P26" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x02 2.--3. " WUPE25 ,Wakeup pin enable for LLWU_P25" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x02 0.--1. " WUPE24 ,Wakeup pin enable for LLWU_P24" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
line.byte 0x03 "PE8,LLWU Pin Enable 8 Register"
|
|
bitfld.byte 0x03 6.--7. " WUPE31 ,Wakeup pin enable for LLWU_P31" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x03 4.--5. " WUPE30 ,Wakeup pin enable for LLWU_P30" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x03 2.--3. " WUPE29 ,Wakeup pin enable for LLWU_P29" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x03 0.--1. " WUPE28 ,Wakeup pin enable for LLWU_P28" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
line.byte 0x04 "ME,LLWU Module Enable Register"
|
|
bitfld.byte 0x04 7. " WUME7 ,Wakeup module enable for module 7" "Disabled,Enabled"
|
|
bitfld.byte 0x04 6. " WUME6 ,Wakeup module enable for module 6" "Disabled,Enabled"
|
|
bitfld.byte 0x04 5. " WUME5 ,Wakeup module enable for module 5" "Disabled,Enabled"
|
|
bitfld.byte 0x04 4. " WUME4 ,Wakeup module enable for module 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x04 3. " WUME3 ,Wakeup module enable for module 3" "Disabled,Enabled"
|
|
bitfld.byte 0x04 2. " WUME2 ,Wakeup module enable for module 2" "Disabled,Enabled"
|
|
bitfld.byte 0x04 1. " WUME1 ,Wakeup module enable for module 1" "Disabled,Enabled"
|
|
bitfld.byte 0x04 0. " WUME0 ,Wakeup module enable for module 0" "Disabled,Enabled"
|
|
line.byte 0x05 "PF1,LLWU Pin Flag 1 Register"
|
|
eventfld.byte 0x05 7. " WUF7 ,Wakeup flag for LLWU_P7" "Disabled,Enabled"
|
|
eventfld.byte 0x05 6. " WUF6 ,Wakeup flag for LLWU_P6" "Disabled,Enabled"
|
|
eventfld.byte 0x05 5. " WUF5 ,Wakeup flag for LLWU_P5" "Disabled,Enabled"
|
|
eventfld.byte 0x05 4. " WUF4 ,Wakeup flag for LLWU_P5" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.byte 0x05 3. " WUF3 ,Wakeup flag for LLWU_P3" "Disabled,Enabled"
|
|
eventfld.byte 0x05 2. " WUF2 ,Wakeup flag for LLWU_P2" "Disabled,Enabled"
|
|
eventfld.byte 0x05 1. " WUF1 ,Wakeup flag for LLWU_P1" "Disabled,Enabled"
|
|
eventfld.byte 0x05 0. " WUF0 ,Wakeup flag for LLWU_P0" "Disabled,Enabled"
|
|
line.byte 0x06 "PF2,LLWU Pin Flag 2 Register"
|
|
eventfld.byte 0x06 7. " WUF15 ,Wakeup flag for LLWU_P15" "Disabled,Enabled"
|
|
eventfld.byte 0x06 6. " WUF14 ,Wakeup flag for LLWU_P14" "Disabled,Enabled"
|
|
eventfld.byte 0x06 5. " WUF13 ,Wakeup flag for LLWU_P13" "Disabled,Enabled"
|
|
eventfld.byte 0x06 4. " WUF12 ,Wakeup flag for LLWU_P12" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.byte 0x06 3. " WUF11 ,Wakeup flag for LLWU_P11" "Disabled,Enabled"
|
|
eventfld.byte 0x06 2. " WUF10 ,Wakeup flag for LLWU_P10" "Disabled,Enabled"
|
|
eventfld.byte 0x06 1. " WUF9 ,Wakeup flag for LLWU_P9" "Disabled,Enabled"
|
|
eventfld.byte 0x06 0. " WUF8 ,Wakeup flag for LLWU_P8" "Disabled,Enabled"
|
|
line.byte 0x07 "PF3,LLWU Pin Flag 3 Register"
|
|
eventfld.byte 0x07 7. " WUF23 ,Wakeup flag for LLWU_P23" "Disabled,Enabled"
|
|
eventfld.byte 0x07 6. " WUF22 ,Wakeup flag for LLWU_P22" "Disabled,Enabled"
|
|
eventfld.byte 0x07 5. " WUF21 ,Wakeup flag for LLWU_P21" "Disabled,Enabled"
|
|
eventfld.byte 0x07 4. " WUF20 ,Wakeup flag for LLWU_P20" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.byte 0x07 3. " WUF19 ,Wakeup flag for LLWU_P19" "Disabled,Enabled"
|
|
eventfld.byte 0x07 2. " WUF18 ,Wakeup flag for LLWU_P18" "Disabled,Enabled"
|
|
eventfld.byte 0x07 1. " WUF17 ,Wakeup flag for LLWU_P17" "Disabled,Enabled"
|
|
eventfld.byte 0x07 0. " WUF16 ,Wakeup flag for LLWU_P16" "Disabled,Enabled"
|
|
line.byte 0x08 "PF4,LLWU Pin Flag 4 Register"
|
|
eventfld.byte 0x08 7. " WUF31 ,Wakeup flag for LLWU_P31" "Disabled,Enabled"
|
|
eventfld.byte 0x08 6. " WUF30 ,Wakeup flag for LLWU_P30" "Disabled,Enabled"
|
|
eventfld.byte 0x08 5. " WUF29 ,Wakeup flag for LLWU_P29" "Disabled,Enabled"
|
|
eventfld.byte 0x08 4. " WUF28 ,Wakeup flag for LLWU_P28" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.byte 0x08 3. " WUF27 ,Wakeup flag for LLWU_P27" "Disabled,Enabled"
|
|
eventfld.byte 0x08 2. " WUF26 ,Wakeup flag for LLWU_P26" "Disabled,Enabled"
|
|
eventfld.byte 0x08 1. " WUF25 ,Wakeup flag for LLWU_P25" "Disabled,Enabled"
|
|
eventfld.byte 0x08 0. " WUF24 ,Wakeup flag for LLWU_P24" "Disabled,Enabled"
|
|
line.byte 0x09 "MF5,LLWU Module Flag 5 Register"
|
|
bitfld.byte 0x09 7. " MWUF7 ,Wakeup flag for module 7" "No error,Error"
|
|
bitfld.byte 0x09 6. " MWUF6 ,Wakeup flag for module 6" "No error,Error"
|
|
bitfld.byte 0x09 5. " MWUF5 ,Wakeup flag for module 5" "No error,Error"
|
|
bitfld.byte 0x09 4. " MWUF4 ,Wakeup flag for module 4" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x09 3. " MWUF3 ,Wakeup flag for module 3" "No error,Error"
|
|
bitfld.byte 0x09 2. " MWUF2 ,Wakeup flag for module 2" "No error,Error"
|
|
bitfld.byte 0x09 1. " MWUF1 ,Wakeup flag for module 1" "No error,Error"
|
|
bitfld.byte 0x09 0. " MWUF0 ,Wakeup flag for module 0" "No error,Error"
|
|
line.byte 0x0A "FILT1,LLWU Pin Filter 1 Register"
|
|
eventfld.byte 0x0A 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup"
|
|
bitfld.byte 0x0A 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.byte 0x0A 0.--4. " FILTSEL ,Filter pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,LLWU_P16,LLWU_P17,LLWU_P18,LLWU_P19,LLWU_P20,LLWU_P21,LLWU_P22,LLWU_P23,LLWU_P24,LLWU_P25,LLWU_P26,LLWU_P27,LLWU_P28,LLWU_P29,LLWU_P30,LLWU_P31"
|
|
line.byte 0x0B "FILT2,LLWU Pin Filter 2 Register"
|
|
eventfld.byte 0x0B 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup"
|
|
bitfld.byte 0x0B 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.byte 0x0B 0.--4. " FILTSEL ,Filter pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,LLWU_P16,LLWU_P17,LLWU_P18,LLWU_P19,LLWU_P20,LLWU_P21,LLWU_P22,LLWU_P23,LLWU_P24,LLWU_P25,LLWU_P26,LLWU_P27,LLWU_P28,LLWU_P29,LLWU_P30,LLWU_P31"
|
|
line.byte 0x0C "FILT3,LLWU Pin Filter 3 Register"
|
|
eventfld.byte 0x0C 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup"
|
|
bitfld.byte 0x0C 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.byte 0x0C 0.--4. " FILTSEL ,Filter pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,LLWU_P16,LLWU_P17,LLWU_P18,LLWU_P19,LLWU_P20,LLWU_P21,LLWU_P22,LLWU_P23,LLWU_P24,LLWU_P25,LLWU_P26,LLWU_P27,LLWU_P28,LLWU_P29,LLWU_P30,LLWU_P31"
|
|
line.byte 0x0D "FILT3,LLWU Pin Filter 3 Register"
|
|
eventfld.byte 0x0D 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup"
|
|
bitfld.byte 0x0D 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.byte 0x0D 0.--4. " FILTSEL ,Filter pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,LLWU_P16,LLWU_P17,LLWU_P18,LLWU_P19,LLWU_P20,LLWU_P21,LLWU_P22,LLWU_P23,LLWU_P24,LLWU_P25,LLWU_P26,LLWU_P27,LLWU_P28,LLWU_P29,LLWU_P30,LLWU_P31"
|
|
else
|
|
group.byte 0x02++0x02
|
|
line.byte 0x00 "ME,LLWU Module Enable Register"
|
|
sif cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL36*")||cpuis("MKL46*")
|
|
bitfld.byte 0x00 7. " WUME7 ,Wakeup module enable for RTC seconds" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " WUME5 ,Wakeup module enable for RTC alarm" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " WUME4 ,Wakeup module enable for TSI0" "Disabled,Enabled"
|
|
elif cpuis("MK13*")||cpuis("MK17Z128*")||cpuis("MK17Z256*")||cpuis("MK33Z*")
|
|
bitfld.byte 0x00 7. " WUME7 ,Wakeup module enable for module 7" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " WUME6 ,Wakeup module enable for module 6" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " WUME5 ,Wakeup module enable for module 5" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " WUME4 ,Wakeup module enable for module 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " WUME3 ,Wakeup module enable for module 3" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " WUME2 ,Wakeup module enable for module 2" "Disabled,Enabled"
|
|
else
|
|
bitfld.byte 0x00 7. " WUME7 ,Wakeup module enable for RTC seconds" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " WUME5 ,Wakeup module enable for RTC alarm" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " WUME1 ,Wakeup module enable for CMP0" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " WUME0 ,Wakeup module enable for LPTMR0" "Disabled,Enabled"
|
|
line.byte 0x01 "F1,LLWU Flag 1 Register"
|
|
sif cpuis("MK13*")||cpuis("MK17Z128*")||cpuis("MK17Z256*")||cpuis("MK33Z*")
|
|
eventfld.byte 0x01 7. " WUF7 ,Wakeup flag for LLWU_P7" "Disabled,Enabled"
|
|
eventfld.byte 0x01 6. " WUF6 ,Wakeup flag for LLWU_P6" "Disabled,Enabled"
|
|
eventfld.byte 0x01 5. " WUF5 ,Wakeup flag for LLWU_P5" "Disabled,Enabled"
|
|
eventfld.byte 0x01 4. " WUF4 ,Wakeup flag for LLWU_P4" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.byte 0x01 3. " WUF3 ,Wakeup flag for LLWU_P3" "Disabled,Enabled"
|
|
eventfld.byte 0x01 2. " WUF2 ,Wakeup flag for LLWU_P2" "Disabled,Enabled"
|
|
eventfld.byte 0x01 1. " WUF1 ,Wakeup flag for LLWU_P1" "Disabled,Enabled"
|
|
eventfld.byte 0x01 0. " WUF0 ,Wakeup flag for LLWU_P0" "Disabled,Enabled"
|
|
else
|
|
eventfld.byte 0x01 7. " WUF7 ,Wakeup flag for LLWU_P7" "Disabled,Enabled"
|
|
eventfld.byte 0x01 6. " WUF6 ,Wakeup flag for LLWU_P6" "Disabled,Enabled"
|
|
eventfld.byte 0x01 5. " WUF5 ,Wakeup flag for LLWU_P5" "Disabled,Enabled"
|
|
endif
|
|
line.byte 0x02 "F2,LLWU Flag 2 Register"
|
|
sif cpuis("MK13*")||cpuis("MK17Z128*")||cpuis("MK17Z256*")||cpuis("MK33Z*")
|
|
eventfld.byte 0x02 7. " WUF15 ,Wakeup flag for LLWU_P15" "Disabled,Enabled"
|
|
eventfld.byte 0x02 6. " WUF14 ,Wakeup flag for LLWU_P14" "Disabled,Enabled"
|
|
eventfld.byte 0x02 5. " WUF13 ,Wakeup flag for LLWU_P13" "Disabled,Enabled"
|
|
eventfld.byte 0x02 4. " WUF12 ,Wakeup flag for LLWU_P12" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.byte 0x02 3. " WUF11 ,Wakeup flag for LLWU_P11" "Disabled,Enabled"
|
|
eventfld.byte 0x02 2. " WUF10 ,Wakeup flag for LLWU_P10" "Disabled,Enabled"
|
|
eventfld.byte 0x02 1. " WUF9 ,Wakeup flag for LLWU_P9" "Disabled,Enabled"
|
|
eventfld.byte 0x02 0. " WUF8 ,Wakeup flag for LLWU_P8" "Disabled,Enabled"
|
|
else
|
|
eventfld.byte 0x02 7. " WUF15 ,Wakeup flag for LLWU_P15" "Disabled,Enabled"
|
|
eventfld.byte 0x02 6. " WUF14 ,Wakeup flag for LLWU_P14" "Disabled,Enabled"
|
|
eventfld.byte 0x02 2. " WUF10 ,Wakeup flag for LLWU_P10" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.byte 0x02 1. " WUF9 ,Wakeup flag for LLWU_P9" "Disabled,Enabled"
|
|
eventfld.byte 0x02 0. " WUF8 ,Wakeup flag for LLWU_P8" "Disabled,Enabled"
|
|
endif
|
|
rgroup.byte 0x07++0x00
|
|
line.byte 0x00 "F3,LLWU Flag 3 Register"
|
|
sif cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL36*")||cpuis("MKL46*")
|
|
bitfld.byte 0x00 7. " MWUF7 ,Wakeup flag for RTC seconds" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 5. " MWUF5 ,Wakeup flag for RTC alarm" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " MWUF4 ,Wakeup flag for TSI0" "Not occurred,Occurred"
|
|
elif cpuis("MK13*")||cpuis("MK17Z128*")||cpuis("MK17Z256*")||cpuis("MK33Z*")
|
|
bitfld.byte 0x00 7. " MWUF7 ,Wakeup flag for module 7" "No error,Error"
|
|
bitfld.byte 0x00 6. " MWUF6 ,Wakeup flag module 6" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 5. " MWUF5 ,Wakeup flag module 5" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " MWUF4 ,Wakeup flag module 4" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MWUF3 ,Wakeup flag for module 3" "No error,Error"
|
|
bitfld.byte 0x00 2. " MWUF6 ,Wakeup flag for module 2" "Not occurred,Occurred"
|
|
else
|
|
bitfld.byte 0x00 7. " MWUF7 ,Wakeup flag for RTC seconds" "No error,Error"
|
|
bitfld.byte 0x00 5. " MWUF5 ,Wakeup flag for RTC alarm" "Not occurred,Occurred"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " MWUF1 ,Wakeup flag for CMP0" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " MWUF0 ,Wakeup flag for LPTMR0" "Not occurred,Occurred"
|
|
width 9.
|
|
group.byte 0x07++0x01
|
|
line.byte 0x00 "FILT1,LLWU Pin Filter 1 Register"
|
|
eventfld.byte 0x00 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup"
|
|
bitfld.byte 0x00 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.byte 0x00 0.--3. " FILTSEL ,Filter pin select" ",,,,,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,,,,LLWU_P14,LLWU_P15"
|
|
line.byte 0x01 "FILT2,LLWU Pin Filter 2 Register"
|
|
eventfld.byte 0x01 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup"
|
|
bitfld.byte 0x01 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.byte 0x01 0.--3. " FILTSEL ,Filter pin select" ",,,,,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,,,,LLWU_P14,LLWU_P15"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
else
|
|
base ad:0x4007C000
|
|
width 9.
|
|
sif cpuis("MKL03*")||cpuis("MKL04*")||cpuis("MKL05*")
|
|
group.byte 0x00++0x02
|
|
line.byte 0x00 "PE1,LLWU Pin Enable 1 Register"
|
|
bitfld.byte 0x00 6.--7. " WUPE3 ,Wakeup pin enable for LLWU_P3" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x00 4.--5. " WUPE2 ,Wakeup pin enable for LLWU_P2" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x00 2.--3. " WUPE1 ,Wakeup pin enable for LLWU_P1" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x00 0.--1. " WUPE0 ,Wakeup pin enable for LLWU_P0" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
line.byte 0x01 "PE2,LLWU Pin Enable 2 Register"
|
|
bitfld.byte 0x01 6.--7. " WUPE7 ,Wakeup pin enable for LLWU_P7" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x01 4.--5. " WUPE6 ,Wakeup pin enable for LLWU_P6" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x01 2.--3. " WUPE5 ,Wakeup pin enable for LLWU_P5" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x01 0.--1. " WUPE4 ,Wakeup pin enable for LLWU_P4" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
line.byte 0x02 "ME,LLWU Module Enable Register"
|
|
bitfld.byte 0x02 7. " WUME7 ,Wakeup module enable for module 7" "Disabled,Enabled"
|
|
bitfld.byte 0x02 6. " WUME6 ,Wakeup module enable for module 6" "Disabled,Enabled"
|
|
bitfld.byte 0x02 5. " WUME5 ,Wakeup module enable for module 5" "Disabled,Enabled"
|
|
bitfld.byte 0x02 4. " WUME4 ,Wakeup module enable for module 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x02 3. " WUME3 ,Wakeup module enable for module 3" "Disabled,Enabled"
|
|
bitfld.byte 0x02 2. " WUME2 ,Wakeup module enable for module 2" "Disabled,Enabled"
|
|
bitfld.byte 0x02 1. " WUME1 ,Wakeup module enable for module 1" "Disabled,Enabled"
|
|
bitfld.byte 0x02 0. " WUME0 ,Wakeup module enable for module 1" "Disabled,Enabled"
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "F1,LLWU Flag 1 Register"
|
|
eventfld.byte 0x00 7. " WUF7 ,Wakeup flag for LLWU_P7" "Disabled,Enabled"
|
|
eventfld.byte 0x00 6. " WUF6 ,Wakeup flag for LLWU_P6" "Disabled,Enabled"
|
|
eventfld.byte 0x00 5. " WUF5 ,Wakeup flag for LLWU_P5" "Disabled,Enabled"
|
|
eventfld.byte 0x00 4. " WUF4 ,Wakeup flag for LLWU_P4" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.byte 0x00 3. " WUF3 ,Wakeup flag for LLWU_P3" "Disabled,Enabled"
|
|
eventfld.byte 0x00 2. " WUF2 ,Wakeup flag for LLWU_P2" "Disabled,Enabled"
|
|
eventfld.byte 0x00 1. " WUF1 ,Wakeup flag for LLWU_P1" "Disabled,Enabled"
|
|
eventfld.byte 0x00 0. " WUF0 ,Wakeup flag for LLWU_P0" "Disabled,Enabled"
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "F3,LLWU Flag 3 Register"
|
|
sif cpuis("MKL05*")||cpuis("MKL03*")
|
|
bitfld.byte 0x00 7. " MWUF7 ,Wakeup flag for module 7" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 6. " MWUF6 ,Wakeup flag for module 6" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 5. " MWUF5 ,Wakeup flag for module 5" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " MWUF4 ,Wakeup flag for module 4" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MWUF3 ,Wakeup flag for module 3" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " MWUF2 ,Wakeup flag for module 2" "Not occurred,Occurred"
|
|
else
|
|
bitfld.byte 0x00 7. " MWUF7 ,Wakeup flag for RTC seconds" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 5. " MWUF5 ,Wakeup flag for RTC alarm" "Not occurred,Occurred"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " MWUF1 ,Wakeup flag for module 1" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " MWUF0 ,Wakeup flag for module 0" "Not occurred,Occurred"
|
|
group.byte 0x05++0x01
|
|
line.byte 0x00 "FILT1,LLWU Pin Filter 1 Register"
|
|
eventfld.byte 0x00 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup"
|
|
bitfld.byte 0x00 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
sif cpuis("MKL03Z*")||cpuis("MKL05*")
|
|
bitfld.byte 0x00 0.--3. " FILTSEL ,Filter pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15"
|
|
else
|
|
bitfld.byte 0x00 0.--3. " FILTSEL ,Filter pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,?..."
|
|
endif
|
|
line.byte 0x01 "FILT2,LLWU Pin Filter 2 Register"
|
|
eventfld.byte 0x01 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup"
|
|
bitfld.byte 0x01 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
sif cpuis("MKL03Z*")||cpuis("MKL05*")
|
|
bitfld.byte 0x01 0.--3. " FILTSEL ,Filter pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15"
|
|
else
|
|
bitfld.byte 0x01 0.--3. " FILTSEL ,Filter pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,?..."
|
|
endif
|
|
elif cpuis("MKL28Z*")
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number"
|
|
line.long 0x04 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " PINS ,Pin number"
|
|
hexmask.long.byte 0x04 16.--23. 1. " MODULES ,Module number"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " DMAS ,DMA number"
|
|
hexmask.long.byte 0x04 0.--7. 1. " FILTERS ,Filter number"
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "PE1,LLWU Pin Enable 1 Register"
|
|
bitfld.long 0x00 30.--31. " WUPE15 ,Wakeup pin enable for LLWU_P15" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x00 28.--29. " WUPE14 ,Wakeup pin enable for LLWU_P14" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x00 26.--27. " WUPE13 ,Wakeup pin enable for LLWU_P13" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x00 24.--25. " WUPE12 ,Wakeup pin enable for LLWU_P12" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " WUPE11 ,Wakeup pin enable for LLWU_P11" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x00 20.--21. " WUPE10 ,Wakeup pin enable for LLWU_P10" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x00 18.--19. " WUPE9 ,Wakeup pin enable for LLWU_P9" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x00 16.--17. " WUPE8 ,Wakeup pin enable for LLWU_P8" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " WUPE7 ,Wakeup pin enable for LLWU_P7" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x00 12.--13. " WUPE6 ,Wakeup pin enable for LLWU_P6" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x00 10.--11. " WUPE5 ,Wakeup pin enable for LLWU_P5" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x00 8.--9. " WUPE4 ,Wakeup pin enable for LLWU_P4" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " WUPE3 ,Wakeup pin enable for LLWU_P3" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x00 4.--5. " WUPE2 ,Wakeup pin enable for LLWU_P2" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x00 2.--3. " WUPE1 ,Wakeup pin enable for LLWU_P1" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x00 0.--1. " WUPE0 ,Wakeup pin enable for LLWU_P0" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
line.long 0x04 "PE2,LLWU Pin Enable 2 Register"
|
|
bitfld.long 0x04 30.--31. " WUPE31 ,Wakeup pin enable for LLWU_P31" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x04 28.--29. " WUPE30 ,Wakeup pin enable for LLWU_P30" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x04 26.--27. " WUPE29 ,Wakeup pin enable for LLWU_P29" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x04 24.--25. " WUPE28 ,Wakeup pin enable for LLWU_P28" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
textline " "
|
|
bitfld.long 0x04 22.--23. " WUPE27 ,Wakeup pin enable for LLWU_P27" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x04 20.--21. " WUPE26 ,Wakeup pin enable for LLWU_P26" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x04 18.--19. " WUPE25 ,Wakeup pin enable for LLWU_P25" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x04 16.--17. " WUPE24 ,Wakeup pin enable for LLWU_P24" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " WUPE23 ,Wakeup pin enable for LLWU_P23" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x04 12.--13. " WUPE22 ,Wakeup pin enable for LLWU_P22" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x04 10.--11. " WUPE21 ,Wakeup pin enable for LLWU_P21" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x04 8.--9. " WUPE20 ,Wakeup pin enable for LLWU_P20" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " WUPE19 ,Wakeup pin enable for LLWU_P19" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x04 4.--5. " WUPE18 ,Wakeup pin enable for LLWU_P18" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x04 2.--3. " WUPE17 ,Wakeup pin enable for LLWU_P17" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x04 0.--1. " WUPE16 ,Wakeup pin enable for LLWU_P16" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
group.long 0x18++0x0B
|
|
line.long 0x00 "ME,LLWU Module Interrupt Enable Register"
|
|
bitfld.long 0x00 7. " WUME7 ,Wakeup module enable for module 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " WUME6 ,Wakeup module enable for module 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " WUME5 ,Wakeup module enable for module 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " WUME4 ,Wakeup module enable for module 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " WUME3 ,Wakeup module enable for module 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " WUME2 ,Wakeup module enable for module 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " WUME1 ,Wakeup module enable for module 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " WUME0 ,Wakeup module enable for module 0" "Disabled,Enabled"
|
|
line.long 0x04 "DE,LLWU Module DMA Enable Register"
|
|
bitfld.long 0x04 7. " WUDE7 ,DMA wakeup enable for module 7" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " WUDE6 ,DMA wakeup enable for module 6" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " WUDE5 ,DMA wakeup enable for module 5" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " WUDE4 ,DMA wakeup enable for module 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " WUDE3 ,DMA wakeup enable for module 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " WUDE2 ,DMA wakeup enable for module 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " WUDE1 ,DMA wakeup enable for module 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " WUDE0 ,DMA wakeup enable for module 0" "Disabled,Enabled"
|
|
line.long 0x08 "PF,LLWU Pin Flag Register"
|
|
eventfld.long 0x08 31. " WUF31 ,Wakeup flag for LLWU_P31" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 30. " WUF30 ,Wakeup flag for LLWU_P30" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 29. " WUF29 ,Wakeup flag for LLWU_P29" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 28. " WUF28 ,Wakeup flag for LLWU_P28" "No wakeup,Wakeup"
|
|
textline " "
|
|
eventfld.long 0x08 27. " WUF27 ,Wakeup flag for LLWU_P27" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 26. " WUF26 ,Wakeup flag for LLWU_P26" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 25. " WUF25 ,Wakeup flag for LLWU_P25" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 24. " WUF24 ,Wakeup flag for LLWU_P24" "No wakeup,Wakeup"
|
|
textline " "
|
|
eventfld.long 0x08 23. " WUF23 ,Wakeup flag for LLWU_P23" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 22. " WUF22 ,Wakeup flag for LLWU_P22" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 21. " WUF21 ,Wakeup flag for LLWU_P21" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 20. " WUF20 ,Wakeup flag for LLWU_P20" "No wakeup,Wakeup"
|
|
textline " "
|
|
eventfld.long 0x08 19. " WUF19 ,Wakeup flag for LLWU_P19" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 18. " WUF18 ,Wakeup flag for LLWU_P18" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 17. " WUF17 ,Wakeup flag for LLWU_P17" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 16. " WUF16 ,Wakeup flag for LLWU_P16" "No wakeup,Wakeup"
|
|
textline " "
|
|
eventfld.long 0x08 15. " WUF15 ,Wakeup flag for LLWU_P15" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 14. " WUF14 ,Wakeup flag for LLWU_P14" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 13. " WUF13 ,Wakeup flag for LLWU_P13" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 12. " WUF12 ,Wakeup flag for LLWU_P12" "No wakeup,Wakeup"
|
|
textline " "
|
|
eventfld.long 0x08 11. " WUF11 ,Wakeup flag for LLWU_P11" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 10. " WUF10 ,Wakeup flag for LLWU_P10" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 9. " WUF9 ,Wakeup flag for LLWU_P9" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 8. " WUF8 ,Wakeup flag for LLWU_P8" "No wakeup,Wakeup"
|
|
textline " "
|
|
eventfld.long 0x08 7. " WUF7 ,Wakeup flag for LLWU_P7" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 6. " WUF6 ,Wakeup flag for LLWU_P6" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 5. " WUF5 ,Wakeup flag for LLWU_P5" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 4. " WUF4 ,Wakeup flag for LLWU_P4" "No wakeup,Wakeup"
|
|
textline " "
|
|
eventfld.long 0x08 3. " WUF3 ,Wakeup flag for LLWU_P3" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 2. " WUF2 ,Wakeup flag for LLWU_P2" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 1. " WUF1 ,Wakeup flag for LLWU_P1" "No wakeup,Wakeup"
|
|
eventfld.long 0x08 0. " WUF0 ,Wakeup flag for LLWU_P0" "No wakeup,Wakeup"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "MF,LLWU Module Interrupt Flag Register"
|
|
bitfld.long 0x00 7. " MWUF7 ,Wakeup flag for module 7" "No error,Error"
|
|
bitfld.long 0x00 6. " MWUF6 ,Wakeup flag for module 6" "No error,Error"
|
|
bitfld.long 0x00 5. " MWUF5 ,Wakeup flag for module 5" "No error,Error"
|
|
bitfld.long 0x00 4. " MWUF4 ,Wakeup flag for module 4" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MWUF3 ,Wakeup flag for module 3" "No error,Error"
|
|
bitfld.long 0x00 2. " MWUF2 ,Wakeup flag for module 2" "No error,Error"
|
|
bitfld.long 0x00 1. " MWUF1 ,Wakeup flag for module 1" "No error,Error"
|
|
bitfld.long 0x00 0. " MWUF0 ,Wakeup flag for module 0" "No error,Error"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "FILT,LLWU Pin Filter Register"
|
|
eventfld.long 0x00 31. " FILTF4 ,Filter 4 flag" "No wakeup,Wakeup"
|
|
bitfld.long 0x00 29.--30. " FILTE4 ,Filter 4 enable" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x00 24.--28. " FILTSEL4 ,Filter 4 pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,LLWU_P16,LLWU_P17,LLWU_P18,LLWU_P19,LLWU_P20,LLWU_P21,LLWU_P22,LLWU_P23,LLWU_P24,LLWU_P25,LLWU_P26,LLWU_P27,LLWU_P28,LLWU_P29,LLWU_P30,LLWU_P31"
|
|
textline " "
|
|
eventfld.long 0x00 23. " FILTF3 ,Filter 3 flag" "No wakeup,Wakeup"
|
|
bitfld.long 0x00 21.--22. " FILTE3 ,Filter 3 enable" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x00 16.--20. " FILTSEL3 ,Filter 3 pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,LLWU_P16,LLWU_P17,LLWU_P18,LLWU_P19,LLWU_P20,LLWU_P21,LLWU_P22,LLWU_P23,LLWU_P24,LLWU_P25,LLWU_P26,LLWU_P27,LLWU_P28,LLWU_P29,LLWU_P30,LLWU_P31"
|
|
textline " "
|
|
eventfld.long 0x00 15. " FILTF2 ,Filter 2 flag" "No wakeup,Wakeup"
|
|
bitfld.long 0x00 13.--14. " FILTE2 ,Filter 2 enable" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x00 8.--12. " FILTSEL2 ,Filter 2 pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,LLWU_P16,LLWU_P17,LLWU_P18,LLWU_P19,LLWU_P20,LLWU_P21,LLWU_P22,LLWU_P23,LLWU_P24,LLWU_P25,LLWU_P26,LLWU_P27,LLWU_P28,LLWU_P29,LLWU_P30,LLWU_P31"
|
|
textline " "
|
|
eventfld.long 0x00 7. " FILTF1 ,Filter 1 flag" "No wakeup,Wakeup"
|
|
bitfld.long 0x00 5.--6. " FILTE1 ,Filter 1 enable" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.long 0x00 0.--4. " FILTSEL1 ,Filter 1 pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,LLWU_P16,LLWU_P17,LLWU_P18,LLWU_P19,LLWU_P20,LLWU_P21,LLWU_P22,LLWU_P23,LLWU_P24,LLWU_P25,LLWU_P26,LLWU_P27,LLWU_P28,LLWU_P29,LLWU_P30,LLWU_P31"
|
|
else
|
|
sif cpuis("MKL13Z*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL17Z256*")||cpuis("MKL33Z*")||cpuis("MKL82Z*")
|
|
group.byte 0x00++0x02
|
|
line.byte 0x00 "PE1,LLWU Pin Enable 1 Register"
|
|
bitfld.byte 0x00 6.--7. " WUPE3 ,Wakeup pin enable for LLWU_P3" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x00 4.--5. " WUPE2 ,Wakeup pin enable for LLWU_P2" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x00 2.--3. " WUPE1 ,Wakeup pin enable for LLWU_P1" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x00 0.--1. " WUPE0 ,Wakeup pin enable for LLWU_P0" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
endif
|
|
group.byte 0x01++0x02
|
|
line.byte 0x00 "PE2,LLWU Pin Enable 2 Register"
|
|
bitfld.byte 0x00 6.--7. " WUPE7 ,Wakeup pin enable for LLWU_P7" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x00 4.--5. " WUPE6 ,Wakeup pin enable for LLWU_P6" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x00 2.--3. " WUPE5 ,Wakeup pin enable for LLWU_P5" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
textline " "
|
|
sif cpuis("MKL13Z*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL17Z256*")||cpuis("MKL33Z*")||cpuis("MKL82Z*")
|
|
bitfld.byte 0x00 0.--1. " WUPE4 ,Wakeup pin enable for LLWU_P4" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
endif
|
|
line.byte 0x01 "PE3,LLWU Pin Enable 3 Register"
|
|
sif cpuis("MKL13Z*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL17Z256*")||cpuis("MKL33Z*")||cpuis("MKL82Z*")
|
|
bitfld.byte 0x01 6.--7. " WUPE11 ,Wakeup pin enable for LLWU_P11" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x01 4.--5. " WUPE10 ,Wakeup pin enable for LLWU_P10" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x01 2.--3. " WUPE9 ,Wakeup pin enable for LLWU_P9" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x01 0.--1. " WUPE8 ,Wakeup pin enable for LLWU_P8" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
line.byte 0x02 "PE4,LLWU Pin Enable 4 Register"
|
|
bitfld.byte 0x02 6.--7. " WUPE15 ,Wakeup pin enable for LLWU_P15" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x02 4.--5. " WUPE14 ,Wakeup pin enable for LLWU_P14" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
textline " "
|
|
sif cpuis("MKL13Z*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL17Z256*")||cpuis("MKL33Z*")||cpuis("MKL82Z*")
|
|
bitfld.byte 0x02 2.--3. " WUPE13 ,Wakeup pin enable for LLWU_P13" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x02 0.--1. " WUPE12 ,Wakeup pin enable for LLWU_P12" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
endif
|
|
sif cpuis("MKL82Z*")
|
|
group.byte 0x04++0x0D
|
|
line.byte 0x00 "PE5,LLWU Pin Enable 5 Register"
|
|
bitfld.byte 0x00 6.--7. " WUPE19 ,Wakeup pin enable for LLWU_P19" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x00 4.--5. " WUPE18 ,Wakeup pin enable for LLWU_P18" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x00 2.--3. " WUPE17 ,Wakeup pin enable for LLWU_P17" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x00 0.--1. " WUPE16 ,Wakeup pin enable for LLWU_P16" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
line.byte 0x01 "PE6,LLWU Pin Enable 6 Register"
|
|
bitfld.byte 0x01 6.--7. " WUPE23 ,Wakeup pin enable for LLWU_P23" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x01 4.--5. " WUPE22 ,Wakeup pin enable for LLWU_P22" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x01 2.--3. " WUPE21 ,Wakeup pin enable for LLWU_P21" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x01 0.--1. " WUPE20 ,Wakeup pin enable for LLWU_P20" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
line.byte 0x02 "PE7,LLWU Pin Enable 7 Register"
|
|
bitfld.byte 0x02 6.--7. " WUPE27 ,Wakeup pin enable for LLWU_P27" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x02 4.--5. " WUPE26 ,Wakeup pin enable for LLWU_P26" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x02 2.--3. " WUPE25 ,Wakeup pin enable for LLWU_P25" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x02 0.--1. " WUPE24 ,Wakeup pin enable for LLWU_P24" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
line.byte 0x03 "PE8,LLWU Pin Enable 8 Register"
|
|
bitfld.byte 0x03 6.--7. " WUPE31 ,Wakeup pin enable for LLWU_P31" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x03 4.--5. " WUPE30 ,Wakeup pin enable for LLWU_P30" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x03 2.--3. " WUPE29 ,Wakeup pin enable for LLWU_P29" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
bitfld.byte 0x03 0.--1. " WUPE28 ,Wakeup pin enable for LLWU_P28" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change"
|
|
line.byte 0x04 "ME,LLWU Module Enable Register"
|
|
bitfld.byte 0x04 7. " WUME7 ,Wakeup module enable for module 7" "Disabled,Enabled"
|
|
bitfld.byte 0x04 6. " WUME6 ,Wakeup module enable for module 6" "Disabled,Enabled"
|
|
bitfld.byte 0x04 5. " WUME5 ,Wakeup module enable for module 5" "Disabled,Enabled"
|
|
bitfld.byte 0x04 4. " WUME4 ,Wakeup module enable for module 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x04 3. " WUME3 ,Wakeup module enable for module 3" "Disabled,Enabled"
|
|
bitfld.byte 0x04 2. " WUME2 ,Wakeup module enable for module 2" "Disabled,Enabled"
|
|
bitfld.byte 0x04 1. " WUME1 ,Wakeup module enable for module 1" "Disabled,Enabled"
|
|
bitfld.byte 0x04 0. " WUME0 ,Wakeup module enable for module 0" "Disabled,Enabled"
|
|
line.byte 0x05 "PF1,LLWU Pin Flag 1 Register"
|
|
eventfld.byte 0x05 7. " WUF7 ,Wakeup flag for LLWU_P7" "Disabled,Enabled"
|
|
eventfld.byte 0x05 6. " WUF6 ,Wakeup flag for LLWU_P6" "Disabled,Enabled"
|
|
eventfld.byte 0x05 5. " WUF5 ,Wakeup flag for LLWU_P5" "Disabled,Enabled"
|
|
eventfld.byte 0x05 4. " WUF4 ,Wakeup flag for LLWU_P5" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.byte 0x05 3. " WUF3 ,Wakeup flag for LLWU_P3" "Disabled,Enabled"
|
|
eventfld.byte 0x05 2. " WUF2 ,Wakeup flag for LLWU_P2" "Disabled,Enabled"
|
|
eventfld.byte 0x05 1. " WUF1 ,Wakeup flag for LLWU_P1" "Disabled,Enabled"
|
|
eventfld.byte 0x05 0. " WUF0 ,Wakeup flag for LLWU_P0" "Disabled,Enabled"
|
|
line.byte 0x06 "PF2,LLWU Pin Flag 2 Register"
|
|
eventfld.byte 0x06 7. " WUF15 ,Wakeup flag for LLWU_P15" "Disabled,Enabled"
|
|
eventfld.byte 0x06 6. " WUF14 ,Wakeup flag for LLWU_P14" "Disabled,Enabled"
|
|
eventfld.byte 0x06 5. " WUF13 ,Wakeup flag for LLWU_P13" "Disabled,Enabled"
|
|
eventfld.byte 0x06 4. " WUF12 ,Wakeup flag for LLWU_P12" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.byte 0x06 3. " WUF11 ,Wakeup flag for LLWU_P11" "Disabled,Enabled"
|
|
eventfld.byte 0x06 2. " WUF10 ,Wakeup flag for LLWU_P10" "Disabled,Enabled"
|
|
eventfld.byte 0x06 1. " WUF9 ,Wakeup flag for LLWU_P9" "Disabled,Enabled"
|
|
eventfld.byte 0x06 0. " WUF8 ,Wakeup flag for LLWU_P8" "Disabled,Enabled"
|
|
line.byte 0x07 "PF3,LLWU Pin Flag 3 Register"
|
|
eventfld.byte 0x07 7. " WUF23 ,Wakeup flag for LLWU_P23" "Disabled,Enabled"
|
|
eventfld.byte 0x07 6. " WUF22 ,Wakeup flag for LLWU_P22" "Disabled,Enabled"
|
|
eventfld.byte 0x07 5. " WUF21 ,Wakeup flag for LLWU_P21" "Disabled,Enabled"
|
|
eventfld.byte 0x07 4. " WUF20 ,Wakeup flag for LLWU_P20" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.byte 0x07 3. " WUF19 ,Wakeup flag for LLWU_P19" "Disabled,Enabled"
|
|
eventfld.byte 0x07 2. " WUF18 ,Wakeup flag for LLWU_P18" "Disabled,Enabled"
|
|
eventfld.byte 0x07 1. " WUF17 ,Wakeup flag for LLWU_P17" "Disabled,Enabled"
|
|
eventfld.byte 0x07 0. " WUF16 ,Wakeup flag for LLWU_P16" "Disabled,Enabled"
|
|
line.byte 0x08 "PF4,LLWU Pin Flag 4 Register"
|
|
eventfld.byte 0x08 7. " WUF31 ,Wakeup flag for LLWU_P31" "Disabled,Enabled"
|
|
eventfld.byte 0x08 6. " WUF30 ,Wakeup flag for LLWU_P30" "Disabled,Enabled"
|
|
eventfld.byte 0x08 5. " WUF29 ,Wakeup flag for LLWU_P29" "Disabled,Enabled"
|
|
eventfld.byte 0x08 4. " WUF28 ,Wakeup flag for LLWU_P28" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.byte 0x08 3. " WUF27 ,Wakeup flag for LLWU_P27" "Disabled,Enabled"
|
|
eventfld.byte 0x08 2. " WUF26 ,Wakeup flag for LLWU_P26" "Disabled,Enabled"
|
|
eventfld.byte 0x08 1. " WUF25 ,Wakeup flag for LLWU_P25" "Disabled,Enabled"
|
|
eventfld.byte 0x08 0. " WUF24 ,Wakeup flag for LLWU_P24" "Disabled,Enabled"
|
|
line.byte 0x09 "MF5,LLWU Module Flag 5 Register"
|
|
bitfld.byte 0x09 7. " MWUF7 ,Wakeup flag for module 7" "No error,Error"
|
|
bitfld.byte 0x09 6. " MWUF6 ,Wakeup flag for module 6" "No error,Error"
|
|
bitfld.byte 0x09 5. " MWUF5 ,Wakeup flag for module 5" "No error,Error"
|
|
bitfld.byte 0x09 4. " MWUF4 ,Wakeup flag for module 4" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x09 3. " MWUF3 ,Wakeup flag for module 3" "No error,Error"
|
|
bitfld.byte 0x09 2. " MWUF2 ,Wakeup flag for module 2" "No error,Error"
|
|
bitfld.byte 0x09 1. " MWUF1 ,Wakeup flag for module 1" "No error,Error"
|
|
bitfld.byte 0x09 0. " MWUF0 ,Wakeup flag for module 0" "No error,Error"
|
|
line.byte 0x0A "FILT1,LLWU Pin Filter 1 Register"
|
|
eventfld.byte 0x0A 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup"
|
|
bitfld.byte 0x0A 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.byte 0x0A 0.--4. " FILTSEL ,Filter pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,LLWU_P16,LLWU_P17,LLWU_P18,LLWU_P19,LLWU_P20,LLWU_P21,LLWU_P22,LLWU_P23,LLWU_P24,LLWU_P25,LLWU_P26,LLWU_P27,LLWU_P28,LLWU_P29,LLWU_P30,LLWU_P31"
|
|
line.byte 0x0B "FILT2,LLWU Pin Filter 2 Register"
|
|
eventfld.byte 0x0B 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup"
|
|
bitfld.byte 0x0B 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.byte 0x0B 0.--4. " FILTSEL ,Filter pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,LLWU_P16,LLWU_P17,LLWU_P18,LLWU_P19,LLWU_P20,LLWU_P21,LLWU_P22,LLWU_P23,LLWU_P24,LLWU_P25,LLWU_P26,LLWU_P27,LLWU_P28,LLWU_P29,LLWU_P30,LLWU_P31"
|
|
line.byte 0x0C "FILT3,LLWU Pin Filter 3 Register"
|
|
eventfld.byte 0x0C 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup"
|
|
bitfld.byte 0x0C 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.byte 0x0C 0.--4. " FILTSEL ,Filter pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,LLWU_P16,LLWU_P17,LLWU_P18,LLWU_P19,LLWU_P20,LLWU_P21,LLWU_P22,LLWU_P23,LLWU_P24,LLWU_P25,LLWU_P26,LLWU_P27,LLWU_P28,LLWU_P29,LLWU_P30,LLWU_P31"
|
|
line.byte 0x0D "FILT3,LLWU Pin Filter 3 Register"
|
|
eventfld.byte 0x0D 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup"
|
|
bitfld.byte 0x0D 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.byte 0x0D 0.--4. " FILTSEL ,Filter pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,LLWU_P16,LLWU_P17,LLWU_P18,LLWU_P19,LLWU_P20,LLWU_P21,LLWU_P22,LLWU_P23,LLWU_P24,LLWU_P25,LLWU_P26,LLWU_P27,LLWU_P28,LLWU_P29,LLWU_P30,LLWU_P31"
|
|
else
|
|
group.byte 0x02++0x02
|
|
line.byte 0x00 "ME,LLWU Module Enable Register"
|
|
sif cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL36*")||cpuis("MKL46*")
|
|
bitfld.byte 0x00 7. " WUME7 ,Wakeup module enable for RTC seconds" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " WUME5 ,Wakeup module enable for RTC alarm" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " WUME4 ,Wakeup module enable for TSI0" "Disabled,Enabled"
|
|
elif cpuis("MK13*")||cpuis("MK17Z128*")||cpuis("MK17Z256*")||cpuis("MK33Z*")
|
|
bitfld.byte 0x00 7. " WUME7 ,Wakeup module enable for module 7" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " WUME6 ,Wakeup module enable for module 6" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " WUME5 ,Wakeup module enable for module 5" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " WUME4 ,Wakeup module enable for module 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " WUME3 ,Wakeup module enable for module 3" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " WUME2 ,Wakeup module enable for module 2" "Disabled,Enabled"
|
|
else
|
|
bitfld.byte 0x00 7. " WUME7 ,Wakeup module enable for RTC seconds" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " WUME5 ,Wakeup module enable for RTC alarm" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " WUME1 ,Wakeup module enable for CMP0" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " WUME0 ,Wakeup module enable for LPTMR0" "Disabled,Enabled"
|
|
line.byte 0x01 "F1,LLWU Flag 1 Register"
|
|
sif cpuis("MK13*")||cpuis("MK17Z128*")||cpuis("MK17Z256*")||cpuis("MK33Z*")
|
|
eventfld.byte 0x01 7. " WUF7 ,Wakeup flag for LLWU_P7" "Disabled,Enabled"
|
|
eventfld.byte 0x01 6. " WUF6 ,Wakeup flag for LLWU_P6" "Disabled,Enabled"
|
|
eventfld.byte 0x01 5. " WUF5 ,Wakeup flag for LLWU_P5" "Disabled,Enabled"
|
|
eventfld.byte 0x01 4. " WUF4 ,Wakeup flag for LLWU_P4" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.byte 0x01 3. " WUF3 ,Wakeup flag for LLWU_P3" "Disabled,Enabled"
|
|
eventfld.byte 0x01 2. " WUF2 ,Wakeup flag for LLWU_P2" "Disabled,Enabled"
|
|
eventfld.byte 0x01 1. " WUF1 ,Wakeup flag for LLWU_P1" "Disabled,Enabled"
|
|
eventfld.byte 0x01 0. " WUF0 ,Wakeup flag for LLWU_P0" "Disabled,Enabled"
|
|
else
|
|
eventfld.byte 0x01 7. " WUF7 ,Wakeup flag for LLWU_P7" "Disabled,Enabled"
|
|
eventfld.byte 0x01 6. " WUF6 ,Wakeup flag for LLWU_P6" "Disabled,Enabled"
|
|
eventfld.byte 0x01 5. " WUF5 ,Wakeup flag for LLWU_P5" "Disabled,Enabled"
|
|
endif
|
|
line.byte 0x02 "F2,LLWU Flag 2 Register"
|
|
sif cpuis("MK13*")||cpuis("MK17Z128*")||cpuis("MK17Z256*")||cpuis("MK33Z*")
|
|
eventfld.byte 0x02 7. " WUF15 ,Wakeup flag for LLWU_P15" "Disabled,Enabled"
|
|
eventfld.byte 0x02 6. " WUF14 ,Wakeup flag for LLWU_P14" "Disabled,Enabled"
|
|
eventfld.byte 0x02 5. " WUF13 ,Wakeup flag for LLWU_P13" "Disabled,Enabled"
|
|
eventfld.byte 0x02 4. " WUF12 ,Wakeup flag for LLWU_P12" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.byte 0x02 3. " WUF11 ,Wakeup flag for LLWU_P11" "Disabled,Enabled"
|
|
eventfld.byte 0x02 2. " WUF10 ,Wakeup flag for LLWU_P10" "Disabled,Enabled"
|
|
eventfld.byte 0x02 1. " WUF9 ,Wakeup flag for LLWU_P9" "Disabled,Enabled"
|
|
eventfld.byte 0x02 0. " WUF8 ,Wakeup flag for LLWU_P8" "Disabled,Enabled"
|
|
else
|
|
eventfld.byte 0x02 7. " WUF15 ,Wakeup flag for LLWU_P15" "Disabled,Enabled"
|
|
eventfld.byte 0x02 6. " WUF14 ,Wakeup flag for LLWU_P14" "Disabled,Enabled"
|
|
eventfld.byte 0x02 2. " WUF10 ,Wakeup flag for LLWU_P10" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.byte 0x02 1. " WUF9 ,Wakeup flag for LLWU_P9" "Disabled,Enabled"
|
|
eventfld.byte 0x02 0. " WUF8 ,Wakeup flag for LLWU_P8" "Disabled,Enabled"
|
|
endif
|
|
rgroup.byte 0x07++0x00
|
|
line.byte 0x00 "F3,LLWU Flag 3 Register"
|
|
sif cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL36*")||cpuis("MKL46*")
|
|
bitfld.byte 0x00 7. " MWUF7 ,Wakeup flag for RTC seconds" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 5. " MWUF5 ,Wakeup flag for RTC alarm" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " MWUF4 ,Wakeup flag for TSI0" "Not occurred,Occurred"
|
|
elif cpuis("MK13*")||cpuis("MK17Z128*")||cpuis("MK17Z256*")||cpuis("MK33Z*")
|
|
bitfld.byte 0x00 7. " MWUF7 ,Wakeup flag for module 7" "No error,Error"
|
|
bitfld.byte 0x00 6. " MWUF6 ,Wakeup flag module 6" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 5. " MWUF5 ,Wakeup flag module 5" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " MWUF4 ,Wakeup flag module 4" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MWUF3 ,Wakeup flag for module 3" "No error,Error"
|
|
bitfld.byte 0x00 2. " MWUF6 ,Wakeup flag for module 2" "Not occurred,Occurred"
|
|
else
|
|
bitfld.byte 0x00 7. " MWUF7 ,Wakeup flag for RTC seconds" "No error,Error"
|
|
bitfld.byte 0x00 5. " MWUF5 ,Wakeup flag for RTC alarm" "Not occurred,Occurred"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " MWUF1 ,Wakeup flag for CMP0" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " MWUF0 ,Wakeup flag for LPTMR0" "Not occurred,Occurred"
|
|
width 9.
|
|
group.byte 0x07++0x01
|
|
line.byte 0x00 "FILT1,LLWU Pin Filter 1 Register"
|
|
eventfld.byte 0x00 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup"
|
|
bitfld.byte 0x00 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.byte 0x00 0.--3. " FILTSEL ,Filter pin select" ",,,,,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,,,,LLWU_P14,LLWU_P15"
|
|
line.byte 0x01 "FILT2,LLWU Pin Filter 2 Register"
|
|
eventfld.byte 0x01 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup"
|
|
bitfld.byte 0x01 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter pos. Edge,Filter neg. Edge,Filter any edge"
|
|
bitfld.byte 0x01 0.--3. " FILTSEL ,Filter pin select" ",,,,,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,,,,LLWU_P14,LLWU_P15"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "RCM (Reset Control Module)"
|
|
base ad:0x4007F000
|
|
width 11.
|
|
sif cpuis("MKL28*")
|
|
rgroup.long 0x00++0x0B
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number"
|
|
hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number"
|
|
line.long 0x04 "PARAM,Parameter Register"
|
|
bitfld.long 0x04 16. " ECORE1 ,Existence of SRS[CORE1] status indication feature" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " ETAMPER ,Existence of SRS[TAMPER] status indication feature" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " ESACKERR ,Existence of SRS[SACKERR] status indication feature" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " EMDM_AP ,Existence of SRS[MDM_AP] status indication feature" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " ESW ,Existence of SRS[SW] status indication feature" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " ELOCKUP ,Existence of SRS[LOCKUP] status indication feature" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " EJTAG ,Existence of SRS[JTAG] status indication feature" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " EPOR ,Existence of SRS[POR] status indication feature" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " EPIN ,Existence of SRS[PIN] status indication feature" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " EWDOG ,Existence of SRS[WDOG] status indication feature" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " ELOL ,Existence of SRS[LOL] status indication feature" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " ELOC ,Existence of SRS[LOC] status indication feature" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ELVD ,Existence of SRS[LVD] status indication feature" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " EWAKEUP ,Existence of SRS[WAKEUP] status indication feature" "Disabled,Enabled"
|
|
line.long 0x08 "SRS,System Reset Status Register"
|
|
bitfld.long 0x08 13. " SACKERR ,Stop acknowledge error" "Not caused,Caused"
|
|
bitfld.long 0x08 11. " MDM_AP ,MDM-AP system reset request" "Not caused,Caused"
|
|
bitfld.long 0x08 10. " SW ,Software" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x08 9. " LOCKUP ,Core lockup" "Not caused,Caused"
|
|
bitfld.long 0x08 7. " POR ,Power-On reset" "Not caused,Caused"
|
|
bitfld.long 0x08 6. " PIN ,External reset pin" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x08 5. " WDOG ,Watchdog" "Not caused,Caused"
|
|
bitfld.long 0x08 3. " LOL ,Loss-of-Lock reset" "Not caused,Caused"
|
|
bitfld.long 0x08 2. " LOC ,Loss-of-Clock reset" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x08 1. " LVD ,Low-Voltage detect reset or High-Voltage detect reset" "Not caused,Caused"
|
|
bitfld.long 0x08 0. " WAKEUP ,VLLS wakeup reset" "Not caused,Caused"
|
|
group.long 0x0C++0x13
|
|
line.long 0x00 "RPC,Reset Pin Control Register"
|
|
bitfld.long 0x00 8.--12. " RSTFLTSEL ,Reset pin filter bus clock select" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 2. " RSTFLTSS ,Reset pin filter select in stop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " RSTFLTSRW ,Reset pin filter select in run and wait modes" "All disabled,Bus clock filter,LPO clock filter,?..."
|
|
line.long 0x04 "MR,Mode Register"
|
|
bitfld.long 0x04 1.--2. " BOOTROM[0] ,Boot ROM configuration. Indicates the boot source" "Flash,BOOTCFG0,FOPT[7],BOOTCFG0 and FOPT[7]"
|
|
line.long 0x08 "FM,Force Mode Register"
|
|
bitfld.long 0x08 1.--2. " FORCEROM ,Force ROM boot" "No effect,Force with RCM_MR[1] set,Force with RCM_MR[2] set,Force with RCM_MR[2:1] set"
|
|
line.long 0x0C "SSRS,Sticky System Reset Status Register"
|
|
eventfld.long 0x0C 13. " SSACKERR ,Sticky stop mode acknowledge error reset" "Not caused,Caused"
|
|
eventfld.long 0x0C 11. " SMDM_AP ,Sticky MDM-AP system reset request" "Not caused,Caused"
|
|
eventfld.long 0x0C 10. " SSW ,Sticky software" "Not caused,Caused"
|
|
textline " "
|
|
eventfld.long 0x0C 9. " SLOCKUP ,Sticky core lockup" "Not caused,Caused"
|
|
eventfld.long 0x0C 7. " SPOR ,Sticky power-on reset" "Not caused,Caused"
|
|
eventfld.long 0x0C 6. " SPIN ,Sticky external reset pin" "Not caused,Caused"
|
|
textline " "
|
|
eventfld.long 0x0C 5. " SWDOG ,Sticky watchdog" "Not caused,Caused"
|
|
eventfld.long 0x0C 3. " SLOL ,Sticky Loss-of-Lock reset" "Not caused,Caused"
|
|
eventfld.long 0x0C 2. " SLOC ,Sticky Loss-of-Clock reset" "Not caused,Caused"
|
|
textline " "
|
|
eventfld.long 0x0C 1. " SLVD ,Sticky low-voltage detect reset" "Not caused,Caused"
|
|
eventfld.long 0x0C 0. " SWAKEUP ,Sticky low leakage wakeup reset" "Not caused,Caused"
|
|
line.long 0x10 "SRIE,System Reset Interrupt Enable Register"
|
|
eventfld.long 0x10 13. " SACKERR ,Stop acknowledge error interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x10 11. " MDM_AP ,MDM-AP system reset request" "Disabled,Enabled"
|
|
eventfld.long 0x10 10. " SW ,Software interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 9. " LOCKUP ,Core lockup interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x10 7. " GIE ,Global interrupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x10 6. " PIN ,External reset pin interrupt" "Not caused,Caused"
|
|
textline " "
|
|
eventfld.long 0x10 5. " WDOG ,Watchdog interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x10 3. " LOL ,Loss-of-Lock interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x10 2. " LOC ,Loss-of-Clock interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " DELAY ,Reset delay time" "10 LPO cycles,34 LPO cycles,130 LPO cycles,514 LPO cycles"
|
|
width 7.
|
|
else
|
|
rgroup.byte 0x00++0x01
|
|
line.byte 0x00 "SRS0,System Reset Status Register 0"
|
|
sif cpuis("MK14LN*")||cpuis("MK15LN*")||cpuis("MKL14*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL34*")||cpuis("MKL36*")||cpuis("MKL46*")||cpuis("MKL82*")
|
|
bitfld.byte 0x00 7. " POR ,Power-on reset" "Not caused,Caused"
|
|
bitfld.byte 0x00 6. " PIN ,External reset pin" "Not caused,Caused"
|
|
bitfld.byte 0x00 5. " WDOG ,Watchdog" "Not caused,Caused"
|
|
bitfld.byte 0x00 3. " LOL ,Loss-of-lock reset" "Not caused,Caused"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x00 7. " POR ,Power-on reset" "Not caused,Caused"
|
|
bitfld.byte 0x00 6. " PIN ,External reset pin" "Not caused,Caused"
|
|
bitfld.byte 0x00 5. " WDOG ,Watchdog" "Not caused,Caused"
|
|
textline " "
|
|
endif
|
|
sif cpuis("MKL03*")||cpuis("MKL13*")||cpuis("MKL17*")||cpuis("MKL27*")||cpuis("MKL33*")||cpuis("MKL43*")
|
|
bitfld.byte 0x00 1. " LVD ,Low-voltage detect reset" "Not caused,Caused"
|
|
bitfld.byte 0x00 0. " WAKEUP ,Low-leakage wakeup reset" "Not caused,Caused"
|
|
else
|
|
bitfld.byte 0x00 2. " LOC ,Loss-of-clock reset" "Not caused,Caused"
|
|
bitfld.byte 0x00 1. " LVD ,Low-voltage detect reset" "Not caused,Caused"
|
|
bitfld.byte 0x00 0. " WAKEUP ,Low-leakage wakeup reset" "Not caused,Caused"
|
|
endif
|
|
line.byte 0x01 "SRS1,System Reset Status Register 1"
|
|
bitfld.byte 0x01 5. " SACKERR ,Stop mode acknowledge error reset" "Not caused,Caused"
|
|
bitfld.byte 0x01 3. " MDM_AP ,MDM-AP system reset request" "Not caused,Caused"
|
|
bitfld.byte 0x01 2. " SW ,Software" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " LOCKUP ,Core lockup" "Not caused,Caused"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "RPFC,Reset Pin Filter Control Register"
|
|
bitfld.byte 0x00 2. " RSTFLTSS ,Reset pin filter select in stop mode" "All disabled,LPO clock filter"
|
|
bitfld.byte 0x00 0.--1. " RSTFLTSRW ,Reset pin filter select in run and wait modes" "All disabled,Bus clock filter,LPO clock filter,?..."
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "RPFW,Reset Pin Filter Width Register"
|
|
bitfld.byte 0x00 0.--4. " RSTFLTSEL ,Selects the reset pin bus clock filter width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
sif cpuis("MKL03*")||cpuis("MKL13*")||cpuis("MKL17*")||cpuis("MKL27*")||cpuis("MKL33*")||cpuis("MKL43*")||cpuis("MKL82*")
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "FM,Force Mode Register"
|
|
bitfld.byte 0x00 1.--2. " FORCEROM ,Force ROM boot" "No effect,Force with RCM_MR[1] set,Force with RCM_MR[2] set,Force with RCM_MR[2:1] set"
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "MR,Mode Register"
|
|
bitfld.byte 0x00 1.--2. " BOOTROM[0] ,Boot ROM configuration. Indicates the boot source" "Flash,BOOTCFG0,FOPT[7],BOOTCFG0 and FOPT[7]"
|
|
group.byte 0x08++0x01
|
|
line.byte 0x00 "SSRS0,Sticky System Reset Status Register"
|
|
eventfld.byte 0x00 7. " SPOR ,Sticky power-on reset" "Not caused,Caused"
|
|
eventfld.byte 0x00 6. " SPIN ,Sticky external reset pin" "Not caused,Caused"
|
|
eventfld.byte 0x00 5. " SWDOG ,Sticky watchdog" "Not caused,Caused"
|
|
textline " "
|
|
sif cpuis("MKL82*")
|
|
eventfld.byte 0x00 3. " SLOL ,Sticky Loss-of-Lock reset" "Not caused,Caused"
|
|
eventfld.byte 0x00 2. " SLOC ,Sticky Loss-of-Clock reset" "Not caused,Caused"
|
|
textline " "
|
|
endif
|
|
eventfld.byte 0x00 1. " SLVD ,Sticky low-voltage detect reset" "Not caused,Caused"
|
|
eventfld.byte 0x00 0. " SWAKEUP ,Sticky low leakage wakeup reset" "Not caused,Caused"
|
|
line.byte 0x01 "SSRS1,System Reset Status Register 1"
|
|
eventfld.byte 0x01 5. " SSACKERR ,Sticky stop mode acknowledge error reset" "Not caused,Caused"
|
|
eventfld.byte 0x01 3. " SMDM_AP ,Sticky MDM-AP system reset request" "Not caused,Caused"
|
|
eventfld.byte 0x01 2. " SSW ,Sticky software" "Not caused,Caused"
|
|
textline " "
|
|
eventfld.byte 0x01 1. " SLOCKUP ,Sticky core lockup" "Not caused,Caused"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "MCM (Miscellaneous Control Module)"
|
|
base ad:0xF0003000
|
|
width 7.
|
|
rgroup.word 0x08++0x03
|
|
line.word 0x00 "PLASC,Crossbar Switch (AXBS) Slave Configuration"
|
|
bitfld.word 0x00 7. " ASC[7] ,Connection to the crossbar switch's slave input port 7" "Not connected,Connected"
|
|
bitfld.word 0x00 6. " [6] ,Connection to the crossbar switch's slave input port 6" "Not connected,Connected"
|
|
bitfld.word 0x00 5. " [5] ,Connection to the crossbar switch's slave input port 5" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.word 0x00 4. " [4] ,Connection to the crossbar switch's slave input port 4" "Not connected,Connected"
|
|
bitfld.word 0x00 3. " [3] ,Connection to the crossbar switch's slave input port 3" "Not connected,Connected"
|
|
bitfld.word 0x00 2. " [2] ,Connection to the crossbar switch's slave input port 2" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.word 0x00 1. " [1] ,Connection to the crossbar switch's slave input port 1" "Not connected,Connected"
|
|
bitfld.word 0x00 0. " [0] ,Connection to the crossbar switch's slave input port 0" "Not connected,Connected"
|
|
line.word 0x02 "PLAMC,Crossbar Switch (AXBS) Master Configuration"
|
|
bitfld.word 0x02 7. " AMC[7] ,Connection to the AXBS master input port 7" "Not connected,Connected"
|
|
bitfld.word 0x02 6. " [6] ,Connection to the AXBS master input port 6" "Not connected,Connected"
|
|
bitfld.word 0x02 5. " [5] ,Connection to the AXBS master input port 5" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.word 0x02 4. " [4] ,Connection to the AXBS master input port 4" "Not connected,Connected"
|
|
bitfld.word 0x02 3. " [3] ,Connection to the AXBS master input port 3" "Not connected,Connected"
|
|
bitfld.word 0x02 2. " [2] ,Connection to the AXBS master input port 2" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.word 0x02 1. " [1] ,Connection to the AXBS master input port 1" "Not connected,Connected"
|
|
bitfld.word 0x02 0. " [0] ,Connection to the AXBS master input port 0" "Not connected,Connected"
|
|
newline
|
|
sif (cpu()=="VF7XX-CM4"||cpu()=="VF6XX-CM4"||cpu()=="VF7XX-CA5"||cpu()=="VF6XX-CA5"||cpu()=="VF5XX-CA5"||cpu()=="VF4XX-CA5"||cpu()=="VF3XX-CA5")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 30. " SRAMLWP ,SRAM_L write protect" "Not protected,Protected"
|
|
bitfld.long 0x00 28.--29. " SRAMUWP ,SRAM_L arbitration priority" "Round robin,Special round robin,Processor highest,Backdoor highest"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SRAMUWP ,SRAM_U write protect" "Not protected,Protected"
|
|
bitfld.long 0x00 24.--25. " SRAMUAP ,SRAM_U arbitration priority" "Round robin,Special round robin,Processor highest,Backdoor highest"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ISCR,Interrupt Status And Control Register"
|
|
bitfld.long 0x00 31. " FIDCE ,FPU input denormal interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FIXCE ,FPU inexact interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " FUFCE ,FPU underflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " FOFCE ,FPU overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " FDZCE ,FPU divide-by-zero interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " FIOCE ,FPU invalid operation interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CWBEE ,Cache write buffer error enable" "Disable,Enable"
|
|
rbitfld.long 0x00 15. " FIDC ,FPU input denormal interrupt status" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 12. " FIXC ,FPU inexact interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " FUFC ,FPU underflow interrupt status" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 10. " FOFC ,FPU overflow interrupt status" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 9. " FDZC ,FPU divide-by-zero interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " FIOC ,FPU invalid operation interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " CWBER ,Cache write buffer error status" "No error,Error"
|
|
rbitfld.long 0x00 3. " DHREQ ,Debug halt request indicator" "Not requested,Requested"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "FADR,Fault Address Register"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "FATR,Fault Attributes Register"
|
|
bitfld.long 0x00 31. " BEOVR ,Bus error overrun" "No error,Error"
|
|
bitfld.long 0x00 8.--11. " BEMN ,Bus error master number" ",1,?..."
|
|
bitfld.long 0x00 7. " BEWT ,Bus error write" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BESZ ,Bus error size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 1. " BEMD ,Bus error privilege level" "User,Supervisor"
|
|
bitfld.long 0x00 0. " BEDA ,Bus error access type" "Instruction,Data"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "FDR,Fault Data Register"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PLACR,Platform Control Register"
|
|
bitfld.long 0x00 16. " ESFC ,Enable stalling flash controller" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " DFCS ,Disable flash controller speculation" "No,Yes"
|
|
bitfld.long 0x00 14. " EFDS ,Enable flash data speculation" "Disabled,Enabled"
|
|
sif !cpuis("MKL03*")
|
|
textline " "
|
|
bitfld.long 0x00 13. " DFCC ,Disable flash controller cache" "No,Yes"
|
|
bitfld.long 0x00 12. " DFCIC ,Disable flash controller instruction caching" "No,Yes"
|
|
bitfld.long 0x00 11. " DFCDA ,Disable flash controller data caching" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CFCC ,Clear flash controller cache" "No effect,Clear"
|
|
bitfld.long 0x00 9. " ARB ,Arbitration select" "Fixed-priority,Round-robin"
|
|
sif cpuis("MKL28*")
|
|
textline " "
|
|
bitfld.long 0x00 8. " MMCAU ,MMCAU Present" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CPO,Compute Operation Control Register"
|
|
bitfld.long 0x00 2. " CPOWOI ,Compute operation wakeup on interrupt" "No wakeup,Wakeup"
|
|
rbitfld.long 0x00 1. " CPOACK ,Compute operation" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " CPOREQ ,Compute operation request" "Not requested,Requested"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("MKL82Z*")
|
|
tree "MPU (Memory Protection Unit)"
|
|
base ad:0x4000D000
|
|
width 16.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CESR,Control/Error Status Register"
|
|
eventfld.long 0x00 31. " SPERR ,Slave port 0 error" "No error,Error"
|
|
eventfld.long 0x00 30. " SPERR ,Slave port 1 error" "No error,Error"
|
|
newline
|
|
sif cpuis("MKL82Z*")
|
|
eventfld.long 0x00 29. " SPERR ,Slave port 2 error" "No error,Error"
|
|
eventfld.long 0x00 28. " SPERR ,Slave port 3 error" "No error,Error"
|
|
newline
|
|
endif
|
|
rbitfld.long 0x00 16.--19. " HRL ,Hardware revision level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 12.--15. " NSP ,Number of slave ports" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 8.--11. " NRGD ,Number of region descriptors" "8 regions,12 regions,16 regions,?..."
|
|
bitfld.long 0x00 0. " VLD ,Valid" "Disabled,Enabled"
|
|
rgroup.long 0x10++0x0F
|
|
line.long 0x00 "EAR0,Error Address Register 0, Slave Port 0"
|
|
line.long 0x04 "EDR0,Error Detail Register 0, Slave Port 0"
|
|
hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail"
|
|
hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification"
|
|
sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKL82Z*")
|
|
bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x04 4.--7. " EMN ,Error master number" ",Bus 0,Bus 2,,Bus 3,,,,Bus 4,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x04 1.--3. " EATTR ,Error attributes" "User-instruction,User-data,Supervisor-instruction,Supervisor-data,?..."
|
|
bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write"
|
|
line.long 0x08 "EAR1,Error Address Register 1, Slave Port 1"
|
|
line.long 0x0C "EDR1,Error Detail Register 1, Slave Port 1"
|
|
hexmask.long.word 0x0C 16.--31. 1. " EACD ,Error access control detail"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " EPID ,Error process identification"
|
|
sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKL82Z*")
|
|
bitfld.long 0x0C 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x0C 4.--7. " EMN ,Error master number" ",Bus 0,Bus 2,,Bus 3,,,,Bus 4,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x0C 1.--3. " EATTR ,Error attributes" "User-instruction,User-data,Supervisor-instruction,Supervisor-data,?..."
|
|
bitfld.long 0x0C 0. " ERW ,Error read/write" "Read,Write"
|
|
sif cpuis("MKL82Z*")
|
|
rgroup.long 0x20++0x17
|
|
line.long 0x00 "EAR2,Error Address Register 2, Slave Port 2"
|
|
line.long 0x04 "EDR2,Error Detail Register 2, Slave Port 2"
|
|
hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail"
|
|
hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification"
|
|
bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 1.--3. " EATTR ,Error attributes" "User-instruction,User-data,Supervisor-instruction,Supervisor-data,?..."
|
|
bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write"
|
|
line.long 0x08 "EAR3,Error Address Register 3, Slave Port 3"
|
|
line.long 0x0C "EDR3,Error Detail Register 3, Slave Port 3"
|
|
hexmask.long.word 0x0C 16.--31. 1. " EACD ,Error access control detail"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " EPID ,Error process identification"
|
|
bitfld.long 0x0C 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0C 1.--3. " EATTR ,Error attributes" "User-instruction,User-data,Supervisor-instruction,Supervisor-data,?..."
|
|
bitfld.long 0x0C 0. " ERW ,Error read/write" "Read,Write"
|
|
line.long 0x10 "EAR4,Error Address Register 4, Slave Port 4"
|
|
line.long 0x14 "EDR4,Error Detail Register 4, Slave Port 4"
|
|
hexmask.long.word 0x14 16.--31. 1. " EACD ,Error access control detail"
|
|
hexmask.long.byte 0x14 8.--15. 1. " EPID ,Error process identification"
|
|
bitfld.long 0x14 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x14 1.--3. " EATTR ,Error attributes" "User-instruction,User-data,Supervisor-instruction,Supervisor-data,?..."
|
|
bitfld.long 0x14 0. " ERW ,Error read/write" "Read,Write"
|
|
endif
|
|
group.long (0x400+0x0)++0x07
|
|
line.long 0x00 "RGD0_WORD0,Region Descriptor 0, Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address"
|
|
line.long 0x04 "RGD0_WORD1,Region Descriptor 0, Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address"
|
|
group.long (0x408+0x0)++0x07
|
|
line.long 0x00 "RGD0_WORD2,Region Descriptor 0, Word 2"
|
|
bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "r/w/x,r/x,r/w,M3UM"
|
|
bitfld.long 0x00 18.--20. " M3UM ,Bus master 3 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "r/w/x,r/x,r/w,M2UM"
|
|
bitfld.long 0x00 12.--14. " M2UM ,Bus master 2 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "r/w/x,r/x,r/w,M1UM"
|
|
bitfld.long 0x00 6.--8. " M1UM ,Bus master 1 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "r/w/x,r/x,r/w,M0UM"
|
|
bitfld.long 0x00 0.--2. " M0UM ,Bus master 0 user mode access control" "Not allowed,Allowed,?..."
|
|
line.long 0x04 "RGD0_WORD3,Region Descriptor 0, Word 3"
|
|
hexmask.long.byte 0x04 24.--31. 1. " PID ,Process identifier"
|
|
hexmask.long.byte 0x04 16.--23. 1. " PIDMASK ,Process identifier mask"
|
|
bitfld.long 0x04 0. " VLD ,Valid" "Invalid,Valid"
|
|
group.long (0x400+0x10)++0x07
|
|
line.long 0x00 "RGD1_WORD0,Region Descriptor 1, Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address"
|
|
line.long 0x04 "RGD1_WORD1,Region Descriptor 1, Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address"
|
|
group.long (0x408+0x10)++0x07
|
|
line.long 0x00 "RGD1_WORD2,Region Descriptor 1, Word 2"
|
|
bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "r/w/x,r/x,r/w,M3UM"
|
|
bitfld.long 0x00 18.--20. " M3UM ,Bus master 3 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "r/w/x,r/x,r/w,M2UM"
|
|
bitfld.long 0x00 12.--14. " M2UM ,Bus master 2 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "r/w/x,r/x,r/w,M1UM"
|
|
bitfld.long 0x00 6.--8. " M1UM ,Bus master 1 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "r/w/x,r/x,r/w,M0UM"
|
|
bitfld.long 0x00 0.--2. " M0UM ,Bus master 0 user mode access control" "Not allowed,Allowed,?..."
|
|
line.long 0x04 "RGD1_WORD3,Region Descriptor 1, Word 3"
|
|
hexmask.long.byte 0x04 24.--31. 1. " PID ,Process identifier"
|
|
hexmask.long.byte 0x04 16.--23. 1. " PIDMASK ,Process identifier mask"
|
|
bitfld.long 0x04 0. " VLD ,Valid" "Invalid,Valid"
|
|
group.long (0x400+0x20)++0x07
|
|
line.long 0x00 "RGD2_WORD0,Region Descriptor 2, Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address"
|
|
line.long 0x04 "RGD2_WORD1,Region Descriptor 2, Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address"
|
|
group.long (0x408+0x20)++0x07
|
|
line.long 0x00 "RGD2_WORD2,Region Descriptor 2, Word 2"
|
|
bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "r/w/x,r/x,r/w,M3UM"
|
|
bitfld.long 0x00 18.--20. " M3UM ,Bus master 3 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "r/w/x,r/x,r/w,M2UM"
|
|
bitfld.long 0x00 12.--14. " M2UM ,Bus master 2 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "r/w/x,r/x,r/w,M1UM"
|
|
bitfld.long 0x00 6.--8. " M1UM ,Bus master 1 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "r/w/x,r/x,r/w,M0UM"
|
|
bitfld.long 0x00 0.--2. " M0UM ,Bus master 0 user mode access control" "Not allowed,Allowed,?..."
|
|
line.long 0x04 "RGD2_WORD3,Region Descriptor 2, Word 3"
|
|
hexmask.long.byte 0x04 24.--31. 1. " PID ,Process identifier"
|
|
hexmask.long.byte 0x04 16.--23. 1. " PIDMASK ,Process identifier mask"
|
|
bitfld.long 0x04 0. " VLD ,Valid" "Invalid,Valid"
|
|
group.long (0x400+0x30)++0x07
|
|
line.long 0x00 "RGD3_WORD0,Region Descriptor 3, Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address"
|
|
line.long 0x04 "RGD3_WORD1,Region Descriptor 3, Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address"
|
|
group.long (0x408+0x30)++0x07
|
|
line.long 0x00 "RGD3_WORD2,Region Descriptor 3, Word 2"
|
|
bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "r/w/x,r/x,r/w,M3UM"
|
|
bitfld.long 0x00 18.--20. " M3UM ,Bus master 3 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "r/w/x,r/x,r/w,M2UM"
|
|
bitfld.long 0x00 12.--14. " M2UM ,Bus master 2 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "r/w/x,r/x,r/w,M1UM"
|
|
bitfld.long 0x00 6.--8. " M1UM ,Bus master 1 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "r/w/x,r/x,r/w,M0UM"
|
|
bitfld.long 0x00 0.--2. " M0UM ,Bus master 0 user mode access control" "Not allowed,Allowed,?..."
|
|
line.long 0x04 "RGD3_WORD3,Region Descriptor 3, Word 3"
|
|
hexmask.long.byte 0x04 24.--31. 1. " PID ,Process identifier"
|
|
hexmask.long.byte 0x04 16.--23. 1. " PIDMASK ,Process identifier mask"
|
|
bitfld.long 0x04 0. " VLD ,Valid" "Invalid,Valid"
|
|
group.long (0x400+0x40)++0x07
|
|
line.long 0x00 "RGD4_WORD0,Region Descriptor 4, Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address"
|
|
line.long 0x04 "RGD4_WORD1,Region Descriptor 4, Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address"
|
|
group.long (0x408+0x40)++0x07
|
|
line.long 0x00 "RGD4_WORD2,Region Descriptor 4, Word 2"
|
|
bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "r/w/x,r/x,r/w,M3UM"
|
|
bitfld.long 0x00 18.--20. " M3UM ,Bus master 3 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "r/w/x,r/x,r/w,M2UM"
|
|
bitfld.long 0x00 12.--14. " M2UM ,Bus master 2 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "r/w/x,r/x,r/w,M1UM"
|
|
bitfld.long 0x00 6.--8. " M1UM ,Bus master 1 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "r/w/x,r/x,r/w,M0UM"
|
|
bitfld.long 0x00 0.--2. " M0UM ,Bus master 0 user mode access control" "Not allowed,Allowed,?..."
|
|
line.long 0x04 "RGD4_WORD3,Region Descriptor 4, Word 3"
|
|
hexmask.long.byte 0x04 24.--31. 1. " PID ,Process identifier"
|
|
hexmask.long.byte 0x04 16.--23. 1. " PIDMASK ,Process identifier mask"
|
|
bitfld.long 0x04 0. " VLD ,Valid" "Invalid,Valid"
|
|
group.long (0x400+0x50)++0x07
|
|
line.long 0x00 "RGD5_WORD0,Region Descriptor 5, Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address"
|
|
line.long 0x04 "RGD5_WORD1,Region Descriptor 5, Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address"
|
|
group.long (0x408+0x50)++0x07
|
|
line.long 0x00 "RGD5_WORD2,Region Descriptor 5, Word 2"
|
|
bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "r/w/x,r/x,r/w,M3UM"
|
|
bitfld.long 0x00 18.--20. " M3UM ,Bus master 3 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "r/w/x,r/x,r/w,M2UM"
|
|
bitfld.long 0x00 12.--14. " M2UM ,Bus master 2 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "r/w/x,r/x,r/w,M1UM"
|
|
bitfld.long 0x00 6.--8. " M1UM ,Bus master 1 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "r/w/x,r/x,r/w,M0UM"
|
|
bitfld.long 0x00 0.--2. " M0UM ,Bus master 0 user mode access control" "Not allowed,Allowed,?..."
|
|
line.long 0x04 "RGD5_WORD3,Region Descriptor 5, Word 3"
|
|
hexmask.long.byte 0x04 24.--31. 1. " PID ,Process identifier"
|
|
hexmask.long.byte 0x04 16.--23. 1. " PIDMASK ,Process identifier mask"
|
|
bitfld.long 0x04 0. " VLD ,Valid" "Invalid,Valid"
|
|
group.long (0x400+0x60)++0x07
|
|
line.long 0x00 "RGD6_WORD0,Region Descriptor 6, Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address"
|
|
line.long 0x04 "RGD6_WORD1,Region Descriptor 6, Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address"
|
|
group.long (0x408+0x60)++0x07
|
|
line.long 0x00 "RGD6_WORD2,Region Descriptor 6, Word 2"
|
|
bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "r/w/x,r/x,r/w,M3UM"
|
|
bitfld.long 0x00 18.--20. " M3UM ,Bus master 3 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "r/w/x,r/x,r/w,M2UM"
|
|
bitfld.long 0x00 12.--14. " M2UM ,Bus master 2 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "r/w/x,r/x,r/w,M1UM"
|
|
bitfld.long 0x00 6.--8. " M1UM ,Bus master 1 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "r/w/x,r/x,r/w,M0UM"
|
|
bitfld.long 0x00 0.--2. " M0UM ,Bus master 0 user mode access control" "Not allowed,Allowed,?..."
|
|
line.long 0x04 "RGD6_WORD3,Region Descriptor 6, Word 3"
|
|
hexmask.long.byte 0x04 24.--31. 1. " PID ,Process identifier"
|
|
hexmask.long.byte 0x04 16.--23. 1. " PIDMASK ,Process identifier mask"
|
|
bitfld.long 0x04 0. " VLD ,Valid" "Invalid,Valid"
|
|
group.long (0x400+0x70)++0x07
|
|
line.long 0x00 "RGD7_WORD0,Region Descriptor 7, Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address"
|
|
line.long 0x04 "RGD7_WORD1,Region Descriptor 7, Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address"
|
|
group.long (0x408+0x70)++0x07
|
|
line.long 0x00 "RGD7_WORD2,Region Descriptor 7, Word 2"
|
|
bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "r/w/x,r/x,r/w,M3UM"
|
|
bitfld.long 0x00 18.--20. " M3UM ,Bus master 3 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "r/w/x,r/x,r/w,M2UM"
|
|
bitfld.long 0x00 12.--14. " M2UM ,Bus master 2 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "r/w/x,r/x,r/w,M1UM"
|
|
bitfld.long 0x00 6.--8. " M1UM ,Bus master 1 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "r/w/x,r/x,r/w,M0UM"
|
|
bitfld.long 0x00 0.--2. " M0UM ,Bus master 0 user mode access control" "Not allowed,Allowed,?..."
|
|
line.long 0x04 "RGD7_WORD3,Region Descriptor 7, Word 3"
|
|
hexmask.long.byte 0x04 24.--31. 1. " PID ,Process identifier"
|
|
hexmask.long.byte 0x04 16.--23. 1. " PIDMASK ,Process identifier mask"
|
|
bitfld.long 0x04 0. " VLD ,Valid" "Invalid,Valid"
|
|
group.long (0x800+0x0)++0x03
|
|
line.long 0x00 "RGDAAC0,Region Descriptor Alternate Access Control 0"
|
|
bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "r/w/x,r/x,r/w,M3UM"
|
|
bitfld.long 0x00 18.--20. " M3UM ,Bus master 3 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "r/w/x,r/x,r/w,M2UM"
|
|
bitfld.long 0x00 12.--14. " M2UM ,Bus master 2 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "r/w/x,r/x,r/w,M1UM"
|
|
bitfld.long 0x00 6.--8. " M1UM ,Bus master 1 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "r/w/x,r/x,r/w,M0UM"
|
|
bitfld.long 0x00 0.--2. " M0UM ,Bus master 0 user mode access control" "Not allowed,Allowed,?..."
|
|
group.long (0x800+0x4)++0x03
|
|
line.long 0x00 "RGDAAC1,Region Descriptor Alternate Access Control 1"
|
|
bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "r/w/x,r/x,r/w,M3UM"
|
|
bitfld.long 0x00 18.--20. " M3UM ,Bus master 3 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "r/w/x,r/x,r/w,M2UM"
|
|
bitfld.long 0x00 12.--14. " M2UM ,Bus master 2 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "r/w/x,r/x,r/w,M1UM"
|
|
bitfld.long 0x00 6.--8. " M1UM ,Bus master 1 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "r/w/x,r/x,r/w,M0UM"
|
|
bitfld.long 0x00 0.--2. " M0UM ,Bus master 0 user mode access control" "Not allowed,Allowed,?..."
|
|
group.long (0x800+0x8)++0x03
|
|
line.long 0x00 "RGDAAC2,Region Descriptor Alternate Access Control 2"
|
|
bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "r/w/x,r/x,r/w,M3UM"
|
|
bitfld.long 0x00 18.--20. " M3UM ,Bus master 3 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "r/w/x,r/x,r/w,M2UM"
|
|
bitfld.long 0x00 12.--14. " M2UM ,Bus master 2 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "r/w/x,r/x,r/w,M1UM"
|
|
bitfld.long 0x00 6.--8. " M1UM ,Bus master 1 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "r/w/x,r/x,r/w,M0UM"
|
|
bitfld.long 0x00 0.--2. " M0UM ,Bus master 0 user mode access control" "Not allowed,Allowed,?..."
|
|
group.long (0x800+0xC)++0x03
|
|
line.long 0x00 "RGDAAC3,Region Descriptor Alternate Access Control 3"
|
|
bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "r/w/x,r/x,r/w,M3UM"
|
|
bitfld.long 0x00 18.--20. " M3UM ,Bus master 3 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "r/w/x,r/x,r/w,M2UM"
|
|
bitfld.long 0x00 12.--14. " M2UM ,Bus master 2 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "r/w/x,r/x,r/w,M1UM"
|
|
bitfld.long 0x00 6.--8. " M1UM ,Bus master 1 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "r/w/x,r/x,r/w,M0UM"
|
|
bitfld.long 0x00 0.--2. " M0UM ,Bus master 0 user mode access control" "Not allowed,Allowed,?..."
|
|
group.long (0x800+0x10)++0x03
|
|
line.long 0x00 "RGDAAC4,Region Descriptor Alternate Access Control 4"
|
|
bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "r/w/x,r/x,r/w,M3UM"
|
|
bitfld.long 0x00 18.--20. " M3UM ,Bus master 3 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "r/w/x,r/x,r/w,M2UM"
|
|
bitfld.long 0x00 12.--14. " M2UM ,Bus master 2 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "r/w/x,r/x,r/w,M1UM"
|
|
bitfld.long 0x00 6.--8. " M1UM ,Bus master 1 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "r/w/x,r/x,r/w,M0UM"
|
|
bitfld.long 0x00 0.--2. " M0UM ,Bus master 0 user mode access control" "Not allowed,Allowed,?..."
|
|
group.long (0x800+0x14)++0x03
|
|
line.long 0x00 "RGDAAC5,Region Descriptor Alternate Access Control 5"
|
|
bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "r/w/x,r/x,r/w,M3UM"
|
|
bitfld.long 0x00 18.--20. " M3UM ,Bus master 3 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "r/w/x,r/x,r/w,M2UM"
|
|
bitfld.long 0x00 12.--14. " M2UM ,Bus master 2 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "r/w/x,r/x,r/w,M1UM"
|
|
bitfld.long 0x00 6.--8. " M1UM ,Bus master 1 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "r/w/x,r/x,r/w,M0UM"
|
|
bitfld.long 0x00 0.--2. " M0UM ,Bus master 0 user mode access control" "Not allowed,Allowed,?..."
|
|
group.long (0x800+0x18)++0x03
|
|
line.long 0x00 "RGDAAC6,Region Descriptor Alternate Access Control 6"
|
|
bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "r/w/x,r/x,r/w,M3UM"
|
|
bitfld.long 0x00 18.--20. " M3UM ,Bus master 3 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "r/w/x,r/x,r/w,M2UM"
|
|
bitfld.long 0x00 12.--14. " M2UM ,Bus master 2 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "r/w/x,r/x,r/w,M1UM"
|
|
bitfld.long 0x00 6.--8. " M1UM ,Bus master 1 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "r/w/x,r/x,r/w,M0UM"
|
|
bitfld.long 0x00 0.--2. " M0UM ,Bus master 0 user mode access control" "Not allowed,Allowed,?..."
|
|
group.long (0x800+0x1C)++0x03
|
|
line.long 0x00 "RGDAAC7,Region Descriptor Alternate Access Control 7"
|
|
bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "r/w/x,r/x,r/w,M3UM"
|
|
bitfld.long 0x00 18.--20. " M3UM ,Bus master 3 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "r/w/x,r/x,r/w,M2UM"
|
|
bitfld.long 0x00 12.--14. " M2UM ,Bus master 2 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "r/w/x,r/x,r/w,M1UM"
|
|
bitfld.long 0x00 6.--8. " M1UM ,Bus master 1 user mode access control" "Not allowed,Allowed,?..."
|
|
bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "r/w/x,r/x,r/w,M0UM"
|
|
bitfld.long 0x00 0.--2. " M0UM ,Bus master 0 user mode access control" "Not allowed,Allowed,?..."
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "MTB (Micro Trace Buffer)"
|
|
tree "MTB_RAM"
|
|
base ad:0xF0000000
|
|
width 14.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "POSITION,MTB Position Register"
|
|
hexmask.long 0x00 3.--31. 0x08 " POINTER ,Trace packet address pointer"
|
|
bitfld.long 0x00 2. " WRAP ,Pointer value wraps" "Not wrapped,Wrapped"
|
|
line.long 0x04 "MASTER,MTB Master Register"
|
|
bitfld.long 0x04 31. " EN ,Main trace enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " HALTREQ ,Halt request bit" "Not requested,Requested"
|
|
bitfld.long 0x04 8. " RAMPRIV ,RAM privilege bit" "User/privilege AHB,Privilege AHB"
|
|
textline " "
|
|
bitfld.long 0x04 7. " SFRWPRIV ,Special function register write privilege bit" "User/privilege AHB,Privilege AHB"
|
|
bitfld.long 0x04 6. " TSTOPEN ,Trace stop input enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " TSTARTEN ,Trace start input enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0.--4. " MASK ,Maximum size of the trace buffer in RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "FLOW,MTB Flow Register"
|
|
hexmask.long 0x08 3.--31. 1. " WATERMARK ,Watermark value"
|
|
bitfld.long 0x08 1. " AUTOHALT ,Auto halt" "Not halted,Halted"
|
|
bitfld.long 0x08 0. " AUTOSTOP ,Autostop" "Not stopped,Stopped"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "BASE,MTB Base Register"
|
|
rgroup.long 0xF00++0x03
|
|
line.long 0x00 "MODECTRL,Integration Mode Control Register"
|
|
rgroup.long 0xFA0++0x07
|
|
line.long 0x00 "TAGSET,Claim TAG Set Register"
|
|
line.long 0x04 "TAGCLEAR,Claim TAG Clear Register"
|
|
rgroup.long 0xFB0++0x0F
|
|
line.long 0x00 "LOCKACCESS,Lock Access Register"
|
|
line.long 0x04 "LOCKSTAT,Lock Status Register"
|
|
line.long 0x08 "AUTHSTAT,Authentication Status Register"
|
|
bitfld.long 0x08 2. " BIT2 ,It's hardwired to NIDEN or DBGEN signal" "Low,High"
|
|
bitfld.long 0x08 0. " BIT0 ,It's hardwired to DBGEN" "Low,High"
|
|
line.long 0x0C "DEVICEARCH,Device Architecture Register"
|
|
rgroup.long 0xFC8++0x07
|
|
line.long 0x00 "DEVICECFG,Device Configuration Register"
|
|
line.long 0x04 "DEVICETYPID,Device Type Identifier Register"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PERIPHID_4,Peripheral ID Register 4"
|
|
rgroup.long 0xFD4++0x03
|
|
line.long 0x00 "PERIPHID_5,Peripheral ID Register 5"
|
|
rgroup.long 0xFD8++0x03
|
|
line.long 0x00 "PERIPHID_6,Peripheral ID Register 6"
|
|
rgroup.long 0xFDC++0x03
|
|
line.long 0x00 "PERIPHID_7,Peripheral ID Register 7"
|
|
rgroup.long 0xFE0++0x03
|
|
line.long 0x00 "PERIPHID_0,Peripheral ID Register 0"
|
|
rgroup.long 0xFE4++0x03
|
|
line.long 0x00 "PERIPHID_1,Peripheral ID Register 1"
|
|
rgroup.long 0xFE8++0x03
|
|
line.long 0x00 "PERIPHID_2,Peripheral ID Register 2"
|
|
rgroup.long 0xFEC++0x03
|
|
line.long 0x00 "PERIPHID_3,Peripheral ID Register 3"
|
|
rgroup.long 0xFF0++0x03
|
|
line.long 0x00 "COMPID_0,Component ID Register 0"
|
|
rgroup.long 0xFF4++0x03
|
|
line.long 0x00 "COMPID_1,Component ID Register 1"
|
|
rgroup.long 0xFF8++0x03
|
|
line.long 0x00 "COMPID_2,Component ID Register 2"
|
|
rgroup.long 0xFFC++0x03
|
|
line.long 0x00 "COMPID_3,Component ID Register 3"
|
|
width 0x0B
|
|
tree.end
|
|
tree "MTB_DWT"
|
|
base ad:0xF0001000
|
|
width 13.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CTRL,MTB DWT Control Register"
|
|
bitfld.long 0x00 28.--31. " NUMCMP ,Number of comparators" "0,1,?..."
|
|
bitfld.long 0x00 27. " NOTRCPKT ,Trace sample and exception trace" "Supported,Not supported"
|
|
bitfld.long 0x00 26. " NOEXTTRIG ,External match signals" "Supported,Not supported"
|
|
textline " "
|
|
bitfld.long 0x00 25. " NOCYCCNT ,Cycle counter" "Supported,Not supported"
|
|
bitfld.long 0x00 24. " NOPRFCNT ,Profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEBTENA ,POSTCNT underflow packets" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Folded instruction counter overflow events" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,LSU counter overflow events" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Sleep counter overflow events" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Exception overhead counter events" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,CPI counter overflow events" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLENA ,Periodic PC sample packets" "Not generated,Generated"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Synchronization packets" "0,1,2,3"
|
|
bitfld.long 0x00 9. " CYCTAP ,Cycle counter" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Cycle counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Cycle counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Cycle counter" "Not supported,Supported"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "COMP_0,MTB_DWT Comparator Register 0"
|
|
line.long 0x04 "MASK_0,MTB_DWT Comparator Mask Register 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,?..."
|
|
line.long 0x08 "FCT_0,MTB_DWT Comparator Function Register 0"
|
|
rbitfld.long 0x08 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x08 12.--15. " DATAVADDR0 ,Data value address 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 10.--11. " DATAVSIZE ,Data value size" "Byte,Halfword,Word,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8. " DATAVMATCH ,Data value match" "Address comparison,Data value comparison"
|
|
bitfld.long 0x08 0.--3. " FUNCTION ,Function" "Disabled,,,,Instruction fetch,Data operand read,Data operand write,R/W,?..."
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "COMP_1,MTB_DWT Comparator Register 1"
|
|
line.long 0x04 "MASK_1,MTB_DWT Comparator Mask Register 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,?..."
|
|
line.long 0x08 "FCT_1,MTB_DWT Comparator Function Register 1"
|
|
rbitfld.long 0x08 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x08 0.--3. " FUNCTION ,Function" "Disabled,,,,Instruction fetch,Data operand read,Data operand write,R/W,?..."
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "TBCTRL,MTB_DWT Trace Buffer Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators" "0,1,?..."
|
|
bitfld.long 0x00 1. " ACOMP1 ,Action based on comparator 1 match" "Stopped,Started"
|
|
bitfld.long 0x00 0. " ACOMP0 ,Action based on comparator 0 match" "Stopped,Started"
|
|
rgroup.long 0xFC8++0x07
|
|
line.long 0x00 "DEVICECFG,Device Configuration Register"
|
|
line.long 0x04 "DEVICETYPID,Device Type Identifier Register"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PERIPHID_4,Peripheral ID Register 4"
|
|
rgroup.long 0xFD4++0x03
|
|
line.long 0x00 "PERIPHID_5,Peripheral ID Register 5"
|
|
rgroup.long 0xFD8++0x03
|
|
line.long 0x00 "PERIPHID_6,Peripheral ID Register 6"
|
|
rgroup.long 0xFDC++0x03
|
|
line.long 0x00 "PERIPHID_7,Peripheral ID Register 7"
|
|
rgroup.long 0xFE0++0x03
|
|
line.long 0x00 "PERIPHID_0,Peripheral ID Register 0"
|
|
rgroup.long 0xFE4++0x03
|
|
line.long 0x00 "PERIPHID_1,Peripheral ID Register 1"
|
|
rgroup.long 0xFE8++0x03
|
|
line.long 0x00 "PERIPHID_2,Peripheral ID Register 2"
|
|
rgroup.long 0xFEC++0x03
|
|
line.long 0x00 "PERIPHID_3,Peripheral ID Register 3"
|
|
rgroup.long 0xFF0++0x03
|
|
line.long 0x00 "COMPID_0,Component ID Register 0"
|
|
rgroup.long 0xFF4++0x03
|
|
line.long 0x00 "COMPID_1,Component ID Register 1"
|
|
rgroup.long 0xFF8++0x03
|
|
line.long 0x00 "COMPID_2,Component ID Register 2"
|
|
rgroup.long 0xFFC++0x03
|
|
line.long 0x00 "COMPID_3,Component ID Register 3"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SYSTEM_ROM"
|
|
base ad:0xF0002000
|
|
width 13.
|
|
sif cpuis("K32W0?2S1M*")
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "ENTRY_0,Entry Register 0"
|
|
rgroup.long 0x4++0x03
|
|
line.long 0x00 "ENTRY_1,Entry Register 1"
|
|
rgroup.long 0x8++0x03
|
|
line.long 0x00 "ENTRY_2,Entry Register 2"
|
|
rgroup.long 0xC++0x03
|
|
line.long 0x00 "ENTRY_3,Entry Register 3"
|
|
else
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "ENTRY_0,Entry Register 0"
|
|
rgroup.long 0x4++0x03
|
|
line.long 0x00 "ENTRY_1,Entry Register 1"
|
|
rgroup.long 0x8++0x03
|
|
line.long 0x00 "ENTRY_2,Entry Register 2"
|
|
endif
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "TABLEMARK,End Of Table Marker Register"
|
|
rgroup.long 0xFCC++0x03
|
|
line.long 0x00 "SYSACCESS,System Access Register"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PERIPHID_4,Peripheral ID Register 4"
|
|
rgroup.long 0xFD4++0x03
|
|
line.long 0x00 "PERIPHID_5,Peripheral ID Register 5"
|
|
rgroup.long 0xFD8++0x03
|
|
line.long 0x00 "PERIPHID_6,Peripheral ID Register 6"
|
|
rgroup.long 0xFDC++0x03
|
|
line.long 0x00 "PERIPHID_7,Peripheral ID Register 7"
|
|
rgroup.long 0xFE0++0x03
|
|
line.long 0x00 "PERIPHID_0,Peripheral ID Register 0"
|
|
rgroup.long 0xFE4++0x03
|
|
line.long 0x00 "PERIPHID_1,Peripheral ID Register 1"
|
|
rgroup.long 0xFE8++0x03
|
|
line.long 0x00 "PERIPHID_2,Peripheral ID Register 2"
|
|
rgroup.long 0xFEC++0x03
|
|
line.long 0x00 "PERIPHID_3,Peripheral ID Register 3"
|
|
rgroup.long 0xFF0++0x03
|
|
line.long 0x00 "COMPID_0,Component ID Register 0"
|
|
rgroup.long 0xFF4++0x03
|
|
line.long 0x00 "COMPID_1,Component ID Register 1"
|
|
rgroup.long 0xFF8++0x03
|
|
line.long 0x00 "COMPID_2,Component ID Register 2"
|
|
rgroup.long 0xFFC++0x03
|
|
line.long 0x00 "COMPID_3,Component ID Register 3"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
tree "DMAMUX (Direct Memory Access Multiplexer)"
|
|
base ad:0x40021000
|
|
width 10.
|
|
sif cpuis("MKL28Z*")
|
|
group.byte 0x0++0x00
|
|
line.byte 0x00 "CHCFG_0,Channel Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 0 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA channel 0 trigger enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" "Disabled,,LPUART0 rx,LPUART0 tx,LPUART1 rx,LPUART1 tx,UART2 rx,UART2 tx,,,Flex_io ch_0,Flex_io ch_1,Flex_io ch_2,Flex_io ch_3,I2S0 rx,I2S0 tx,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,,,I2C0,I2C1,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,TMP2 ch_0,TMP2 ch_1,,,,,ADC0,,CMP0,,,DAC0,,,,Port control A,,Port control C,Port control D,,TMP0 overflow,TMP1 overflow,TMP2 overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
group.byte 0x1++0x00
|
|
line.byte 0x00 "CHCFG_1,Channel Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 1 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" "Disabled,,LPUART0 rx,LPUART0 tx,LPUART1 rx,LPUART1 tx,UART2 rx,UART2 tx,,,Flex_io ch_0,Flex_io ch_1,Flex_io ch_2,Flex_io ch_3,I2S0 rx,I2S0 tx,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,,,I2C0,I2C1,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,TMP2 ch_0,TMP2 ch_1,,,,,ADC0,,CMP0,,,DAC0,,,,Port control A,,Port control C,Port control D,,TMP0 overflow,TMP1 overflow,TMP2 overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
group.byte 0x2++0x00
|
|
line.byte 0x00 "CHCFG_2,Channel Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 2 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" "Disabled,,LPUART0 rx,LPUART0 tx,LPUART1 rx,LPUART1 tx,UART2 rx,UART2 tx,,,Flex_io ch_0,Flex_io ch_1,Flex_io ch_2,Flex_io ch_3,I2S0 rx,I2S0 tx,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,,,I2C0,I2C1,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,TMP2 ch_0,TMP2 ch_1,,,,,ADC0,,CMP0,,,DAC0,,,,Port control A,,Port control C,Port control D,,TMP0 overflow,TMP1 overflow,TMP2 overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
group.byte 0x3++0x00
|
|
line.byte 0x00 "CHCFG_3,Channel Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 3 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA channel 3 trigger enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" "Disabled,,LPUART0 rx,LPUART0 tx,LPUART1 rx,LPUART1 tx,UART2 rx,UART2 tx,,,Flex_io ch_0,Flex_io ch_1,Flex_io ch_2,Flex_io ch_3,I2S0 rx,I2S0 tx,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,,,I2C0,I2C1,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,TMP2 ch_0,TMP2 ch_1,,,,,ADC0,,CMP0,,,DAC0,,,,Port control A,,Port control C,Port control D,,TMP0 overflow,TMP1 overflow,TMP2 overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
group.byte 0x4++0x00
|
|
line.byte 0x00 "CHCFG_4,Channel Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 4 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA channel 4 trigger enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 4 source" "Disabled,,LPUART0 rx,LPUART0 tx,LPUART1 rx,LPUART1 tx,UART2 rx,UART2 tx,,,Flex_io ch_0,Flex_io ch_1,Flex_io ch_2,Flex_io ch_3,I2S0 rx,I2S0 tx,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,,,I2C0,I2C1,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,TMP2 ch_0,TMP2 ch_1,,,,,ADC0,,CMP0,,,DAC0,,,,Port control A,,Port control C,Port control D,,TMP0 overflow,TMP1 overflow,TMP2 overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
group.byte 0x5++0x00
|
|
line.byte 0x00 "CHCFG_5,Channel Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 5 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA channel 5 trigger enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 5 source" "Disabled,,LPUART0 rx,LPUART0 tx,LPUART1 rx,LPUART1 tx,UART2 rx,UART2 tx,,,Flex_io ch_0,Flex_io ch_1,Flex_io ch_2,Flex_io ch_3,I2S0 rx,I2S0 tx,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,,,I2C0,I2C1,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,TMP2 ch_0,TMP2 ch_1,,,,,ADC0,,CMP0,,,DAC0,,,,Port control A,,Port control C,Port control D,,TMP0 overflow,TMP1 overflow,TMP2 overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
group.byte 0x6++0x00
|
|
line.byte 0x00 "CHCFG_6,Channel Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 6 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA channel 6 trigger enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 6 source" "Disabled,,LPUART0 rx,LPUART0 tx,LPUART1 rx,LPUART1 tx,UART2 rx,UART2 tx,,,Flex_io ch_0,Flex_io ch_1,Flex_io ch_2,Flex_io ch_3,I2S0 rx,I2S0 tx,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,,,I2C0,I2C1,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,TMP2 ch_0,TMP2 ch_1,,,,,ADC0,,CMP0,,,DAC0,,,,Port control A,,Port control C,Port control D,,TMP0 overflow,TMP1 overflow,TMP2 overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
group.byte 0x7++0x00
|
|
line.byte 0x00 "CHCFG_7,Channel Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 7 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA channel 7 trigger enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 7 source" "Disabled,,LPUART0 rx,LPUART0 tx,LPUART1 rx,LPUART1 tx,UART2 rx,UART2 tx,,,Flex_io ch_0,Flex_io ch_1,Flex_io ch_2,Flex_io ch_3,I2S0 rx,I2S0 tx,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,,,I2C0,I2C1,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,TMP2 ch_0,TMP2 ch_1,,,,,ADC0,,CMP0,,,DAC0,,,,Port control A,,Port control C,Port control D,,TMP0 overflow,TMP1 overflow,TMP2 overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
else
|
|
group.byte 0x0++0x00
|
|
line.byte 0x00 "CHCFG_0,Channel Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 0 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA channel 0 trigger enable" "Disabled,Enabled"
|
|
sif cpuis("MKL25Z*")||cpuis("MKL15Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" "Disabled,,UART0 rx,UART0 tx,UART1 rx,UART1 tx,UART2 rx,UART2 tx,,,,,,,,,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,,,I2C0,I2C1,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,TMP2 ch_0,TMP2 ch_1,,,,,ADC0,,CMP0,,,DAC0,,,,Port control A,,,Port control D,,TMP0 overflow,TMP1 overflow,TMP2 overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif cpuis("MKL34Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" "Disabled,,UART0 rx,UART0 tx,UART1 rx,UART1 tx,UART2 rx,UART2 tx,,,,,,,,,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,,,I2C0,I2C1,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,TMP2 ch_0,TMP2 ch_1,,,,,ADC0,,CMP0,,,DAC0,,,,Port control A,,Port control C,Port control D,,TMP0 overflow,TMP1 overflow,TMP2 overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif cpuis("MKL36Z*")||cpuis("MKL46Z*")||cpuis("MKL16*")||cpuis("MKL26*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" "Disabled,,UART0 rx,UART0 tx,UART1 rx,UART1 tx,UART2 rx,UART2 tx,,,,,,,I2S0 rx,I2S0 tx,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,,,I2C0,I2C1,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,TMP2 ch_0,TMP2 ch_1,,,,,ADC0,,CMP0,,,DAC0,,,,Port control A,,Port control C,Port control D,,TMP0 overflow,TMP1 overflow,TMP2 overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif cpuis("MKL24Z*")||cpuis("MKL14Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" "Disabled,,UART0 rx,UART0 tx,UART1 rx,UART1 tx,UART2 rx,UART2 tx,,,,,,,,,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,,,I2C0,I2C1,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,TMP2 ch_0,TMP2 ch_1,,,,,ADC0,,CMP0,,,,,,,Port control A,,,Port control D,,TMP0 overflow,TMP1 overflow,TMP2 overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif cpuis("MKL05Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" "Disabled,,UART0 rx,UART0 tx,,,,,,,,,,,,,SPI0 rx,SPI0 tx,,,,,I2C0,,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,,,,,,,ADC0,,CMP0,,,DAC0,,,,Port control A,Port control B,,,,TMP0 overflow,TMP1 overflow,,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif cpuis("MKL04Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" "Disabled,,UART0 rx,UART0 tx,,,,,,,,,,,,,SPI0 rx,SPI0 tx,,,,,I2C0,,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,,,,,,,ADC0,,CMP0,,,,,,,Port control A,Port control B,,,,TMP0 overflow,TMP1 overflow,,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL27Z128*")||cpuis("MKL27Z256*")||cpuis("MKL33Z128*")||cpuis("MKL33Z256*")||cpuis("MKL43Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" "Disabled,,LPUART0 rx,LPUART0 tx,LPUART1 rx,LPUART1 tx,UART2 rx,UART2 tx,,,Flex_io ch_0,Flex_io ch_1,Flex_io ch_2,Flex_io ch_3,I2S0 rx,I2S0 tx,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,,,I2C0,I2C1,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,TMP2 ch_0,TMP2 ch_1,,,,,ADC0,,CMP0,,,DAC0,,,,Port control A,,Port control C,Port control D,,TMP0 overflow,TMP1 overflow,TMP2 overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif cpuis("MKL13*")||cpuis("MKL17Z32*")||cpuis("MKL17Z64*")||cpuis("MKL27Z32*")||cpuis("MKL27Z64*")||cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" "Disabled,,LPUART0 rx,LPUART0 tx,LPUART1 rx,LPUART1 tx,UART2 rx,UART2 tx,,,Flex_io ch_0,Flex_io ch_1,Flex_io ch_2,Flex_io ch_3,,,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,,,I2C0,I2C1,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,TMP2 ch_0,TMP2 ch_1,,,,,ADC0,,CMP0,,,,,,,Port control A,Port control B,Port control C,Port control D,Port control E,TMP0 overflow,TMP1 overflow,TMP2 overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif cpuis("MKL82*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" "Disabled,Flex_io sh_0,Flex_io sh_1,Flex_io sh_2,Flex_io sh_3,Flex_io sh_4,Flex_io sh_5,Flex_io sh_6,Flex_io sh_7,I2C0,I2C1,,,,,LPUART0 rx,LPUART0 tx,LPUART1 rx,LPUART1 tx,LPUART2 rx,LPUART2 tx,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,QSPI0 rx,QSPI0 tx,TPM0 ch_0,TPM0 ch_1,TPM0 ch_2,TPM0 ch_3,TPM0 ch_4,TPM0 ch_5,,,TPM0 overflow,TPM1 ch_0,TPM1 ch_1,TPM1 overflow,TPM2 ch_0,TPM2 ch_1,TPM2 overflow,TSI0,EMVSIM0 rx,EMVSIM0 tx,EMVSIM1 rx,EMVSIM1 tx,PortA,PortB,PortC,PortD,PortE,ADC0,,DAC0,LTC0 RAM,CMP0,,LTC0 Input,LTC0 Output,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
endif
|
|
group.byte 0x1++0x00
|
|
line.byte 0x00 "CHCFG_1,Channel Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 1 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA channel 1 trigger enable" "Disabled,Enabled"
|
|
sif cpuis("MKL25Z*")||cpuis("MKL15Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" "Disabled,,UART0 rx,UART0 tx,UART1 rx,UART1 tx,UART2 rx,UART2 tx,,,,,,,,,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,,,I2C0,I2C1,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,TMP2 ch_0,TMP2 ch_1,,,,,ADC0,,CMP0,,,DAC0,,,,Port control A,,,Port control D,,TMP0 overflow,TMP1 overflow,TMP2 overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif cpuis("MKL34Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" "Disabled,,UART0 rx,UART0 tx,UART1 rx,UART1 tx,UART2 rx,UART2 tx,,,,,,,,,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,,,I2C0,I2C1,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,TMP2 ch_0,TMP2 ch_1,,,,,ADC0,,CMP0,,,DAC0,,,,Port control A,,Port control C,Port control D,,TMP0 overflow,TMP1 overflow,TMP2 overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif cpuis("MKL36Z*")||cpuis("MKL46Z*")||cpuis("MKL16*")||cpuis("MKL26*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" "Disabled,,UART0 rx,UART0 tx,UART1 rx,UART1 tx,UART2 rx,UART2 tx,,,,,,,I2S0 rx,I2S0 tx,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,,,I2C0,I2C1,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,TMP2 ch_0,TMP2 ch_1,,,,,ADC0,,CMP0,,,DAC0,,,,Port control A,,Port control C,Port control D,,TMP0 overflow,TMP1 overflow,TMP2 overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif cpuis("MKL24Z*")||cpuis("MKL14Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" "Disabled,,UART0 rx,UART0 tx,UART1 rx,UART1 tx,UART2 rx,UART2 tx,,,,,,,,,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,,,I2C0,I2C1,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,TMP2 ch_0,TMP2 ch_1,,,,,ADC0,,CMP0,,,,,,,Port control A,,,Port control D,,TMP0 overflow,TMP1 overflow,TMP2 overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif cpuis("MKL05Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" "Disabled,,UART0 rx,UART0 tx,,,,,,,,,,,,,SPI0 rx,SPI0 tx,,,,,I2C0,,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,,,,,,,ADC0,,CMP0,,,DAC0,,,,Port control A,Port control B,,,,TMP0 overflow,TMP1 overflow,,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif cpuis("MKL04Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" "Disabled,,UART0 rx,UART0 tx,,,,,,,,,,,,,SPI0 rx,SPI0 tx,,,,,I2C0,,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,,,,,,,ADC0,,CMP0,,,,,,,Port control A,Port control B,,,,TMP0 overflow,TMP1 overflow,,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL27Z128*")||cpuis("MKL27Z256*")||cpuis("MKL33Z128*")||cpuis("MKL33Z256*")||cpuis("MKL43Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" "Disabled,,LPUART0 rx,LPUART0 tx,LPUART1 rx,LPUART1 tx,UART2 rx,UART2 tx,,,Flex_io ch_0,Flex_io ch_1,Flex_io ch_2,Flex_io ch_3,I2S0 rx,I2S0 tx,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,,,I2C0,I2C1,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,TMP2 ch_0,TMP2 ch_1,,,,,ADC0,,CMP0,,,DAC0,,,,Port control A,,Port control C,Port control D,,TMP0 overflow,TMP1 overflow,TMP2 overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif cpuis("MKL13*")||cpuis("MKL17Z32*")||cpuis("MKL17Z64*")||cpuis("MKL27Z32*")||cpuis("MKL27Z64*")||cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" "Disabled,,LPUART0 rx,LPUART0 tx,LPUART1 rx,LPUART1 tx,UART2 rx,UART2 tx,,,Flex_io ch_0,Flex_io ch_1,Flex_io ch_2,Flex_io ch_3,,,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,,,I2C0,I2C1,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,TMP2 ch_0,TMP2 ch_1,,,,,ADC0,,CMP0,,,,,,,Port control A,Port control B,Port control C,Port control D,Port control E,TMP0 overflow,TMP1 overflow,TMP2 overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif cpuis("MKL82*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" "Disabled,Flex_io sh_0,Flex_io sh_1,Flex_io sh_2,Flex_io sh_3,Flex_io sh_4,Flex_io sh_5,Flex_io sh_6,Flex_io sh_7,I2C0,I2C1,,,,,LPUART0 rx,LPUART0 tx,LPUART1 rx,LPUART1 tx,LPUART2 rx,LPUART2 tx,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,QSPI0 rx,QSPI0 tx,TPM0 ch_0,TPM0 ch_1,TPM0 ch_2,TPM0 ch_3,TPM0 ch_4,TPM0 ch_5,,,TPM0 overflow,TPM1 ch_0,TPM1 ch_1,TPM1 overflow,TPM2 ch_0,TPM2 ch_1,TPM2 overflow,TSI0,EMVSIM0 rx,EMVSIM0 tx,EMVSIM1 rx,EMVSIM1 tx,PortA,PortB,PortC,PortD,PortE,ADC0,,DAC0,LTC0 RAM,CMP0,,LTC0 Input,LTC0 Output,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
endif
|
|
group.byte 0x2++0x00
|
|
line.byte 0x00 "CHCFG_2,Channel Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 2 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA channel 2 trigger enable" "Disabled,Enabled"
|
|
sif cpuis("MKL25Z*")||cpuis("MKL15Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" "Disabled,,UART0 rx,UART0 tx,UART1 rx,UART1 tx,UART2 rx,UART2 tx,,,,,,,,,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,,,I2C0,I2C1,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,TMP2 ch_0,TMP2 ch_1,,,,,ADC0,,CMP0,,,DAC0,,,,Port control A,,,Port control D,,TMP0 overflow,TMP1 overflow,TMP2 overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif cpuis("MKL34Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" "Disabled,,UART0 rx,UART0 tx,UART1 rx,UART1 tx,UART2 rx,UART2 tx,,,,,,,,,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,,,I2C0,I2C1,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,TMP2 ch_0,TMP2 ch_1,,,,,ADC0,,CMP0,,,DAC0,,,,Port control A,,Port control C,Port control D,,TMP0 overflow,TMP1 overflow,TMP2 overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif cpuis("MKL36Z*")||cpuis("MKL46Z*")||cpuis("MKL16*")||cpuis("MKL26*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" "Disabled,,UART0 rx,UART0 tx,UART1 rx,UART1 tx,UART2 rx,UART2 tx,,,,,,,I2S0 rx,I2S0 tx,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,,,I2C0,I2C1,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,TMP2 ch_0,TMP2 ch_1,,,,,ADC0,,CMP0,,,DAC0,,,,Port control A,,Port control C,Port control D,,TMP0 overflow,TMP1 overflow,TMP2 overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif cpuis("MKL24Z*")||cpuis("MKL14Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" "Disabled,,UART0 rx,UART0 tx,UART1 rx,UART1 tx,UART2 rx,UART2 tx,,,,,,,,,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,,,I2C0,I2C1,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,TMP2 ch_0,TMP2 ch_1,,,,,ADC0,,CMP0,,,,,,,Port control A,,,Port control D,,TMP0 overflow,TMP1 overflow,TMP2 overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif cpuis("MKL05Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" "Disabled,,UART0 rx,UART0 tx,,,,,,,,,,,,,SPI0 rx,SPI0 tx,,,,,I2C0,,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,,,,,,,ADC0,,CMP0,,,DAC0,,,,Port control A,Port control B,,,,TMP0 overflow,TMP1 overflow,,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif cpuis("MKL04Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" "Disabled,,UART0 rx,UART0 tx,,,,,,,,,,,,,SPI0 rx,SPI0 tx,,,,,I2C0,,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,,,,,,,ADC0,,CMP0,,,,,,,Port control A,Port control B,,,,TMP0 overflow,TMP1 overflow,,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL27Z128*")||cpuis("MKL27Z256*")||cpuis("MKL33Z128*")||cpuis("MKL33Z256*")||cpuis("MKL43Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" "Disabled,,LPUART0 rx,LPUART0 tx,LPUART1 rx,LPUART1 tx,UART2 rx,UART2 tx,,,Flex_io ch_0,Flex_io ch_1,Flex_io ch_2,Flex_io ch_3,I2S0 rx,I2S0 tx,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,,,I2C0,I2C1,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,TMP2 ch_0,TMP2 ch_1,,,,,ADC0,,CMP0,,,DAC0,,,,Port control A,,Port control C,Port control D,,TMP0 overflow,TMP1 overflow,TMP2 overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif cpuis("MKL13*")||cpuis("MKL17Z32*")||cpuis("MKL17Z64*")||cpuis("MKL27Z32*")||cpuis("MKL27Z64*")||cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" "Disabled,,LPUART0 rx,LPUART0 tx,LPUART1 rx,LPUART1 tx,UART2 rx,UART2 tx,,,Flex_io ch_0,Flex_io ch_1,Flex_io ch_2,Flex_io ch_3,,,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,,,I2C0,I2C1,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,TMP2 ch_0,TMP2 ch_1,,,,,ADC0,,CMP0,,,,,,,Port control A,Port control B,Port control C,Port control D,Port control E,TMP0 overflow,TMP1 overflow,TMP2 overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif cpuis("MKL82*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" "Disabled,Flex_io sh_0,Flex_io sh_1,Flex_io sh_2,Flex_io sh_3,Flex_io sh_4,Flex_io sh_5,Flex_io sh_6,Flex_io sh_7,I2C0,I2C1,,,,,LPUART0 rx,LPUART0 tx,LPUART1 rx,LPUART1 tx,LPUART2 rx,LPUART2 tx,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,QSPI0 rx,QSPI0 tx,TPM0 ch_0,TPM0 ch_1,TPM0 ch_2,TPM0 ch_3,TPM0 ch_4,TPM0 ch_5,,,TPM0 overflow,TPM1 ch_0,TPM1 ch_1,TPM1 overflow,TPM2 ch_0,TPM2 ch_1,TPM2 overflow,TSI0,EMVSIM0 rx,EMVSIM0 tx,EMVSIM1 rx,EMVSIM1 tx,PortA,PortB,PortC,PortD,PortE,ADC0,,DAC0,LTC0 RAM,CMP0,,LTC0 Input,LTC0 Output,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
endif
|
|
group.byte 0x3++0x00
|
|
line.byte 0x00 "CHCFG_3,Channel Configuration Register"
|
|
bitfld.byte 0x00 7. " ENBL ,DMA channel 3 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TRIG ,DMA channel 3 trigger enable" "Disabled,Enabled"
|
|
sif cpuis("MKL25Z*")||cpuis("MKL15Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" "Disabled,,UART0 rx,UART0 tx,UART1 rx,UART1 tx,UART2 rx,UART2 tx,,,,,,,,,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,,,I2C0,I2C1,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,TMP2 ch_0,TMP2 ch_1,,,,,ADC0,,CMP0,,,DAC0,,,,Port control A,,,Port control D,,TMP0 overflow,TMP1 overflow,TMP2 overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif cpuis("MKL34Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" "Disabled,,UART0 rx,UART0 tx,UART1 rx,UART1 tx,UART2 rx,UART2 tx,,,,,,,,,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,,,I2C0,I2C1,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,TMP2 ch_0,TMP2 ch_1,,,,,ADC0,,CMP0,,,DAC0,,,,Port control A,,Port control C,Port control D,,TMP0 overflow,TMP1 overflow,TMP2 overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif cpuis("MKL36Z*")||cpuis("MKL46Z*")||cpuis("MKL16*")||cpuis("MKL26*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" "Disabled,,UART0 rx,UART0 tx,UART1 rx,UART1 tx,UART2 rx,UART2 tx,,,,,,,I2S0 rx,I2S0 tx,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,,,I2C0,I2C1,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,TMP2 ch_0,TMP2 ch_1,,,,,ADC0,,CMP0,,,DAC0,,,,Port control A,,Port control C,Port control D,,TMP0 overflow,TMP1 overflow,TMP2 overflow,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif cpuis("MKL24Z*")||cpuis("MKL14Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" "Disabled,,UART0 rx,UART0 tx,UART1 rx,UART1 tx,UART2 rx,UART2 tx,,,,,,,,,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,,,I2C0,I2C1,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,TMP2 ch_0,TMP2 ch_1,,,,,ADC0,,CMP0,,,,,,,Port control A,,,Port control D,,TMP0 overflow,TMP1 overflow,TMP2 overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif cpuis("MKL05Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" "Disabled,,UART0 rx,UART0 tx,,,,,,,,,,,,,SPI0 rx,SPI0 tx,,,,,I2C0,,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,,,,,,,ADC0,,CMP0,,,DAC0,,,,Port control A,Port control B,,,,TMP0 overflow,TMP1 overflow,,TSI,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif cpuis("MKL04Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" "Disabled,,UART0 rx,UART0 tx,,,,,,,,,,,,,SPI0 rx,SPI0 tx,,,,,I2C0,,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,,,,,,,ADC0,,CMP0,,,,,,,Port control A,Port control B,,,,TMP0 overflow,TMP1 overflow,,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL27Z128*")||cpuis("MKL27Z256*")||cpuis("MKL33Z128*")||cpuis("MKL33Z256*")||cpuis("MKL43Z*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" "Disabled,,LPUART0 rx,LPUART0 tx,LPUART1 rx,LPUART1 tx,UART2 rx,UART2 tx,,,Flex_io ch_0,Flex_io ch_1,Flex_io ch_2,Flex_io ch_3,I2S0 rx,I2S0 tx,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,,,I2C0,I2C1,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,TMP2 ch_0,TMP2 ch_1,,,,,ADC0,,CMP0,,,DAC0,,,,Port control A,,Port control C,Port control D,,TMP0 overflow,TMP1 overflow,TMP2 overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif cpuis("MKL13*")||cpuis("MKL17Z32*")||cpuis("MKL17Z64*")||cpuis("MKL27Z32*")||cpuis("MKL27Z64*")||cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" "Disabled,,LPUART0 rx,LPUART0 tx,LPUART1 rx,LPUART1 tx,UART2 rx,UART2 tx,,,Flex_io ch_0,Flex_io ch_1,Flex_io ch_2,Flex_io ch_3,,,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,,,I2C0,I2C1,TMP0 ch_0,TMP0 ch_1,TMP0 ch_2,TMP0 ch_3,TMP0 ch_4,TMP0 ch_5,,,TMP1 ch_0,TMP1 ch_1,TMP2 ch_0,TMP2 ch_1,,,,,ADC0,,CMP0,,,,,,,Port control A,Port control B,Port control C,Port control D,Port control E,TMP0 overflow,TMP1 overflow,TMP2 overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
elif cpuis("MKL82*")
|
|
bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" "Disabled,Flex_io sh_0,Flex_io sh_1,Flex_io sh_2,Flex_io sh_3,Flex_io sh_4,Flex_io sh_5,Flex_io sh_6,Flex_io sh_7,I2C0,I2C1,,,,,LPUART0 rx,LPUART0 tx,LPUART1 rx,LPUART1 tx,LPUART2 rx,LPUART2 tx,SPI0 rx,SPI0 tx,SPI1 rx,SPI1 tx,QSPI0 rx,QSPI0 tx,TPM0 ch_0,TPM0 ch_1,TPM0 ch_2,TPM0 ch_3,TPM0 ch_4,TPM0 ch_5,,,TPM0 overflow,TPM1 ch_0,TPM1 ch_1,TPM1 overflow,TPM2 ch_0,TPM2 ch_1,TPM2 overflow,TSI0,EMVSIM0 rx,EMVSIM0 tx,EMVSIM1 rx,EMVSIM1 tx,PortA,PortB,PortC,PortD,PortE,ADC0,,DAC0,LTC0 RAM,CMP0,,LTC0 Input,LTC0 Output,DMA MUX,DMA MUX,DMA MUX,DMA MUX"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("MKL28*")||cpuis("MKL82*")
|
|
tree "eDMA (Enhanced Direct Memory Access)"
|
|
base ad:0x40008000
|
|
tree "Edma Control And Status Registers"
|
|
width 6.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
rbitfld.long 0x00 31. " ACTIVE ,DMA active status" "Idle,Active"
|
|
bitfld.long 0x00 17. " CX ,Cancel transfer" "Not canceled,Canceled"
|
|
bitfld.long 0x00 16. " ECX ,Error cancel transfer" "Not canceled,Canceled"
|
|
bitfld.long 0x00 7. " EMLM ,Enable minor loop mapping" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLM ,Continuous link mode" "Through ch arbit.,Not through ch arbit."
|
|
bitfld.long 0x00 5. " HALT ,Halt DMA operations" "Not halted,Halted"
|
|
bitfld.long 0x00 4. " HOE ,Halt on error" "Not halted,Halted"
|
|
bitfld.long 0x00 2. " ERCA ,Enable round robin channel arbitration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EDBG ,Enable debug" "Disabled,Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ES,Error Status Register"
|
|
bitfld.long 0x00 31. " VLD ,Logical OR of all ERR status bits" "Not occurred,Occurred"
|
|
bitfld.long 0x00 16. " ECX ,Transfer cancelled" "Not cancelled,Cancelled"
|
|
bitfld.long 0x00 14. " CPE ,Channel priority error" "No error,Error"
|
|
sif cpuis("MKL28*")||cpuis("MKL82*")
|
|
bitfld.long 0x00 8.--10. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 8.--9. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " SAE ,Source address error" "No error,Error"
|
|
bitfld.long 0x00 6. " SOE ,Source offset error" "No error,Error"
|
|
bitfld.long 0x00 5. " DAE ,Destination address error" "No error,Error"
|
|
bitfld.long 0x00 4. " DOE ,Destination offset error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NCE ,NBYTES/CITER configuration error" "No error,Error"
|
|
bitfld.long 0x00 2. " SGE ,Scatter/gather configuration error" "No error,Error"
|
|
bitfld.long 0x00 1. " SBE ,Source bus error" "No error,Error"
|
|
bitfld.long 0x00 0. " DBE ,Destination bus error" "No error,Error"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ERQ,Enable Request Register"
|
|
sif cpuis("MKL28*")||cpuis("MKL82*")
|
|
bitfld.long 0x00 7. " ERQ7 ,Enable DMA request 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ERQ6 ,Enable DMA request 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ERQ5 ,Enable DMA request 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ERQ4 ,Enable DMA request 4" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " ERQ3 ,Enable DMA request 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ERQ2 ,Enable DMA request 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ERQ1 ,Enable DMA request 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ERQ0 ,Enable DMA request 0" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "EEI,Enable Error Interrupt Register"
|
|
sif cpuis("MKL28*")||cpuis("MKL82*")
|
|
bitfld.long 0x00 7. " EEI7 ,Enable error interrupt 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " EEI6 ,Enable error interrupt 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EEI5 ,Enable error interrupt 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " EEI4 ,Enable error interrupt 4" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " EEI3 ,Enable error interrupt 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EEI2 ,Enable error interrupt 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EEI1 ,Enable error interrupt 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EEI0 ,Enable error interrupt 0" "Disabled,Enabled"
|
|
textline " "
|
|
width 6.
|
|
wgroup.byte 0x18++0x07
|
|
line.byte 0x00 "CEEI,Clear Enable Error Interrupt Register"
|
|
bitfld.byte 0x00 7. " NOP ,No operation bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CAEE ,Clear all enable error interrupts" "CEEI only,All EEI"
|
|
sif cpuis("MKL28*")||cpuis("MKL82*")
|
|
bitfld.byte 0x00 2. " CEEI[2] ,Clear enable error interrupt 2 in EEI" "No effect,Clear"
|
|
endif
|
|
bitfld.byte 0x00 1. " CEEI[1] ,Clear enable error interrupt 1 in EEI" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " CEEI[0] ,Clear enable error interrupt 0 in EEI" "No effect,Clear"
|
|
line.byte 0x01 "SEEI,Set Enable Error Interrupt Register"
|
|
bitfld.byte 0x01 7. " NOP ,No operation bit" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " SAEE ,Sets all enable error interrupts" "SEEI only,All EEI"
|
|
sif cpuis("MKL28*")||cpuis("MKL82*")
|
|
bitfld.byte 0x01 2. " SEEI[2] ,Set enable error interrupt 2 in EEI" "No effect,Set"
|
|
endif
|
|
bitfld.byte 0x01 1. " SEEI[1] ,Set enable error interrupt 1 in EEI" "No effect,Set"
|
|
bitfld.byte 0x01 0. " SEEI[0] ,Set enable error interrupt 0 in EEI" "No effect,Set"
|
|
line.byte 0x02 "CERQ,Clear Enable Request Register"
|
|
bitfld.byte 0x02 7. " NOP ,No operation bit" "Disabled,Enabled"
|
|
bitfld.byte 0x02 6. " CAER ,Clear all enable requests" "CER only,ALL ER"
|
|
sif cpuis("MKL28*")||cpuis("MKL82*")
|
|
bitfld.byte 0x02 2. " CERQ[2] ,Clear enable request" "No effect,Clear"
|
|
endif
|
|
bitfld.byte 0x02 1. " CERQ[1] ,Clear enable request" "No effect,Clear"
|
|
bitfld.byte 0x02 0. " CERQ[0] ,Clear enable request" "No effect,Clear"
|
|
line.byte 0x03 "SERQ,Set Enable Request Register"
|
|
bitfld.byte 0x03 7. " NOP ,No operation bit" "Disabled,Enabled"
|
|
bitfld.byte 0x03 6. " SAER ,Set all enable requests" "SAER only,All ER"
|
|
sif cpuis("MKL28*")||cpuis("MKL82*")
|
|
bitfld.byte 0x03 2. " SERQ[2] ,Set enable request" "No effect,Set"
|
|
endif
|
|
bitfld.byte 0x03 1. " SERQ[1] ,Set enable request" "No effect,Set"
|
|
bitfld.byte 0x03 0. " SERQ[0] ,Set enable request" "No effect,Set"
|
|
line.byte 0x04 "CDNE,Clear DONE Status Bit Register"
|
|
bitfld.byte 0x04 7. " NOP ,No operation bit" "Disabled,Enabled"
|
|
bitfld.byte 0x04 6. " CADN ,Clear all DONE bits" "CADB only,All DB"
|
|
sif cpuis("MKL28*")||cpuis("MKL82*")
|
|
bitfld.byte 0x04 2. " CDNE[2] ,Clear DONE bit" "No effect,Clear"
|
|
endif
|
|
bitfld.byte 0x04 1. " CDNE[1] ,Clear DONE bit" "No effect,Clear"
|
|
bitfld.byte 0x04 0. " CDNE[0] ,Clear DONE bit" "No effect,Clear"
|
|
line.byte 0x05 "SSRT,Set START Bit Register"
|
|
bitfld.byte 0x05 7. " NOP ,No operation bit" "Disabled,Enabled"
|
|
bitfld.byte 0x05 6. " SAST ,Set all START bits" "SASB only,All SB"
|
|
sif cpuis("MKL28*")||cpuis("MKL82*")
|
|
bitfld.byte 0x05 2. " SSRT[2] ,Set START bit" "No effect,Clear"
|
|
endif
|
|
bitfld.byte 0x05 1. " SSRT[1] ,Set START bit" "No effect,Clear"
|
|
bitfld.byte 0x05 0. " SSRT[0] ,Set START bit" "No effect,Clear"
|
|
line.byte 0x06 "CERR,Clear Error Register"
|
|
bitfld.byte 0x06 7. " NOP ,No operation bit" "Disabled,Enabled"
|
|
bitfld.byte 0x06 6. " CAEI ,Clear all error indicators" "CAEI only,ALL EI"
|
|
sif cpuis("MKL28*")||cpuis("MKL82*")
|
|
bitfld.byte 0x06 2. " CERR[2] ,Clear error indicator" "No effect,Clear"
|
|
endif
|
|
bitfld.byte 0x06 1. " CERR[1] ,Clear error indicator" "No effect,Clear"
|
|
bitfld.byte 0x06 0. " CERR[0] ,Clear error indicator" "No effect,Clear"
|
|
line.byte 0x07 "CINT,Clear Interrupt Request Register"
|
|
bitfld.byte 0x07 7. " NOP ,No operation bit" "Disabled,Enabled"
|
|
bitfld.byte 0x07 6. " CAIR ,Clear all interrupt request" "CAIR only,All IR"
|
|
sif cpuis("MKL28*")||cpuis("MKL82*")
|
|
bitfld.byte 0x07 2. " CINT[2] ,Clear interrupt request" "No effect,Clear"
|
|
endif
|
|
bitfld.byte 0x07 1. " CINT[1] ,Clear interrupt request" "No effect,Clear"
|
|
bitfld.byte 0x07 0. " CINT[0] ,Clear interrupt request" "No effect,Clear"
|
|
textline " "
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "INT,Interrupt Request Register"
|
|
sif cpuis("MKL28*")||cpuis("MKL82*")
|
|
eventfld.long 0x00 7. " INT7 ,Interrupt request 7" "Not requested,Requested"
|
|
eventfld.long 0x00 6. " INT6 ,Interrupt request 6" "Not requested,Requested"
|
|
eventfld.long 0x00 5. " INT5 ,Interrupt request 5" "Not requested,Requested"
|
|
eventfld.long 0x00 4. " INT4 ,Interrupt request 4" "Not requested,Requested"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 3. " INT3 ,Interrupt request 3" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " INT2 ,Interrupt request 2" "Not requested,Requested"
|
|
eventfld.long 0x00 1. " INT1 ,Interrupt request 1" "Not requested,Requested"
|
|
eventfld.long 0x00 0. " INT0 ,Interrupt request 0" "Not requested,Requested"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ERR,Error Register"
|
|
sif cpuis("MKL28*")||cpuis("MKL82*")
|
|
eventfld.long 0x00 7. " ERR7 ,Error in channel 7" "No error,Error"
|
|
eventfld.long 0x00 6. " ERR6 ,Error in channel 6" "No error,Error"
|
|
eventfld.long 0x00 5. " ERR5 ,Error in channel 5" "No error,Error"
|
|
eventfld.long 0x00 4. " ERR4 ,Error in channel 4" "No error,Error"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 3. " ERR3 ,Error in channel 3" "No error,Error"
|
|
eventfld.long 0x00 2. " ERR2 ,Error in channel 2" "No error,Error"
|
|
eventfld.long 0x00 1. " ERR1 ,Error in channel 1" "No error,Error"
|
|
eventfld.long 0x00 0. " ERR0 ,Error in channel 0" "No error,Error"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "HRS,Hardware Request Status Register"
|
|
sif cpuis("MKL28*")||cpuis("MKL82*")
|
|
bitfld.long 0x00 7. " HRS7 ,Hardware request status for channel 7" "Not present,Present"
|
|
bitfld.long 0x00 6. " HRS6 ,Hardware request status for channel 6" "Not present,Present"
|
|
bitfld.long 0x00 5. " HRS5 ,Hardware request status for channel 5" "Not present,Present"
|
|
bitfld.long 0x00 4. " HRS4 ,Hardware request status for channel 4" "Not present,Present"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " HRS3 ,Hardware request status for channel 3" "Not present,Present"
|
|
bitfld.long 0x00 2. " HRS2 ,Hardware request status for channel 2" "Not present,Present"
|
|
bitfld.long 0x00 1. " HRS1 ,Hardware request status for channel 1" "Not present,Present"
|
|
bitfld.long 0x00 0. " HRS0 ,Hardware request status for channel 0" "Not present,Present"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "EARS,Enable Asynchronous Request In Stop Register"
|
|
sif cpuis("MKL28*")||cpuis("MKL82*")
|
|
bitfld.long 0x00 7. " EDREQ_7 ,Enable asynchronous DMA request in stop for channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " EDREQ_6 ,Enable asynchronous DMA request in stop for channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EDREQ_5 ,Enable asynchronous DMA request in stop for channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " EDREQ_4 ,Enable asynchronous DMA request in stop for channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " EDREQ_3 ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EDREQ_2 ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EDREQ_1 ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EDREQ_0 ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled"
|
|
tree.end
|
|
tree "DMA Channel Priority Registers"
|
|
width 11.
|
|
sif cpuis("MKL28*")||cpuis("MKL82*")
|
|
group.byte (0x0+0x100)++0x00
|
|
line.byte 0x00 "DCHPRI_3,Channel 3 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--2. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,3,4,5,6,Highest"
|
|
group.byte (0x1+0x100)++0x00
|
|
line.byte 0x00 "DCHPRI_2,Channel 2 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--2. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,3,4,5,6,Highest"
|
|
group.byte (0x2+0x100)++0x00
|
|
line.byte 0x00 "DCHPRI_1,Channel 1 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--2. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,3,4,5,6,Highest"
|
|
group.byte (0x3+0x100)++0x00
|
|
line.byte 0x00 "DCHPRI_0,Channel 0 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--2. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,3,4,5,6,Highest"
|
|
group.byte (0x4+0x100)++0x00
|
|
line.byte 0x00 "DCHPRI_7,Channel 7 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 7 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 7 preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--2. " CHPRI ,Channel 7 arbitration priority" "Lowest,1,2,3,4,5,6,Highest"
|
|
group.byte (0x5+0x100)++0x00
|
|
line.byte 0x00 "DCHPRI_6,Channel 6 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 6 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 6 preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--2. " CHPRI ,Channel 6 arbitration priority" "Lowest,1,2,3,4,5,6,Highest"
|
|
group.byte (0x6+0x100)++0x00
|
|
line.byte 0x00 "DCHPRI_5,Channel 5 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 5 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 5 preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--2. " CHPRI ,Channel 5 arbitration priority" "Lowest,1,2,3,4,5,6,Highest"
|
|
group.byte (0x7+0x100)++0x00
|
|
line.byte 0x00 "DCHPRI_4,Channel 4 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 4 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 4 preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--2. " CHPRI ,Channel 4 arbitration priority" "Lowest,1,2,3,4,5,6,Highest"
|
|
else
|
|
group.byte (0x0+0x100)++0x00
|
|
line.byte 0x00 "DCHPRI_3,Channel 3 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--1. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,Highest"
|
|
group.byte (0x1+0x100)++0x00
|
|
line.byte 0x00 "DCHPRI_2,Channel 2 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--1. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,Highest"
|
|
group.byte (0x2+0x100)++0x00
|
|
line.byte 0x00 "DCHPRI_1,Channel 1 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--1. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,Highest"
|
|
group.byte (0x3+0x100)++0x00
|
|
line.byte 0x00 "DCHPRI_0,Channel 0 Priority Register"
|
|
bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes"
|
|
bitfld.byte 0x00 0.--1. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,Highest"
|
|
endif
|
|
tree.end
|
|
base ad:0x40009000
|
|
tree.open "Transfer Control Descriptor Registers"
|
|
sif cpuis("MKL28*")||cpuis("MKL82*")
|
|
tree "Channel 0"
|
|
width 13.
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "TCD0_SADDR,TCD Source Address"
|
|
group.word (0x0+0x04)++0x03
|
|
line.word 0x00 "TCD0_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD0_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
width 23.
|
|
if (((per.l(ad:0x40008000))&0x80)==0x00)
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif (((per.l(ad:0x40009000+(0x0+0x08)))&0xc0000000)==0x0)
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x0+0x0C)++0x07
|
|
line.long 0x00 "TCD0_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD0_DADDR,TCD Destination Address"
|
|
group.word (0x0+0x14)++0x01
|
|
line.word 0x00 "TCD0_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x0+0x16)))&0x8000)==0x0)
|
|
group.word (0x0+0x16)++0x01
|
|
line.word 0x00 "TCD0_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x0+0x16)++0x01
|
|
line.word 0x00 "TCD0_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x0+0x18)++0x03
|
|
line.long 0x00 "TCD0_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
if (((per.l(ad:0x40009000+(0x0+0x1C)))&0x80)==0x80)
|
|
group.word (0x0+0x1C)++0x01
|
|
line.word 0x00 "TCD0_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No edma stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
else
|
|
group.word (0x0+0x1C)++0x01
|
|
line.word 0x00 "TCD0_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No edma stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
endif
|
|
if (((per.l(ad:0x40009000+(0x0+0x1E)))&0x8000)==0x0)
|
|
group.word (0x0+0x1E)++0x01
|
|
line.word 0x00 "TCD0_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x0+0x1E)++0x01
|
|
line.word 0x00 "TCD0_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 1"
|
|
width 13.
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TCD1_SADDR,TCD Source Address"
|
|
group.word (0x20+0x04)++0x03
|
|
line.word 0x00 "TCD1_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD1_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
width 23.
|
|
if (((per.l(ad:0x40008000))&0x80)==0x00)
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif (((per.l(ad:0x40009000+(0x20+0x08)))&0xc0000000)==0x0)
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x20+0x0C)++0x07
|
|
line.long 0x00 "TCD1_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD1_DADDR,TCD Destination Address"
|
|
group.word (0x20+0x14)++0x01
|
|
line.word 0x00 "TCD1_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x20+0x16)))&0x8000)==0x0)
|
|
group.word (0x20+0x16)++0x01
|
|
line.word 0x00 "TCD1_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x20+0x16)++0x01
|
|
line.word 0x00 "TCD1_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x20+0x18)++0x03
|
|
line.long 0x00 "TCD1_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
if (((per.l(ad:0x40009000+(0x20+0x1C)))&0x80)==0x80)
|
|
group.word (0x20+0x1C)++0x01
|
|
line.word 0x00 "TCD1_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No edma stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
else
|
|
group.word (0x20+0x1C)++0x01
|
|
line.word 0x00 "TCD1_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No edma stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
endif
|
|
if (((per.l(ad:0x40009000+(0x20+0x1E)))&0x8000)==0x0)
|
|
group.word (0x20+0x1E)++0x01
|
|
line.word 0x00 "TCD1_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x20+0x1E)++0x01
|
|
line.word 0x00 "TCD1_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 2"
|
|
width 13.
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TCD2_SADDR,TCD Source Address"
|
|
group.word (0x40+0x04)++0x03
|
|
line.word 0x00 "TCD2_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD2_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
width 23.
|
|
if (((per.l(ad:0x40008000))&0x80)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif (((per.l(ad:0x40009000+(0x40+0x08)))&0xc0000000)==0x0)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x40+0x0C)++0x07
|
|
line.long 0x00 "TCD2_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD2_DADDR,TCD Destination Address"
|
|
group.word (0x40+0x14)++0x01
|
|
line.word 0x00 "TCD2_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x40+0x16)))&0x8000)==0x0)
|
|
group.word (0x40+0x16)++0x01
|
|
line.word 0x00 "TCD2_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x40+0x16)++0x01
|
|
line.word 0x00 "TCD2_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x40+0x18)++0x03
|
|
line.long 0x00 "TCD2_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
if (((per.l(ad:0x40009000+(0x40+0x1C)))&0x80)==0x80)
|
|
group.word (0x40+0x1C)++0x01
|
|
line.word 0x00 "TCD2_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No edma stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
else
|
|
group.word (0x40+0x1C)++0x01
|
|
line.word 0x00 "TCD2_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No edma stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
endif
|
|
if (((per.l(ad:0x40009000+(0x40+0x1E)))&0x8000)==0x0)
|
|
group.word (0x40+0x1E)++0x01
|
|
line.word 0x00 "TCD2_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x40+0x1E)++0x01
|
|
line.word 0x00 "TCD2_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 3"
|
|
width 13.
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TCD3_SADDR,TCD Source Address"
|
|
group.word (0x60+0x04)++0x03
|
|
line.word 0x00 "TCD3_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD3_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
width 23.
|
|
if (((per.l(ad:0x40008000))&0x80)==0x00)
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif (((per.l(ad:0x40009000+(0x60+0x08)))&0xc0000000)==0x0)
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x60+0x0C)++0x07
|
|
line.long 0x00 "TCD3_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD3_DADDR,TCD Destination Address"
|
|
group.word (0x60+0x14)++0x01
|
|
line.word 0x00 "TCD3_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x60+0x16)))&0x8000)==0x0)
|
|
group.word (0x60+0x16)++0x01
|
|
line.word 0x00 "TCD3_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x60+0x16)++0x01
|
|
line.word 0x00 "TCD3_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x60+0x18)++0x03
|
|
line.long 0x00 "TCD3_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
if (((per.l(ad:0x40009000+(0x60+0x1C)))&0x80)==0x80)
|
|
group.word (0x60+0x1C)++0x01
|
|
line.word 0x00 "TCD3_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No edma stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
else
|
|
group.word (0x60+0x1C)++0x01
|
|
line.word 0x00 "TCD3_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No edma stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
endif
|
|
if (((per.l(ad:0x40009000+(0x60+0x1E)))&0x8000)==0x0)
|
|
group.word (0x60+0x1E)++0x01
|
|
line.word 0x00 "TCD3_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x60+0x1E)++0x01
|
|
line.word 0x00 "TCD3_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 4"
|
|
width 13.
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TCD4_SADDR,TCD Source Address"
|
|
group.word (0x80+0x04)++0x03
|
|
line.word 0x00 "TCD4_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD4_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
width 23.
|
|
if (((per.l(ad:0x40008000))&0x80)==0x00)
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif (((per.l(ad:0x40009000+(0x80+0x08)))&0xc0000000)==0x0)
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x80+0x0C)++0x07
|
|
line.long 0x00 "TCD4_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD4_DADDR,TCD Destination Address"
|
|
group.word (0x80+0x14)++0x01
|
|
line.word 0x00 "TCD4_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x80+0x16)))&0x8000)==0x0)
|
|
group.word (0x80+0x16)++0x01
|
|
line.word 0x00 "TCD4_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x80+0x16)++0x01
|
|
line.word 0x00 "TCD4_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x80+0x18)++0x03
|
|
line.long 0x00 "TCD4_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
if (((per.l(ad:0x40009000+(0x80+0x1C)))&0x80)==0x80)
|
|
group.word (0x80+0x1C)++0x01
|
|
line.word 0x00 "TCD4_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No edma stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
else
|
|
group.word (0x80+0x1C)++0x01
|
|
line.word 0x00 "TCD4_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No edma stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
endif
|
|
if (((per.l(ad:0x40009000+(0x80+0x1E)))&0x8000)==0x0)
|
|
group.word (0x80+0x1E)++0x01
|
|
line.word 0x00 "TCD4_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x80+0x1E)++0x01
|
|
line.word 0x00 "TCD4_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 5"
|
|
width 13.
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "TCD5_SADDR,TCD Source Address"
|
|
group.word (0xA0+0x04)++0x03
|
|
line.word 0x00 "TCD5_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD5_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
width 23.
|
|
if (((per.l(ad:0x40008000))&0x80)==0x00)
|
|
group.long (0xA0+0x08)++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif (((per.l(ad:0x40009000+(0xA0+0x08)))&0xc0000000)==0x0)
|
|
group.long (0xA0+0x08)++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0xA0+0x08)++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0xA0+0x0C)++0x07
|
|
line.long 0x00 "TCD5_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD5_DADDR,TCD Destination Address"
|
|
group.word (0xA0+0x14)++0x01
|
|
line.word 0x00 "TCD5_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0xA0+0x16)))&0x8000)==0x0)
|
|
group.word (0xA0+0x16)++0x01
|
|
line.word 0x00 "TCD5_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0xA0+0x16)++0x01
|
|
line.word 0x00 "TCD5_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0xA0+0x18)++0x03
|
|
line.long 0x00 "TCD5_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
if (((per.l(ad:0x40009000+(0xA0+0x1C)))&0x80)==0x80)
|
|
group.word (0xA0+0x1C)++0x01
|
|
line.word 0x00 "TCD5_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No edma stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
else
|
|
group.word (0xA0+0x1C)++0x01
|
|
line.word 0x00 "TCD5_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No edma stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
endif
|
|
if (((per.l(ad:0x40009000+(0xA0+0x1E)))&0x8000)==0x0)
|
|
group.word (0xA0+0x1E)++0x01
|
|
line.word 0x00 "TCD5_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0xA0+0x1E)++0x01
|
|
line.word 0x00 "TCD5_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 6"
|
|
width 13.
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "TCD6_SADDR,TCD Source Address"
|
|
group.word (0xC0+0x04)++0x03
|
|
line.word 0x00 "TCD6_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD6_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
width 23.
|
|
if (((per.l(ad:0x40008000))&0x80)==0x00)
|
|
group.long (0xC0+0x08)++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif (((per.l(ad:0x40009000+(0xC0+0x08)))&0xc0000000)==0x0)
|
|
group.long (0xC0+0x08)++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0xC0+0x08)++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0xC0+0x0C)++0x07
|
|
line.long 0x00 "TCD6_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD6_DADDR,TCD Destination Address"
|
|
group.word (0xC0+0x14)++0x01
|
|
line.word 0x00 "TCD6_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0xC0+0x16)))&0x8000)==0x0)
|
|
group.word (0xC0+0x16)++0x01
|
|
line.word 0x00 "TCD6_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0xC0+0x16)++0x01
|
|
line.word 0x00 "TCD6_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0xC0+0x18)++0x03
|
|
line.long 0x00 "TCD6_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
if (((per.l(ad:0x40009000+(0xC0+0x1C)))&0x80)==0x80)
|
|
group.word (0xC0+0x1C)++0x01
|
|
line.word 0x00 "TCD6_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No edma stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
else
|
|
group.word (0xC0+0x1C)++0x01
|
|
line.word 0x00 "TCD6_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No edma stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
endif
|
|
if (((per.l(ad:0x40009000+(0xC0+0x1E)))&0x8000)==0x0)
|
|
group.word (0xC0+0x1E)++0x01
|
|
line.word 0x00 "TCD6_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0xC0+0x1E)++0x01
|
|
line.word 0x00 "TCD6_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 7"
|
|
width 13.
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "TCD7_SADDR,TCD Source Address"
|
|
group.word (0xE0+0x04)++0x03
|
|
line.word 0x00 "TCD7_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD7_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
width 23.
|
|
if (((per.l(ad:0x40008000))&0x80)==0x00)
|
|
group.long (0xE0+0x08)++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif (((per.l(ad:0x40009000+(0xE0+0x08)))&0xc0000000)==0x0)
|
|
group.long (0xE0+0x08)++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0xE0+0x08)++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0xE0+0x0C)++0x07
|
|
line.long 0x00 "TCD7_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD7_DADDR,TCD Destination Address"
|
|
group.word (0xE0+0x14)++0x01
|
|
line.word 0x00 "TCD7_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0xE0+0x16)))&0x8000)==0x0)
|
|
group.word (0xE0+0x16)++0x01
|
|
line.word 0x00 "TCD7_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0xE0+0x16)++0x01
|
|
line.word 0x00 "TCD7_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0xE0+0x18)++0x03
|
|
line.long 0x00 "TCD7_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
if (((per.l(ad:0x40009000+(0xE0+0x1C)))&0x80)==0x80)
|
|
group.word (0xE0+0x1C)++0x01
|
|
line.word 0x00 "TCD7_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No edma stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
else
|
|
group.word (0xE0+0x1C)++0x01
|
|
line.word 0x00 "TCD7_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No edma stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
endif
|
|
if (((per.l(ad:0x40009000+(0xE0+0x1E)))&0x8000)==0x0)
|
|
group.word (0xE0+0x1E)++0x01
|
|
line.word 0x00 "TCD7_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0xE0+0x1E)++0x01
|
|
line.word 0x00 "TCD7_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
else
|
|
tree "Channel 0"
|
|
width 13.
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "TCD0_SADDR,TCD Source Address"
|
|
group.word (0x0+0x04)++0x03
|
|
line.word 0x00 "TCD0_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD0_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
width 23.
|
|
if (((per.l(ad:0x40008000))&0x80)==0x00)
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif (((per.l(ad:0x40009000+(0x0+0x08)))&0xc0000000)==0x0)
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x0+0x0C)++0x07
|
|
line.long 0x00 "TCD0_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD0_DADDR,TCD Destination Address"
|
|
group.word (0x0+0x14)++0x01
|
|
line.word 0x00 "TCD0_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x0+0x16)))&0x8000)==0x0)
|
|
group.word (0x0+0x16)++0x01
|
|
line.word 0x00 "TCD0_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x0+0x16)++0x01
|
|
line.word 0x00 "TCD0_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x0+0x18)++0x03
|
|
line.long 0x00 "TCD0_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
group.word (0x0+0x1C)++0x01
|
|
line.word 0x00 "TCD0_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No edma stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x0+0x1E)))&0x8000)==0x0)
|
|
group.word (0x0+0x1E)++0x01
|
|
line.word 0x00 "TCD0_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x0+0x1E)++0x01
|
|
line.word 0x00 "TCD0_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 1"
|
|
width 13.
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TCD1_SADDR,TCD Source Address"
|
|
group.word (0x20+0x04)++0x03
|
|
line.word 0x00 "TCD1_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD1_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
width 23.
|
|
if (((per.l(ad:0x40008000))&0x80)==0x00)
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif (((per.l(ad:0x40009000+(0x20+0x08)))&0xc0000000)==0x0)
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x20+0x0C)++0x07
|
|
line.long 0x00 "TCD1_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD1_DADDR,TCD Destination Address"
|
|
group.word (0x20+0x14)++0x01
|
|
line.word 0x00 "TCD1_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x20+0x16)))&0x8000)==0x0)
|
|
group.word (0x20+0x16)++0x01
|
|
line.word 0x00 "TCD1_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x20+0x16)++0x01
|
|
line.word 0x00 "TCD1_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x20+0x18)++0x03
|
|
line.long 0x00 "TCD1_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
group.word (0x20+0x1C)++0x01
|
|
line.word 0x00 "TCD1_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No edma stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x20+0x1E)))&0x8000)==0x0)
|
|
group.word (0x20+0x1E)++0x01
|
|
line.word 0x00 "TCD1_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x20+0x1E)++0x01
|
|
line.word 0x00 "TCD1_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 2"
|
|
width 13.
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TCD2_SADDR,TCD Source Address"
|
|
group.word (0x40+0x04)++0x03
|
|
line.word 0x00 "TCD2_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD2_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
width 23.
|
|
if (((per.l(ad:0x40008000))&0x80)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif (((per.l(ad:0x40009000+(0x40+0x08)))&0xc0000000)==0x0)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x40+0x0C)++0x07
|
|
line.long 0x00 "TCD2_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD2_DADDR,TCD Destination Address"
|
|
group.word (0x40+0x14)++0x01
|
|
line.word 0x00 "TCD2_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x40+0x16)))&0x8000)==0x0)
|
|
group.word (0x40+0x16)++0x01
|
|
line.word 0x00 "TCD2_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x40+0x16)++0x01
|
|
line.word 0x00 "TCD2_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x40+0x18)++0x03
|
|
line.long 0x00 "TCD2_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
group.word (0x40+0x1C)++0x01
|
|
line.word 0x00 "TCD2_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No edma stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x40+0x1E)))&0x8000)==0x0)
|
|
group.word (0x40+0x1E)++0x01
|
|
line.word 0x00 "TCD2_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x40+0x1E)++0x01
|
|
line.word 0x00 "TCD2_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
tree "Channel 3"
|
|
width 13.
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TCD3_SADDR,TCD Source Address"
|
|
group.word (0x60+0x04)++0x03
|
|
line.word 0x00 "TCD3_SOFF,TCD Signed Source Address Offset Register"
|
|
line.word 0x02 "TCD3_ATTR,TCD Transfer Attributes Register"
|
|
bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..."
|
|
textline " "
|
|
width 23.
|
|
if (((per.l(ad:0x40008000))&0x80)==0x00)
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLNO,TCD Minor Byte Count"
|
|
elif (((per.l(ad:0x40009000+(0x60+0x08)))&0xc0000000)==0x0)
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count"
|
|
else
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset"
|
|
bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/destination address"
|
|
hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count"
|
|
endif
|
|
group.long (0x60+0x0C)++0x07
|
|
line.long 0x00 "TCD3_SLAST,TCD Last Source Address Adjustment"
|
|
line.long 0x04 "TCD3_DADDR,TCD Destination Address"
|
|
group.word (0x60+0x14)++0x01
|
|
line.word 0x00 "TCD3_DOFF,TCD Signed Destination Address Offset"
|
|
if (((per.l(ad:0x40009000+(0x60+0x16)))&0x8000)==0x0)
|
|
group.word (0x60+0x16)++0x01
|
|
line.word 0x00 "TCD3_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count"
|
|
else
|
|
group.word (0x60+0x16)++0x01
|
|
line.word 0x00 "TCD3_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count"
|
|
endif
|
|
group.long (0x60+0x18)++0x03
|
|
line.long 0x00 "TCD3_DLASTSGA,TCD Last Destination Address Adjustment/scatter Gather Address"
|
|
group.word (0x60+0x1C)++0x01
|
|
line.word 0x00 "TCD3_CSR,TCD Control And Status"
|
|
bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No edma stalls,,Stalls for 4 cycles,Stalls for 8 cycles"
|
|
bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3"
|
|
bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active"
|
|
bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes"
|
|
bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " START ,Channel start" "Not started,Started"
|
|
if (((per.l(ad:0x40009000+(0x60+0x1E)))&0x8000)==0x0)
|
|
group.word (0x60+0x1E)++0x01
|
|
line.word 0x00 "TCD3_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count"
|
|
else
|
|
group.word (0x60+0x1E)++0x01
|
|
line.word 0x00 "TCD3_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)"
|
|
bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3"
|
|
hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count"
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "DMA (Direct Memory Access Controller Module)"
|
|
base ad:0x40008000
|
|
width 6.
|
|
sif cpuis("MK14L*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "REQC,DMA Request Control Register"
|
|
bitfld.long 0x00 31. " CFSM0 ,Clear state machine control 0" "No effect,Clear"
|
|
bitfld.long 0x00 24.--27. " DMAC0 ,DMA channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " CFSM1 ,Clear state machine control 1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DMAC1 ,DMA channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " CFSM2 ,Clear state machine control 2" "No effect,Clear"
|
|
bitfld.long 0x00 8.--11. " DMAC2 ,DMA channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CFSM3 ,Clear state machine control 3" "No effect,Clear"
|
|
bitfld.long 0x00 0.--3. " DMAC3 ,DMA channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
width 12.
|
|
tree "Channel_0"
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "SAR_0,Source Address Register 0"
|
|
line.long 0x04 "DAR_0,Destination Address Register 0"
|
|
line.long 0x08 "DSR_BCR_0,DMA Status Register/byte Count Register 0"
|
|
rbitfld.long 0x08 30. " CE ,Configuration error" "Not occurred,Occurred"
|
|
rbitfld.long 0x08 29. " BES ,Bus error on source" "Not occurred,Occurred"
|
|
rbitfld.long 0x08 28. " BED ,Bus error on destination" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x08 26. " REQ ,Request" "Not requested,Requested"
|
|
rbitfld.long 0x08 25. " BSY ,Busy" "Not busy,Busy"
|
|
eventfld.long 0x08 24. " DONE ,Transactions done" "Not completed,Completed"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " BCR ,Number of bytes yet to be transferred for a given block"
|
|
line.long 0x0C "DCR_0,DMA Control Register 0"
|
|
bitfld.long 0x0C 31. " EINT ,Enable interrupt on completion of transfer" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " ERQ ,Enable peripheral request" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " CS ,Cycle steal" "Continuous r/w,Single r/w"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " AA ,Auto-align" "Disabled,Enabled"
|
|
bitfld.long 0x0C 23. " EADREQ ,Enable asynchronous DMA requests" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " SINC ,Source increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x0C 20.--21. " SSIZE ,Source size" "32-bit,8-bit,16-bit,?..."
|
|
bitfld.long 0x0C 19. " DINC ,Destination increment" "Not incremented,Incremented"
|
|
bitfld.long 0x0C 17.--18. " DSIZE ,Destination size" "32-bit,8-bit,16-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 16. " START ,Start transfer" "Not started,Started"
|
|
bitfld.long 0x0C 12.--15. " SMOD ,Size of the source data circular buffer" "Disabled,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1 KB,2 KB,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB"
|
|
bitfld.long 0x0C 8.--11. " DMOD ,Size of the destination data circular buffer" "Disabled,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1 KB,2 KB,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " D_REQ ,Disable request" "No,Yes"
|
|
bitfld.long 0x0C 4.--5. " LINKCC ,Link channel control" "No channel,LCH1 after each cycle-steal transfer,LCH1 after each cycle-steal transfer,LCH1 after the BCR decrements to zero"
|
|
textline " "
|
|
bitfld.long 0x0C 2.--3. " LCH1 ,Link channel 1" "Channel 0,Channel 1,Channel 2,Channel 3"
|
|
bitfld.long 0x0C 0.--1. " LCH2 ,Link channel 2" "Channel 0,Channel 1,Channel 2,Channel 3"
|
|
tree.end
|
|
tree "Channel_1"
|
|
group.long 0x110++0x0F
|
|
line.long 0x00 "SAR_1,Source Address Register 1"
|
|
line.long 0x04 "DAR_1,Destination Address Register 1"
|
|
line.long 0x08 "DSR_BCR_1,DMA Status Register/byte Count Register 1"
|
|
rbitfld.long 0x08 30. " CE ,Configuration error" "Not occurred,Occurred"
|
|
rbitfld.long 0x08 29. " BES ,Bus error on source" "Not occurred,Occurred"
|
|
rbitfld.long 0x08 28. " BED ,Bus error on destination" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x08 26. " REQ ,Request" "Not requested,Requested"
|
|
rbitfld.long 0x08 25. " BSY ,Busy" "Not busy,Busy"
|
|
eventfld.long 0x08 24. " DONE ,Transactions done" "Not completed,Completed"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " BCR ,Number of bytes yet to be transferred for a given block"
|
|
line.long 0x0C "DCR_1,DMA Control Register 1"
|
|
bitfld.long 0x0C 31. " EINT ,Enable interrupt on completion of transfer" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " ERQ ,Enable peripheral request" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " CS ,Cycle steal" "Continuous r/w,Single r/w"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " AA ,Auto-align" "Disabled,Enabled"
|
|
bitfld.long 0x0C 23. " EADREQ ,Enable asynchronous DMA requests" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " SINC ,Source increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x0C 20.--21. " SSIZE ,Source size" "32-bit,8-bit,16-bit,?..."
|
|
bitfld.long 0x0C 19. " DINC ,Destination increment" "Not incremented,Incremented"
|
|
bitfld.long 0x0C 17.--18. " DSIZE ,Destination size" "32-bit,8-bit,16-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 16. " START ,Start transfer" "Not started,Started"
|
|
bitfld.long 0x0C 12.--15. " SMOD ,Size of the source data circular buffer" "Disabled,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1 KB,2 KB,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB"
|
|
bitfld.long 0x0C 8.--11. " DMOD ,Size of the destination data circular buffer" "Disabled,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1 KB,2 KB,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " D_REQ ,Disable request" "No,Yes"
|
|
bitfld.long 0x0C 4.--5. " LINKCC ,Link channel control" "No channel,LCH1 after each cycle-steal transfer,LCH1 after each cycle-steal transfer,LCH1 after the BCR decrements to zero"
|
|
textline " "
|
|
bitfld.long 0x0C 2.--3. " LCH1 ,Link channel 1" "Channel 0,Channel 1,Channel 2,Channel 3"
|
|
bitfld.long 0x0C 0.--1. " LCH2 ,Link channel 2" "Channel 0,Channel 1,Channel 2,Channel 3"
|
|
tree.end
|
|
tree "Channel_2"
|
|
group.long 0x120++0x0F
|
|
line.long 0x00 "SAR_2,Source Address Register 2"
|
|
line.long 0x04 "DAR_2,Destination Address Register 2"
|
|
line.long 0x08 "DSR_BCR_2,DMA Status Register/byte Count Register 2"
|
|
rbitfld.long 0x08 30. " CE ,Configuration error" "Not occurred,Occurred"
|
|
rbitfld.long 0x08 29. " BES ,Bus error on source" "Not occurred,Occurred"
|
|
rbitfld.long 0x08 28. " BED ,Bus error on destination" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x08 26. " REQ ,Request" "Not requested,Requested"
|
|
rbitfld.long 0x08 25. " BSY ,Busy" "Not busy,Busy"
|
|
eventfld.long 0x08 24. " DONE ,Transactions done" "Not completed,Completed"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " BCR ,Number of bytes yet to be transferred for a given block"
|
|
line.long 0x0C "DCR_2,DMA Control Register 2"
|
|
bitfld.long 0x0C 31. " EINT ,Enable interrupt on completion of transfer" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " ERQ ,Enable peripheral request" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " CS ,Cycle steal" "Continuous r/w,Single r/w"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " AA ,Auto-align" "Disabled,Enabled"
|
|
bitfld.long 0x0C 23. " EADREQ ,Enable asynchronous DMA requests" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " SINC ,Source increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x0C 20.--21. " SSIZE ,Source size" "32-bit,8-bit,16-bit,?..."
|
|
bitfld.long 0x0C 19. " DINC ,Destination increment" "Not incremented,Incremented"
|
|
bitfld.long 0x0C 17.--18. " DSIZE ,Destination size" "32-bit,8-bit,16-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 16. " START ,Start transfer" "Not started,Started"
|
|
bitfld.long 0x0C 12.--15. " SMOD ,Size of the source data circular buffer" "Disabled,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1 KB,2 KB,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB"
|
|
bitfld.long 0x0C 8.--11. " DMOD ,Size of the destination data circular buffer" "Disabled,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1 KB,2 KB,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " D_REQ ,Disable request" "No,Yes"
|
|
bitfld.long 0x0C 4.--5. " LINKCC ,Link channel control" "No channel,LCH1 after each cycle-steal transfer,LCH1 after each cycle-steal transfer,LCH1 after the BCR decrements to zero"
|
|
textline " "
|
|
bitfld.long 0x0C 2.--3. " LCH1 ,Link channel 1" "Channel 0,Channel 1,Channel 2,Channel 3"
|
|
bitfld.long 0x0C 0.--1. " LCH2 ,Link channel 2" "Channel 0,Channel 1,Channel 2,Channel 3"
|
|
tree.end
|
|
tree "Channel_3"
|
|
group.long 0x130++0x0F
|
|
line.long 0x00 "SAR_3,Source Address Register 3"
|
|
line.long 0x04 "DAR_3,Destination Address Register 3"
|
|
line.long 0x08 "DSR_BCR_3,DMA Status Register/byte Count Register 3"
|
|
rbitfld.long 0x08 30. " CE ,Configuration error" "Not occurred,Occurred"
|
|
rbitfld.long 0x08 29. " BES ,Bus error on source" "Not occurred,Occurred"
|
|
rbitfld.long 0x08 28. " BED ,Bus error on destination" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x08 26. " REQ ,Request" "Not requested,Requested"
|
|
rbitfld.long 0x08 25. " BSY ,Busy" "Not busy,Busy"
|
|
eventfld.long 0x08 24. " DONE ,Transactions done" "Not completed,Completed"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " BCR ,Number of bytes yet to be transferred for a given block"
|
|
line.long 0x0C "DCR_3,DMA Control Register 3"
|
|
bitfld.long 0x0C 31. " EINT ,Enable interrupt on completion of transfer" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " ERQ ,Enable peripheral request" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " CS ,Cycle steal" "Continuous r/w,Single r/w"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " AA ,Auto-align" "Disabled,Enabled"
|
|
bitfld.long 0x0C 23. " EADREQ ,Enable asynchronous DMA requests" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " SINC ,Source increment" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0x0C 20.--21. " SSIZE ,Source size" "32-bit,8-bit,16-bit,?..."
|
|
bitfld.long 0x0C 19. " DINC ,Destination increment" "Not incremented,Incremented"
|
|
bitfld.long 0x0C 17.--18. " DSIZE ,Destination size" "32-bit,8-bit,16-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 16. " START ,Start transfer" "Not started,Started"
|
|
bitfld.long 0x0C 12.--15. " SMOD ,Size of the source data circular buffer" "Disabled,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1 KB,2 KB,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB"
|
|
bitfld.long 0x0C 8.--11. " DMOD ,Size of the destination data circular buffer" "Disabled,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1 KB,2 KB,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " D_REQ ,Disable request" "No,Yes"
|
|
bitfld.long 0x0C 4.--5. " LINKCC ,Link channel control" "No channel,LCH1 after each cycle-steal transfer,LCH1 after each cycle-steal transfer,LCH1 after the BCR decrements to zero"
|
|
textline " "
|
|
bitfld.long 0x0C 2.--3. " LCH1 ,Link channel 1" "Channel 0,Channel 1,Channel 2,Channel 3"
|
|
bitfld.long 0x0C 0.--1. " LCH2 ,Link channel 2" "Channel 0,Channel 1,Channel 2,Channel 3"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
endif
|
|
sif !cpuis("MKL28*")
|
|
tree "MCG (Multipurpose Clock Generator)"
|
|
base ad:0x40064000
|
|
width 7.
|
|
sif cpuis("MKL03Z*")||cpuis("MKL13Z*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")
|
|
if (((per.l(ad:0x40064000+0x01))&0x1)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "C1,MCG Control 1 Register"
|
|
bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "HIRC,LIRC_2M,EXT,?..."
|
|
bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "C1,MCG Control 1 Register"
|
|
bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "HIRC,LIRC_8M,EXT,?..."
|
|
bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("MKL13Z*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "C2,MCG Control 2 Register"
|
|
bitfld.byte 0x00 4.--5. " RANGE ,External clock source frequency range select" "Low freq.,High freq.,Very high freq.,Very high freq."
|
|
bitfld.byte 0x00 3. " HGO ,Crystal oscillator operation mode select" "Low power,High gain"
|
|
bitfld.byte 0x00 2. " EREFS ,External clock source select" "Ext. clk,Oscillator"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " IRCS ,Internal reference clock select" "2 mhz,8 mhz"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "C2,MCG Control 2 Register"
|
|
bitfld.byte 0x00 2. " EREFS ,External clock source select" "Ext. clk,Oscillator"
|
|
bitfld.byte 0x00 0. " IRCS ,Internal reference clock select" "2 mhz,8 mhz"
|
|
endif
|
|
rgroup.byte 0x06++0x00
|
|
line.byte 0x00 "S,MCG Status Register"
|
|
bitfld.byte 0x00 2.--3. " CLKST ,Clock mode status" "HIRC,LIRC,EXT,?..."
|
|
bitfld.byte 0x00 1. " OSCINIT ,OSC initialization status" "Not ready,Ready"
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "SC,MCG Status And Control Register"
|
|
bitfld.byte 0x00 1.--3. " FCIRDIV ,Low-frequency internal reference clock divider" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
sif cpuis("MKL13Z*")||cpuis("MKL17Z32*")||cpuis("MKL17Z64*")||cpuis("MKL27Z32*")||cpuis("MKL27Z64*")||cpuis("MKL33Z32*")||cpuis("MKL33Z64*")
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MC,MCG Miscellaneous Control Register"
|
|
bitfld.byte 0x00 7. " HIRCEN ,High-frequency IRC enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " HIRCLPEN ,High-frequency IRC low-power mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " LIRC_DIV2 ,Second low-frequency internal reference clock divider" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
else
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MC,MCG Miscellaneous Control Register"
|
|
bitfld.byte 0x00 7. " HIRCEN ,High-frequency IRC enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " LIRC_DIV2 ,Second low-frequency internal reference clock divider" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40064000+0x01))&0x30)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "C1,MCG Control 1 Register"
|
|
bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL/PLL,Internal ref clk,External ref clk,?..."
|
|
bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "C1,MCG Control 1 Register"
|
|
bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL/PLL,Internal ref clk,External ref clk,?..."
|
|
bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/32,/64,/128,/256,/512,/1024,/1280,/1536"
|
|
bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x01++0x01
|
|
line.byte 0x00 "C2,MCG Control 2 Register"
|
|
sif cpuis("MKL02*")||cpuis("MKL16*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")||cpuis("MKL82Z*")
|
|
bitfld.byte 0x00 7. " LOCRE ,Loss of clock reset enable" "Interrupt,Reset"
|
|
bitfld.byte 0x00 6. " FCFTRIM ,Fast internal reference clock fine trim" "Increased period,Decreased period"
|
|
bitfld.byte 0x00 4.--5. " RANGE ,Frequency range select" "32 khz - 40 khz,3 mhz - 8 mhz,8 mhz - 32 mhz,8 mhz - 32 mhz"
|
|
else
|
|
bitfld.byte 0x00 7. " LOCRE ,Loss of clock reset enable" "Interrupt,Reset"
|
|
bitfld.byte 0x00 4.--5. " RANGE ,Frequency range select" "32 khz - 40 khz,3 mhz - 8 mhz,8 mhz - 32 mhz,8 mhz - 32 mhz"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 3. " HGO ,High gain oscillator select" "Low-power,High-gain"
|
|
bitfld.byte 0x00 2. " EREFS ,External reference select" "Ext. clk,Oscillator"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LP ,Low power select" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " IRCS ,Internal reference clock select" "Slow,Fast"
|
|
line.byte 0x01 "C3,MCG Control 3 Register"
|
|
if (((per.l(ad:0x40064000+0x03))&0x60)==0x0)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "C4,MCG Control 4 Register"
|
|
bitfld.byte 0x00 7. " DMX32 ,DCO maximum frequency with 32.768 khz reference" "20 - 25 mhz,24 mhz"
|
|
bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range"
|
|
textline " "
|
|
bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Increased period,Decreased period"
|
|
elif (((per.l(ad:0x40064000+0x03))&0x60)==0x20)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "C4,MCG Control 4 Register"
|
|
bitfld.byte 0x00 7. " DMX32 ,DCO maximum frequency with 32.768 khz reference" "40 - 50 mhz,48 mhz"
|
|
bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range"
|
|
textline " "
|
|
bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Increased period,Decreased period"
|
|
elif (((per.l(ad:0x40064000+0x03))&0x60)==0x40)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "C4,MCG Control 4 Register"
|
|
bitfld.byte 0x00 7. " DMX32 ,DCO maximum frequency with 32.768 khz reference" "60 - 75 mhz,72 mhz"
|
|
bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range"
|
|
textline " "
|
|
bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Increased period,Decreased period"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "C4,MCG Control 4 Register"
|
|
bitfld.byte 0x00 7. " DMX32 ,DCO maximum frequency with 32.768 khz reference" "80 - 100 mhz,96 mhz"
|
|
bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range"
|
|
textline " "
|
|
bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Increased period,Decreased period"
|
|
endif
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL04*")&&!cpuis("MKL05*")
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "C5,MCG Control 5 Register"
|
|
bitfld.byte 0x00 6. " PLLCLKEN ,PLL clock enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " PLLSTEN ,PLL stop enable" "Disabled,Enabled"
|
|
sif cpuis("MKL82Z*")
|
|
bitfld.byte 0x00 0.--2. " PRDIV ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
else
|
|
bitfld.byte 0x00 0.--4. " PRDIV ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,?..."
|
|
endif
|
|
endif
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "C6,MCG Control 6 Register"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL04*")&&!cpuis("MKL05*")
|
|
bitfld.byte 0x00 7. " LOLIE ,Loss of lock interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " PLLS ,PLL select" "FLL,PLL"
|
|
bitfld.byte 0x00 5. " CME ,Clock monitor enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--4. " VDIV ,VCO divider" "/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55"
|
|
else
|
|
bitfld.byte 0x00 5. " CME ,Clock monitor enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.byte 0x06++0x00
|
|
line.byte 0x00 "S,MCG Status Register"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL04*")&&!cpuis("MKL05*")
|
|
bitfld.byte 0x00 7. " LOLS ,Loss of lock status" "Not lost,Lost"
|
|
bitfld.byte 0x00 6. " LOCK ,Lock status" "Not locked,Locked"
|
|
bitfld.byte 0x00 5. " PLLST ,PLL select status" "FLL,PLL"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " IREFST ,Internal reference status" "External,Internal"
|
|
bitfld.byte 0x00 2.--3. " CLKST ,Clock mode status" "Out FLL,Internal ref,External ref,Out PLL"
|
|
bitfld.byte 0x00 1. " OSCINIT ,OSC initialization" "Not completed,Completed"
|
|
else
|
|
bitfld.byte 0x00 4. " IREFST ,Internal reference status" "External,Internal"
|
|
bitfld.byte 0x00 2.--3. " CLKST ,Clock mode status" "Out FLL,Internal ref,External ref,?..."
|
|
bitfld.byte 0x00 1. " OSCINIT ,OSC initialization" "Not completed,Completed"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 0. " IRCST ,Internal reference clock status" "Slow clock,Fast clock"
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "SC,MCG Status And Control Register"
|
|
bitfld.byte 0x00 7. " ATME ,Automatic trim machine enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ATMS ,Automatic trim machine select" "32khz,4mhz"
|
|
sif cpuis("MKL82Z*")
|
|
eventfld.byte 0x00 5. " ATMF ,Automatic trim machine fail flag" "Not occurred,Occurred"
|
|
else
|
|
rbitfld.byte 0x00 5. " ATMF ,Automatic trim machine fail flag" "Not occurred,Occurred"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 4. " FLTPRSRV ,FLL filter preserve enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1.--3. " FCIRDIV ,Fast clock internal reference divider" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
sif cpuis("MKL82Z*")
|
|
eventfld.byte 0x00 0. " LOCS ,OSC0 loss of clock status" "Not occurred,Occurred"
|
|
else
|
|
rbitfld.byte 0x00 0. " LOCS ,OSC0 loss of clock status" "Not occurred,Occurred"
|
|
endif
|
|
group.byte 0x0A++0x01
|
|
line.byte 0x00 "ATCVH,MCG Auto Trim Compare Value High Register"
|
|
line.byte 0x01 "ATCVL,MCG Auto Trim Compare Value Low Register"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL04*")&&!cpuis("MKL05*")
|
|
sif cpuis("MKL16*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")||cpuis("MKL82Z*")
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "C7,MCG Control 7 Register"
|
|
bitfld.byte 0x00 0. " OSCSEL ,MCG OSC clock select" "OSCCLK,32khz RTC"
|
|
else
|
|
hgroup.byte 0x0C++0x00
|
|
hide.byte 0x00 "C7,MCG Control 7 Register"
|
|
endif
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "C8,MCG Control 8 Register"
|
|
bitfld.byte 0x00 6. " LOLRE ,PLL loss of lock reset enable" "Disabled,Enabled"
|
|
sif !cpuis("MKL82Z*")
|
|
hgroup.byte 0x0E++0x01
|
|
hide.byte 0x00 "C9,MCG Control 9 Register"
|
|
hide.byte 0x01 "C10,MCG Control 10 Register"
|
|
endif
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif !cpuis("MKL28*")
|
|
tree "OSC (Oscillator)"
|
|
base ad:0x40065000
|
|
width 4.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "CR,OSC Control Register"
|
|
bitfld.byte 0x00 7. " ERCLKEN ,External reference enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " EREFSTEN ,External reference stop enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SC_2P ,Oscillator 2 pF capacitor load configure" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " SC_4P ,Oscillator 4 pF capacitor load configure" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SC_8P ,Oscillator 8 pF capacitor load configure" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " SC_16P ,Oscillator 16 pF capacitor load configure" "Disabled,Enabled"
|
|
sif cpuis("MKL82Z*")
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "DIV,OSC Clock Divider Register"
|
|
bitfld.byte 0x00 6.--7. " ERPS ,ERCLK prescaler" "1,2,4,8"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree "FTFA (Flash Memory Module)"
|
|
base ad:0x40020000
|
|
width 10.
|
|
group.byte 0x00++0x01
|
|
line.byte 0x00 "FSTAT,Flash Status Register"
|
|
eventfld.byte 0x00 7. " CCIF ,Command complete interrupt flag" "Not completed,Completed"
|
|
eventfld.byte 0x00 6. " RDCOLERR ,FTFL read collision error flag" "No error,Error"
|
|
eventfld.byte 0x00 5. " ACCERR ,Flash access error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.byte 0x00 4. " FPVIOL ,Flash protection violation flag" "Not detected,Detected"
|
|
rbitfld.byte 0x00 0. " MGSTAT0 ,Memory controller command completion status flag" "No error,Error"
|
|
line.byte 0x01 "FCNFG,Flash Configuration Register"
|
|
bitfld.byte 0x01 7. " CCIE ,Command complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " RDCOLLIE ,Read collision error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x01 5. " ERSAREQ ,Erase all request" "Not erased,Erased"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " ERSSUSP ,Erase suspend" "Not suspended,Suspended"
|
|
rgroup.byte 0x02++0x01
|
|
line.byte 0x00 "FSEC,Flash Security Register"
|
|
bitfld.byte 0x00 6.--7. " KEYEN ,Backdoor key security enable" "Disabled,Disabled,Enabled,Disabled"
|
|
bitfld.byte 0x00 4.--5. " MEEN ,Mass erase enable bits" "Enabled,Enabled,Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. " FSLACC ,Freescale failure analysis access code" "Granted,Denied,Denied,Granted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " SEC ,Flash security" "Secured,Secured,Unsecured,Secured"
|
|
line.byte 0x01 "FOPT,Flash Option Register"
|
|
group.byte 0x4++0x00
|
|
line.byte 0x00 "FCCOB_3,Flash Common Command Object Registers"
|
|
group.byte 0x5++0x00
|
|
line.byte 0x00 "FCCOB_2,Flash Common Command Object Registers"
|
|
group.byte 0x6++0x00
|
|
line.byte 0x00 "FCCOB_1,Flash Common Command Object Registers"
|
|
group.byte 0x7++0x00
|
|
line.byte 0x00 "FCCOB_0,Flash Common Command Object Registers"
|
|
group.byte 0x8++0x00
|
|
line.byte 0x00 "FCCOB_7,Flash Common Command Object Registers"
|
|
group.byte 0x9++0x00
|
|
line.byte 0x00 "FCCOB_6,Flash Common Command Object Registers"
|
|
group.byte 0xA++0x00
|
|
line.byte 0x00 "FCCOB_5,Flash Common Command Object Registers"
|
|
group.byte 0xB++0x00
|
|
line.byte 0x00 "FCCOB_4,Flash Common Command Object Registers"
|
|
group.byte 0xC++0x00
|
|
line.byte 0x00 "FCCOB_B,Flash Common Command Object Registers"
|
|
group.byte 0xD++0x00
|
|
line.byte 0x00 "FCCOB_A,Flash Common Command Object Registers"
|
|
group.byte 0xE++0x00
|
|
line.byte 0x00 "FCCOB_9,Flash Common Command Object Registers"
|
|
group.byte 0xF++0x00
|
|
line.byte 0x00 "FCCOB_8,Flash Common Command Object Registers"
|
|
sif cpuis("MKL??Z8*")&&!cpuis("MKL03Z*")&&!cpuis("MKL05Z*")
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "FPROT_3,Program Flash Protection Register 3"
|
|
bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 6. " PROT[6] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 5. " PROT[5] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 4. " PROT[4] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PROT[3] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 2. " PROT[2] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 1. " PROT[1] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 0. " PROT[0] ,Program flash region protect" "Protected,Not protected"
|
|
elif cpuis("MKL??Z16*")
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "FPROT_3,Program Flash Protection Register 3"
|
|
bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 6. " PROT[6] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 5. " PROT[5] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 4. " PROT[4] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PROT[3] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 2. " PROT[2] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 1. " PROT[1] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 0. " PROT[0] ,Program flash region protect" "Protected,Not protected"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "FPROT_2,Program Flash Protection Register 2"
|
|
bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 6. " PROT[6] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 5. " PROT[5] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 4. " PROT[4] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PROT[3] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 2. " PROT[2] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 1. " PROT[1] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 0. " PROT[0] ,Program flash region protect" "Protected,Not protected"
|
|
else
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "FPROT_3,Program Flash Protection Register 3"
|
|
bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 6. " PROT[6] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 5. " PROT[5] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 4. " PROT[4] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PROT[3] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 2. " PROT[2] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 1. " PROT[1] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 0. " PROT[0] ,Program flash region protect" "Protected,Not protected"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "FPROT_2,Program Flash Protection Register 2"
|
|
bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 6. " PROT[6] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 5. " PROT[5] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 4. " PROT[4] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PROT[3] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 2. " PROT[2] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 1. " PROT[1] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 0. " PROT[0] ,Program flash region protect" "Protected,Not protected"
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "FPROT_1,Program Flash Protection Register 1"
|
|
bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 6. " PROT[6] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 5. " PROT[5] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 4. " PROT[4] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PROT[3] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 2. " PROT[2] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 1. " PROT[1] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 0. " PROT[0] ,Program flash region protect" "Protected,Not protected"
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "FPROT_0,Program Flash Protection Register 0"
|
|
bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 6. " PROT[6] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 5. " PROT[5] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 4. " PROT[4] ,Program flash region protect" "Protected,Not protected"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PROT[3] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 2. " PROT[2] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 1. " PROT[1] ,Program flash region protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 0. " PROT[0] ,Program flash region protect" "Protected,Not protected"
|
|
endif
|
|
sif cpuis("MKL28Z*")||cpuis("MKL82Z*")
|
|
rgroup.byte 0x18++0x03
|
|
line.byte 0x00 "XACCH_3,Execute-only Access Register 3"
|
|
rgroup.byte 0x19++0x03
|
|
line.byte 0x00 "XACCH_2,Execute-only Access Register 2"
|
|
rgroup.byte 0x1A++0x03
|
|
line.byte 0x00 "XACCH_1,Execute-only Access Register 1"
|
|
rgroup.byte 0x1B++0x03
|
|
line.byte 0x00 "XACCH_0,Execute-only Access Register 0"
|
|
rgroup.byte 0x1C++0x03
|
|
line.byte 0x00 "XACCL3,Execute-only Access Register 3"
|
|
rgroup.byte 0x1D++0x03
|
|
line.byte 0x00 "XACCL2,Execute-only Access Register 2"
|
|
rgroup.byte 0x1E++0x03
|
|
line.byte 0x00 "XACCL1,Execute-only Access Register 1"
|
|
rgroup.byte 0x1F++0x03
|
|
line.byte 0x00 "XACCL0,Execute-only Access Register 0"
|
|
rgroup.byte 0x20++0x03
|
|
line.byte 0x00 "SACCH3,Supervisor-only Access Register 3"
|
|
rgroup.byte 0x21++0x03
|
|
line.byte 0x00 "SACCH2,Supervisor-only Access Register 2"
|
|
rgroup.byte 0x22++0x03
|
|
line.byte 0x00 "SACCH1,Supervisor-only Access Register 1"
|
|
rgroup.byte 0x23++0x03
|
|
line.byte 0x00 "SACCH0,Supervisor-only Access Register 0"
|
|
rgroup.byte 0x24++0x03
|
|
line.byte 0x00 "SACCL3,Supervisor-only Access Register 3"
|
|
rgroup.byte 0x25++0x03
|
|
line.byte 0x00 "SACCL2,Supervisor-only Access Register 2"
|
|
rgroup.byte 0x26++0x03
|
|
line.byte 0x00 "SACCL1,Supervisor-only Access Register 1"
|
|
rgroup.byte 0x27++0x03
|
|
line.byte 0x00 "SACCL0,Supervisor-only Access Register 0"
|
|
rgroup.byte 0x28++0x00
|
|
line.byte 0x00 "FACSS,Flash Access Segment Size Register"
|
|
rgroup.byte 0x2B++0x00
|
|
line.byte 0x00 "FACSN,Flash Access Segment Number Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "ADC (Analog-to-Digital Converter)"
|
|
sif cpuis("MKL28*")
|
|
base ad:0x40066000
|
|
width 16.
|
|
sif cpuis("MKL0*")||cpuis("MKL24*")
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "ADC0_SC1_A,ADC Status And Control Register 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled"
|
|
sif cpuis("MKL02*VFG*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",ADC0_SE1,,,ADC0_SE4,,,,ADC0_SE5,ADC0_SE6,ADC0_SE7,,,,,ADC0_SE12,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL02*CAF*")||cpuis("MKL03*VFG*")||cpuis("MKL03*CAF*")||cpuis("MKL03*CBF*")||cpuis("MKL03*VFK*")||cpuis("MKL05*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp Sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL02*VFM*")||cpuis("MKL02*VFK*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_SE0,ADC0_SE1,ADC0_SE2,ADC0_SE3,ADC0_SE4,,,,ADC0_SE5,ADC0_SE6,ADC0_SE7,ADC0_SE8,ADC0_SE9,ADC0_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("*CAF*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_SE0,ADC0_SE1,ADC0_SE2,ADC0_SE3,,,,,ADC0_SE8,ADC0_SE9,,,,,,ADC0_SE15,,,,,,,,,,,Temp sensor,Bandgap,,VDD,VSS,Disabled"
|
|
elif cpuis("MKL04*VFM*")||cpuis("MKL04*VLC*")||cpuis("MKL04*VLF*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_SE0,ADC0_SE1,ADC0_SE2,ADC0_SE3,ADC0_SE4,ADC0_SE5,ADC0_SE6,ADC0_SE7,ADC0_SE8,ADC0_SE9,ADC0_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL04*VFK*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_SE0,ADC0_SE1,ADC0_SE2,ADC0_SE3,ADC0_SE4,ADC0_SE5,ADC0_SE6,ADC0_SE7,ADC0_SE8,ADC0_SE9,,,ADC0_SE12,ADC0_SE13,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL24*VFM*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",,,,,,AD6 a/b,AD7 b,AD8,AD9,,AD11,,,,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL24*VFT*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,,,,AD4 a/b,AD5 b,AD6 a/b,AD7 b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL24*VLH*")||cpuis("MKL24*VLK*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,,,AD3,AD4 a/b,AD5 b,AD6 a/b,AD7 a/b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
endif
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "ADC0_SC1_B,ADC Status And Control Register 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled"
|
|
sif cpuis("MKL02*VFG*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",ADC0_SE1,,,ADC0_SE4,,,,ADC0_SE5,ADC0_SE6,ADC0_SE7,,,,,ADC0_SE12,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL02*CAF*")||cpuis("MKL03*VFG*")||cpuis("MKL03*CAF*")||cpuis("MKL03*CBF*")||cpuis("MKL03*VFK*")||cpuis("MKL05*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp Sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL02*VFM*")||cpuis("MKL02*VFK*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_SE0,ADC0_SE1,ADC0_SE2,ADC0_SE3,ADC0_SE4,,,,ADC0_SE5,ADC0_SE6,ADC0_SE7,ADC0_SE8,ADC0_SE9,ADC0_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("*CAF*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_SE0,ADC0_SE1,ADC0_SE2,ADC0_SE3,,,,,ADC0_SE8,ADC0_SE9,,,,,,ADC0_SE15,,,,,,,,,,,Temp sensor,Bandgap,,VDD,VSS,Disabled"
|
|
elif cpuis("MKL04*VFM*")||cpuis("MKL04*VLC*")||cpuis("MKL04*VLF*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_SE0,ADC0_SE1,ADC0_SE2,ADC0_SE3,ADC0_SE4,ADC0_SE5,ADC0_SE6,ADC0_SE7,ADC0_SE8,ADC0_SE9,ADC0_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL04*VFK*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_SE0,ADC0_SE1,ADC0_SE2,ADC0_SE3,ADC0_SE4,ADC0_SE5,ADC0_SE6,ADC0_SE7,ADC0_SE8,ADC0_SE9,,,ADC0_SE12,ADC0_SE13,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL24*VFM*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",,,,,,AD6 a/b,AD7 b,AD8,AD9,,AD11,,,,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL24*VFT*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,,,,AD4 a/b,AD5 b,AD6 a/b,AD7 b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL24*VLH*")||cpuis("MKL24*VLK*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,,,AD3,AD4 a/b,AD5 b,AD6 a/b,AD7 a/b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC0_CFG_1,ADC Configuration Register 1"
|
|
bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power"
|
|
bitfld.long 0x00 5.--6. " ADIV ,Clock divide select" "/1,/2,/4,/8"
|
|
bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long"
|
|
bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "Single-ended 8-bit,Single-ended 12-bit,Single-ended 10-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK"
|
|
else
|
|
if (((per.l(ad:0x40066000+0x0))&0x20)==0x0)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "ADC0_SC1_A,ADC Status And Control Register 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled"
|
|
sif cpuis("MKL15*CAD*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,,AD4 a/b,AD5 a,AD6 a/b,AD7 b,AD8,AD9,,AD11,,,,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL13*VLH*")||cpuis("MKL13*VLK*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL28Z*")||cpuis("MKL33Z*")||cpuis("MKL82Z*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL17*VDA*")||cpuis("MKL27*VDA*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4 a,AD5 a,AD6 a/b,AD7 a/b,AD8,AD9,,AD11,,,,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL26*CAL*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DADP1,DADP2,,,AD5 a,AD6 a/b,AD7 b,AD8,AD9,,AD11,,,,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL27Z32*VLH*")||cpuis("MKL27Z64*VLH*")||cpuis("MKL27Z32*VMP*")||cpuis("MKL27Z64*VMP*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,,DADP3,AD4 a/b,AD5 b,AD6 b,AD7 a/b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL27Z128*VLH*")||cpuis("MKL27Z256*VLH*")||cpuis("MKL27Z128*VMP*")||cpuis("MKL27Z256*VMP*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,,,DADP3,AD4 a/b,AD5 b,AD6 b,AD7 a/b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL2*VFM*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",,,,,,AD6 a/b,AD7 b,AD8,AD9,,AD11,,,,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL2*VFT*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,,,,AD4 a/b,AD5 b,AD6 a/b,AD7 b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL2*VLH*")||cpuis("MKL2*VMP*")||cpuis("MKL2*VLK*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,,,DADP3,AD4 a/b,AD5 b,AD6 a/b,AD7 a/b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL2*VMC*")||cpuis("MKL2*VLL*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4 a/b,AD5 a/b,AD6 a/b,AD7 a/b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("*VFM*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DADP1,DADP2,,,AD5 a,AD6 a/b,AD7 b,AD8,AD9,,AD11,,,,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("*VFT*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,,AD4 a/b,AD5 a/b,AD6 a/b,AD7 b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("*VLH*")||cpuis("*VMP*")||cpuis("*VLK*")||cpuis("*VMC*")||cpuis("*VLL*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4 a/b,AD5 a/b,AD6 a/b,AD7 a/b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
endif
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "ADC0_SC1_A,ADC Status And Control Register 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled"
|
|
sif cpuis("MKL15*CAD*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,,Disabled"
|
|
elif cpuis("MKL17*")||cpuis("*VLH*")||cpuis("*VMP*")||cpuis("*VLK*")||cpuis("*VMC*")||cpuis("*VLL*")||cpuis("MKL28Z*")||cpuis("MKL33Z*")||cpuis("MKL82Z*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,,Disabled"
|
|
elif cpuis("MKL26*CAL*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DAD1,DAD2,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,,Disabled"
|
|
elif cpuis("MKL27Z32*VLH*")||cpuis("MKL27Z64*VLH*")||cpuis("MKL27Z32*VMP*")||cpuis("MKL27Z64*VMP*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,,Disabled"
|
|
elif cpuis("MKL27Z128*VLH*")||cpuis("MKL27Z256*VLH*")||cpuis("MKL27Z128*VMP*")||cpuis("MKL27Z256*VMP*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,,,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,,Disabled"
|
|
elif cpuis("MKL2*VFM*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",,,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL2*VFT*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,,,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL2*VLH*")||cpuis("MKL2*VMP*")||cpuis("MKL2*VLK*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,,,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL2*VMC*")||cpuis("MKL2*VLL*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("*VFM*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DAD1,DAD2,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,,Disabled"
|
|
elif cpuis("*VFT*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,,Disabled"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40066000+0x4))&0x20)==0x0)
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "ADC0_SC1_B,ADC Status And Control Register 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled"
|
|
sif cpuis("MKL15*CAD*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,,AD4 a/b,AD5 a,AD6 a/b,AD7 b,AD8,AD9,,AD11,,,,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL13*VLH*")||cpuis("MKL13*VLK*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL28Z*")||cpuis("MKL33Z*")||cpuis("MKL82Z*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL17*VDA*")||cpuis("MKL27*VDA*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4 a,AD5 a,AD6 a/b,AD7 a/b,AD8,AD9,,AD11,,,,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL26*CAL*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DADP1,DADP2,,,AD5 a,AD6 a/b,AD7 b,AD8,AD9,,AD11,,,,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL27Z32*VLH*")||cpuis("MKL27Z64*VLH*")||cpuis("MKL27Z32*VMP*")||cpuis("MKL27Z64*VMP*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,,DADP3,AD4 a/b,AD5 b,AD6 b,AD7 a/b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL27Z128*VLH*")||cpuis("MKL27Z256*VLH*")||cpuis("MKL27Z128*VMP*")||cpuis("MKL27Z256*VMP*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,,,DADP3,AD4 a/b,AD5 b,AD6 b,AD7 a/b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL2*VFM*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",,,,,,AD6 a/b,AD7 b,AD8,AD9,,AD11,,,,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL2*VFT*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,,,,AD4 a/b,AD5 b,AD6 a/b,AD7 b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL2*VLH*")||cpuis("MKL2*VMP*")||cpuis("MKL2*VLK*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,,,DADP3,AD4 a/b,AD5 b,AD6 a/b,AD7 a/b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL2*VMC*")||cpuis("MKL2*VLL*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4 a/b,AD5 a/b,AD6 a/b,AD7 a/b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("*VFM*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DADP1,DADP2,,,AD5 a,AD6 a/b,AD7 b,AD8,AD9,,AD11,,,,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("*VFT*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,,AD4 a/b,AD5 a/b,AD6 a/b,AD7 b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("*VLH*")||cpuis("*VMP*")||cpuis("*VLK*")||cpuis("*VMC*")||cpuis("*VLL*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4 a/b,AD5 a/b,AD6 a/b,AD7 a/b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
endif
|
|
else
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "ADC0_SC1_B,ADC Status And Control Register 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled"
|
|
sif cpuis("MKL15*CAD*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,,Disabled"
|
|
elif cpuis("MKL17*")||cpuis("*VLH*")||cpuis("*VMP*")||cpuis("*VLK*")||cpuis("*VMC*")||cpuis("*VLL*")||cpuis("MKL28Z*")||cpuis("MKL33Z*")||cpuis("MKL82Z*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,,Disabled"
|
|
elif cpuis("MKL26*CAL*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DAD1,DAD2,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,,Disabled"
|
|
elif cpuis("MKL27Z32*VLH*")||cpuis("MKL27Z64*VLH*")||cpuis("MKL27Z32*VMP*")||cpuis("MKL27Z64*VMP*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,,Disabled"
|
|
elif cpuis("MKL27Z128*VLH*")||cpuis("MKL27Z256*VLH*")||cpuis("MKL27Z128*VMP*")||cpuis("MKL27Z256*VMP*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,,,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,,Disabled"
|
|
elif cpuis("MKL2*VFM*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",,,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL2*VFT*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,,,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL2*VLH*")||cpuis("MKL2*VMP*")||cpuis("MKL2*VLK*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,,,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL2*VMC*")||cpuis("MKL2*VLL*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("*VFM*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DAD1,DAD2,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,,Disabled"
|
|
elif cpuis("*VFT*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,,Disabled"
|
|
endif
|
|
endif
|
|
sif cpuis("MKL13Z32*")||cpuis("MKL13Z64*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL28Z*")||cpuis("MKL82Z*")
|
|
if ((per.l(ad:0x40066000)&0x20)==0x0)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC0_CFG_1,ADC Configuration Register 1"
|
|
bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power"
|
|
bitfld.long 0x00 5.--6. " ADIV ,Clock divide select" "/1,/2,/4,/8"
|
|
bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long"
|
|
bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "Single-ended 8-bit,Single-ended 12-bit,Single-ended 10-bit,Single-ended 16-bit"
|
|
textline " "
|
|
sif (cpuis("MKL82*"))
|
|
bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,ALTCLK2,ALTCLK,ADACK"
|
|
else
|
|
bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK"
|
|
endif
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC0_CFG_1,ADC Configuration Register 1"
|
|
bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power"
|
|
bitfld.long 0x00 5.--6. " ADIV ,Clock divide select" "/1,/2,/4,/8"
|
|
bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long"
|
|
bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "Differential 9-bit,Differential 13-bit,Differential 11-bit,Differential 16-bit"
|
|
textline " "
|
|
sif (cpuis("MKL82*"))
|
|
bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,ALTCLK2,ALTCLK,ADACK"
|
|
else
|
|
bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK"
|
|
endif
|
|
endif
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC0_CFG_1,ADC Configuration Register 1"
|
|
bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power"
|
|
bitfld.long 0x00 5.--6. " ADIV ,Clock divide select" "/1,/2,/4,/8"
|
|
bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long"
|
|
sif (cpuis("MKL34"))
|
|
bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "Single-ended 8-bit/Differential 9-bit,Single-ended 12-bit/Differential 13-bit,Single-ended 10-bit/Differential 11-bit,?..."
|
|
else
|
|
bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "Single-ended 8-bit/Differential 9-bit,Single-ended 12-bit/Differential 13-bit,Single-ended 10-bit/Differential 11-bit,Single-ended 16-bit/Differential 16-bit"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("MKL13*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL26*"))
|
|
bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,ALTCLK2,ALTCLK,ADACK"
|
|
else
|
|
bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK"
|
|
endif
|
|
endif
|
|
endif
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC0_CFG_2,ADC Configuration Register 2"
|
|
bitfld.long 0x00 4. " MUXSEL ,ADC mux select" "AD_A,AD_B"
|
|
bitfld.long 0x00 3. " ADACKEN ,Asynchronous clock output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ADHSC ,High speed configuration" "Normal,High-speed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " ADLSTS ,Long sample time select (total time)" "24 ADCK cycles,16 ADCK cycles,10 ADCK cycles,6 ADCK cycles"
|
|
sif cpuis("MKL0*")||cpuis("MKL24*")
|
|
if (((per.l(ad:0x40066000+0x08))&0x0C)==0x00)
|
|
rgroup.long 0x10++0x07
|
|
line.long 0x00 "ADC0_RA,ADC Data Result Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " D ,Data result"
|
|
line.long 0x04 "ADC0_RB,ADC Data Result Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " D ,Data result"
|
|
group.long 0x18++0x07
|
|
line.long 0x00 "ADC0_CV1,Compare Value Registers"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CV ,Compare value"
|
|
line.long 0x04 "ADC0_CV2,Compare Value Registers"
|
|
hexmask.long.byte 0x04 0.--7. 1. " CV ,Compare value"
|
|
elif (((per.l(ad:0x40066000+0x08))&0x0C)==0x08)
|
|
rgroup.long 0x10++0x07
|
|
line.long 0x00 "ADC0_RA,ADC Data Result Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " D ,Data result"
|
|
line.long 0x04 "ADC0_RB,ADC Data Result Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " D ,Data result"
|
|
group.long 0x18++0x07
|
|
line.long 0x00 "ADC0_CV1,Compare Value Registers"
|
|
hexmask.long.word 0x00 0.--9. 1. " CV ,Compare value"
|
|
line.long 0x04 "ADC0_CV2,Compare Value Registers"
|
|
hexmask.long.word 0x04 0.--9. 1. " CV ,Compare value"
|
|
else
|
|
rgroup.long 0x10++0x07
|
|
line.long 0x00 "ADC0_RA,ADC Data Result Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " D ,Data result"
|
|
line.long 0x04 "ADC0_RB,ADC Data Result Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " D ,Data result"
|
|
group.long 0x18++0x07
|
|
line.long 0x00 "ADC0_CV1,Compare Value Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. " CV ,Compare value"
|
|
line.long 0x04 "ADC0_CV2,Compare Value Registers"
|
|
hexmask.long.word 0x04 0.--11. 1. " CV ,Compare value"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40066000+0x00))&0x20)==0x00)
|
|
if (((per.l(ad:0x40066000+0x08))&0x0C)==0x00)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ADC0_RA,ADC Data Result Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " D ,Data result"
|
|
elif (((per.l(ad:0x40066000+0x08))&0x0C)==0x04)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ADC0_RA,ADC Data Result Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " D ,Data result"
|
|
elif (((per.l(ad:0x40066000+0x08))&0x0C)==0x08)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ADC0_RA,ADC Data Result Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " D ,Data result"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ADC0_RA,ADC Data Result Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " D ,Data result"
|
|
endif
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ADC0_RA,ADC Data Result Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " D ,Data result"
|
|
endif
|
|
if (((per.l(ad:0x40066000+0x04))&0x20)==0x00)
|
|
if (((per.l(ad:0x40066000+0x08))&0x0C)==0x00)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ADC0_RB,ADC Data Result Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " D ,Data result"
|
|
elif (((per.l(ad:0x40066000+0x08))&0x0C)==0x04)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ADC0_RB,ADC Data Result Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " D ,Data result"
|
|
elif (((per.l(ad:0x40066000+0x08))&0xC)==0x8)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ADC0_RB,ADC Data Result Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " D ,Data result"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ADC0_RB,ADC Data Result Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " D ,Data result"
|
|
endif
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ADC0_RB,ADC Data Result Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " D ,Data result"
|
|
endif
|
|
if (((per.l(ad:0x40066000+0x00))&0x20)==0x00)
|
|
if (((per.l(ad:0x40066000+0x08))&0x0C)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ADC0_CV1,Compare Value Registers"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CV ,Compare value"
|
|
elif (((per.l(ad:0x40066000+0x08))&0x0C)==0x04)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ADC0_CV1,Compare Value Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. " CV ,Compare value"
|
|
elif (((per.l(ad:0x40066000+0x08))&0x0C)==0x08)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ADC0_CV1,Compare Value Registers"
|
|
hexmask.long.word 0x00 0.--9. 1. " CV ,Compare value"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ADC0_CV1,Compare Value Registers"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value"
|
|
endif
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ADC0_CV1,Compare Value Registers"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value"
|
|
endif
|
|
if (((per.l(ad:0x40066000+0x04))&0x20)==0x00)
|
|
if (((per.l(ad:0x40066000+0x08))&0x0C)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ADC0_CV2,Compare Value Registers"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CV ,Compare value"
|
|
elif (((per.l(ad:0x40066000+0x08))&0x0C)==0x04)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ADC0_CV2,Compare Value Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. " CV ,Compare value"
|
|
elif (((per.l(ad:0x40066000+0x08))&0x0C)==0x08)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ADC0_CV2,Compare Value Registers"
|
|
hexmask.long.word 0x00 0.--9. 1. " CV ,Compare value"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ADC0_CV2,Compare Value Registers"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value"
|
|
endif
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ADC0_CV2,Compare Value Registers"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value"
|
|
endif
|
|
endif
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "ADC0_SC2,Status And Control Register 2"
|
|
rbitfld.long 0x00 7. " ADACT ,Conversion active" "Not in progress,In progress"
|
|
bitfld.long 0x00 6. " ADTRG ,Conversion trigger select" "Software,Hardware"
|
|
bitfld.long 0x00 5. " ACFE ,Compare function enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("MKL02Z*")||cpuis("MKL03Z*")
|
|
bitfld.long 0x00 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ACREN ,Compare function range enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " REFSEL ,Voltage reference selection" "Default,Alternate,?..."
|
|
else
|
|
bitfld.long 0x00 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ACREN ,Compare function range enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " REFSEL ,Voltage reference selection" "Default,Alternate,?..."
|
|
endif
|
|
line.long 0x04 "ADC0_SC3,Status And Control Register 3"
|
|
bitfld.long 0x04 7. " CAL ,Calibration" "Not started,Started"
|
|
eventfld.long 0x04 6. " CALF ,Calibration failed flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 3. " ADCO ,Continuous conversion enable" "Single,Continuous"
|
|
textline " "
|
|
bitfld.long 0x04 2. " AVGE ,Hardware average enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--1. " AVGS ,Hardware average select" "4 samples,8 samples,16 samples,32 samples"
|
|
line.long 0x08 "ADC0_OFS,ADC Offset Correction Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " OFS ,Offset error correction value"
|
|
line.long 0x0C "ADC0_PG,ADC Plus-side Gain Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " PG ,Plus-side gain"
|
|
sif !cpuis("MKL0*")&&!cpuis("MK14*")&&!cpuis("MKL14*")&&!cpuis("MKL24*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "ADC0_MG,ADC Minus-side Gain Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " MG ,Minus-side gain"
|
|
endif
|
|
group.long 0x34++0x1B
|
|
line.long 0x00 "ADC0_CLPD,ADC Plus-side General Calibration Value Register"
|
|
bitfld.long 0x00 0.--5. " CLPD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "ADC0_CLPS,ADC Plus-side General Calibration Value Register"
|
|
bitfld.long 0x04 0.--5. " CLPS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "ADC0_CLP4,ADC Plus-side General Calibration Value Register 4"
|
|
hexmask.long.word 0x08 0.--9. 1. " CLP4 ,Calibration value"
|
|
line.long 0x0C "ADC0_CLP3,ADC Plus-side General Calibration Value Register 3"
|
|
hexmask.long.word 0x0C 0.--8. 1. " CLP3 ,Calibration value"
|
|
line.long 0x10 "ADC0_CLP2,ADC Plus-side General Calibration Value Register 2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " CLP2 ,Calibration value"
|
|
line.long 0x14 "ADC0_CLP1,ADC Plus-side General Calibration Value Register 1"
|
|
hexmask.long.byte 0x14 0.--6. 1. " CLP1 ,Calibration value"
|
|
line.long 0x18 "ADC0_CLP0,ADC Plus-side General Calibration Value Register 0"
|
|
bitfld.long 0x18 0.--5. " CLP0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif !cpuis("MKL0*")&&!cpuis("MK14*")&&!cpuis("MKL14*")&&!cpuis("MKL24*")
|
|
group.long 0x54++0x1B
|
|
line.long 0x00 "ADC0_CLMD,ADC Minus-side General Calibration Value Register"
|
|
bitfld.long 0x00 0.--5. " CLMD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "ADC0_CLMS,ADC Minus-side General Calibration Value Register"
|
|
bitfld.long 0x04 0.--5. " CLMS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "ADC0_CLM4,ADC Minus-side General Calibration Value Register 4"
|
|
hexmask.long.word 0x08 0.--9. 1. " CLM4 ,Calibration value"
|
|
line.long 0x0C "ADC0_CLM3,ADC Minus-side General Calibration Value Register 3"
|
|
hexmask.long.word 0x0C 0.--8. 1. " CLM3 ,Calibration value"
|
|
line.long 0x10 "ADC0_CLM2,ADC Minus-side General Calibration Value Register 2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " CLM2 ,Calibration value"
|
|
line.long 0x14 "ADC0_CLM1,ADC Minus-side General Calibration Value Register 1"
|
|
hexmask.long.byte 0x14 0.--6. 1. " CLM1 ,Calibration value"
|
|
line.long 0x18 "ADC0_CLM0,ADC Minus-side General Calibration Value Register 0"
|
|
bitfld.long 0x18 0.--5. " CLM0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
base ad:0x4003B000
|
|
width 16.
|
|
sif cpuis("MKL0*")||cpuis("MKL24*")
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "ADC0_SC1_A,ADC Status And Control Register 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled"
|
|
sif cpuis("MKL02*VFG*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",ADC0_SE1,,,ADC0_SE4,,,,ADC0_SE5,ADC0_SE6,ADC0_SE7,,,,,ADC0_SE12,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL02*CAF*")||cpuis("MKL03*VFG*")||cpuis("MKL03*CAF*")||cpuis("MKL03*CBF*")||cpuis("MKL03*VFK*")||cpuis("MKL05*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp Sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL02*VFM*")||cpuis("MKL02*VFK*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_SE0,ADC0_SE1,ADC0_SE2,ADC0_SE3,ADC0_SE4,,,,ADC0_SE5,ADC0_SE6,ADC0_SE7,ADC0_SE8,ADC0_SE9,ADC0_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("*CAF*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_SE0,ADC0_SE1,ADC0_SE2,ADC0_SE3,,,,,ADC0_SE8,ADC0_SE9,,,,,,ADC0_SE15,,,,,,,,,,,Temp sensor,Bandgap,,VDD,VSS,Disabled"
|
|
elif cpuis("MKL04*VFM*")||cpuis("MKL04*VLC*")||cpuis("MKL04*VLF*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_SE0,ADC0_SE1,ADC0_SE2,ADC0_SE3,ADC0_SE4,ADC0_SE5,ADC0_SE6,ADC0_SE7,ADC0_SE8,ADC0_SE9,ADC0_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL04*VFK*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_SE0,ADC0_SE1,ADC0_SE2,ADC0_SE3,ADC0_SE4,ADC0_SE5,ADC0_SE6,ADC0_SE7,ADC0_SE8,ADC0_SE9,,,ADC0_SE12,ADC0_SE13,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL24*VFM*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",,,,,,AD6 a/b,AD7 b,AD8,AD9,,AD11,,,,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL24*VFT*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,,,,AD4 a/b,AD5 b,AD6 a/b,AD7 b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL24*VLH*")||cpuis("MKL24*VLK*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,,,AD3,AD4 a/b,AD5 b,AD6 a/b,AD7 a/b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
endif
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "ADC0_SC1_B,ADC Status And Control Register 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled"
|
|
sif cpuis("MKL02*VFG*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",ADC0_SE1,,,ADC0_SE4,,,,ADC0_SE5,ADC0_SE6,ADC0_SE7,,,,,ADC0_SE12,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL02*CAF*")||cpuis("MKL03*VFG*")||cpuis("MKL03*CAF*")||cpuis("MKL03*CBF*")||cpuis("MKL03*VFK*")||cpuis("MKL05*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp Sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL02*VFM*")||cpuis("MKL02*VFK*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_SE0,ADC0_SE1,ADC0_SE2,ADC0_SE3,ADC0_SE4,,,,ADC0_SE5,ADC0_SE6,ADC0_SE7,ADC0_SE8,ADC0_SE9,ADC0_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("*CAF*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_SE0,ADC0_SE1,ADC0_SE2,ADC0_SE3,,,,,ADC0_SE8,ADC0_SE9,,,,,,ADC0_SE15,,,,,,,,,,,Temp sensor,Bandgap,,VDD,VSS,Disabled"
|
|
elif cpuis("MKL04*VFM*")||cpuis("MKL04*VLC*")||cpuis("MKL04*VLF*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_SE0,ADC0_SE1,ADC0_SE2,ADC0_SE3,ADC0_SE4,ADC0_SE5,ADC0_SE6,ADC0_SE7,ADC0_SE8,ADC0_SE9,ADC0_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL04*VFK*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_SE0,ADC0_SE1,ADC0_SE2,ADC0_SE3,ADC0_SE4,ADC0_SE5,ADC0_SE6,ADC0_SE7,ADC0_SE8,ADC0_SE9,,,ADC0_SE12,ADC0_SE13,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL24*VFM*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",,,,,,AD6 a/b,AD7 b,AD8,AD9,,AD11,,,,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL24*VFT*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,,,,AD4 a/b,AD5 b,AD6 a/b,AD7 b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL24*VLH*")||cpuis("MKL24*VLK*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,,,AD3,AD4 a/b,AD5 b,AD6 a/b,AD7 a/b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC0_CFG_1,ADC Configuration Register 1"
|
|
bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power"
|
|
bitfld.long 0x00 5.--6. " ADIV ,Clock divide select" "/1,/2,/4,/8"
|
|
bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long"
|
|
bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "Single-ended 8-bit,Single-ended 12-bit,Single-ended 10-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK"
|
|
else
|
|
if (((per.l(ad:0x4003B000+0x0))&0x20)==0x0)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "ADC0_SC1_A,ADC Status And Control Register 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled"
|
|
sif cpuis("MKL15*CAD*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,,AD4 a/b,AD5 a,AD6 a/b,AD7 b,AD8,AD9,,AD11,,,,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL13*VLH*")||cpuis("MKL13*VLK*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL28Z*")||cpuis("MKL33Z*")||cpuis("MKL82Z*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL17*VDA*")||cpuis("MKL27*VDA*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4 a,AD5 a,AD6 a/b,AD7 a/b,AD8,AD9,,AD11,,,,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL26*CAL*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DADP1,DADP2,,,AD5 a,AD6 a/b,AD7 b,AD8,AD9,,AD11,,,,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL27Z32*VLH*")||cpuis("MKL27Z64*VLH*")||cpuis("MKL27Z32*VMP*")||cpuis("MKL27Z64*VMP*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,,DADP3,AD4 a/b,AD5 b,AD6 b,AD7 a/b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL27Z128*VLH*")||cpuis("MKL27Z256*VLH*")||cpuis("MKL27Z128*VMP*")||cpuis("MKL27Z256*VMP*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,,,DADP3,AD4 a/b,AD5 b,AD6 b,AD7 a/b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL2*VFM*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",,,,,,AD6 a/b,AD7 b,AD8,AD9,,AD11,,,,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL2*VFT*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,,,,AD4 a/b,AD5 b,AD6 a/b,AD7 b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL2*VLH*")||cpuis("MKL2*VMP*")||cpuis("MKL2*VLK*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,,,DADP3,AD4 a/b,AD5 b,AD6 a/b,AD7 a/b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL2*VMC*")||cpuis("MKL2*VLL*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4 a/b,AD5 a/b,AD6 a/b,AD7 a/b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("*VFM*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DADP1,DADP2,,,AD5 a,AD6 a/b,AD7 b,AD8,AD9,,AD11,,,,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("*VFT*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,,AD4 a/b,AD5 a/b,AD6 a/b,AD7 b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("*VLH*")||cpuis("*VMP*")||cpuis("*VLK*")||cpuis("*VMC*")||cpuis("*VLL*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4 a/b,AD5 a/b,AD6 a/b,AD7 a/b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
endif
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "ADC0_SC1_A,ADC Status And Control Register 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled"
|
|
sif cpuis("MKL15*CAD*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,,Disabled"
|
|
elif cpuis("MKL17*")||cpuis("*VLH*")||cpuis("*VMP*")||cpuis("*VLK*")||cpuis("*VMC*")||cpuis("*VLL*")||cpuis("MKL28Z*")||cpuis("MKL33Z*")||cpuis("MKL82Z*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,,Disabled"
|
|
elif cpuis("MKL26*CAL*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DAD1,DAD2,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,,Disabled"
|
|
elif cpuis("MKL27Z32*VLH*")||cpuis("MKL27Z64*VLH*")||cpuis("MKL27Z32*VMP*")||cpuis("MKL27Z64*VMP*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,,Disabled"
|
|
elif cpuis("MKL27Z128*VLH*")||cpuis("MKL27Z256*VLH*")||cpuis("MKL27Z128*VMP*")||cpuis("MKL27Z256*VMP*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,,,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,,Disabled"
|
|
elif cpuis("MKL2*VFM*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",,,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL2*VFT*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,,,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL2*VLH*")||cpuis("MKL2*VMP*")||cpuis("MKL2*VLK*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,,,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL2*VMC*")||cpuis("MKL2*VLL*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("*VFM*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DAD1,DAD2,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,,Disabled"
|
|
elif cpuis("*VFT*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,,Disabled"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x4003B000+0x4))&0x20)==0x0)
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "ADC0_SC1_B,ADC Status And Control Register 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled"
|
|
sif cpuis("MKL15*CAD*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,,AD4 a/b,AD5 a,AD6 a/b,AD7 b,AD8,AD9,,AD11,,,,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL13*VLH*")||cpuis("MKL13*VLK*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL28Z*")||cpuis("MKL33Z*")||cpuis("MKL82Z*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL17*VDA*")||cpuis("MKL27*VDA*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4 a,AD5 a,AD6 a/b,AD7 a/b,AD8,AD9,,AD11,,,,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL26*CAL*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DADP1,DADP2,,,AD5 a,AD6 a/b,AD7 b,AD8,AD9,,AD11,,,,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL27Z32*VLH*")||cpuis("MKL27Z64*VLH*")||cpuis("MKL27Z32*VMP*")||cpuis("MKL27Z64*VMP*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,,DADP3,AD4 a/b,AD5 b,AD6 b,AD7 a/b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL27Z128*VLH*")||cpuis("MKL27Z256*VLH*")||cpuis("MKL27Z128*VMP*")||cpuis("MKL27Z256*VMP*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,,,DADP3,AD4 a/b,AD5 b,AD6 b,AD7 a/b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL2*VFM*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",,,,,,AD6 a/b,AD7 b,AD8,AD9,,AD11,,,,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL2*VFT*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,,,,AD4 a/b,AD5 b,AD6 a/b,AD7 b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL2*VLH*")||cpuis("MKL2*VMP*")||cpuis("MKL2*VLK*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,,,DADP3,AD4 a/b,AD5 b,AD6 a/b,AD7 a/b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL2*VMC*")||cpuis("MKL2*VLL*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4 a/b,AD5 a/b,AD6 a/b,AD7 a/b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("*VFM*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DADP1,DADP2,,,AD5 a,AD6 a/b,AD7 b,AD8,AD9,,AD11,,,,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("*VFT*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,,AD4 a/b,AD5 a/b,AD6 a/b,AD7 b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("*VLH*")||cpuis("*VMP*")||cpuis("*VLK*")||cpuis("*VMC*")||cpuis("*VLL*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4 a/b,AD5 a/b,AD6 a/b,AD7 a/b,AD8,AD9,,AD11,AD12,AD13,AD14,AD15,,,,,,,,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
endif
|
|
else
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "ADC0_SC1_B,ADC Status And Control Register 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled"
|
|
sif cpuis("MKL15*CAD*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,,Disabled"
|
|
elif cpuis("MKL17*")||cpuis("*VLH*")||cpuis("*VMP*")||cpuis("*VLK*")||cpuis("*VMC*")||cpuis("*VLL*")||cpuis("MKL28Z*")||cpuis("MKL33Z*")||cpuis("MKL82Z*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,,Disabled"
|
|
elif cpuis("MKL26*CAL*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DAD1,DAD2,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,,Disabled"
|
|
elif cpuis("MKL27Z32*VLH*")||cpuis("MKL27Z64*VLH*")||cpuis("MKL27Z32*VMP*")||cpuis("MKL27Z64*VMP*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,,Disabled"
|
|
elif cpuis("MKL27Z128*VLH*")||cpuis("MKL27Z256*VLH*")||cpuis("MKL27Z128*VMP*")||cpuis("MKL27Z256*VMP*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,,,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,,Disabled"
|
|
elif cpuis("MKL2*VFM*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",,,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL2*VFT*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,,,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL2*VLH*")||cpuis("MKL2*VMP*")||cpuis("MKL2*VLK*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,,,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("MKL2*VMC*")||cpuis("MKL2*VLL*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled"
|
|
elif cpuis("*VFM*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DAD1,DAD2,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,,Disabled"
|
|
elif cpuis("*VFT*")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor,Bandgap,,VREFSH,,Disabled"
|
|
endif
|
|
endif
|
|
sif cpuis("MKL13Z32*")||cpuis("MKL13Z64*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL28Z*")||cpuis("MKL82Z*")
|
|
if ((per.l(ad:0x4003B000)&0x20)==0x0)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC0_CFG_1,ADC Configuration Register 1"
|
|
bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power"
|
|
bitfld.long 0x00 5.--6. " ADIV ,Clock divide select" "/1,/2,/4,/8"
|
|
bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long"
|
|
bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "Single-ended 8-bit,Single-ended 12-bit,Single-ended 10-bit,Single-ended 16-bit"
|
|
textline " "
|
|
sif (cpuis("MKL82*"))
|
|
bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,ALTCLK2,ALTCLK,ADACK"
|
|
else
|
|
bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK"
|
|
endif
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC0_CFG_1,ADC Configuration Register 1"
|
|
bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power"
|
|
bitfld.long 0x00 5.--6. " ADIV ,Clock divide select" "/1,/2,/4,/8"
|
|
bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long"
|
|
bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "Differential 9-bit,Differential 13-bit,Differential 11-bit,Differential 16-bit"
|
|
textline " "
|
|
sif (cpuis("MKL82*"))
|
|
bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,ALTCLK2,ALTCLK,ADACK"
|
|
else
|
|
bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK"
|
|
endif
|
|
endif
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC0_CFG_1,ADC Configuration Register 1"
|
|
bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power"
|
|
bitfld.long 0x00 5.--6. " ADIV ,Clock divide select" "/1,/2,/4,/8"
|
|
bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long"
|
|
sif (cpuis("MKL34"))
|
|
bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "Single-ended 8-bit/Differential 9-bit,Single-ended 12-bit/Differential 13-bit,Single-ended 10-bit/Differential 11-bit,?..."
|
|
else
|
|
bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "Single-ended 8-bit/Differential 9-bit,Single-ended 12-bit/Differential 13-bit,Single-ended 10-bit/Differential 11-bit,Single-ended 16-bit/Differential 16-bit"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("MKL13*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL26*"))
|
|
bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,ALTCLK2,ALTCLK,ADACK"
|
|
else
|
|
bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK"
|
|
endif
|
|
endif
|
|
endif
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC0_CFG_2,ADC Configuration Register 2"
|
|
bitfld.long 0x00 4. " MUXSEL ,ADC mux select" "AD_A,AD_B"
|
|
bitfld.long 0x00 3. " ADACKEN ,Asynchronous clock output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ADHSC ,High speed configuration" "Normal,High-speed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " ADLSTS ,Long sample time select (total time)" "24 ADCK cycles,16 ADCK cycles,10 ADCK cycles,6 ADCK cycles"
|
|
sif cpuis("MKL0*")||cpuis("MKL24*")
|
|
if (((per.l(ad:0x4003B000+0x08))&0x0C)==0x00)
|
|
rgroup.long 0x10++0x07
|
|
line.long 0x00 "ADC0_RA,ADC Data Result Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " D ,Data result"
|
|
line.long 0x04 "ADC0_RB,ADC Data Result Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " D ,Data result"
|
|
group.long 0x18++0x07
|
|
line.long 0x00 "ADC0_CV1,Compare Value Registers"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CV ,Compare value"
|
|
line.long 0x04 "ADC0_CV2,Compare Value Registers"
|
|
hexmask.long.byte 0x04 0.--7. 1. " CV ,Compare value"
|
|
elif (((per.l(ad:0x4003B000+0x08))&0x0C)==0x08)
|
|
rgroup.long 0x10++0x07
|
|
line.long 0x00 "ADC0_RA,ADC Data Result Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " D ,Data result"
|
|
line.long 0x04 "ADC0_RB,ADC Data Result Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " D ,Data result"
|
|
group.long 0x18++0x07
|
|
line.long 0x00 "ADC0_CV1,Compare Value Registers"
|
|
hexmask.long.word 0x00 0.--9. 1. " CV ,Compare value"
|
|
line.long 0x04 "ADC0_CV2,Compare Value Registers"
|
|
hexmask.long.word 0x04 0.--9. 1. " CV ,Compare value"
|
|
else
|
|
rgroup.long 0x10++0x07
|
|
line.long 0x00 "ADC0_RA,ADC Data Result Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " D ,Data result"
|
|
line.long 0x04 "ADC0_RB,ADC Data Result Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " D ,Data result"
|
|
group.long 0x18++0x07
|
|
line.long 0x00 "ADC0_CV1,Compare Value Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. " CV ,Compare value"
|
|
line.long 0x04 "ADC0_CV2,Compare Value Registers"
|
|
hexmask.long.word 0x04 0.--11. 1. " CV ,Compare value"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4003B000+0x00))&0x20)==0x00)
|
|
if (((per.l(ad:0x4003B000+0x08))&0x0C)==0x00)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ADC0_RA,ADC Data Result Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " D ,Data result"
|
|
elif (((per.l(ad:0x4003B000+0x08))&0x0C)==0x04)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ADC0_RA,ADC Data Result Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " D ,Data result"
|
|
elif (((per.l(ad:0x4003B000+0x08))&0x0C)==0x08)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ADC0_RA,ADC Data Result Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " D ,Data result"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ADC0_RA,ADC Data Result Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " D ,Data result"
|
|
endif
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ADC0_RA,ADC Data Result Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " D ,Data result"
|
|
endif
|
|
if (((per.l(ad:0x4003B000+0x04))&0x20)==0x00)
|
|
if (((per.l(ad:0x4003B000+0x08))&0x0C)==0x00)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ADC0_RB,ADC Data Result Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " D ,Data result"
|
|
elif (((per.l(ad:0x4003B000+0x08))&0x0C)==0x04)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ADC0_RB,ADC Data Result Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " D ,Data result"
|
|
elif (((per.l(ad:0x4003B000+0x08))&0xC)==0x8)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ADC0_RB,ADC Data Result Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " D ,Data result"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ADC0_RB,ADC Data Result Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " D ,Data result"
|
|
endif
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ADC0_RB,ADC Data Result Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " D ,Data result"
|
|
endif
|
|
if (((per.l(ad:0x4003B000+0x00))&0x20)==0x00)
|
|
if (((per.l(ad:0x4003B000+0x08))&0x0C)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ADC0_CV1,Compare Value Registers"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CV ,Compare value"
|
|
elif (((per.l(ad:0x4003B000+0x08))&0x0C)==0x04)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ADC0_CV1,Compare Value Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. " CV ,Compare value"
|
|
elif (((per.l(ad:0x4003B000+0x08))&0x0C)==0x08)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ADC0_CV1,Compare Value Registers"
|
|
hexmask.long.word 0x00 0.--9. 1. " CV ,Compare value"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ADC0_CV1,Compare Value Registers"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value"
|
|
endif
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ADC0_CV1,Compare Value Registers"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value"
|
|
endif
|
|
if (((per.l(ad:0x4003B000+0x04))&0x20)==0x00)
|
|
if (((per.l(ad:0x4003B000+0x08))&0x0C)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ADC0_CV2,Compare Value Registers"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CV ,Compare value"
|
|
elif (((per.l(ad:0x4003B000+0x08))&0x0C)==0x04)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ADC0_CV2,Compare Value Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. " CV ,Compare value"
|
|
elif (((per.l(ad:0x4003B000+0x08))&0x0C)==0x08)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ADC0_CV2,Compare Value Registers"
|
|
hexmask.long.word 0x00 0.--9. 1. " CV ,Compare value"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ADC0_CV2,Compare Value Registers"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value"
|
|
endif
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ADC0_CV2,Compare Value Registers"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value"
|
|
endif
|
|
endif
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "ADC0_SC2,Status And Control Register 2"
|
|
rbitfld.long 0x00 7. " ADACT ,Conversion active" "Not in progress,In progress"
|
|
bitfld.long 0x00 6. " ADTRG ,Conversion trigger select" "Software,Hardware"
|
|
bitfld.long 0x00 5. " ACFE ,Compare function enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("MKL02Z*")||cpuis("MKL03Z*")
|
|
bitfld.long 0x00 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ACREN ,Compare function range enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " REFSEL ,Voltage reference selection" "Default,Alternate,?..."
|
|
else
|
|
bitfld.long 0x00 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ACREN ,Compare function range enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " REFSEL ,Voltage reference selection" "Default,Alternate,?..."
|
|
endif
|
|
line.long 0x04 "ADC0_SC3,Status And Control Register 3"
|
|
bitfld.long 0x04 7. " CAL ,Calibration" "Not started,Started"
|
|
eventfld.long 0x04 6. " CALF ,Calibration failed flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 3. " ADCO ,Continuous conversion enable" "Single,Continuous"
|
|
textline " "
|
|
bitfld.long 0x04 2. " AVGE ,Hardware average enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--1. " AVGS ,Hardware average select" "4 samples,8 samples,16 samples,32 samples"
|
|
line.long 0x08 "ADC0_OFS,ADC Offset Correction Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " OFS ,Offset error correction value"
|
|
line.long 0x0C "ADC0_PG,ADC Plus-side Gain Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " PG ,Plus-side gain"
|
|
sif !cpuis("MKL0*")&&!cpuis("MK14*")&&!cpuis("MKL14*")&&!cpuis("MKL24*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "ADC0_MG,ADC Minus-side Gain Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " MG ,Minus-side gain"
|
|
endif
|
|
group.long 0x34++0x1B
|
|
line.long 0x00 "ADC0_CLPD,ADC Plus-side General Calibration Value Register"
|
|
bitfld.long 0x00 0.--5. " CLPD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "ADC0_CLPS,ADC Plus-side General Calibration Value Register"
|
|
bitfld.long 0x04 0.--5. " CLPS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "ADC0_CLP4,ADC Plus-side General Calibration Value Register 4"
|
|
hexmask.long.word 0x08 0.--9. 1. " CLP4 ,Calibration value"
|
|
line.long 0x0C "ADC0_CLP3,ADC Plus-side General Calibration Value Register 3"
|
|
hexmask.long.word 0x0C 0.--8. 1. " CLP3 ,Calibration value"
|
|
line.long 0x10 "ADC0_CLP2,ADC Plus-side General Calibration Value Register 2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " CLP2 ,Calibration value"
|
|
line.long 0x14 "ADC0_CLP1,ADC Plus-side General Calibration Value Register 1"
|
|
hexmask.long.byte 0x14 0.--6. 1. " CLP1 ,Calibration value"
|
|
line.long 0x18 "ADC0_CLP0,ADC Plus-side General Calibration Value Register 0"
|
|
bitfld.long 0x18 0.--5. " CLP0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif !cpuis("MKL0*")&&!cpuis("MK14*")&&!cpuis("MKL14*")&&!cpuis("MKL24*")
|
|
group.long 0x54++0x1B
|
|
line.long 0x00 "ADC0_CLMD,ADC Minus-side General Calibration Value Register"
|
|
bitfld.long 0x00 0.--5. " CLMD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "ADC0_CLMS,ADC Minus-side General Calibration Value Register"
|
|
bitfld.long 0x04 0.--5. " CLMS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "ADC0_CLM4,ADC Minus-side General Calibration Value Register 4"
|
|
hexmask.long.word 0x08 0.--9. 1. " CLM4 ,Calibration value"
|
|
line.long 0x0C "ADC0_CLM3,ADC Minus-side General Calibration Value Register 3"
|
|
hexmask.long.word 0x0C 0.--8. 1. " CLM3 ,Calibration value"
|
|
line.long 0x10 "ADC0_CLM2,ADC Minus-side General Calibration Value Register 2"
|
|
hexmask.long.byte 0x10 0.--7. 1. " CLM2 ,Calibration value"
|
|
line.long 0x14 "ADC0_CLM1,ADC Minus-side General Calibration Value Register 1"
|
|
hexmask.long.byte 0x14 0.--6. 1. " CLM1 ,Calibration value"
|
|
line.long 0x18 "ADC0_CLM0,ADC Minus-side General Calibration Value Register 0"
|
|
bitfld.long 0x18 0.--5. " CLM0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
tree "CMP (Comparator)"
|
|
sif cpuis("MKL28Z*")
|
|
base ad:0x4006E000
|
|
width 7.
|
|
group.byte 0x0++0x05 "CMP_0"
|
|
line.byte 0x00 "CR0,CMP_0 Control Register 0"
|
|
bitfld.byte 0x00 4.--6. " FILTER_CNT ,Filter sample count" "Disabled,1 sample,2 samples,3 samples,4 samples,5 samples,6 samples,7 samples"
|
|
bitfld.byte 0x00 0.--1. " HYSTCTR ,Comparator hard block hysteresis control" "5 mv,10 mv,20 mv,30 mv"
|
|
line.byte 0x01 "CR1,CMP_0 Control Register 1"
|
|
bitfld.byte 0x01 7. " SE ,Sample enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " WE ,Windowing enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 5. " TRIGM ,Trigger mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed"
|
|
bitfld.byte 0x01 3. " INV ,Comparator invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA"
|
|
bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled"
|
|
line.byte 0x02 "FPR,CMP_0 Filter Period Register"
|
|
line.byte 0x03 "SCR,CMP_0 Status And Control Register"
|
|
bitfld.byte 0x03 6. " DMAEN ,DMA enable control" "Disabled,Enabled"
|
|
bitfld.byte 0x03 4. " IER ,Comparator interrupt enable rising" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x03 3. " IEF ,Comparator interrupt enable falling" "Disabled,Enabled"
|
|
eventfld.byte 0x03 2. " CFR ,Analog comparator flag rising" "Not occurred,Occurred"
|
|
eventfld.byte 0x03 1. " CFF ,Analog comparator flag falling" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.byte 0x03 0. " COUT ,Analog comparator output" "Low,High"
|
|
line.byte 0x04 "DACCR,DAC Control Register"
|
|
bitfld.byte 0x04 7. " DACEN ,DAC enable" "Disabled,Enabled"
|
|
bitfld.byte 0x04 6. " VRSEL ,Supply voltage reference source select" "Vin1,Vin2"
|
|
bitfld.byte 0x04 0.--5. " VOSEL ,DAC output voltage level select" "1/64 vin,2/64 vin,3/64 vin,4/64 vin,5/64 vin,6/64 vin,7/64 vin,8/64 vin,9/64 vin,10/64 vin,11/64 vin,12/64 vin,13/64 vin,14/64 vin,15/64 vin,16/64 vin,17/64 vin,18/64 vin,19/64 vin,20/64 vin,21/64 vin,22/64 vin,23/64 vin,24/64 vin,25/64 vin,26/64 vin,27/64 vin,28/64 vin,29/64 vin,30/64 vin,31/64 vin,32/64 vin,33/64 vin,34/64 vin,35/64 vin,36/64 vin,37/64 vin,38/64 vin,39/64 vin,40/64 vin,41/64 vin,42/64 vin,43/64 vin,44/64 vin,45/64 vin,46/64 vin,47/64 vin,48/64 vin,49/64 vin,50/64 vin,51/64 vin,52/64 vin,53/64 vin,54/64 vin,55/64 vin,56/64 vin,57/64 vin,58/64 vin,59/64 vin,60/64 vin,61/64 vin,62/64 vin,63/64 vin,Vin"
|
|
line.byte 0x05 "MUXCR,MUX Control Register"
|
|
bitfld.byte 0x05 6. " PSTM ,Pass through mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,Bandgap,6-bit DAC0 ref."
|
|
bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,Bandgap,6-bit DAC0 ref."
|
|
group.byte 0x8100++0x05 "CMP_1"
|
|
line.byte 0x00 "CR0,CMP_1 Control Register 0"
|
|
bitfld.byte 0x00 4.--6. " FILTER_CNT ,Filter sample count" "Disabled,1 sample,2 samples,3 samples,4 samples,5 samples,6 samples,7 samples"
|
|
bitfld.byte 0x00 0.--1. " HYSTCTR ,Comparator hard block hysteresis control" "5 mv,10 mv,20 mv,30 mv"
|
|
line.byte 0x01 "CR1,CMP_1 Control Register 1"
|
|
bitfld.byte 0x01 7. " SE ,Sample enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " WE ,Windowing enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 5. " TRIGM ,Trigger mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed"
|
|
bitfld.byte 0x01 3. " INV ,Comparator invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA"
|
|
bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled"
|
|
line.byte 0x02 "FPR,CMP_1 Filter Period Register"
|
|
line.byte 0x03 "SCR,CMP_1 Status And Control Register"
|
|
bitfld.byte 0x03 6. " DMAEN ,DMA enable control" "Disabled,Enabled"
|
|
bitfld.byte 0x03 4. " IER ,Comparator interrupt enable rising" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x03 3. " IEF ,Comparator interrupt enable falling" "Disabled,Enabled"
|
|
eventfld.byte 0x03 2. " CFR ,Analog comparator flag rising" "Not occurred,Occurred"
|
|
eventfld.byte 0x03 1. " CFF ,Analog comparator flag falling" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.byte 0x03 0. " COUT ,Analog comparator output" "Low,High"
|
|
line.byte 0x04 "DACCR,DAC Control Register"
|
|
bitfld.byte 0x04 7. " DACEN ,DAC enable" "Disabled,Enabled"
|
|
bitfld.byte 0x04 6. " VRSEL ,Supply voltage reference source select" "Vin1,Vin2"
|
|
bitfld.byte 0x04 0.--5. " VOSEL ,DAC output voltage level select" "1/64 vin,2/64 vin,3/64 vin,4/64 vin,5/64 vin,6/64 vin,7/64 vin,8/64 vin,9/64 vin,10/64 vin,11/64 vin,12/64 vin,13/64 vin,14/64 vin,15/64 vin,16/64 vin,17/64 vin,18/64 vin,19/64 vin,20/64 vin,21/64 vin,22/64 vin,23/64 vin,24/64 vin,25/64 vin,26/64 vin,27/64 vin,28/64 vin,29/64 vin,30/64 vin,31/64 vin,32/64 vin,33/64 vin,34/64 vin,35/64 vin,36/64 vin,37/64 vin,38/64 vin,39/64 vin,40/64 vin,41/64 vin,42/64 vin,43/64 vin,44/64 vin,45/64 vin,46/64 vin,47/64 vin,48/64 vin,49/64 vin,50/64 vin,51/64 vin,52/64 vin,53/64 vin,54/64 vin,55/64 vin,56/64 vin,57/64 vin,58/64 vin,59/64 vin,60/64 vin,61/64 vin,62/64 vin,63/64 vin,Vin"
|
|
line.byte 0x05 "MUXCR,MUX Control Register"
|
|
bitfld.byte 0x05 6. " PSTM ,Pass through mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,Bandgap,6-bit DAC0 ref."
|
|
bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,Bandgap,6-bit DAC0 ref."
|
|
width 0x0B
|
|
else
|
|
base ad:0x40073000
|
|
width 7.
|
|
group.byte 0x00++0x05
|
|
line.byte 0x00 "CR0,CMP Control Register 0"
|
|
bitfld.byte 0x00 4.--6. " FILTER_CNT ,Filter sample count" "Disabled,1 sample,2 samples,3 samples,4 samples,5 samples,6 samples,7 samples"
|
|
bitfld.byte 0x00 0.--1. " HYSTCTR ,Comparator hard block hysteresis control" "5 mv,10 mv,20 mv,30 mv"
|
|
line.byte 0x01 "CR1,CMP Control Register 1"
|
|
bitfld.byte 0x01 7. " SE ,Sample enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " WE ,Windowing enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 5. " TRIGM ,Trigger mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed"
|
|
bitfld.byte 0x01 3. " INV ,Comparator invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA"
|
|
bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled"
|
|
line.byte 0x02 "FPR,CMP Filter Period Register"
|
|
line.byte 0x03 "SCR,CMP Status And Control Register"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03*")
|
|
bitfld.byte 0x03 6. " DMAEN ,DMA enable control" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x03 4. " IER ,Comparator interrupt enable rising" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x03 3. " IEF ,Comparator interrupt enable falling" "Disabled,Enabled"
|
|
eventfld.byte 0x03 2. " CFR ,Analog comparator flag rising" "Not occurred,Occurred"
|
|
eventfld.byte 0x03 1. " CFF ,Analog comparator flag falling" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.byte 0x03 0. " COUT ,Analog comparator output" "Low,High"
|
|
line.byte 0x04 "DACCR,DAC Control Register"
|
|
bitfld.byte 0x04 7. " DACEN ,DAC enable" "Disabled,Enabled"
|
|
bitfld.byte 0x04 6. " VRSEL ,Supply voltage reference source select" "Vin1,Vin2"
|
|
bitfld.byte 0x04 0.--5. " VOSEL ,DAC output voltage level select" "1/64 vin,2/64 vin,3/64 vin,4/64 vin,5/64 vin,6/64 vin,7/64 vin,8/64 vin,9/64 vin,10/64 vin,11/64 vin,12/64 vin,13/64 vin,14/64 vin,15/64 vin,16/64 vin,17/64 vin,18/64 vin,19/64 vin,20/64 vin,21/64 vin,22/64 vin,23/64 vin,24/64 vin,25/64 vin,26/64 vin,27/64 vin,28/64 vin,29/64 vin,30/64 vin,31/64 vin,32/64 vin,33/64 vin,34/64 vin,35/64 vin,36/64 vin,37/64 vin,38/64 vin,39/64 vin,40/64 vin,41/64 vin,42/64 vin,43/64 vin,44/64 vin,45/64 vin,46/64 vin,47/64 vin,48/64 vin,49/64 vin,50/64 vin,51/64 vin,52/64 vin,53/64 vin,54/64 vin,55/64 vin,56/64 vin,57/64 vin,58/64 vin,59/64 vin,60/64 vin,61/64 vin,62/64 vin,63/64 vin,Vin"
|
|
line.byte 0x05 "MUXCR,MUX Control Register"
|
|
sif cpuis("MKL03*VFG*")
|
|
bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" ",IN1,IN2,IN3,,IN5,Bandgap,6-bit DAC0 ref."
|
|
bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" ",IN1,IN2,IN3,,IN5,Bandgap,6-bit DAC0 ref."
|
|
elif cpuis("MKL03Z*")
|
|
bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,,IN5,Bandgap,6-bit DAC0 ref."
|
|
bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" ",IN1,IN2,IN3,,IN5,Bandgap,6-bit DAC0 ref."
|
|
elif cpuis("MKL03*VFK*")||cpuis("MKL03*CAF*")
|
|
bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,,IN5,Bandgap,6-bit DAC0 ref."
|
|
bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,,IN5,Bandgap,6-bit DAC0 ref."
|
|
elif cpuis("MKL0*VFG*")
|
|
bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" ",IN1,IN2,IN3,,,Bandgap,6-bit DAC0 ref."
|
|
bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" ",IN1,IN2,IN3,,,Bandgap,6-bit DAC0 ref."
|
|
elif cpuis("MKL0*VFM*")||cpuis("MKL0*VFK*")||cpuis("MKL0*CAF*")||cpuis("MKL0*VLH*")||cpuis("MKL0*VLK*")
|
|
bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,,,Bandgap,6-bit DAC0 ref."
|
|
bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,,,Bandgap,6-bit DAC0 ref."
|
|
elif cpuis("*VFM*")||cpuis("MKL26*CAL*")||cpuis("MKL17*VDA*")||cpuis("MKL27*VDA*")
|
|
bitfld.byte 0x05 6. " PSTM ,Pass through mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,,IN4,,Bandgap,6-bit DAC0 ref."
|
|
bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,,IN4,,Bandgap,6-bit DAC0 ref."
|
|
elif cpuis("*VFT*")||cpuis("MKL15*CAD*")||cpuis("MKL2*VLH*")||cpuis("MKL2*VMP*")||cpuis("MKL3*VLH*")||cpuis("MKL3*VMP*")||cpuis("MKL4*VLH*")||cpuis("MKL4*VMP*")
|
|
bitfld.byte 0x05 6. " PSTM ,Pass through mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,,IN4,IN5,Bandgap,6-bit DAC0 ref."
|
|
bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,,IN4,IN5,Bandgap,6-bit DAC0 ref."
|
|
else
|
|
bitfld.byte 0x05 6. " PSTM ,Pass through mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,Bandgap,6-bit DAC0 ref."
|
|
bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,Bandgap,6-bit DAC0 ref."
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
sif cpuis("MKL03Z*")||cpuis("MKL13Z*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL28Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MKL82Z*")
|
|
tree "VREF (Voltage Reference)"
|
|
sif cpuis("MKL28Z*")
|
|
base ad:0x40072000
|
|
width 6.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "TRM,VREF Trim Register"
|
|
bitfld.byte 0x00 6. " CHOPEN ,Chop oscillator enable" "Disabled,Enabled"
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.byte 0x00 0.--5. " TRIM ,Trim bits" "Min,Max-(31mV),2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,Max"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " TRIM ,Trim bits" "Min,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,Max"
|
|
endif
|
|
if (((per.b(ad:0x40072000)&0x40))==0x40)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SC,VREF Status And Control Register"
|
|
bitfld.byte 0x00 7. " VREFEN ,Internal voltage reference enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " REGEN ,1.75 V regulator enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " ICOMPEN ,Second order curvature compensation enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.byte 0x00 4. " TRESEN ,Test second order curvature compensation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TMUXEN ,Test MUX enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--1. " MODE_LV ,Buffer mode selection" "Bandgap,High power buffer,Low-power buffer,?..."
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SC,VREF Status And Control Register"
|
|
bitfld.byte 0x00 7. " VREFEN ,Internal voltage reference enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " REGEN ,1.75 V regulator enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " ICOMPEN ,Second order curvature compensation enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.byte 0x00 4. " TRESEN ,Test second order curvature compensation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TMUXEN ,Test MUX enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.byte 0x00 2. " VREFST ,Internal voltage reference stable" "Not stable,Stable"
|
|
bitfld.byte 0x00 0.--1. " MODE_LV ,Buffer mode selection" "Bandgap,High power buffer,Low-power buffer,?..."
|
|
endif
|
|
sif cpuis("K32W0?2S1M*")||cpuis("MKL28Z*")
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "TRM4,VREF Trim 2.1V Register"
|
|
sif (cpuis("MKL28Z*")||cpuis("K32W0?2S1M*"))
|
|
bitfld.byte 0x00 7. " VREF2V1_EN ,Internal voltage reference (2.1V) enable" "Enabled,Disabled"
|
|
else
|
|
bitfld.byte 0x00 6. " VREF2V1_EN ,Internal voltage reference (2.1V) enable" "Enabled,Disabled"
|
|
endif
|
|
bitfld.byte 0x00 0.--5. " TRIM2V1 ,VREF 2.1V trim bits" "Min,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,Max"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
base ad:0x40074000
|
|
width 6.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "TRM,VREF Trim Register"
|
|
bitfld.byte 0x00 6. " CHOPEN ,Chop oscillator enable" "Disabled,Enabled"
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.byte 0x00 0.--5. " TRIM ,Trim bits" "Min,Max-(31mV),2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,Max"
|
|
else
|
|
bitfld.byte 0x00 0.--5. " TRIM ,Trim bits" "Min,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,Max"
|
|
endif
|
|
if (((per.b(ad:0x40074000)&0x40))==0x40)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SC,VREF Status And Control Register"
|
|
bitfld.byte 0x00 7. " VREFEN ,Internal voltage reference enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " REGEN ,1.75 V regulator enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " ICOMPEN ,Second order curvature compensation enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.byte 0x00 4. " TRESEN ,Test second order curvature compensation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TMUXEN ,Test MUX enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 0.--1. " MODE_LV ,Buffer mode selection" "Bandgap,High power buffer,Low-power buffer,?..."
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SC,VREF Status And Control Register"
|
|
bitfld.byte 0x00 7. " VREFEN ,Internal voltage reference enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " REGEN ,1.75 V regulator enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " ICOMPEN ,Second order curvature compensation enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.byte 0x00 4. " TRESEN ,Test second order curvature compensation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TMUXEN ,Test MUX enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.byte 0x00 2. " VREFST ,Internal voltage reference stable" "Not stable,Stable"
|
|
bitfld.byte 0x00 0.--1. " MODE_LV ,Buffer mode selection" "Bandgap,High power buffer,Low-power buffer,?..."
|
|
endif
|
|
sif cpuis("K32W0?2S1M*")||cpuis("MKL28Z*")
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "TRM4,VREF Trim 2.1V Register"
|
|
sif (cpuis("MKL28Z*")||cpuis("K32W0?2S1M*"))
|
|
bitfld.byte 0x00 7. " VREF2V1_EN ,Internal voltage reference (2.1V) enable" "Enabled,Disabled"
|
|
else
|
|
bitfld.byte 0x00 6. " VREF2V1_EN ,Internal voltage reference (2.1V) enable" "Enabled,Disabled"
|
|
endif
|
|
bitfld.byte 0x00 0.--5. " TRIM2V1 ,VREF 2.1V trim bits" "Min,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,Max"
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("MKL05*")||cpuis("MKL13*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL27Z128*")||cpuis("MKL27Z256*")||cpuis("MKL33Z*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL43Z*")||cpuis("MKL46Z*")||cpuis("MKL82Z*")||cpuis("KKL15*")||cpuis("MKL28Z*")
|
|
tree "DAC (Digital-to-Analog Converter)"
|
|
sif cpuis("MKL28Z*")
|
|
base ad:0x4006A000
|
|
width 16.
|
|
sif (cpu()=="MK20DX64VMC7")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")
|
|
group.byte 0x0++0x00
|
|
line.byte 0x00 "DAC0_DAT0L,DAC Data Low Register"
|
|
group.byte 0x2++0x00
|
|
line.byte 0x00 "DAC0_DAT1L,DAC Data Low Register"
|
|
group.byte 0x4++0x00
|
|
line.byte 0x00 "DAC0_DAT2L,DAC Data Low Register"
|
|
group.byte 0x6++0x00
|
|
line.byte 0x00 "DAC0_DAT3L,DAC Data Low Register"
|
|
group.byte 0x8++0x00
|
|
line.byte 0x00 "DAC0_DAT4L,DAC Data Low Register"
|
|
group.byte 0xA++0x00
|
|
line.byte 0x00 "DAC0_DAT5L,DAC Data Low Register"
|
|
group.byte 0xC++0x00
|
|
line.byte 0x00 "DAC0_DAT6L,DAC Data Low Register"
|
|
group.byte 0xE++0x00
|
|
line.byte 0x00 "DAC0_DAT7L,DAC Data Low Register"
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "DAC0_DAT8L,DAC Data Low Register"
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "DAC0_DAT9L,DAC Data Low Register"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "DAC0_DAT10L,DAC Data Low Register"
|
|
group.byte 0x16++0x00
|
|
line.byte 0x00 "DAC0_DAT11L,DAC Data Low Register"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "DAC0_DAT12L,DAC Data Low Register"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "DAC0_DAT13L,DAC Data Low Register"
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "DAC0_DAT14L,DAC Data Low Register"
|
|
group.byte 0x1E++0x00
|
|
line.byte 0x00 "DAC0_DAT15L,DAC Data Low Register"
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "DAC0_DATH,DAC Data High Register"
|
|
hexmask.byte 0x00 0.--3. 1. " DATA[11:8] ,Data bits"
|
|
elif cpuis("MK28Z*")||cpuis("MKL82Z*")||cpuis("MKL05*")||cpuis("MKL13*")||cpuis("MK15*")||cpuis("KKL15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL27Z128*")||cpuis("MKL27Z256*")||cpuis("MKL33Z*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL43Z*")||cpuis("MKL46Z*")
|
|
group.byte 0x0++0x01
|
|
line.byte 0x00 "DAC0_DAT0L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DATA_0[7:0] ,Data bits"
|
|
line.byte 0x01 "DAC0_DAT0H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_0[11:8] ,Data bits"
|
|
group.byte 0x2++0x01
|
|
line.byte 0x00 "DAC0_DAT1L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DATA_1[7:0] ,Data bits"
|
|
line.byte 0x01 "DAC0_DAT1H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_1[11:8] ,Data bits"
|
|
group.byte 0x4++0x01
|
|
line.byte 0x00 "DAC0_DAT2L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DATA_2[7:0] ,Data bits"
|
|
line.byte 0x01 "DAC0_DAT2H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_2[11:8] ,Data bits"
|
|
group.byte 0x6++0x01
|
|
line.byte 0x00 "DAC0_DAT3L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DATA_3[7:0] ,Data bits"
|
|
line.byte 0x01 "DAC0_DAT3H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_3[11:8] ,Data bits"
|
|
group.byte 0x8++0x01
|
|
line.byte 0x00 "DAC0_DAT4L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DATA_4[7:0] ,Data bits"
|
|
line.byte 0x01 "DAC0_DAT4H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_4[11:8] ,Data bits"
|
|
group.byte 0xA++0x01
|
|
line.byte 0x00 "DAC0_DAT5L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DATA_5[7:0] ,Data bits"
|
|
line.byte 0x01 "DAC0_DAT5H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_5[11:8] ,Data bits"
|
|
group.byte 0xC++0x01
|
|
line.byte 0x00 "DAC0_DAT6L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DATA_6[7:0] ,Data bits"
|
|
line.byte 0x01 "DAC0_DAT6H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_6[11:8] ,Data bits"
|
|
group.byte 0xE++0x01
|
|
line.byte 0x00 "DAC0_DAT7L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DATA_7[7:0] ,Data bits"
|
|
line.byte 0x01 "DAC0_DAT7H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_7[11:8] ,Data bits"
|
|
group.byte 0x10++0x01
|
|
line.byte 0x00 "DAC0_DAT8L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DATA_8[7:0] ,Data bits"
|
|
line.byte 0x01 "DAC0_DAT8H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_8[11:8] ,Data bits"
|
|
group.byte 0x12++0x01
|
|
line.byte 0x00 "DAC0_DAT9L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DATA_9[7:0] ,Data bits"
|
|
line.byte 0x01 "DAC0_DAT9H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_9[11:8] ,Data bits"
|
|
group.byte 0x14++0x01
|
|
line.byte 0x00 "DAC0_DAT10L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DATA_10[7:0] ,Data bits"
|
|
line.byte 0x01 "DAC0_DAT10H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_10[11:8] ,Data bits"
|
|
group.byte 0x16++0x01
|
|
line.byte 0x00 "DAC0_DAT11L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DATA_11[7:0] ,Data bits"
|
|
line.byte 0x01 "DAC0_DAT11H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_11[11:8] ,Data bits"
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "DAC0_DAT12L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DATA_12[7:0] ,Data bits"
|
|
line.byte 0x01 "DAC0_DAT12H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_12[11:8] ,Data bits"
|
|
group.byte 0x1A++0x01
|
|
line.byte 0x00 "DAC0_DAT13L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DATA_13[7:0] ,Data bits"
|
|
line.byte 0x01 "DAC0_DAT13H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_13[11:8] ,Data bits"
|
|
group.byte 0x1C++0x01
|
|
line.byte 0x00 "DAC0_DAT14L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DATA_14[7:0] ,Data bits"
|
|
line.byte 0x01 "DAC0_DAT14H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_14[11:8] ,Data bits"
|
|
group.byte 0x1E++0x01
|
|
line.byte 0x00 "DAC0_DAT15L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DATA_15[7:0] ,Data bits"
|
|
line.byte 0x01 "DAC0_DAT15H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_15[11:8] ,Data bits"
|
|
else
|
|
group.byte 0x0++0x01
|
|
line.byte 0x00 "DAC0_DAT0L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT0H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_0[11:8] ,Data bits"
|
|
group.byte 0x2++0x01
|
|
line.byte 0x00 "DAC0_DAT1L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT1H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_1[11:8] ,Data bits"
|
|
group.byte 0x4++0x01
|
|
line.byte 0x00 "DAC0_DAT2L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT2H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_2[11:8] ,Data bits"
|
|
group.byte 0x6++0x01
|
|
line.byte 0x00 "DAC0_DAT3L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT3H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_3[11:8] ,Data bits"
|
|
group.byte 0x8++0x01
|
|
line.byte 0x00 "DAC0_DAT4L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT4H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_4[11:8] ,Data bits"
|
|
group.byte 0xA++0x01
|
|
line.byte 0x00 "DAC0_DAT5L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT5H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_5[11:8] ,Data bits"
|
|
group.byte 0xC++0x01
|
|
line.byte 0x00 "DAC0_DAT6L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT6H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_6[11:8] ,Data bits"
|
|
group.byte 0xE++0x01
|
|
line.byte 0x00 "DAC0_DAT7L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT7H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_7[11:8] ,Data bits"
|
|
group.byte 0x10++0x01
|
|
line.byte 0x00 "DAC0_DAT8L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT8H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_8[11:8] ,Data bits"
|
|
group.byte 0x12++0x01
|
|
line.byte 0x00 "DAC0_DAT9L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT9H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_9[11:8] ,Data bits"
|
|
group.byte 0x14++0x01
|
|
line.byte 0x00 "DAC0_DAT10L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT10H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_10[11:8] ,Data bits"
|
|
group.byte 0x16++0x01
|
|
line.byte 0x00 "DAC0_DAT11L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT11H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_11[11:8] ,Data bits"
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "DAC0_DAT12L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT12H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_12[11:8] ,Data bits"
|
|
group.byte 0x1A++0x01
|
|
line.byte 0x00 "DAC0_DAT13L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT13H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_13[11:8] ,Data bits"
|
|
group.byte 0x1C++0x01
|
|
line.byte 0x00 "DAC0_DAT14L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT14H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_14[11:8] ,Data bits"
|
|
group.byte 0x1E++0x01
|
|
line.byte 0x00 "DAC0_DAT15L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT15H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_15[11:8] ,Data bits"
|
|
endif
|
|
newline
|
|
sif cpuis("MKL05*")||cpuis("MKL13*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("KKL15*")||cpuis("MKL16*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL27Z128*")||cpuis("MKL27Z256*")||cpuis("MKL33Z*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL43Z*")||cpuis("MKL46Z*")
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "DAC0_SR,DAC Status Register"
|
|
bitfld.byte 0x00 1. " DACBFRPTF ,DAC buffer read pointer top position flag" "Non-zero,Zero"
|
|
bitfld.byte 0x00 0. " DACBFRPBF ,DAC buffer read pointer bottom position flag" "Not equal DACBFUP,Equal DACBFUP"
|
|
elif (cpu()=="MK40DN512ZVLQ10")||(cpu()=="MK40DN512ZVMD10")||(cpu()=="MK40DX128ZVLQ10")||(cpu()=="MK40DX256ZVLQ10")||(cpu()=="MK40DX256ZVMD10")||(cpu()=="MK40DN512ZVLL10")||cpuis("MK28Z*")||cpuis("MKL82Z*")
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "DAC0_SR,DAC Status Register"
|
|
bitfld.byte 0x00 2. " DACBFWMF ,DAC buffer watermark flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " DACBFRPTF ,DAC buffer read pointer top position flag" "Non-zero,Zero"
|
|
bitfld.byte 0x00 0. " DACBFRPBF ,DAC buffer read pointer bottom position flag" "Not equal DACBFUP,Equal DACBFUP"
|
|
else
|
|
rgroup.byte 0x20++0x00
|
|
line.byte 0x00 "DAC0_SR,DAC Status Register"
|
|
bitfld.byte 0x00 2. " DACBFWMF ,DAC buffer watermark flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " DACBFRPTF ,DAC buffer read pointer top position flag" "Non-zero,Zero"
|
|
bitfld.byte 0x00 0. " DACBFRPBF ,DAC buffer read pointer bottom position flag" "Not equal DACBFUP,Equal DACBFUP"
|
|
endif
|
|
group.byte 0x21++0x02
|
|
line.byte 0x00 "DAC0_C0,DAC Control Register"
|
|
bitfld.byte 0x00 7. " DACEN ,DAC enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpu()=="MK20DN512ZAB10")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK21DX128VLK5")||(cpu()=="MK21DX256VLK5")||(cpu()=="MK21DN512VLK5")||(cpu()=="MK21DX128VMC5")||(cpu()=="MK21DX256VMC5")||(cpu()=="MK21DN512VMC5")||(cpu()=="MK22DX128VLH5")||(cpu()=="MK22DX256VLH5")||(cpu()=="MK22DN512VLH5")||(cpu()=="MK22DX128VLK5")||(cpu()=="MK22DX256VLK5")||(cpu()=="MK22DN512VLK5")||(cpu()=="MK22DX128VMC5")||(cpu()=="MK22DX256VMC5")||(cpu()=="MK22DN512VMC5")||(cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||cpuis("MKL05*")||cpuis("MKL13*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL27Z128*")||cpuis("MKL27Z256*")||cpuis("MKL33Z*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL43Z*")||cpuis("MKL46Z*")||(cpu()=="MK40DN512ZVLL10")||(cpu()=="MK40DN512ZVLQ10")||(cpu()=="MK40DN512ZVMD10")||(cpu()=="MK40DX128ZVLQ10")||(cpu()=="MK40DX256ZVLQ10")||(cpu()=="MK40DX256ZVMD10")||cpuis("MK28Z*")||cpuis("MKL82Z*")
|
|
bitfld.byte 0x00 6. " DACRFS ,DAC reference select" "DACREF_1,DACREF_2"
|
|
newline
|
|
else
|
|
bitfld.byte 0x00 6. " DACRFS ,DAC reference select" "Internal,External"
|
|
newline
|
|
endif
|
|
bitfld.byte 0x00 5. " DACTRGSEL ,DAC trigger select" "Hardware,Software"
|
|
sif (cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")
|
|
newline
|
|
rbitfld.byte 0x00 4. " DACSWTRG ,DAC software trigger" "Not valid,Valid"
|
|
elif cpuis("MKL05*")||cpuis("MKL13*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("KKL15*")||cpuis("MKL16*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL27Z128*")||cpuis("MKL27Z256*")||cpuis("MKL33Z*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL43Z*")||cpuis("MKL46Z*")||cpuis("MK28Z*")||cpuis("MKL82Z*")
|
|
newline
|
|
bitfld.byte 0x00 4. " DACSWTRG ,DAC software trigger" "No effect,Trigger"
|
|
else
|
|
newline
|
|
bitfld.byte 0x00 4. " DACSWTRG ,DAC software trigger" "Not valid,Valid"
|
|
endif
|
|
newline
|
|
bitfld.byte 0x00 3. " LPEN ,DAC low power control" "High-power,Low-power"
|
|
sif !cpuis("MKL05*")&&!cpuis("MKL13*")&&!cpuis("MK15*")&&!cpuis("MKL15*")&&!cpuis("KKL15*")&&!cpuis("MKL16*")&&!cpuis("MKL17Z128*")&&!cpuis("MKL17Z256*")&&!cpuis("MKL25*")&&!cpuis("MKL26*")&&!cpuis("MKL27Z128*")&&!cpuis("MKL27Z256*")&&!cpuis("MKL33Z*")&&!cpuis("MKL34Z*")&&!cpuis("MKL36Z*")&&!cpuis("MKL43Z*")&&!cpuis("MKL46Z*")
|
|
bitfld.byte 0x00 2. " DACBWIEN ,DAC buffer watermark interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.byte 0x00 1. " DACBTIEN ,DAC buffer read pointer top flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " DACBBIEN ,DAC buffer read pointer bottom flag interrupt enable" "Disabled,Enabled"
|
|
line.byte 0x01 "DAC0_C1,DAC Control Register 1"
|
|
bitfld.byte 0x01 7. " DMAEN ,DMA enable select" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("MKL05*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("KKL15*")||cpuis("MKL16*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")
|
|
bitfld.byte 0x01 2. " DACBFMD ,DAC buffer work mode select" "Normal,One-time scan"
|
|
newline
|
|
elif cpuis("MKL13*")||cpuis("MKL17Z*")||cpuis("MKL27Z128*")||cpuis("MKL27Z256*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")
|
|
bitfld.byte 0x01 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,,One-time scan,FIFO mode"
|
|
newline
|
|
else
|
|
bitfld.byte 0x01 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,3 words,4 words"
|
|
bitfld.byte 0x01 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-time scan,?..."
|
|
newline
|
|
endif
|
|
bitfld.byte 0x01 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled"
|
|
line.byte 0x02 "DAC0_C2,DAC Control Register 2"
|
|
sif cpuis("MKL05*")||cpuis("MKL13*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("KKL15*")||cpuis("MKL16*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL27Z128*")||cpuis("MKL27Z256*")||cpuis("MKL33Z*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL43Z*")||cpuis("MKL46Z*")
|
|
bitfld.byte 0x02 4. " DACBFRP ,DAC buffer read pointer. Keeps the current value of the buffer read pointer" "0,1"
|
|
bitfld.byte 0x02 0. " DACBFUP ,DAC buffer upper limit. Selects the upper limit of the DAC buffer" "0,1"
|
|
else
|
|
bitfld.byte 0x02 4.--7. " DACBFRP ,DAC buffer read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x02 0.--3. " DACBFUP ,DAC buffer upper limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
base ad:0x4003F000
|
|
width 16.
|
|
sif (cpu()=="MK20DX64VMC7")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")
|
|
group.byte 0x0++0x00
|
|
line.byte 0x00 "DAC0_DAT0L,DAC Data Low Register"
|
|
group.byte 0x2++0x00
|
|
line.byte 0x00 "DAC0_DAT1L,DAC Data Low Register"
|
|
group.byte 0x4++0x00
|
|
line.byte 0x00 "DAC0_DAT2L,DAC Data Low Register"
|
|
group.byte 0x6++0x00
|
|
line.byte 0x00 "DAC0_DAT3L,DAC Data Low Register"
|
|
group.byte 0x8++0x00
|
|
line.byte 0x00 "DAC0_DAT4L,DAC Data Low Register"
|
|
group.byte 0xA++0x00
|
|
line.byte 0x00 "DAC0_DAT5L,DAC Data Low Register"
|
|
group.byte 0xC++0x00
|
|
line.byte 0x00 "DAC0_DAT6L,DAC Data Low Register"
|
|
group.byte 0xE++0x00
|
|
line.byte 0x00 "DAC0_DAT7L,DAC Data Low Register"
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "DAC0_DAT8L,DAC Data Low Register"
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "DAC0_DAT9L,DAC Data Low Register"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "DAC0_DAT10L,DAC Data Low Register"
|
|
group.byte 0x16++0x00
|
|
line.byte 0x00 "DAC0_DAT11L,DAC Data Low Register"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "DAC0_DAT12L,DAC Data Low Register"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "DAC0_DAT13L,DAC Data Low Register"
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "DAC0_DAT14L,DAC Data Low Register"
|
|
group.byte 0x1E++0x00
|
|
line.byte 0x00 "DAC0_DAT15L,DAC Data Low Register"
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "DAC0_DATH,DAC Data High Register"
|
|
hexmask.byte 0x00 0.--3. 1. " DATA[11:8] ,Data bits"
|
|
elif cpuis("MK28Z*")||cpuis("MKL82Z*")||cpuis("MKL05*")||cpuis("MKL13*")||cpuis("MK15*")||cpuis("KKL15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL27Z128*")||cpuis("MKL27Z256*")||cpuis("MKL33Z*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL43Z*")||cpuis("MKL46Z*")
|
|
group.byte 0x0++0x01
|
|
line.byte 0x00 "DAC0_DAT0L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DATA_0[7:0] ,Data bits"
|
|
line.byte 0x01 "DAC0_DAT0H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_0[11:8] ,Data bits"
|
|
group.byte 0x2++0x01
|
|
line.byte 0x00 "DAC0_DAT1L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DATA_1[7:0] ,Data bits"
|
|
line.byte 0x01 "DAC0_DAT1H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_1[11:8] ,Data bits"
|
|
group.byte 0x4++0x01
|
|
line.byte 0x00 "DAC0_DAT2L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DATA_2[7:0] ,Data bits"
|
|
line.byte 0x01 "DAC0_DAT2H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_2[11:8] ,Data bits"
|
|
group.byte 0x6++0x01
|
|
line.byte 0x00 "DAC0_DAT3L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DATA_3[7:0] ,Data bits"
|
|
line.byte 0x01 "DAC0_DAT3H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_3[11:8] ,Data bits"
|
|
group.byte 0x8++0x01
|
|
line.byte 0x00 "DAC0_DAT4L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DATA_4[7:0] ,Data bits"
|
|
line.byte 0x01 "DAC0_DAT4H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_4[11:8] ,Data bits"
|
|
group.byte 0xA++0x01
|
|
line.byte 0x00 "DAC0_DAT5L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DATA_5[7:0] ,Data bits"
|
|
line.byte 0x01 "DAC0_DAT5H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_5[11:8] ,Data bits"
|
|
group.byte 0xC++0x01
|
|
line.byte 0x00 "DAC0_DAT6L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DATA_6[7:0] ,Data bits"
|
|
line.byte 0x01 "DAC0_DAT6H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_6[11:8] ,Data bits"
|
|
group.byte 0xE++0x01
|
|
line.byte 0x00 "DAC0_DAT7L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DATA_7[7:0] ,Data bits"
|
|
line.byte 0x01 "DAC0_DAT7H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_7[11:8] ,Data bits"
|
|
group.byte 0x10++0x01
|
|
line.byte 0x00 "DAC0_DAT8L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DATA_8[7:0] ,Data bits"
|
|
line.byte 0x01 "DAC0_DAT8H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_8[11:8] ,Data bits"
|
|
group.byte 0x12++0x01
|
|
line.byte 0x00 "DAC0_DAT9L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DATA_9[7:0] ,Data bits"
|
|
line.byte 0x01 "DAC0_DAT9H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_9[11:8] ,Data bits"
|
|
group.byte 0x14++0x01
|
|
line.byte 0x00 "DAC0_DAT10L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DATA_10[7:0] ,Data bits"
|
|
line.byte 0x01 "DAC0_DAT10H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_10[11:8] ,Data bits"
|
|
group.byte 0x16++0x01
|
|
line.byte 0x00 "DAC0_DAT11L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DATA_11[7:0] ,Data bits"
|
|
line.byte 0x01 "DAC0_DAT11H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_11[11:8] ,Data bits"
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "DAC0_DAT12L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DATA_12[7:0] ,Data bits"
|
|
line.byte 0x01 "DAC0_DAT12H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_12[11:8] ,Data bits"
|
|
group.byte 0x1A++0x01
|
|
line.byte 0x00 "DAC0_DAT13L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DATA_13[7:0] ,Data bits"
|
|
line.byte 0x01 "DAC0_DAT13H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_13[11:8] ,Data bits"
|
|
group.byte 0x1C++0x01
|
|
line.byte 0x00 "DAC0_DAT14L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DATA_14[7:0] ,Data bits"
|
|
line.byte 0x01 "DAC0_DAT14H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_14[11:8] ,Data bits"
|
|
group.byte 0x1E++0x01
|
|
line.byte 0x00 "DAC0_DAT15L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DATA_15[7:0] ,Data bits"
|
|
line.byte 0x01 "DAC0_DAT15H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_15[11:8] ,Data bits"
|
|
else
|
|
group.byte 0x0++0x01
|
|
line.byte 0x00 "DAC0_DAT0L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT0H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_0[11:8] ,Data bits"
|
|
group.byte 0x2++0x01
|
|
line.byte 0x00 "DAC0_DAT1L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT1H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_1[11:8] ,Data bits"
|
|
group.byte 0x4++0x01
|
|
line.byte 0x00 "DAC0_DAT2L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT2H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_2[11:8] ,Data bits"
|
|
group.byte 0x6++0x01
|
|
line.byte 0x00 "DAC0_DAT3L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT3H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_3[11:8] ,Data bits"
|
|
group.byte 0x8++0x01
|
|
line.byte 0x00 "DAC0_DAT4L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT4H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_4[11:8] ,Data bits"
|
|
group.byte 0xA++0x01
|
|
line.byte 0x00 "DAC0_DAT5L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT5H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_5[11:8] ,Data bits"
|
|
group.byte 0xC++0x01
|
|
line.byte 0x00 "DAC0_DAT6L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT6H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_6[11:8] ,Data bits"
|
|
group.byte 0xE++0x01
|
|
line.byte 0x00 "DAC0_DAT7L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT7H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_7[11:8] ,Data bits"
|
|
group.byte 0x10++0x01
|
|
line.byte 0x00 "DAC0_DAT8L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT8H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_8[11:8] ,Data bits"
|
|
group.byte 0x12++0x01
|
|
line.byte 0x00 "DAC0_DAT9L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT9H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_9[11:8] ,Data bits"
|
|
group.byte 0x14++0x01
|
|
line.byte 0x00 "DAC0_DAT10L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT10H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_10[11:8] ,Data bits"
|
|
group.byte 0x16++0x01
|
|
line.byte 0x00 "DAC0_DAT11L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT11H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_11[11:8] ,Data bits"
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "DAC0_DAT12L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT12H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_12[11:8] ,Data bits"
|
|
group.byte 0x1A++0x01
|
|
line.byte 0x00 "DAC0_DAT13L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT13H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_13[11:8] ,Data bits"
|
|
group.byte 0x1C++0x01
|
|
line.byte 0x00 "DAC0_DAT14L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT14H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_14[11:8] ,Data bits"
|
|
group.byte 0x1E++0x01
|
|
line.byte 0x00 "DAC0_DAT15L,DAC Data Low Register"
|
|
line.byte 0x01 "DAC0_DAT15H,DAC Data High Register"
|
|
hexmask.byte 0x01 0.--3. 1. " DATA_15[11:8] ,Data bits"
|
|
endif
|
|
newline
|
|
sif cpuis("MKL05*")||cpuis("MKL13*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("KKL15*")||cpuis("MKL16*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL27Z128*")||cpuis("MKL27Z256*")||cpuis("MKL33Z*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL43Z*")||cpuis("MKL46Z*")
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "DAC0_SR,DAC Status Register"
|
|
bitfld.byte 0x00 1. " DACBFRPTF ,DAC buffer read pointer top position flag" "Non-zero,Zero"
|
|
bitfld.byte 0x00 0. " DACBFRPBF ,DAC buffer read pointer bottom position flag" "Not equal DACBFUP,Equal DACBFUP"
|
|
elif (cpu()=="MK40DN512ZVLQ10")||(cpu()=="MK40DN512ZVMD10")||(cpu()=="MK40DX128ZVLQ10")||(cpu()=="MK40DX256ZVLQ10")||(cpu()=="MK40DX256ZVMD10")||(cpu()=="MK40DN512ZVLL10")||cpuis("MK28Z*")||cpuis("MKL82Z*")
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "DAC0_SR,DAC Status Register"
|
|
bitfld.byte 0x00 2. " DACBFWMF ,DAC buffer watermark flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " DACBFRPTF ,DAC buffer read pointer top position flag" "Non-zero,Zero"
|
|
bitfld.byte 0x00 0. " DACBFRPBF ,DAC buffer read pointer bottom position flag" "Not equal DACBFUP,Equal DACBFUP"
|
|
else
|
|
rgroup.byte 0x20++0x00
|
|
line.byte 0x00 "DAC0_SR,DAC Status Register"
|
|
bitfld.byte 0x00 2. " DACBFWMF ,DAC buffer watermark flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " DACBFRPTF ,DAC buffer read pointer top position flag" "Non-zero,Zero"
|
|
bitfld.byte 0x00 0. " DACBFRPBF ,DAC buffer read pointer bottom position flag" "Not equal DACBFUP,Equal DACBFUP"
|
|
endif
|
|
group.byte 0x21++0x02
|
|
line.byte 0x00 "DAC0_C0,DAC Control Register"
|
|
bitfld.byte 0x00 7. " DACEN ,DAC enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpu()=="MK20DN512ZAB10")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK21DX128VLK5")||(cpu()=="MK21DX256VLK5")||(cpu()=="MK21DN512VLK5")||(cpu()=="MK21DX128VMC5")||(cpu()=="MK21DX256VMC5")||(cpu()=="MK21DN512VMC5")||(cpu()=="MK22DX128VLH5")||(cpu()=="MK22DX256VLH5")||(cpu()=="MK22DN512VLH5")||(cpu()=="MK22DX128VLK5")||(cpu()=="MK22DX256VLK5")||(cpu()=="MK22DN512VLK5")||(cpu()=="MK22DX128VMC5")||(cpu()=="MK22DX256VMC5")||(cpu()=="MK22DN512VMC5")||(cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||cpuis("MKL05*")||cpuis("MKL13*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL27Z128*")||cpuis("MKL27Z256*")||cpuis("MKL33Z*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL43Z*")||cpuis("MKL46Z*")||(cpu()=="MK40DN512ZVLL10")||(cpu()=="MK40DN512ZVLQ10")||(cpu()=="MK40DN512ZVMD10")||(cpu()=="MK40DX128ZVLQ10")||(cpu()=="MK40DX256ZVLQ10")||(cpu()=="MK40DX256ZVMD10")||cpuis("MK28Z*")||cpuis("MKL82Z*")
|
|
bitfld.byte 0x00 6. " DACRFS ,DAC reference select" "DACREF_1,DACREF_2"
|
|
newline
|
|
else
|
|
bitfld.byte 0x00 6. " DACRFS ,DAC reference select" "Internal,External"
|
|
newline
|
|
endif
|
|
bitfld.byte 0x00 5. " DACTRGSEL ,DAC trigger select" "Hardware,Software"
|
|
sif (cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")
|
|
newline
|
|
rbitfld.byte 0x00 4. " DACSWTRG ,DAC software trigger" "Not valid,Valid"
|
|
elif cpuis("MKL05*")||cpuis("MKL13*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("KKL15*")||cpuis("MKL16*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL27Z128*")||cpuis("MKL27Z256*")||cpuis("MKL33Z*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL43Z*")||cpuis("MKL46Z*")||cpuis("MK28Z*")||cpuis("MKL82Z*")
|
|
newline
|
|
bitfld.byte 0x00 4. " DACSWTRG ,DAC software trigger" "No effect,Trigger"
|
|
else
|
|
newline
|
|
bitfld.byte 0x00 4. " DACSWTRG ,DAC software trigger" "Not valid,Valid"
|
|
endif
|
|
newline
|
|
bitfld.byte 0x00 3. " LPEN ,DAC low power control" "High-power,Low-power"
|
|
sif !cpuis("MKL05*")&&!cpuis("MKL13*")&&!cpuis("MK15*")&&!cpuis("MKL15*")&&!cpuis("KKL15*")&&!cpuis("MKL16*")&&!cpuis("MKL17Z128*")&&!cpuis("MKL17Z256*")&&!cpuis("MKL25*")&&!cpuis("MKL26*")&&!cpuis("MKL27Z128*")&&!cpuis("MKL27Z256*")&&!cpuis("MKL33Z*")&&!cpuis("MKL34Z*")&&!cpuis("MKL36Z*")&&!cpuis("MKL43Z*")&&!cpuis("MKL46Z*")
|
|
bitfld.byte 0x00 2. " DACBWIEN ,DAC buffer watermark interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.byte 0x00 1. " DACBTIEN ,DAC buffer read pointer top flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " DACBBIEN ,DAC buffer read pointer bottom flag interrupt enable" "Disabled,Enabled"
|
|
line.byte 0x01 "DAC0_C1,DAC Control Register 1"
|
|
bitfld.byte 0x01 7. " DMAEN ,DMA enable select" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("MKL05*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("KKL15*")||cpuis("MKL16*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")
|
|
bitfld.byte 0x01 2. " DACBFMD ,DAC buffer work mode select" "Normal,One-time scan"
|
|
newline
|
|
elif cpuis("MKL13*")||cpuis("MKL17Z*")||cpuis("MKL27Z128*")||cpuis("MKL27Z256*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")
|
|
bitfld.byte 0x01 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,,One-time scan,FIFO mode"
|
|
newline
|
|
else
|
|
bitfld.byte 0x01 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,3 words,4 words"
|
|
bitfld.byte 0x01 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-time scan,?..."
|
|
newline
|
|
endif
|
|
bitfld.byte 0x01 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled"
|
|
line.byte 0x02 "DAC0_C2,DAC Control Register 2"
|
|
sif cpuis("MKL05*")||cpuis("MKL13*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("KKL15*")||cpuis("MKL16*")||cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL27Z128*")||cpuis("MKL27Z256*")||cpuis("MKL33Z*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL43Z*")||cpuis("MKL46Z*")
|
|
bitfld.byte 0x02 4. " DACBFRP ,DAC buffer read pointer. Keeps the current value of the buffer read pointer" "0,1"
|
|
bitfld.byte 0x02 0. " DACBFUP ,DAC buffer upper limit. Selects the upper limit of the DAC buffer" "0,1"
|
|
else
|
|
bitfld.byte 0x02 4.--7. " DACBFRP ,DAC buffer read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x02 0.--3. " DACBFUP ,DAC buffer upper limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("MKL28Z*")
|
|
tree.open "TPM (Timer/PWM Module)"
|
|
tree "TPM0"
|
|
base ad:0x400AC000
|
|
width 15.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "TPM0_VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number"
|
|
hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature identification number"
|
|
line.long 0x04 "TPM0_PARAM,Parameter Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " WIDTH ,Counter width"
|
|
hexmask.long.byte 0x04 8.--15. 1. " TRIG ,Trigger count"
|
|
hexmask.long.byte 0x04 0.--7. 1. " CHAN ,Channel count"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TPM0_GLOBAL,TPM Global Register"
|
|
bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset"
|
|
newline
|
|
sif !cpuis("MKL28Z*")
|
|
bitfld.long 0x00 0. " NOUPDATE ,No update" "Normal update,No update"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TPM0_SC,Status And Control"
|
|
bitfld.long 0x00 8. " DMA ,DMA enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 7. " TOF ,Timer overflow flag" "No effect,Overflow"
|
|
bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-down counting"
|
|
bitfld.long 0x00 3.--4. " CMOD ,Clock mode selection" "Disabled,TPM counter,TPM_EXTCLK,External input"
|
|
bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
group.long 0x14++0x0B
|
|
line.long 0x00 "TPM0_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value"
|
|
line.long 0x04 "TPM0_MOD,Modulo"
|
|
hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value"
|
|
line.long 0x08 "TPM0_STATUS,Capture And Compare Status"
|
|
eventfld.long 0x08 8. " TOF ,Timer overflow flag" "No overflowed,Overflowed"
|
|
newline
|
|
sif (cpuis("MKL28Z*")||cpuis("K32W0?2S1M*"))
|
|
eventfld.long 0x08 5. " CH5F ,Channel 5 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x08 4. " CH4F ,Channel 4 flag" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x08 3. " CH3F ,Channel 3 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x08 2. " CH2F ,Channel 2 flag" "Not occurred,Occurred"
|
|
newline
|
|
endif
|
|
eventfld.long 0x08 1. " CH1F ,Channel 1 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x08 0. " CH0F ,Channel 0 flag" "Not occurred,Occurred"
|
|
if ((per.l(ad:0x400AC000+0x10)&0x20)==0x0)
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" "None/Channel disabled,Input capture/Rising Edge,Input capture/Falling Edge,Input capture/Rising or Falling Edge,Software compare/Pin not used,Output compare/Toggle Output,Output compare/Clear Output,Output compare/Set Output,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,,Output compare/Pulse Output high,Output compare/Pulse Output low,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP0_C0V,Channel 0 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
else
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" ",,,,,,,,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP0_C0V,Channel 1 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
endif
|
|
if ((per.l(ad:0x400AC000+0x10)&0x20)==0x0)
|
|
group.long 0x28++0x07
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" "None/Channel disabled,Input capture/Rising Edge,Input capture/Falling Edge,Input capture/Rising or Falling Edge,Software compare/Pin not used,Output compare/Toggle Output,Output compare/Clear Output,Output compare/Set Output,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,,Output compare/Pulse Output high,Output compare/Pulse Output low,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP0_C1V,Channel 0 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
else
|
|
group.long 0x28++0x07
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" ",,,,,,,,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP0_C1V,Channel 1 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
endif
|
|
if ((per.l(ad:0x400AC000+0x10)&0x20)==0x0)
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" "None/Channel disabled,Input capture/Rising Edge,Input capture/Falling Edge,Input capture/Rising or Falling Edge,Software compare/Pin not used,Output compare/Toggle Output,Output compare/Clear Output,Output compare/Set Output,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,,Output compare/Pulse Output high,Output compare/Pulse Output low,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP0_C2V,Channel 0 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
else
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" ",,,,,,,,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP0_C2V,Channel 1 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
endif
|
|
if ((per.l(ad:0x400AC000+0x10)&0x20)==0x0)
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" "None/Channel disabled,Input capture/Rising Edge,Input capture/Falling Edge,Input capture/Rising or Falling Edge,Software compare/Pin not used,Output compare/Toggle Output,Output compare/Clear Output,Output compare/Set Output,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,,Output compare/Pulse Output high,Output compare/Pulse Output low,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP0_C3V,Channel 0 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
else
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" ",,,,,,,,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP0_C3V,Channel 1 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
endif
|
|
if ((per.l(ad:0x400AC000+0x10)&0x20)==0x0)
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "TPM0_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" "None/Channel disabled,Input capture/Rising Edge,Input capture/Falling Edge,Input capture/Rising or Falling Edge,Software compare/Pin not used,Output compare/Toggle Output,Output compare/Clear Output,Output compare/Set Output,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,,Output compare/Pulse Output high,Output compare/Pulse Output low,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP0_C4V,Channel 0 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
else
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "TPM0_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" ",,,,,,,,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP0_C4V,Channel 1 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
endif
|
|
if ((per.l(ad:0x400AC000+0x10)&0x20)==0x0)
|
|
group.long 0x48++0x07
|
|
line.long 0x00 "TPM0_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" "None/Channel disabled,Input capture/Rising Edge,Input capture/Falling Edge,Input capture/Rising or Falling Edge,Software compare/Pin not used,Output compare/Toggle Output,Output compare/Clear Output,Output compare/Set Output,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,,Output compare/Pulse Output high,Output compare/Pulse Output low,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP0_C5V,Channel 0 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
else
|
|
group.long 0x48++0x07
|
|
line.long 0x00 "TPM0_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" ",,,,,,,,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP0_C5V,Channel 1 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
endif
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TPM0_COMBINE,Combine Channel Register"
|
|
bitfld.long 0x00 17. " COMSWAP2 ,Combine channel 4 and 5 swap" "Even,Odd"
|
|
bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
bitfld.long 0x00 9. " COMSWAP1 ,Combine channel 2 and 3 swap" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined"
|
|
bitfld.long 0x00 1. " COMSWAP0 ,Combine channel 0 and 1 swap" "Even,Odd"
|
|
bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TPM0_TRIG,Channel Trigger"
|
|
bitfld.long 0x00 5. " TRIG5 ,Channel 5 trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x00 4. " TRIG4 ,Channel 4 trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x00 3. " TRIG3 ,Channel 3 trigger" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 2. " TRIG2 ,Channel 2 trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x00 1. " TRIG1 ,Channel 1 trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " TRIG0 ,Channel 0 trigger" "Not triggered,Triggered"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TPM0_POL,Channel Polarity"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TPM0_FILTER,Filter Control"
|
|
bitfld.long 0x00 20.--23. " CH5FVAL ,Channel 5 filter value" "Disabled,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.long 0x00 16.--19. " CH4FVAL ,Channel 4 filter value" "Disabled,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 filter value" "Disabled,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 filter value" "Disabled,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 filter value" "Disabled,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 filter value" "Disabled,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TPM0_QDCTRL,Quadrature Decoder Control And Status"
|
|
bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase,Count and direction"
|
|
rbitfld.long 0x00 2. " QUADIR ,Counter direction in quadrature decode mode" "Decreasing,Increasing"
|
|
rbitfld.long 0x00 1. " TOFDIR ,TOF direction (TOF bit set on the top or the bottom of counting)" "Bottom,Top"
|
|
newline
|
|
bitfld.long 0x00 0. " QUADEN ,Enables quadrature decoder mode" "Disabled,Enabled"
|
|
if ((per.l(ad:0x400AC000+0x10))&0x18)==0x00
|
|
if ((per.l(ad:0x400AC000+0x84))&0x800000)==0x00
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "TPM0_CONF,Configuration"
|
|
bitfld.long 0x00 24.--25. " TRGSEL ,Trigger select" "0,1,2,3"
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "No effect,Paused"
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "No effect,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Continued,Stopped"
|
|
newline
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Immediately,On rising edge"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "Paused,,,Continued"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Continued,Paused"
|
|
else
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "TPM0_CONF,Configuration"
|
|
bitfld.long 0x00 24.--25. " TRGSEL ,Trigger select" "0,1,2,3"
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "No effect,Paused"
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "No effect,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Continued,Stopped"
|
|
newline
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Immediately,On rising edge"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "Paused,,,Continued"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Continued,Paused"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x400AC000+0x84))&0x800000)==0x00
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM0_CONF,Configuration"
|
|
bitfld.long 0x00 24.--25. " TRGSEL ,Trigger select" "0,1,2,3"
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "No effect,Paused"
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "No effect,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Continued,Stopped"
|
|
newline
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Immediately,On rising edge"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "Paused,,,Continued"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Continued,Paused"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM0_CONF,Configuration"
|
|
bitfld.long 0x00 24.--25. " TRGSEL ,Trigger select" "0,1,2,3"
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "No effect,Paused"
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "No effect,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Continued,Stopped"
|
|
newline
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Immediately,On rising edge"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "Paused,,,Continued"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Continued,Paused"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "TPM1"
|
|
base ad:0x400AD000
|
|
width 15.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "TPM1_VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number"
|
|
hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature identification number"
|
|
line.long 0x04 "TPM1_PARAM,Parameter Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " WIDTH ,Counter width"
|
|
hexmask.long.byte 0x04 8.--15. 1. " TRIG ,Trigger count"
|
|
hexmask.long.byte 0x04 0.--7. 1. " CHAN ,Channel count"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TPM1_GLOBAL,TPM Global Register"
|
|
bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset"
|
|
newline
|
|
sif !cpuis("MKL28Z*")
|
|
bitfld.long 0x00 0. " NOUPDATE ,No update" "Normal update,No update"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TPM1_SC,Status And Control"
|
|
bitfld.long 0x00 8. " DMA ,DMA enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 7. " TOF ,Timer overflow flag" "No effect,Overflow"
|
|
bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-down counting"
|
|
bitfld.long 0x00 3.--4. " CMOD ,Clock mode selection" "Disabled,TPM counter,TPM_EXTCLK,External input"
|
|
bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
group.long 0x14++0x0B
|
|
line.long 0x00 "TPM1_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value"
|
|
line.long 0x04 "TPM1_MOD,Modulo"
|
|
hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value"
|
|
line.long 0x08 "TPM1_STATUS,Capture And Compare Status"
|
|
eventfld.long 0x08 8. " TOF ,Timer overflow flag" "No overflowed,Overflowed"
|
|
newline
|
|
sif (cpuis("MKL28Z*")||cpuis("K32W0?2S1M*"))
|
|
eventfld.long 0x08 5. " CH5F ,Channel 5 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x08 4. " CH4F ,Channel 4 flag" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x08 3. " CH3F ,Channel 3 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x08 2. " CH2F ,Channel 2 flag" "Not occurred,Occurred"
|
|
newline
|
|
endif
|
|
eventfld.long 0x08 1. " CH1F ,Channel 1 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x08 0. " CH0F ,Channel 0 flag" "Not occurred,Occurred"
|
|
if ((per.l(ad:0x400AD000+0x10)&0x20)==0x0)
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" "None/Channel disabled,Input capture/Rising Edge,Input capture/Falling Edge,Input capture/Rising or Falling Edge,Software compare/Pin not used,Output compare/Toggle Output,Output compare/Clear Output,Output compare/Set Output,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,,Output compare/Pulse Output high,Output compare/Pulse Output low,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP1_C0V,Channel 0 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
else
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" ",,,,,,,,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP1_C0V,Channel 1 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
endif
|
|
if ((per.l(ad:0x400AD000+0x10)&0x20)==0x0)
|
|
group.long 0x28++0x07
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" "None/Channel disabled,Input capture/Rising Edge,Input capture/Falling Edge,Input capture/Rising or Falling Edge,Software compare/Pin not used,Output compare/Toggle Output,Output compare/Clear Output,Output compare/Set Output,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,,Output compare/Pulse Output high,Output compare/Pulse Output low,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP1_C1V,Channel 0 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
else
|
|
group.long 0x28++0x07
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" ",,,,,,,,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP1_C1V,Channel 1 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
endif
|
|
if ((per.l(ad:0x400AD000+0x10)&0x20)==0x0)
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "TPM1_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" "None/Channel disabled,Input capture/Rising Edge,Input capture/Falling Edge,Input capture/Rising or Falling Edge,Software compare/Pin not used,Output compare/Toggle Output,Output compare/Clear Output,Output compare/Set Output,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,,Output compare/Pulse Output high,Output compare/Pulse Output low,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP1_C2V,Channel 0 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
else
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "TPM1_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" ",,,,,,,,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP1_C2V,Channel 1 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
endif
|
|
if ((per.l(ad:0x400AD000+0x10)&0x20)==0x0)
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "TPM1_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" "None/Channel disabled,Input capture/Rising Edge,Input capture/Falling Edge,Input capture/Rising or Falling Edge,Software compare/Pin not used,Output compare/Toggle Output,Output compare/Clear Output,Output compare/Set Output,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,,Output compare/Pulse Output high,Output compare/Pulse Output low,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP1_C3V,Channel 0 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
else
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "TPM1_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" ",,,,,,,,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP1_C3V,Channel 1 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
endif
|
|
if ((per.l(ad:0x400AD000+0x10)&0x20)==0x0)
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "TPM1_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" "None/Channel disabled,Input capture/Rising Edge,Input capture/Falling Edge,Input capture/Rising or Falling Edge,Software compare/Pin not used,Output compare/Toggle Output,Output compare/Clear Output,Output compare/Set Output,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,,Output compare/Pulse Output high,Output compare/Pulse Output low,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP1_C4V,Channel 0 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
else
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "TPM1_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" ",,,,,,,,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP1_C4V,Channel 1 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
endif
|
|
if ((per.l(ad:0x400AD000+0x10)&0x20)==0x0)
|
|
group.long 0x48++0x07
|
|
line.long 0x00 "TPM1_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" "None/Channel disabled,Input capture/Rising Edge,Input capture/Falling Edge,Input capture/Rising or Falling Edge,Software compare/Pin not used,Output compare/Toggle Output,Output compare/Clear Output,Output compare/Set Output,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,,Output compare/Pulse Output high,Output compare/Pulse Output low,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP1_C5V,Channel 0 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
else
|
|
group.long 0x48++0x07
|
|
line.long 0x00 "TPM1_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" ",,,,,,,,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP1_C5V,Channel 1 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
endif
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TPM1_COMBINE,Combine Channel Register"
|
|
bitfld.long 0x00 17. " COMSWAP2 ,Combine channel 4 and 5 swap" "Even,Odd"
|
|
bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
bitfld.long 0x00 9. " COMSWAP1 ,Combine channel 2 and 3 swap" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined"
|
|
bitfld.long 0x00 1. " COMSWAP0 ,Combine channel 0 and 1 swap" "Even,Odd"
|
|
bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TPM1_TRIG,Channel Trigger"
|
|
bitfld.long 0x00 5. " TRIG5 ,Channel 5 trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x00 4. " TRIG4 ,Channel 4 trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x00 3. " TRIG3 ,Channel 3 trigger" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 2. " TRIG2 ,Channel 2 trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x00 1. " TRIG1 ,Channel 1 trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " TRIG0 ,Channel 0 trigger" "Not triggered,Triggered"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TPM1_POL,Channel Polarity"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TPM1_FILTER,Filter Control"
|
|
bitfld.long 0x00 20.--23. " CH5FVAL ,Channel 5 filter value" "Disabled,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.long 0x00 16.--19. " CH4FVAL ,Channel 4 filter value" "Disabled,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 filter value" "Disabled,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 filter value" "Disabled,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 filter value" "Disabled,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 filter value" "Disabled,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TPM1_QDCTRL,Quadrature Decoder Control And Status"
|
|
bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase,Count and direction"
|
|
rbitfld.long 0x00 2. " QUADIR ,Counter direction in quadrature decode mode" "Decreasing,Increasing"
|
|
rbitfld.long 0x00 1. " TOFDIR ,TOF direction (TOF bit set on the top or the bottom of counting)" "Bottom,Top"
|
|
newline
|
|
bitfld.long 0x00 0. " QUADEN ,Enables quadrature decoder mode" "Disabled,Enabled"
|
|
if ((per.l(ad:0x400AD000+0x10))&0x18)==0x00
|
|
if ((per.l(ad:0x400AD000+0x84))&0x800000)==0x00
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "TPM1_CONF,Configuration"
|
|
bitfld.long 0x00 24.--25. " TRGSEL ,Trigger select" "0,1,2,3"
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "No effect,Paused"
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "No effect,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Continued,Stopped"
|
|
newline
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Immediately,On rising edge"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "Paused,,,Continued"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Continued,Paused"
|
|
else
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "TPM1_CONF,Configuration"
|
|
bitfld.long 0x00 24.--25. " TRGSEL ,Trigger select" "0,1,2,3"
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "No effect,Paused"
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "No effect,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Continued,Stopped"
|
|
newline
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Immediately,On rising edge"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "Paused,,,Continued"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Continued,Paused"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x400AD000+0x84))&0x800000)==0x00
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM1_CONF,Configuration"
|
|
bitfld.long 0x00 24.--25. " TRGSEL ,Trigger select" "0,1,2,3"
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "No effect,Paused"
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "No effect,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Continued,Stopped"
|
|
newline
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Immediately,On rising edge"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "Paused,,,Continued"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Continued,Paused"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM1_CONF,Configuration"
|
|
bitfld.long 0x00 24.--25. " TRGSEL ,Trigger select" "0,1,2,3"
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "No effect,Paused"
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "No effect,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Continued,Stopped"
|
|
newline
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Immediately,On rising edge"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "Paused,,,Continued"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Continued,Paused"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "TPM2"
|
|
base ad:0x4002E000
|
|
width 15.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "TPM2_VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number"
|
|
hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature identification number"
|
|
line.long 0x04 "TPM2_PARAM,Parameter Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " WIDTH ,Counter width"
|
|
hexmask.long.byte 0x04 8.--15. 1. " TRIG ,Trigger count"
|
|
hexmask.long.byte 0x04 0.--7. 1. " CHAN ,Channel count"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TPM2_GLOBAL,TPM Global Register"
|
|
bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset"
|
|
newline
|
|
sif !cpuis("MKL28Z*")
|
|
bitfld.long 0x00 0. " NOUPDATE ,No update" "Normal update,No update"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TPM2_SC,Status And Control"
|
|
bitfld.long 0x00 8. " DMA ,DMA enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 7. " TOF ,Timer overflow flag" "No effect,Overflow"
|
|
bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-down counting"
|
|
bitfld.long 0x00 3.--4. " CMOD ,Clock mode selection" "Disabled,TPM counter,TPM_EXTCLK,External input"
|
|
bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
group.long 0x14++0x0B
|
|
line.long 0x00 "TPM2_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value"
|
|
line.long 0x04 "TPM2_MOD,Modulo"
|
|
hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value"
|
|
line.long 0x08 "TPM2_STATUS,Capture And Compare Status"
|
|
eventfld.long 0x08 8. " TOF ,Timer overflow flag" "No overflowed,Overflowed"
|
|
newline
|
|
sif (cpuis("MKL28Z*")||cpuis("K32W0?2S1M*"))
|
|
eventfld.long 0x08 5. " CH5F ,Channel 5 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x08 4. " CH4F ,Channel 4 flag" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x08 3. " CH3F ,Channel 3 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x08 2. " CH2F ,Channel 2 flag" "Not occurred,Occurred"
|
|
newline
|
|
endif
|
|
eventfld.long 0x08 1. " CH1F ,Channel 1 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x08 0. " CH0F ,Channel 0 flag" "Not occurred,Occurred"
|
|
if ((per.l(ad:0x4002E000+0x10)&0x20)==0x0)
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" "None/Channel disabled,Input capture/Rising Edge,Input capture/Falling Edge,Input capture/Rising or Falling Edge,Software compare/Pin not used,Output compare/Toggle Output,Output compare/Clear Output,Output compare/Set Output,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,,Output compare/Pulse Output high,Output compare/Pulse Output low,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP2_C0V,Channel 0 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
else
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" ",,,,,,,,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP2_C0V,Channel 1 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
endif
|
|
if ((per.l(ad:0x4002E000+0x10)&0x20)==0x0)
|
|
group.long 0x28++0x07
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" "None/Channel disabled,Input capture/Rising Edge,Input capture/Falling Edge,Input capture/Rising or Falling Edge,Software compare/Pin not used,Output compare/Toggle Output,Output compare/Clear Output,Output compare/Set Output,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,,Output compare/Pulse Output high,Output compare/Pulse Output low,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP2_C1V,Channel 0 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
else
|
|
group.long 0x28++0x07
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" ",,,,,,,,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP2_C1V,Channel 1 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
endif
|
|
if ((per.l(ad:0x4002E000+0x10)&0x20)==0x0)
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "TPM2_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" "None/Channel disabled,Input capture/Rising Edge,Input capture/Falling Edge,Input capture/Rising or Falling Edge,Software compare/Pin not used,Output compare/Toggle Output,Output compare/Clear Output,Output compare/Set Output,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,,Output compare/Pulse Output high,Output compare/Pulse Output low,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP2_C2V,Channel 0 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
else
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "TPM2_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" ",,,,,,,,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP2_C2V,Channel 1 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
endif
|
|
if ((per.l(ad:0x4002E000+0x10)&0x20)==0x0)
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "TPM2_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" "None/Channel disabled,Input capture/Rising Edge,Input capture/Falling Edge,Input capture/Rising or Falling Edge,Software compare/Pin not used,Output compare/Toggle Output,Output compare/Clear Output,Output compare/Set Output,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,,Output compare/Pulse Output high,Output compare/Pulse Output low,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP2_C3V,Channel 0 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
else
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "TPM2_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" ",,,,,,,,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP2_C3V,Channel 1 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
endif
|
|
if ((per.l(ad:0x4002E000+0x10)&0x20)==0x0)
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "TPM2_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" "None/Channel disabled,Input capture/Rising Edge,Input capture/Falling Edge,Input capture/Rising or Falling Edge,Software compare/Pin not used,Output compare/Toggle Output,Output compare/Clear Output,Output compare/Set Output,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,,Output compare/Pulse Output high,Output compare/Pulse Output low,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP2_C4V,Channel 0 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
else
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "TPM2_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" ",,,,,,,,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP2_C4V,Channel 1 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
endif
|
|
if ((per.l(ad:0x4002E000+0x10)&0x20)==0x0)
|
|
group.long 0x48++0x07
|
|
line.long 0x00 "TPM2_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" "None/Channel disabled,Input capture/Rising Edge,Input capture/Falling Edge,Input capture/Rising or Falling Edge,Software compare/Pin not used,Output compare/Toggle Output,Output compare/Clear Output,Output compare/Set Output,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,,Output compare/Pulse Output high,Output compare/Pulse Output low,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP2_C5V,Channel 0 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
else
|
|
group.long 0x48++0x07
|
|
line.long 0x00 "TPM2_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/configuration)" ",,,,,,,,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,Center-aligned PWM/High-true pulses,Center-aligned PWM/Low-true pulses,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
line.long 0x04 "TMP2_C5V,Channel 1 Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value"
|
|
endif
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TPM2_COMBINE,Combine Channel Register"
|
|
bitfld.long 0x00 17. " COMSWAP2 ,Combine channel 4 and 5 swap" "Even,Odd"
|
|
bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined"
|
|
bitfld.long 0x00 9. " COMSWAP1 ,Combine channel 2 and 3 swap" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined"
|
|
bitfld.long 0x00 1. " COMSWAP0 ,Combine channel 0 and 1 swap" "Even,Odd"
|
|
bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TPM2_TRIG,Channel Trigger"
|
|
bitfld.long 0x00 5. " TRIG5 ,Channel 5 trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x00 4. " TRIG4 ,Channel 4 trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x00 3. " TRIG3 ,Channel 3 trigger" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 2. " TRIG2 ,Channel 2 trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x00 1. " TRIG1 ,Channel 1 trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " TRIG0 ,Channel 0 trigger" "Not triggered,Triggered"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TPM2_POL,Channel Polarity"
|
|
bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TPM2_FILTER,Filter Control"
|
|
bitfld.long 0x00 20.--23. " CH5FVAL ,Channel 5 filter value" "Disabled,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.long 0x00 16.--19. " CH4FVAL ,Channel 4 filter value" "Disabled,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 filter value" "Disabled,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 filter value" "Disabled,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 filter value" "Disabled,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 filter value" "Disabled,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TPM2_QDCTRL,Quadrature Decoder Control And Status"
|
|
bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase,Count and direction"
|
|
rbitfld.long 0x00 2. " QUADIR ,Counter direction in quadrature decode mode" "Decreasing,Increasing"
|
|
rbitfld.long 0x00 1. " TOFDIR ,TOF direction (TOF bit set on the top or the bottom of counting)" "Bottom,Top"
|
|
newline
|
|
bitfld.long 0x00 0. " QUADEN ,Enables quadrature decoder mode" "Disabled,Enabled"
|
|
if ((per.l(ad:0x4002E000+0x10))&0x18)==0x00
|
|
if ((per.l(ad:0x4002E000+0x84))&0x800000)==0x00
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "TPM2_CONF,Configuration"
|
|
bitfld.long 0x00 24.--25. " TRGSEL ,Trigger select" "0,1,2,3"
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "No effect,Paused"
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "No effect,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Continued,Stopped"
|
|
newline
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Immediately,On rising edge"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "Paused,,,Continued"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Continued,Paused"
|
|
else
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "TPM2_CONF,Configuration"
|
|
bitfld.long 0x00 24.--25. " TRGSEL ,Trigger select" "0,1,2,3"
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "No effect,Paused"
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "No effect,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Continued,Stopped"
|
|
newline
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Immediately,On rising edge"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "Paused,,,Continued"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Continued,Paused"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x4002E000+0x84))&0x800000)==0x00
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM2_CONF,Configuration"
|
|
bitfld.long 0x00 24.--25. " TRGSEL ,Trigger select" "0,1,2,3"
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "No effect,Paused"
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "No effect,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Continued,Stopped"
|
|
newline
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Immediately,On rising edge"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "Paused,,,Continued"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Continued,Paused"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM2_CONF,Configuration"
|
|
bitfld.long 0x00 24.--25. " TRGSEL ,Trigger select" "0,1,2,3"
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "No effect,Paused"
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "No effect,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Continued,Stopped"
|
|
newline
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Immediately,On rising edge"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "Paused,,,Continued"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Continued,Paused"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
else
|
|
tree.open "TPM (Timer/PWM Module)"
|
|
tree "TPM_0"
|
|
base ad:0x40038000
|
|
sif cpuis("MKL02*")||cpuis("MKL03Z*")
|
|
width 13.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "TPM0_SC,Status And Control"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
bitfld.long 0x00 8. " DMA ,DMA enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting mode,Up-down counting mode"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " CMOD ,Clock mode selection" "Disabled,Incremented on TPM counter clock,Incremented on rising edge of TPM_EXTCLK,?..."
|
|
bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
line.long 0x04 "TPM0_CNT,Counter"
|
|
hexmask.long.word 0x04 0.--15. 1. " COUNT ,Counter value"
|
|
line.long 0x08 "TPM0_MOD,Modulo"
|
|
hexmask.long.word 0x08 0.--15. 1. " MOD ,Modulo value"
|
|
newline
|
|
sif cpuis("MK8?FN256V*")
|
|
if ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0xC)&0x30)==0x00)&&((per.l(ad:0x40038000+0xC)&0xC)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "None,Software compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0xC)&0x30)==0x10)&&((per.l(ad:0x40038000+0xC)&0xC)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "None,Software compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0xC)&0x30)==0x00)&&((per.l(ad:0x40038000+0xC)&0xC)!=0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0xC)&0x30)==0x10)&&((per.l(ad:0x40038000+0xC)&0xC)!=0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0xC)&0x30)==0x20)&&((per.l(ad:0x40038000+0xC)&0xC)!=0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" ",Low,High,Low"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0xC)&0x30)==0x30)&&((per.l(ad:0x40038000+0xC)&0xC)!=0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" ",High,Low,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0xC)&0x30)==0x00)&&((per.l(ad:0x40038000+0xC)&0xC)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "None,Software compare,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0xC)&0x30)==0x10)&&((per.l(ad:0x40038000+0xC)&0xC)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "None,Software compare,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0xC)&0x30)==0x00)&&((per.l(ad:0x40038000+0xC)&0xC)!=0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0xC)&0x30)==0x20)&&((per.l(ad:0x40038000+0xC)&0xC)!=0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" ",Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0xC)&0x10)==0x20)&&((per.l(ad:0x40038000+0xC)&0xC)!=0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xC+0x04)++0x03
|
|
line.long 0x00 "TPM0_C0V,Channel 0 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x14)&0x30)==0x00)&&((per.l(ad:0x40038000+0x14)&0xC)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "None,Software compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x14)&0x30)==0x10)&&((per.l(ad:0x40038000+0x14)&0xC)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "None,Software compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x14)&0x30)==0x00)&&((per.l(ad:0x40038000+0x14)&0xC)!=0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x14)&0x30)==0x10)&&((per.l(ad:0x40038000+0x14)&0xC)!=0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x14)&0x30)==0x20)&&((per.l(ad:0x40038000+0x14)&0xC)!=0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" ",Low,High,Low"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x14)&0x30)==0x30)&&((per.l(ad:0x40038000+0x14)&0xC)!=0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" ",High,Low,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x14)&0x30)==0x00)&&((per.l(ad:0x40038000+0x14)&0xC)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "None,Software compare,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x14)&0x30)==0x10)&&((per.l(ad:0x40038000+0x14)&0xC)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "None,Software compare,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x14)&0x30)==0x00)&&((per.l(ad:0x40038000+0x14)&0xC)!=0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x14)&0x30)==0x20)&&((per.l(ad:0x40038000+0x14)&0xC)!=0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" ",Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x14)&0x10)==0x20)&&((per.l(ad:0x40038000+0x14)&0xC)!=0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x04)++0x03
|
|
line.long 0x00 "TPM0_C1V,Channel 1 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
else
|
|
if ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0xC)&0x30)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0xC)&0x30)==0x10)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0xC)&0x30)==0x20)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Low,High,Low"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0xC)&0x30)==0x30)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,High,Low,High"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0xC)&0x30)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,?..."
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0xC)&0x30)==0x20)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Low,High,Low"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,?..."
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC+0x04)++0x03
|
|
line.long 0x00 "TPM0_C0V,Channel 0 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x14)&0x30)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x14)&0x30)==0x10)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x14)&0x30)==0x20)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Low,High,Low"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x14)&0x30)==0x30)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,High,Low,High"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x14)&0x30)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,?..."
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x14)&0x30)==0x20)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Low,High,Low"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,?..."
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x14+0x04)++0x03
|
|
line.long 0x00 "TPM0_C1V,Channel 1 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
endif
|
|
newline
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TPM0_STATUS,Capture And Compare Status"
|
|
eventfld.long 0x00 8. " TOF ,Timer overflow flag" "No overflow,Overflow"
|
|
newline
|
|
eventfld.long 0x00 1. " CH_1F ,Channel 1 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " CH_0F ,Channel 0 flag" "Not occurred,Occurred"
|
|
sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*")
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TPM0_COMBINE,Combine Channel Register"
|
|
bitfld.long 0x00 1. " COMSWAP0 ,Combine Channel 0 and 1 Swap" "Not swapped,Swapped"
|
|
bitfld.long 0x00 0. " COMBINE0 ,Combine Channels 0 and 1 Enable" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("MKL13*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MK84FN2M0CAU15R*")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*")
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TPM0_POL,Channel Polarity"
|
|
bitfld.long 0x00 1. " POL_1 ,Channel 1 polarity" "High,Low"
|
|
bitfld.long 0x00 0. " POL_0 ,Channel 0 polarity" "High,Low"
|
|
endif
|
|
newline
|
|
sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*")
|
|
sif cpuis("MK84FN2M0CAU15R")
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TPM0_FILTER,Filter Control"
|
|
bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 Filter Value" "Disabled,4 clock cycles,8 clock cycles,12 clock cycles,16 clock cycles,40 clock cycles,48 clock cycles,56 clock cycles,64 clock cycles,72 clock cycles,80 clock cycles,88 clock cycles,96 clock cycles,104 clock cycles,112 clock cycles,116 clock cycles"
|
|
bitfld.long 0x00 0.--3. " CH1FVAL ,Channel 0 Filter Value" "Disabled,4 clock cycles,8 clock cycles,12 clock cycles,16 clock cycles,40 clock cycles,48 clock cycles,56 clock cycles,64 clock cycles,72 clock cycles,80 clock cycles,88 clock cycles,96 clock cycles,104 clock cycles,112 clock cycles,116 clock cycles"
|
|
else
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TPM0_FILTER,Filter Control"
|
|
bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 Filter Value" "Disabled,4 clock cycles,8 clock cycles,12 clock cycles,16 clock cycles,20 clock cycles,24 clock cycles,28 clock cycles,32 clock cycles,36 clock cycles,40 clock cycles,44 clock cycles,48 clock cycles,52 clock cycles,56 clock cycles,60 clock cycles"
|
|
bitfld.long 0x00 0.--3. " CH1FVAL ,Channel 0 Filter Value" "Disabled,4 clock cycles,8 clock cycles,12 clock cycles,16 clock cycles,20 clock cycles,24 clock cycles,28 clock cycles,32 clock cycles,36 clock cycles,40 clock cycles,44 clock cycles,48 clock cycles,52 clock cycles,56 clock cycles,60 clock cycles"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TPM0_QDCTRL,Quadrature Decoder Control and Status"
|
|
bitfld.long 0x00 3. " QUADMODE ,Selects encoding mode used in quadrature decoder mode" "Phase encode,Count and direction encode"
|
|
rbitfld.long 0x00 2. " QUADIR ,Counter Direction in Quadrature Decode Mode" "Decrement,Increment"
|
|
rbitfld.long 0x00 1. " TOFDIR ,TOF bit was set on the top or the bottom of counting" "Bottom,Top"
|
|
newline
|
|
bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*")
|
|
if (((per.l(ad:0x40038000+0x84)&0x800000))==0x00)
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM0_CONF,Configuration"
|
|
sif cpuis("MK84FN2M0CAU15R")
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,,,PIT Ch.0 Output,PIT Ch.1 Output,PIT Ch.2 Output,PIT Ch.3 Output,FTM_0 trigger,FTM_1 trigger,FTM_2 trigger,FTM_3 trigger,RTC alarm,RTC seconds,LPTMR Output,Software Trigger"
|
|
newline
|
|
elif cpuis("MK8?FN256V*")
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,CMP_1,,PIT Ch.0 Output,PIT Ch.1 Output,PIT Ch.2 Output,PIT Ch.3 Output,FTM_0 trigger,FTM_1 trigger,FTM_2 trigger,FTM_3 trigger,RTC alarm,RTC seconds,LPTMR Output,Software Trigger"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP0 output,,,PIT trigger 0,PIT trigger 1,,,TPM0 overflow,TPM1 overflow,TPM2 overflow,,RTC alarm,RTC seconds,LPTMR trigger,?..."
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
newline
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM0_CONF,Configuration"
|
|
sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" ",Ch_0 pin input capture,Ch_1 pin input capture,Ch_0 or ch_1 pin input capture,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" ",Ch_0 pin input capture,Ch_1 pin input capture,Ch_0 or ch_1 pin input capture,Ch_2 pin input capture,Ch_0 or ch_2 pin input capture,Ch_1 or ch_2 pin input capture,Ch_0 or ch_1 or ch_2 pin input capture,Ch_3 pin input capture,Ch_0 or ch_3 pin input capture,Ch_1 or ch_3 pin input capture,Ch_0 or ch_1 or ch_3 pin input capture,Ch_2 or ch_3 pin input capture,Ch_0 or ch_2 or ch_3 pin input capture,Ch_1 or ch_2 or ch_3 pin input capture,Ch_0 or ch_1 or ch_2 or ch_3 pin input capture"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
newline
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM0_CONF,Configuration"
|
|
sif cpuis("MKL02*")
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP0 output,,,,,,,TPM0 overflow,TMP1 overflow,,,,,LPTMR trigger,?..."
|
|
newline
|
|
elif cpuis("MKL03Z*")
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP0 output,,,,,,,TPM0 overflow,TPM1 overflow,,,RTC alarm,RTC seconds,LPTMR trigger,?..."
|
|
newline
|
|
elif cpuis("MKL04*")||cpuis("MKL05*")
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP0 output,,,PIT trigger 0,PIT trigger 1,,,TPM0 overflow,TPM1 overflow,,,RTC alarm,RTC seconds,LPTMR trigger,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP0 output,,,PIT trigger 0,PIT trigger 1,,,TPM0 overflow,TPM1 overflow,TPM2 overflow,,RTC alarm,RTC seconds,LPTMR trigger,?..."
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
width 13.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "TPM0_SC,Status And Control"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
bitfld.long 0x00 8. " DMA ,DMA enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting mode,Up-down counting mode"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " CMOD ,Clock mode selection" "Disabled,Incremented on TPM counter clock,Incremented on rising edge of TPM_EXTCLK,?..."
|
|
bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
line.long 0x04 "TPM0_CNT,Counter"
|
|
hexmask.long.word 0x04 0.--15. 1. " COUNT ,Counter value"
|
|
line.long 0x08 "TPM0_MOD,Modulo"
|
|
hexmask.long.word 0x08 0.--15. 1. " MOD ,Modulo value"
|
|
newline
|
|
sif cpuis("MK8?FN256V*")
|
|
if ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0xC)&0x30)==0x00)&&((per.l(ad:0x40038000+0xC)&0xC)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "None,Software compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0xC)&0x30)==0x10)&&((per.l(ad:0x40038000+0xC)&0xC)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "None,Software compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0xC)&0x30)==0x00)&&((per.l(ad:0x40038000+0xC)&0xC)!=0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0xC)&0x30)==0x10)&&((per.l(ad:0x40038000+0xC)&0xC)!=0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0xC)&0x30)==0x20)&&((per.l(ad:0x40038000+0xC)&0xC)!=0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" ",Low,High,Low"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0xC)&0x30)==0x30)&&((per.l(ad:0x40038000+0xC)&0xC)!=0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" ",High,Low,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0xC)&0x30)==0x00)&&((per.l(ad:0x40038000+0xC)&0xC)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "None,Software compare,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0xC)&0x30)==0x10)&&((per.l(ad:0x40038000+0xC)&0xC)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "None,Software compare,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0xC)&0x30)==0x00)&&((per.l(ad:0x40038000+0xC)&0xC)!=0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0xC)&0x30)==0x20)&&((per.l(ad:0x40038000+0xC)&0xC)!=0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" ",Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0xC)&0x10)==0x20)&&((per.l(ad:0x40038000+0xC)&0xC)!=0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xC+0x04)++0x03
|
|
line.long 0x00 "TPM0_C0V,Channel 0 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x14)&0x30)==0x00)&&((per.l(ad:0x40038000+0x14)&0xC)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "None,Software compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x14)&0x30)==0x10)&&((per.l(ad:0x40038000+0x14)&0xC)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "None,Software compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x14)&0x30)==0x00)&&((per.l(ad:0x40038000+0x14)&0xC)!=0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x14)&0x30)==0x10)&&((per.l(ad:0x40038000+0x14)&0xC)!=0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x14)&0x30)==0x20)&&((per.l(ad:0x40038000+0x14)&0xC)!=0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" ",Low,High,Low"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x14)&0x30)==0x30)&&((per.l(ad:0x40038000+0x14)&0xC)!=0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" ",High,Low,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x14)&0x30)==0x00)&&((per.l(ad:0x40038000+0x14)&0xC)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "None,Software compare,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x14)&0x30)==0x10)&&((per.l(ad:0x40038000+0x14)&0xC)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "None,Software compare,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x14)&0x30)==0x00)&&((per.l(ad:0x40038000+0x14)&0xC)!=0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x14)&0x30)==0x20)&&((per.l(ad:0x40038000+0x14)&0xC)!=0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" ",Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x14)&0x10)==0x20)&&((per.l(ad:0x40038000+0x14)&0xC)!=0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x04)++0x03
|
|
line.long 0x00 "TPM0_C1V,Channel 1 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x1C)&0x30)==0x00)&&((per.l(ad:0x40038000+0x1C)&0xC)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS2B/MS2A ,Channel mode select" "None,Software compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS2B/ELS2A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x1C)&0x30)==0x10)&&((per.l(ad:0x40038000+0x1C)&0xC)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS2B/MS2A ,Channel mode select" "None,Software compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS2B/ELS2A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x1C)&0x30)==0x00)&&((per.l(ad:0x40038000+0x1C)&0xC)!=0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS2B/MS2A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS2B/ELS2A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x1C)&0x30)==0x10)&&((per.l(ad:0x40038000+0x1C)&0xC)!=0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS2B/MS2A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS2B/ELS2A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x1C)&0x30)==0x20)&&((per.l(ad:0x40038000+0x1C)&0xC)!=0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS2B/MS2A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS2B/ELS2A ,Edge or level select" ",Low,High,Low"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x1C)&0x30)==0x30)&&((per.l(ad:0x40038000+0x1C)&0xC)!=0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS2B/MS2A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS2B/ELS2A ,Edge or level select" ",High,Low,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x1C)&0x30)==0x00)&&((per.l(ad:0x40038000+0x1C)&0xC)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS2B/MS2A ,Channel mode select" "None,Software compare,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS2B/ELS2A ,Edge or level select" "Disabled,Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x1C)&0x30)==0x10)&&((per.l(ad:0x40038000+0x1C)&0xC)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS2B/MS2A ,Channel mode select" "None,Software compare,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS2B/ELS2A ,Edge or level select" "Not used,Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x1C)&0x30)==0x00)&&((per.l(ad:0x40038000+0x1C)&0xC)!=0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS2B/MS2A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS2B/ELS2A ,Edge or level select" "Disabled,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x1C)&0x30)==0x20)&&((per.l(ad:0x40038000+0x1C)&0xC)!=0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS2B/MS2A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS2B/ELS2A ,Edge or level select" ",Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x1C)&0x10)==0x20)&&((per.l(ad:0x40038000+0x1C)&0xC)!=0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS2B/MS2A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS2B/ELS2A ,Edge or level select" "Not used,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS2B/MS2A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS2B/ELS2A ,Edge or level select" "?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x1C+0x04)++0x03
|
|
line.long 0x00 "TPM0_C2V,Channel 2 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x24)&0x30)==0x00)&&((per.l(ad:0x40038000+0x24)&0xC)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS3B/MS3A ,Channel mode select" "None,Software compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS3B/ELS3A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x24)&0x30)==0x10)&&((per.l(ad:0x40038000+0x24)&0xC)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS3B/MS3A ,Channel mode select" "None,Software compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS3B/ELS3A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x24)&0x30)==0x00)&&((per.l(ad:0x40038000+0x24)&0xC)!=0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS3B/MS3A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS3B/ELS3A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x24)&0x30)==0x10)&&((per.l(ad:0x40038000+0x24)&0xC)!=0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS3B/MS3A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS3B/ELS3A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x24)&0x30)==0x20)&&((per.l(ad:0x40038000+0x24)&0xC)!=0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS3B/MS3A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS3B/ELS3A ,Edge or level select" ",Low,High,Low"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x24)&0x30)==0x30)&&((per.l(ad:0x40038000+0x24)&0xC)!=0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS3B/MS3A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS3B/ELS3A ,Edge or level select" ",High,Low,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x24)&0x30)==0x00)&&((per.l(ad:0x40038000+0x24)&0xC)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS3B/MS3A ,Channel mode select" "None,Software compare,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS3B/ELS3A ,Edge or level select" "Disabled,Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x24)&0x30)==0x10)&&((per.l(ad:0x40038000+0x24)&0xC)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS3B/MS3A ,Channel mode select" "None,Software compare,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS3B/ELS3A ,Edge or level select" "Not used,Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x24)&0x30)==0x00)&&((per.l(ad:0x40038000+0x24)&0xC)!=0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS3B/MS3A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS3B/ELS3A ,Edge or level select" "Disabled,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x24)&0x30)==0x20)&&((per.l(ad:0x40038000+0x24)&0xC)!=0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS3B/MS3A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS3B/ELS3A ,Edge or level select" ",Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x24)&0x10)==0x20)&&((per.l(ad:0x40038000+0x24)&0xC)!=0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS3B/MS3A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS3B/ELS3A ,Edge or level select" "Not used,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS3B/MS3A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS3B/ELS3A ,Edge or level select" "?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x24+0x04)++0x03
|
|
line.long 0x00 "TPM0_C3V,Channel 3 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x2C)&0x30)==0x00)&&((per.l(ad:0x40038000+0x2C)&0xC)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM0_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS4B/MS4A ,Channel mode select" "None,Software compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS4B/ELS4A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x2C)&0x30)==0x10)&&((per.l(ad:0x40038000+0x2C)&0xC)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM0_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS4B/MS4A ,Channel mode select" "None,Software compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS4B/ELS4A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x2C)&0x30)==0x00)&&((per.l(ad:0x40038000+0x2C)&0xC)!=0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM0_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS4B/MS4A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS4B/ELS4A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x2C)&0x30)==0x10)&&((per.l(ad:0x40038000+0x2C)&0xC)!=0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM0_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS4B/MS4A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS4B/ELS4A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x2C)&0x30)==0x20)&&((per.l(ad:0x40038000+0x2C)&0xC)!=0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM0_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS4B/MS4A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS4B/ELS4A ,Edge or level select" ",Low,High,Low"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x2C)&0x30)==0x30)&&((per.l(ad:0x40038000+0x2C)&0xC)!=0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM0_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS4B/MS4A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS4B/ELS4A ,Edge or level select" ",High,Low,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x2C)&0x30)==0x00)&&((per.l(ad:0x40038000+0x2C)&0xC)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM0_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS4B/MS4A ,Channel mode select" "None,Software compare,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS4B/ELS4A ,Edge or level select" "Disabled,Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x2C)&0x30)==0x10)&&((per.l(ad:0x40038000+0x2C)&0xC)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM0_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS4B/MS4A ,Channel mode select" "None,Software compare,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS4B/ELS4A ,Edge or level select" "Not used,Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x2C)&0x30)==0x00)&&((per.l(ad:0x40038000+0x2C)&0xC)!=0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM0_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS4B/MS4A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS4B/ELS4A ,Edge or level select" "Disabled,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x2C)&0x30)==0x20)&&((per.l(ad:0x40038000+0x2C)&0xC)!=0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM0_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS4B/MS4A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS4B/ELS4A ,Edge or level select" ",Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x2C)&0x10)==0x20)&&((per.l(ad:0x40038000+0x2C)&0xC)!=0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM0_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS4B/MS4A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS4B/ELS4A ,Edge or level select" "Not used,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM0_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS4B/MS4A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS4B/ELS4A ,Edge or level select" "?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x2C+0x04)++0x03
|
|
line.long 0x00 "TPM0_C4V,Channel 4 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x34)&0x30)==0x00)&&((per.l(ad:0x40038000+0x34)&0xC)==0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM0_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS5B/MS5A ,Channel mode select" "None,Software compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS5B/ELS5A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x34)&0x30)==0x10)&&((per.l(ad:0x40038000+0x34)&0xC)==0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM0_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS5B/MS5A ,Channel mode select" "None,Software compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS5B/ELS5A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x34)&0x30)==0x00)&&((per.l(ad:0x40038000+0x34)&0xC)!=0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM0_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS5B/MS5A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS5B/ELS5A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x34)&0x30)==0x10)&&((per.l(ad:0x40038000+0x34)&0xC)!=0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM0_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS5B/MS5A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS5B/ELS5A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x34)&0x30)==0x20)&&((per.l(ad:0x40038000+0x34)&0xC)!=0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM0_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS5B/MS5A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS5B/ELS5A ,Edge or level select" ",Low,High,Low"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x34)&0x30)==0x30)&&((per.l(ad:0x40038000+0x34)&0xC)!=0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM0_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS5B/MS5A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS5B/ELS5A ,Edge or level select" ",High,Low,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x34)&0x30)==0x00)&&((per.l(ad:0x40038000+0x34)&0xC)==0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM0_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS5B/MS5A ,Channel mode select" "None,Software compare,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS5B/ELS5A ,Edge or level select" "Disabled,Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x34)&0x30)==0x10)&&((per.l(ad:0x40038000+0x34)&0xC)==0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM0_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS5B/MS5A ,Channel mode select" "None,Software compare,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS5B/ELS5A ,Edge or level select" "Not used,Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x34)&0x30)==0x00)&&((per.l(ad:0x40038000+0x34)&0xC)!=0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM0_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS5B/MS5A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS5B/ELS5A ,Edge or level select" "Disabled,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x34)&0x30)==0x20)&&((per.l(ad:0x40038000+0x34)&0xC)!=0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM0_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS5B/MS5A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS5B/ELS5A ,Edge or level select" ",Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x34)&0x10)==0x20)&&((per.l(ad:0x40038000+0x34)&0xC)!=0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM0_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS5B/MS5A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS5B/ELS5A ,Edge or level select" "Not used,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM0_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS5B/MS5A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS5B/ELS5A ,Edge or level select" "?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x34+0x04)++0x03
|
|
line.long 0x00 "TPM0_C5V,Channel 5 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
else
|
|
if ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0xC)&0x30)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0xC)&0x30)==0x10)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0xC)&0x30)==0x20)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Low,High,Low"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0xC)&0x30)==0x30)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,High,Low,High"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0xC)&0x30)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,?..."
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0xC)&0x30)==0x20)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Low,High,Low"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM0_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,?..."
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC+0x04)++0x03
|
|
line.long 0x00 "TPM0_C0V,Channel 0 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x14)&0x30)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x14)&0x30)==0x10)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x14)&0x30)==0x20)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Low,High,Low"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x14)&0x30)==0x30)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,High,Low,High"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x14)&0x30)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,?..."
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x14)&0x30)==0x20)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Low,High,Low"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM0_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,?..."
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x14+0x04)++0x03
|
|
line.long 0x00 "TPM0_C1V,Channel 1 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x1C)&0x30)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS2B/MS2A ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS2B/ELS2A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x1C)&0x30)==0x10)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS2B/MS2A ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS2B/ELS2A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x1C)&0x30)==0x20)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS2B/MS2A ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS2B/ELS2A ,Edge or level select" "Not used,Low,High,Low"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x1C)&0x30)==0x30)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS2B/MS2A ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS2B/ELS2A ,Edge or level select" "Not used,High,Low,High"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x1C)&0x30)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS2B/MS2A ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS2B/ELS2A ,Edge or level select" "Disabled,?..."
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x1C)&0x30)==0x20)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS2B/MS2A ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS2B/ELS2A ,Edge or level select" "Not used,Low,High,Low"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TPM0_C2SC,Channel 2 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS2B/MS2A ,Channel mode select (ELS2 = 0/ELS2 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS2B/ELS2A ,Edge or level select" "Not used,?..."
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x1C+0x04)++0x03
|
|
line.long 0x00 "TPM0_C2V,Channel 2 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x24)&0x30)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS3B/MS3A ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS3B/ELS3A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x24)&0x30)==0x10)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS3B/MS3A ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS3B/ELS3A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x24)&0x30)==0x20)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS3B/MS3A ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS3B/ELS3A ,Edge or level select" "Not used,Low,High,Low"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x24)&0x30)==0x30)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS3B/MS3A ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS3B/ELS3A ,Edge or level select" "Not used,High,Low,High"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x24)&0x30)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS3B/MS3A ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS3B/ELS3A ,Edge or level select" "Disabled,?..."
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x24)&0x30)==0x20)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS3B/MS3A ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS3B/ELS3A ,Edge or level select" "Not used,Low,High,Low"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TPM0_C3SC,Channel 3 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS3B/MS3A ,Channel mode select (ELS3 = 0/ELS3 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS3B/ELS3A ,Edge or level select" "Not used,?..."
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x24+0x04)++0x03
|
|
line.long 0x00 "TPM0_C3V,Channel 3 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x2C)&0x30)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM0_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS4B/MS4A ,Channel mode select (ELS4 = 0/ELS4 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS4B/ELS4A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x2C)&0x30)==0x10)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM0_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS4B/MS4A ,Channel mode select (ELS4 = 0/ELS4 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS4B/ELS4A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x2C)&0x30)==0x20)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM0_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS4B/MS4A ,Channel mode select (ELS4 = 0/ELS4 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS4B/ELS4A ,Edge or level select" "Not used,Low,High,Low"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x2C)&0x30)==0x30)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM0_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS4B/MS4A ,Channel mode select (ELS4 = 0/ELS4 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS4B/ELS4A ,Edge or level select" "Not used,High,Low,High"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x2C)&0x30)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM0_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS4B/MS4A ,Channel mode select (ELS4 = 0/ELS4 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS4B/ELS4A ,Edge or level select" "Disabled,?..."
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x2C)&0x30)==0x20)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM0_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS4B/MS4A ,Channel mode select (ELS4 = 0/ELS4 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS4B/ELS4A ,Edge or level select" "Not used,Low,High,Low"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TPM0_C4SC,Channel 4 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS4B/MS4A ,Channel mode select (ELS4 = 0/ELS4 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS4B/ELS4A ,Edge or level select" "Not used,?..."
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x2C+0x04)++0x03
|
|
line.long 0x00 "TPM0_C4V,Channel 4 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x34)&0x30)==0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM0_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS5B/MS5A ,Channel mode select (ELS5 = 0/ELS5 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS5B/ELS5A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x34)&0x30)==0x10)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM0_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS5B/MS5A ,Channel mode select (ELS5 = 0/ELS5 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS5B/ELS5A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x34)&0x30)==0x20)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM0_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS5B/MS5A ,Channel mode select (ELS5 = 0/ELS5 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS5B/ELS5A ,Edge or level select" "Not used,Low,High,Low"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x00)&&((per.l(ad:0x40038000+0x34)&0x30)==0x30)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM0_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS5B/MS5A ,Channel mode select (ELS5 = 0/ELS5 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS5B/ELS5A ,Edge or level select" "Not used,High,Low,High"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x34)&0x30)==0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM0_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS5B/MS5A ,Channel mode select (ELS5 = 0/ELS5 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS5B/ELS5A ,Edge or level select" "Disabled,?..."
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40038000)&0x20)==0x20)&&((per.l(ad:0x40038000+0x34)&0x30)==0x20)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM0_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS5B/MS5A ,Channel mode select (ELS5 = 0/ELS5 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS5B/ELS5A ,Edge or level select" "Not used,Low,High,Low"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPM0_C5SC,Channel 5 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS5B/MS5A ,Channel mode select (ELS5 = 0/ELS5 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS5B/ELS5A ,Edge or level select" "Not used,?..."
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x34+0x04)++0x03
|
|
line.long 0x00 "TPM0_C5V,Channel 5 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
endif
|
|
newline
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TPM0_STATUS,Capture And Compare Status"
|
|
eventfld.long 0x00 8. " TOF ,Timer overflow flag" "No overflow,Overflow"
|
|
newline
|
|
eventfld.long 0x00 5. " CH_5F ,Channel 5 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 4. " CH_4F ,Channel 4 flag" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 3. " CH_3F ,Channel 3 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " CH_2F ,Channel 2 flag" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 1. " CH_1F ,Channel 1 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " CH_0F ,Channel 0 flag" "Not occurred,Occurred"
|
|
sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*")
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TPM0_COMBINE,Combine Channel Register"
|
|
bitfld.long 0x00 1. " COMSWAP0 ,Combine Channel 0 and 1 Swap" "Not swapped,Swapped"
|
|
bitfld.long 0x00 0. " COMBINE0 ,Combine Channels 0 and 1 Enable" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("MKL13*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MK84FN2M0CAU15R*")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*")
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TPM0_POL,Channel Polarity"
|
|
bitfld.long 0x00 5. " POL_5 ,Channel 5 polarity" "High,Low"
|
|
bitfld.long 0x00 4. " POL_4 ,Channel 4 polarity" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 3. " POL_3 ,Channel 3 polarity" "High,Low"
|
|
bitfld.long 0x00 2. " POL_2 ,Channel 2 polarity" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 1. " POL_1 ,Channel 1 polarity" "High,Low"
|
|
bitfld.long 0x00 0. " POL_0 ,Channel 0 polarity" "High,Low"
|
|
endif
|
|
newline
|
|
sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*")
|
|
sif cpuis("MK84FN2M0CAU15R")
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TPM0_FILTER,Filter Control"
|
|
bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 Filter Value" "Disabled,4 clock cycles,8 clock cycles,12 clock cycles,16 clock cycles,40 clock cycles,48 clock cycles,56 clock cycles,64 clock cycles,72 clock cycles,80 clock cycles,88 clock cycles,96 clock cycles,104 clock cycles,112 clock cycles,116 clock cycles"
|
|
bitfld.long 0x00 0.--3. " CH1FVAL ,Channel 0 Filter Value" "Disabled,4 clock cycles,8 clock cycles,12 clock cycles,16 clock cycles,40 clock cycles,48 clock cycles,56 clock cycles,64 clock cycles,72 clock cycles,80 clock cycles,88 clock cycles,96 clock cycles,104 clock cycles,112 clock cycles,116 clock cycles"
|
|
else
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TPM0_FILTER,Filter Control"
|
|
bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 Filter Value" "Disabled,4 clock cycles,8 clock cycles,12 clock cycles,16 clock cycles,20 clock cycles,24 clock cycles,28 clock cycles,32 clock cycles,36 clock cycles,40 clock cycles,44 clock cycles,48 clock cycles,52 clock cycles,56 clock cycles,60 clock cycles"
|
|
bitfld.long 0x00 0.--3. " CH1FVAL ,Channel 0 Filter Value" "Disabled,4 clock cycles,8 clock cycles,12 clock cycles,16 clock cycles,20 clock cycles,24 clock cycles,28 clock cycles,32 clock cycles,36 clock cycles,40 clock cycles,44 clock cycles,48 clock cycles,52 clock cycles,56 clock cycles,60 clock cycles"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TPM0_QDCTRL,Quadrature Decoder Control and Status"
|
|
bitfld.long 0x00 3. " QUADMODE ,Selects encoding mode used in quadrature decoder mode" "Phase encode,Count and direction encode"
|
|
rbitfld.long 0x00 2. " QUADIR ,Counter Direction in Quadrature Decode Mode" "Decrement,Increment"
|
|
rbitfld.long 0x00 1. " TOFDIR ,TOF bit was set on the top or the bottom of counting" "Bottom,Top"
|
|
newline
|
|
bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*")
|
|
if (((per.l(ad:0x40038000+0x84)&0x800000))==0x00)
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM0_CONF,Configuration"
|
|
sif cpuis("MK84FN2M0CAU15R")
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,,,PIT Ch.0 Output,PIT Ch.1 Output,PIT Ch.2 Output,PIT Ch.3 Output,FTM_0 trigger,FTM_1 trigger,FTM_2 trigger,FTM_3 trigger,RTC alarm,RTC seconds,LPTMR Output,Software Trigger"
|
|
newline
|
|
elif cpuis("MK8?FN256V*")
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,CMP_1,,PIT Ch.0 Output,PIT Ch.1 Output,PIT Ch.2 Output,PIT Ch.3 Output,FTM_0 trigger,FTM_1 trigger,FTM_2 trigger,FTM_3 trigger,RTC alarm,RTC seconds,LPTMR Output,Software Trigger"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP0 output,,,PIT trigger 0,PIT trigger 1,,,TPM0 overflow,TPM1 overflow,TPM2 overflow,,RTC alarm,RTC seconds,LPTMR trigger,?..."
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
newline
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM0_CONF,Configuration"
|
|
sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" ",Ch_0 pin input capture,Ch_1 pin input capture,Ch_0 or ch_1 pin input capture,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" ",Ch_0 pin input capture,Ch_1 pin input capture,Ch_0 or ch_1 pin input capture,Ch_2 pin input capture,Ch_0 or ch_2 pin input capture,Ch_1 or ch_2 pin input capture,Ch_0 or ch_1 or ch_2 pin input capture,Ch_3 pin input capture,Ch_0 or ch_3 pin input capture,Ch_1 or ch_3 pin input capture,Ch_0 or ch_1 or ch_3 pin input capture,Ch_2 or ch_3 pin input capture,Ch_0 or ch_2 or ch_3 pin input capture,Ch_1 or ch_2 or ch_3 pin input capture,Ch_0 or ch_1 or ch_2 or ch_3 pin input capture"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
newline
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM0_CONF,Configuration"
|
|
sif cpuis("MKL02*")
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP0 output,,,,,,,TPM0 overflow,TMP1 overflow,,,,,LPTMR trigger,?..."
|
|
newline
|
|
elif cpuis("MKL03Z*")
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP0 output,,,,,,,TPM0 overflow,TPM1 overflow,,,RTC alarm,RTC seconds,LPTMR trigger,?..."
|
|
newline
|
|
elif cpuis("MKL04*")||cpuis("MKL05*")
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP0 output,,,PIT trigger 0,PIT trigger 1,,,TPM0 overflow,TPM1 overflow,,,RTC alarm,RTC seconds,LPTMR trigger,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP0 output,,,PIT trigger 0,PIT trigger 1,,,TPM0 overflow,TPM1 overflow,TPM2 overflow,,RTC alarm,RTC seconds,LPTMR trigger,?..."
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
tree "TPM_1"
|
|
base ad:0x40039000
|
|
width 13.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "TPM1_SC,Status And Control"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
bitfld.long 0x00 8. " DMA ,DMA enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting mode,Up-down counting mode"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " CMOD ,Clock mode selection" "Disabled,Incremented on TPM counter clock,Incremented on rising edge of TPM_EXTCLK,?..."
|
|
bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
line.long 0x04 "TPM1_CNT,Counter"
|
|
hexmask.long.word 0x04 0.--15. 1. " COUNT ,Counter value"
|
|
line.long 0x08 "TPM1_MOD,Modulo"
|
|
hexmask.long.word 0x08 0.--15. 1. " MOD ,Modulo value"
|
|
newline
|
|
sif cpuis("MK8?FN256V*")
|
|
if ((per.l(ad:0x40039000)&0x20)==0x00)&&((per.l(ad:0x40039000+0xC)&0x30)==0x00)&&((per.l(ad:0x40039000+0xC)&0xC)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "None,Software compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x00)&&((per.l(ad:0x40039000+0xC)&0x30)==0x10)&&((per.l(ad:0x40039000+0xC)&0xC)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "None,Software compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x00)&&((per.l(ad:0x40039000+0xC)&0x30)==0x00)&&((per.l(ad:0x40039000+0xC)&0xC)!=0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x00)&&((per.l(ad:0x40039000+0xC)&0x30)==0x10)&&((per.l(ad:0x40039000+0xC)&0xC)!=0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x00)&&((per.l(ad:0x40039000+0xC)&0x30)==0x20)&&((per.l(ad:0x40039000+0xC)&0xC)!=0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" ",Low,High,Low"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x00)&&((per.l(ad:0x40039000+0xC)&0x30)==0x30)&&((per.l(ad:0x40039000+0xC)&0xC)!=0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" ",High,Low,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0xC)&0x30)==0x00)&&((per.l(ad:0x40039000+0xC)&0xC)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "None,Software compare,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0xC)&0x30)==0x10)&&((per.l(ad:0x40039000+0xC)&0xC)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "None,Software compare,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0xC)&0x30)==0x00)&&((per.l(ad:0x40039000+0xC)&0xC)!=0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0xC)&0x30)==0x20)&&((per.l(ad:0x40039000+0xC)&0xC)!=0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" ",Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0xC)&0x10)==0x20)&&((per.l(ad:0x40039000+0xC)&0xC)!=0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xC+0x04)++0x03
|
|
line.long 0x00 "TPM1_C0V,Channel 0 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x40039000)&0x20)==0x00)&&((per.l(ad:0x40039000+0x14)&0x30)==0x00)&&((per.l(ad:0x40039000+0x14)&0xC)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "None,Software compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x00)&&((per.l(ad:0x40039000+0x14)&0x30)==0x10)&&((per.l(ad:0x40039000+0x14)&0xC)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "None,Software compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x00)&&((per.l(ad:0x40039000+0x14)&0x30)==0x00)&&((per.l(ad:0x40039000+0x14)&0xC)!=0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x00)&&((per.l(ad:0x40039000+0x14)&0x30)==0x10)&&((per.l(ad:0x40039000+0x14)&0xC)!=0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x00)&&((per.l(ad:0x40039000+0x14)&0x30)==0x20)&&((per.l(ad:0x40039000+0x14)&0xC)!=0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" ",Low,High,Low"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x00)&&((per.l(ad:0x40039000+0x14)&0x30)==0x30)&&((per.l(ad:0x40039000+0x14)&0xC)!=0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" ",High,Low,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0x14)&0x30)==0x00)&&((per.l(ad:0x40039000+0x14)&0xC)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "None,Software compare,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0x14)&0x30)==0x10)&&((per.l(ad:0x40039000+0x14)&0xC)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "None,Software compare,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0x14)&0x30)==0x00)&&((per.l(ad:0x40039000+0x14)&0xC)!=0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0x14)&0x30)==0x20)&&((per.l(ad:0x40039000+0x14)&0xC)!=0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" ",Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0x14)&0x10)==0x20)&&((per.l(ad:0x40039000+0x14)&0xC)!=0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x04)++0x03
|
|
line.long 0x00 "TPM1_C1V,Channel 1 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
else
|
|
if ((per.l(ad:0x40039000)&0x20)==0x00)&&((per.l(ad:0x40039000+0xC)&0x30)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x00)&&((per.l(ad:0x40039000+0xC)&0x30)==0x10)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x00)&&((per.l(ad:0x40039000+0xC)&0x30)==0x20)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Low,High,Low"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x00)&&((per.l(ad:0x40039000+0xC)&0x30)==0x30)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,High,Low,High"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0xC)&0x30)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,?..."
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0xC)&0x30)==0x20)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Low,High,Low"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,?..."
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC+0x04)++0x03
|
|
line.long 0x00 "TPM1_C0V,Channel 0 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x40039000)&0x20)==0x00)&&((per.l(ad:0x40039000+0x14)&0x30)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x00)&&((per.l(ad:0x40039000+0x14)&0x30)==0x10)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x00)&&((per.l(ad:0x40039000+0x14)&0x30)==0x20)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Low,High,Low"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x00)&&((per.l(ad:0x40039000+0x14)&0x30)==0x30)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,High,Low,High"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0x14)&0x30)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,?..."
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40039000)&0x20)==0x20)&&((per.l(ad:0x40039000+0x14)&0x30)==0x20)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Low,High,Low"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,?..."
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x14+0x04)++0x03
|
|
line.long 0x00 "TPM1_C1V,Channel 1 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
endif
|
|
newline
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TPM1_STATUS,Capture And Compare Status"
|
|
eventfld.long 0x00 8. " TOF ,Timer overflow flag" "No overflow,Overflow"
|
|
newline
|
|
eventfld.long 0x00 1. " CH_1F ,Channel 1 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " CH_0F ,Channel 0 flag" "Not occurred,Occurred"
|
|
sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*")
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TPM1_COMBINE,Combine Channel Register"
|
|
bitfld.long 0x00 1. " COMSWAP0 ,Combine Channel 0 and 1 Swap" "Not swapped,Swapped"
|
|
bitfld.long 0x00 0. " COMBINE0 ,Combine Channels 0 and 1 Enable" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("MKL13*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MK84FN2M0CAU15R*")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*")
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TPM1_POL,Channel Polarity"
|
|
bitfld.long 0x00 1. " POL_1 ,Channel 1 polarity" "High,Low"
|
|
bitfld.long 0x00 0. " POL_0 ,Channel 0 polarity" "High,Low"
|
|
endif
|
|
newline
|
|
sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*")
|
|
sif cpuis("MK84FN2M0CAU15R")
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TPM1_FILTER,Filter Control"
|
|
bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 Filter Value" "Disabled,4 clock cycles,8 clock cycles,12 clock cycles,16 clock cycles,40 clock cycles,48 clock cycles,56 clock cycles,64 clock cycles,72 clock cycles,80 clock cycles,88 clock cycles,96 clock cycles,104 clock cycles,112 clock cycles,116 clock cycles"
|
|
bitfld.long 0x00 0.--3. " CH1FVAL ,Channel 0 Filter Value" "Disabled,4 clock cycles,8 clock cycles,12 clock cycles,16 clock cycles,40 clock cycles,48 clock cycles,56 clock cycles,64 clock cycles,72 clock cycles,80 clock cycles,88 clock cycles,96 clock cycles,104 clock cycles,112 clock cycles,116 clock cycles"
|
|
else
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TPM1_FILTER,Filter Control"
|
|
bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 Filter Value" "Disabled,4 clock cycles,8 clock cycles,12 clock cycles,16 clock cycles,20 clock cycles,24 clock cycles,28 clock cycles,32 clock cycles,36 clock cycles,40 clock cycles,44 clock cycles,48 clock cycles,52 clock cycles,56 clock cycles,60 clock cycles"
|
|
bitfld.long 0x00 0.--3. " CH1FVAL ,Channel 0 Filter Value" "Disabled,4 clock cycles,8 clock cycles,12 clock cycles,16 clock cycles,20 clock cycles,24 clock cycles,28 clock cycles,32 clock cycles,36 clock cycles,40 clock cycles,44 clock cycles,48 clock cycles,52 clock cycles,56 clock cycles,60 clock cycles"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TPM1_QDCTRL,Quadrature Decoder Control and Status"
|
|
bitfld.long 0x00 3. " QUADMODE ,Selects encoding mode used in quadrature decoder mode" "Phase encode,Count and direction encode"
|
|
rbitfld.long 0x00 2. " QUADIR ,Counter Direction in Quadrature Decode Mode" "Decrement,Increment"
|
|
rbitfld.long 0x00 1. " TOFDIR ,TOF bit was set on the top or the bottom of counting" "Bottom,Top"
|
|
newline
|
|
bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*")
|
|
if (((per.l(ad:0x40039000+0x84)&0x800000))==0x00)
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM1_CONF,Configuration"
|
|
sif cpuis("MK84FN2M0CAU15R")
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,,,PIT Ch.0 Output,PIT Ch.1 Output,PIT Ch.2 Output,PIT Ch.3 Output,FTM_0 trigger,FTM_1 trigger,FTM_2 trigger,FTM_3 trigger,RTC alarm,RTC seconds,LPTMR Output,Software Trigger"
|
|
newline
|
|
elif cpuis("MK8?FN256V*")
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,CMP_1,,PIT Ch.0 Output,PIT Ch.1 Output,PIT Ch.2 Output,PIT Ch.3 Output,FTM_0 trigger,FTM_1 trigger,FTM_2 trigger,FTM_3 trigger,RTC alarm,RTC seconds,LPTMR Output,Software Trigger"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP0 output,,,PIT trigger 0,PIT trigger 1,,,TPM0 overflow,TPM1 overflow,TPM2 overflow,,RTC alarm,RTC seconds,LPTMR trigger,?..."
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
newline
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM1_CONF,Configuration"
|
|
sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" ",Ch_0 pin input capture,Ch_1 pin input capture,Ch_0 or ch_1 pin input capture,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" ",Ch_0 pin input capture,Ch_1 pin input capture,Ch_0 or ch_1 pin input capture,Ch_2 pin input capture,Ch_0 or ch_2 pin input capture,Ch_1 or ch_2 pin input capture,Ch_0 or ch_1 or ch_2 pin input capture,Ch_3 pin input capture,Ch_0 or ch_3 pin input capture,Ch_1 or ch_3 pin input capture,Ch_0 or ch_1 or ch_3 pin input capture,Ch_2 or ch_3 pin input capture,Ch_0 or ch_2 or ch_3 pin input capture,Ch_1 or ch_2 or ch_3 pin input capture,Ch_0 or ch_1 or ch_2 or ch_3 pin input capture"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
newline
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM1_CONF,Configuration"
|
|
sif cpuis("MKL02*")
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP0 output,,,,,,,TPM0 overflow,TMP1 overflow,,,,,LPTMR trigger,?..."
|
|
newline
|
|
elif cpuis("MKL03Z*")
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP0 output,,,,,,,TPM0 overflow,TPM1 overflow,,,RTC alarm,RTC seconds,LPTMR trigger,?..."
|
|
newline
|
|
elif cpuis("MKL04*")||cpuis("MKL05*")
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP0 output,,,PIT trigger 0,PIT trigger 1,,,TPM0 overflow,TPM1 overflow,,,RTC alarm,RTC seconds,LPTMR trigger,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP0 output,,,PIT trigger 0,PIT trigger 1,,,TPM0 overflow,TPM1 overflow,TPM2 overflow,,RTC alarm,RTC seconds,LPTMR trigger,?..."
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("MKL13*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL17Z*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL43Z*")||cpuis("MKL46Z*")||cpuis("MKL82Z*")||cpuis("KKL15*")
|
|
tree "TPM_2"
|
|
base ad:0x4003A000
|
|
width 13.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "TPM2_SC,Status And Control"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
bitfld.long 0x00 8. " DMA ,DMA enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting mode,Up-down counting mode"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " CMOD ,Clock mode selection" "Disabled,Incremented on TPM counter clock,Incremented on rising edge of TPM_EXTCLK,?..."
|
|
bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
line.long 0x04 "TPM2_CNT,Counter"
|
|
hexmask.long.word 0x04 0.--15. 1. " COUNT ,Counter value"
|
|
line.long 0x08 "TPM2_MOD,Modulo"
|
|
hexmask.long.word 0x08 0.--15. 1. " MOD ,Modulo value"
|
|
newline
|
|
sif cpuis("MK8?FN256V*")
|
|
if ((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0xC)&0x30)==0x00)&&((per.l(ad:0x4003A000+0xC)&0xC)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "None,Software compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0xC)&0x30)==0x10)&&((per.l(ad:0x4003A000+0xC)&0xC)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "None,Software compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0xC)&0x30)==0x00)&&((per.l(ad:0x4003A000+0xC)&0xC)!=0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0xC)&0x30)==0x10)&&((per.l(ad:0x4003A000+0xC)&0xC)!=0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0xC)&0x30)==0x20)&&((per.l(ad:0x4003A000+0xC)&0xC)!=0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" ",Low,High,Low"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0xC)&0x30)==0x30)&&((per.l(ad:0x4003A000+0xC)&0xC)!=0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" ",High,Low,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0xC)&0x30)==0x00)&&((per.l(ad:0x4003A000+0xC)&0xC)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "None,Software compare,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0xC)&0x30)==0x10)&&((per.l(ad:0x4003A000+0xC)&0xC)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "None,Software compare,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0xC)&0x30)==0x00)&&((per.l(ad:0x4003A000+0xC)&0xC)!=0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0xC)&0x30)==0x20)&&((per.l(ad:0x4003A000+0xC)&0xC)!=0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" ",Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0xC)&0x10)==0x20)&&((per.l(ad:0x4003A000+0xC)&0xC)!=0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xC+0x04)++0x03
|
|
line.long 0x00 "TPM2_C0V,Channel 0 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x14)&0x30)==0x00)&&((per.l(ad:0x4003A000+0x14)&0xC)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "None,Software compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x14)&0x30)==0x10)&&((per.l(ad:0x4003A000+0x14)&0xC)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "None,Software compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x14)&0x30)==0x00)&&((per.l(ad:0x4003A000+0x14)&0xC)!=0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x14)&0x30)==0x10)&&((per.l(ad:0x4003A000+0x14)&0xC)!=0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x14)&0x30)==0x20)&&((per.l(ad:0x4003A000+0x14)&0xC)!=0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" ",Low,High,Low"
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x14)&0x30)==0x30)&&((per.l(ad:0x4003A000+0x14)&0xC)!=0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" ",High,Low,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x14)&0x30)==0x00)&&((per.l(ad:0x4003A000+0x14)&0xC)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "None,Software compare,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x14)&0x30)==0x10)&&((per.l(ad:0x4003A000+0x14)&0xC)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "None,Software compare,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x14)&0x30)==0x00)&&((per.l(ad:0x4003A000+0x14)&0xC)!=0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x14)&0x30)==0x20)&&((per.l(ad:0x4003A000+0x14)&0xC)!=0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" ",Low,High,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x14)&0x10)==0x20)&&((per.l(ad:0x4003A000+0x14)&0xC)!=0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" ",,Center-aligned PWM,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "?..."
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x04)++0x03
|
|
line.long 0x00 "TPM2_C1V,Channel 1 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
else
|
|
if ((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0xC)&0x30)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0xC)&0x30)==0x10)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0xC)&0x30)==0x20)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Low,High,Low"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0xC)&0x30)==0x30)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,High,Low,High"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0xC)&0x30)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,?..."
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0xC)&0x30)==0x20)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Low,High,Low"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,?..."
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0xC+0x04)++0x03
|
|
line.long 0x00 "TPM2_C0V,Channel 0 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
if ((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x14)&0x30)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,Rising,Falling,Both"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x14)&0x30)==0x10)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Toggle,Clear,Set"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x14)&0x30)==0x20)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Low,High,Low"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x14)&0x30)==0x30)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,High,Low,High"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x14)&0x30)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,?..."
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x14)&0x30)==0x20)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Low,High,Low"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control"
|
|
eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,?..."
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long (0x14+0x04)++0x03
|
|
line.long 0x00 "TPM2_C1V,Channel 1 Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value"
|
|
endif
|
|
newline
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TPM2_STATUS,Capture And Compare Status"
|
|
eventfld.long 0x00 8. " TOF ,Timer overflow flag" "No overflow,Overflow"
|
|
newline
|
|
eventfld.long 0x00 1. " CH_1F ,Channel 1 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " CH_0F ,Channel 0 flag" "Not occurred,Occurred"
|
|
sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*")
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TPM2_COMBINE,Combine Channel Register"
|
|
bitfld.long 0x00 1. " COMSWAP0 ,Combine Channel 0 and 1 Swap" "Not swapped,Swapped"
|
|
bitfld.long 0x00 0. " COMBINE0 ,Combine Channels 0 and 1 Enable" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("MKL13*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MK84FN2M0CAU15R*")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*")
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TPM2_POL,Channel Polarity"
|
|
bitfld.long 0x00 1. " POL_1 ,Channel 1 polarity" "High,Low"
|
|
bitfld.long 0x00 0. " POL_0 ,Channel 0 polarity" "High,Low"
|
|
endif
|
|
newline
|
|
sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*")
|
|
sif cpuis("MK84FN2M0CAU15R")
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TPM2_FILTER,Filter Control"
|
|
bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 Filter Value" "Disabled,4 clock cycles,8 clock cycles,12 clock cycles,16 clock cycles,40 clock cycles,48 clock cycles,56 clock cycles,64 clock cycles,72 clock cycles,80 clock cycles,88 clock cycles,96 clock cycles,104 clock cycles,112 clock cycles,116 clock cycles"
|
|
bitfld.long 0x00 0.--3. " CH1FVAL ,Channel 0 Filter Value" "Disabled,4 clock cycles,8 clock cycles,12 clock cycles,16 clock cycles,40 clock cycles,48 clock cycles,56 clock cycles,64 clock cycles,72 clock cycles,80 clock cycles,88 clock cycles,96 clock cycles,104 clock cycles,112 clock cycles,116 clock cycles"
|
|
else
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TPM2_FILTER,Filter Control"
|
|
bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 Filter Value" "Disabled,4 clock cycles,8 clock cycles,12 clock cycles,16 clock cycles,20 clock cycles,24 clock cycles,28 clock cycles,32 clock cycles,36 clock cycles,40 clock cycles,44 clock cycles,48 clock cycles,52 clock cycles,56 clock cycles,60 clock cycles"
|
|
bitfld.long 0x00 0.--3. " CH1FVAL ,Channel 0 Filter Value" "Disabled,4 clock cycles,8 clock cycles,12 clock cycles,16 clock cycles,20 clock cycles,24 clock cycles,28 clock cycles,32 clock cycles,36 clock cycles,40 clock cycles,44 clock cycles,48 clock cycles,52 clock cycles,56 clock cycles,60 clock cycles"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TPM2_QDCTRL,Quadrature Decoder Control and Status"
|
|
bitfld.long 0x00 3. " QUADMODE ,Selects encoding mode used in quadrature decoder mode" "Phase encode,Count and direction encode"
|
|
rbitfld.long 0x00 2. " QUADIR ,Counter Direction in Quadrature Decode Mode" "Decrement,Increment"
|
|
rbitfld.long 0x00 1. " TOFDIR ,TOF bit was set on the top or the bottom of counting" "Bottom,Top"
|
|
newline
|
|
bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*")
|
|
if (((per.l(ad:0x4003A000+0x84)&0x800000))==0x00)
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM2_CONF,Configuration"
|
|
sif cpuis("MK84FN2M0CAU15R")
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,,,PIT Ch.0 Output,PIT Ch.1 Output,PIT Ch.2 Output,PIT Ch.3 Output,FTM_0 trigger,FTM_1 trigger,FTM_2 trigger,FTM_3 trigger,RTC alarm,RTC seconds,LPTMR Output,Software Trigger"
|
|
newline
|
|
elif cpuis("MK8?FN256V*")
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,CMP_1,,PIT Ch.0 Output,PIT Ch.1 Output,PIT Ch.2 Output,PIT Ch.3 Output,FTM_0 trigger,FTM_1 trigger,FTM_2 trigger,FTM_3 trigger,RTC alarm,RTC seconds,LPTMR Output,Software Trigger"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP0 output,,,PIT trigger 0,PIT trigger 1,,,TPM0 overflow,TPM1 overflow,TPM2 overflow,,RTC alarm,RTC seconds,LPTMR trigger,?..."
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
newline
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM2_CONF,Configuration"
|
|
sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" ",Ch_0 pin input capture,Ch_1 pin input capture,Ch_0 or ch_1 pin input capture,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" ",Ch_0 pin input capture,Ch_1 pin input capture,Ch_0 or ch_1 pin input capture,Ch_2 pin input capture,Ch_0 or ch_2 pin input capture,Ch_1 or ch_2 pin input capture,Ch_0 or ch_1 or ch_2 pin input capture,Ch_3 pin input capture,Ch_0 or ch_3 pin input capture,Ch_1 or ch_3 pin input capture,Ch_0 or ch_1 or ch_3 pin input capture,Ch_2 or ch_3 pin input capture,Ch_0 or ch_2 or ch_3 pin input capture,Ch_1 or ch_2 or ch_3 pin input capture,Ch_0 or ch_1 or ch_2 or ch_3 pin input capture"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
newline
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TPM2_CONF,Configuration"
|
|
sif cpuis("MKL02*")
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP0 output,,,,,,,TPM0 overflow,TMP1 overflow,,,,,LPTMR trigger,?..."
|
|
newline
|
|
elif cpuis("MKL03Z*")
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP0 output,,,,,,,TPM0 overflow,TPM1 overflow,,,RTC alarm,RTC seconds,LPTMR trigger,?..."
|
|
newline
|
|
elif cpuis("MKL04*")||cpuis("MKL05*")
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP0 output,,,PIT trigger 0,PIT trigger 1,,,TPM0 overflow,TPM1 overflow,,,RTC alarm,RTC seconds,LPTMR trigger,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP0 output,,,PIT trigger 0,PIT trigger 1,,,TPM0 overflow,TPM1 overflow,TPM2 overflow,,RTC alarm,RTC seconds,LPTMR trigger,?..."
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled"
|
|
bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03Z*")
|
|
tree "PIT (Periodic Interrupt Timer)"
|
|
base ad:0x40037000
|
|
width 9.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,PIT Module Control Register"
|
|
bitfld.long 0x00 1. " MDIS ,Module disable" "No,Yes"
|
|
bitfld.long 0x00 0. " FRZ ,Freeze in debug mode" "Not stopped,Stopped"
|
|
rgroup.long 0xE0++0x07
|
|
line.long 0x00 "LTMR64H,PIT Upper Lifetime Timer Register"
|
|
line.long 0x04 "LTMR64L,PIT Lower Lifetime Timer Register"
|
|
sif cpuis("MKL82Z*")
|
|
group.long 0x100++0x03 "PIT_0 Registers"
|
|
line.long 0x00 "LDVAL0,PIT0 Timer Load Value Register"
|
|
rgroup.long (0x100+0x04)++0x03
|
|
line.long 0x00 "CVAL0,PIT0 Current Timer Value Register"
|
|
group.long (0x100+0x08)++0x07
|
|
line.long 0x00 "TCTRL0,PIT0 Timer Control Register"
|
|
bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled"
|
|
line.long 0x04 "TFLG0,PIT0 Timer Flag Register"
|
|
eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "Not occurred,Occurred"
|
|
group.long 0x110++0x03 "PIT_1 Registers"
|
|
line.long 0x00 "LDVAL1,PIT1 Timer Load Value Register"
|
|
rgroup.long (0x110+0x04)++0x03
|
|
line.long 0x00 "CVAL1,PIT1 Current Timer Value Register"
|
|
group.long (0x110+0x08)++0x07
|
|
line.long 0x00 "TCTRL1,PIT1 Timer Control Register"
|
|
bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled"
|
|
line.long 0x04 "TFLG1,PIT1 Timer Flag Register"
|
|
eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "Not occurred,Occurred"
|
|
group.long 0x120++0x03 "PIT_2 Registers"
|
|
line.long 0x00 "LDVAL2,PIT2 Timer Load Value Register"
|
|
rgroup.long (0x120+0x04)++0x03
|
|
line.long 0x00 "CVAL2,PIT2 Current Timer Value Register"
|
|
group.long (0x120+0x08)++0x07
|
|
line.long 0x00 "TCTRL2,PIT2 Timer Control Register"
|
|
bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled"
|
|
line.long 0x04 "TFLG2,PIT2 Timer Flag Register"
|
|
eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "Not occurred,Occurred"
|
|
group.long 0x130++0x03 "PIT_3 Registers"
|
|
line.long 0x00 "LDVAL3,PIT3 Timer Load Value Register"
|
|
rgroup.long (0x130+0x04)++0x03
|
|
line.long 0x00 "CVAL3,PIT3 Current Timer Value Register"
|
|
group.long (0x130+0x08)++0x07
|
|
line.long 0x00 "TCTRL3,PIT3 Timer Control Register"
|
|
bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled"
|
|
line.long 0x04 "TFLG3,PIT3 Timer Flag Register"
|
|
eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "Not occurred,Occurred"
|
|
elif (cpuis("S32S247*")||cpuis("S32D248*"))
|
|
group.long 0x100++0x03 "PIT_0 Registers"
|
|
line.long 0x00 "LDVAL0,PIT0 Timer Load Value Register"
|
|
rgroup.long (0x100+0x04)++0x03
|
|
line.long 0x00 "CVAL0,Current Timer Value Register"
|
|
group.long (0x100+0x08)++0x07
|
|
line.long 0x00 "TCTRL0,Timer Control Register"
|
|
bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained"
|
|
bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled"
|
|
line.long 0x04 "TFLG0,Timer Flag Register"
|
|
eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "Not occurred,Occurred"
|
|
group.long 0x110++0x03 "PIT_1 Registers"
|
|
line.long 0x00 "LDVAL1,PIT1 Timer Load Value Register"
|
|
rgroup.long (0x110+0x04)++0x03
|
|
line.long 0x00 "CVAL1,Current Timer Value Register"
|
|
group.long (0x110+0x08)++0x07
|
|
line.long 0x00 "TCTRL1,Timer Control Register"
|
|
bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained"
|
|
bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled"
|
|
line.long 0x04 "TFLG1,Timer Flag Register"
|
|
eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "Not occurred,Occurred"
|
|
group.long 0x120++0x03 "PIT_2 Registers"
|
|
line.long 0x00 "LDVAL2,PIT2 Timer Load Value Register"
|
|
rgroup.long (0x120+0x04)++0x03
|
|
line.long 0x00 "CVAL2,Current Timer Value Register"
|
|
group.long (0x120+0x08)++0x07
|
|
line.long 0x00 "TCTRL2,Timer Control Register"
|
|
bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained"
|
|
bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled"
|
|
line.long 0x04 "TFLG2,Timer Flag Register"
|
|
eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "Not occurred,Occurred"
|
|
group.long 0x130++0x03 "PIT_3 Registers"
|
|
line.long 0x00 "LDVAL3,PIT3 Timer Load Value Register"
|
|
rgroup.long (0x130+0x04)++0x03
|
|
line.long 0x00 "CVAL3,Current Timer Value Register"
|
|
group.long (0x130+0x08)++0x07
|
|
line.long 0x00 "TCTRL3,Timer Control Register"
|
|
bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained"
|
|
bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled"
|
|
line.long 0x04 "TFLG3,Timer Flag Register"
|
|
eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "Not occurred,Occurred"
|
|
group.long 0x140++0x03 "PIT_4 Registers"
|
|
line.long 0x00 "LDVAL4,PIT4 Timer Load Value Register"
|
|
rgroup.long (0x140+0x04)++0x03
|
|
line.long 0x00 "CVAL4,Current Timer Value Register"
|
|
group.long (0x140+0x08)++0x07
|
|
line.long 0x00 "TCTRL4,Timer Control Register"
|
|
bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained"
|
|
bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled"
|
|
line.long 0x04 "TFLG4,Timer Flag Register"
|
|
eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "Not occurred,Occurred"
|
|
group.long 0x150++0x03 "PIT_5 Registers"
|
|
line.long 0x00 "LDVAL5,PIT5 Timer Load Value Register"
|
|
rgroup.long (0x150+0x04)++0x03
|
|
line.long 0x00 "CVAL5,Current Timer Value Register"
|
|
group.long (0x150+0x08)++0x07
|
|
line.long 0x00 "TCTRL5,Timer Control Register"
|
|
bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained"
|
|
bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled"
|
|
line.long 0x04 "TFLG5,Timer Flag Register"
|
|
eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "Not occurred,Occurred"
|
|
group.long 0x160++0x03 "PIT_6 Registers"
|
|
line.long 0x00 "LDVAL6,PIT6 Timer Load Value Register"
|
|
rgroup.long (0x160+0x04)++0x03
|
|
line.long 0x00 "CVAL6,Current Timer Value Register"
|
|
group.long (0x160+0x08)++0x07
|
|
line.long 0x00 "TCTRL6,Timer Control Register"
|
|
bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained"
|
|
bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled"
|
|
line.long 0x04 "TFLG6,Timer Flag Register"
|
|
eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "Not occurred,Occurred"
|
|
else
|
|
group.long 0x100++0x03 "PIT_0 Registers"
|
|
line.long 0x00 "LDVAL0,PIT0 Timer Load Value Register"
|
|
rgroup.long (0x100+0x04)++0x03
|
|
line.long 0x00 "CVAL0,PIT0 Current Timer Value Register"
|
|
group.long (0x100+0x08)++0x07
|
|
line.long 0x00 "TCTRL0,PIT0 Timer Control Register"
|
|
bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled"
|
|
line.long 0x04 "TFLG0,PIT0 Timer Flag Register"
|
|
eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "Not occurred,Occurred"
|
|
group.long 0x110++0x03 "PIT_1 Registers"
|
|
line.long 0x00 "LDVAL1,PIT1 Timer Load Value Register"
|
|
rgroup.long (0x110+0x04)++0x03
|
|
line.long 0x00 "CVAL1,PIT1 Current Timer Value Register"
|
|
group.long (0x110+0x08)++0x07
|
|
line.long 0x00 "TCTRL1,PIT1 Timer Control Register"
|
|
bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled"
|
|
line.long 0x04 "TFLG1,PIT1 Timer Flag Register"
|
|
eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "Not occurred,Occurred"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
elif cpuis("MKL28Z*")
|
|
tree "LPIT (Low Power Interrupt Timer)"
|
|
base ad:0x40030000
|
|
width 22.
|
|
endian.be
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number"
|
|
hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature number"
|
|
line.long 0x04 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " EXT_TRIG ,Number of external trigger inputs"
|
|
hexmask.long.byte 0x04 0.--7. 1. " CHANNEL ,Number of timer channels"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "MCR,Module Control Register"
|
|
bitfld.long 0x00 3. " DBG_EN ,Debug enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DOZE_EN ,DOZE mode enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SW_RST ,Software reset bit" "No reset,Reset"
|
|
bitfld.long 0x00 0. " M_CEN ,Module clock enable" "Disabled,Enabled"
|
|
line.long 0x04 "MSR,Module Status Register"
|
|
eventfld.long 0x04 3. " TIF3 ,Channel 3 timer interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 2. " TIF2 ,Channel 2 timer interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 1. " TIF1 ,Channel 1 timer interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 0. " TIF0 ,Channel 0 timer interrupt flag" "No interrupt,Interrupt"
|
|
line.long 0x08 "MIER,Module Interrupt Enable Register"
|
|
bitfld.long 0x08 3. " TIE3 ,Channel 3 timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " TIE2 ,Channel 2 timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " TIE1 ,Channel 1 timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TIE0 ,Channel 0 timer interrupt enable" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TEN_SET/CLR,Set/Clear Timer Enable Register"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " T_EN_3 ,Timer 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " T_EN_2 ,Timer 2 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " T_EN_1 ,Timer 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " T_EN_0 ,Timer 0 enable" "Disabled,Enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TVAL0,Timer Value Register"
|
|
rgroup.long (0x20+0x04)++0x03
|
|
line.long 0x00 "CVAL0,Current Timer Value"
|
|
if (((per.l.be(ad:0x40030000+0x20+0x08))&0x01)==0x00)
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "TCTRL0,Timer Control Register"
|
|
bitfld.long 0x00 24.--27. " TRG_SEL ,Trigger select" "Timer ch 0,Timer ch 1,Timer ch 2,Timer ch 3,?..."
|
|
bitfld.long 0x00 23. " TRG_SRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 18. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 16. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge"
|
|
bitfld.long 0x00 2.--3. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture"
|
|
bitfld.long 0x00 1. " CHAIN ,Chain channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " T_EN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "TCTRL0,Timer Control Register"
|
|
rbitfld.long 0x00 24.--27. " TRG_SEL ,Trigger select" "Timer ch 0,Timer ch 1,Timer ch 2,Timer ch 3,?..."
|
|
bitfld.long 0x00 23. " TRG_SRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 18. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 16. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge"
|
|
bitfld.long 0x00 2.--3. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture"
|
|
bitfld.long 0x00 1. " CHAIN ,Chain channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " T_EN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TVAL1,Timer Value Register"
|
|
rgroup.long (0x30+0x04)++0x03
|
|
line.long 0x00 "CVAL1,Current Timer Value"
|
|
if (((per.l.be(ad:0x40030000+0x30+0x08))&0x01)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "TCTRL1,Timer Control Register"
|
|
bitfld.long 0x00 24.--27. " TRG_SEL ,Trigger select" "Timer ch 0,Timer ch 1,Timer ch 2,Timer ch 3,?..."
|
|
bitfld.long 0x00 23. " TRG_SRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 18. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 16. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge"
|
|
bitfld.long 0x00 2.--3. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture"
|
|
bitfld.long 0x00 1. " CHAIN ,Chain channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " T_EN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "TCTRL1,Timer Control Register"
|
|
rbitfld.long 0x00 24.--27. " TRG_SEL ,Trigger select" "Timer ch 0,Timer ch 1,Timer ch 2,Timer ch 3,?..."
|
|
bitfld.long 0x00 23. " TRG_SRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 18. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 16. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge"
|
|
bitfld.long 0x00 2.--3. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture"
|
|
bitfld.long 0x00 1. " CHAIN ,Chain channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " T_EN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TVAL2,Timer Value Register"
|
|
rgroup.long (0x40+0x04)++0x03
|
|
line.long 0x00 "CVAL2,Current Timer Value"
|
|
if (((per.l.be(ad:0x40030000+0x40+0x08))&0x01)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TCTRL2,Timer Control Register"
|
|
bitfld.long 0x00 24.--27. " TRG_SEL ,Trigger select" "Timer ch 0,Timer ch 1,Timer ch 2,Timer ch 3,?..."
|
|
bitfld.long 0x00 23. " TRG_SRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 18. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 16. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge"
|
|
bitfld.long 0x00 2.--3. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture"
|
|
bitfld.long 0x00 1. " CHAIN ,Chain channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " T_EN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TCTRL2,Timer Control Register"
|
|
rbitfld.long 0x00 24.--27. " TRG_SEL ,Trigger select" "Timer ch 0,Timer ch 1,Timer ch 2,Timer ch 3,?..."
|
|
bitfld.long 0x00 23. " TRG_SRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 18. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 16. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge"
|
|
bitfld.long 0x00 2.--3. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture"
|
|
bitfld.long 0x00 1. " CHAIN ,Chain channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " T_EN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TVAL3,Timer Value Register"
|
|
rgroup.long (0x50+0x04)++0x03
|
|
line.long 0x00 "CVAL3,Current Timer Value"
|
|
if (((per.l.be(ad:0x40030000+0x50+0x08))&0x01)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "TCTRL3,Timer Control Register"
|
|
bitfld.long 0x00 24.--27. " TRG_SEL ,Trigger select" "Timer ch 0,Timer ch 1,Timer ch 2,Timer ch 3,?..."
|
|
bitfld.long 0x00 23. " TRG_SRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 18. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 16. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge"
|
|
bitfld.long 0x00 2.--3. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture"
|
|
bitfld.long 0x00 1. " CHAIN ,Chain channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " T_EN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "TCTRL3,Timer Control Register"
|
|
rbitfld.long 0x00 24.--27. " TRG_SEL ,Trigger select" "Timer ch 0,Timer ch 1,Timer ch 2,Timer ch 3,?..."
|
|
bitfld.long 0x00 23. " TRG_SRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 18. " TROT ,Timer reload on trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 17. " TSOI ,Timer stop on interrupt" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 16. " TSOT ,Timer start on trigger" "Decrement immediately,Decrement on rising edge"
|
|
bitfld.long 0x00 2.--3. " MODE ,Timer operation mode" "32-bit periodic counter,Dual 16-bit periodic counter,32-bit trigger accumulator,32-bit trigger input capture"
|
|
bitfld.long 0x00 1. " CHAIN ,Chain channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " T_EN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
endian.le
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "LPTMR (Low Power Timer)"
|
|
sif cpuis("MKL28Z*")
|
|
base ad:0x40034000
|
|
width 5.
|
|
sif cpuis("MKL28Z*")
|
|
group.long 0x0++0x03 "Low Power Timer Register 0"
|
|
line.long 0x00 "CSR,Low Power Timer Control Status Register"
|
|
bitfld.long 0x00 8. "TDRE,Timer DMA request enable" "Disabled,Enabled"
|
|
newline
|
|
eventfld.long 0x00 7. " TCF ,Timer compare flag" "Not equaled,Equaled"
|
|
bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP0,LPTMR_ALT1,LPTMR_ALT2,LPTMR_ALT3"
|
|
newline
|
|
bitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " TFC ,Timer free running counter" "Reset on TCF set,Reset on overflow"
|
|
newline
|
|
bitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter"
|
|
bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40034000+0x0))&0x02)==0x00)
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
newline
|
|
bitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Not bypassed,Bypassed"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK"
|
|
else
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
bitfld.long 0x00 3.--6. " GFW ,Glitch filter width" "Disabled,2 clk edges,4 clk edges,8 clk edges,16 clk edges,32 clk edges,64 clk edges,128 clk edges,256 clk edges,512 clk edges,1024 clk edges,2048 clk edges,4096 clk edges,8192 clk edges,16384 clk edges,32768 clk edges"
|
|
newline
|
|
bitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Not bypassed,Bypassed"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK"
|
|
endif
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "CMR,Low Power Timer Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COMPARE ,Compare value"
|
|
group.long (0x0+0x0C)++0x03
|
|
line.long 0x00 "CNR,Low Power Timer Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter value"
|
|
group.long 0x1000++0x03 "Low Power Timer Register 1"
|
|
line.long 0x00 "CSR,Low Power Timer Control Status Register"
|
|
bitfld.long 0x00 8. "TDRE,Timer DMA request enable" "Disabled,Enabled"
|
|
newline
|
|
eventfld.long 0x00 7. " TCF ,Timer compare flag" "Not equaled,Equaled"
|
|
bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP0,LPTMR_ALT1,LPTMR_ALT2,LPTMR_ALT3"
|
|
newline
|
|
bitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " TFC ,Timer free running counter" "Reset on TCF set,Reset on overflow"
|
|
newline
|
|
bitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter"
|
|
bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40034000+0x1000))&0x02)==0x00)
|
|
group.long (0x1000+0x04)++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
newline
|
|
bitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Not bypassed,Bypassed"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK"
|
|
else
|
|
group.long (0x1000+0x04)++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
bitfld.long 0x00 3.--6. " GFW ,Glitch filter width" "Disabled,2 clk edges,4 clk edges,8 clk edges,16 clk edges,32 clk edges,64 clk edges,128 clk edges,256 clk edges,512 clk edges,1024 clk edges,2048 clk edges,4096 clk edges,8192 clk edges,16384 clk edges,32768 clk edges"
|
|
newline
|
|
bitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Not bypassed,Bypassed"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK"
|
|
endif
|
|
group.long (0x1000+0x08)++0x03
|
|
line.long 0x00 "CMR,Low Power Timer Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COMPARE ,Compare value"
|
|
group.long (0x1000+0x0C)++0x03
|
|
line.long 0x00 "CNR,Low Power Timer Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter value"
|
|
elif cpuis("MKL82Z*")
|
|
group.long 0x0++0x03 "Low Power Timer Register 0"
|
|
line.long 0x00 "CSR,Low Power Timer Control Status Register"
|
|
eventfld.long 0x00 7. " TCF ,Timer compare flag" "Not equaled,Equaled"
|
|
bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP0,LPTMR_ALT1,LPTMR_ALT2,LPTMR_ALT3"
|
|
newline
|
|
bitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " TFC ,Timer free running counter" "Reset on TCF set,Reset on overflow"
|
|
newline
|
|
bitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter"
|
|
bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40034000+0x0))&0x02)==0x00)
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
newline
|
|
bitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Not bypassed,Bypassed"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK"
|
|
else
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
bitfld.long 0x00 3.--6. " GFW ,Glitch filter width" "Disabled,2 clk edges,4 clk edges,8 clk edges,16 clk edges,32 clk edges,64 clk edges,128 clk edges,256 clk edges,512 clk edges,1024 clk edges,2048 clk edges,4096 clk edges,8192 clk edges,16384 clk edges,32768 clk edges"
|
|
newline
|
|
bitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Not bypassed,Bypassed"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK"
|
|
endif
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "CMR,Low Power Timer Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COMPARE ,Compare value"
|
|
group.long (0x0+0x0C)++0x03
|
|
line.long 0x00 "CNR,Low Power Timer Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter value"
|
|
group.long 0x4000++0x03 "Low Power Timer Register 1"
|
|
line.long 0x00 "CSR,Low Power Timer Control Status Register"
|
|
eventfld.long 0x00 7. " TCF ,Timer compare flag" "Not equaled,Equaled"
|
|
bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP0,LPTMR_ALT1,LPTMR_ALT2,LPTMR_ALT3"
|
|
newline
|
|
bitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " TFC ,Timer free running counter" "Reset on TCF set,Reset on overflow"
|
|
newline
|
|
bitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter"
|
|
bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40034000+0x4000))&0x02)==0x00)
|
|
group.long (0x4000+0x04)++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
newline
|
|
bitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Not bypassed,Bypassed"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK"
|
|
else
|
|
group.long (0x4000+0x04)++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
bitfld.long 0x00 3.--6. " GFW ,Glitch filter width" "Disabled,2 clk edges,4 clk edges,8 clk edges,16 clk edges,32 clk edges,64 clk edges,128 clk edges,256 clk edges,512 clk edges,1024 clk edges,2048 clk edges,4096 clk edges,8192 clk edges,16384 clk edges,32768 clk edges"
|
|
newline
|
|
bitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Not bypassed,Bypassed"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK"
|
|
endif
|
|
group.long (0x4000+0x08)++0x03
|
|
line.long 0x00 "CMR,Low Power Timer Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COMPARE ,Compare value"
|
|
group.long (0x4000+0x0C)++0x03
|
|
line.long 0x00 "CNR,Low Power Timer Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter value"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CSR,Low Power Timer Control Status Register"
|
|
eventfld.long 0x00 7. " TCF ,Timer compare flag" "Not equaled,Equaled"
|
|
bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpu()=="MK21DX128VMC5")||(cpu()=="MK21DX256VMC5")||(cpu()=="MK21DN512VMC5")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||cpuis("MKL02*")||cpuis("MKL03Z*")||cpuis("MKL04Z*")||cpuis("MKL05Z*")||cpuis("MKL13Z*")||cpuis("MK14L*")||cpuis("MKL14Z*")||cpuis("MK15L*")||cpuis("MKL15Z*")||cpuis("MKL16*")||cpuis("MKL17Z*")||cpuis("MKL24Z*")||cpuis("MKL25Z*")||cpuis("MKL26*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL43Z*")||cpuis("MKL46Z*")
|
|
bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP0,LPTMR_ALT1,LPTMR_ALT2,LPTMR_ALT3"
|
|
newline
|
|
elif (cpu()=="MK22DX128VLF5")||(cpu()=="MK22DX256VLF5")||(cpu()=="MK22DX128VLH5")||(cpu()=="MK22DX256VLH5")||(cpu()=="MK22DN512VLH5")||(cpu()=="MK22DX128VLK5")||(cpu()=="MK22DX256VLK5")||(cpu()=="MK22DN512VLK5")||(cpu()=="MK22DX128VMC5")||(cpu()=="MK22DX256VMC5")||(cpu()=="MK22DN512VMC5")||(cpu()=="MK21DX128VLK5")||(cpu()=="MK21DX256VLK5")||(cpu()=="MK21DN512VLK5")||(cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")
|
|
bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP0,LPTMR_ALT1,LPTMR_ALT2,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "HSCMP,LPT_ALT1,LPT_ALT2,LPT_ALT3"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " TFC ,Timer free running counter" "Reset on TCF set,Reset on overflow"
|
|
newline
|
|
bitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter"
|
|
bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40034000))&0x02)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
sif (cpu()=="MK21DX128VLK5")||(cpu()=="MK21DX256VLK5")||(cpu()=="MK21DN512VLK5")||(cpu()=="MK21DX128VMC5")||(cpu()=="MK21DX256VMC5")||(cpu()=="MK21DN512VMC5")||(cpu()=="MK22DX128VLF5")||(cpu()=="MK22DX256VLF5")||(cpu()=="MK22DX128VLH5")||(cpu()=="MK22DX256VLH5")||(cpu()=="MK22DN512VLH5")||(cpu()=="MK22DX128VLK5")||(cpu()=="MK22DX256VLK5")||(cpu()=="MK22DN512VLK5")||(cpu()=="MK22DX128VMC5")||(cpu()=="MK22DX256VMC5")||(cpu()=="MK22DN512VMC5")||(cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")||cpuis("MKL02*")||cpuis("MKL03Z*")||cpuis("MKL04Z*")||cpuis("MKL05Z*")||cpuis("MKL13Z*")||cpuis("MK14L*")||cpuis("MKL14Z*")||cpuis("MK15L*")||cpuis("MKL15Z*")||cpuis("MKL16*")||cpuis("MKL17Z*")||cpuis("MKL24Z*")||cpuis("MKL25Z*")||cpuis("MKL26*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL43Z*")||cpuis("MKL46Z*")
|
|
bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "Disabled,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Not bypassed,Bypassed"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
bitfld.long 0x00 3.--6. " GFW ,Glitch filter width" "Disabled,2 clk edges,4 clk edges,8 clk edges,16 clk edges,32 clk edges,64 clk edges,128 clk edges,256 clk edges,512 clk edges,1024 clk edges,2048 clk edges,4096 clk edges,8192 clk edges,16384 clk edges,32768 clk edges"
|
|
newline
|
|
bitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Not bypassed,Bypassed"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CMR,Low Power Timer Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COMPARE ,Compare value"
|
|
sif (cpu()=="MK21DX128VLK5")||(cpu()=="MK21DX256VLK5")||(cpu()=="MK21DN512VLK5")||(cpu()=="MK21DX128VMC5")||(cpu()=="MK21DX256VMC5")||(cpu()=="MK21DN512VMC5")||(cpu()=="MK22DX128VLF5")||(cpu()=="MK22DX256VLF5")||(cpu()=="MK22DX128VLH5")||(cpu()=="MK22DX256VLH5")||(cpu()=="MK22DN512VLH5")||(cpu()=="MK22DX128VLK5")||(cpu()=="MK22DX256VLK5")||(cpu()=="MK22DN512VLK5")||(cpu()=="MK22DX128VMC5")||(cpu()=="MK22DX256VMC5")||(cpu()=="MK22DN512VMC5")||(cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")||cpuis("MKL02*")||cpuis("MKL03Z*")||cpuis("MKL04Z*")||cpuis("MKL05Z*")||cpuis("MK14L*")||cpuis("MKL14Z*")||cpuis("MK15L*")||cpuis("MKL15Z*")||cpuis("MKL16*")||cpuis("MKL24Z*")||cpuis("MKL25Z*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CNR,Low Power Timer Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter value"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CNR,Low Power Timer Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter value"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
else
|
|
base ad:0x40040000
|
|
width 5.
|
|
sif cpuis("MKL28Z*")
|
|
group.long 0x0++0x03 "Low Power Timer Register 0"
|
|
line.long 0x00 "CSR,Low Power Timer Control Status Register"
|
|
bitfld.long 0x00 8. "TDRE,Timer DMA request enable" "Disabled,Enabled"
|
|
newline
|
|
eventfld.long 0x00 7. " TCF ,Timer compare flag" "Not equaled,Equaled"
|
|
bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP0,LPTMR_ALT1,LPTMR_ALT2,LPTMR_ALT3"
|
|
newline
|
|
bitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " TFC ,Timer free running counter" "Reset on TCF set,Reset on overflow"
|
|
newline
|
|
bitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter"
|
|
bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40040000+0x0))&0x02)==0x00)
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
newline
|
|
bitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Not bypassed,Bypassed"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK"
|
|
else
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
bitfld.long 0x00 3.--6. " GFW ,Glitch filter width" "Disabled,2 clk edges,4 clk edges,8 clk edges,16 clk edges,32 clk edges,64 clk edges,128 clk edges,256 clk edges,512 clk edges,1024 clk edges,2048 clk edges,4096 clk edges,8192 clk edges,16384 clk edges,32768 clk edges"
|
|
newline
|
|
bitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Not bypassed,Bypassed"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK"
|
|
endif
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "CMR,Low Power Timer Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COMPARE ,Compare value"
|
|
group.long (0x0+0x0C)++0x03
|
|
line.long 0x00 "CNR,Low Power Timer Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter value"
|
|
group.long 0x1000++0x03 "Low Power Timer Register 1"
|
|
line.long 0x00 "CSR,Low Power Timer Control Status Register"
|
|
bitfld.long 0x00 8. "TDRE,Timer DMA request enable" "Disabled,Enabled"
|
|
newline
|
|
eventfld.long 0x00 7. " TCF ,Timer compare flag" "Not equaled,Equaled"
|
|
bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP0,LPTMR_ALT1,LPTMR_ALT2,LPTMR_ALT3"
|
|
newline
|
|
bitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " TFC ,Timer free running counter" "Reset on TCF set,Reset on overflow"
|
|
newline
|
|
bitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter"
|
|
bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40040000+0x1000))&0x02)==0x00)
|
|
group.long (0x1000+0x04)++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
newline
|
|
bitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Not bypassed,Bypassed"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK"
|
|
else
|
|
group.long (0x1000+0x04)++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
bitfld.long 0x00 3.--6. " GFW ,Glitch filter width" "Disabled,2 clk edges,4 clk edges,8 clk edges,16 clk edges,32 clk edges,64 clk edges,128 clk edges,256 clk edges,512 clk edges,1024 clk edges,2048 clk edges,4096 clk edges,8192 clk edges,16384 clk edges,32768 clk edges"
|
|
newline
|
|
bitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Not bypassed,Bypassed"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK"
|
|
endif
|
|
group.long (0x1000+0x08)++0x03
|
|
line.long 0x00 "CMR,Low Power Timer Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COMPARE ,Compare value"
|
|
group.long (0x1000+0x0C)++0x03
|
|
line.long 0x00 "CNR,Low Power Timer Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter value"
|
|
elif cpuis("MKL82Z*")
|
|
group.long 0x0++0x03 "Low Power Timer Register 0"
|
|
line.long 0x00 "CSR,Low Power Timer Control Status Register"
|
|
eventfld.long 0x00 7. " TCF ,Timer compare flag" "Not equaled,Equaled"
|
|
bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP0,LPTMR_ALT1,LPTMR_ALT2,LPTMR_ALT3"
|
|
newline
|
|
bitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " TFC ,Timer free running counter" "Reset on TCF set,Reset on overflow"
|
|
newline
|
|
bitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter"
|
|
bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40040000+0x0))&0x02)==0x00)
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
newline
|
|
bitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Not bypassed,Bypassed"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK"
|
|
else
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
bitfld.long 0x00 3.--6. " GFW ,Glitch filter width" "Disabled,2 clk edges,4 clk edges,8 clk edges,16 clk edges,32 clk edges,64 clk edges,128 clk edges,256 clk edges,512 clk edges,1024 clk edges,2048 clk edges,4096 clk edges,8192 clk edges,16384 clk edges,32768 clk edges"
|
|
newline
|
|
bitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Not bypassed,Bypassed"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK"
|
|
endif
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "CMR,Low Power Timer Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COMPARE ,Compare value"
|
|
group.long (0x0+0x0C)++0x03
|
|
line.long 0x00 "CNR,Low Power Timer Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter value"
|
|
group.long 0x4000++0x03 "Low Power Timer Register 1"
|
|
line.long 0x00 "CSR,Low Power Timer Control Status Register"
|
|
eventfld.long 0x00 7. " TCF ,Timer compare flag" "Not equaled,Equaled"
|
|
bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP0,LPTMR_ALT1,LPTMR_ALT2,LPTMR_ALT3"
|
|
newline
|
|
bitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " TFC ,Timer free running counter" "Reset on TCF set,Reset on overflow"
|
|
newline
|
|
bitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter"
|
|
bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40040000+0x4000))&0x02)==0x00)
|
|
group.long (0x4000+0x04)++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
newline
|
|
bitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Not bypassed,Bypassed"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK"
|
|
else
|
|
group.long (0x4000+0x04)++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
bitfld.long 0x00 3.--6. " GFW ,Glitch filter width" "Disabled,2 clk edges,4 clk edges,8 clk edges,16 clk edges,32 clk edges,64 clk edges,128 clk edges,256 clk edges,512 clk edges,1024 clk edges,2048 clk edges,4096 clk edges,8192 clk edges,16384 clk edges,32768 clk edges"
|
|
newline
|
|
bitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Not bypassed,Bypassed"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK"
|
|
endif
|
|
group.long (0x4000+0x08)++0x03
|
|
line.long 0x00 "CMR,Low Power Timer Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COMPARE ,Compare value"
|
|
group.long (0x4000+0x0C)++0x03
|
|
line.long 0x00 "CNR,Low Power Timer Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter value"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CSR,Low Power Timer Control Status Register"
|
|
eventfld.long 0x00 7. " TCF ,Timer compare flag" "Not equaled,Equaled"
|
|
bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpu()=="MK21DX128VMC5")||(cpu()=="MK21DX256VMC5")||(cpu()=="MK21DN512VMC5")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||cpuis("MKL02*")||cpuis("MKL03Z*")||cpuis("MKL04Z*")||cpuis("MKL05Z*")||cpuis("MKL13Z*")||cpuis("MK14L*")||cpuis("MKL14Z*")||cpuis("MK15L*")||cpuis("MKL15Z*")||cpuis("MKL16*")||cpuis("MKL17Z*")||cpuis("MKL24Z*")||cpuis("MKL25Z*")||cpuis("MKL26*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL43Z*")||cpuis("MKL46Z*")
|
|
bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP0,LPTMR_ALT1,LPTMR_ALT2,LPTMR_ALT3"
|
|
newline
|
|
elif (cpu()=="MK22DX128VLF5")||(cpu()=="MK22DX256VLF5")||(cpu()=="MK22DX128VLH5")||(cpu()=="MK22DX256VLH5")||(cpu()=="MK22DN512VLH5")||(cpu()=="MK22DX128VLK5")||(cpu()=="MK22DX256VLK5")||(cpu()=="MK22DN512VLK5")||(cpu()=="MK22DX128VMC5")||(cpu()=="MK22DX256VMC5")||(cpu()=="MK22DN512VMC5")||(cpu()=="MK21DX128VLK5")||(cpu()=="MK21DX256VLK5")||(cpu()=="MK21DN512VLK5")||(cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")
|
|
bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP0,LPTMR_ALT1,LPTMR_ALT2,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "HSCMP,LPT_ALT1,LPT_ALT2,LPT_ALT3"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " TFC ,Timer free running counter" "Reset on TCF set,Reset on overflow"
|
|
newline
|
|
bitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter"
|
|
bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40040000))&0x02)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
sif (cpu()=="MK21DX128VLK5")||(cpu()=="MK21DX256VLK5")||(cpu()=="MK21DN512VLK5")||(cpu()=="MK21DX128VMC5")||(cpu()=="MK21DX256VMC5")||(cpu()=="MK21DN512VMC5")||(cpu()=="MK22DX128VLF5")||(cpu()=="MK22DX256VLF5")||(cpu()=="MK22DX128VLH5")||(cpu()=="MK22DX256VLH5")||(cpu()=="MK22DN512VLH5")||(cpu()=="MK22DX128VLK5")||(cpu()=="MK22DX256VLK5")||(cpu()=="MK22DN512VLK5")||(cpu()=="MK22DX128VMC5")||(cpu()=="MK22DX256VMC5")||(cpu()=="MK22DN512VMC5")||(cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")||cpuis("MKL02*")||cpuis("MKL03Z*")||cpuis("MKL04Z*")||cpuis("MKL05Z*")||cpuis("MKL13Z*")||cpuis("MK14L*")||cpuis("MKL14Z*")||cpuis("MK15L*")||cpuis("MKL15Z*")||cpuis("MKL16*")||cpuis("MKL17Z*")||cpuis("MKL24Z*")||cpuis("MKL25Z*")||cpuis("MKL26*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL43Z*")||cpuis("MKL46Z*")
|
|
bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "Disabled,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Not bypassed,Bypassed"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
bitfld.long 0x00 3.--6. " GFW ,Glitch filter width" "Disabled,2 clk edges,4 clk edges,8 clk edges,16 clk edges,32 clk edges,64 clk edges,128 clk edges,256 clk edges,512 clk edges,1024 clk edges,2048 clk edges,4096 clk edges,8192 clk edges,16384 clk edges,32768 clk edges"
|
|
newline
|
|
bitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Not bypassed,Bypassed"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CMR,Low Power Timer Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COMPARE ,Compare value"
|
|
sif (cpu()=="MK21DX128VLK5")||(cpu()=="MK21DX256VLK5")||(cpu()=="MK21DN512VLK5")||(cpu()=="MK21DX128VMC5")||(cpu()=="MK21DX256VMC5")||(cpu()=="MK21DN512VMC5")||(cpu()=="MK22DX128VLF5")||(cpu()=="MK22DX256VLF5")||(cpu()=="MK22DX128VLH5")||(cpu()=="MK22DX256VLH5")||(cpu()=="MK22DN512VLH5")||(cpu()=="MK22DX128VLK5")||(cpu()=="MK22DX256VLK5")||(cpu()=="MK22DN512VLK5")||(cpu()=="MK22DX128VMC5")||(cpu()=="MK22DX256VMC5")||(cpu()=="MK22DN512VMC5")||(cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")||cpuis("MKL02*")||cpuis("MKL03Z*")||cpuis("MKL04Z*")||cpuis("MKL05Z*")||cpuis("MK14L*")||cpuis("MKL14Z*")||cpuis("MK15L*")||cpuis("MKL15Z*")||cpuis("MKL16*")||cpuis("MKL24Z*")||cpuis("MKL25Z*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CNR,Low Power Timer Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter value"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CNR,Low Power Timer Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter value"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
sif cpuis("MKL13*")||cpuis("MKL17Z32*")||cpuis("MKL17Z64*")||cpuis("MKL27Z32*")||cpuis("MKL27Z64*")||cpuis("MKL28Z*")||cpuis("MKL33Z32*")||cpuis("MKL33Z64*")||cpuis("MKL82Z*")
|
|
tree "CRC (Cyclic Redundancy Check)"
|
|
sif cpuis("MKL28Z*")
|
|
base ad:0x40078000
|
|
width 9.
|
|
if (((per.l(ad:0x40078000+0x08))&0x3000000)==0x2000000)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "DATA_L,CRC Data Low Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " LU ,CRC low upper byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " LL ,CRC low lower byte"
|
|
hgroup.word 0x02++0x01
|
|
hide.word 0x00 "DATA_H,CRC Data Low Register"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "DATA_L,CRC Data Low Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " LU ,CRC high upper byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " LL ,CRC high lower byte"
|
|
group.word 0x02++0x01
|
|
line.word 0x00 "DATA_H,CRC Data High Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " HU ,CRC low upper byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " HL ,CRC low lower byte"
|
|
endif
|
|
if (((per.l(ad:0x40078000+0x08))&0x1000000)==0x1000000)
|
|
group.word 0x04++0x03
|
|
line.word 0x00 "GPOLY_L,CRC Polynomial Low Register"
|
|
hexmask.word 0x00 0.--15. 1. " LOW ,Low polynominal half-word"
|
|
line.word 0x02 "GPOLY_H,CRC Polynomial High Register"
|
|
hexmask.word 0x02 0.--15. 1. " HIGH ,High polynominal half-word"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "GPOLY_L,CRC Polynomial Low Register"
|
|
hexmask.word 0x00 0.--15. 1. " LOW ,Low polynominal half-word"
|
|
hgroup.word 0x06++0x01
|
|
hide.word 0x00 "GPOLY_H,CRC Polynomial High Register"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 30.--31. " TOT ,Type of transpose for writes" "No transposition,Bits only,Bits and bytes,Bytes only"
|
|
bitfld.long 0x00 28.--29. " TOTR ,Type of transpose for read" "No transposition,Bits only,Bits and bytes,Bytes only"
|
|
bitfld.long 0x00 26. " FXOR ,Bit to enable xor-ing the final checksum value while reading" "No XOR,XOR"
|
|
newline
|
|
bitfld.long 0x00 25. " WAS ,Write CRC data register as seed" "Data,Seed"
|
|
bitfld.long 0x00 24. " TCRC ,Width of CRC" "16-bit,32-bit"
|
|
width 0x0B
|
|
else
|
|
base ad:0x40032000
|
|
width 9.
|
|
if (((per.l(ad:0x40032000+0x08))&0x3000000)==0x2000000)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "DATA_L,CRC Data Low Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " LU ,CRC low upper byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " LL ,CRC low lower byte"
|
|
hgroup.word 0x02++0x01
|
|
hide.word 0x00 "DATA_H,CRC Data Low Register"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "DATA_L,CRC Data Low Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " LU ,CRC high upper byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " LL ,CRC high lower byte"
|
|
group.word 0x02++0x01
|
|
line.word 0x00 "DATA_H,CRC Data High Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " HU ,CRC low upper byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " HL ,CRC low lower byte"
|
|
endif
|
|
if (((per.l(ad:0x40032000+0x08))&0x1000000)==0x1000000)
|
|
group.word 0x04++0x03
|
|
line.word 0x00 "GPOLY_L,CRC Polynomial Low Register"
|
|
hexmask.word 0x00 0.--15. 1. " LOW ,Low polynominal half-word"
|
|
line.word 0x02 "GPOLY_H,CRC Polynomial High Register"
|
|
hexmask.word 0x02 0.--15. 1. " HIGH ,High polynominal half-word"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "GPOLY_L,CRC Polynomial Low Register"
|
|
hexmask.word 0x00 0.--15. 1. " LOW ,Low polynominal half-word"
|
|
hgroup.word 0x06++0x01
|
|
hide.word 0x00 "GPOLY_H,CRC Polynomial High Register"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 30.--31. " TOT ,Type of transpose for writes" "No transposition,Bits only,Bits and bytes,Bytes only"
|
|
bitfld.long 0x00 28.--29. " TOTR ,Type of transpose for read" "No transposition,Bits only,Bits and bytes,Bytes only"
|
|
bitfld.long 0x00 26. " FXOR ,Bit to enable xor-ing the final checksum value while reading" "No XOR,XOR"
|
|
newline
|
|
bitfld.long 0x00 25. " WAS ,Write CRC data register as seed" "Data,Seed"
|
|
bitfld.long 0x00 24. " TCRC ,Width of CRC" "16-bit,32-bit"
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("MKL82Z*")
|
|
tree "LTC (LP Trusted Cryptography)"
|
|
base ad:0x40051000
|
|
width 14.
|
|
if (((per.l(ad:0x40058000))&0xF00000)==0x800000)
|
|
if (((per.l(ad:0x40058000))&0x3F)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LTC0_MDPK,LTC Mode (PublicKey)"
|
|
bitfld.long 0x00 20.--23. " ALG ,Algorithm" ",AES,DES,,,,,,PKHA,?..."
|
|
bitfld.long 0x00 19. " ARAM ,Aram" "A not selected,A selected"
|
|
bitfld.long 0x00 18. " BRAM ,Bram" "B not selected,B selected"
|
|
newline
|
|
bitfld.long 0x00 17. " ERAM ,Eram" "E not selected,E selected"
|
|
bitfld.long 0x00 16. " NRAM ,Nram" "N not selected,N selected"
|
|
bitfld.long 0x00 9. " Q3 ,Quadrant 3" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 8. " Q2 ,Quadrant 2" "Not selected,Selected"
|
|
bitfld.long 0x00 7. " Q1 ,Quadrant 1" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " Q0 ,Quadrant 0" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " Function ,Function" ",,(A + B) mod N,(A - B) mod N,(B - A) mod N,(A x B) mod N,A^E mod N,A mod N,A^-1 mod N,(P1 + P2),(P2 + P2),(E x P1),,,GCD(A,N),Miller-Rabin Primality Test,?..."
|
|
elif (((per.l(ad:0x40058000))&0x1F)==(0x10||0x11))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LTC0_MDPK,LTC Mode (PublicKey)"
|
|
bitfld.long 0x00 20.--23. " ALG ,Algorithm" ",AES,DES,,,,,,PKHA,?..."
|
|
bitfld.long 0x00 17.--19. " Source_Register ,Source Register" "A,B,,N,?..."
|
|
bitfld.long 0x00 10.--11. 16. " Destination_Register ,Destination Register" "A,B,E,N,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--9. " SOURCE_SEGMENT ,Source Segment" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " DESTINATION_SEGMENT ,Destination Segment" "0,1,2,3"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 0.--5. " FUNCTION ,Function" ",,(A + B) mod N,(A - B) mod N,(B - A) mod N,(A x B) mod N,A^E mod N,A mod N,A^-1 mod N,(P1 + P2),(P2 + P2),(E x P1),,,GCD(A,N),Miller-Rabin Primality Test,?..."
|
|
elif (((per.l(ad:0x40058000))&0xF0)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LTC0_MDPK,LTC Mode (PublicKey)"
|
|
bitfld.long 0x00 20.--23. " ALG ,Algorithm" ",AES,DES,,,,,,PKHA,?..."
|
|
bitfld.long 0x00 19. " INM ,Inputs in Montgomery Format" "Normal,Montgomery"
|
|
bitfld.long 0x00 18. " OUTM ,Outputs in Montgomery format" "Normal,Montgomery"
|
|
newline
|
|
bitfld.long 0x00 17. " F2M ,F2m" "Integer,Binary"
|
|
bitfld.long 0x00 16. " R2 ,R2 mod N" "Calculated,Input"
|
|
bitfld.long 0x00 10. " TEQ ,Timing Equalized" "Not Equalized,Equalized"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " OUTSEL ,Output destination select" "B,A,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--5. " Function ,Function" ",,(A + B) mod N,(A - B) mod N,(B - A) mod N,(A x B) mod N,A^E mod N,A mod N,A^-1 mod N,(P1 + P2),(P2 + P2),(E x P1),,,GCD(A,N),Miller-Rabin Primality Test,?..."
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LTC0_MDPK,LTC Mode (PublicKey)"
|
|
bitfld.long 0x00 20.--23. " ALG ,Algorithm" ",AES,DES,,,,,,PKHA,?..."
|
|
newline
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 0.--5. " Function ,Function" ",,(A + B) mod N,(A - B) mod N,(B - A) mod N,(A x B) mod N,A^E mod N,A mod N,A^-1 mod N,(P1 + P2),(P2 + P2),(E x P1),,,GCD(A,N),Miller-Rabin Primality Test,?..."
|
|
endif
|
|
elif (((per.l(ad:0x40058000))&0xFF0000)==0x100000)&&(((per.l(ad:0x40058000))&0x1F00)==0x200)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LTC0_MD,LTC Mode (non-PKHA/non-RNG use)"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ALG ,Algorithm"
|
|
hexmask.long.word 0x00 4.--12. 1. " AAI ,Additional Algorithm information"
|
|
bitfld.long 0x00 2.--3. " AS ,Algorithm State" "Updated,Initialized,Finalized,Initialized/Finalized"
|
|
newline
|
|
bitfld.long 0x00 1. " ICV_TEST ,ICV Checking" "Not Compared,Compared"
|
|
bitfld.long 0x00 0. " ENC ,Encrypt/Decrypt" "Decrypted,Encrypted"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LTC0_MD,LTC Mode (non-PKHA/non-RNG use)"
|
|
bitfld.long 0x00 16.--23. " ALG ,Algorithm" ",,,,,,,,,,,,,,,,AES,,,,,,,,,,,,,,,,DES,3DES,?..."
|
|
hexmask.long.word 0x00 4.--12. 1. " AAI ,Additional Algorithm information"
|
|
bitfld.long 0x00 2.--3. " AS ,Algorithm State" "Updated,Initialized,Finalized,Initialized/Finalized"
|
|
newline
|
|
bitfld.long 0x00 1. " ICV_TEST ,Test AES fault detection" "Not Injected,Injected"
|
|
bitfld.long 0x00 0. " ENC ,Encrypt/Decrypt" "Decrypted,Encrypted"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "LTC0_KS,LTC Key Size"
|
|
bitfld.long 0x00 0.--5. " KS ,Key Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "LTC0_DS,LTC Data Size"
|
|
hexmask.long.word 0x00 0.--11. 1. " DS ,Data Size"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "LTC0_ICVS,LTC ICV Size"
|
|
bitfld.long 0x00 0.--4. " ICVS ,ICV Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "LTC0_COM,LTC Command"
|
|
sif cpuis("MKL82Z*")
|
|
bitfld.long 0x00 7. " MD ,Reset MDHA" "No effect,Reset"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 6. " PK ,Reset PKHA" "No effect,Reset"
|
|
bitfld.long 0x00 2. " DES ,Reset DESA" "No effect,Reset"
|
|
bitfld.long 0x00 1. " AES ,Reset AESA" "No effect,Reset"
|
|
bitfld.long 0x00 0. " ALL ,Reset All Internal Logic" "No effect,Reset"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "LTC0_CTL,LTC Control"
|
|
bitfld.long 0x00 31. " KAL ,Key Register Access Lock" "Not locked,Locked"
|
|
bitfld.long 0x00 23. " COS ,Context Register Output Byte Swap" "Not swapped,Swapped"
|
|
bitfld.long 0x00 22. " CIS ,Context Register Input Byte Swap" "Not swapped,Swapped"
|
|
newline
|
|
bitfld.long 0x00 21. " KOS ,Key Register Output Byte Swap" "Not swapped,Swapped"
|
|
bitfld.long 0x00 20. " KIS ,Key Register Input Byte Swap" "Not swapped,Swapped"
|
|
bitfld.long 0x00 17. " OFS ,Output FIFO Byte Swap" "Not swapped,Swapped"
|
|
newline
|
|
bitfld.long 0x00 16. " IFS ,Input FIFO Byte Swap" "Not swapped,Swapped"
|
|
bitfld.long 0x00 13. " OFR ,Output FIFO DMA Request Size" "1 Entry,4 Entries"
|
|
bitfld.long 0x00 12. " OFE ,Output FIFO DMA Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " IFR ,Input FIFO DMA Request Size" "1 Entry,4 Entries"
|
|
bitfld.long 0x00 8. " IFE ,Input FIFO DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PDE ,PKHA Register DMA Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " IM ,Interrupt Mask" "Not masked,Masked"
|
|
wgroup.long 0x40++0x03
|
|
line.long 0x00 "LTC0_CW,LTC Clear Written"
|
|
bitfld.long 0x00 31. " CIF ,Clear Input FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 30. " COF ,Clear Output FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 15. " CPKE ,Clear the PKHA E Size Register" "No effect,Clear"
|
|
bitfld.long 0x00 14. " CPKN ,Clear the PKHA N Size Register" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 13. " CPKB ,Clear the PHKA B Size Register" "No effect,Clear"
|
|
bitfld.long 0x00 12. " CPKA ,Clear the PHKA A Size Register" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CKR ,Clear the Key Register" "No effect,Clear"
|
|
bitfld.long 0x00 5. " CCR ,Clear the Context Register" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 3. " CICV ,Clear the ICV Size Register" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CDS ,Clear the Data Size Register" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CM ,Clear the Mode Register" "No effect,Clear"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "LTC0_STA,LTC Status"
|
|
rbitfld.long 0x00 30. " PKZ ,Public Key Operation is Zero" "Not zero,Zero"
|
|
rbitfld.long 0x00 29. " PKO ,Public Key Operation is One" "Not one,One"
|
|
rbitfld.long 0x00 28. " PKP ,Public Key is Prime" "Not prime,Prime"
|
|
newline
|
|
sif cpuis("MKL82Z*")
|
|
bitfld.long 0x00 24. " DPARRN ,Asserted after POR and after every 50K blocks processed by AESA and DESA" "Not asserted,Asserted"
|
|
newline
|
|
endif
|
|
newline
|
|
rbitfld.long 0x00 20. " EI ,Error Interrupt" "Not error,Error"
|
|
eventfld.long 0x00 16. " DI ,Done Interrupt asserted" "Not asserted,Asserted"
|
|
newline
|
|
sif cpuis("MKL82Z*")
|
|
bitfld.long 0x00 7. " MB ,MDHA Busy" "Idle,Busy"
|
|
newline
|
|
endif
|
|
rbitfld.long 0x00 6. " PB ,PKHA Busy" "Idle,Busy"
|
|
newline
|
|
rbitfld.long 0x00 2. " DB ,DESA Busy" "Idle,Busy"
|
|
rbitfld.long 0x00 1. " AB ,AESA Busy" "Idle,Busy"
|
|
newline
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "LTC0_ESTA,LTC Error Status"
|
|
bitfld.long 0x00 8.--11. " CL1 ,algorithms" "LTC General Error,AES,DES,,,,,,Public Key,?..."
|
|
bitfld.long 0x00 0.--3. " ERRID1 ,Error ID 1" ",Mode,Data size,Key size,PKHA A register size,PKHA B register size,Data arrived out of sequence,PKHA divide by zero,PKHA modulus even,DES key parity,ICV check failed,Internal hardware failure,CCM AAD size,,,Invalid crypto engine selected"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "LTC0_AADSZ,LTC AAD Size"
|
|
bitfld.long 0x00 31. " AL ,AAD Last" "Not last,Last"
|
|
bitfld.long 0x00 0.--3. " AADSZ ,AAD size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (!(cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")))
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "LTC0_IVSZ,LTC IV Size"
|
|
bitfld.long 0x00 31. " IL ,IV Last" "Not last,Last"
|
|
bitfld.long 0x00 0.--3. " IVSZ ,IV size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x68++0x03
|
|
line.long 0x00 "LTC0_DPAMS,LTC DPA Mask Seed"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "LTC0_PKASZ,LTC PKHA A Size"
|
|
hexmask.long.word 0x00 0.--8. 1. " PKASZ ,PKHA A Size"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "LTC0_PKBSZ,LTC PKHA B Size"
|
|
hexmask.long.word 0x00 0.--8. 1. " PKBSZ ,PKHA B Size"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "LTC0_PKNSZ,LTC PKHA N Size"
|
|
hexmask.long.word 0x00 0.--8. 1. " PKNSZ ,PKHA N Size"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "LTC0_PKESZ,LTC PKHA E Size"
|
|
hexmask.long.word 0x00 0.--8. 1. " PKESZ ,PKHA E Size"
|
|
endif
|
|
newline
|
|
width 14.
|
|
sif (!(cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")))
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "LTC0_CTX_0,LTC Context"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "LTC0_CTX_1,LTC Context"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "LTC0_CTX_2,LTC Context"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "LTC0_CTX_3,LTC Context"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "LTC0_CTX_4,LTC Context"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "LTC0_CTX_5,LTC Context"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "LTC0_CTX_6,LTC Context"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "LTC0_CTX_7,LTC Context"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "LTC0_CTX_8,LTC Context"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "LTC0_CTX_9,LTC Context"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "LTC0_CTX_10,LTC Context"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "LTC0_CTX_11,LTC Context"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "LTC0_CTX_12,LTC Context"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "LTC0_CTX_13,LTC Context"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "LTC0_CTX_14,LTC Context"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "LTC0_CTX_15,LTC Context"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "LTC0_CTX_0,LTC Context"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "LTC0_CTX_1,LTC Context"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "LTC0_CTX_2,LTC Context"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "LTC0_CTX_3,LTC Context"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "LTC0_CTX_4,LTC Context"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "LTC0_CTX_5,LTC Context"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "LTC0_CTX_6,LTC Context"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "LTC0_CTX_7,LTC Context"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "LTC0_CTX_8,LTC Context"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "LTC0_CTX_9,LTC Context"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "LTC0_CTX_10,LTC Context"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "LTC0_CTX_11,LTC Context"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "LTC0_CTX_12,LTC Context"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "LTC0_CTX_13,LTC Context"
|
|
endif
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "LTC0_KEY_0,LTC Keys"
|
|
line.long 0x04 "LTC0_KEY_1,LTC Keys"
|
|
line.long 0x08 "LTC0_KEY_2,LTC Keys"
|
|
line.long 0x0C "LTC0_KEY_3,LTC Keys"
|
|
sif (!(cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")))
|
|
line.long 0x10 "LTC0_KEY_4,LTC Keys"
|
|
line.long 0x14 "LTC0_KEY_5,LTC Keys"
|
|
line.long 0x18 "LTC0_KEY_6,LTC Keys"
|
|
line.long 0x1C "LTC0_KEY_7,LTC Keys"
|
|
endif
|
|
sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKL82Z*"))
|
|
rgroup.long 0x4F0++0x07
|
|
line.long 0x00 "LTC0_VID1,LTC Version ID"
|
|
hexmask.long.word 0x00 16.--31. 1. " IP_ID ,ID"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MAJ_REV ,Major revision number"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MIN_REV ,Minor revision number"
|
|
line.long 0x04 "LTC0_VID2,LTC Version ID 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ARCH_ERA ,Architectural ERA"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ECO_REV ,ECO Revision Number"
|
|
endif
|
|
sif (!(cpuis("MKW40Z*")||cpuis("MKW30Z*")||cpuis("MKW20Z*")))
|
|
rgroup.long 0x4F8++0x03
|
|
line.long 0x00 "LTC0_CHAVID,LTC CHA Version ID"
|
|
sif cpuis("MKL82Z*")
|
|
bitfld.long 0x00 28.--31. " MDHAVID , MDHA Hashing Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " MDHAREV ,MDHA Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 20.--23. " PKHAVID ,PK Version ID" "32 bit,64 bit,128 bit,16 bit,?..."
|
|
bitfld.long 0x00 16.--19. " PKHAREV ,PK Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DESVID ,DES Version ID(0x0)" "High-performance,Low-performance,?..."
|
|
bitfld.long 0x00 8.--11. " DESREV ,DES Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " AESVID ,AES Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " AESREV ,AES Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
rgroup.long 0x7C0++0x03
|
|
line.long 0x00 "LTC0_FIFOSTA,LTC FIFO Status"
|
|
bitfld.long 0x00 31. " OFF ,Output FIFO Full" "Not Full,Full"
|
|
hexmask.long.byte 0x00 16.--22. 1. " OFL ,Output FIFO Level"
|
|
bitfld.long 0x00 15. " IFF ,Input FIFO Full" "Not full,Full"
|
|
hexmask.long.byte 0x00 0.--6. 1. " IFL ,Input FIFO Level"
|
|
wgroup.long 0x7E0++0x03
|
|
line.long 0x00 "LTC0_IFIFO,LTC Input Data FIFO"
|
|
rgroup.long 0x7F0++0x03
|
|
line.long 0x00 "LTC0_OFIFO,LTC Output Data FIFO"
|
|
sif (!(cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")))
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "LTC0_PKA0_0,LTC PKHA A0"
|
|
group.long 0x804++0x03
|
|
line.long 0x00 "LTC0_PKA0_1,LTC PKHA A0"
|
|
group.long 0x808++0x03
|
|
line.long 0x00 "LTC0_PKA0_2,LTC PKHA A0"
|
|
group.long 0x80C++0x03
|
|
line.long 0x00 "LTC0_PKA0_3,LTC PKHA A0"
|
|
group.long 0x810++0x03
|
|
line.long 0x00 "LTC0_PKA0_4,LTC PKHA A0"
|
|
group.long 0x814++0x03
|
|
line.long 0x00 "LTC0_PKA0_5,LTC PKHA A0"
|
|
group.long 0x818++0x03
|
|
line.long 0x00 "LTC0_PKA0_6,LTC PKHA A0"
|
|
group.long 0x81C++0x03
|
|
line.long 0x00 "LTC0_PKA0_7,LTC PKHA A0"
|
|
group.long 0x820++0x03
|
|
line.long 0x00 "LTC0_PKA0_8,LTC PKHA A0"
|
|
group.long 0x824++0x03
|
|
line.long 0x00 "LTC0_PKA0_9,LTC PKHA A0"
|
|
group.long 0x828++0x03
|
|
line.long 0x00 "LTC0_PKA0_10,LTC PKHA A0"
|
|
group.long 0x82C++0x03
|
|
line.long 0x00 "LTC0_PKA0_11,LTC PKHA A0"
|
|
group.long 0x830++0x03
|
|
line.long 0x00 "LTC0_PKA0_12,LTC PKHA A0"
|
|
group.long 0x834++0x03
|
|
line.long 0x00 "LTC0_PKA0_13,LTC PKHA A0"
|
|
group.long 0x838++0x03
|
|
line.long 0x00 "LTC0_PKA0_14,LTC PKHA A0"
|
|
group.long 0x83C++0x03
|
|
line.long 0x00 "LTC0_PKA0_15,LTC PKHA A0"
|
|
group.long 0x840++0x03
|
|
line.long 0x00 "LTC0_PKA1_0,LTC PKHA A1"
|
|
group.long 0x844++0x03
|
|
line.long 0x00 "LTC0_PKA1_1,LTC PKHA A1"
|
|
group.long 0x848++0x03
|
|
line.long 0x00 "LTC0_PKA1_2,LTC PKHA A1"
|
|
group.long 0x84C++0x03
|
|
line.long 0x00 "LTC0_PKA1_3,LTC PKHA A1"
|
|
group.long 0x850++0x03
|
|
line.long 0x00 "LTC0_PKA1_4,LTC PKHA A1"
|
|
group.long 0x854++0x03
|
|
line.long 0x00 "LTC0_PKA1_5,LTC PKHA A1"
|
|
group.long 0x858++0x03
|
|
line.long 0x00 "LTC0_PKA1_6,LTC PKHA A1"
|
|
group.long 0x85C++0x03
|
|
line.long 0x00 "LTC0_PKA1_7,LTC PKHA A1"
|
|
group.long 0x860++0x03
|
|
line.long 0x00 "LTC0_PKA1_8,LTC PKHA A1"
|
|
group.long 0x864++0x03
|
|
line.long 0x00 "LTC0_PKA1_9,LTC PKHA A1"
|
|
group.long 0x868++0x03
|
|
line.long 0x00 "LTC0_PKA1_10,LTC PKHA A1"
|
|
group.long 0x86C++0x03
|
|
line.long 0x00 "LTC0_PKA1_11,LTC PKHA A1"
|
|
group.long 0x870++0x03
|
|
line.long 0x00 "LTC0_PKA1_12,LTC PKHA A1"
|
|
group.long 0x874++0x03
|
|
line.long 0x00 "LTC0_PKA1_13,LTC PKHA A1"
|
|
group.long 0x878++0x03
|
|
line.long 0x00 "LTC0_PKA1_14,LTC PKHA A1"
|
|
group.long 0x87C++0x03
|
|
line.long 0x00 "LTC0_PKA1_15,LTC PKHA A1"
|
|
group.long 0x880++0x03
|
|
line.long 0x00 "LTC0_PKA2_0,LTC PKHA A2"
|
|
group.long 0x884++0x03
|
|
line.long 0x00 "LTC0_PKA2_1,LTC PKHA A2"
|
|
group.long 0x888++0x03
|
|
line.long 0x00 "LTC0_PKA2_2,LTC PKHA A2"
|
|
group.long 0x88C++0x03
|
|
line.long 0x00 "LTC0_PKA2_3,LTC PKHA A2"
|
|
group.long 0x890++0x03
|
|
line.long 0x00 "LTC0_PKA2_4,LTC PKHA A2"
|
|
group.long 0x894++0x03
|
|
line.long 0x00 "LTC0_PKA2_5,LTC PKHA A2"
|
|
group.long 0x898++0x03
|
|
line.long 0x00 "LTC0_PKA2_6,LTC PKHA A2"
|
|
group.long 0x89C++0x03
|
|
line.long 0x00 "LTC0_PKA2_7,LTC PKHA A2"
|
|
group.long 0x8A0++0x03
|
|
line.long 0x00 "LTC0_PKA2_8,LTC PKHA A2"
|
|
group.long 0x8A4++0x03
|
|
line.long 0x00 "LTC0_PKA2_9,LTC PKHA A2"
|
|
group.long 0x8A8++0x03
|
|
line.long 0x00 "LTC0_PKA2_10,LTC PKHA A2"
|
|
group.long 0x8AC++0x03
|
|
line.long 0x00 "LTC0_PKA2_11,LTC PKHA A2"
|
|
group.long 0x8B0++0x03
|
|
line.long 0x00 "LTC0_PKA2_12,LTC PKHA A2"
|
|
group.long 0x8B4++0x03
|
|
line.long 0x00 "LTC0_PKA2_13,LTC PKHA A2"
|
|
group.long 0x8B8++0x03
|
|
line.long 0x00 "LTC0_PKA2_14,LTC PKHA A2"
|
|
group.long 0x8BC++0x03
|
|
line.long 0x00 "LTC0_PKA2_15,LTC PKHA A2"
|
|
group.long 0x8C0++0x03
|
|
line.long 0x00 "LTC0_PKA3_0,LTC PKHA A3"
|
|
group.long 0x8C4++0x03
|
|
line.long 0x00 "LTC0_PKA3_1,LTC PKHA A3"
|
|
group.long 0x8C8++0x03
|
|
line.long 0x00 "LTC0_PKA3_2,LTC PKHA A3"
|
|
group.long 0x8CC++0x03
|
|
line.long 0x00 "LTC0_PKA3_3,LTC PKHA A3"
|
|
group.long 0x8D0++0x03
|
|
line.long 0x00 "LTC0_PKA3_4,LTC PKHA A3"
|
|
group.long 0x8D4++0x03
|
|
line.long 0x00 "LTC0_PKA3_5,LTC PKHA A3"
|
|
group.long 0x8D8++0x03
|
|
line.long 0x00 "LTC0_PKA3_6,LTC PKHA A3"
|
|
group.long 0x8DC++0x03
|
|
line.long 0x00 "LTC0_PKA3_7,LTC PKHA A3"
|
|
group.long 0x8E0++0x03
|
|
line.long 0x00 "LTC0_PKA3_8,LTC PKHA A3"
|
|
group.long 0x8E4++0x03
|
|
line.long 0x00 "LTC0_PKA3_9,LTC PKHA A3"
|
|
group.long 0x8E8++0x03
|
|
line.long 0x00 "LTC0_PKA3_10,LTC PKHA A3"
|
|
group.long 0x8EC++0x03
|
|
line.long 0x00 "LTC0_PKA3_11,LTC PKHA A3"
|
|
group.long 0x8F0++0x03
|
|
line.long 0x00 "LTC0_PKA3_12,LTC PKHA A3"
|
|
group.long 0x8F4++0x03
|
|
line.long 0x00 "LTC0_PKA3_13,LTC PKHA A3"
|
|
group.long 0x8F8++0x03
|
|
line.long 0x00 "LTC0_PKA3_14,LTC PKHA A3"
|
|
group.long 0x8FC++0x03
|
|
line.long 0x00 "LTC0_PKA3_15,LTC PKHA A3"
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 "LTC0_PKB0_0,LTC PKHA B0"
|
|
group.long 0xA04++0x03
|
|
line.long 0x00 "LTC0_PKB0_1,LTC PKHA B0"
|
|
group.long 0xA08++0x03
|
|
line.long 0x00 "LTC0_PKB0_2,LTC PKHA B0"
|
|
group.long 0xA0C++0x03
|
|
line.long 0x00 "LTC0_PKB0_3,LTC PKHA B0"
|
|
group.long 0xA10++0x03
|
|
line.long 0x00 "LTC0_PKB0_4,LTC PKHA B0"
|
|
group.long 0xA14++0x03
|
|
line.long 0x00 "LTC0_PKB0_5,LTC PKHA B0"
|
|
group.long 0xA18++0x03
|
|
line.long 0x00 "LTC0_PKB0_6,LTC PKHA B0"
|
|
group.long 0xA1C++0x03
|
|
line.long 0x00 "LTC0_PKB0_7,LTC PKHA B0"
|
|
group.long 0xA20++0x03
|
|
line.long 0x00 "LTC0_PKB0_8,LTC PKHA B0"
|
|
group.long 0xA24++0x03
|
|
line.long 0x00 "LTC0_PKB0_9,LTC PKHA B0"
|
|
group.long 0xA28++0x03
|
|
line.long 0x00 "LTC0_PKB0_10,LTC PKHA B0"
|
|
group.long 0xA2C++0x03
|
|
line.long 0x00 "LTC0_PKB0_11,LTC PKHA B0"
|
|
group.long 0xA30++0x03
|
|
line.long 0x00 "LTC0_PKB0_12,LTC PKHA B0"
|
|
group.long 0xA34++0x03
|
|
line.long 0x00 "LTC0_PKB0_13,LTC PKHA B0"
|
|
group.long 0xA38++0x03
|
|
line.long 0x00 "LTC0_PKB0_14,LTC PKHA B0"
|
|
group.long 0xA3C++0x03
|
|
line.long 0x00 "LTC0_PKB0_15,LTC PKHA B0"
|
|
group.long 0xA40++0x03
|
|
line.long 0x00 "LTC0_PKB1_0,LTC PKHA B1"
|
|
group.long 0xA44++0x03
|
|
line.long 0x00 "LTC0_PKB1_1,LTC PKHA B1"
|
|
group.long 0xA48++0x03
|
|
line.long 0x00 "LTC0_PKB1_2,LTC PKHA B1"
|
|
group.long 0xA4C++0x03
|
|
line.long 0x00 "LTC0_PKB1_3,LTC PKHA B1"
|
|
group.long 0xA50++0x03
|
|
line.long 0x00 "LTC0_PKB1_4,LTC PKHA B1"
|
|
group.long 0xA54++0x03
|
|
line.long 0x00 "LTC0_PKB1_5,LTC PKHA B1"
|
|
group.long 0xA58++0x03
|
|
line.long 0x00 "LTC0_PKB1_6,LTC PKHA B1"
|
|
group.long 0xA5C++0x03
|
|
line.long 0x00 "LTC0_PKB1_7,LTC PKHA B1"
|
|
group.long 0xA60++0x03
|
|
line.long 0x00 "LTC0_PKB1_8,LTC PKHA B1"
|
|
group.long 0xA64++0x03
|
|
line.long 0x00 "LTC0_PKB1_9,LTC PKHA B1"
|
|
group.long 0xA68++0x03
|
|
line.long 0x00 "LTC0_PKB1_10,LTC PKHA B1"
|
|
group.long 0xA6C++0x03
|
|
line.long 0x00 "LTC0_PKB1_11,LTC PKHA B1"
|
|
group.long 0xA70++0x03
|
|
line.long 0x00 "LTC0_PKB1_12,LTC PKHA B1"
|
|
group.long 0xA74++0x03
|
|
line.long 0x00 "LTC0_PKB1_13,LTC PKHA B1"
|
|
group.long 0xA78++0x03
|
|
line.long 0x00 "LTC0_PKB1_14,LTC PKHA B1"
|
|
group.long 0xA7C++0x03
|
|
line.long 0x00 "LTC0_PKB1_15,LTC PKHA B1"
|
|
group.long 0xA80++0x03
|
|
line.long 0x00 "LTC0_PKB2_0,LTC PKHA B2"
|
|
group.long 0xA84++0x03
|
|
line.long 0x00 "LTC0_PKB2_1,LTC PKHA B2"
|
|
group.long 0xA88++0x03
|
|
line.long 0x00 "LTC0_PKB2_2,LTC PKHA B2"
|
|
group.long 0xA8C++0x03
|
|
line.long 0x00 "LTC0_PKB2_3,LTC PKHA B2"
|
|
group.long 0xA90++0x03
|
|
line.long 0x00 "LTC0_PKB2_4,LTC PKHA B2"
|
|
group.long 0xA94++0x03
|
|
line.long 0x00 "LTC0_PKB2_5,LTC PKHA B2"
|
|
group.long 0xA98++0x03
|
|
line.long 0x00 "LTC0_PKB2_6,LTC PKHA B2"
|
|
group.long 0xA9C++0x03
|
|
line.long 0x00 "LTC0_PKB2_7,LTC PKHA B2"
|
|
group.long 0xAA0++0x03
|
|
line.long 0x00 "LTC0_PKB2_8,LTC PKHA B2"
|
|
group.long 0xAA4++0x03
|
|
line.long 0x00 "LTC0_PKB2_9,LTC PKHA B2"
|
|
group.long 0xAA8++0x03
|
|
line.long 0x00 "LTC0_PKB2_10,LTC PKHA B2"
|
|
group.long 0xAAC++0x03
|
|
line.long 0x00 "LTC0_PKB2_11,LTC PKHA B2"
|
|
group.long 0xAB0++0x03
|
|
line.long 0x00 "LTC0_PKB2_12,LTC PKHA B2"
|
|
group.long 0xAB4++0x03
|
|
line.long 0x00 "LTC0_PKB2_13,LTC PKHA B2"
|
|
group.long 0xAB8++0x03
|
|
line.long 0x00 "LTC0_PKB2_14,LTC PKHA B2"
|
|
group.long 0xABC++0x03
|
|
line.long 0x00 "LTC0_PKB2_15,LTC PKHA B2"
|
|
group.long 0xAC0++0x03
|
|
line.long 0x00 "LTC0_PKB3_0,LTC PKHA B3"
|
|
group.long 0xAC4++0x03
|
|
line.long 0x00 "LTC0_PKB3_1,LTC PKHA B3"
|
|
group.long 0xAC8++0x03
|
|
line.long 0x00 "LTC0_PKB3_2,LTC PKHA B3"
|
|
group.long 0xACC++0x03
|
|
line.long 0x00 "LTC0_PKB3_3,LTC PKHA B3"
|
|
group.long 0xAD0++0x03
|
|
line.long 0x00 "LTC0_PKB3_4,LTC PKHA B3"
|
|
group.long 0xAD4++0x03
|
|
line.long 0x00 "LTC0_PKB3_5,LTC PKHA B3"
|
|
group.long 0xAD8++0x03
|
|
line.long 0x00 "LTC0_PKB3_6,LTC PKHA B3"
|
|
group.long 0xADC++0x03
|
|
line.long 0x00 "LTC0_PKB3_7,LTC PKHA B3"
|
|
group.long 0xAE0++0x03
|
|
line.long 0x00 "LTC0_PKB3_8,LTC PKHA B3"
|
|
group.long 0xAE4++0x03
|
|
line.long 0x00 "LTC0_PKB3_9,LTC PKHA B3"
|
|
group.long 0xAE8++0x03
|
|
line.long 0x00 "LTC0_PKB3_10,LTC PKHA B3"
|
|
group.long 0xAEC++0x03
|
|
line.long 0x00 "LTC0_PKB3_11,LTC PKHA B3"
|
|
group.long 0xAF0++0x03
|
|
line.long 0x00 "LTC0_PKB3_12,LTC PKHA B3"
|
|
group.long 0xAF4++0x03
|
|
line.long 0x00 "LTC0_PKB3_13,LTC PKHA B3"
|
|
group.long 0xAF8++0x03
|
|
line.long 0x00 "LTC0_PKB3_14,LTC PKHA B3"
|
|
group.long 0xAFC++0x03
|
|
line.long 0x00 "LTC0_PKB3_15,LTC PKHA B3"
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "LTC0_PKN0_0,LTC PKHA N0"
|
|
group.long 0xC04++0x03
|
|
line.long 0x00 "LTC0_PKN0_1,LTC PKHA N0"
|
|
group.long 0xC08++0x03
|
|
line.long 0x00 "LTC0_PKN0_2,LTC PKHA N0"
|
|
group.long 0xC0C++0x03
|
|
line.long 0x00 "LTC0_PKN0_3,LTC PKHA N0"
|
|
group.long 0xC10++0x03
|
|
line.long 0x00 "LTC0_PKN0_4,LTC PKHA N0"
|
|
group.long 0xC14++0x03
|
|
line.long 0x00 "LTC0_PKN0_5,LTC PKHA N0"
|
|
group.long 0xC18++0x03
|
|
line.long 0x00 "LTC0_PKN0_6,LTC PKHA N0"
|
|
group.long 0xC1C++0x03
|
|
line.long 0x00 "LTC0_PKN0_7,LTC PKHA N0"
|
|
group.long 0xC20++0x03
|
|
line.long 0x00 "LTC0_PKN0_8,LTC PKHA N0"
|
|
group.long 0xC24++0x03
|
|
line.long 0x00 "LTC0_PKN0_9,LTC PKHA N0"
|
|
group.long 0xC28++0x03
|
|
line.long 0x00 "LTC0_PKN0_10,LTC PKHA N0"
|
|
group.long 0xC2C++0x03
|
|
line.long 0x00 "LTC0_PKN0_11,LTC PKHA N0"
|
|
group.long 0xC30++0x03
|
|
line.long 0x00 "LTC0_PKN0_12,LTC PKHA N0"
|
|
group.long 0xC34++0x03
|
|
line.long 0x00 "LTC0_PKN0_13,LTC PKHA N0"
|
|
group.long 0xC38++0x03
|
|
line.long 0x00 "LTC0_PKN0_14,LTC PKHA N0"
|
|
group.long 0xC3C++0x03
|
|
line.long 0x00 "LTC0_PKN0_15,LTC PKHA N0"
|
|
group.long 0xC40++0x03
|
|
line.long 0x00 "LTC0_PKN1_0,LTC PKHA N1"
|
|
group.long 0xC44++0x03
|
|
line.long 0x00 "LTC0_PKN1_1,LTC PKHA N1"
|
|
group.long 0xC48++0x03
|
|
line.long 0x00 "LTC0_PKN1_2,LTC PKHA N1"
|
|
group.long 0xC4C++0x03
|
|
line.long 0x00 "LTC0_PKN1_3,LTC PKHA N1"
|
|
group.long 0xC50++0x03
|
|
line.long 0x00 "LTC0_PKN1_4,LTC PKHA N1"
|
|
group.long 0xC54++0x03
|
|
line.long 0x00 "LTC0_PKN1_5,LTC PKHA N1"
|
|
group.long 0xC58++0x03
|
|
line.long 0x00 "LTC0_PKN1_6,LTC PKHA N1"
|
|
group.long 0xC5C++0x03
|
|
line.long 0x00 "LTC0_PKN1_7,LTC PKHA N1"
|
|
group.long 0xC60++0x03
|
|
line.long 0x00 "LTC0_PKN1_8,LTC PKHA N1"
|
|
group.long 0xC64++0x03
|
|
line.long 0x00 "LTC0_PKN1_9,LTC PKHA N1"
|
|
group.long 0xC68++0x03
|
|
line.long 0x00 "LTC0_PKN1_10,LTC PKHA N1"
|
|
group.long 0xC6C++0x03
|
|
line.long 0x00 "LTC0_PKN1_11,LTC PKHA N1"
|
|
group.long 0xC70++0x03
|
|
line.long 0x00 "LTC0_PKN1_12,LTC PKHA N1"
|
|
group.long 0xC74++0x03
|
|
line.long 0x00 "LTC0_PKN1_13,LTC PKHA N1"
|
|
group.long 0xC78++0x03
|
|
line.long 0x00 "LTC0_PKN1_14,LTC PKHA N1"
|
|
group.long 0xC7C++0x03
|
|
line.long 0x00 "LTC0_PKN1_15,LTC PKHA N1"
|
|
group.long 0xC80++0x03
|
|
line.long 0x00 "LTC0_PKN2_0,LTC PKHA N2"
|
|
group.long 0xC84++0x03
|
|
line.long 0x00 "LTC0_PKN2_1,LTC PKHA N2"
|
|
group.long 0xC88++0x03
|
|
line.long 0x00 "LTC0_PKN2_2,LTC PKHA N2"
|
|
group.long 0xC8C++0x03
|
|
line.long 0x00 "LTC0_PKN2_3,LTC PKHA N2"
|
|
group.long 0xC90++0x03
|
|
line.long 0x00 "LTC0_PKN2_4,LTC PKHA N2"
|
|
group.long 0xC94++0x03
|
|
line.long 0x00 "LTC0_PKN2_5,LTC PKHA N2"
|
|
group.long 0xC98++0x03
|
|
line.long 0x00 "LTC0_PKN2_6,LTC PKHA N2"
|
|
group.long 0xC9C++0x03
|
|
line.long 0x00 "LTC0_PKN2_7,LTC PKHA N2"
|
|
group.long 0xCA0++0x03
|
|
line.long 0x00 "LTC0_PKN2_8,LTC PKHA N2"
|
|
group.long 0xCA4++0x03
|
|
line.long 0x00 "LTC0_PKN2_9,LTC PKHA N2"
|
|
group.long 0xCA8++0x03
|
|
line.long 0x00 "LTC0_PKN2_10,LTC PKHA N2"
|
|
group.long 0xCAC++0x03
|
|
line.long 0x00 "LTC0_PKN2_11,LTC PKHA N2"
|
|
group.long 0xCB0++0x03
|
|
line.long 0x00 "LTC0_PKN2_12,LTC PKHA N2"
|
|
group.long 0xCB4++0x03
|
|
line.long 0x00 "LTC0_PKN2_13,LTC PKHA N2"
|
|
group.long 0xCB8++0x03
|
|
line.long 0x00 "LTC0_PKN2_14,LTC PKHA N2"
|
|
group.long 0xCBC++0x03
|
|
line.long 0x00 "LTC0_PKN2_15,LTC PKHA N2"
|
|
group.long 0xCC0++0x03
|
|
line.long 0x00 "LTC0_PKN3_0,LTC PKHA N3"
|
|
group.long 0xCC4++0x03
|
|
line.long 0x00 "LTC0_PKN3_1,LTC PKHA N3"
|
|
group.long 0xCC8++0x03
|
|
line.long 0x00 "LTC0_PKN3_2,LTC PKHA N3"
|
|
group.long 0xCCC++0x03
|
|
line.long 0x00 "LTC0_PKN3_3,LTC PKHA N3"
|
|
group.long 0xCD0++0x03
|
|
line.long 0x00 "LTC0_PKN3_4,LTC PKHA N3"
|
|
group.long 0xCD4++0x03
|
|
line.long 0x00 "LTC0_PKN3_5,LTC PKHA N3"
|
|
group.long 0xCD8++0x03
|
|
line.long 0x00 "LTC0_PKN3_6,LTC PKHA N3"
|
|
group.long 0xCDC++0x03
|
|
line.long 0x00 "LTC0_PKN3_7,LTC PKHA N3"
|
|
group.long 0xCE0++0x03
|
|
line.long 0x00 "LTC0_PKN3_8,LTC PKHA N3"
|
|
group.long 0xCE4++0x03
|
|
line.long 0x00 "LTC0_PKN3_9,LTC PKHA N3"
|
|
group.long 0xCE8++0x03
|
|
line.long 0x00 "LTC0_PKN3_10,LTC PKHA N3"
|
|
group.long 0xCEC++0x03
|
|
line.long 0x00 "LTC0_PKN3_11,LTC PKHA N3"
|
|
group.long 0xCF0++0x03
|
|
line.long 0x00 "LTC0_PKN3_12,LTC PKHA N3"
|
|
group.long 0xCF4++0x03
|
|
line.long 0x00 "LTC0_PKN3_13,LTC PKHA N3"
|
|
group.long 0xCF8++0x03
|
|
line.long 0x00 "LTC0_PKN3_14,LTC PKHA N3"
|
|
group.long 0xCFC++0x03
|
|
line.long 0x00 "LTC0_PKN3_15,LTC PKHA N3"
|
|
wgroup.long 0xE00++0x03
|
|
line.long 0x00 "LTC0_PKE_0,LTC PKHA E"
|
|
wgroup.long 0xE04++0x03
|
|
line.long 0x00 "LTC0_PKE_1,LTC PKHA E"
|
|
wgroup.long 0xE08++0x03
|
|
line.long 0x00 "LTC0_PKE_2,LTC PKHA E"
|
|
wgroup.long 0xE0C++0x03
|
|
line.long 0x00 "LTC0_PKE_3,LTC PKHA E"
|
|
wgroup.long 0xE10++0x03
|
|
line.long 0x00 "LTC0_PKE_4,LTC PKHA E"
|
|
wgroup.long 0xE14++0x03
|
|
line.long 0x00 "LTC0_PKE_5,LTC PKHA E"
|
|
wgroup.long 0xE18++0x03
|
|
line.long 0x00 "LTC0_PKE_6,LTC PKHA E"
|
|
wgroup.long 0xE1C++0x03
|
|
line.long 0x00 "LTC0_PKE_7,LTC PKHA E"
|
|
wgroup.long 0xE20++0x03
|
|
line.long 0x00 "LTC0_PKE_8,LTC PKHA E"
|
|
wgroup.long 0xE24++0x03
|
|
line.long 0x00 "LTC0_PKE_9,LTC PKHA E"
|
|
wgroup.long 0xE28++0x03
|
|
line.long 0x00 "LTC0_PKE_10,LTC PKHA E"
|
|
wgroup.long 0xE2C++0x03
|
|
line.long 0x00 "LTC0_PKE_11,LTC PKHA E"
|
|
wgroup.long 0xE30++0x03
|
|
line.long 0x00 "LTC0_PKE_12,LTC PKHA E"
|
|
wgroup.long 0xE34++0x03
|
|
line.long 0x00 "LTC0_PKE_13,LTC PKHA E"
|
|
wgroup.long 0xE38++0x03
|
|
line.long 0x00 "LTC0_PKE_14,LTC PKHA E"
|
|
wgroup.long 0xE3C++0x03
|
|
line.long 0x00 "LTC0_PKE_15,LTC PKHA E"
|
|
wgroup.long 0xE40++0x03
|
|
line.long 0x00 "LTC0_PKE_16,LTC PKHA E"
|
|
wgroup.long 0xE44++0x03
|
|
line.long 0x00 "LTC0_PKE_17,LTC PKHA E"
|
|
wgroup.long 0xE48++0x03
|
|
line.long 0x00 "LTC0_PKE_18,LTC PKHA E"
|
|
wgroup.long 0xE4C++0x03
|
|
line.long 0x00 "LTC0_PKE_19,LTC PKHA E"
|
|
wgroup.long 0xE50++0x03
|
|
line.long 0x00 "LTC0_PKE_20,LTC PKHA E"
|
|
wgroup.long 0xE54++0x03
|
|
line.long 0x00 "LTC0_PKE_21,LTC PKHA E"
|
|
wgroup.long 0xE58++0x03
|
|
line.long 0x00 "LTC0_PKE_22,LTC PKHA E"
|
|
wgroup.long 0xE5C++0x03
|
|
line.long 0x00 "LTC0_PKE_23,LTC PKHA E"
|
|
wgroup.long 0xE60++0x03
|
|
line.long 0x00 "LTC0_PKE_24,LTC PKHA E"
|
|
wgroup.long 0xE64++0x03
|
|
line.long 0x00 "LTC0_PKE_25,LTC PKHA E"
|
|
wgroup.long 0xE68++0x03
|
|
line.long 0x00 "LTC0_PKE_26,LTC PKHA E"
|
|
wgroup.long 0xE6C++0x03
|
|
line.long 0x00 "LTC0_PKE_27,LTC PKHA E"
|
|
wgroup.long 0xE70++0x03
|
|
line.long 0x00 "LTC0_PKE_28,LTC PKHA E"
|
|
wgroup.long 0xE74++0x03
|
|
line.long 0x00 "LTC0_PKE_29,LTC PKHA E"
|
|
wgroup.long 0xE78++0x03
|
|
line.long 0x00 "LTC0_PKE_30,LTC PKHA E"
|
|
wgroup.long 0xE7C++0x03
|
|
line.long 0x00 "LTC0_PKE_31,LTC PKHA E"
|
|
wgroup.long 0xE80++0x03
|
|
line.long 0x00 "LTC0_PKE_32,LTC PKHA E"
|
|
wgroup.long 0xE84++0x03
|
|
line.long 0x00 "LTC0_PKE_33,LTC PKHA E"
|
|
wgroup.long 0xE88++0x03
|
|
line.long 0x00 "LTC0_PKE_34,LTC PKHA E"
|
|
wgroup.long 0xE8C++0x03
|
|
line.long 0x00 "LTC0_PKE_35,LTC PKHA E"
|
|
wgroup.long 0xE90++0x03
|
|
line.long 0x00 "LTC0_PKE_36,LTC PKHA E"
|
|
wgroup.long 0xE94++0x03
|
|
line.long 0x00 "LTC0_PKE_37,LTC PKHA E"
|
|
wgroup.long 0xE98++0x03
|
|
line.long 0x00 "LTC0_PKE_38,LTC PKHA E"
|
|
wgroup.long 0xE9C++0x03
|
|
line.long 0x00 "LTC0_PKE_39,LTC PKHA E"
|
|
wgroup.long 0xEA0++0x03
|
|
line.long 0x00 "LTC0_PKE_40,LTC PKHA E"
|
|
wgroup.long 0xEA4++0x03
|
|
line.long 0x00 "LTC0_PKE_41,LTC PKHA E"
|
|
wgroup.long 0xEA8++0x03
|
|
line.long 0x00 "LTC0_PKE_42,LTC PKHA E"
|
|
wgroup.long 0xEAC++0x03
|
|
line.long 0x00 "LTC0_PKE_43,LTC PKHA E"
|
|
wgroup.long 0xEB0++0x03
|
|
line.long 0x00 "LTC0_PKE_44,LTC PKHA E"
|
|
wgroup.long 0xEB4++0x03
|
|
line.long 0x00 "LTC0_PKE_45,LTC PKHA E"
|
|
wgroup.long 0xEB8++0x03
|
|
line.long 0x00 "LTC0_PKE_46,LTC PKHA E"
|
|
wgroup.long 0xEBC++0x03
|
|
line.long 0x00 "LTC0_PKE_47,LTC PKHA E"
|
|
wgroup.long 0xEC0++0x03
|
|
line.long 0x00 "LTC0_PKE_48,LTC PKHA E"
|
|
wgroup.long 0xEC4++0x03
|
|
line.long 0x00 "LTC0_PKE_49,LTC PKHA E"
|
|
wgroup.long 0xEC8++0x03
|
|
line.long 0x00 "LTC0_PKE_50,LTC PKHA E"
|
|
wgroup.long 0xECC++0x03
|
|
line.long 0x00 "LTC0_PKE_51,LTC PKHA E"
|
|
wgroup.long 0xED0++0x03
|
|
line.long 0x00 "LTC0_PKE_52,LTC PKHA E"
|
|
wgroup.long 0xED4++0x03
|
|
line.long 0x00 "LTC0_PKE_53,LTC PKHA E"
|
|
wgroup.long 0xED8++0x03
|
|
line.long 0x00 "LTC0_PKE_54,LTC PKHA E"
|
|
wgroup.long 0xEDC++0x03
|
|
line.long 0x00 "LTC0_PKE_55,LTC PKHA E"
|
|
wgroup.long 0xEE0++0x03
|
|
line.long 0x00 "LTC0_PKE_56,LTC PKHA E"
|
|
wgroup.long 0xEE4++0x03
|
|
line.long 0x00 "LTC0_PKE_57,LTC PKHA E"
|
|
wgroup.long 0xEE8++0x03
|
|
line.long 0x00 "LTC0_PKE_58,LTC PKHA E"
|
|
wgroup.long 0xEEC++0x03
|
|
line.long 0x00 "LTC0_PKE_59,LTC PKHA E"
|
|
wgroup.long 0xEF0++0x03
|
|
line.long 0x00 "LTC0_PKE_60,LTC PKHA E"
|
|
wgroup.long 0xEF4++0x03
|
|
line.long 0x00 "LTC0_PKE_61,LTC PKHA E"
|
|
wgroup.long 0xEF8++0x03
|
|
line.long 0x00 "LTC0_PKE_62,LTC PKHA E"
|
|
wgroup.long 0xEFC++0x03
|
|
line.long 0x00 "LTC0_PKE_63,LTC PKHA E"
|
|
elif (cpuis("MKW40Z*")||cpuis("MKW30Z*")||cpuis("MKW20Z*"))
|
|
rgroup.long 0x8F0++0x03
|
|
line.long 0x00 "LTC0_VID1,LTC Version ID"
|
|
hexmask.long.word 0x00 16.--31. 1. " IP_ID ,ID"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MAJ_REV ,Major revision number"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MIN_REV ,Minor revision number"
|
|
rgroup.long 0x8F8++0x03
|
|
line.long 0x00 "LTC0_CHAVID,LTC CHA Version ID"
|
|
bitfld.long 0x00 4.--7. " AESVID ,AES Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " AESREV ,AES Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif !cpuis("MKL02*")
|
|
tree "RTC (Real Time Clock)"
|
|
sif cpuis("MKL28Z*")
|
|
base ad:0x40038000
|
|
width 5.
|
|
if (((per.l(ad:0x40038000+0x14))&0x10)==0x00)
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "TSR,RTC Time Seconds Register"
|
|
line.long 0x04 "TPR,RTC Time Prescaler Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TPR ,Time prescaler"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "TSR,RTC Time Seconds Register"
|
|
line.long 0x04 "TPR,RTC Time Prescaler Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TPR ,Time prescaler"
|
|
endif
|
|
group.long 0x08++0x17
|
|
line.long 0x00 "TAR,RTC Time Alarm Register"
|
|
line.long 0x04 "TCR,RTC Time Compensation Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " CIC ,Compensation interval counter"
|
|
hexmask.long.byte 0x04 16.--23. 1. " TCV ,Time compensation value"
|
|
hexmask.long.byte 0x04 8.--15. 1. " CIR ,Compensation interval register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TCR ,Time compensation register"
|
|
line.long 0x08 "CR,RTC Control Register"
|
|
bitfld.long 0x08 13. " SC2P ,Oscillator 2pF load configure" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " SC4P ,Oscillator 4pF load configure" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " SC8P ,Oscillator 8pF load configure" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " SC16P ,Oscillator 16pF load configure" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 9. " CLKO ,Indicate whether clock is output to other peripherals or not" "Output,Not output"
|
|
bitfld.long 0x08 8. " OSCE ,Oscillator enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("MKL28*")
|
|
bitfld.long 0x08 7. " LPOS ,LPO select" "32kHz,1kHz LPO"
|
|
bitfld.long 0x08 5. " CPS ,Clock pin select" "0,1"
|
|
newline
|
|
endif
|
|
sif !cpuis("MKL05*")
|
|
bitfld.long 0x08 4. " WPS ,Wakeup pin select" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x08 3. " UM ,Update mode" "Low,High"
|
|
newline
|
|
bitfld.long 0x08 2. " SUP ,Supervisor write access" "Supervisor,Non-supervisor"
|
|
bitfld.long 0x08 1. " WPE ,Wakeup pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " SWR ,Software reset" "No reset,Reset"
|
|
line.long 0x0C "SR,RTC Status Register"
|
|
bitfld.long 0x0C 4. " TCE ,Time counter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x0C 2. " TAF ,Time alarm flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x0C 1. " TOF ,Time overflow flag" "No overflow,Overflow"
|
|
rbitfld.long 0x0C 0. " TIF ,Time invalid flag" "Valid,Invalid"
|
|
line.long 0x10 "LR,RTC Lock Register"
|
|
bitfld.long 0x10 6. " LRL ,Lock register lock" "Locked,Not locked"
|
|
bitfld.long 0x10 5. " SRL ,Status register lock" "Locked,Not locked"
|
|
bitfld.long 0x10 4. " CRL ,Control register lock" "Locked,Not locked"
|
|
bitfld.long 0x10 3. " TCL ,Time compensation lock" "Locked,Not locked"
|
|
line.long 0x14 "IER,RTC Interrupt Enable Register"
|
|
bitfld.long 0x14 7. " WPON ,Wakeup pin on" "No effect,Wake up"
|
|
bitfld.long 0x14 4. " TSIE ,Time seconds interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " TAIE ,Time alarm interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " TOIE ,Time overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 0. " TIIE ,Time invalid interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("MKL82Z*")
|
|
group.long 0x800++0x07
|
|
line.long 0x00 "WAR,RTC Write Access Register"
|
|
bitfld.long 0x00 7. " IERW ,Interrupt enable register write" "Ignored,Normal"
|
|
bitfld.long 0x00 6. " LRW ,Lock register write" "Ignored,Normal"
|
|
bitfld.long 0x00 5. " SRW ,Status register write" "Ignored,Normal"
|
|
bitfld.long 0x00 4. " CRW ,Control register write" "Ignored,Normal"
|
|
newline
|
|
bitfld.long 0x00 3. " TCRW ,Time compensation register write" "Ignored,Normal"
|
|
bitfld.long 0x00 2. " TARW ,Time alarm register write" "Ignored,Normal"
|
|
bitfld.long 0x00 1. " TPRW ,Time prescaler register write" "Ignored,Normal"
|
|
bitfld.long 0x00 0. " TSRW ,Time seconds register write" "Ignored,Normal"
|
|
line.long 0x04 "RAR,RTC Read Access Register"
|
|
bitfld.long 0x04 7. " IERR ,Interrupt enable register read" "Ignored,Normal"
|
|
bitfld.long 0x04 6. " LRR ,Lock register read" "Ignored,Normal"
|
|
bitfld.long 0x04 5. " SRR ,Status register read" "Ignored,Normal"
|
|
bitfld.long 0x04 4. " CRR ,Control register read" "Ignored,Normal"
|
|
newline
|
|
bitfld.long 0x04 3. " TCRR ,Time compensation register read" "Ignored,Normal"
|
|
bitfld.long 0x04 2. " TARR ,Time alarm register read" "Ignored,Normal"
|
|
bitfld.long 0x04 1. " TPRR ,Time prescaler register read" "Ignored,Normal"
|
|
bitfld.long 0x04 0. " TSRR ,Time seconds register read" "Ignored,Normal"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
base ad:0x4003D000
|
|
width 5.
|
|
if (((per.l(ad:0x4003D000+0x14))&0x10)==0x00)
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "TSR,RTC Time Seconds Register"
|
|
line.long 0x04 "TPR,RTC Time Prescaler Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TPR ,Time prescaler"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "TSR,RTC Time Seconds Register"
|
|
line.long 0x04 "TPR,RTC Time Prescaler Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TPR ,Time prescaler"
|
|
endif
|
|
group.long 0x08++0x17
|
|
line.long 0x00 "TAR,RTC Time Alarm Register"
|
|
line.long 0x04 "TCR,RTC Time Compensation Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " CIC ,Compensation interval counter"
|
|
hexmask.long.byte 0x04 16.--23. 1. " TCV ,Time compensation value"
|
|
hexmask.long.byte 0x04 8.--15. 1. " CIR ,Compensation interval register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TCR ,Time compensation register"
|
|
line.long 0x08 "CR,RTC Control Register"
|
|
bitfld.long 0x08 13. " SC2P ,Oscillator 2pF load configure" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " SC4P ,Oscillator 4pF load configure" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " SC8P ,Oscillator 8pF load configure" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " SC16P ,Oscillator 16pF load configure" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 9. " CLKO ,Indicate whether clock is output to other peripherals or not" "Output,Not output"
|
|
bitfld.long 0x08 8. " OSCE ,Oscillator enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("MKL28*")
|
|
bitfld.long 0x08 7. " LPOS ,LPO select" "32kHz,1kHz LPO"
|
|
bitfld.long 0x08 5. " CPS ,Clock pin select" "0,1"
|
|
newline
|
|
endif
|
|
sif !cpuis("MKL05*")
|
|
bitfld.long 0x08 4. " WPS ,Wakeup pin select" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x08 3. " UM ,Update mode" "Low,High"
|
|
newline
|
|
bitfld.long 0x08 2. " SUP ,Supervisor write access" "Supervisor,Non-supervisor"
|
|
bitfld.long 0x08 1. " WPE ,Wakeup pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " SWR ,Software reset" "No reset,Reset"
|
|
line.long 0x0C "SR,RTC Status Register"
|
|
bitfld.long 0x0C 4. " TCE ,Time counter enable" "Disabled,Enabled"
|
|
rbitfld.long 0x0C 2. " TAF ,Time alarm flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x0C 1. " TOF ,Time overflow flag" "No overflow,Overflow"
|
|
rbitfld.long 0x0C 0. " TIF ,Time invalid flag" "Valid,Invalid"
|
|
line.long 0x10 "LR,RTC Lock Register"
|
|
bitfld.long 0x10 6. " LRL ,Lock register lock" "Locked,Not locked"
|
|
bitfld.long 0x10 5. " SRL ,Status register lock" "Locked,Not locked"
|
|
bitfld.long 0x10 4. " CRL ,Control register lock" "Locked,Not locked"
|
|
bitfld.long 0x10 3. " TCL ,Time compensation lock" "Locked,Not locked"
|
|
line.long 0x14 "IER,RTC Interrupt Enable Register"
|
|
bitfld.long 0x14 7. " WPON ,Wakeup pin on" "No effect,Wake up"
|
|
bitfld.long 0x14 4. " TSIE ,Time seconds interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " TAIE ,Time alarm interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " TOIE ,Time overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 0. " TIIE ,Time invalid interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("MKL82Z*")
|
|
group.long 0x800++0x07
|
|
line.long 0x00 "WAR,RTC Write Access Register"
|
|
bitfld.long 0x00 7. " IERW ,Interrupt enable register write" "Ignored,Normal"
|
|
bitfld.long 0x00 6. " LRW ,Lock register write" "Ignored,Normal"
|
|
bitfld.long 0x00 5. " SRW ,Status register write" "Ignored,Normal"
|
|
bitfld.long 0x00 4. " CRW ,Control register write" "Ignored,Normal"
|
|
newline
|
|
bitfld.long 0x00 3. " TCRW ,Time compensation register write" "Ignored,Normal"
|
|
bitfld.long 0x00 2. " TARW ,Time alarm register write" "Ignored,Normal"
|
|
bitfld.long 0x00 1. " TPRW ,Time prescaler register write" "Ignored,Normal"
|
|
bitfld.long 0x00 0. " TSRW ,Time seconds register write" "Ignored,Normal"
|
|
line.long 0x04 "RAR,RTC Read Access Register"
|
|
bitfld.long 0x04 7. " IERR ,Interrupt enable register read" "Ignored,Normal"
|
|
bitfld.long 0x04 6. " LRR ,Lock register read" "Ignored,Normal"
|
|
bitfld.long 0x04 5. " SRR ,Status register read" "Ignored,Normal"
|
|
bitfld.long 0x04 4. " CRR ,Control register read" "Ignored,Normal"
|
|
newline
|
|
bitfld.long 0x04 3. " TCRR ,Time compensation register read" "Ignored,Normal"
|
|
bitfld.long 0x04 2. " TARR ,Time alarm register read" "Ignored,Normal"
|
|
bitfld.long 0x04 1. " TPRR ,Time prescaler register read" "Ignored,Normal"
|
|
bitfld.long 0x04 0. " TSRR ,Time seconds register read" "Ignored,Normal"
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL46Z*")
|
|
tree "USBOTG (Universal Serial Bus OTG Controller)"
|
|
base ad:0x40072000
|
|
width 14.
|
|
rgroup.byte 0x00++0x00
|
|
line.byte 0x00 "PERID,Peripheral ID Register"
|
|
hexmask.byte 0x00 0.--5. 1. " ID ,Peripheral identification"
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "IDCOMP,Peripheral ID Complement Register"
|
|
hexmask.byte 0x00 0.--5. 1. " NID ,Ones complement of peripheral identification"
|
|
rgroup.byte 0x08++0x00
|
|
line.byte 0x00 "REV,Peripheral Revision Register"
|
|
rgroup.byte 0x0C++0x00
|
|
line.byte 0x00 "ADDINFO,Peripheral Additional Info Register"
|
|
sif !cpuis("MKL28Z*")&&!cpuis("MKL82Z*")
|
|
hexmask.byte 0x00 3.--7. 1. " IRQ_NUM ,Assigned interrupt request number"
|
|
newline
|
|
endif
|
|
bitfld.byte 0x00 0. " IEHOST ,Host mode enable" "Disabled,Enabled"
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "OTGISTAT,OTG Interrupt Status Register"
|
|
sif !cpuis("MKL28Z*")&&!cpuis("MKL82Z*")
|
|
bitfld.byte 0x00 7. " ID_CHG ,ID signal from USB connector change interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL28Z*")
|
|
eventfld.byte 0x00 6. " ONE_MSEC ,1 millisecond timer expired interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x00 5. " LINE_STATE_CHG ,USB line state change interrupt" "No interrupt,Interrupt"
|
|
else
|
|
bitfld.byte 0x00 6. " ONE_MSEC ,1 millisecond timer expired interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.byte 0x00 5. " LINE_STATE_CHG ,USB line state change interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
sif !cpuis("MKL28Z*")&&!cpuis("MKL82Z*")
|
|
newline
|
|
bitfld.byte 0x00 3. " SESS_VLD_CHG ,VBUS change indicating session valid/invalid interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.byte 0x00 2. " B_SESS_CHG ,VBUS change on B device interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " A_VBUS_CHG ,VBUS change on A device interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "OTGICR,OTG Interrupt Control Register"
|
|
sif !cpuis("MKL28Z*")&&!cpuis("MKL82Z*")
|
|
bitfld.byte 0x00 7. " ID_EN ,ID interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.byte 0x00 6. " ONE_MSEC_EN ,1 millisecond interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 5. " LINE_STATE_EN ,Line state change interrupt enable" "Disabled,Enabled"
|
|
sif !cpuis("MKL28Z*")&&!cpuis("MKL82Z*")
|
|
newline
|
|
bitfld.byte 0x00 3. " SESS_VLD_EN ,Session valid interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " B_SESS_EN ,B session END interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " A_VBUS_EN ,A VBUS valid interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "OTGSTAT,OTG Status Register"
|
|
sif !cpuis("MKL28Z*")&&!cpuis("MKL82Z*")
|
|
bitfld.byte 0x00 7. " ID ,Current state of the ID pin on USB connector" "Type A cable,No/type B cable"
|
|
bitfld.byte 0x00 6. " ONE_MSEC_EN ,1 millisecond interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.byte 0x00 5. " LINE_STATE_STABLE ,LINE_STATE_CHG bit stable" "Not stable,Stable"
|
|
sif !cpuis("MKL28Z*")&&!cpuis("MKL82Z*")
|
|
newline
|
|
bitfld.byte 0x00 3. " SESS_VLD ,Session valid" "Invalid,Valid"
|
|
newline
|
|
bitfld.byte 0x00 2. " B_SESS_END ,B session END" "Not END,END"
|
|
bitfld.byte 0x00 0. " A_VBUS_VLD ,A VBUS valid" "Invalid,Valid"
|
|
endif
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "OTGCTL,OTG Control Register"
|
|
bitfld.byte 0x00 7. " DP_HIGH ,D+ data line pullup resistor enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DP_LOW ,D+ data line pull-down resistor enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " DM_LOW ,D- data line pull-down resistor enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " OTG_EN ,On-the-go pullup/pulldown resistor enable" "Disabled,Enabled"
|
|
if (((per.b(ad:0x40072000+0x94))&0x08)==0x08)
|
|
group.byte 0x80++0x00
|
|
line.byte 0x00 "ISTAT,Interrupt Status Register"
|
|
eventfld.byte 0x00 7. " STALL ,Stall interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 6. " ATTACH ,Attach interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x00 5. " RESUME ,Signal remote wake-up signaling interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 4. " SLEEP ,Idle on USB bus (For 3ms) interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 3. " TOKDNE ,Token completed interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x00 2. " SOF_TOK ,Start of frame token interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 1. " ERROR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 0. " USB_RST ,USB reset interrupt" "No interrupt,Interrupt"
|
|
group.byte 0x84++0x00
|
|
line.byte 0x00 "INTEN,Interrupt Enable Register"
|
|
bitfld.byte 0x00 7. " STALL_EN ,STALL interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ATTACH_EN ,ATTACH interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " RESUME_EN ,RESUME interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " SLEEP_EN ,SLEEP interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TOK_DNE_EN ,TOK_DNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " SOF_TOK_EN ,SOF_TOK interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " ERROR_EN ,ERROR interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " USB_RST_EN ,USB_RST interrupt enable" "Disabled,Enabled"
|
|
group.byte 0x88++0x00
|
|
line.byte 0x00 "ERRSTAT,Error Interrupt Status Register"
|
|
sif cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL46Z*")||(cpu()=="MK21DX128VLK5")||(cpu()=="MK21DX256VLK5")||(cpu()=="MK21DN512VLK5")||(cpu()=="MK21DX128VMC5")||(cpu()=="MK21DX256VMC5")||(cpu()=="MK21DN512VMC5")||(cpu()=="MK22DX128VLF5")||(cpu()=="MK22DX256VLF5")||(cpu()=="MK22DX128VLH5")||(cpu()=="MK22DX256VLH5")||(cpu()=="MK22DN512VLH5")||(cpu()=="MK22DX128VLK5")||(cpu()=="MK22DX256VLK5")||(cpu()=="MK22DN512VLK5")||(cpu()=="MK22DX128VMC5")||(cpu()=="MK22DX256VMC5")||(cpu()=="MK22DN512VMC5")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")||cpuis("MKL28Z*")||cpuis("MKL82Z*")||(cpu()=="MK40DN512ZVLL10")||(cpu()=="MK40DN512ZVLQ10")||(cpu()=="MK40DN512ZVMD10")||(cpu()=="MK40DX128ZVLQ10")||(cpu()=="MK40DX256ZVLQ10")||(cpu()=="MK40DX256ZVMD10")
|
|
eventfld.byte 0x00 7. " BTS_ERR ,Bit stuff error interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 5. " DMA_ERR ,DMA error interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 4. " BTOERR ,Bus turnaround timeout error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x00 3. " DFN8 ,Data received was not 8 bits in length interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 2. " CRC16 ,CRC16 error interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 1. " EOF ,End of frame error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x00 0. " PID_ERR ,PID check failed interrupt" "No interrupt,Interrupt"
|
|
else
|
|
bitfld.byte 0x00 7. " BTS_ERR ,Bit stuff error interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 5. " DMA_ERR ,DMA error interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 4. " BTO ,Bus turnaround timeout error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.byte 0x00 3. " DFN8 ,Data received was not 8 bits in length interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 2. " CRC16 ,CRC16 error interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " EOF ,End of frame error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.byte 0x00 0. " PID_ERR ,PID check failed interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
group.byte 0x8C++0x00
|
|
line.byte 0x00 "ERREN,Error Interrupt Enable Register"
|
|
bitfld.byte 0x00 7. " BTS_ERR_EN ,BTS_ERR interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DMA_ERR_EN ,DMA_ERR interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " BTO_ERR_EN ,BTO_ERR interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 3. " DFN8_EN ,DFN8 interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " CRC16_EN ,CRC16 interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EOF_EN ,EOF interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 0. " PID_ERR_EN ,PID_ERR interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x80++0x00
|
|
line.byte 0x00 "ISTAT,Interrupt Status Register"
|
|
eventfld.byte 0x00 7. " STALL ,Stall interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x00 5. " RESUME ,Signal remote wake-up signaling interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 4. " SLEEP ,Idle on USB bus (For 3ms) interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 3. " TOKDNE ,Token completed interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x00 2. " SOF_TOK ,Start of frame token interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 1. " ERROR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 0. " USB_RST ,USB reset interrupt" "No interrupt,Interrupt"
|
|
group.byte 0x84++0x00
|
|
line.byte 0x00 "INTEN,Interrupt Enable Register"
|
|
bitfld.byte 0x00 7. " STALL_EN ,STALL interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 5. " RESUME_EN ,RESUME interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " SLEEP_EN ,SLEEP interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TOK_DNE_EN ,TOK_DNE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 2. " SOF_TOK_EN ,SOF_TOK interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " ERROR_EN ,ERROR interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " USB_RST_EN ,USB_RST interrupt enable" "Disabled,Enabled"
|
|
group.byte 0x88++0x00
|
|
line.byte 0x00 "ERRSTAT,Error Interrupt Status Register"
|
|
sif cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL46Z*")||(cpu()=="MK21DX128VLK5")||(cpu()=="MK21DX256VLK5")||(cpu()=="MK21DN512VLK5")||(cpu()=="MK21DX128VMC5")||(cpu()=="MK21DX256VMC5")||(cpu()=="MK21DN512VMC5")||(cpu()=="MK22DX128VLF5")||(cpu()=="MK22DX256VLF5")||(cpu()=="MK22DX128VLH5")||(cpu()=="MK22DX256VLH5")||(cpu()=="MK22DN512VLH5")||(cpu()=="MK22DX128VLK5")||(cpu()=="MK22DX256VLK5")||(cpu()=="MK22DN512VLK5")||(cpu()=="MK22DX128VMC5")||(cpu()=="MK22DX256VMC5")||(cpu()=="MK22DN512VMC5")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")||cpuis("MKL28Z*")||cpuis("MKL82Z*")||(cpu()=="MK40DN512ZVLL10")||(cpu()=="MK40DN512ZVLQ10")||(cpu()=="MK40DN512ZVMD10")||(cpu()=="MK40DX128ZVLQ10")||(cpu()=="MK40DX256ZVLQ10")||(cpu()=="MK40DX256ZVMD10")
|
|
eventfld.byte 0x00 7. " BTS_ERR ,Bit stuff error interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 5. " DMA_ERR ,DMA error interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 4. " BTO ,Bus turnaround timeout error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x00 3. " DFN8 ,Data received was not 8 bits in length interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 2. " CRC16 ,CRC16 error interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 1. " CRC5 ,CRC5 error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x00 0. " PID_ERR ,PID check failed interrupt" "No interrupt,Interrupt"
|
|
else
|
|
bitfld.byte 0x00 7. " BTS_ERR ,Bit stuff error interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 5. " DMA_ERR ,DMA error interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 4. " BTO ,Bus turnaround timeout error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.byte 0x00 3. " DFN8 ,Data received was not 8 bits in length interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 2. " CRC16 ,CRC16 error interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " CRC5 ,CRC5 error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.byte 0x00 0. " PID_ERR ,PID check failed interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
group.byte 0x8C++0x00
|
|
line.byte 0x00 "ERREN,Error Interrupt Enable Register"
|
|
bitfld.byte 0x00 7. " BTS_ERR_EN ,BTS_ERR interrupt enable" "Disabled,Enabled"
|
|
sif !cpuis("MKL28Z*")&&!cpuis("MKL82Z*")&&!(cpu()=="MK40DN512ZVLQ10")&&!(cpu()=="MK40DN512ZVMD10")&&!(cpu()=="MK40DX128ZVLQ10")&&!(cpu()=="MK40DX256ZVLQ10")&&!(cpu()=="MK40DX256ZVMD10")&&!(cpu()=="MK40DN512ZVLL10")
|
|
newline
|
|
bitfld.byte 0x00 6. " OWNERREN ,OWNERR interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.byte 0x00 5. " DMA_ERR_EN ,DMA_ERR interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " BTO_ERR_EN ,BTO_ERR interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 3. " DFN8_EN ,DFN8 interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " CRC16_EN ,CRC16 interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " CRC5_EN ,CRC5 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 0. " PID_ERR_EN ,PID_ERR interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40072000+0x84))&0x08)==0x08)
|
|
rgroup.byte 0x90++0x00
|
|
line.byte 0x00 "STAT,Status Register"
|
|
bitfld.byte 0x00 4.--7. " ENDP ,Endpoint address" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
|
|
bitfld.byte 0x00 3. " TX ,Transmit indicator" "Receive,Transmit"
|
|
bitfld.byte 0x00 2. " ODD ,Last buffer descriptor in odd bank of BDT" "Not odd,Odd"
|
|
else
|
|
hgroup.byte 0x90++0x00
|
|
hide.byte 0x00 "STAT,Status Register"
|
|
endif
|
|
if (((per.b(ad:0x40072000+0x94))&0x08)==0x08)
|
|
group.byte 0x94++0x00
|
|
line.byte 0x00 "CTL,Control Register"
|
|
bitfld.byte 0x00 7. " JSTATE ,Live USB differential receiver JSTATE signal" "Low,High"
|
|
bitfld.byte 0x00 6. " SE0 ,Live USB single ended zero signal" "Low,High"
|
|
bitfld.byte 0x00 5. " TOKEN_BUSY ,USB module is busy executing a USB token" "Not busy,Busy"
|
|
bitfld.byte 0x00 4. " RESET ,USB reset" "No reset,Reset"
|
|
newline
|
|
bitfld.byte 0x00 3. " HOST_MODE_EN ,Host mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RESUME ,Resume signaling enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " ODD_RST ,BDT ODD ping/pong bits reset" "No reset,Reset"
|
|
bitfld.byte 0x00 0. " USB_EN_SOF_EN ,USB enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x94++0x00
|
|
line.byte 0x00 "CTL,Control Register"
|
|
bitfld.byte 0x00 7. " JSTATE ,Live USB differential receiver JSTATE signal" "Low,High"
|
|
bitfld.byte 0x00 6. " SE0 ,Live USB single ended zero signal" "Low,High"
|
|
bitfld.byte 0x00 5. " TX_SUSPEND ,Packet transmission and reception disable" "No,Yes"
|
|
newline
|
|
bitfld.byte 0x00 3. " HOST_MODE_EN ,Host mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RESUME ,Resume signaling enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " ODD_RST ,BDT ODD ping/pong bits reset" "No reset,Reset"
|
|
bitfld.byte 0x00 0. " USB_EN_SOF_EN ,USB enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x98++0x00
|
|
line.byte 0x00 "ADDR,Address Register"
|
|
bitfld.byte 0x00 7. " LS_EN ,Low speed enable" "Disabled,Enabled"
|
|
hexmask.byte 0x00 0.--6. 0x01 " ADDR ,USB address"
|
|
group.byte 0x9C++0x00
|
|
line.byte 0x00 "BDTPAGE1,BDT Page Register 1"
|
|
hexmask.byte 0x00 1.--7. 0x02 " BDT_BA[15:9] ,BDT base address bits [15:9]"
|
|
group.byte 0xA0++0x00
|
|
line.byte 0x00 "FRMNUML,Frame Number Register Low"
|
|
group.byte 0xA4++0x00
|
|
line.byte 0x00 "FRMNUMH,Frame Number Register High"
|
|
bitfld.byte 0x00 0.--2. " FRM[10:8] ,Upper 3 bits of BDT system memory address" "000,001,010,011,100,101,110,111"
|
|
if (((per.b(ad:0x40072000+0x94))&0x08)==0x08)
|
|
group.byte 0xA8++0x00
|
|
line.byte 0x00 "TOKEN,Token Register"
|
|
bitfld.byte 0x00 4.--7. " TOKEN_PID ,Token type" ",OUT,,,,,,,,IN,,,,SETUP,?..."
|
|
bitfld.byte 0x00 0.--3. " TOKEN_ENDPT ,Endpoint address for the token command" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
|
|
group.byte 0xAC++0x00
|
|
line.byte 0x00 "SOFTHLD,SOF Threshold Register"
|
|
else
|
|
hgroup.byte 0xA8++0x00
|
|
hide.byte 0x00 "TOKEN,Token Register"
|
|
hgroup.byte 0xAC++0x00
|
|
hide.byte 0x00 "SOFTHLD,SOF Threshold Register"
|
|
endif
|
|
group.byte 0xB0++0x00
|
|
line.byte 0x00 "BDTPAGE2,BDT Page Register 2"
|
|
group.byte 0xB4++0x00
|
|
line.byte 0x00 "BDTPAGE3,BDT Page Register 3"
|
|
width 9.
|
|
tree "Endpoints Registers"
|
|
if (((per.b(ad:0x40072000+0x94))&0x08)==0x08)&&(((per.b(ad:0x40072000+0xC0))&0x0C)!=0x00)
|
|
group.byte 0xC0++0x00
|
|
line.byte 0x00 "ENDPT0,Endpoint Control Register 0"
|
|
bitfld.byte 0x00 7. " HOST_WO_HUB ,Host communicated to directly connected low speed device" "Not allowed,Allowed"
|
|
bitfld.byte 0x00 6. " RETRY_DIS ,Negative acknowledgement transactions retry disable" "No,Yes"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
newline
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0x40072000+0x94))&0x08)==0x00)&&(((per.b(ad:0x40072000+0xC0))&0x0C)!=0x00)
|
|
group.byte 0xC0++0x00
|
|
line.byte 0x00 "ENDPT0,Endpoint Control Register 0"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0x40072000+0x94))&0x08)==0x08)&&(((per.b(ad:0x40072000+0xC0))&0x0C)==0x00)
|
|
group.byte 0xC0++0x00
|
|
line.byte 0x00 "ENDPT0,Endpoint Control Register 0"
|
|
bitfld.byte 0x00 7. " HOST_WO_HUB ,Host communicated to directly connected low speed device" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.byte 0x00 6. " RETRY_DIS ,Negative acknowledgement transactions retry disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xC0++0x00
|
|
line.byte 0x00 "ENDPT0,Endpoint Control Register 0"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40072000+0xC4))&0x0C)!=0x00)
|
|
group.byte 0xC4++0x00
|
|
line.byte 0x00 "ENDPT1,Endpoint Control Register 1"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xC4++0x00
|
|
line.byte 0x00 "ENDPT1,Endpoint Control Register 1"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40072000+0xC8))&0x0C)!=0x00)
|
|
group.byte 0xC8++0x00
|
|
line.byte 0x00 "ENDPT2,Endpoint Control Register 2"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xC8++0x00
|
|
line.byte 0x00 "ENDPT2,Endpoint Control Register 2"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40072000+0xCC))&0x0C)!=0x00)
|
|
group.byte 0xCC++0x00
|
|
line.byte 0x00 "ENDPT3,Endpoint Control Register 3"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xCC++0x00
|
|
line.byte 0x00 "ENDPT3,Endpoint Control Register 3"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40072000+0xD0))&0x0C)!=0x00)
|
|
group.byte 0xD0++0x00
|
|
line.byte 0x00 "ENDPT4,Endpoint Control Register 4"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xD0++0x00
|
|
line.byte 0x00 "ENDPT4,Endpoint Control Register 4"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40072000+0xD4))&0x0C)!=0x00)
|
|
group.byte 0xD4++0x00
|
|
line.byte 0x00 "ENDPT5,Endpoint Control Register 5"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xD4++0x00
|
|
line.byte 0x00 "ENDPT5,Endpoint Control Register 5"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40072000+0xD8))&0x0C)!=0x00)
|
|
group.byte 0xD8++0x00
|
|
line.byte 0x00 "ENDPT6,Endpoint Control Register 6"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xD8++0x00
|
|
line.byte 0x00 "ENDPT6,Endpoint Control Register 6"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40072000+0xDC))&0x0C)!=0x00)
|
|
group.byte 0xDC++0x00
|
|
line.byte 0x00 "ENDPT7,Endpoint Control Register 7"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xDC++0x00
|
|
line.byte 0x00 "ENDPT7,Endpoint Control Register 7"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40072000+0xE0))&0x0C)!=0x00)
|
|
group.byte 0xE0++0x00
|
|
line.byte 0x00 "ENDPT8,Endpoint Control Register 8"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xE0++0x00
|
|
line.byte 0x00 "ENDPT8,Endpoint Control Register 8"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40072000+0xE4))&0x0C)!=0x00)
|
|
group.byte 0xE4++0x00
|
|
line.byte 0x00 "ENDPT9,Endpoint Control Register 9"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xE4++0x00
|
|
line.byte 0x00 "ENDPT9,Endpoint Control Register 9"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40072000+0xE8))&0x0C)!=0x00)
|
|
group.byte 0xE8++0x00
|
|
line.byte 0x00 "ENDPT10,Endpoint Control Register 10"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xE8++0x00
|
|
line.byte 0x00 "ENDPT10,Endpoint Control Register 10"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40072000+0xEC))&0x0C)!=0x00)
|
|
group.byte 0xEC++0x00
|
|
line.byte 0x00 "ENDPT11,Endpoint Control Register 11"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xEC++0x00
|
|
line.byte 0x00 "ENDPT11,Endpoint Control Register 11"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40072000+0xF0))&0x0C)!=0x00)
|
|
group.byte 0xF0++0x00
|
|
line.byte 0x00 "ENDPT12,Endpoint Control Register 12"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xF0++0x00
|
|
line.byte 0x00 "ENDPT12,Endpoint Control Register 12"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40072000+0xF4))&0x0C)!=0x00)
|
|
group.byte 0xF4++0x00
|
|
line.byte 0x00 "ENDPT13,Endpoint Control Register 13"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xF4++0x00
|
|
line.byte 0x00 "ENDPT13,Endpoint Control Register 13"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40072000+0xF8))&0x0C)!=0x00)
|
|
group.byte 0xF8++0x00
|
|
line.byte 0x00 "ENDPT14,Endpoint Control Register 14"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xF8++0x00
|
|
line.byte 0x00 "ENDPT14,Endpoint Control Register 14"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40072000+0xFC))&0x0C)!=0x00)
|
|
group.byte 0xFC++0x00
|
|
line.byte 0x00 "ENDPT15,Endpoint Control Register 15"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xFC++0x00
|
|
line.byte 0x00 "ENDPT15,Endpoint Control Register 15"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
tree.end
|
|
width 28.
|
|
newline
|
|
group.byte 0x100++0x00
|
|
line.byte 0x00 "USBCTRL,USB Control Register"
|
|
bitfld.byte 0x00 7. " SUSP ,USB transceiver suspend state" "Not suspended,Suspended"
|
|
bitfld.byte 0x00 6. " PDE ,USB transceiver weak pulldowns enable" "Disabled,Enabled"
|
|
sif cpuis("MKL28Z*")||cpuis("MKL82Z*")
|
|
newline
|
|
bitfld.byte 0x00 5. " UARTCHLS ,UART signal channel select" "UART TX/RX,UART RX/TX"
|
|
bitfld.byte 0x00 4. " UARTSEL ,Selects USB signals to be used as UART signals" "Not used,Used"
|
|
endif
|
|
rgroup.byte 0x104++0x00
|
|
line.byte 0x00 "OBSERVE,USB OTG Observe Register"
|
|
bitfld.byte 0x00 7. " DP_PU ,D+ pull up signal output observability" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DP_PD ,D+ pull down signal output observability" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " DM_PD ,D- pull down signal output observability" "Disabled,Enabled"
|
|
group.byte 0x108++0x00
|
|
line.byte 0x00 "CONTROL,USB OTG Control Register"
|
|
bitfld.byte 0x00 4. " DPPULLUP_NONOTG ,DP PULLUP in the USB OTG control" "Disabled,Enabled"
|
|
sif (cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL46Z*")||cpuis("MKL28Z*")||(cpu()=="MK40DN512ZVLL10")||(cpu()=="MK40DN512ZVLQ10")||(cpu()=="MK40DN512ZVMD10")||(cpu()=="MK40DX128ZVLQ10")||(cpu()=="MK40DX256ZVLQ10")||(cpu()=="MK40DX256ZVMD10")
|
|
group.byte 0x10C++0x00
|
|
line.byte 0x00 "USBTRC0,USB Transceiver Control Register 0"
|
|
bitfld.byte 0x00 7. " USBRESET ,USB_OTG module reset" "No reset,Reset"
|
|
bitfld.byte 0x00 5. " USBRESMEN ,Asynchronous resume interrupt enable" "Disabled,Enabled"
|
|
sif cpuis("MKL28Z*")||cpuis("MKL82Z*")
|
|
newline
|
|
rbitfld.byte 0x00 4. " VFEDG_DET ,VREGIN falling edge interrupt detect" "Not detected,Detected"
|
|
rbitfld.byte 0x00 3. " VREDG_DET ,VREGIN rising edge interrupt detect" "Not detected,Detected"
|
|
rbitfld.byte 0x00 2. " USB_CLK_RECOVERY_INT ,Combined USB clock recovery interrupt status" "Not detected,Detected"
|
|
endif
|
|
newline
|
|
rbitfld.byte 0x00 1. " SYNC_DET ,Synchronous USB interrupt detect" "Not detected,Detected"
|
|
rbitfld.byte 0x00 0. " USB_RESUME_INT ,USB asynchronous interrupt" "No interrupt,Interrupt"
|
|
else
|
|
group.byte 0x10C++0x00
|
|
line.byte 0x00 "USBTRC0,USB Transceiver Control Register 0"
|
|
bitfld.byte 0x00 7. " USBRESET ,USB_OTG module reset" "No reset,Reset"
|
|
bitfld.byte 0x00 5. " USBRESMEN ,Asynchronous resume interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SYNC_DET ,Synchronous USB interrupt detect" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " USB_RESUME_INT ,USB asynchronous interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
sif (cpuis("K70"))||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL46Z*")||(cpu()=="MK21DX128VLK5")||(cpu()=="MK21DX256VLK5")||(cpu()=="MK21DN512VLK5")||(cpu()=="MK21DX128VMC5")||(cpu()=="MK21DX256VMC5")||(cpu()=="MK21DN512VMC5")||(cpu()=="MK22DX128VLF5")||(cpu()=="MK22DX256VLF5")||(cpu()=="MK22DX128VLH5")||(cpu()=="MK22DX256VLH5")||(cpu()=="MK22DN512VLH5")||(cpu()=="MK22DX128VLK5")||(cpu()=="MK22DX256VLK5")||(cpu()=="MK22DN512VLK5")||(cpu()=="MK22DX128VMC5")||(cpu()=="MK22DX256VMC5")||(cpu()=="MK22DN512VMC5")||(cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")
|
|
group.byte 0x114++0x00
|
|
line.byte 0x00 "USBFRMADJUST,Frame Adjust Register"
|
|
elif cpuis("MKL28Z*")||cpuis("MKL82Z*")
|
|
group.byte 0x114++0x00
|
|
line.byte 0x00 "USBFRMADJUST,Frame Adjust Register"
|
|
sif cpuis("MKL82Z*")
|
|
group.byte 0x124++0x01
|
|
line.byte 0x00 "KEEP_ALIVE_CTRL,Keep Alive Mode Control"
|
|
rbitfld.byte 0x00 7. " WAKE_INT_STS ,Wakeup interrupt status" "Not received,Received"
|
|
newline
|
|
bitfld.byte 0x00 4. " WAKE_INT_EN ,Wakeup interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " WAKE_REQ_EN ,Wakeup request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " OWN_OVERRD_EN ,OWN override enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 0. " KEEP_ALIVE_EN ,Keep alive enabled" "Disabled,Enabled"
|
|
line.byte 0x01 "KEEP_ALIVE_WKCTRL,Keep Alive Mode Wakeup Control"
|
|
rbitfld.byte 0x01 4.--7. " WAKE_ENDPT ,Wakeup endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x01 0.--3. " WAKE_ON_THIS ,Wakeup usb" ",OUT/SETUP,,,,,,,,,,,,SETUP,?..."
|
|
endif
|
|
if (((per.b(ad:0x40072000+0x94))&0x08)==0x08)
|
|
group.byte 0x12C++0x00
|
|
line.byte 0x00 "MISCCTRL,Miscellaneous Control Register"
|
|
bitfld.byte 0x00 4. " VFEDG_EN ,VREGIN falling edge interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " VREDG_EN ,VREGIN rising edge interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SOFBUSSET ,SOF_TOK interrupt generation mode select" "SOF threshold value,Counter reaches 0"
|
|
bitfld.byte 0x00 0. " SOFDYNTHLD ,Dynamic SOF threshold compare mode" "Byte time,8 byte times"
|
|
else
|
|
group.byte 0x12C++0x00
|
|
line.byte 0x00 "MISCCTRL,Miscellaneous Control Register"
|
|
bitfld.byte 0x00 4. " VFEDG_EN ,VREGIN falling edge interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " VREDG_EN ,VREGIN rising edge interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " OWNERRISODIS ,OWN error detect for ISO IN / ISO OUT disable" "No,Yes"
|
|
endif
|
|
sif cpuis("MKL82Z*")
|
|
if ((((per.b(ad:0x40072000+0x94))&0x8)!=0x8)&&(((per.b(ad:0x40072000+0x12C))&0x80)==0x80))
|
|
group.byte 0x130++0x00
|
|
line.byte 0x00 "USB_STALL_IL_DIS,Peripheral Mode Stall Disable For Endpoints 7 To 0 In IN Direction"
|
|
bitfld.byte 0x00 7. " STALL_I_DIS7 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 6. " STALL_I_DIS6 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 5. " STALL_I_DIS5 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 4. " STALL_I_DIS4 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " STALL_I_DIS3 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 2. " STALL_I_DIS2 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 1. " STALL_I_DIS1 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 0. " STALL_I_DIS0 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
group.byte 0x134++0x00
|
|
line.byte 0x00 "USB_STALL_IH_DIS,Peripheral Mode Stall Disable For Endpoints 15 To 8 In IN Direction"
|
|
bitfld.byte 0x00 7. " STALL_I_DIS15 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 6. " STALL_I_DIS14 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 5. " STALL_I_DIS13 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 4. " STALL_I_DIS12 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " STALL_I_DIS11 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 2. " STALL_I_DIS10 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 1. " STALL_I_DIS9 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 0. " STALL_I_DIS8 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
group.byte 0x138++0x00
|
|
line.byte 0x00 "USB_STALL_OL_DIS,Peripheral Mode Stall Disable For Endpoints 7 To 0 In OUT Direction"
|
|
bitfld.byte 0x00 7. " STALL_O_DIS7 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 6. " STALL_O_DIS6 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 5. " STALL_O_DIS5 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 4. " STALL_O_DIS4 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " STALL_O_DIS3 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 2. " STALL_O_DIS2 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 1. " STALL_O_DIS1 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 0. " STALL_O_DIS0 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
group.byte 0x13C++0x00
|
|
line.byte 0x00 "USB_STALL_OH_DIS,Peripheral Mode Stall Disable For Endpoints 15 To 0 In OUT Direction"
|
|
bitfld.byte 0x00 7. " STALL_O_DIS15 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 6. " STALL_O_DIS14 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 5. " STALL_O_DIS13 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 4. " STALL_O_DIS12 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " STALL_O_DIS11 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 2. " STALL_O_DIS10 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 1. " STALL_O_DIS9 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 0. " STALL_O_DIS8 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
endif
|
|
endif
|
|
group.byte 0x140++0x00
|
|
line.byte 0x00 "USB_CLK_RECOVER_CTRL,USB Clock Recovery Control Register"
|
|
bitfld.byte 0x00 7. " CLOCK_RECOVER_EN ,Crystal-less USB enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RESET_RESUME_ROUGH_EN ,Reset/resume to rough phase enable" "Resume,Reset"
|
|
newline
|
|
bitfld.byte 0x00 5. " RESTART_IFRTRIM_EN ,Restart from IFR trim value" "No effect,Restart"
|
|
group.byte 0x144++0x00
|
|
line.byte 0x00 "USB_CLK_RECOVER_IRC_EN,IRC48M Oscillator Enable Register"
|
|
group.byte 0x154++0x00
|
|
line.byte 0x00 "USB_CLK_RECOVER_INT_EN,Clock Recovery Combined Interrupt Enable Register"
|
|
bitfld.byte 0x00 4. " OVF_ERROR_EN ,Determines whether OVF_ERROR condition signal is used in generation of USB_CLK_RECOVERY_INT" "Disabled,Enabled"
|
|
hgroup.byte 0x15C++0x00
|
|
hide.byte 0x00 "USB_CLK_RECOVER_INT_STATUS,Clock Recovery Separated Interrupt Status Register"
|
|
in
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
elif cpuis("MKL28Z*")||cpuis("MKL82Z*")
|
|
tree "USBFSOTG (Universal Serial Bus Full Speed OTG Controller)"
|
|
base ad:0x40055000
|
|
width 14.
|
|
rgroup.byte 0x00++0x00
|
|
line.byte 0x00 "PERID,Peripheral ID Register"
|
|
hexmask.byte 0x00 0.--5. 1. " ID ,Peripheral identification"
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "IDCOMP,Peripheral ID Complement Register"
|
|
hexmask.byte 0x00 0.--5. 1. " NID ,Ones complement of peripheral identification"
|
|
rgroup.byte 0x08++0x00
|
|
line.byte 0x00 "REV,Peripheral Revision Register"
|
|
rgroup.byte 0x0C++0x00
|
|
line.byte 0x00 "ADDINFO,Peripheral Additional Info Register"
|
|
sif !cpuis("MKL28Z*")&&!cpuis("MKL82Z*")
|
|
hexmask.byte 0x00 3.--7. 1. " IRQ_NUM ,Assigned interrupt request number"
|
|
newline
|
|
endif
|
|
bitfld.byte 0x00 0. " IEHOST ,Host mode enable" "Disabled,Enabled"
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "OTGISTAT,OTG Interrupt Status Register"
|
|
sif !cpuis("MKL28Z*")&&!cpuis("MKL82Z*")
|
|
bitfld.byte 0x00 7. " ID_CHG ,ID signal from USB connector change interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL28Z*")
|
|
eventfld.byte 0x00 6. " ONE_MSEC ,1 millisecond timer expired interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x00 5. " LINE_STATE_CHG ,USB line state change interrupt" "No interrupt,Interrupt"
|
|
else
|
|
bitfld.byte 0x00 6. " ONE_MSEC ,1 millisecond timer expired interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.byte 0x00 5. " LINE_STATE_CHG ,USB line state change interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
sif !cpuis("MKL28Z*")&&!cpuis("MKL82Z*")
|
|
newline
|
|
bitfld.byte 0x00 3. " SESS_VLD_CHG ,VBUS change indicating session valid/invalid interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.byte 0x00 2. " B_SESS_CHG ,VBUS change on B device interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " A_VBUS_CHG ,VBUS change on A device interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "OTGICR,OTG Interrupt Control Register"
|
|
sif !cpuis("MKL28Z*")&&!cpuis("MKL82Z*")
|
|
bitfld.byte 0x00 7. " ID_EN ,ID interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.byte 0x00 6. " ONE_MSEC_EN ,1 millisecond interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 5. " LINE_STATE_EN ,Line state change interrupt enable" "Disabled,Enabled"
|
|
sif !cpuis("MKL28Z*")&&!cpuis("MKL82Z*")
|
|
newline
|
|
bitfld.byte 0x00 3. " SESS_VLD_EN ,Session valid interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " B_SESS_EN ,B session END interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " A_VBUS_EN ,A VBUS valid interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "OTGSTAT,OTG Status Register"
|
|
sif !cpuis("MKL28Z*")&&!cpuis("MKL82Z*")
|
|
bitfld.byte 0x00 7. " ID ,Current state of the ID pin on USB connector" "Type A cable,No/type B cable"
|
|
bitfld.byte 0x00 6. " ONE_MSEC_EN ,1 millisecond interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.byte 0x00 5. " LINE_STATE_STABLE ,LINE_STATE_CHG bit stable" "Not stable,Stable"
|
|
sif !cpuis("MKL28Z*")&&!cpuis("MKL82Z*")
|
|
newline
|
|
bitfld.byte 0x00 3. " SESS_VLD ,Session valid" "Invalid,Valid"
|
|
newline
|
|
bitfld.byte 0x00 2. " B_SESS_END ,B session END" "Not END,END"
|
|
bitfld.byte 0x00 0. " A_VBUS_VLD ,A VBUS valid" "Invalid,Valid"
|
|
endif
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "OTGCTL,OTG Control Register"
|
|
bitfld.byte 0x00 7. " DP_HIGH ,D+ data line pullup resistor enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DP_LOW ,D+ data line pull-down resistor enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " DM_LOW ,D- data line pull-down resistor enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " OTG_EN ,On-the-go pullup/pulldown resistor enable" "Disabled,Enabled"
|
|
if (((per.b(ad:0x40055000+0x94))&0x08)==0x08)
|
|
group.byte 0x80++0x00
|
|
line.byte 0x00 "ISTAT,Interrupt Status Register"
|
|
eventfld.byte 0x00 7. " STALL ,Stall interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 6. " ATTACH ,Attach interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x00 5. " RESUME ,Signal remote wake-up signaling interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 4. " SLEEP ,Idle on USB bus (For 3ms) interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 3. " TOKDNE ,Token completed interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x00 2. " SOF_TOK ,Start of frame token interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 1. " ERROR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 0. " USB_RST ,USB reset interrupt" "No interrupt,Interrupt"
|
|
group.byte 0x84++0x00
|
|
line.byte 0x00 "INTEN,Interrupt Enable Register"
|
|
bitfld.byte 0x00 7. " STALL_EN ,STALL interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ATTACH_EN ,ATTACH interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " RESUME_EN ,RESUME interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " SLEEP_EN ,SLEEP interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TOK_DNE_EN ,TOK_DNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " SOF_TOK_EN ,SOF_TOK interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " ERROR_EN ,ERROR interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " USB_RST_EN ,USB_RST interrupt enable" "Disabled,Enabled"
|
|
group.byte 0x88++0x00
|
|
line.byte 0x00 "ERRSTAT,Error Interrupt Status Register"
|
|
sif cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL46Z*")||(cpu()=="MK21DX128VLK5")||(cpu()=="MK21DX256VLK5")||(cpu()=="MK21DN512VLK5")||(cpu()=="MK21DX128VMC5")||(cpu()=="MK21DX256VMC5")||(cpu()=="MK21DN512VMC5")||(cpu()=="MK22DX128VLF5")||(cpu()=="MK22DX256VLF5")||(cpu()=="MK22DX128VLH5")||(cpu()=="MK22DX256VLH5")||(cpu()=="MK22DN512VLH5")||(cpu()=="MK22DX128VLK5")||(cpu()=="MK22DX256VLK5")||(cpu()=="MK22DN512VLK5")||(cpu()=="MK22DX128VMC5")||(cpu()=="MK22DX256VMC5")||(cpu()=="MK22DN512VMC5")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")||cpuis("MKL28Z*")||cpuis("MKL82Z*")||(cpu()=="MK40DN512ZVLL10")||(cpu()=="MK40DN512ZVLQ10")||(cpu()=="MK40DN512ZVMD10")||(cpu()=="MK40DX128ZVLQ10")||(cpu()=="MK40DX256ZVLQ10")||(cpu()=="MK40DX256ZVMD10")
|
|
eventfld.byte 0x00 7. " BTS_ERR ,Bit stuff error interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 5. " DMA_ERR ,DMA error interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 4. " BTOERR ,Bus turnaround timeout error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x00 3. " DFN8 ,Data received was not 8 bits in length interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 2. " CRC16 ,CRC16 error interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 1. " EOF ,End of frame error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x00 0. " PID_ERR ,PID check failed interrupt" "No interrupt,Interrupt"
|
|
else
|
|
bitfld.byte 0x00 7. " BTS_ERR ,Bit stuff error interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 5. " DMA_ERR ,DMA error interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 4. " BTO ,Bus turnaround timeout error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.byte 0x00 3. " DFN8 ,Data received was not 8 bits in length interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 2. " CRC16 ,CRC16 error interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " EOF ,End of frame error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.byte 0x00 0. " PID_ERR ,PID check failed interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
group.byte 0x8C++0x00
|
|
line.byte 0x00 "ERREN,Error Interrupt Enable Register"
|
|
bitfld.byte 0x00 7. " BTS_ERR_EN ,BTS_ERR interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DMA_ERR_EN ,DMA_ERR interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " BTO_ERR_EN ,BTO_ERR interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 3. " DFN8_EN ,DFN8 interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " CRC16_EN ,CRC16 interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EOF_EN ,EOF interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 0. " PID_ERR_EN ,PID_ERR interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x80++0x00
|
|
line.byte 0x00 "ISTAT,Interrupt Status Register"
|
|
eventfld.byte 0x00 7. " STALL ,Stall interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x00 5. " RESUME ,Signal remote wake-up signaling interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 4. " SLEEP ,Idle on USB bus (For 3ms) interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 3. " TOKDNE ,Token completed interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x00 2. " SOF_TOK ,Start of frame token interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 1. " ERROR ,Error interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 0. " USB_RST ,USB reset interrupt" "No interrupt,Interrupt"
|
|
group.byte 0x84++0x00
|
|
line.byte 0x00 "INTEN,Interrupt Enable Register"
|
|
bitfld.byte 0x00 7. " STALL_EN ,STALL interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 5. " RESUME_EN ,RESUME interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " SLEEP_EN ,SLEEP interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TOK_DNE_EN ,TOK_DNE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 2. " SOF_TOK_EN ,SOF_TOK interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " ERROR_EN ,ERROR interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " USB_RST_EN ,USB_RST interrupt enable" "Disabled,Enabled"
|
|
group.byte 0x88++0x00
|
|
line.byte 0x00 "ERRSTAT,Error Interrupt Status Register"
|
|
sif cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL46Z*")||(cpu()=="MK21DX128VLK5")||(cpu()=="MK21DX256VLK5")||(cpu()=="MK21DN512VLK5")||(cpu()=="MK21DX128VMC5")||(cpu()=="MK21DX256VMC5")||(cpu()=="MK21DN512VMC5")||(cpu()=="MK22DX128VLF5")||(cpu()=="MK22DX256VLF5")||(cpu()=="MK22DX128VLH5")||(cpu()=="MK22DX256VLH5")||(cpu()=="MK22DN512VLH5")||(cpu()=="MK22DX128VLK5")||(cpu()=="MK22DX256VLK5")||(cpu()=="MK22DN512VLK5")||(cpu()=="MK22DX128VMC5")||(cpu()=="MK22DX256VMC5")||(cpu()=="MK22DN512VMC5")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")||cpuis("MKL28Z*")||cpuis("MKL82Z*")||(cpu()=="MK40DN512ZVLL10")||(cpu()=="MK40DN512ZVLQ10")||(cpu()=="MK40DN512ZVMD10")||(cpu()=="MK40DX128ZVLQ10")||(cpu()=="MK40DX256ZVLQ10")||(cpu()=="MK40DX256ZVMD10")
|
|
eventfld.byte 0x00 7. " BTS_ERR ,Bit stuff error interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 5. " DMA_ERR ,DMA error interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 4. " BTO ,Bus turnaround timeout error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x00 3. " DFN8 ,Data received was not 8 bits in length interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 2. " CRC16 ,CRC16 error interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 1. " CRC5 ,CRC5 error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x00 0. " PID_ERR ,PID check failed interrupt" "No interrupt,Interrupt"
|
|
else
|
|
bitfld.byte 0x00 7. " BTS_ERR ,Bit stuff error interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 5. " DMA_ERR ,DMA error interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 4. " BTO ,Bus turnaround timeout error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.byte 0x00 3. " DFN8 ,Data received was not 8 bits in length interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 2. " CRC16 ,CRC16 error interrupt" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " CRC5 ,CRC5 error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.byte 0x00 0. " PID_ERR ,PID check failed interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
group.byte 0x8C++0x00
|
|
line.byte 0x00 "ERREN,Error Interrupt Enable Register"
|
|
bitfld.byte 0x00 7. " BTS_ERR_EN ,BTS_ERR interrupt enable" "Disabled,Enabled"
|
|
sif !cpuis("MKL28Z*")&&!cpuis("MKL82Z*")&&!(cpu()=="MK40DN512ZVLQ10")&&!(cpu()=="MK40DN512ZVMD10")&&!(cpu()=="MK40DX128ZVLQ10")&&!(cpu()=="MK40DX256ZVLQ10")&&!(cpu()=="MK40DX256ZVMD10")&&!(cpu()=="MK40DN512ZVLL10")
|
|
newline
|
|
bitfld.byte 0x00 6. " OWNERREN ,OWNERR interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.byte 0x00 5. " DMA_ERR_EN ,DMA_ERR interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " BTO_ERR_EN ,BTO_ERR interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 3. " DFN8_EN ,DFN8 interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " CRC16_EN ,CRC16 interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " CRC5_EN ,CRC5 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 0. " PID_ERR_EN ,PID_ERR interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40055000+0x84))&0x08)==0x08)
|
|
rgroup.byte 0x90++0x00
|
|
line.byte 0x00 "STAT,Status Register"
|
|
bitfld.byte 0x00 4.--7. " ENDP ,Endpoint address" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
|
|
bitfld.byte 0x00 3. " TX ,Transmit indicator" "Receive,Transmit"
|
|
bitfld.byte 0x00 2. " ODD ,Last buffer descriptor in odd bank of BDT" "Not odd,Odd"
|
|
else
|
|
hgroup.byte 0x90++0x00
|
|
hide.byte 0x00 "STAT,Status Register"
|
|
endif
|
|
if (((per.b(ad:0x40055000+0x94))&0x08)==0x08)
|
|
group.byte 0x94++0x00
|
|
line.byte 0x00 "CTL,Control Register"
|
|
bitfld.byte 0x00 7. " JSTATE ,Live USB differential receiver JSTATE signal" "Low,High"
|
|
bitfld.byte 0x00 6. " SE0 ,Live USB single ended zero signal" "Low,High"
|
|
bitfld.byte 0x00 5. " TOKEN_BUSY ,USB module is busy executing a USB token" "Not busy,Busy"
|
|
bitfld.byte 0x00 4. " RESET ,USB reset" "No reset,Reset"
|
|
newline
|
|
bitfld.byte 0x00 3. " HOST_MODE_EN ,Host mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RESUME ,Resume signaling enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " ODD_RST ,BDT ODD ping/pong bits reset" "No reset,Reset"
|
|
bitfld.byte 0x00 0. " USB_EN_SOF_EN ,USB enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x94++0x00
|
|
line.byte 0x00 "CTL,Control Register"
|
|
bitfld.byte 0x00 7. " JSTATE ,Live USB differential receiver JSTATE signal" "Low,High"
|
|
bitfld.byte 0x00 6. " SE0 ,Live USB single ended zero signal" "Low,High"
|
|
bitfld.byte 0x00 5. " TX_SUSPEND ,Packet transmission and reception disable" "No,Yes"
|
|
newline
|
|
bitfld.byte 0x00 3. " HOST_MODE_EN ,Host mode enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RESUME ,Resume signaling enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " ODD_RST ,BDT ODD ping/pong bits reset" "No reset,Reset"
|
|
bitfld.byte 0x00 0. " USB_EN_SOF_EN ,USB enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x98++0x00
|
|
line.byte 0x00 "ADDR,Address Register"
|
|
bitfld.byte 0x00 7. " LS_EN ,Low speed enable" "Disabled,Enabled"
|
|
hexmask.byte 0x00 0.--6. 0x01 " ADDR ,USB address"
|
|
group.byte 0x9C++0x00
|
|
line.byte 0x00 "BDTPAGE1,BDT Page Register 1"
|
|
hexmask.byte 0x00 1.--7. 0x02 " BDT_BA[15:9] ,BDT base address bits [15:9]"
|
|
group.byte 0xA0++0x00
|
|
line.byte 0x00 "FRMNUML,Frame Number Register Low"
|
|
group.byte 0xA4++0x00
|
|
line.byte 0x00 "FRMNUMH,Frame Number Register High"
|
|
bitfld.byte 0x00 0.--2. " FRM[10:8] ,Upper 3 bits of BDT system memory address" "000,001,010,011,100,101,110,111"
|
|
if (((per.b(ad:0x40055000+0x94))&0x08)==0x08)
|
|
group.byte 0xA8++0x00
|
|
line.byte 0x00 "TOKEN,Token Register"
|
|
bitfld.byte 0x00 4.--7. " TOKEN_PID ,Token type" ",OUT,,,,,,,,IN,,,,SETUP,?..."
|
|
bitfld.byte 0x00 0.--3. " TOKEN_ENDPT ,Endpoint address for the token command" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
|
|
group.byte 0xAC++0x00
|
|
line.byte 0x00 "SOFTHLD,SOF Threshold Register"
|
|
else
|
|
hgroup.byte 0xA8++0x00
|
|
hide.byte 0x00 "TOKEN,Token Register"
|
|
hgroup.byte 0xAC++0x00
|
|
hide.byte 0x00 "SOFTHLD,SOF Threshold Register"
|
|
endif
|
|
group.byte 0xB0++0x00
|
|
line.byte 0x00 "BDTPAGE2,BDT Page Register 2"
|
|
group.byte 0xB4++0x00
|
|
line.byte 0x00 "BDTPAGE3,BDT Page Register 3"
|
|
width 9.
|
|
tree "Endpoints Registers"
|
|
if (((per.b(ad:0x40055000+0x94))&0x08)==0x08)&&(((per.b(ad:0x40055000+0xC0))&0x0C)!=0x00)
|
|
group.byte 0xC0++0x00
|
|
line.byte 0x00 "ENDPT0,Endpoint Control Register 0"
|
|
bitfld.byte 0x00 7. " HOST_WO_HUB ,Host communicated to directly connected low speed device" "Not allowed,Allowed"
|
|
bitfld.byte 0x00 6. " RETRY_DIS ,Negative acknowledgement transactions retry disable" "No,Yes"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
newline
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0x40055000+0x94))&0x08)==0x00)&&(((per.b(ad:0x40055000+0xC0))&0x0C)!=0x00)
|
|
group.byte 0xC0++0x00
|
|
line.byte 0x00 "ENDPT0,Endpoint Control Register 0"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0x40055000+0x94))&0x08)==0x08)&&(((per.b(ad:0x40055000+0xC0))&0x0C)==0x00)
|
|
group.byte 0xC0++0x00
|
|
line.byte 0x00 "ENDPT0,Endpoint Control Register 0"
|
|
bitfld.byte 0x00 7. " HOST_WO_HUB ,Host communicated to directly connected low speed device" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.byte 0x00 6. " RETRY_DIS ,Negative acknowledgement transactions retry disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xC0++0x00
|
|
line.byte 0x00 "ENDPT0,Endpoint Control Register 0"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40055000+0xC4))&0x0C)!=0x00)
|
|
group.byte 0xC4++0x00
|
|
line.byte 0x00 "ENDPT1,Endpoint Control Register 1"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xC4++0x00
|
|
line.byte 0x00 "ENDPT1,Endpoint Control Register 1"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40055000+0xC8))&0x0C)!=0x00)
|
|
group.byte 0xC8++0x00
|
|
line.byte 0x00 "ENDPT2,Endpoint Control Register 2"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xC8++0x00
|
|
line.byte 0x00 "ENDPT2,Endpoint Control Register 2"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40055000+0xCC))&0x0C)!=0x00)
|
|
group.byte 0xCC++0x00
|
|
line.byte 0x00 "ENDPT3,Endpoint Control Register 3"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xCC++0x00
|
|
line.byte 0x00 "ENDPT3,Endpoint Control Register 3"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40055000+0xD0))&0x0C)!=0x00)
|
|
group.byte 0xD0++0x00
|
|
line.byte 0x00 "ENDPT4,Endpoint Control Register 4"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xD0++0x00
|
|
line.byte 0x00 "ENDPT4,Endpoint Control Register 4"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40055000+0xD4))&0x0C)!=0x00)
|
|
group.byte 0xD4++0x00
|
|
line.byte 0x00 "ENDPT5,Endpoint Control Register 5"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xD4++0x00
|
|
line.byte 0x00 "ENDPT5,Endpoint Control Register 5"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40055000+0xD8))&0x0C)!=0x00)
|
|
group.byte 0xD8++0x00
|
|
line.byte 0x00 "ENDPT6,Endpoint Control Register 6"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xD8++0x00
|
|
line.byte 0x00 "ENDPT6,Endpoint Control Register 6"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40055000+0xDC))&0x0C)!=0x00)
|
|
group.byte 0xDC++0x00
|
|
line.byte 0x00 "ENDPT7,Endpoint Control Register 7"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xDC++0x00
|
|
line.byte 0x00 "ENDPT7,Endpoint Control Register 7"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40055000+0xE0))&0x0C)!=0x00)
|
|
group.byte 0xE0++0x00
|
|
line.byte 0x00 "ENDPT8,Endpoint Control Register 8"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xE0++0x00
|
|
line.byte 0x00 "ENDPT8,Endpoint Control Register 8"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40055000+0xE4))&0x0C)!=0x00)
|
|
group.byte 0xE4++0x00
|
|
line.byte 0x00 "ENDPT9,Endpoint Control Register 9"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xE4++0x00
|
|
line.byte 0x00 "ENDPT9,Endpoint Control Register 9"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40055000+0xE8))&0x0C)!=0x00)
|
|
group.byte 0xE8++0x00
|
|
line.byte 0x00 "ENDPT10,Endpoint Control Register 10"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xE8++0x00
|
|
line.byte 0x00 "ENDPT10,Endpoint Control Register 10"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40055000+0xEC))&0x0C)!=0x00)
|
|
group.byte 0xEC++0x00
|
|
line.byte 0x00 "ENDPT11,Endpoint Control Register 11"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xEC++0x00
|
|
line.byte 0x00 "ENDPT11,Endpoint Control Register 11"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40055000+0xF0))&0x0C)!=0x00)
|
|
group.byte 0xF0++0x00
|
|
line.byte 0x00 "ENDPT12,Endpoint Control Register 12"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xF0++0x00
|
|
line.byte 0x00 "ENDPT12,Endpoint Control Register 12"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40055000+0xF4))&0x0C)!=0x00)
|
|
group.byte 0xF4++0x00
|
|
line.byte 0x00 "ENDPT13,Endpoint Control Register 13"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xF4++0x00
|
|
line.byte 0x00 "ENDPT13,Endpoint Control Register 13"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40055000+0xF8))&0x0C)!=0x00)
|
|
group.byte 0xF8++0x00
|
|
line.byte 0x00 "ENDPT14,Endpoint Control Register 14"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xF8++0x00
|
|
line.byte 0x00 "ENDPT14,Endpoint Control Register 14"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40055000+0xFC))&0x0C)!=0x00)
|
|
group.byte 0xFC++0x00
|
|
line.byte 0x00 "ENDPT15,Endpoint Control Register 15"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xFC++0x00
|
|
line.byte 0x00 "ENDPT15,Endpoint Control Register 15"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
tree.end
|
|
width 28.
|
|
newline
|
|
group.byte 0x100++0x00
|
|
line.byte 0x00 "USBCTRL,USB Control Register"
|
|
bitfld.byte 0x00 7. " SUSP ,USB transceiver suspend state" "Not suspended,Suspended"
|
|
bitfld.byte 0x00 6. " PDE ,USB transceiver weak pulldowns enable" "Disabled,Enabled"
|
|
sif cpuis("MKL28Z*")||cpuis("MKL82Z*")
|
|
newline
|
|
bitfld.byte 0x00 5. " UARTCHLS ,UART signal channel select" "UART TX/RX,UART RX/TX"
|
|
bitfld.byte 0x00 4. " UARTSEL ,Selects USB signals to be used as UART signals" "Not used,Used"
|
|
endif
|
|
rgroup.byte 0x104++0x00
|
|
line.byte 0x00 "OBSERVE,USB OTG Observe Register"
|
|
bitfld.byte 0x00 7. " DP_PU ,D+ pull up signal output observability" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DP_PD ,D+ pull down signal output observability" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " DM_PD ,D- pull down signal output observability" "Disabled,Enabled"
|
|
group.byte 0x108++0x00
|
|
line.byte 0x00 "CONTROL,USB OTG Control Register"
|
|
bitfld.byte 0x00 4. " DPPULLUP_NONOTG ,DP PULLUP in the USB OTG control" "Disabled,Enabled"
|
|
sif (cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL46Z*")||cpuis("MKL28Z*")||(cpu()=="MK40DN512ZVLL10")||(cpu()=="MK40DN512ZVLQ10")||(cpu()=="MK40DN512ZVMD10")||(cpu()=="MK40DX128ZVLQ10")||(cpu()=="MK40DX256ZVLQ10")||(cpu()=="MK40DX256ZVMD10")
|
|
group.byte 0x10C++0x00
|
|
line.byte 0x00 "USBTRC0,USB Transceiver Control Register 0"
|
|
bitfld.byte 0x00 7. " USBRESET ,USB_OTG module reset" "No reset,Reset"
|
|
bitfld.byte 0x00 5. " USBRESMEN ,Asynchronous resume interrupt enable" "Disabled,Enabled"
|
|
sif cpuis("MKL28Z*")||cpuis("MKL82Z*")
|
|
newline
|
|
rbitfld.byte 0x00 4. " VFEDG_DET ,VREGIN falling edge interrupt detect" "Not detected,Detected"
|
|
rbitfld.byte 0x00 3. " VREDG_DET ,VREGIN rising edge interrupt detect" "Not detected,Detected"
|
|
rbitfld.byte 0x00 2. " USB_CLK_RECOVERY_INT ,Combined USB clock recovery interrupt status" "Not detected,Detected"
|
|
endif
|
|
newline
|
|
rbitfld.byte 0x00 1. " SYNC_DET ,Synchronous USB interrupt detect" "Not detected,Detected"
|
|
rbitfld.byte 0x00 0. " USB_RESUME_INT ,USB asynchronous interrupt" "No interrupt,Interrupt"
|
|
else
|
|
group.byte 0x10C++0x00
|
|
line.byte 0x00 "USBTRC0,USB Transceiver Control Register 0"
|
|
bitfld.byte 0x00 7. " USBRESET ,USB_OTG module reset" "No reset,Reset"
|
|
bitfld.byte 0x00 5. " USBRESMEN ,Asynchronous resume interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SYNC_DET ,Synchronous USB interrupt detect" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " USB_RESUME_INT ,USB asynchronous interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
sif (cpuis("K70"))||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL46Z*")||(cpu()=="MK21DX128VLK5")||(cpu()=="MK21DX256VLK5")||(cpu()=="MK21DN512VLK5")||(cpu()=="MK21DX128VMC5")||(cpu()=="MK21DX256VMC5")||(cpu()=="MK21DN512VMC5")||(cpu()=="MK22DX128VLF5")||(cpu()=="MK22DX256VLF5")||(cpu()=="MK22DX128VLH5")||(cpu()=="MK22DX256VLH5")||(cpu()=="MK22DN512VLH5")||(cpu()=="MK22DX128VLK5")||(cpu()=="MK22DX256VLK5")||(cpu()=="MK22DN512VLK5")||(cpu()=="MK22DX128VMC5")||(cpu()=="MK22DX256VMC5")||(cpu()=="MK22DN512VMC5")||(cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")
|
|
group.byte 0x114++0x00
|
|
line.byte 0x00 "USBFRMADJUST,Frame Adjust Register"
|
|
elif cpuis("MKL28Z*")||cpuis("MKL82Z*")
|
|
group.byte 0x114++0x00
|
|
line.byte 0x00 "USBFRMADJUST,Frame Adjust Register"
|
|
sif cpuis("MKL82Z*")
|
|
group.byte 0x124++0x01
|
|
line.byte 0x00 "KEEP_ALIVE_CTRL,Keep Alive Mode Control"
|
|
rbitfld.byte 0x00 7. " WAKE_INT_STS ,Wakeup interrupt status" "Not received,Received"
|
|
newline
|
|
bitfld.byte 0x00 4. " WAKE_INT_EN ,Wakeup interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " WAKE_REQ_EN ,Wakeup request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " OWN_OVERRD_EN ,OWN override enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 0. " KEEP_ALIVE_EN ,Keep alive enabled" "Disabled,Enabled"
|
|
line.byte 0x01 "KEEP_ALIVE_WKCTRL,Keep Alive Mode Wakeup Control"
|
|
rbitfld.byte 0x01 4.--7. " WAKE_ENDPT ,Wakeup endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x01 0.--3. " WAKE_ON_THIS ,Wakeup usb" ",OUT/SETUP,,,,,,,,,,,,SETUP,?..."
|
|
endif
|
|
if (((per.b(ad:0x40055000+0x94))&0x08)==0x08)
|
|
group.byte 0x12C++0x00
|
|
line.byte 0x00 "MISCCTRL,Miscellaneous Control Register"
|
|
bitfld.byte 0x00 4. " VFEDG_EN ,VREGIN falling edge interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " VREDG_EN ,VREGIN rising edge interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SOFBUSSET ,SOF_TOK interrupt generation mode select" "SOF threshold value,Counter reaches 0"
|
|
bitfld.byte 0x00 0. " SOFDYNTHLD ,Dynamic SOF threshold compare mode" "Byte time,8 byte times"
|
|
else
|
|
group.byte 0x12C++0x00
|
|
line.byte 0x00 "MISCCTRL,Miscellaneous Control Register"
|
|
bitfld.byte 0x00 4. " VFEDG_EN ,VREGIN falling edge interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " VREDG_EN ,VREGIN rising edge interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " OWNERRISODIS ,OWN error detect for ISO IN / ISO OUT disable" "No,Yes"
|
|
endif
|
|
sif cpuis("MKL82Z*")
|
|
if ((((per.b(ad:0x40055000+0x94))&0x8)!=0x8)&&(((per.b(ad:0x40055000+0x12C))&0x80)==0x80))
|
|
group.byte 0x130++0x00
|
|
line.byte 0x00 "USB_STALL_IL_DIS,Peripheral Mode Stall Disable For Endpoints 7 To 0 In IN Direction"
|
|
bitfld.byte 0x00 7. " STALL_I_DIS7 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 6. " STALL_I_DIS6 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 5. " STALL_I_DIS5 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 4. " STALL_I_DIS4 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " STALL_I_DIS3 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 2. " STALL_I_DIS2 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 1. " STALL_I_DIS1 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 0. " STALL_I_DIS0 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
group.byte 0x134++0x00
|
|
line.byte 0x00 "USB_STALL_IH_DIS,Peripheral Mode Stall Disable For Endpoints 15 To 8 In IN Direction"
|
|
bitfld.byte 0x00 7. " STALL_I_DIS15 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 6. " STALL_I_DIS14 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 5. " STALL_I_DIS13 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 4. " STALL_I_DIS12 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " STALL_I_DIS11 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 2. " STALL_I_DIS10 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 1. " STALL_I_DIS9 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 0. " STALL_I_DIS8 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
group.byte 0x138++0x00
|
|
line.byte 0x00 "USB_STALL_OL_DIS,Peripheral Mode Stall Disable For Endpoints 7 To 0 In OUT Direction"
|
|
bitfld.byte 0x00 7. " STALL_O_DIS7 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 6. " STALL_O_DIS6 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 5. " STALL_O_DIS5 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 4. " STALL_O_DIS4 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " STALL_O_DIS3 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 2. " STALL_O_DIS2 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 1. " STALL_O_DIS1 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 0. " STALL_O_DIS0 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
group.byte 0x13C++0x00
|
|
line.byte 0x00 "USB_STALL_OH_DIS,Peripheral Mode Stall Disable For Endpoints 15 To 0 In OUT Direction"
|
|
bitfld.byte 0x00 7. " STALL_O_DIS15 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 6. " STALL_O_DIS14 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 5. " STALL_O_DIS13 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 4. " STALL_O_DIS12 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " STALL_O_DIS11 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 2. " STALL_O_DIS10 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 1. " STALL_O_DIS9 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
bitfld.byte 0x00 0. " STALL_O_DIS8 ,Dynamic SOF threshold compare mode" "No,Yes"
|
|
endif
|
|
endif
|
|
group.byte 0x140++0x00
|
|
line.byte 0x00 "USB_CLK_RECOVER_CTRL,USB Clock Recovery Control Register"
|
|
bitfld.byte 0x00 7. " CLOCK_RECOVER_EN ,Crystal-less USB enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RESET_RESUME_ROUGH_EN ,Reset/resume to rough phase enable" "Resume,Reset"
|
|
newline
|
|
bitfld.byte 0x00 5. " RESTART_IFRTRIM_EN ,Restart from IFR trim value" "No effect,Restart"
|
|
group.byte 0x144++0x00
|
|
line.byte 0x00 "USB_CLK_RECOVER_IRC_EN,IRC48M Oscillator Enable Register"
|
|
group.byte 0x154++0x00
|
|
line.byte 0x00 "USB_CLK_RECOVER_INT_EN,Clock Recovery Combined Interrupt Enable Register"
|
|
bitfld.byte 0x00 4. " OVF_ERROR_EN ,Determines whether OVF_ERROR condition signal is used in generation of USB_CLK_RECOVERY_INT" "Disabled,Enabled"
|
|
hgroup.byte 0x15C++0x00
|
|
hide.byte 0x00 "USB_CLK_RECOVER_INT_STATUS,Clock Recovery Separated Interrupt Status Register"
|
|
in
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif cpuis("MKL27Z*")||cpuis("MKL43Z*")
|
|
tree "USB-FS (Universal Serial Bus FS Subsystem)"
|
|
base ad:0x40072000
|
|
width 11.
|
|
rgroup.byte 0x00++0x00
|
|
line.byte 0x00 "PERID,Peripheral ID Register"
|
|
hexmask.byte 0x00 0.--5. 1. " ID ,Peripheral identification"
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "IDCOMP,Peripheral ID Complement Register"
|
|
hexmask.byte 0x00 0.--5. 1. " NID ,Ones complement of peripheral identification"
|
|
rgroup.byte 0x08++0x00
|
|
line.byte 0x00 "REV,Peripheral Revision Register"
|
|
rgroup.byte 0x0C++0x00
|
|
line.byte 0x00 "ADDINFO,Peripheral Additional Info Register"
|
|
bitfld.byte 0x00 0. " IEHOST ,Host mode enable" "Disabled,Enabled"
|
|
sif !cpuis("MKL27Z32*")&&!cpuis("MKL27Z64*")
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "OTGCTL,OTG Control Register"
|
|
bitfld.byte 0x00 7. " DP_HIGH ,D+ data line pullup resistor enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x80++0x00
|
|
line.byte 0x00 "ISTAT,Interrupt Status Register"
|
|
eventfld.byte 0x00 7. " STALL ,Stall interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 5. " RESUME ,Signal remote wake-up signaling interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 4. " SLEEP ,Idle on USB bus (For 3ms) interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x00 3. " TOKDNE ,Token completed interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 2. " SOF_TOK ,Start of frame token interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 1. " ERROR ,Error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x00 0. " USB_RST ,USB reset interrupt" "No interrupt,Interrupt"
|
|
group.byte 0x84++0x00
|
|
line.byte 0x00 "INTEN,Interrupt Enable Register"
|
|
bitfld.byte 0x00 7. " STALL_EN ,STALL interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " RESUME_EN ,RESUME interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " SLEEP_EN ,SLEEP interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 3. " TOK_DNE_EN ,TOK_DNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " SOF_TOK_EN ,SOF_TOK interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " ERROR_EN ,ERROR interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 0. " USB_RST_EN ,USB_RST interrupt enable" "Disabled,Enabled"
|
|
if ((per.b(ad:0x40072000+0x94)&0x08)==0x08)
|
|
group.byte 0x88++0x00
|
|
line.byte 0x00 "ERRSTAT,Error Interrupt Status Register"
|
|
eventfld.byte 0x00 7. " BTS_ERR ,Bit stuff error interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 5. " DMA_ERR ,DMA error interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 4. " BTOERR ,Bus turnaround timeout error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x00 3. " DFN8 ,Data received was not 8 bits in length interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 2. " CRC16 ,CRC16 error interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 1. " EOF ,End of frame error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x00 0. " PID_ERR ,PID check failed interrupt" "No interrupt,Interrupt"
|
|
group.byte 0x8C++0x00
|
|
line.byte 0x00 "ERREN,Error Interrupt Enable Register"
|
|
bitfld.byte 0x00 7. " BTS_ERR_EN ,BTS_ERR interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DMA_ERR_EN ,DMA_ERR interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " BTO_ERR_EN ,BTO_ERR interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 3. " DFN8_EN ,DFN8 interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " CRC16_EN ,CRC16 interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EOF ,End of frame interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 0. " PID_ERR_EN ,PID_ERR interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x88++0x00
|
|
line.byte 0x00 "ERRSTAT,Error Interrupt Status Register"
|
|
eventfld.byte 0x00 7. " BTS_ERR ,Bit stuff error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
sif cpuis("K32W0?2S1M*")
|
|
eventfld.byte 0x00 6. " OWNERR ,OWNERR" "No interrupt,Interrupt"
|
|
newline
|
|
endif
|
|
eventfld.byte 0x00 5. " DMA_ERR ,DMA error interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 4. " BTOERR ,Bus turnaround timeout error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x00 3. " DFN8 ,Data received was not 8 bits in length interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 2. " CRC16 ,CRC16 error interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x00 1. " CRC5 ,CRC5 error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x00 0. " PID_ERR ,PID check failed interrupt" "No interrupt,Interrupt"
|
|
group.byte 0x8C++0x00
|
|
line.byte 0x00 "ERREN,Error Interrupt Enable Register"
|
|
bitfld.byte 0x00 7. " BTS_ERR_EN ,BTS_ERR interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.byte 0x00 6. " OWNERREN ,OWNERR interrupt enable" "No interrupt,Interrupt"
|
|
newline
|
|
endif
|
|
bitfld.byte 0x00 5. " DMA_ERR_EN ,DMA_ERR interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " BTO_ERR_EN ,BTO_ERR interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 3. " DFN8_EN ,DFN8 interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " CRC16_EN ,CRC16 interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " CRC5 ,CRC5 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 0. " PID_ERR_EN ,PID_ERR interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0x84)&0x08)==0x08)
|
|
rgroup.byte 0x90++0x00
|
|
line.byte 0x00 "STAT,Status Register"
|
|
bitfld.byte 0x00 4.--7. " ENDP ,Endpoint address" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
|
|
bitfld.byte 0x00 3. " TX ,Transmit indicator" "Receive,Transmit"
|
|
bitfld.byte 0x00 2. " ODD ,Last buffer descriptor in odd bank of BDT" "Not odd,Odd"
|
|
else
|
|
hgroup.byte 0x90++0x00
|
|
hide.byte 0x00 "STAT,Status Register"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0x94)&0x08)==0x08)
|
|
group.byte 0x94++0x00
|
|
line.byte 0x00 "CTL,Control Register"
|
|
bitfld.byte 0x00 7. " JSTATE ,Live USB differential receiver JSTATE signal" "Low,High"
|
|
bitfld.byte 0x00 6. " SE0 ,Live USB single ended zero signal" "Low,High"
|
|
bitfld.byte 0x00 5. " TOKEN_BUSY ,USB module is busy executing a USB token" "Not busy,Busy"
|
|
newline
|
|
bitfld.byte 0x00 3. " HOSTMODEEN ,Host mode enable" "Device mode,Host mode"
|
|
bitfld.byte 0x00 2. " RESUME ,Resume" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " ODD_RST ,BDT ODD ping/pong bits reset" "No reset,Reset"
|
|
newline
|
|
bitfld.byte 0x00 0. " USB_EN_SOF_EN ,USB enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x94++0x00
|
|
line.byte 0x00 "CTL,Control Register"
|
|
bitfld.byte 0x00 7. " JSTATE ,Live USB differential receiver JSTATE signal" "Low,High"
|
|
bitfld.byte 0x00 6. " SE0 ,Live USB single ended zero signal" "Low,High"
|
|
bitfld.byte 0x00 5. " TX_SUSPEND ,Packet transmission and reception disable" "No,Yes"
|
|
newline
|
|
bitfld.byte 0x00 3. " HOSTMODEEN ,Host mode enable" "Device mode,Host mode"
|
|
bitfld.byte 0x00 2. " RESUME ,Resume" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " ODD_RST ,BDT ODD ping/pong bits reset" "No reset,Reset"
|
|
newline
|
|
bitfld.byte 0x00 0. " USB_EN_SOF_EN ,USB enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x98++0x00
|
|
line.byte 0x00 "ADDR,Address Register"
|
|
hexmask.byte 0x00 0.--6. 0x01 " ADDR ,USB address"
|
|
group.byte 0x9C++0x00
|
|
line.byte 0x00 "BDTPAGE_1,BDT Page Register 1"
|
|
hexmask.byte 0x00 1.--7. 0x02 " BDTBA ,BDT base address"
|
|
group.byte 0xA0++0x00
|
|
line.byte 0x00 "FRMNUML,Frame Number Register Low"
|
|
group.byte 0xA4++0x00
|
|
line.byte 0x00 "FRMNUMH,Frame Number Register High"
|
|
hexmask.byte 0x00 0.--2. 1. " FRM ,Frame number"
|
|
group.byte 0xB0++0x00
|
|
line.byte 0x00 "BDTPAGE_2,BDT Page Register 2"
|
|
group.byte 0xB4++0x00
|
|
line.byte 0x00 "BDTPAGE_3,BDT Page Register 3"
|
|
width 10.
|
|
tree "Endpoints Registers"
|
|
if ((per.b(ad:0x40072000+0xC0)&0x0C)!=0x00)
|
|
group.byte 0xC0++0x00
|
|
line.byte 0x00 "ENDPT_0,Endpoint Control Register 0"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xC0++0x00
|
|
line.byte 0x00 "ENDPT_0,Endpoint Control Register 0"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
newline
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0xC4)&0x0C)!=0x00)
|
|
group.byte 0xC4++0x00
|
|
line.byte 0x00 "ENDPT_1,Endpoint Control Register 1"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xC4++0x00
|
|
line.byte 0x00 "ENDPT_1,Endpoint Control Register 1"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
newline
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0xC8)&0x0C)!=0x00)
|
|
group.byte 0xC8++0x00
|
|
line.byte 0x00 "ENDPT_2,Endpoint Control Register 2"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xC8++0x00
|
|
line.byte 0x00 "ENDPT_2,Endpoint Control Register 2"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
newline
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0xCC)&0x0C)!=0x00)
|
|
group.byte 0xCC++0x00
|
|
line.byte 0x00 "ENDPT_3,Endpoint Control Register 3"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xCC++0x00
|
|
line.byte 0x00 "ENDPT_3,Endpoint Control Register 3"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
newline
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0xD0)&0x0C)!=0x00)
|
|
group.byte 0xD0++0x00
|
|
line.byte 0x00 "ENDPT_4,Endpoint Control Register 4"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xD0++0x00
|
|
line.byte 0x00 "ENDPT_4,Endpoint Control Register 4"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
newline
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0xD4)&0x0C)!=0x00)
|
|
group.byte 0xD4++0x00
|
|
line.byte 0x00 "ENDPT_5,Endpoint Control Register 5"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xD4++0x00
|
|
line.byte 0x00 "ENDPT_5,Endpoint Control Register 5"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
newline
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0xD8)&0x0C)!=0x00)
|
|
group.byte 0xD8++0x00
|
|
line.byte 0x00 "ENDPT_6,Endpoint Control Register 6"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xD8++0x00
|
|
line.byte 0x00 "ENDPT_6,Endpoint Control Register 6"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
newline
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0xDC)&0x0C)!=0x00)
|
|
group.byte 0xDC++0x00
|
|
line.byte 0x00 "ENDPT_7,Endpoint Control Register 7"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xDC++0x00
|
|
line.byte 0x00 "ENDPT_7,Endpoint Control Register 7"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
newline
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0xE0)&0x0C)!=0x00)
|
|
group.byte 0xE0++0x00
|
|
line.byte 0x00 "ENDPT_8,Endpoint Control Register 8"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xE0++0x00
|
|
line.byte 0x00 "ENDPT_8,Endpoint Control Register 8"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
newline
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0xE4)&0x0C)!=0x00)
|
|
group.byte 0xE4++0x00
|
|
line.byte 0x00 "ENDPT_9,Endpoint Control Register 9"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xE4++0x00
|
|
line.byte 0x00 "ENDPT_9,Endpoint Control Register 9"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
newline
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0xE8)&0x0C)!=0x00)
|
|
group.byte 0xE8++0x00
|
|
line.byte 0x00 "ENDPT_10,Endpoint Control Register 10"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xE8++0x00
|
|
line.byte 0x00 "ENDPT_10,Endpoint Control Register 10"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
newline
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0xEC)&0x0C)!=0x00)
|
|
group.byte 0xEC++0x00
|
|
line.byte 0x00 "ENDPT_11,Endpoint Control Register 11"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xEC++0x00
|
|
line.byte 0x00 "ENDPT_11,Endpoint Control Register 11"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
newline
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0xF0)&0x0C)!=0x00)
|
|
group.byte 0xF0++0x00
|
|
line.byte 0x00 "ENDPT_12,Endpoint Control Register 12"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xF0++0x00
|
|
line.byte 0x00 "ENDPT_12,Endpoint Control Register 12"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
newline
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0xF4)&0x0C)!=0x00)
|
|
group.byte 0xF4++0x00
|
|
line.byte 0x00 "ENDPT_13,Endpoint Control Register 13"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xF4++0x00
|
|
line.byte 0x00 "ENDPT_13,Endpoint Control Register 13"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
newline
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0xF8)&0x0C)!=0x00)
|
|
group.byte 0xF8++0x00
|
|
line.byte 0x00 "ENDPT_14,Endpoint Control Register 14"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xF8++0x00
|
|
line.byte 0x00 "ENDPT_14,Endpoint Control Register 14"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
newline
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0xFC)&0x0C)!=0x00)
|
|
group.byte 0xFC++0x00
|
|
line.byte 0x00 "ENDPT_15,Endpoint Control Register 15"
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0xFC++0x00
|
|
line.byte 0x00 "ENDPT_15,Endpoint Control Register 15"
|
|
bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (Setup) transfers disable" "No,Yes"
|
|
newline
|
|
bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " EP_STALL ,Endpoint call" "Not called,Called"
|
|
bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled"
|
|
endif
|
|
tree.end
|
|
width 28.
|
|
newline
|
|
group.byte 0x100++0x00
|
|
line.byte 0x00 "USBCTRL,USB Control Register"
|
|
bitfld.byte 0x00 7. " SUSP ,USB transceiver suspend state" "Not suspended,Suspended"
|
|
bitfld.byte 0x00 6. " PDE ,USB transceiver weak pulldowns enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.byte 0x00 5. " UARTCHLS ,UART signal channel select" "TX/RX,RX/TX"
|
|
bitfld.byte 0x00 4. " UARTSEL ,UART select" "Not used,Used"
|
|
endif
|
|
rgroup.byte 0x104++0x00
|
|
line.byte 0x00 "OBSERVE,USB OTG Observe Register"
|
|
bitfld.byte 0x00 7. " DP_PU ,D+ pull up signal output observability" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DP_PD ,D+ pull down signal output observability" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " DM_PD ,D- pull down signal output observability" "Disabled,Enabled"
|
|
group.byte 0x108++0x00
|
|
line.byte 0x00 "CONTROL,USB OTG Control Register"
|
|
bitfld.byte 0x00 4. " DPPULLUP_NONOTG ,DP pull up in the USB OTG control" "Disabled,Enabled"
|
|
group.byte 0x10C++0x00
|
|
line.byte 0x00 "USBTRC_0,USB Transceiver Control Register 0"
|
|
bitfld.byte 0x00 7. " USBRESET ,USB reset" "No reset,Reset"
|
|
newline
|
|
sif cpuis("K32W0?2S1M*")
|
|
rbitfld.byte 0x00 6. " VREGIN_STS ,Indicates the VREGIN status" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.byte 0x00 5. " USBRESMEN ,Asynchronous resume interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("K32W0?2S1M*")
|
|
rbitfld.byte 0x00 4. " VFEDG_DET ,VREGIN falling edge interrupt detect" "Not detected,Detected"
|
|
rbitfld.byte 0x00 3. " VREDG_DET ,VREGIN rising edge interrupt detect" "Not detected,Detected"
|
|
newline
|
|
endif
|
|
rbitfld.byte 0x00 2. " USB_CLK_RECOVERY_INT ,Combined USB clock recovery interrupt status" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.byte 0x00 1. " SYNC_DET ,Synchronous USB interrupt detect" "Not detected,Detected"
|
|
rbitfld.byte 0x00 0. " USB_RESUME_INT ,USB asynchronous interrupt" "No interrupt,Interrupt"
|
|
sif !cpuis("K32W0?2S1M*")
|
|
group.byte 0x114++0x00
|
|
line.byte 0x00 "USBFRMADJUST,Frame Adjust Register"
|
|
endif
|
|
sif cpuis("MKL27Z32*")||cpuis("MKL27Z64*")||cpuis("K32W0?2S1M*")
|
|
group.byte 0x124++0x00
|
|
line.byte 0x00 "USB_KEEP_ALIVE_CTRL,Keep Alive Mode Control Register"
|
|
rbitfld.byte 0x00 7. " WAKE_INT_STS ,Wakeup interrupt status" "No interrupt,Interrupt"
|
|
newline
|
|
sif cpuis("K32W0?2S1M*")
|
|
rbitfld.byte 0x00 6. " KEEP_ALIVE_STS ,Keep alive status" "Off,On"
|
|
newline
|
|
endif
|
|
bitfld.byte 0x00 4. " WAKE_INT_EN ,Wakeup interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.byte 0x00 3. " WAKE_REQ_EN ,WAKE_REQ_EN" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.byte 0x00 3. " AHB_DLY_EN ,First USB AHB transfer delay" "Not delayed,Delayed"
|
|
newline
|
|
endif
|
|
bitfld.byte 0x00 2. " STOP_ACK_DLY_EN ,Enter and exit KEEP_ALIVE mode select" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " OWN_OVERRD_EN ,OWN bit of current BD forcing enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " KEEP_ALIVE_EN ,Global enable for USB_KEEP_ALIVE mode" "Disabled,Enabled"
|
|
group.byte 0x128++0x00
|
|
line.byte 0x00 "USB_KEEP_ALIVE_WKCTRL,Keep Alive Mode Wakeup Control Register"
|
|
rbitfld.byte 0x00 4.--7. " WAKE_ENDPT ,Wakeup endpoint select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " WAKE_ON_THIS ,Wakeup USB select token" ",Out/setup,,,,,,,,,,,,Setup,?..."
|
|
endif
|
|
sif cpuis("K32W0?2S1M*")
|
|
if ((per.b(ad:0x40072000+0x94)&0x08)==0x08)
|
|
group.byte 0x12C++0x00
|
|
line.byte 0x00 "MISCCTRL,Miscellaneous Control Register"
|
|
bitfld.byte 0x00 7. " STL_ADJ_EN ,USB peripheral mode stall adjust enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " VFEDG_EN ,VREGIN falling edge interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " VREDG_EN ,VREGIN rising edge interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 2. " OWNERRISODIS ,OWN error detect for ISO IN/ISO OUT disable" "No,Yes"
|
|
bitfld.byte 0x00 1. " SOFBUSSET ,SOF_TOK interrupt generation mode select" "According,When"
|
|
bitfld.byte 0x00 0. " SOFDYNTHLD ,Dynamic SOF threshold compare mode" "Not reached,Reached"
|
|
else
|
|
group.byte 0x12C++0x00
|
|
line.byte 0x00 "MISCCTRL,Miscellaneous Control Register"
|
|
bitfld.byte 0x00 4. " VFEDG_EN ,VREGIN falling edge interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " VREDG_EN ,VREGIN rising edge interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0x40072000+0x94)&0x08)==0x08)&&((per.b(ad:0x40072000+0x12C)&0x80)==0x80)
|
|
group.byte 0x130++0x00
|
|
line.byte 0x00 "STALL_IL_DIS,Peripheral Mode Stall Disable For Endpoints 7 To 0 In IN Direction"
|
|
bitfld.byte 0x00 7. " STALL_I_DIS7 ,Disable endpoint 7 IN direction" "No,Yes"
|
|
bitfld.byte 0x00 6. " STALL_I_DIS6 ,Disable endpoint 6 IN direction" "No,Yes"
|
|
bitfld.byte 0x00 5. " STALL_I_DIS5 ,Disable endpoint 5 IN direction" "No,Yes"
|
|
newline
|
|
bitfld.byte 0x00 4. " STALL_I_DIS4 ,Disable endpoint 4 IN direction" "No,Yes"
|
|
bitfld.byte 0x00 3. " STALL_I_DIS3 ,Disable endpoint 3 IN direction" "No,Yes"
|
|
bitfld.byte 0x00 2. " STALL_I_DIS2 ,Disable endpoint 2 IN direction" "No,Yes"
|
|
newline
|
|
bitfld.byte 0x00 1. " STALL_I_DIS1 ,Disable endpoint 1 IN direction" "No,Yes"
|
|
bitfld.byte 0x00 0. " STALL_I_DIS0 ,Disable endpoint 0 IN direction" "No,Yes"
|
|
group.byte 0x134++0x00
|
|
line.byte 0x00 "STALL_IH_DIS,Peripheral Mode Stall Disable For Endpoints 15 To 8 In IN Direction"
|
|
bitfld.byte 0x00 7. " STALL_I_DIS7 ,Disable endpoint 7 IN direction" "No,Yes"
|
|
bitfld.byte 0x00 6. " STALL_I_DIS6 ,Disable endpoint 6 IN direction" "No,Yes"
|
|
bitfld.byte 0x00 5. " STALL_I_DIS5 ,Disable endpoint 5 IN direction" "No,Yes"
|
|
newline
|
|
bitfld.byte 0x00 4. " STALL_I_DIS4 ,Disable endpoint 4 IN direction" "No,Yes"
|
|
bitfld.byte 0x00 3. " STALL_I_DIS3 ,Disable endpoint 3 IN direction" "No,Yes"
|
|
bitfld.byte 0x00 2. " STALL_I_DIS2 ,Disable endpoint 2 IN direction" "No,Yes"
|
|
newline
|
|
bitfld.byte 0x00 1. " STALL_I_DIS1 ,Disable endpoint 1 IN direction" "No,Yes"
|
|
bitfld.byte 0x00 0. " STALL_I_DIS0 ,Disable endpoint 0 IN direction" "No,Yes"
|
|
group.byte 0x138++0x00
|
|
line.byte 0x00 "STALL_OL_DIS,Peripheral Mode Stall Disable For Endpoints 7 To 0 In OUT Direction"
|
|
bitfld.byte 0x00 7. " STALL_I_DIS7 ,Disable endpoint 7 IN direction" "No,Yes"
|
|
bitfld.byte 0x00 6. " STALL_I_DIS6 ,Disable endpoint 6 IN direction" "No,Yes"
|
|
bitfld.byte 0x00 5. " STALL_I_DIS5 ,Disable endpoint 5 IN direction" "No,Yes"
|
|
newline
|
|
bitfld.byte 0x00 4. " STALL_I_DIS4 ,Disable endpoint 4 IN direction" "No,Yes"
|
|
bitfld.byte 0x00 3. " STALL_I_DIS3 ,Disable endpoint 3 IN direction" "No,Yes"
|
|
bitfld.byte 0x00 2. " STALL_I_DIS2 ,Disable endpoint 2 IN direction" "No,Yes"
|
|
newline
|
|
bitfld.byte 0x00 1. " STALL_I_DIS1 ,Disable endpoint 1 IN direction" "No,Yes"
|
|
bitfld.byte 0x00 0. " STALL_I_DIS0 ,Disable endpoint 0 IN direction" "No,Yes"
|
|
group.byte 0x13C++0x00
|
|
line.byte 0x00 "STALL_OH_DIS,Peripheral Mode Stall Disable For Endpoints 15 To 8 In OUT Direction"
|
|
bitfld.byte 0x00 7. " STALL_I_DIS7 ,Disable endpoint 7 IN direction" "No,Yes"
|
|
bitfld.byte 0x00 6. " STALL_I_DIS6 ,Disable endpoint 6 IN direction" "No,Yes"
|
|
bitfld.byte 0x00 5. " STALL_I_DIS5 ,Disable endpoint 5 IN direction" "No,Yes"
|
|
newline
|
|
bitfld.byte 0x00 4. " STALL_I_DIS4 ,Disable endpoint 4 IN direction" "No,Yes"
|
|
bitfld.byte 0x00 3. " STALL_I_DIS3 ,Disable endpoint 3 IN direction" "No,Yes"
|
|
bitfld.byte 0x00 2. " STALL_I_DIS2 ,Disable endpoint 2 IN direction" "No,Yes"
|
|
newline
|
|
bitfld.byte 0x00 1. " STALL_I_DIS1 ,Disable endpoint 1 IN direction" "No,Yes"
|
|
bitfld.byte 0x00 0. " STALL_I_DIS0 ,Disable endpoint 0 IN direction" "No,Yes"
|
|
else
|
|
hgroup.byte 0x130++0x00
|
|
hide.byte 0x00 "STALL_IL_DIS,Peripheral Mode Stall Disable For Endpoints 7 To 0 In IN Direction"
|
|
hgroup.byte 0x134++0x00
|
|
hide.byte 0x00 "STALL_IH_DIS,Peripheral Mode Stall Disable For Endpoints 15 To 8 In IN Direction"
|
|
hgroup.byte 0x138++0x00
|
|
hide.byte 0x00 "STALL_OL_DIS,Peripheral Mode Stall Disable For Endpoints 7 To 0 In OUT Direction"
|
|
hgroup.byte 0x13C++0x00
|
|
hide.byte 0x00 "STALL_OH_DIS,Peripheral Mode Stall Disable For Endpoints 15 To 8 In OUT Direction"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40072000+0x144)&0x02))==0x02)
|
|
group.byte 0x140++0x00
|
|
line.byte 0x00 "USB_CLK_RECOVER_CTRL,USB Clock Recovery Control Register"
|
|
bitfld.byte 0x00 7. " CLOCK_RECOVER_EN ,Crystal-less USB enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RESET_RESUME_ROUGH_EN ,Reset/resume to rough phase enable" "Always works,Back to rough"
|
|
bitfld.byte 0x00 5. " RESTART_IFRTRIM_EN ,Restart from IFR trim value" "Always works,From IFR"
|
|
else
|
|
hgroup.byte 0x140++0x00
|
|
hide.byte 0x00 "USB_CLK_RECOVER_CTRL,USB Clock Recovery Control Register"
|
|
endif
|
|
group.byte 0x144++0x00
|
|
line.byte 0x00 "USB_CLK_RECOVER_IRC_EN,IRC48M Oscillator Enable Register"
|
|
bitfld.byte 0x00 1. " IRC_EN ,IRC48MHZ enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("K32W0?2S1M*")
|
|
bitfld.byte 0x00 0. " REG_EN ,Regulator enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x154++0x00
|
|
line.byte 0x00 "USB_CLK_RECOVER_INT_EN,Clock Recovery Combined Interrupt Enable Register"
|
|
bitfld.byte 0x00 4. " OVF_ERROR_EN ,Determines whether OVF_ERROR condition signal is used in generation of USB_CLK_RECOVERY_INT" "Disabled,Enabled"
|
|
group.byte 0x15C++0x00
|
|
line.byte 0x00 "USB_CLK_RECOVER_INT_STATUS,Clock Recovery Separated Interrupt Status Register"
|
|
eventfld.byte 0x00 4. " OVF_ERROR ,OVF_ERROR interrupt" "No interrupt,Interrupt"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif cpuis("MKL82*")
|
|
tree.open "SPI (Serial Peripheral Interface)"
|
|
tree "SPI0"
|
|
base ad:0x4002C000
|
|
width 19.
|
|
sif cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK40DN512ZVLL10")
|
|
if (((per.l(ad:0x4002C000+0x0C))&0x2000000)==0x0000000)&&(((per.l(ad:0x4002C000+0x10))&0x2000000)==0x0000000)
|
|
if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000)
|
|
if ((per.l(ad:0x4002C000)&0x4000)==0x4000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,DSPI0 Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..."
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High"
|
|
bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
sif cpuis("MK40DN512ZVLL10")
|
|
bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
newline
|
|
rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,DSPI0 Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..."
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High"
|
|
bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
sif cpuis("MK40DN512ZVLL10")
|
|
bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x4002C000)&0x4000)==0x4000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,DSPI0 Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..."
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..."
|
|
bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,DSPI0 Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..."
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..."
|
|
bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped"
|
|
endif
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000)
|
|
if ((per.l(ad:0x4002C000)&0x4000)==0x4000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,DSPI0 Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..."
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High"
|
|
bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
sif cpuis("MK40DN512ZVLL10")
|
|
bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,DSPI0 Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..."
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High"
|
|
bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
sif cpuis("MK40DN512ZVLL10")
|
|
bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
newline
|
|
rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x4002C000)&0x4000)==0x4000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,DSPI0 Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..."
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,DSPI0 Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..."
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped"
|
|
endif
|
|
endif
|
|
endif
|
|
elif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")
|
|
if (((per.l(ad:0x4002C000+0x2C))&0x40000000)==0x40000000)
|
|
if (((per.l(ad:0x4002C000+0x0C))&0x2000000)==0x0000000)&&(((per.l(ad:0x4002C000+0x10))&0x2000000)==0x0000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,DSPI0 Module Configuration Register"
|
|
rbitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
rbitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..."
|
|
rbitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted"
|
|
newline
|
|
rbitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")
|
|
rbitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
rbitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512VMC10R")
|
|
rbitfld.long 0x00 20. " PCSIS[4] ,Peripheral chip select 4 inactive state" "Low,High"
|
|
rbitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High"
|
|
rbitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High"
|
|
rbitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High"
|
|
newline
|
|
rbitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High"
|
|
newline
|
|
else
|
|
rbitfld.long 0x00 21. " PCSIS[5] ,Peripheral chip select 5 inactive state" "Low,High"
|
|
rbitfld.long 0x00 20. " [4] ,Peripheral chip select 4 inactive state" "Low,High"
|
|
rbitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High"
|
|
rbitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High"
|
|
newline
|
|
rbitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High"
|
|
rbitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High"
|
|
newline
|
|
endif
|
|
newline
|
|
rbitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
newline
|
|
rbitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear"
|
|
rbitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear"
|
|
rbitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 clocks,1 clock,2 clocks,?..."
|
|
bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,DSPI0 Module Configuration Register"
|
|
rbitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
rbitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..."
|
|
rbitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted"
|
|
newline
|
|
rbitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")
|
|
rbitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
rbitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512VMC10R")
|
|
rbitfld.long 0x00 20. " PCSIS[4] ,Peripheral chip select 4 inactive state" "Low,High"
|
|
rbitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High"
|
|
rbitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High"
|
|
rbitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High"
|
|
newline
|
|
rbitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High"
|
|
newline
|
|
else
|
|
rbitfld.long 0x00 21. " PCSIS[5] ,Peripheral chip select 5 inactive state" "Low,High"
|
|
rbitfld.long 0x00 20. " [4] ,Peripheral chip select 4 inactive state" "Low,High"
|
|
rbitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High"
|
|
rbitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High"
|
|
newline
|
|
rbitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High"
|
|
rbitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High"
|
|
newline
|
|
endif
|
|
newline
|
|
rbitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
newline
|
|
rbitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear"
|
|
rbitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4002C000+0x0C))&0x2000000)==0x0000000)&&(((per.l(ad:0x4002C000+0x10))&0x2000000)==0x0000000)
|
|
if ((per.l(ad:0x4002C000)&0x4000)==0x4000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,DSPI0 Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..."
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")
|
|
bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512VMC10R")
|
|
bitfld.long 0x00 20. " PCSIS[4] ,Peripheral chip select 4 inactive state" "Low,High"
|
|
bitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High"
|
|
bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 21. " PCSIS[5] ,Peripheral chip select 5 inactive state" "Low,High"
|
|
bitfld.long 0x00 20. " [4] ,Peripheral chip select 4 inactive state" "Low,High"
|
|
bitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High"
|
|
bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 clocks,1 clock,2 clocks,?..."
|
|
bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,DSPI0 Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..."
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")
|
|
bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512VMC10R")
|
|
bitfld.long 0x00 20. " PCSIS[4] ,Peripheral chip select 4 inactive state" "Low,High"
|
|
bitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High"
|
|
bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 21. " PCSIS[5] ,Peripheral chip select 5 inactive state" "Low,High"
|
|
bitfld.long 0x00 20. " [4] ,Peripheral chip select 4 inactive state" "Low,High"
|
|
bitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High"
|
|
bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 clocks,1 clock,2 clocks,?..."
|
|
bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x4002C000)&0x4000)==0x4000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,DSPI0 Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..."
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")
|
|
bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512VMC10R")
|
|
bitfld.long 0x00 20. " PCSIS[4] ,Peripheral chip select 4 inactive state" "Low,High"
|
|
bitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High"
|
|
bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 21. " PCSIS[5] ,Peripheral chip select 5 inactive state" "Low,High"
|
|
bitfld.long 0x00 20. " [4] ,Peripheral chip select 4 inactive state" "Low,High"
|
|
bitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High"
|
|
bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,DSPI0 Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..."
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")
|
|
bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512VMC10R")
|
|
bitfld.long 0x00 20. " PCSIS[4] ,Peripheral chip select 4 inactive state" "Low,High"
|
|
bitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High"
|
|
bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 21. " PCSIS[5] ,Peripheral chip select 5 inactive state" "Low,High"
|
|
bitfld.long 0x00 20. " [4] ,Peripheral chip select 4 inactive state" "Low,High"
|
|
bitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High"
|
|
bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop"
|
|
endif
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4002C000+0x0C))&0x2000000)==0x0000000)&&(((per.l(ad:0x4002C000+0x10))&0x2000000)==0x0000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,DSPI0 Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLL10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK60FN1M0VLQ15")
|
|
bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..."
|
|
newline
|
|
else
|
|
rbitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..."
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted"
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("MK??F*")||(cpuis("MK30D????ZVLQ*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK40DN512ZVLL10")||cpuis("MKL82*")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15")
|
|
bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("MK70*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10"))
|
|
bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High"
|
|
bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High"
|
|
bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High"
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
newline
|
|
else
|
|
sif cpuis("MKL82*")
|
|
bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High"
|
|
bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High"
|
|
newline
|
|
else
|
|
sif cpuis("MK??F*")||(cpuis("MK30D????ZVLQ*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK40DN512ZVLL10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15")
|
|
bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High"
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
newline
|
|
sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")
|
|
rbitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear"
|
|
rbitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..."
|
|
bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,DSPI0 Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK40DN512ZVLL10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK60FN1M0VLQ15")
|
|
bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..."
|
|
newline
|
|
else
|
|
rbitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..."
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted"
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("MK??F*")||(cpuis("MK30D????ZVLQ*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK40DN512ZVLL10")||cpuis("MKL82*")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15")
|
|
bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("MK70*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10"))
|
|
bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High"
|
|
bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High"
|
|
bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High"
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
newline
|
|
else
|
|
sif cpuis("MKL82*")
|
|
bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High"
|
|
bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High"
|
|
newline
|
|
else
|
|
sif cpuis("MK??F*")||(cpuis("MK30D????ZVLQ*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK40DN512ZVLL10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15")
|
|
bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High"
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
newline
|
|
sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")
|
|
rbitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear"
|
|
rbitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped"
|
|
endif
|
|
endif
|
|
newline
|
|
sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")
|
|
if (((per.l(ad:0x4002C000+0x2C))&0x40000000)==0x40000000)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TCR,DSPI0 Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TCR,DSPI0 Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter"
|
|
endif
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TCR,DSPI0 Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter"
|
|
endif
|
|
sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60DN512ZCAB10R")
|
|
if (((per.l(ad:0x4002C000+0x2C))&0x40000000)==0x40000000)
|
|
if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000)
|
|
rgroup.long 0xC++0x03
|
|
line.long 0x00 "CTAR0,DSPI0 Clock and Transfer Attributes Register 0"
|
|
bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled"
|
|
bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high"
|
|
bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured"
|
|
newline
|
|
bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB"
|
|
bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7"
|
|
bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7"
|
|
bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7"
|
|
bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CTAR1,DSPI0 Clock and Transfer Attributes Register 1"
|
|
bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled"
|
|
bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high"
|
|
bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured"
|
|
newline
|
|
bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB"
|
|
bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7"
|
|
bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7"
|
|
bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7"
|
|
bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CTAR0_SLAVE,DSPI0 Clock and Transfer Attributes Register (In Slave Mode)"
|
|
bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "CTAR0,DSPI0 Clock and Transfer Attributes Register 0"
|
|
bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled"
|
|
bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high"
|
|
bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured"
|
|
newline
|
|
bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB"
|
|
bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7"
|
|
bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7"
|
|
bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7"
|
|
bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CTAR1,DSPI0 Clock and Transfer Attributes Register 1"
|
|
bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled"
|
|
bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high"
|
|
bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured"
|
|
newline
|
|
bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB"
|
|
bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7"
|
|
bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7"
|
|
bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7"
|
|
bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CTAR0_SLAVE,DSPI0 Clock and Transfer Attributes Register (In Slave Mode)"
|
|
bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured"
|
|
endif
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "CTAR0,DSPI0 Clock and Transfer Attributes Register 0"
|
|
bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled"
|
|
bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high"
|
|
bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured"
|
|
newline
|
|
bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB"
|
|
bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7"
|
|
bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7"
|
|
bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7"
|
|
bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CTAR1,DSPI0 Clock and Transfer Attributes Register 1"
|
|
bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled"
|
|
bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high"
|
|
bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured"
|
|
newline
|
|
bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB"
|
|
bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7"
|
|
bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7"
|
|
bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7"
|
|
bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CTAR0_SLAVE,DSPI0 Clock and Transfer Attributes Register 0"
|
|
sif cpuis("MKL82*")
|
|
bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 27.--31. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high"
|
|
bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured"
|
|
sif !cpuis("MK8?FN256V*")&&!cpuis("MK40DN512ZVLL10")&&!cpuis("MKL82*")&&!cpuis("MK40DN512ZVLQ10")&&!cpuis("MK40DN512ZVMD10")&&!cpuis("MK40DX128ZVLQ10")&&!cpuis("MK40DX256ZVLQ10")&&!cpuis("MK40DX256ZVMD10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512VMC10R")
|
|
sif cpuis("MK60DN512ZCAB10R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZVLQ10R")
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "CTAR1_SLAVE,DSPI0 Clock and Transfer Attributes Register 1"
|
|
endif
|
|
endif
|
|
endif
|
|
endif
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SR,DSPI0 Status Register"
|
|
eventfld.long 0x00 31. " TCF ,Transfer complete flag" "Not completed,Completed"
|
|
sif cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK40DN512ZVLL10")||cpuis("MKL82*")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK8?FN256V*")
|
|
newline
|
|
eventfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
rbitfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 28. " EOQF ,End of queue flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 27. " TFUF ,Transmit FIFO underflow flag" "No underflow,Underflow"
|
|
eventfld.long 0x00 25. " TFFF ,Transmit FIFO fill flag" "Full,Not full"
|
|
eventfld.long 0x00 19. " RFOF ,Receive FIFO overflow flag" "No overflow,Overflow"
|
|
newline
|
|
eventfld.long 0x00 17. " RFDF ,Receive FIFO drain flag" "Empty,Not empty"
|
|
rbitfld.long 0x00 12.--15. " TXCTR ,TX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 8.--11. " TXNXTPTR ,Transmit next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 4.--7. " RXCTR ,RX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 0.--3. " POPNXTPTR ,Pop next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")
|
|
if (((per.l(ad:0x4002C000+0x2C))&0x40000000)==0x40000000)
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "RSER,DSPI0 DMA/Interrupt Request Select and Enable Register"
|
|
bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA / Interrupt request select" "Interrupt,DMA"
|
|
bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA / Interrupt request select" "Interrupt,DMA"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RSER,DSPI0 DMA/Interrupt Request Select and Enable Register"
|
|
bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA / Interrupt request select" "Interrupt,DMA"
|
|
bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA / Interrupt request select" "Interrupt,DMA"
|
|
endif
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RSER,DSPI0 DMA/Interrupt Request Select and Enable Register"
|
|
bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA / Interrupt request select" "Interrupt,DMA"
|
|
bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA / Interrupt request select" "Interrupt,DMA"
|
|
endif
|
|
if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "PUSHR,DSPI0 PUSH TX FIFO Register"
|
|
bitfld.long 0x00 31. " CONT ,Continuous peripheral chip select enable" "Return to inactive,Keep asserted"
|
|
bitfld.long 0x00 28.--30. " CTAS ,Clock and transfer attributes select" "CTAR0,CTAR1,?..."
|
|
bitfld.long 0x00 27. " EOQ ,End Of queue" "Not ended,Ended"
|
|
bitfld.long 0x00 26. " CTCNT ,Clear transfer counter" "No effect,Clear"
|
|
newline
|
|
sif !cpuis("MK30DN512ZVLK10")&&!cpuis("MK30D????ZVLQ*")&&!cpuis("MK30DX256VLL7*")&&!cpuis("MK70*")
|
|
sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")
|
|
bitfld.long 0x00 21. " PCS5 ,PCS 5 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 20. " PCS4 ,PCS 4 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted"
|
|
newline
|
|
bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted"
|
|
newline
|
|
elif cpuis("MK*LL*")||cpuis("MK*MC*")||cpuis("MK*LQ*")||cpuis("MK*MD*")||cpuis("MK*VMJ*")||cpuis("MK*AB*")||cpuis("MK6*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK40DN512ZVLL10")||cpuis("MKL82*")||cpuis("MK40DN512ZVLL10")||cpuis("MK53DX256ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCLL10")||cpuis("MK50DN512ZCMD10")
|
|
bitfld.long 0x00 21. " PCS5 ,PCS 5 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 20. " PCS4 ,PCS 4 signal assertion" "Negated,Asserted"
|
|
newline
|
|
sif cpuis("MK66FN2M0VLQ18R")
|
|
bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted"
|
|
newline
|
|
bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted"
|
|
newline
|
|
elif cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")
|
|
bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted"
|
|
newline
|
|
bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted"
|
|
newline
|
|
elif cpuis("MK60DN512ZCAB10R")
|
|
bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted"
|
|
newline
|
|
bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted"
|
|
newline
|
|
sif cpuis("MK40DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK63FN1M0VLQ12R")
|
|
bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted"
|
|
newline
|
|
else
|
|
sif cpuis("MK*VLL10")||cpuis("MK*AB*")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")
|
|
bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted"
|
|
newline
|
|
endif
|
|
endif
|
|
endif
|
|
else
|
|
bitfld.long 0x00 20. " PCS4 ,PCS 4 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted"
|
|
newline
|
|
bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted"
|
|
newline
|
|
endif
|
|
else
|
|
bitfld.long 0x00 21. " PCS5 ,PCS 5 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 20. " PCS4 ,PCS 4 signal assertion" "Negated,Asserted"
|
|
newline
|
|
bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted"
|
|
newline
|
|
bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted"
|
|
newline
|
|
endif
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
else
|
|
sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK70*")||cpuis("MK40DN512ZVLL10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10"))||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60FN1M0VLQ15")
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PUSHR_SLAVE,DSPI0 PUSH TX FIFO Register"
|
|
sif cpuis("MK?0D*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK30DX256VLL7*")||cpuis("MKL82*")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512VMC10R")
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
endif
|
|
endif
|
|
endif
|
|
newline
|
|
width 16.
|
|
sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLL10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "POPR,DSPI0 POP RX FIFO Register"
|
|
else
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "POPR,DSPI0 POP RX FIFO Register"
|
|
in
|
|
endif
|
|
if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000)
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "TXFR0,DSPI0 Transmit FIFO Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "TXFR1,DSPI0 Transmit FIFO Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "TXFR2,DSPI0 Transmit FIFO Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "TXFR3,DSPI0 Transmit FIFO Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
else
|
|
sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "TXFR0,DSPI0 Transmit FIFO Register 0"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "TXFR1,DSPI0 Transmit FIFO Register 1"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "TXFR2,DSPI0 Transmit FIFO Register 2"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "TXFR3,DSPI0 Transmit FIFO Register 3"
|
|
elif !cpuis("MK8?FN256V*")
|
|
hgroup.long 0x3C++0x03
|
|
hide.long 0x00 "TXFR0,DSPI0 Transmit FIFO Register 0"
|
|
in
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "TXFR1,DSPI0 Transmit FIFO Register 1"
|
|
in
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "TXFR2,DSPI0 Transmit FIFO Register 2"
|
|
in
|
|
hgroup.long 0x48++0x03
|
|
hide.long 0x00 "TXFR3,DSPI0 Transmit FIFO Register 3"
|
|
in
|
|
endif
|
|
endif
|
|
sif cpuis("MK8?FN256V*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")
|
|
rgroup.long (0x7C+0x0)++0x03
|
|
line.long 0x00 "RXFR0,DSPI0 Receive FIFO Register 0"
|
|
rgroup.long (0x7C+0x4)++0x03
|
|
line.long 0x00 "RXFR1,DSPI0 Receive FIFO Register 1"
|
|
rgroup.long (0x7C+0x8)++0x03
|
|
line.long 0x00 "RXFR2,DSPI0 Receive FIFO Register 2"
|
|
rgroup.long (0x7C+0xC)++0x03
|
|
line.long 0x00 "RXFR3,DSPI0 Receive FIFO Register 3"
|
|
else
|
|
hgroup.long 0x0++0x03 "DSPI0 Rx FIFO Registers"
|
|
hide.long 0x00 "RXFR0,DSPI0 Receive FIFO Register 0"
|
|
in
|
|
hgroup.long 0x4++0x03 "DSPI0 Rx FIFO Registers"
|
|
hide.long 0x00 "RXFR1,DSPI0 Receive FIFO Register 1"
|
|
in
|
|
hgroup.long 0x8++0x03 "DSPI0 Rx FIFO Registers"
|
|
hide.long 0x00 "RXFR2,DSPI0 Receive FIFO Register 2"
|
|
in
|
|
hgroup.long 0xC++0x03 "DSPI0 Rx FIFO Registers"
|
|
hide.long 0x00 "RXFR3,DSPI0 Receive FIFO Register 3"
|
|
in
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPI1"
|
|
base ad:0x4002D000
|
|
width 19.
|
|
sif cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK40DN512ZVLL10")
|
|
if (((per.l(ad:0x4002D000+0x0C))&0x2000000)==0x0000000)&&(((per.l(ad:0x4002D000+0x10))&0x2000000)==0x0000000)
|
|
if ((per.l(ad:0x4002D000)&0x80000000)==0x80000000)
|
|
if ((per.l(ad:0x4002D000)&0x4000)==0x4000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,DSPI1 Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..."
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
sif cpuis("MK40DN512ZVLL10")
|
|
bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
newline
|
|
rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,DSPI1 Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..."
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
sif cpuis("MK40DN512ZVLL10")
|
|
bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x4002D000)&0x4000)==0x4000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,DSPI1 Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..."
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..."
|
|
bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,DSPI1 Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..."
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..."
|
|
bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped"
|
|
endif
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x4002D000)&0x80000000)==0x80000000)
|
|
if ((per.l(ad:0x4002D000)&0x4000)==0x4000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,DSPI1 Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..."
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
sif cpuis("MK40DN512ZVLL10")
|
|
bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,DSPI1 Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..."
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
sif cpuis("MK40DN512ZVLL10")
|
|
bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
newline
|
|
rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x4002D000)&0x4000)==0x4000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,DSPI1 Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..."
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,DSPI1 Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..."
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped"
|
|
endif
|
|
endif
|
|
endif
|
|
elif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")
|
|
if (((per.l(ad:0x4002D000+0x2C))&0x40000000)==0x40000000)
|
|
if (((per.l(ad:0x4002D000+0x0C))&0x2000000)==0x0000000)&&(((per.l(ad:0x4002D000+0x10))&0x2000000)==0x0000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,DSPI1 Module Configuration Register"
|
|
rbitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
rbitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..."
|
|
rbitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted"
|
|
newline
|
|
rbitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")
|
|
rbitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
rbitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("KK60DN512ZCAB10R")
|
|
rbitfld.long 0x00 19. " PCSIS[3] ,Peripheral chip select 3 inactive state" "Low,High"
|
|
rbitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High"
|
|
rbitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High"
|
|
rbitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High"
|
|
endif
|
|
newline
|
|
rbitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
newline
|
|
rbitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear"
|
|
rbitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear"
|
|
rbitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 clocks,1 clock,2 clocks,?..."
|
|
bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,DSPI1 Module Configuration Register"
|
|
rbitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
rbitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..."
|
|
rbitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted"
|
|
newline
|
|
rbitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")
|
|
rbitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
rbitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("KK60DN512ZCAB10R")
|
|
rbitfld.long 0x00 19. " PCSIS[3] ,Peripheral chip select 3 inactive state" "Low,High"
|
|
rbitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High"
|
|
rbitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High"
|
|
rbitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High"
|
|
endif
|
|
newline
|
|
rbitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
newline
|
|
rbitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear"
|
|
rbitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4002D000+0x0C))&0x2000000)==0x0000000)&&(((per.l(ad:0x4002D000+0x10))&0x2000000)==0x0000000)
|
|
if ((per.l(ad:0x4002D000)&0x4000)==0x4000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,DSPI1 Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..."
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")
|
|
bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("KK60DN512ZCAB10R")
|
|
bitfld.long 0x00 19. " PCSIS[3] ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High"
|
|
bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High"
|
|
bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 clocks,1 clock,2 clocks,?..."
|
|
bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,DSPI1 Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..."
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")
|
|
bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("KK60DN512ZCAB10R")
|
|
bitfld.long 0x00 19. " PCSIS[3] ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High"
|
|
bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High"
|
|
bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 clocks,1 clock,2 clocks,?..."
|
|
bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x4002D000)&0x4000)==0x4000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,DSPI1 Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..."
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")
|
|
bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("KK60DN512ZCAB10R")
|
|
bitfld.long 0x00 19. " PCSIS[3] ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High"
|
|
bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High"
|
|
bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,DSPI1 Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..."
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted"
|
|
newline
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")
|
|
bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("KK60DN512ZCAB10R")
|
|
bitfld.long 0x00 19. " PCSIS[3] ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High"
|
|
bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High"
|
|
bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop"
|
|
endif
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4002D000+0x0C))&0x2000000)==0x0000000)&&(((per.l(ad:0x4002D000+0x10))&0x2000000)==0x0000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,DSPI1 Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLL10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK60FN1M0VLQ15")
|
|
bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..."
|
|
newline
|
|
else
|
|
rbitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..."
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted"
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("MK??F*")||(cpuis("MK30D????ZVLQ*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK40DN512ZVLL10")||cpuis("MKL82*")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15")
|
|
bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("MK70*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10"))
|
|
sif !cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK51DN512ZCLL10")
|
|
bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High"
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
newline
|
|
else
|
|
sif cpuis("MKL82*")
|
|
else
|
|
sif cpuis("MK??F*")||(cpuis("MK30D????ZVLQ*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK40DN512ZVLL10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15")
|
|
bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High"
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
newline
|
|
sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")
|
|
rbitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear"
|
|
rbitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..."
|
|
bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,DSPI1 Module Configuration Register"
|
|
bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master"
|
|
bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK40DN512ZVLL10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK60FN1M0VLQ15")
|
|
bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..."
|
|
newline
|
|
else
|
|
rbitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..."
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted"
|
|
bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("MK??F*")||(cpuis("MK30D????ZVLQ*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK40DN512ZVLL10")||cpuis("MKL82*")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15")
|
|
bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("MK70*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10"))
|
|
sif !cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK51DN512ZCLL10")
|
|
bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High"
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
newline
|
|
else
|
|
sif cpuis("MKL82*")
|
|
else
|
|
sif cpuis("MK??F*")||(cpuis("MK30D????ZVLQ*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK40DN512ZVLL10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15")
|
|
bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High"
|
|
bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High"
|
|
bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High"
|
|
bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes"
|
|
bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes"
|
|
bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes"
|
|
newline
|
|
sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")
|
|
rbitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear"
|
|
rbitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped"
|
|
endif
|
|
endif
|
|
newline
|
|
sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")
|
|
if (((per.l(ad:0x4002D000+0x2C))&0x40000000)==0x40000000)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TCR,DSPI1 Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TCR,DSPI1 Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter"
|
|
endif
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TCR,DSPI1 Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter"
|
|
endif
|
|
sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60DN512ZCAB10R")
|
|
if (((per.l(ad:0x4002D000+0x2C))&0x40000000)==0x40000000)
|
|
if ((per.l(ad:0x4002D000)&0x80000000)==0x80000000)
|
|
rgroup.long 0xC++0x03
|
|
line.long 0x00 "CTAR0,DSPI1 Clock and Transfer Attributes Register 0"
|
|
bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled"
|
|
bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high"
|
|
bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured"
|
|
newline
|
|
bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB"
|
|
bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7"
|
|
bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7"
|
|
bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7"
|
|
bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CTAR1,DSPI1 Clock and Transfer Attributes Register 1"
|
|
bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled"
|
|
bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high"
|
|
bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured"
|
|
newline
|
|
bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB"
|
|
bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7"
|
|
bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7"
|
|
bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7"
|
|
bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CTAR0_SLAVE,DSPI1 Clock and Transfer Attributes Register (In Slave Mode)"
|
|
bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x4002D000)&0x80000000)==0x80000000)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "CTAR0,DSPI1 Clock and Transfer Attributes Register 0"
|
|
bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled"
|
|
bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high"
|
|
bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured"
|
|
newline
|
|
bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB"
|
|
bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7"
|
|
bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7"
|
|
bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7"
|
|
bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CTAR1,DSPI1 Clock and Transfer Attributes Register 1"
|
|
bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled"
|
|
bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high"
|
|
bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured"
|
|
newline
|
|
bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB"
|
|
bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7"
|
|
bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7"
|
|
bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7"
|
|
bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CTAR0_SLAVE,DSPI1 Clock and Transfer Attributes Register (In Slave Mode)"
|
|
bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured"
|
|
endif
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x4002D000)&0x80000000)==0x80000000)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "CTAR0,DSPI1 Clock and Transfer Attributes Register 0"
|
|
bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled"
|
|
bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high"
|
|
bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured"
|
|
newline
|
|
bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB"
|
|
bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7"
|
|
bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7"
|
|
bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7"
|
|
bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CTAR1,DSPI1 Clock and Transfer Attributes Register 1"
|
|
bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled"
|
|
bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high"
|
|
bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured"
|
|
newline
|
|
bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB"
|
|
bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7"
|
|
bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7"
|
|
bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7"
|
|
bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CTAR0_SLAVE,DSPI1 Clock and Transfer Attributes Register 0"
|
|
sif cpuis("MKL82*")
|
|
bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 27.--31. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high"
|
|
bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured"
|
|
sif !cpuis("MK8?FN256V*")&&!cpuis("MK40DN512ZVLL10")&&!cpuis("MKL82*")&&!cpuis("MK40DN512ZVLQ10")&&!cpuis("MK40DN512ZVMD10")&&!cpuis("MK40DX128ZVLQ10")&&!cpuis("MK40DX256ZVLQ10")&&!cpuis("MK40DX256ZVMD10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512VMC10R")
|
|
sif cpuis("MK60DN512ZCAB10R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZVLQ10R")
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "CTAR1_SLAVE,DSPI1 Clock and Transfer Attributes Register 1"
|
|
endif
|
|
endif
|
|
endif
|
|
endif
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SR,DSPI1 Status Register"
|
|
eventfld.long 0x00 31. " TCF ,Transfer complete flag" "Not completed,Completed"
|
|
sif cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK40DN512ZVLL10")||cpuis("MKL82*")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK8?FN256V*")
|
|
newline
|
|
eventfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
rbitfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 28. " EOQF ,End of queue flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 27. " TFUF ,Transmit FIFO underflow flag" "No underflow,Underflow"
|
|
eventfld.long 0x00 25. " TFFF ,Transmit FIFO fill flag" "Full,Not full"
|
|
eventfld.long 0x00 19. " RFOF ,Receive FIFO overflow flag" "No overflow,Overflow"
|
|
newline
|
|
eventfld.long 0x00 17. " RFDF ,Receive FIFO drain flag" "Empty,Not empty"
|
|
rbitfld.long 0x00 12.--15. " TXCTR ,TX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 8.--11. " TXNXTPTR ,Transmit next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 4.--7. " RXCTR ,RX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 0.--3. " POPNXTPTR ,Pop next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")
|
|
if (((per.l(ad:0x4002D000+0x2C))&0x40000000)==0x40000000)
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "RSER,DSPI1 DMA/Interrupt Request Select and Enable Register"
|
|
bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA / Interrupt request select" "Interrupt,DMA"
|
|
bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA / Interrupt request select" "Interrupt,DMA"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RSER,DSPI1 DMA/Interrupt Request Select and Enable Register"
|
|
bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA / Interrupt request select" "Interrupt,DMA"
|
|
bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA / Interrupt request select" "Interrupt,DMA"
|
|
endif
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RSER,DSPI1 DMA/Interrupt Request Select and Enable Register"
|
|
bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA / Interrupt request select" "Interrupt,DMA"
|
|
bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA / Interrupt request select" "Interrupt,DMA"
|
|
endif
|
|
if ((per.l(ad:0x4002D000)&0x80000000)==0x80000000)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "PUSHR,DSPI1 PUSH TX FIFO Register"
|
|
bitfld.long 0x00 31. " CONT ,Continuous peripheral chip select enable" "Return to inactive,Keep asserted"
|
|
bitfld.long 0x00 28.--30. " CTAS ,Clock and transfer attributes select" "CTAR0,CTAR1,?..."
|
|
bitfld.long 0x00 27. " EOQ ,End Of queue" "Not ended,Ended"
|
|
bitfld.long 0x00 26. " CTCNT ,Clear transfer counter" "No effect,Clear"
|
|
newline
|
|
sif !cpuis("MK30DN512ZVLK10")&&!cpuis("MK30D????ZVLQ*")&&!cpuis("MK30DX256VLL7*")&&!cpuis("MK70*")
|
|
sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")
|
|
sif !cpuis("KK60DN512ZCAB10R")
|
|
sif !cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK51DN512ZCLL10")
|
|
bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted"
|
|
newline
|
|
endif
|
|
elif cpuis("MK*LL*")||cpuis("MK*MC*")||cpuis("MK*LQ*")||cpuis("MK*MD*")||cpuis("MK*VMJ*")||cpuis("MK*AB*")||cpuis("MK6*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK40DN512ZVLL10")||cpuis("MKL82*")||cpuis("MK40DN512ZVLL10")||cpuis("MK53DX256ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCLL10")||cpuis("MK50DN512ZCMD10")
|
|
sif cpuis("MK66FN2M0VLQ18R")
|
|
bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted"
|
|
newline
|
|
elif cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")
|
|
bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted"
|
|
newline
|
|
elif cpuis("MK60DN512ZCAB10R")
|
|
else
|
|
bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted"
|
|
newline
|
|
sif cpuis("MK40DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK63FN1M0VLQ12R")
|
|
bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted"
|
|
newline
|
|
else
|
|
sif cpuis("MK*VLL10")||cpuis("MK*AB*")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")
|
|
bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted"
|
|
newline
|
|
endif
|
|
endif
|
|
endif
|
|
else
|
|
sif !cpuis("MK*LH7")
|
|
bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted"
|
|
newline
|
|
endif
|
|
else
|
|
bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted"
|
|
newline
|
|
bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted"
|
|
bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted"
|
|
newline
|
|
endif
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
else
|
|
sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK70*")||cpuis("MK40DN512ZVLL10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10"))||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60FN1M0VLQ15")
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PUSHR_SLAVE,DSPI1 PUSH TX FIFO Register"
|
|
sif cpuis("MK?0D*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK30DX256VLL7*")||cpuis("MKL82*")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512VMC10R")
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
endif
|
|
endif
|
|
endif
|
|
newline
|
|
width 16.
|
|
sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLL10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "POPR,DSPI1 POP RX FIFO Register"
|
|
else
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "POPR,DSPI1 POP RX FIFO Register"
|
|
in
|
|
endif
|
|
if ((per.l(ad:0x4002D000)&0x80000000)==0x80000000)
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "TXFR0,DSPI1 Transmit FIFO Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "TXFR1,DSPI1 Transmit FIFO Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "TXFR2,DSPI1 Transmit FIFO Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "TXFR3,DSPI1 Transmit FIFO Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data"
|
|
else
|
|
sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "TXFR0,DSPI1 Transmit FIFO Register 0"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "TXFR1,DSPI1 Transmit FIFO Register 1"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "TXFR2,DSPI1 Transmit FIFO Register 2"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "TXFR3,DSPI1 Transmit FIFO Register 3"
|
|
elif !cpuis("MK8?FN256V*")
|
|
hgroup.long 0x3C++0x03
|
|
hide.long 0x00 "TXFR0,DSPI1 Transmit FIFO Register 0"
|
|
in
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "TXFR1,DSPI1 Transmit FIFO Register 1"
|
|
in
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "TXFR2,DSPI1 Transmit FIFO Register 2"
|
|
in
|
|
hgroup.long 0x48++0x03
|
|
hide.long 0x00 "TXFR3,DSPI1 Transmit FIFO Register 3"
|
|
in
|
|
endif
|
|
endif
|
|
sif cpuis("MK8?FN256V*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")
|
|
rgroup.long (0x7C+0x0)++0x03
|
|
line.long 0x00 "RXFR0,DSPI1 Receive FIFO Register 0"
|
|
rgroup.long (0x7C+0x4)++0x03
|
|
line.long 0x00 "RXFR1,DSPI1 Receive FIFO Register 1"
|
|
rgroup.long (0x7C+0x8)++0x03
|
|
line.long 0x00 "RXFR2,DSPI1 Receive FIFO Register 2"
|
|
rgroup.long (0x7C+0xC)++0x03
|
|
line.long 0x00 "RXFR3,DSPI1 Receive FIFO Register 3"
|
|
else
|
|
hgroup.long 0x0++0x03 "DSPI1 Rx FIFO Registers"
|
|
hide.long 0x00 "RXFR0,DSPI1 Receive FIFO Register 0"
|
|
in
|
|
hgroup.long 0x4++0x03 "DSPI1 Rx FIFO Registers"
|
|
hide.long 0x00 "RXFR1,DSPI1 Receive FIFO Register 1"
|
|
in
|
|
hgroup.long 0x8++0x03 "DSPI1 Rx FIFO Registers"
|
|
hide.long 0x00 "RXFR2,DSPI1 Receive FIFO Register 2"
|
|
in
|
|
hgroup.long 0xC++0x03 "DSPI1 Rx FIFO Registers"
|
|
hide.long 0x00 "RXFR3,DSPI1 Receive FIFO Register 3"
|
|
in
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
elif !cpuis("MKL28*")
|
|
tree.open "SPI (Serial Peripheral Interface)"
|
|
tree "SPI_0"
|
|
base ad:0x40076000
|
|
sif cpuis("MKL03*")||cpuis("MKL13*")||cpuis("MKL16*")||cpuis("MKL17Z*")||cpuis("MKL26*")||cpuis("MKL27Z*")||cpuis("MKL33*")||cpuis("MKL34*")||cpuis("MKL36*")||cpuis("MKL43*")||cpuis("MKL46*")
|
|
width 9.
|
|
hgroup.byte 0x00++0x00
|
|
hide.byte 0x00 "SPI0_S,SPI Status Register"
|
|
in
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SPI0_BR,SPI Baud Rate Register"
|
|
bitfld.byte 0x00 4.--6. " SPPR ,SPI baud rate prescale divisor" "1,2,3,4,5,6,7,8"
|
|
bitfld.byte 0x00 0.--3. " SPR ,SPI baud rate divisor" "2,4,8,16,32,64,128,256,512,?..."
|
|
if ((per.b(ad:0x40076000+0x03)&0x10)==0x10)&&((per.b(ad:0x40076000+0x02)&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SPI0_C2,SPI0 Control Register 2"
|
|
sif !cpuis("MKL03*")
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPIMODE ,SPI 8-bit or 16-bit mode" "8-bit,16-bit"
|
|
bitfld.byte 0x00 5. " TXDMAE ,Transmit DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " MODFEN ,Master mode-fault function enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " BIDIROE ,Bidirectional mode output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RXDMAE ,Receive DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
else
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " MODFEN ,Master mode-fault function enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " BIDIROE ,Bidirectional mode output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
endif
|
|
elif ((per.b(ad:0x40076000+0x03)&0x10)==0x10)&&((per.b(ad:0x40076000+0x02)&0x01)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SPI0_C2,SPI0 Control Register 2"
|
|
sif !cpuis("MKL03*")
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPIMODE ,SPI 8-bit or 16-bit mode" "8-bit,16-bit"
|
|
bitfld.byte 0x00 5. " TXDMAE ,Transmit DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " MODFEN ,Master mode-fault function enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RXDMAE ,Receive DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
else
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " MODFEN ,Master mode-fault function enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
endif
|
|
elif ((per.b(ad:0x40076000+0x03)&0x10)==0x00)&&((per.b(ad:0x40076000+0x02)&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SPI0_C2,SPI0 Control Register 2"
|
|
sif !cpuis("MKL03*")
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPIMODE ,SPI 8-bit or 16-bit mode" "8-bit,16-bit"
|
|
bitfld.byte 0x00 5. " TXDMAE ,Transmit DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 3. " BIDIROE ,Bidirectional mode output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RXDMAE ,Receive DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
else
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 3. " BIDIROE ,Bidirectional mode output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
endif
|
|
elif ((per.b(ad:0x40076000+0x03)&0x10)==0x00)&&((per.b(ad:0x40076000+0x02)&0x01)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SPI0_C2,SPI0 Control Register 2"
|
|
sif !cpuis("MKL03*")
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPIMODE ,SPI 8-bit or 16-bit mode" "8-bit,16-bit"
|
|
bitfld.byte 0x00 5. " TXDMAE ,Transmit DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 2. " RXDMAE ,Receive DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
else
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
newline
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
endif
|
|
endif
|
|
sif cpuis("MKL03Z*")
|
|
if ((per.b(ad:0x40076000+0x02)&0x10)==0x10)&&((per.b(ad:0x40076000+0x03)&0x10)==0x10)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SPI0_C1,SPI0 Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (SPRF" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
newline
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "Input,Output"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
elif ((per.b(ad:0x40076000+0x02)&0x10)==0x00)&&((per.b(ad:0x40076000+0x03)&0x10)==0x10)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SPI0_C1,SPI0 Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (SPRF" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
newline
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "GPIO,GPIO"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
elif ((per.b(ad:0x40076000+0x03)&0x10)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SPI0_C1,SPI0 Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (SPRF" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
newline
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "Input,Input"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
endif
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SPI0_M,SPI Match Register"
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "SPI0_D,SPI Data Register"
|
|
else
|
|
if (((per.b(ad:0x40076000+0x0B))&0x01)==0x00)&&(((per.b(ad:0x40076000+0x03))&0x10)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SPI0_C1,SPI Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (SPRF,MODF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
newline
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "Input,Input"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
elif (((per.b(ad:0x40076000+0x0B))&0x01)==0x01)&&(((per.b(ad:0x40076000+0x03))&0x10)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SPI0_C1,SPI Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (fifo)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
newline
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "Input,Input"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
elif (((per.b(ad:0x40076000+0x0B))&0x01)==0x00)&&(((per.b(ad:0x40076000+0x02))&0x10)==0x00)&&(((per.b(ad:0x40076000+0x03))&0x10)==0x10)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SPI0_C1,SPI Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (SPRF,MODF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
newline
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "GPIO,GPIO"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
elif (((per.b(ad:0x40076000+0x0B))&0x01)==0x01)&&(((per.b(ad:0x40076000+0x02))&0x10)==0x00)&&(((per.b(ad:0x40076000+0x03))&0x10)==0x10)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SPI0_C1,SPI Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (fifo)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
newline
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "GPIO,GPIO"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
elif (((per.b(ad:0x40076000+0x0B))&0x01)==0x00)&&(((per.b(ad:0x40076000+0x02))&0x10)==0x10)&&(((per.b(ad:0x40076000+0x03))&0x10)==0x10)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SPI0_C1,SPI Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (SPRF,MODF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
newline
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "Input,Output"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
elif (((per.b(ad:0x40076000+0x0B))&0x01)==0x01)&&(((per.b(ad:0x40076000+0x02))&0x10)==0x10)&&(((per.b(ad:0x40076000+0x03))&0x10)==0x10)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SPI0_C1,SPI Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (fifo)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
newline
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "Input,Output"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
endif
|
|
group.byte 0x04++0x03
|
|
line.byte 0x00 "SPI0_ML,SPI Match Register Low"
|
|
line.byte 0x01 "SPI0_MH,SPI Match Register High"
|
|
line.byte 0x02 "SPI0_DL,SPI Data Register Low"
|
|
line.byte 0x03 "SPI0_DH,SPI Data Register High"
|
|
sif !cpuis("MKL17Z32*")&&!cpuis("MKL17Z64*")&&!cpuis("MKL27Z*")&&!cpuis("MKL43Z*")
|
|
hgroup.byte 0x0A++0x00
|
|
hide.byte 0x00 "SPI0_CI,SPI Clear Interrupt"
|
|
in
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "SPI0_C3,SPI Control Register 3"
|
|
bitfld.byte 0x00 5. " TNEAREF_MARK ,Transmit fifo nearly empty watermark" "16 bits or less,32 bits or less"
|
|
bitfld.byte 0x00 4. " RNFULLF_MARK ,Receive fifo nearly full watermark" "48 bits or more,32 bits or more"
|
|
bitfld.byte 0x00 3. " INTCLR ,Interrupt clearing mechanism" "When flags are cleared,When writing bits in CI"
|
|
newline
|
|
bitfld.byte 0x00 2. " TNEARIEN ,Transmit fifo nearly empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RNFULLIEN ,Receive fifo nearly full interrupt watermark" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FIFOMODE ,Fifo mode enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
else
|
|
width 9.
|
|
if ((per.b(ad:0x40076000+0x01)&0x10)==0x10)&&((per.b(ad:0x40076000)&0x10)==0x10)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SPI0_C1,SPI0 Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (SPRF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
newline
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "Input,Output"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
elif ((per.b(ad:0x40076000+0x01)&0x10)==0x00)&&((per.b(ad:0x40076000)&0x10)==0x10)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SPI0_C1,SPI0 Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (SPRF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
newline
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "GPIO,GPIO"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
elif ((per.b(ad:0x40076000)&0x10)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SPI0_C1,SPI0 Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (SPRF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
newline
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "Input,Input"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
endif
|
|
if ((per.b(ad:0x40076000)&0x10)==0x10)&&((per.b(ad:0x40076000+0x01)&0x01)==0x01)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SPI0_C2,SPI0 Control Register 2"
|
|
sif !cpuis("MKL02*")
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TXDMAE ,Transmit DMA enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " MODFEN ,Master mode-fault function enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " BIDIROE ,Bidirectional mode output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 2. " RXDMAE ,Receive DMA enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
else
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " MODFEN ,Master mode-fault function enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " BIDIROE ,Bidirectional mode output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
endif
|
|
elif ((per.b(ad:0x40076000)&0x10)==0x10)&&((per.b(ad:0x40076000+0x01)&0x01)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SPI0_C2,SPI0 Control Register 2"
|
|
sif !cpuis("MKL02*")
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TXDMAE ,Transmit DMA enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " MODFEN ,Master mode-fault function enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 2. " RXDMAE ,Receive DMA enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
else
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " MODFEN ,Master mode-fault function enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
endif
|
|
elif ((per.b(ad:0x40076000)&0x10)==0x00)&&((per.b(ad:0x40076000+0x01)&0x01)==0x01)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SPI0_C2,SPI0 Control Register 2"
|
|
sif !cpuis("MKL02*")
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TXDMAE ,Transmit DMA enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " BIDIROE ,Bidirectional mode output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 2. " RXDMAE ,Receive DMA enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
else
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " BIDIROE ,Bidirectional mode output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
endif
|
|
elif ((per.b(ad:0x40076000)&0x10)==0x00)&&((per.b(ad:0x40076000+0x01)&0x01)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SPI0_C2,SPI0 Control Register 2"
|
|
sif !cpuis("MKL02*")
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TXDMAE ,Transmit DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 2. " RXDMAE ,Receive DMA enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
else
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
endif
|
|
endif
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SPI0_BR,SPI Baud Rate Register"
|
|
bitfld.byte 0x00 4.--6. " SPPR[2:0] ,SPI baud rate prescale divisor" "1,2,3,4,5,6,7,8"
|
|
bitfld.byte 0x00 0.--3. " SPR[3:0] ,SPI baud rate divisor" "2,4,8,16,32,64,128,256,512,?..."
|
|
hgroup.byte 0x03++0x00
|
|
hide.byte 0x00 "SPI0_S,SPI Status Register"
|
|
in
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "SPI0_D,SPI Data Register"
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "SPI0_M,SPI Match Register"
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
sif !cpuis("MKL02Z*")&&!cpuis("MKL03Z*")&&!cpuis("MKL05Z*")
|
|
tree "SPI_1"
|
|
base ad:0x40077000
|
|
sif cpuis("MKL13*")||cpuis("MKL16*")||cpuis("MKL17Z*")||cpuis("MKL26*")||cpuis("MKL27Z*")||cpuis("MKL33*")||cpuis("MKL34*")||cpuis("MKL36*")||cpuis("MKL43*")||cpuis("MKL46*")
|
|
width 9.
|
|
hgroup.byte 0x00++0x00
|
|
hide.byte 0x00 "SPI1_S,SPI Status Register"
|
|
in
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SPI1_BR,SPI Baud Rate Register"
|
|
bitfld.byte 0x00 4.--6. " SPPR ,SPI baud rate prescale divisor" "1,2,3,4,5,6,7,8"
|
|
bitfld.byte 0x00 0.--3. " SPR ,SPI baud rate divisor" "2,4,8,16,32,64,128,256,512,?..."
|
|
if ((per.b(ad:0x40077000+0x03)&0x10)==0x10)&&((per.b(ad:0x40077000+0x02)&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SPI1_C2,SPI1 Control Register 2"
|
|
sif !cpuis("MKL03*")
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPIMODE ,SPI 8-bit or 16-bit mode" "8-bit,16-bit"
|
|
bitfld.byte 0x00 5. " TXDMAE ,Transmit DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " MODFEN ,Master mode-fault function enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " BIDIROE ,Bidirectional mode output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RXDMAE ,Receive DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
else
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " MODFEN ,Master mode-fault function enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " BIDIROE ,Bidirectional mode output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
endif
|
|
elif ((per.b(ad:0x40077000+0x03)&0x10)==0x10)&&((per.b(ad:0x40077000+0x02)&0x01)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SPI1_C2,SPI1 Control Register 2"
|
|
sif !cpuis("MKL03*")
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPIMODE ,SPI 8-bit or 16-bit mode" "8-bit,16-bit"
|
|
bitfld.byte 0x00 5. " TXDMAE ,Transmit DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " MODFEN ,Master mode-fault function enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RXDMAE ,Receive DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
else
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " MODFEN ,Master mode-fault function enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
endif
|
|
elif ((per.b(ad:0x40077000+0x03)&0x10)==0x00)&&((per.b(ad:0x40077000+0x02)&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SPI1_C2,SPI1 Control Register 2"
|
|
sif !cpuis("MKL03*")
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPIMODE ,SPI 8-bit or 16-bit mode" "8-bit,16-bit"
|
|
bitfld.byte 0x00 5. " TXDMAE ,Transmit DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 3. " BIDIROE ,Bidirectional mode output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RXDMAE ,Receive DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
else
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 3. " BIDIROE ,Bidirectional mode output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
endif
|
|
elif ((per.b(ad:0x40077000+0x03)&0x10)==0x00)&&((per.b(ad:0x40077000+0x02)&0x01)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SPI1_C2,SPI1 Control Register 2"
|
|
sif !cpuis("MKL03*")
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPIMODE ,SPI 8-bit or 16-bit mode" "8-bit,16-bit"
|
|
bitfld.byte 0x00 5. " TXDMAE ,Transmit DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 2. " RXDMAE ,Receive DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
else
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
newline
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
endif
|
|
endif
|
|
sif cpuis("MKL03Z*")
|
|
if ((per.b(ad:0x40077000+0x02)&0x10)==0x10)&&((per.b(ad:0x40077000+0x03)&0x10)==0x10)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SPI1_C1,SPI1 Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (SPRF" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
newline
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "Input,Output"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
elif ((per.b(ad:0x40077000+0x02)&0x10)==0x00)&&((per.b(ad:0x40077000+0x03)&0x10)==0x10)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SPI1_C1,SPI1 Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (SPRF" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
newline
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "GPIO,GPIO"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
elif ((per.b(ad:0x40077000+0x03)&0x10)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SPI1_C1,SPI1 Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (SPRF" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
newline
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "Input,Input"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
endif
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SPI1_M,SPI Match Register"
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "SPI1_D,SPI Data Register"
|
|
else
|
|
if (((per.b(ad:0x40077000+0x0B))&0x01)==0x00)&&(((per.b(ad:0x40077000+0x03))&0x10)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SPI1_C1,SPI Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (SPRF,MODF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
newline
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "Input,Input"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
elif (((per.b(ad:0x40077000+0x0B))&0x01)==0x01)&&(((per.b(ad:0x40077000+0x03))&0x10)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SPI1_C1,SPI Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (fifo)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
newline
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "Input,Input"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
elif (((per.b(ad:0x40077000+0x0B))&0x01)==0x00)&&(((per.b(ad:0x40077000+0x02))&0x10)==0x00)&&(((per.b(ad:0x40077000+0x03))&0x10)==0x10)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SPI1_C1,SPI Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (SPRF,MODF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
newline
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "GPIO,GPIO"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
elif (((per.b(ad:0x40077000+0x0B))&0x01)==0x01)&&(((per.b(ad:0x40077000+0x02))&0x10)==0x00)&&(((per.b(ad:0x40077000+0x03))&0x10)==0x10)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SPI1_C1,SPI Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (fifo)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
newline
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "GPIO,GPIO"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
elif (((per.b(ad:0x40077000+0x0B))&0x01)==0x00)&&(((per.b(ad:0x40077000+0x02))&0x10)==0x10)&&(((per.b(ad:0x40077000+0x03))&0x10)==0x10)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SPI1_C1,SPI Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (SPRF,MODF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
newline
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "Input,Output"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
elif (((per.b(ad:0x40077000+0x0B))&0x01)==0x01)&&(((per.b(ad:0x40077000+0x02))&0x10)==0x10)&&(((per.b(ad:0x40077000+0x03))&0x10)==0x10)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SPI1_C1,SPI Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (fifo)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
newline
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "Input,Output"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
endif
|
|
group.byte 0x04++0x03
|
|
line.byte 0x00 "SPI1_ML,SPI Match Register Low"
|
|
line.byte 0x01 "SPI1_MH,SPI Match Register High"
|
|
line.byte 0x02 "SPI1_DL,SPI Data Register Low"
|
|
line.byte 0x03 "SPI1_DH,SPI Data Register High"
|
|
sif !cpuis("MKL17Z32*")&&!cpuis("MKL17Z64*")&&!cpuis("MKL27Z*")&&!cpuis("MKL43Z*")
|
|
hgroup.byte 0x0A++0x00
|
|
hide.byte 0x00 "SPI1_CI,SPI Clear Interrupt"
|
|
in
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "SPI1_C3,SPI Control Register 3"
|
|
bitfld.byte 0x00 5. " TNEAREF_MARK ,Transmit fifo nearly empty watermark" "16 bits or less,32 bits or less"
|
|
bitfld.byte 0x00 4. " RNFULLF_MARK ,Receive fifo nearly full watermark" "48 bits or more,32 bits or more"
|
|
bitfld.byte 0x00 3. " INTCLR ,Interrupt clearing mechanism" "When flags are cleared,When writing bits in CI"
|
|
newline
|
|
bitfld.byte 0x00 2. " TNEARIEN ,Transmit fifo nearly empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RNFULLIEN ,Receive fifo nearly full interrupt watermark" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FIFOMODE ,Fifo mode enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
elif cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("KKL15*")
|
|
width 9.
|
|
if ((per.b(ad:0x40077000+0x01)&0x10)==0x10)&&((per.b(ad:0x40077000)&0x10)==0x10)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SPI1_C1,SPI1 Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (SPRF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
newline
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "Input,Output"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
elif ((per.b(ad:0x40077000+0x01)&0x10)==0x00)&&((per.b(ad:0x40077000)&0x10)==0x10)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SPI1_C1,SPI1 Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (SPRF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
newline
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "GPIO,GPIO"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
elif ((per.b(ad:0x40077000)&0x10)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SPI1_C1,SPI1 Control Register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (SPRF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
newline
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "Input,Input"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
endif
|
|
if ((per.b(ad:0x40077000)&0x10)==0x10)&&((per.b(ad:0x40077000+0x01)&0x01)==0x01)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SPI1_C2,SPI1 Control Register 2"
|
|
sif !cpuis("MKL02*")
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TXDMAE ,Transmit DMA enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " MODFEN ,Master mode-fault function enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " BIDIROE ,Bidirectional mode output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 2. " RXDMAE ,Receive DMA enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
else
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " MODFEN ,Master mode-fault function enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " BIDIROE ,Bidirectional mode output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
endif
|
|
elif ((per.b(ad:0x40077000)&0x10)==0x10)&&((per.b(ad:0x40077000+0x01)&0x01)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SPI1_C2,SPI1 Control Register 2"
|
|
sif !cpuis("MKL02*")
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TXDMAE ,Transmit DMA enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " MODFEN ,Master mode-fault function enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 2. " RXDMAE ,Receive DMA enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
else
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " MODFEN ,Master mode-fault function enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
endif
|
|
elif ((per.b(ad:0x40077000)&0x10)==0x00)&&((per.b(ad:0x40077000+0x01)&0x01)==0x01)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SPI1_C2,SPI1 Control Register 2"
|
|
sif !cpuis("MKL02*")
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TXDMAE ,Transmit DMA enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " BIDIROE ,Bidirectional mode output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 2. " RXDMAE ,Receive DMA enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
else
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " BIDIROE ,Bidirectional mode output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
endif
|
|
elif ((per.b(ad:0x40077000)&0x10)==0x00)&&((per.b(ad:0x40077000+0x01)&0x01)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SPI1_C2,SPI1 Control Register 2"
|
|
sif !cpuis("MKL02*")
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TXDMAE ,Transmit DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 2. " RXDMAE ,Receive DMA enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
else
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
endif
|
|
endif
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SPI1_BR,SPI Baud Rate Register"
|
|
bitfld.byte 0x00 4.--6. " SPPR[2:0] ,SPI baud rate prescale divisor" "1,2,3,4,5,6,7,8"
|
|
bitfld.byte 0x00 0.--3. " SPR[3:0] ,SPI baud rate divisor" "2,4,8,16,32,64,128,256,512,?..."
|
|
hgroup.byte 0x03++0x00
|
|
hide.byte 0x00 "SPI1_S,SPI Status Register"
|
|
in
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "SPI1_D,SPI Data Register"
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "SPI1_M,SPI Match Register"
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("MKL28*")
|
|
tree "LPI2C (Low Power Inter-Integrated Circuit)"
|
|
base ad:0x40042000
|
|
width 8.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version number"
|
|
hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number"
|
|
line.long 0x04 "PARAM,Parameter Register"
|
|
bitfld.long 0x04 8.--11. " MRXFIFO ,Master receive FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x04 0.--3. " MTXFIFO ,Master transmit FIFO size" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
group.long 0x10++0x13
|
|
line.long 0x00 "MCR,Master Control Register"
|
|
bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset"
|
|
bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset"
|
|
bitfld.long 0x00 3. " DBGEN ,Debug enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " DOZEN ,Doze mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " MEN ,Master enable" "Disabled,Enabled"
|
|
line.long 0x04 "MSR,Master Status Register"
|
|
rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy"
|
|
rbitfld.long 0x04 24. " MBF ,Master busy flag" "Idle,Busy"
|
|
eventfld.long 0x04 14. " DMF ,Data match flag" "No match,Match"
|
|
newline
|
|
eventfld.long 0x04 13. " PLTF ,Pin low timeout flag" "No timeout,Timeout"
|
|
eventfld.long 0x04 12. " FEF ,FIFO error flag" "No error,Error"
|
|
eventfld.long 0x04 11. " ALF ,Arbitration lost flag" "Not lost,Lost"
|
|
newline
|
|
eventfld.long 0x04 10. " NDF ,NACK detect flag" "Not detected,Detected"
|
|
eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected"
|
|
eventfld.long 0x04 8. " EPF ,End packet flag" "Not end packet,End packet"
|
|
newline
|
|
rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready"
|
|
rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested"
|
|
line.long 0x08 "MIER,Master Interrupt Enable Register"
|
|
bitfld.long 0x08 14. " DMIE ,Data match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " PLTIE ,Pin low timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 11. " ALIE ,Arbitration lost interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " NDIE ,NACK detect interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 8. " EPIE ,End packet interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled"
|
|
line.long 0x0C "MDER,Master DMA Enable Register"
|
|
bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled"
|
|
line.long 0x10 "MCFGR0,Master Configuration Register 0"
|
|
bitfld.long 0x10 9. " RDMO ,Receive data match only" "All data,Matched only"
|
|
bitfld.long 0x10 8. " CIRFIFO ,Circular FIFO enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " HRSEL ,Host request select" "LPI2C_HREQ pin,Input trigger"
|
|
newline
|
|
bitfld.long 0x10 1. " HRPOL ,Host request polarity" "Active low,Active high"
|
|
bitfld.long 0x10 0. " HREN ,Host request enable" "Disabled,Enabled"
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKS2?FN???V??12")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
if (((per.l(ad:0x40042000+0x10))&0x01)==0x00)
|
|
group.long 0x24++0x0B
|
|
line.long 0x00 "MCFGR1,Master Configuration Register 1"
|
|
bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1"
|
|
newline
|
|
bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "On SCL low too long,On SCL or SDA low too long"
|
|
bitfld.long 0x00 9. " IGNACK ,Ignore ACK" "Not ignored,Ignored"
|
|
bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
line.long 0x04 "MCFGR2,Master Configuration Register 2"
|
|
bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout"
|
|
line.long 0x08 "MCFGR3,Master Configuration Register 3"
|
|
hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout"
|
|
else
|
|
rgroup.long 0x24++0x0B
|
|
line.long 0x00 "MCFGR1,Master Configuration Register 1"
|
|
bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1"
|
|
newline
|
|
bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "On SCL low too long,On SCL or SDA low too long"
|
|
bitfld.long 0x00 9. " IGNACK ,Ignore ACK" "Not ignored,Ignored"
|
|
bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
line.long 0x04 "MCFGR2,Master Configuration Register 2"
|
|
bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout"
|
|
line.long 0x08 "MCFGR3,Master Configuration Register 3"
|
|
hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout"
|
|
endif
|
|
sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
if (((per.l(ad:0x40042000+0x10))&0x01)==0x00)||(((per.l(ad:0x40042000+0x14))&0x1000000)==0x00)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MDMR,Master Data Match Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value"
|
|
else
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "MDMR,Master Data Match Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value"
|
|
endif
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MDMR,Master Data Match Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value"
|
|
endif
|
|
if (((per.l(ad:0x40042000+0x10))&0x01)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "MCCR0,Master Clock Configuration Register 0"
|
|
bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " SETHOLD ,Setup hold delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "MCCR1,Master Clock Configuration Register 1"
|
|
bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " SETHOLD ,Setup hold delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "MCCR0,Master Clock Configuration Register 0"
|
|
bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " SETHOLD ,Setup hold delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "MCCR1,Master Clock Configuration Register 1"
|
|
bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " SETHOLD ,Setup hold delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
group.long 0x24++0x0B
|
|
line.long 0x00 "MCFGR1,Master Configuration Register 1"
|
|
bitfld.long 0x00 24.--26. " PINCFG ,Pin configuration" "2-pin open drain,2-pin output only,2-pin push-pull,4-pin push-pull,2-pin open drain/separate slave,2-pin output only/separate slave,2-pin push-pull/separate slave,4-pin push-pull/inverted outs"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " MATCFG ,Match configuration" "Match disabled,,1st word=MATCH0 OR MATCH1,Any word = MATCH0 OR MATCH1,1st word = MATCH0 AND 2nd word = MATCH1,Any word = MATCH0 AND next word = MATCH1,1st word AND MATCH1 = MATCH0 AND MATCH1,Any word AND MATCH1 = MATCH0 AND MATCH1"
|
|
newline
|
|
bitfld.long 0x00 10. " TIMECFG ,Timeout configuration" "On SCL low too long,On SCL or SDA low too long"
|
|
bitfld.long 0x00 9. " IGNACK ,Ignore ACK" "Not ignored,Ignored"
|
|
bitfld.long 0x00 8. " AUTOSTOP ,Automatic STOP generation" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " PRESCALE ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
line.long 0x04 "MCFGR2,Master Configuration Register 2"
|
|
bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x04 0.--11. 1. " BUSIDLE ,Bus idle timeout"
|
|
line.long 0x08 "MCFGR3,Master Configuration Register 3"
|
|
hexmask.long.word 0x08 8.--19. 1. " PINLOW ,Pin low timeout"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MDMR,Master Data Match Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MATCH1 ,Match 1 value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MATCH0 ,Match 0 value"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "MCCR0,Master Clock Configuration Register 0"
|
|
bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
bitfld.long 0x00 16.--21. " SETHOLD ,Setup hold delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
newline
|
|
bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
group.long 0x50++0x03
|
|
line.long 0x00 "MCCR1,Master Clock Configuration Register 1"
|
|
bitfld.long 0x00 24.--29. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
bitfld.long 0x00 16.--21. " SETHOLD ,Setup hold delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
bitfld.long 0x00 8.--13. " CLKHI ,Clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
newline
|
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bitfld.long 0x00 0.--5. " CLKLO ,Clock low period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MFCR,Master FIFO Control Register"
|
|
bitfld.long 0x00 16.--17. " RXWATER ,Receive FIFO watermark" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " TXWATER ,Transmit FIFO watermark" "0,1,2,3"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "MFSR,Master FIFO Status Register"
|
|
bitfld.long 0x00 16.--18. " RXCOUNT ,Receive FIFO count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " TXCOUNT ,Transmit FIFO count" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MFCR,Master FIFO Control Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive FIFO watermark"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit FIFO watermark"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "MFSR,Master FIFO Status Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RXCOUNT ,Receive FIFO count"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXCOUNT ,Transmit FIFO count"
|
|
endif
|
|
wgroup.long 0x60++0x03
|
|
line.long 0x00 "MTDR,Master Transmit Data Register"
|
|
bitfld.long 0x00 8.--10. " CMD ,Command data" "Transmit DATA[7:0],Receive (Data[7:0] + 1) bytes,Generate STOP condition,Receive and discard (Data[7:0] + 1) bytes,Generate (Repeated) START and transmit address in DATA[7:0],Generate (Repeated) START and transmit address in DATA[7:0],Generate (Repeated) START and transmit address in DATA[7:0] using high speed mode,Generate (Repeated) START and transmit address in DATA[7:0] using high speed mode"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data"
|
|
newline
|
|
hgroup.long 0x70++0x03
|
|
hide.long 0x00 "MRDR,Master Receive Data Register"
|
|
in
|
|
newline
|
|
sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
if (((per.l(ad:0x40042000+0x110))&0x01)==0x00)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "SCR,Slave Control Register"
|
|
bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset"
|
|
bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset"
|
|
bitfld.long 0x00 5. " FILTDZ ,Filter doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FILTEN ,Filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " SEN ,Slave enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "SCR,Slave Control Register"
|
|
bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset"
|
|
bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset"
|
|
rbitfld.long 0x00 5. " FILTDZ ,Filter doze enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " FILTEN ,Filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " SEN ,Slave enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x114++0x0B
|
|
line.long 0x00 "SSR,Slave Status Register"
|
|
rbitfld.long 0x00 25. " BBF ,Bus busy flag" "Idle,Busy"
|
|
rbitfld.long 0x00 24. " SBF ,Slave busy flag" "Idle,Busy"
|
|
rbitfld.long 0x00 15. " SARF ,SMBus alert response flag" "Not detected,Detected"
|
|
rbitfld.long 0x00 14. " GCF ,General call flag" "Not detected,Detected"
|
|
newline
|
|
rbitfld.long 0x00 13. " AM1F ,Address match 1 flag" "No match,Match"
|
|
rbitfld.long 0x00 12. " AM0F ,Address match 0 flag" "No match,Match"
|
|
eventfld.long 0x00 11. " FEF ,FIFO error flag" "No error,Error"
|
|
eventfld.long 0x00 10. " BEF ,Bit error flag" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 9. " SDF ,STOP detect flag" "Not detected,Detected"
|
|
eventfld.long 0x00 8. " RSF ,Repeated start flag" "Not detected,Detected"
|
|
rbitfld.long 0x00 3. " TAF ,Transmit ACK flag" "Not required,Required"
|
|
rbitfld.long 0x00 2. " AVF ,Address valid flag" "Invalid,Valid"
|
|
newline
|
|
rbitfld.long 0x00 1. " RDF ,Receive data flag" "Not ready,Ready"
|
|
rbitfld.long 0x00 0. " TDF ,Transmit data flag" "Not requested,Requested"
|
|
line.long 0x04 "SIER,Slave Interrupt Enable Register"
|
|
bitfld.long 0x04 15. " SARIE ,SMBus alert response interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " GCIE ,General call interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " AM1F ,Address match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " AM0IE ,Address match 0 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 11. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " BEIE ,Bit error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RSIE ,Repeated start interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " TAIE ,Transmit ACK interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " AVIE ,Address valid interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled"
|
|
line.long 0x08 "SDER,Slave DMA Enable Register"
|
|
bitfld.long 0x08 2. " AVDE ,Address valid DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x110++0x0F
|
|
line.long 0x00 "SCR,Slave Control Register"
|
|
sif cpuis("IMX8DV*")||cpuis("K32W0?2S1M*")||cpuis("MKL28*")||cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKS2?FN???V??12")
|
|
bitfld.long 0x00 9. " RRF ,Reset receive FIFO" "No effect,Reset"
|
|
bitfld.long 0x00 8. " RTF ,Reset transmit FIFO" "No effect,Reset"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " FILTDZ ,Filter doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FILTEN ,Filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " RST ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " SEN ,Slave enable" "Disabled,Enabled"
|
|
line.long 0x04 "SSR,Slave Status Register"
|
|
rbitfld.long 0x04 25. " BBF ,Bus busy flag" "Idle,Busy"
|
|
rbitfld.long 0x04 24. " SBF ,Slave busy flag" "Idle,Busy"
|
|
rbitfld.long 0x04 15. " SARF ,SMBus alert response flag" "Not detected,Detected"
|
|
newline
|
|
rbitfld.long 0x04 14. " GCF ,General call flag" "Not detected,Detected"
|
|
rbitfld.long 0x04 13. " AM1F ,Address match 1 flag" "No match,Match"
|
|
rbitfld.long 0x04 12. " AM0F ,Address match 0 flag" "No match,Match"
|
|
newline
|
|
eventfld.long 0x04 11. " FEF ,FIFO error flag" "No error,Error"
|
|
eventfld.long 0x04 10. " BEF ,Bit error flag" "No error,Error"
|
|
eventfld.long 0x04 9. " SDF ,STOP detect flag" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x04 8. " RSF ,Repeated start flag" "Not detected,Detected"
|
|
rbitfld.long 0x04 3. " TAF ,Transmit ACK flag" "Not required,Required"
|
|
rbitfld.long 0x04 2. " AVF ,Address valid flag" "Invalid,Valid"
|
|
newline
|
|
rbitfld.long 0x04 1. " RDF ,Receive data flag" "Not ready,Ready"
|
|
rbitfld.long 0x04 0. " TDF ,Transmit data flag" "Not requested,Requested"
|
|
line.long 0x08 "SIER,Slave Interrupt Enable Register"
|
|
bitfld.long 0x08 15. " SARIE ,SMBus alert response interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " GCIE ,General call interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " AM1F ,Address match 1 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 12. " AM0IE ,Address match 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " BEIE ,Bit error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 9. " SDIE ,STOP detect interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " RSIE ,Repeated start interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " TAIE ,Transmit ACK interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 2. " AVIE ,Address valid interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " RDIE ,Receive data interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TDIE ,Transmit data interrupt enable" "Disabled,Enabled"
|
|
line.long 0x0C "SDER,Slave DMA Enable Register"
|
|
bitfld.long 0x0C 2. " AVDE ,Address valid DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " RDDE ,Receive data DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " TDDE ,Transmit data DMA enable" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKS2?FN???V??12")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
if (((per.l(ad:0x40042000+0x110))&0x01)==0x00)
|
|
group.long 0x124++0x07
|
|
line.long 0x00 "SCFGR1,Slave Configuration Register 1"
|
|
bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration" "Address match 0 (7-bit),Address match 0 (10-bit),Address match 0 (7-bit) or address match 1 (7-bit),Address match 0 (10-bit) or address match 1 (10-bit),Address match 0 (7-bit) or address match 1 (10-bit),Address match 0 (10-bit) or address match 1 (7-bit),From address match 0 (7-bit) to address match 1 (7-bit),From address match 0 (10-bit) to address match 1 (10-bit)"
|
|
newline
|
|
bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " IGNACK ,Ignore NACK" "Not ignored,Ignored"
|
|
newline
|
|
bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return receive data and clear RDF,Return address status register and clear AVF when AVF set"
|
|
newline
|
|
bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer when TDR empty,On TDR empty"
|
|
newline
|
|
bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled"
|
|
line.long 0x04 "SCFGR2,Slave Configuration Register 2"
|
|
bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x124++0x07
|
|
line.long 0x00 "SCFGR1,Slave Configuration Register 1"
|
|
bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration" "Address match 0 (7-bit),Address match 0 (10-bit),Address match 0 (7-bit) or address match 1 (7-bit),Address match 0 (10-bit) or address match 1 (10-bit),Address match 0 (7-bit) or address match 1 (10-bit),Address match 0 (10-bit) or address match 1 (7-bit),From address match 0 (7-bit) to address match 1 (7-bit),From address match 0 (10-bit) to address match 1 (10-bit)"
|
|
newline
|
|
bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " IGNACK ,Ignore NACK" "Not ignored,Ignored"
|
|
newline
|
|
bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return receive data and clear RDF,Return address status register and clear AVF when AVF set"
|
|
newline
|
|
bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer when TDR empty,On TDR empty"
|
|
newline
|
|
bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled"
|
|
line.long 0x04 "SCFGR2,Slave Configuration Register 2"
|
|
bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
group.long 0x124++0x07
|
|
line.long 0x00 "SCFGR1,Slave Configuration Register 1"
|
|
bitfld.long 0x00 16.--18. " ADDRCFG ,Address configuration" "Address match 0 (7-bit),Address match 0 (10-bit),Address match 0 (7-bit) or address match 1 (7-bit),Address match 0 (10-bit) or address match 1 (10-bit),Address match 0 (7-bit) or address match 1 (10-bit),Address match 0 (10-bit) or address match 1 (7-bit),From address match 0 (7-bit) to address match 1 (7-bit),From address match 0 (10-bit) to address match 1 (10-bit)"
|
|
newline
|
|
bitfld.long 0x00 13. " HSMEN ,High speed mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " IGNACK ,Ignore NACK" "Not ignored,Ignored"
|
|
newline
|
|
bitfld.long 0x00 11. " RXCFG ,Receive data configuration" "Return receive data and clear RDF,Return address status register and clear AVF when AVF set"
|
|
newline
|
|
bitfld.long 0x00 10. " TXCFG ,Transmit flag configuration" "On slave-transmit transfer when TDR empty,On TDR empty"
|
|
newline
|
|
bitfld.long 0x00 9. " SAEN ,SMBus alert enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GCEN ,General call enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ACKSTALL ,ACK SCL stall" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TXDSTALL ,TX data SCL stall" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RXSTALL ,RX SCL stall" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADRSTALL ,Address SCL stall" "Disabled,Enabled"
|
|
line.long 0x04 "SCFGR2,Slave Configuration Register 2"
|
|
bitfld.long 0x04 24.--27. " FILTSDA ,Glitch filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " FILTSCL ,Glitch filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--13. " DATAVD ,Data valid delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " CLKHOLD ,Clock hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
if (((per.l(ad:0x40042000+0x110))&0x01)==0x00)
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "SAMR,Slave Address Match Register"
|
|
hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value"
|
|
hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value"
|
|
else
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "SAMR,Slave Address Match Register"
|
|
hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value"
|
|
hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value"
|
|
endif
|
|
else
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "SAMR,Slave Address Match Register"
|
|
hexmask.long.word 0x00 17.--26. 0x02 " ADDR1 ,Address 1 value"
|
|
hexmask.long.word 0x00 1.--10. 0x02 " ADDR0 ,Address 0 value"
|
|
endif
|
|
newline
|
|
sif cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("S32K1*")||cpuis("MKS2?FN???V??12")||cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
hgroup.long 0x150++0x03
|
|
hide.long 0x00 "SASR,Slave Address Status Register"
|
|
in
|
|
newline
|
|
else
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "SASR,Slave Address Status Register"
|
|
bitfld.long 0x00 14. " ANV ,Address not valid" "Valid,Invalid"
|
|
hexmask.long.word 0x00 0.--10. 1. " RADDR ,Received address"
|
|
endif
|
|
sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
if (((per.l(ad:0x40042000+0x124))&0x08)==0x08)
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "STAR,Slave Transmit ACK Register"
|
|
bitfld.long 0x00 0. " TXNACK ,Transmit NACK" "No,Yes"
|
|
else
|
|
rgroup.long 0x154++0x03
|
|
line.long 0x00 "STAR,Slave Transmit ACK Register"
|
|
bitfld.long 0x00 0. " TXNACK ,Transmit NACK" "No,Yes"
|
|
endif
|
|
else
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "STAR,Slave Transmit ACK Register"
|
|
bitfld.long 0x00 0. " TXNACK ,Transmit NACK" "No,Yes"
|
|
endif
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "STAR,Slave Transmit ACK Register"
|
|
bitfld.long 0x00 0. " TXNACK ,Transmit NACK" "No,Yes"
|
|
wgroup.long 0x160++0x03
|
|
line.long 0x00 "STDR,Slave Transmit Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit data"
|
|
newline
|
|
hgroup.long 0x170++0x03
|
|
hide.long 0x00 "SRDR,Slave Receive Data Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree.open "I2C (Inter-Integrated Circuit)"
|
|
tree "I2C_0"
|
|
base ad:0x40066000
|
|
width 11.
|
|
group.byte 0x00++0x03
|
|
line.byte 0x00 "I2C0_A1,I2C0 Address Register 1"
|
|
hexmask.byte 0x00 1.--7. 0x02 " AD ,Slave address bits [7:1]"
|
|
line.byte 0x01 "I2C0_F,I2C0 Frequency Divider Register"
|
|
bitfld.byte 0x01 6.--7. " MULT ,Multiplier factor" "1,2,4,?..."
|
|
bitfld.byte 0x01 0.--5. " ICR ,Clock rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x02 "I2C0_C1,I2C0 Control Register 1"
|
|
bitfld.byte 0x02 7. " IICEN ,IIC0 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 6. " IICIE ,IIC0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 5. " MST ,Master mode select" "Slave,Master"
|
|
bitfld.byte 0x02 4. " TX ,Transmit mode select" "Receive,Transmit"
|
|
newline
|
|
bitfld.byte 0x02 3. " TXAK ,Transmit acknowledge enable" "Acknowledged,Not acknowledged"
|
|
bitfld.byte 0x02 2. " RSTA ,Repeat START" "Not started,Started"
|
|
bitfld.byte 0x02 1. " WUEN ,Wakeup enable" "Disabled,Enabled"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03*")
|
|
bitfld.byte 0x02 0. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
line.byte 0x03 "I2C0_S,I2C0 Status Register"
|
|
sif cpuis("MKL02Z*")||cpuis("MKL03Z*")||cpuis("MKL04Z*")||cpuis("MKL05Z*")||cpuis("MKL13Z*")||cpuis("MK14*")||cpuis("MKL14Z*")||cpuis("MK15*")||cpuis("MKL15Z*")||cpuis("MKL16Z*")||cpuis("MKL17Z*")||cpuis("MKL24Z*")||cpuis("MKL25Z*")||cpuis("MKL26Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL43Z*")||cpuis("MKL46Z*")
|
|
rbitfld.byte 0x03 7. " TCF ,Transfer complete flag" "Not completed,Completed"
|
|
bitfld.byte 0x03 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed"
|
|
rbitfld.byte 0x03 5. " BUSY ,Bus busy" "Idle,Busy"
|
|
eventfld.byte 0x03 4. " ARBL ,Arbitration lost" "Not lost,Lost"
|
|
newline
|
|
bitfld.byte 0x03 3. " RAM ,Range address match" "Not matched,Matched"
|
|
rbitfld.byte 0x03 2. " SRW ,Slave read/write" "Read,Write"
|
|
eventfld.byte 0x03 1. " IICIF ,Interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x03 0. " RXAK ,Receive acknowledge" "Acknowledged,Not acknowledged"
|
|
else
|
|
bitfld.byte 0x03 7. " TCF ,Transfer complete flag" "Not completed,Completed"
|
|
bitfld.byte 0x03 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed"
|
|
bitfld.byte 0x03 5. " BUSY ,Bus busy" "Idle,Busy"
|
|
eventfld.byte 0x03 4. " ARBL ,Arbitration lost" "Not lost,Lost"
|
|
newline
|
|
bitfld.byte 0x03 3. " RAM ,Range address match" "Not matched,Matched"
|
|
bitfld.byte 0x03 2. " SRW ,Slave read/write" "Read,Write"
|
|
eventfld.byte 0x03 1. " I2CIF ,Interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x03 0. " RXAK ,Receive acknowledge" "Acknowledged,Not acknowledged"
|
|
endif
|
|
hgroup.byte 0x04++0x01
|
|
hide.byte 0x00 "I2C0_D,I2C0 Data I/O Register"
|
|
in
|
|
if ((per.b(ad:0x40066000+0x05)&0x40)==0x40)
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "I2C0_C2,I2C0 Control Register 2"
|
|
bitfld.byte 0x00 7. " GCAEN ,General call address enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ADEXT ,Address extension" "7-bit,10-bit"
|
|
sif !cpuis("MKL03Z*")
|
|
bitfld.byte 0x00 5. " HDRS ,High drive select" "Normal,High"
|
|
bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master's,Independent"
|
|
else
|
|
bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master's,Independent"
|
|
endif
|
|
newline
|
|
bitfld.byte 0x00 3. " RMEN ,Range address matching enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " AD[10:8] ,Slave address bits [10:8]" "000,001,010,011,100,101,110,111"
|
|
else
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "I2C0_C2,I2C0 Control Register 2"
|
|
bitfld.byte 0x00 7. " GCAEN ,General call address enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ADEXT ,Address extension" "7-bit,10-bit"
|
|
sif !cpuis("MKL03Z*")
|
|
bitfld.byte 0x00 5. " HDRS ,High drive select" "Normal,High"
|
|
bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master's,Independent"
|
|
else
|
|
bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master's,Independent"
|
|
endif
|
|
newline
|
|
bitfld.byte 0x00 3. " RMEN ,Range address matching enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x06++0x01
|
|
line.byte 0x00 "I2C0_FLT,I2C0 Programmable Input Glitch Filter Register"
|
|
sif cpuis("MKL02*")||cpuis("MKL04Z*")||cpuis("MKL05Z*")||cpuis("MK14*")||cpuis("MKL14Z*")||cpuis("MK15*")||cpuis("MKL15Z*")||cpuis("MKL16Z*")||cpuis("MKL24Z*")||cpuis("MKL25Z*")||cpuis("MKL26Z*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")
|
|
bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled"
|
|
eventfld.byte 0x00 6. " STOPF ,I2C0 bus stop detect flag" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 5. " STOPIE ,I2C bus stop interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--4. " FLT ,I2C0 programmable filter factor" "No filter,1 clk,2 clks,3 clks,4 clks,5 clks,6 clks,7 clks,8 clks,9 clks,10 clks,11 clks,12 clks,13 clks,14 clks,15 clks,16 clks,17 clks,18 clks,19 clks,20 clks,21 clks,22 clks,23 clks,24 clks,25 clks,26 clks,27 clks,28 clks,29 clks,30 clks,31 clks"
|
|
elif cpuis("MKL03Z*")||cpuis("MKL13Z*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MKL82Z*")
|
|
bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled"
|
|
eventfld.byte 0x00 6. " STOPF ,I2C0 bus stop detect flag" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 5. " SSIE ,I2C bus stop or start interrupt enable" "Disabled,Enabled"
|
|
eventfld.byte 0x00 4. " STARTF ,I2C bus stop interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. " FLT ,I2C0 programmable filter factor" "No filter,1 clk,2 clks,3 clks,4 clks,5 clks,6 clks,7 clks,8 clks,9 clks,10 clks,11 clks,12 clks,13 clks,14 clks,15 clks"
|
|
else
|
|
bitfld.byte 0x00 0.--4. " FLT ,I2C0 programmable filter factor" "No filter,1 clk,2 clks,3 clks,4 clks,5 clks,6 clks,7 clks,8 clks,9 clks,10 clks,11 clks,12 clks,13 clks,14 clks,15 clks,16 clks,17 clks,18 clks,19 clks,20 clks,21 clks,22 clks,23 clks,24 clks,25 clks,26 clks,27 clks,28 clks,29 clks,30 clks,31 clks"
|
|
endif
|
|
line.byte 0x01 "I2C0_RA,I2C0 Range Address Register"
|
|
hexmask.byte 0x01 1.--7. 0x02 " RAD ,Range slave address"
|
|
sif !cpuis("MKL02*")
|
|
group.byte 0x08++0x03
|
|
line.byte 0x00 "I2C0_SMB,I2C0 Smbus Control And Status Register"
|
|
bitfld.byte 0x00 7. " FACK ,Fast NACK/ACK enable" "NACK/ACK,ACK -> 0 to TXAK / NACK -> 1 to TXAK"
|
|
newline
|
|
bitfld.byte 0x00 6. " ALERTEN ,Smbus alert response address enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SI2CAEN ,Second I2C0 address enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")||cpuis("MKL03Z*")||cpuis("MKL04Z*")||cpuis("MKL05Z*")||cpuis("MKL13Z*")||cpuis("MK14*")||cpuis("MKL14Z*")||cpuis("MK15*")||cpuis("MKL15Z*")||cpuis("MKL16Z*")||cpuis("MKL17Z*")||cpuis("MKL24Z*")||cpuis("MKL25Z*")||cpuis("MKL26Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL43Z*")||cpuis("MKL46Z*")||cpuis("MKL82Z*")
|
|
bitfld.byte 0x00 4. " TCKSEL ,Timeout counter clock select" "Bus clock / 64 freq,Bus clock freq"
|
|
eventfld.byte 0x00 3. " SLTF ,SCL low timeout flag" "Not occurred,Occurred"
|
|
rbitfld.byte 0x00 2. " SHTF1 ,SCL high timeout flag 1" "Not occurred,Occurred"
|
|
newline
|
|
else
|
|
bitfld.byte 0x00 4. " TCKSEL ,Timeout counter clock select" "Bus clock / 64 freq,Bus clock freq"
|
|
eventfld.byte 0x00 3. " SLTF ,SCL low timeout flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " SHTF1 ,SCL high timeout flag 1" "Not occurred,Occurred"
|
|
newline
|
|
endif
|
|
eventfld.byte 0x00 1. " SHTF2 ,SCL high timeout flag 2" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SHTF2IE ,SHTF2 interrupt enable" "Disabled,Enabled"
|
|
line.byte 0x01 "I2C0_A2,I2C0 Address Register 2"
|
|
hexmask.byte 0x01 1.--7. 0x02 " SAD ,Smbus address"
|
|
line.byte 0x02 "I2C0_SLTH,I2C0 SCL Low Timeout High Register"
|
|
line.byte 0x03 "I2C0_SLTL,I2C0 SCL Low Timeout Low Register"
|
|
endif
|
|
sif cpuis("MKL03Z*")||cpuis("MKL13Z*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MKL82Z*")
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "I2C0_S2,I2C Status Register 2"
|
|
sif cpuis("MKL82Z*")
|
|
bitfld.byte 0x00 2. " DFEN ,Double buffer enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
eventfld.byte 0x00 1. " ERROR ,Indicates if there are read or write errors with the tx and rx buffers" "No error,Error"
|
|
rbitfld.byte 0x00 0. " EMPTY ,Indicates if the tx or rx buffer is empty" "Not empty,Empty"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif !cpuis("MKL03*")&&!cpuis("MKL04*")&&!cpuis("MKL05*")
|
|
tree "I2C_1"
|
|
base ad:0x40067000
|
|
width 11.
|
|
group.byte 0x00++0x03
|
|
line.byte 0x00 "I2C1_A1,I2C1 Address Register 1"
|
|
hexmask.byte 0x00 1.--7. 0x02 " AD ,Slave address bits [7:1]"
|
|
line.byte 0x01 "I2C1_F,I2C1 Frequency Divider Register"
|
|
bitfld.byte 0x01 6.--7. " MULT ,Multiplier factor" "1,2,4,?..."
|
|
bitfld.byte 0x01 0.--5. " ICR ,Clock rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x02 "I2C1_C1,I2C1 Control Register 1"
|
|
bitfld.byte 0x02 7. " IICEN ,IIC1 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 6. " IICIE ,IIC1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 5. " MST ,Master mode select" "Slave,Master"
|
|
bitfld.byte 0x02 4. " TX ,Transmit mode select" "Receive,Transmit"
|
|
newline
|
|
bitfld.byte 0x02 3. " TXAK ,Transmit acknowledge enable" "Acknowledged,Not acknowledged"
|
|
bitfld.byte 0x02 2. " RSTA ,Repeat START" "Not started,Started"
|
|
bitfld.byte 0x02 1. " WUEN ,Wakeup enable" "Disabled,Enabled"
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL03*")
|
|
bitfld.byte 0x02 0. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
endif
|
|
line.byte 0x03 "I2C1_S,I2C1 Status Register"
|
|
sif cpuis("MKL02Z*")||cpuis("MKL03Z*")||cpuis("MKL04Z*")||cpuis("MKL05Z*")||cpuis("MKL13Z*")||cpuis("MK14*")||cpuis("MKL14Z*")||cpuis("MK15*")||cpuis("MKL15Z*")||cpuis("MKL16Z*")||cpuis("MKL17Z*")||cpuis("MKL24Z*")||cpuis("MKL25Z*")||cpuis("MKL26Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL43Z*")||cpuis("MKL46Z*")
|
|
rbitfld.byte 0x03 7. " TCF ,Transfer complete flag" "Not completed,Completed"
|
|
bitfld.byte 0x03 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed"
|
|
rbitfld.byte 0x03 5. " BUSY ,Bus busy" "Idle,Busy"
|
|
eventfld.byte 0x03 4. " ARBL ,Arbitration lost" "Not lost,Lost"
|
|
newline
|
|
bitfld.byte 0x03 3. " RAM ,Range address match" "Not matched,Matched"
|
|
rbitfld.byte 0x03 2. " SRW ,Slave read/write" "Read,Write"
|
|
eventfld.byte 0x03 1. " IICIF ,Interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x03 0. " RXAK ,Receive acknowledge" "Acknowledged,Not acknowledged"
|
|
else
|
|
bitfld.byte 0x03 7. " TCF ,Transfer complete flag" "Not completed,Completed"
|
|
bitfld.byte 0x03 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed"
|
|
bitfld.byte 0x03 5. " BUSY ,Bus busy" "Idle,Busy"
|
|
eventfld.byte 0x03 4. " ARBL ,Arbitration lost" "Not lost,Lost"
|
|
newline
|
|
bitfld.byte 0x03 3. " RAM ,Range address match" "Not matched,Matched"
|
|
bitfld.byte 0x03 2. " SRW ,Slave read/write" "Read,Write"
|
|
eventfld.byte 0x03 1. " I2CIF ,Interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x03 0. " RXAK ,Receive acknowledge" "Acknowledged,Not acknowledged"
|
|
endif
|
|
hgroup.byte 0x04++0x01
|
|
hide.byte 0x00 "I2C1_D,I2C1 Data I/O Register"
|
|
in
|
|
if ((per.b(ad:0x40067000+0x05)&0x40)==0x40)
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "I2C1_C2,I2C1 Control Register 2"
|
|
bitfld.byte 0x00 7. " GCAEN ,General call address enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ADEXT ,Address extension" "7-bit,10-bit"
|
|
sif !cpuis("MKL03Z*")
|
|
bitfld.byte 0x00 5. " HDRS ,High drive select" "Normal,High"
|
|
bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master's,Independent"
|
|
else
|
|
bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master's,Independent"
|
|
endif
|
|
newline
|
|
bitfld.byte 0x00 3. " RMEN ,Range address matching enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " AD[10:8] ,Slave address bits [10:8]" "000,001,010,011,100,101,110,111"
|
|
else
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "I2C1_C2,I2C1 Control Register 2"
|
|
bitfld.byte 0x00 7. " GCAEN ,General call address enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ADEXT ,Address extension" "7-bit,10-bit"
|
|
sif !cpuis("MKL03Z*")
|
|
bitfld.byte 0x00 5. " HDRS ,High drive select" "Normal,High"
|
|
bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master's,Independent"
|
|
else
|
|
bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master's,Independent"
|
|
endif
|
|
newline
|
|
bitfld.byte 0x00 3. " RMEN ,Range address matching enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x06++0x01
|
|
line.byte 0x00 "I2C1_FLT,I2C1 Programmable Input Glitch Filter Register"
|
|
sif cpuis("MKL02*")||cpuis("MKL04Z*")||cpuis("MKL05Z*")||cpuis("MK14*")||cpuis("MKL14Z*")||cpuis("MK15*")||cpuis("MKL15Z*")||cpuis("MKL16Z*")||cpuis("MKL24Z*")||cpuis("MKL25Z*")||cpuis("MKL26Z*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")
|
|
bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled"
|
|
eventfld.byte 0x00 6. " STOPF ,I2C1 bus stop detect flag" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 5. " STOPIE ,I2C bus stop interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--4. " FLT ,I2C1 programmable filter factor" "No filter,1 clk,2 clks,3 clks,4 clks,5 clks,6 clks,7 clks,8 clks,9 clks,10 clks,11 clks,12 clks,13 clks,14 clks,15 clks,16 clks,17 clks,18 clks,19 clks,20 clks,21 clks,22 clks,23 clks,24 clks,25 clks,26 clks,27 clks,28 clks,29 clks,30 clks,31 clks"
|
|
elif cpuis("MKL03Z*")||cpuis("MKL13Z*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MKL82Z*")
|
|
bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled"
|
|
eventfld.byte 0x00 6. " STOPF ,I2C1 bus stop detect flag" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 5. " SSIE ,I2C bus stop or start interrupt enable" "Disabled,Enabled"
|
|
eventfld.byte 0x00 4. " STARTF ,I2C bus stop interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. " FLT ,I2C1 programmable filter factor" "No filter,1 clk,2 clks,3 clks,4 clks,5 clks,6 clks,7 clks,8 clks,9 clks,10 clks,11 clks,12 clks,13 clks,14 clks,15 clks"
|
|
else
|
|
bitfld.byte 0x00 0.--4. " FLT ,I2C1 programmable filter factor" "No filter,1 clk,2 clks,3 clks,4 clks,5 clks,6 clks,7 clks,8 clks,9 clks,10 clks,11 clks,12 clks,13 clks,14 clks,15 clks,16 clks,17 clks,18 clks,19 clks,20 clks,21 clks,22 clks,23 clks,24 clks,25 clks,26 clks,27 clks,28 clks,29 clks,30 clks,31 clks"
|
|
endif
|
|
line.byte 0x01 "I2C1_RA,I2C1 Range Address Register"
|
|
hexmask.byte 0x01 1.--7. 0x02 " RAD ,Range slave address"
|
|
sif !cpuis("MKL02*")
|
|
group.byte 0x08++0x03
|
|
line.byte 0x00 "I2C1_SMB,I2C1 Smbus Control And Status Register"
|
|
bitfld.byte 0x00 7. " FACK ,Fast NACK/ACK enable" "NACK/ACK,ACK -> 0 to TXAK / NACK -> 1 to TXAK"
|
|
newline
|
|
bitfld.byte 0x00 6. " ALERTEN ,Smbus alert response address enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SI2CAEN ,Second I2C1 address enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")||cpuis("MKL03Z*")||cpuis("MKL04Z*")||cpuis("MKL05Z*")||cpuis("MKL13Z*")||cpuis("MK14*")||cpuis("MKL14Z*")||cpuis("MK15*")||cpuis("MKL15Z*")||cpuis("MKL16Z*")||cpuis("MKL17Z*")||cpuis("MKL24Z*")||cpuis("MKL25Z*")||cpuis("MKL26Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL43Z*")||cpuis("MKL46Z*")||cpuis("MKL82Z*")
|
|
bitfld.byte 0x00 4. " TCKSEL ,Timeout counter clock select" "Bus clock / 64 freq,Bus clock freq"
|
|
eventfld.byte 0x00 3. " SLTF ,SCL low timeout flag" "Not occurred,Occurred"
|
|
rbitfld.byte 0x00 2. " SHTF1 ,SCL high timeout flag 1" "Not occurred,Occurred"
|
|
newline
|
|
else
|
|
bitfld.byte 0x00 4. " TCKSEL ,Timeout counter clock select" "Bus clock / 64 freq,Bus clock freq"
|
|
eventfld.byte 0x00 3. " SLTF ,SCL low timeout flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " SHTF1 ,SCL high timeout flag 1" "Not occurred,Occurred"
|
|
newline
|
|
endif
|
|
eventfld.byte 0x00 1. " SHTF2 ,SCL high timeout flag 2" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SHTF2IE ,SHTF2 interrupt enable" "Disabled,Enabled"
|
|
line.byte 0x01 "I2C1_A2,I2C1 Address Register 2"
|
|
hexmask.byte 0x01 1.--7. 0x02 " SAD ,Smbus address"
|
|
line.byte 0x02 "I2C1_SLTH,I2C1 SCL Low Timeout High Register"
|
|
line.byte 0x03 "I2C1_SLTL,I2C1 SCL Low Timeout Low Register"
|
|
endif
|
|
sif cpuis("MKL03Z*")||cpuis("MKL13Z*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MKL82Z*")
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "I2C1_S2,I2C Status Register 2"
|
|
sif cpuis("MKL82Z*")
|
|
bitfld.byte 0x00 2. " DFEN ,Double buffer enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
eventfld.byte 0x00 1. " ERROR ,Indicates if there are read or write errors with the tx and rx buffers" "No error,Error"
|
|
rbitfld.byte 0x00 0. " EMPTY ,Indicates if the tx or rx buffer is empty" "Not empty,Empty"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("MKL03Z*")||cpuis("MKL13Z*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MKL82*")
|
|
tree.open "LPUART (Low Power UART)"
|
|
tree "LPUART_0"
|
|
base ad:0x40054000
|
|
width 18.
|
|
sif cpuis("MKL28Z*")
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "LPUART_VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor Version Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature Identification Number"
|
|
line.long 0x04 "LPUART_PARAM,Parameter Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " RXFIFO ,Receive FIFO Size"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TXFIFO ,Transmit FIFO Size"
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "LPUART_GLOBAL,LPUART Global Register"
|
|
bitfld.long 0x00 1. " RST ,Software Reset" "Not reset,Reset"
|
|
line.long 0x04 "LPUART_PINCFG,LPUART Pin Configuration Register"
|
|
bitfld.long 0x04 0.--1. " TRGSEL ,Trigger Select" "Disabled,RXD,CTS,TXD"
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "LPUART_BAUD,LPUART Baud Rate Register"
|
|
bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " M10 ,10-bit mode select" "8bit/9bit,10bit"
|
|
newline
|
|
bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x"
|
|
bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address match,Idle match,Match on/off,RWU enabled"
|
|
bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both"
|
|
bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor"
|
|
line.long 0x04 "LPUART_STAT,LPUART Status Register"
|
|
eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected"
|
|
eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected"
|
|
bitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
newline
|
|
bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected"
|
|
bitfld.long 0x04 26. " BRK13 ,Break character generation length" "10/11/12/13bit,13/14/15/16bit"
|
|
newline
|
|
bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "10/11/12/13bit,11/12/14/15bit"
|
|
rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty"
|
|
newline
|
|
rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle"
|
|
rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full"
|
|
eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Receive overrun"
|
|
eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x04 17. " FE ,Framing error flag" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x04 16. " PF ,Parity error flag" "Not detected,Detected"
|
|
eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal"
|
|
eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal"
|
|
if (((per.l(ad:0x40054000+0x08))&0x80)==0x80)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "LPUART_CTRL,LPUART Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in single-wire mode" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby"
|
|
newline
|
|
bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break"
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars"
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop"
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected"
|
|
bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8bit,9bit"
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark"
|
|
newline
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit"
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "LPUART_CTRL,LPUART Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in single-wire mode" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby"
|
|
newline
|
|
bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break"
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars"
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop"
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8bit,9bit"
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark"
|
|
newline
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit"
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd"
|
|
endif
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "LPUART_DATA,LPUART Data Register"
|
|
in
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "LPUART_MATCH,LPUART Match Address Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " MA2 ,Match address 2"
|
|
hexmask.long.word 0x00 0.--9. 1. " MA1 ,Match address 1"
|
|
group.long 0x14++0x0B
|
|
line.long 0x00 "LPUART_MODIR,LPUART Modem Irda Register"
|
|
bitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RTSWATER ,Receive RTS configuration"
|
|
newline
|
|
bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS Source" "LPUART_CTS pin,Receiver Match"
|
|
bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "Start,Idle"
|
|
bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "No effect,RTSWATER"
|
|
newline
|
|
bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High"
|
|
bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "No effect,Enabled"
|
|
bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled"
|
|
line.long 0x04 "LPUART_FIFO,LPUART FIFO Register"
|
|
rbitfld.long 0x04 23. " TXEMPT ,Transmit buffer/fifo empty" "Not empty,Empty"
|
|
rbitfld.long 0x04 22. " RXEMPT ,Receive buffer/fifo empty" "Not empty,Empty"
|
|
eventfld.long 0x04 17. " TXOF ,Transmitter buffer overflow flag" "No occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 16. " RXUF ,Receiver buffer underflow flag" "No occurred,Occurred"
|
|
bitfld.long 0x04 15. " TXFLUSH ,Transmit fifo/buffer flush" "No effect,Clear"
|
|
bitfld.long 0x04 14. " RXFLUSH ,Receive fifo/buffer flush" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled,1 char.,2 char.,4 char.,8 char.,16 char.,32 char.,64 char."
|
|
bitfld.long 0x04 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " RXUFE ,Receive FIFO underflow interrupt enable" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled"
|
|
rbitfld.long 0x04 4.--6. " TXFIFOSIZE ,Transmit FIFO. Buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,256 datawords"
|
|
bitfld.long 0x04 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x04 0.--2. " RXFIFOSIZE ,Receive FIFO. Buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,256 datawords"
|
|
line.long 0x08 "LPUART_WATER,LPUART Watermark Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " RXCOUNT ,Receive counter"
|
|
hexmask.long.byte 0x08 16.--23. 1. " RXWATER ,Receive watermark"
|
|
hexmask.long.byte 0x08 8.--15. 1. " TXCOUNT ,Transmit counter"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. " TXWATER ,Transmit watermark"
|
|
else
|
|
width 18.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "LPUART0_BAUD,LPUART0 Baud Rate Register"
|
|
bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " M10 ,10-bit mode select" "8bit/9bit,10bit"
|
|
newline
|
|
bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x"
|
|
sif !cpuis("MKL03Z*")
|
|
bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address match,Idle match,Match on/off,RWU enabled"
|
|
bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both"
|
|
bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor"
|
|
line.long 0x04 "LPUART0_STAT,LPUART0 Status Register"
|
|
eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected"
|
|
eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected"
|
|
bitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
newline
|
|
bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected"
|
|
bitfld.long 0x04 26. " BRK13 ,Break character generation length" "10/11/12/13bit,13/14/15/16bit"
|
|
newline
|
|
bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "10/11/12/13bit,11/12/14/15bit"
|
|
rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty"
|
|
newline
|
|
rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle"
|
|
rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full"
|
|
eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Receive overrun"
|
|
eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x04 17. " FE ,Framing error flag" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x04 16. " PF ,Parity error flag" "Not detected,Detected"
|
|
eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal"
|
|
eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal"
|
|
if (((per.l(ad:0x40054000+0x08))&0x80)==0x80)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "LPUART0_CTRL,LPUART0 Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in single-wire mode" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby"
|
|
newline
|
|
bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break"
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars"
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop"
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected"
|
|
bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8bit,9bit"
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark"
|
|
newline
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit"
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "LPUART0_CTRL,LPUART0 Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in single-wire mode" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby"
|
|
newline
|
|
bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break"
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars"
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop"
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8bit,9bit"
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark"
|
|
newline
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit"
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd"
|
|
endif
|
|
sif cpuis("MKL03Z*")||cpuis("MKL13Z*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MKL82Z*")
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "LPUART0_DATA,LPUART0 Data Register"
|
|
in
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "LPUART0_DATA,LPUART0 Data Register"
|
|
rbitfld.long 0x00 15. " NOISY ,DATA[R9:R0] received with noise" "No,Yes"
|
|
rbitfld.long 0x00 14. " PARITYE ,DATA[R9:R0] was received with a parity error" "No,Yes"
|
|
bitfld.long 0x00 13. " FRETSC ,Frame error / transmit special character" "No error/normal char,Error/idle char"
|
|
newline
|
|
rbitfld.long 0x00 12. " RXEMPT ,Receive buffer empty" "Valid data,Not data"
|
|
rbitfld.long 0x00 11. " IDLINE ,Idle line" "Not idle,Idle"
|
|
bitfld.long 0x00 9. " R9T9 ,Read receive data buffer 9 or write transmit data buffer 9" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 8. " R8T8 ,Read receive data buffer 8 or write transmit data buffer 8" "Low,High"
|
|
bitfld.long 0x00 7. " R7T7 ,Read receive data buffer 7 or write transmit data buffer 7" "Low,High"
|
|
bitfld.long 0x00 6. " R6T6 ,Read receive data buffer 6 or write transmit data buffer 6" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " R5T5 ,Read receive data buffer 5 or write transmit data buffer 5" "Low,High"
|
|
bitfld.long 0x00 4. " R4T4 ,Read receive data buffer 4 or write transmit data buffer 4" "Low,High"
|
|
bitfld.long 0x00 3. " R3T3 ,Read receive data buffer 3 or write transmit data buffer 3" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " R2T2 ,Read receive data buffer 2 or write transmit data buffer 2" "Low,High"
|
|
bitfld.long 0x00 1. " R1T1 ,Read receive data buffer 1 or write transmit data buffer 1" "Low,High"
|
|
bitfld.long 0x00 0. " R0T0 ,Read receive data buffer 0 or write transmit data buffer 0" "Low,High"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "LPUART0_MATCH,LPUART0 Match Address Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " MA2 ,Match address 2"
|
|
hexmask.long.word 0x00 0.--9. 1. " MA1 ,Match address 1"
|
|
endif
|
|
sif cpuis("MKL82Z*")
|
|
group.long 0x14++0x0B
|
|
line.long 0x00 "LPUART0_MODIR,LPUART0 Modem Irda Register"
|
|
bitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RTSWATER ,Receive RTS configuration"
|
|
newline
|
|
bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS Source" "LPUART_CTS pin,Receiver Match"
|
|
bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "Start,Idle"
|
|
bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "No effect,RTSWATER"
|
|
newline
|
|
bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High"
|
|
bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "No effect,Enabled"
|
|
bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled"
|
|
line.long 0x04 "LPUART0_FIFO,LPUART0 FIFO Register"
|
|
rbitfld.long 0x04 23. " TXEMPT ,Transmit buffer/fifo empty" "Not empty,Empty"
|
|
rbitfld.long 0x04 22. " RXEMPT ,Receive buffer/fifo empty" "Not empty,Empty"
|
|
eventfld.long 0x04 17. " TXOF ,Transmitter buffer overflow flag" "No occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 16. " RXUF ,Receiver buffer underflow flag" "No occurred,Occurred"
|
|
bitfld.long 0x04 15. " TXFLUSH ,Transmit fifo/buffer flush" "No effect,Clear"
|
|
bitfld.long 0x04 14. " RXFLUSH ,Receive fifo/buffer flush" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled,1 char.,2 char.,4 char.,8 char.,16 char.,32 char.,64 char."
|
|
bitfld.long 0x04 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " RXUFE ,Receive FIFO underflow interrupt enable" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled"
|
|
rbitfld.long 0x04 4.--6. " TXFIFOSIZE ,Transmit FIFO. Buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,256 datawords"
|
|
bitfld.long 0x04 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x04 0.--2. " RXFIFOSIZE ,Receive FIFO. Buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,256 datawords"
|
|
line.long 0x08 "LPUART0_WATER,LPUART0 Watermark Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " RXCOUNT ,Receive counter"
|
|
hexmask.long.byte 0x08 16.--23. 1. " RXWATER ,Receive watermark"
|
|
hexmask.long.byte 0x08 8.--15. 1. " TXCOUNT ,Transmit counter"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. " TXWATER ,Transmit watermark"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif !cpuis("MKL03Z*")
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tree "LPUART_1"
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base ad:0x40055000
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width 18.
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sif cpuis("MKL28Z*")
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rgroup.long 0x00++0x07
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line.long 0x00 "LPUART_VERID,Version ID Register"
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hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major Version Number"
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hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor Version Number"
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hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature Identification Number"
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line.long 0x04 "LPUART_PARAM,Parameter Register"
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hexmask.long.byte 0x04 8.--15. 1. " RXFIFO ,Receive FIFO Size"
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hexmask.long.byte 0x04 0.--7. 1. " TXFIFO ,Transmit FIFO Size"
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group.long 0x08++0x07
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line.long 0x00 "LPUART_GLOBAL,LPUART Global Register"
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bitfld.long 0x00 1. " RST ,Software Reset" "Not reset,Reset"
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line.long 0x04 "LPUART_PINCFG,LPUART Pin Configuration Register"
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bitfld.long 0x04 0.--1. " TRGSEL ,Trigger Select" "Disabled,RXD,CTS,TXD"
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group.long 0x10++0x07
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line.long 0x00 "LPUART_BAUD,LPUART Baud Rate Register"
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bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled"
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bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled"
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bitfld.long 0x00 29. " M10 ,10-bit mode select" "8bit/9bit,10bit"
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newline
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bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x"
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bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled"
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bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled"
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newline
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bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address match,Idle match,Match on/off,RWU enabled"
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bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both"
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bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes"
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newline
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bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled"
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bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled"
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bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits"
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newline
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hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor"
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line.long 0x04 "LPUART_STAT,LPUART Status Register"
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eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected"
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eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected"
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bitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first"
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newline
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bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
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bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected"
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bitfld.long 0x04 26. " BRK13 ,Break character generation length" "10/11/12/13bit,13/14/15/16bit"
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newline
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bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "10/11/12/13bit,11/12/14/15bit"
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rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active"
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rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty"
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newline
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rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle"
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rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full"
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eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected"
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newline
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|
eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Receive overrun"
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|
eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected"
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eventfld.long 0x04 17. " FE ,Framing error flag" "Not detected,Detected"
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newline
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eventfld.long 0x04 16. " PF ,Parity error flag" "Not detected,Detected"
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eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal"
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eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal"
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if (((per.l(ad:0x40055000+0x08))&0x80)==0x80)
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group.long 0x08++0x03
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line.long 0x00 "LPUART_CTRL,LPUART Control Register"
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bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High"
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bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High"
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bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in single-wire mode" "Input,Output"
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newline
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bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
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bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
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bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
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newline
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bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
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bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
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bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
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newline
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bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
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bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
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bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
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newline
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bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
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bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
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bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby"
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newline
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bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break"
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bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
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bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
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newline
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bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars"
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bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop"
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bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
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newline
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bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected"
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bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8bit,9bit"
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bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark"
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newline
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bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit"
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bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
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bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd"
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else
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group.long 0x08++0x03
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line.long 0x00 "LPUART_CTRL,LPUART Control Register"
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bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High"
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bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High"
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bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in single-wire mode" "Input,Output"
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newline
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bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
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bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
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bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
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newline
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bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
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bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
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|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
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|
newline
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bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
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bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
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bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
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newline
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bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
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bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
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bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby"
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newline
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bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break"
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bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
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bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
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newline
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bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars"
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bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop"
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bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
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newline
|
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bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8bit,9bit"
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bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark"
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newline
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bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit"
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bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
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bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd"
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endif
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hgroup.long 0x0C++0x03
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hide.long 0x00 "LPUART_DATA,LPUART Data Register"
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in
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group.long 0x10++0x03
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line.long 0x00 "LPUART_MATCH,LPUART Match Address Register"
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hexmask.long.word 0x00 16.--25. 1. " MA2 ,Match address 2"
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hexmask.long.word 0x00 0.--9. 1. " MA1 ,Match address 1"
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group.long 0x14++0x0B
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line.long 0x00 "LPUART_MODIR,LPUART Modem Irda Register"
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bitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled"
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bitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR"
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hexmask.long.byte 0x00 8.--15. 1. " RTSWATER ,Receive RTS configuration"
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newline
|
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bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS Source" "LPUART_CTS pin,Receiver Match"
|
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bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "Start,Idle"
|
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bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "No effect,RTSWATER"
|
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newline
|
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bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High"
|
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bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "No effect,Enabled"
|
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bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled"
|
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line.long 0x04 "LPUART_FIFO,LPUART FIFO Register"
|
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rbitfld.long 0x04 23. " TXEMPT ,Transmit buffer/fifo empty" "Not empty,Empty"
|
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rbitfld.long 0x04 22. " RXEMPT ,Receive buffer/fifo empty" "Not empty,Empty"
|
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eventfld.long 0x04 17. " TXOF ,Transmitter buffer overflow flag" "No occurred,Occurred"
|
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newline
|
|
eventfld.long 0x04 16. " RXUF ,Receiver buffer underflow flag" "No occurred,Occurred"
|
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bitfld.long 0x04 15. " TXFLUSH ,Transmit fifo/buffer flush" "No effect,Clear"
|
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bitfld.long 0x04 14. " RXFLUSH ,Receive fifo/buffer flush" "No effect,Clear"
|
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newline
|
|
bitfld.long 0x04 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled,1 char.,2 char.,4 char.,8 char.,16 char.,32 char.,64 char."
|
|
bitfld.long 0x04 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " RXUFE ,Receive FIFO underflow interrupt enable" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled"
|
|
rbitfld.long 0x04 4.--6. " TXFIFOSIZE ,Transmit FIFO. Buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,256 datawords"
|
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bitfld.long 0x04 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x04 0.--2. " RXFIFOSIZE ,Receive FIFO. Buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,256 datawords"
|
|
line.long 0x08 "LPUART_WATER,LPUART Watermark Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " RXCOUNT ,Receive counter"
|
|
hexmask.long.byte 0x08 16.--23. 1. " RXWATER ,Receive watermark"
|
|
hexmask.long.byte 0x08 8.--15. 1. " TXCOUNT ,Transmit counter"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. " TXWATER ,Transmit watermark"
|
|
else
|
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width 18.
|
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group.long 0x00++0x07
|
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line.long 0x00 "LPUART1_BAUD,LPUART1 Baud Rate Register"
|
|
bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " M10 ,10-bit mode select" "8bit/9bit,10bit"
|
|
newline
|
|
bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x"
|
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sif !cpuis("MKL03Z*")
|
|
bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address match,Idle match,Match on/off,RWU enabled"
|
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bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both"
|
|
bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor"
|
|
line.long 0x04 "LPUART1_STAT,LPUART1 Status Register"
|
|
eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected"
|
|
eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected"
|
|
bitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
newline
|
|
bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected"
|
|
bitfld.long 0x04 26. " BRK13 ,Break character generation length" "10/11/12/13bit,13/14/15/16bit"
|
|
newline
|
|
bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "10/11/12/13bit,11/12/14/15bit"
|
|
rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty"
|
|
newline
|
|
rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle"
|
|
rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full"
|
|
eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Receive overrun"
|
|
eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x04 17. " FE ,Framing error flag" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x04 16. " PF ,Parity error flag" "Not detected,Detected"
|
|
eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal"
|
|
eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal"
|
|
if (((per.l(ad:0x40055000+0x08))&0x80)==0x80)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "LPUART1_CTRL,LPUART1 Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in single-wire mode" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby"
|
|
newline
|
|
bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break"
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars"
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop"
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected"
|
|
bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8bit,9bit"
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark"
|
|
newline
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit"
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "LPUART1_CTRL,LPUART1 Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in single-wire mode" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby"
|
|
newline
|
|
bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break"
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars"
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop"
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8bit,9bit"
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark"
|
|
newline
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit"
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd"
|
|
endif
|
|
sif cpuis("MKL03Z*")||cpuis("MKL13Z*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MKL82Z*")
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "LPUART1_DATA,LPUART1 Data Register"
|
|
in
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "LPUART1_DATA,LPUART1 Data Register"
|
|
rbitfld.long 0x00 15. " NOISY ,DATA[R9:R0] received with noise" "No,Yes"
|
|
rbitfld.long 0x00 14. " PARITYE ,DATA[R9:R0] was received with a parity error" "No,Yes"
|
|
bitfld.long 0x00 13. " FRETSC ,Frame error / transmit special character" "No error/normal char,Error/idle char"
|
|
newline
|
|
rbitfld.long 0x00 12. " RXEMPT ,Receive buffer empty" "Valid data,Not data"
|
|
rbitfld.long 0x00 11. " IDLINE ,Idle line" "Not idle,Idle"
|
|
bitfld.long 0x00 9. " R9T9 ,Read receive data buffer 9 or write transmit data buffer 9" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 8. " R8T8 ,Read receive data buffer 8 or write transmit data buffer 8" "Low,High"
|
|
bitfld.long 0x00 7. " R7T7 ,Read receive data buffer 7 or write transmit data buffer 7" "Low,High"
|
|
bitfld.long 0x00 6. " R6T6 ,Read receive data buffer 6 or write transmit data buffer 6" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " R5T5 ,Read receive data buffer 5 or write transmit data buffer 5" "Low,High"
|
|
bitfld.long 0x00 4. " R4T4 ,Read receive data buffer 4 or write transmit data buffer 4" "Low,High"
|
|
bitfld.long 0x00 3. " R3T3 ,Read receive data buffer 3 or write transmit data buffer 3" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " R2T2 ,Read receive data buffer 2 or write transmit data buffer 2" "Low,High"
|
|
bitfld.long 0x00 1. " R1T1 ,Read receive data buffer 1 or write transmit data buffer 1" "Low,High"
|
|
bitfld.long 0x00 0. " R0T0 ,Read receive data buffer 0 or write transmit data buffer 0" "Low,High"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "LPUART1_MATCH,LPUART1 Match Address Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " MA2 ,Match address 2"
|
|
hexmask.long.word 0x00 0.--9. 1. " MA1 ,Match address 1"
|
|
endif
|
|
sif cpuis("MKL82Z*")
|
|
group.long 0x14++0x0B
|
|
line.long 0x00 "LPUART1_MODIR,LPUART1 Modem Irda Register"
|
|
bitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RTSWATER ,Receive RTS configuration"
|
|
newline
|
|
bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS Source" "LPUART_CTS pin,Receiver Match"
|
|
bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "Start,Idle"
|
|
bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "No effect,RTSWATER"
|
|
newline
|
|
bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High"
|
|
bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "No effect,Enabled"
|
|
bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled"
|
|
line.long 0x04 "LPUART1_FIFO,LPUART1 FIFO Register"
|
|
rbitfld.long 0x04 23. " TXEMPT ,Transmit buffer/fifo empty" "Not empty,Empty"
|
|
rbitfld.long 0x04 22. " RXEMPT ,Receive buffer/fifo empty" "Not empty,Empty"
|
|
eventfld.long 0x04 17. " TXOF ,Transmitter buffer overflow flag" "No occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 16. " RXUF ,Receiver buffer underflow flag" "No occurred,Occurred"
|
|
bitfld.long 0x04 15. " TXFLUSH ,Transmit fifo/buffer flush" "No effect,Clear"
|
|
bitfld.long 0x04 14. " RXFLUSH ,Receive fifo/buffer flush" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled,1 char.,2 char.,4 char.,8 char.,16 char.,32 char.,64 char."
|
|
bitfld.long 0x04 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " RXUFE ,Receive FIFO underflow interrupt enable" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled"
|
|
rbitfld.long 0x04 4.--6. " TXFIFOSIZE ,Transmit FIFO. Buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,256 datawords"
|
|
bitfld.long 0x04 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x04 0.--2. " RXFIFOSIZE ,Receive FIFO. Buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,256 datawords"
|
|
line.long 0x08 "LPUART1_WATER,LPUART1 Watermark Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " RXCOUNT ,Receive counter"
|
|
hexmask.long.byte 0x08 16.--23. 1. " RXWATER ,Receive watermark"
|
|
hexmask.long.byte 0x08 8.--15. 1. " TXCOUNT ,Transmit counter"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. " TXWATER ,Transmit watermark"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif cpuis("MKL82Z*")
|
|
tree "LPUART_2"
|
|
base ad:0x40056000
|
|
width 18.
|
|
sif cpuis("MKL28Z*")
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "LPUART_VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor Version Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature Identification Number"
|
|
line.long 0x04 "LPUART_PARAM,Parameter Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " RXFIFO ,Receive FIFO Size"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TXFIFO ,Transmit FIFO Size"
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "LPUART_GLOBAL,LPUART Global Register"
|
|
bitfld.long 0x00 1. " RST ,Software Reset" "Not reset,Reset"
|
|
line.long 0x04 "LPUART_PINCFG,LPUART Pin Configuration Register"
|
|
bitfld.long 0x04 0.--1. " TRGSEL ,Trigger Select" "Disabled,RXD,CTS,TXD"
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "LPUART_BAUD,LPUART Baud Rate Register"
|
|
bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " M10 ,10-bit mode select" "8bit/9bit,10bit"
|
|
newline
|
|
bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x"
|
|
bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address match,Idle match,Match on/off,RWU enabled"
|
|
bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both"
|
|
bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor"
|
|
line.long 0x04 "LPUART_STAT,LPUART Status Register"
|
|
eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected"
|
|
eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected"
|
|
bitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
newline
|
|
bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected"
|
|
bitfld.long 0x04 26. " BRK13 ,Break character generation length" "10/11/12/13bit,13/14/15/16bit"
|
|
newline
|
|
bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "10/11/12/13bit,11/12/14/15bit"
|
|
rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty"
|
|
newline
|
|
rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle"
|
|
rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full"
|
|
eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Receive overrun"
|
|
eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x04 17. " FE ,Framing error flag" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x04 16. " PF ,Parity error flag" "Not detected,Detected"
|
|
eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal"
|
|
eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal"
|
|
if (((per.l(ad:0x40056000+0x08))&0x80)==0x80)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "LPUART_CTRL,LPUART Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in single-wire mode" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby"
|
|
newline
|
|
bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break"
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars"
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop"
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected"
|
|
bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8bit,9bit"
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark"
|
|
newline
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit"
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "LPUART_CTRL,LPUART Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in single-wire mode" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby"
|
|
newline
|
|
bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break"
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars"
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop"
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8bit,9bit"
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark"
|
|
newline
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit"
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd"
|
|
endif
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "LPUART_DATA,LPUART Data Register"
|
|
in
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "LPUART_MATCH,LPUART Match Address Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " MA2 ,Match address 2"
|
|
hexmask.long.word 0x00 0.--9. 1. " MA1 ,Match address 1"
|
|
group.long 0x14++0x0B
|
|
line.long 0x00 "LPUART_MODIR,LPUART Modem Irda Register"
|
|
bitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RTSWATER ,Receive RTS configuration"
|
|
newline
|
|
bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS Source" "LPUART_CTS pin,Receiver Match"
|
|
bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "Start,Idle"
|
|
bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "No effect,RTSWATER"
|
|
newline
|
|
bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High"
|
|
bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "No effect,Enabled"
|
|
bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled"
|
|
line.long 0x04 "LPUART_FIFO,LPUART FIFO Register"
|
|
rbitfld.long 0x04 23. " TXEMPT ,Transmit buffer/fifo empty" "Not empty,Empty"
|
|
rbitfld.long 0x04 22. " RXEMPT ,Receive buffer/fifo empty" "Not empty,Empty"
|
|
eventfld.long 0x04 17. " TXOF ,Transmitter buffer overflow flag" "No occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 16. " RXUF ,Receiver buffer underflow flag" "No occurred,Occurred"
|
|
bitfld.long 0x04 15. " TXFLUSH ,Transmit fifo/buffer flush" "No effect,Clear"
|
|
bitfld.long 0x04 14. " RXFLUSH ,Receive fifo/buffer flush" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled,1 char.,2 char.,4 char.,8 char.,16 char.,32 char.,64 char."
|
|
bitfld.long 0x04 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " RXUFE ,Receive FIFO underflow interrupt enable" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled"
|
|
rbitfld.long 0x04 4.--6. " TXFIFOSIZE ,Transmit FIFO. Buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,256 datawords"
|
|
bitfld.long 0x04 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x04 0.--2. " RXFIFOSIZE ,Receive FIFO. Buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,256 datawords"
|
|
line.long 0x08 "LPUART_WATER,LPUART Watermark Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " RXCOUNT ,Receive counter"
|
|
hexmask.long.byte 0x08 16.--23. 1. " RXWATER ,Receive watermark"
|
|
hexmask.long.byte 0x08 8.--15. 1. " TXCOUNT ,Transmit counter"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. " TXWATER ,Transmit watermark"
|
|
else
|
|
width 18.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "LPUART1_BAUD,LPUART1 Baud Rate Register"
|
|
bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " M10 ,10-bit mode select" "8bit/9bit,10bit"
|
|
newline
|
|
bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x"
|
|
sif !cpuis("MKL03Z*")
|
|
bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address match,Idle match,Match on/off,RWU enabled"
|
|
bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both"
|
|
bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor"
|
|
line.long 0x04 "LPUART1_STAT,LPUART1 Status Register"
|
|
eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected"
|
|
eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected"
|
|
bitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
newline
|
|
bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected"
|
|
bitfld.long 0x04 26. " BRK13 ,Break character generation length" "10/11/12/13bit,13/14/15/16bit"
|
|
newline
|
|
bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "10/11/12/13bit,11/12/14/15bit"
|
|
rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty"
|
|
newline
|
|
rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle"
|
|
rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full"
|
|
eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Receive overrun"
|
|
eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x04 17. " FE ,Framing error flag" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x04 16. " PF ,Parity error flag" "Not detected,Detected"
|
|
eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal"
|
|
eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal"
|
|
if (((per.l(ad:0x40056000+0x08))&0x80)==0x80)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "LPUART1_CTRL,LPUART1 Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in single-wire mode" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby"
|
|
newline
|
|
bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break"
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars"
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop"
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected"
|
|
bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8bit,9bit"
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark"
|
|
newline
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit"
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "LPUART1_CTRL,LPUART1 Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in single-wire mode" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby"
|
|
newline
|
|
bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break"
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars"
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop"
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8bit,9bit"
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark"
|
|
newline
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit"
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd"
|
|
endif
|
|
sif cpuis("MKL03Z*")||cpuis("MKL13Z*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MKL82Z*")
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "LPUART1_DATA,LPUART1 Data Register"
|
|
in
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "LPUART1_DATA,LPUART1 Data Register"
|
|
rbitfld.long 0x00 15. " NOISY ,DATA[R9:R0] received with noise" "No,Yes"
|
|
rbitfld.long 0x00 14. " PARITYE ,DATA[R9:R0] was received with a parity error" "No,Yes"
|
|
bitfld.long 0x00 13. " FRETSC ,Frame error / transmit special character" "No error/normal char,Error/idle char"
|
|
newline
|
|
rbitfld.long 0x00 12. " RXEMPT ,Receive buffer empty" "Valid data,Not data"
|
|
rbitfld.long 0x00 11. " IDLINE ,Idle line" "Not idle,Idle"
|
|
bitfld.long 0x00 9. " R9T9 ,Read receive data buffer 9 or write transmit data buffer 9" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 8. " R8T8 ,Read receive data buffer 8 or write transmit data buffer 8" "Low,High"
|
|
bitfld.long 0x00 7. " R7T7 ,Read receive data buffer 7 or write transmit data buffer 7" "Low,High"
|
|
bitfld.long 0x00 6. " R6T6 ,Read receive data buffer 6 or write transmit data buffer 6" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " R5T5 ,Read receive data buffer 5 or write transmit data buffer 5" "Low,High"
|
|
bitfld.long 0x00 4. " R4T4 ,Read receive data buffer 4 or write transmit data buffer 4" "Low,High"
|
|
bitfld.long 0x00 3. " R3T3 ,Read receive data buffer 3 or write transmit data buffer 3" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " R2T2 ,Read receive data buffer 2 or write transmit data buffer 2" "Low,High"
|
|
bitfld.long 0x00 1. " R1T1 ,Read receive data buffer 1 or write transmit data buffer 1" "Low,High"
|
|
bitfld.long 0x00 0. " R0T0 ,Read receive data buffer 0 or write transmit data buffer 0" "Low,High"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "LPUART1_MATCH,LPUART1 Match Address Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " MA2 ,Match address 2"
|
|
hexmask.long.word 0x00 0.--9. 1. " MA1 ,Match address 1"
|
|
endif
|
|
sif cpuis("MKL82Z*")
|
|
group.long 0x14++0x0B
|
|
line.long 0x00 "LPUART1_MODIR,LPUART1 Modem Irda Register"
|
|
bitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RTSWATER ,Receive RTS configuration"
|
|
newline
|
|
bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS Source" "LPUART_CTS pin,Receiver Match"
|
|
bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "Start,Idle"
|
|
bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "No effect,RTSWATER"
|
|
newline
|
|
bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High"
|
|
bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "No effect,Enabled"
|
|
bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled"
|
|
line.long 0x04 "LPUART1_FIFO,LPUART1 FIFO Register"
|
|
rbitfld.long 0x04 23. " TXEMPT ,Transmit buffer/fifo empty" "Not empty,Empty"
|
|
rbitfld.long 0x04 22. " RXEMPT ,Receive buffer/fifo empty" "Not empty,Empty"
|
|
eventfld.long 0x04 17. " TXOF ,Transmitter buffer overflow flag" "No occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 16. " RXUF ,Receiver buffer underflow flag" "No occurred,Occurred"
|
|
bitfld.long 0x04 15. " TXFLUSH ,Transmit fifo/buffer flush" "No effect,Clear"
|
|
bitfld.long 0x04 14. " RXFLUSH ,Receive fifo/buffer flush" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled,1 char.,2 char.,4 char.,8 char.,16 char.,32 char.,64 char."
|
|
bitfld.long 0x04 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " RXUFE ,Receive FIFO underflow interrupt enable" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled"
|
|
rbitfld.long 0x04 4.--6. " TXFIFOSIZE ,Transmit FIFO. Buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,256 datawords"
|
|
bitfld.long 0x04 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x04 0.--2. " RXFIFOSIZE ,Receive FIFO. Buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,256 datawords"
|
|
line.long 0x08 "LPUART1_WATER,LPUART1 Watermark Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " RXCOUNT ,Receive counter"
|
|
hexmask.long.byte 0x08 16.--23. 1. " RXWATER ,Receive watermark"
|
|
hexmask.long.byte 0x08 8.--15. 1. " TXCOUNT ,Transmit counter"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. " TXWATER ,Transmit watermark"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif !cpuis("MKL03Z*")
|
|
tree.open "UART (Universal Asynchronous Receiver/Transmitter)"
|
|
tree "UART_2"
|
|
base ad:0x4006C000
|
|
width 11.
|
|
group.byte 0x00++0x03 "UART2 Standard Features Registers"
|
|
line.byte 0x00 "UART2_BDH,UART Baud Rate Register High"
|
|
bitfld.byte 0x00 6. " RXEDGIE ,Rxd input active edge interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--4. " SBR ,UART baud rate bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x01 "UART2_BDL,UART Baud Rate Register Low"
|
|
line.byte 0x02 "UART2_C1,UART Control Register 1"
|
|
bitfld.byte 0x02 7. " LOOPS ,Loop mode select" "Not selected,Selected"
|
|
bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Internal loop-back mode,Single-wire UART"
|
|
bitfld.byte 0x02 4. " M ,9-bit or 8-bit mode select" "Normal 8 bits+stop,Use 9 bits+stop"
|
|
textline " "
|
|
bitfld.byte 0x02 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark"
|
|
bitfld.byte 0x02 2. " ILT ,Idle line type select" "After start bit,After stop bit"
|
|
bitfld.byte 0x02 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x02 0. " PT ,Parity type" "Even,Odd"
|
|
line.byte 0x03 "UART2_C2,UART Control Register 2"
|
|
bitfld.byte 0x03 7. " TIE ,Transmitter interrupt or DMA transfer enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 6. " TCIE ,Transmission complete interrupt or DMA transfer enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 5. " RIE ,Receiver full interrupt or DMA transfer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x03 4. " ILIE ,Idle line interrupt or DMA transfer enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " RWU ,Receiver wakeup control" "Normal,Wake-up"
|
|
bitfld.byte 0x03 0. " SBK ,Send break" "Normal,Break"
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "UART2_S1,UART Status Register 1"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred"
|
|
group.byte 0x05++0x01
|
|
line.byte 0x00 "UART2_S2,UART Status Register 2"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,Rxd pin active edge interrupt flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first"
|
|
bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bit long,13/14 bit long"
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active"
|
|
line.byte 0x01 "UART2_C3,UART Control Register 3"
|
|
rbitfld.byte 0x01 7. " R8 ,Received bit 8" "No RX,RX"
|
|
bitfld.byte 0x01 6. " T8 ,Transmit bit 8" "No TX,TX"
|
|
bitfld.byte 0x01 5. " TXDIR ,Transmitter pin data direction in single-wire mode" "Input,Output"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x01 3. " ORIE ,Overrun error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
hgroup.byte 0x07++0x00
|
|
hide.byte 0x00 "UART2_D,UART Data Register"
|
|
in
|
|
group.byte 0x08++0x03
|
|
line.byte 0x00 "UART2_MA1,UART Match Address Registers 1"
|
|
line.byte 0x01 "UART2_MA2,UART Match Address Registers 2"
|
|
line.byte 0x02 "UART2_C4,UART Control Register 4"
|
|
bitfld.byte 0x02 7. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled"
|
|
bitfld.byte 0x02 6. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled"
|
|
bitfld.byte 0x02 5. " M10 ,10-bit mode select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x02 0.--4. " BRFA ,Baud rate fine adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x03 "UART2_C5,UART Control Register 5"
|
|
bitfld.byte 0x03 7. " TDMAS ,Transmitter DMA select" "Interrupt service,DMA transfer"
|
|
bitfld.byte 0x03 5. " RDMAS ,Receiver full DMA select" "Interrupt service,DMA transfer"
|
|
textline " "
|
|
width 18.
|
|
if ((per.b(ad:0x4006C000+0x18)&0x1)==0x1)
|
|
group.byte 0x18++0x00 "UART_2 ISO7816 Registers"
|
|
line.byte 0x00 "UART2_C7816,UART 7816 Control Register"
|
|
rbitfld.byte 0x00 4. " ONACK ,Generate NACK on overflow" "Not generated,Generated"
|
|
rbitfld.byte 0x00 3. " ANACK ,Generate NACK on error" "Not generated,Generated"
|
|
rbitfld.byte 0x00 2. " INIT ,Detect initial character" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TTYPE ,Transfer type" "0 per the ISO-7816,1 per the ISO-7816"
|
|
bitfld.byte 0x00 0. " ISO_7816E ,ISO-7816 functionality enabled" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x18++0x00 "UART_2 ISO7816 Registers"
|
|
line.byte 0x00 "UART2_C7816,UART 7816 Control Register"
|
|
bitfld.byte 0x00 4. " ONACK ,Generate NACK on overflow" "Not generated,Generated"
|
|
bitfld.byte 0x00 3. " ANACK ,Generate NACK on error" "Not generated,Generated"
|
|
bitfld.byte 0x00 2. " INIT ,Detect initial character" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TTYPE ,Transfer type" "0 per the ISO-7816,1 per the ISO-7816"
|
|
bitfld.byte 0x00 0. " ISO_7816E ,ISO-7816 functionality enabled" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "UART2_IE7816,UART 7816 Interrupt Enable Register"
|
|
bitfld.byte 0x00 7. " WTE ,Wait timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CWTE ,Character wait timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " BWTE ,Block wait timer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " INITDE ,Initial character detected interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " ADTE ,ATR duration timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " GTVE ,Guard timer violated interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TXTE ,Transmit threshold exceeded interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " RXTE ,Receive threshold exceeded interrupt enable" "Disabled,Enabled"
|
|
line.byte 0x01 "UART2_IS7816,UART 7816 Interrupt Status Register"
|
|
eventfld.byte 0x01 7. " WT ,Wait timer interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x01 6. " CWT ,Character wait timer interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x01 5. " BWT ,Block wait timer interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.byte 0x01 4. " INITD ,Initial character detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x01 2. " GTV ,Guard timer violated interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x01 1. " TXT ,Transmit threshold exceeded interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.byte 0x01 0. " RXT ,Receive threshold exceeded interrupt" "No interrupt,Interrupt"
|
|
if ((per.b(ad:0x4006C000+0x18)&0x02)==0x02)&&((per.b(ad:0x4006C000+0x18)&0x01)==0x00)
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "UART2_WP7816T0,UART 7816 Wait Parameter Register"
|
|
elif ((per.b(ad:0x4006C000+0x18)&0x02)==0x02)&&((per.b(ad:0x4006C000+0x18)&0x01)==0x01)
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "UART2_WP7816T0,UART 7816 Wait Parameter Register"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "UART2_WP7816T0,UART 7816 Wait Parameter Register"
|
|
endif
|
|
if ((per.b(ad:0x4006C000+0x18)&0x01)==0x00)
|
|
group.byte 0x1C++0x02
|
|
line.byte 0x00 "UART2_WN7816,UART 7816 Wait N Register"
|
|
line.byte 0x01 "UART2_WF7816,UART 7816 Wait FD Register"
|
|
line.byte 0x02 "UART2_ET7816,UART 7816 Error Threshold Register"
|
|
bitfld.byte 0x02 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x02 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.byte 0x1C++0x02
|
|
line.byte 0x00 "UART2_WN7816,UART 7816 Wait N Register"
|
|
line.byte 0x01 "UART2_WF7816,UART 7816 Wait FD Register"
|
|
line.byte 0x02 "UART2_ET7816,UART 7816 Error Threshold Register"
|
|
bitfld.byte 0x02 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x02 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if ((per.b(ad:0x4006C000+0x18)&0x02)==0x00)
|
|
hgroup.byte 0x1F++0x00
|
|
hide.byte 0x00 "UART2_TL7816,UART 7816 Transmit Length Register"
|
|
elif ((per.b(ad:0x4006C000+0x03)&0x08)==0x00)
|
|
group.byte 0x1F++0x00
|
|
line.byte 0x00 "UART2_TL7816,UART 7816 Transmit Length Register"
|
|
else
|
|
rgroup.byte 0x1F++0x00
|
|
line.byte 0x00 "UART2_TL7816,UART 7816 Transmit Length Register"
|
|
endif
|
|
if ((per.b(ad:0x4006C000+0x18)&0x02)==0x00)
|
|
group.byte 0x3A++0x01
|
|
line.byte 0x00 "UART2_AP7816A_T0,UART 7816 ATR Duration Timer Register A"
|
|
line.byte 0x01 "UART2_AP7816B_T0,UART 7816 ATR Duration Timer Register B"
|
|
else
|
|
hgroup.byte 0x3A++0x01
|
|
hide.byte 0x00 "UART2_AP7816A_T0,UART 7816 ATR Duration Timer Register A"
|
|
hide.byte 0x01 "UART2_AP7816B_T0,UART 7816 ATR Duration Timer Register B"
|
|
endif
|
|
if ((per.b(ad:0x4006C000+0x18)&0x03)==0x00)
|
|
group.byte 0x3C++0x01
|
|
line.byte 0x00 "UART2_WP7816A_T0,UART 7816 Wait Parameter Register A"
|
|
line.byte 0x01 "UART2_WP7816B_T0,UART 7816 Wait Parameter Register B"
|
|
hgroup.byte 0x3E++0x01
|
|
hide.byte 0x00 "UART2_WGP7816_T1,UART 7816 Wait And Guard Parameter Register"
|
|
hide.byte 0x01 "UART2_WP7816C_T1,UART 7816 Wait Parameter Register C"
|
|
elif ((per.b(ad:0x4006C000+0x18)&0x03)==0x01)
|
|
rgroup.byte 0x3C++0x01
|
|
line.byte 0x00 "UART2_WP7816A_T0,UART 7816 Wait Parameter Register A"
|
|
line.byte 0x01 "UART2_WP7816B_T0,UART 7816 Wait Parameter Register B"
|
|
hgroup.byte 0x3E++0x01
|
|
hide.byte 0x00 "UART2_WGP7816_T1,UART 7816 Wait And Guard Parameter Register"
|
|
hide.byte 0x01 "UART2_WP7816C_T1,UART 7816 Wait Parameter Register C"
|
|
elif ((per.b(ad:0x4006C000+0x18)&0x03)==0x02)
|
|
group.byte 0x3C++0x03
|
|
line.byte 0x00 "UART2_WP7816A_T1,UART 7816 Wait Parameter Register A"
|
|
line.byte 0x01 "UART2_WP7816B_T1,UART 7816 Wait Parameter Register B"
|
|
line.byte 0x02 "UART2_WGP7816_T1,UART 7816 Wait And Guard Parameter Register"
|
|
bitfld.byte 0x02 4.--7. " CWI_1 ,Character wait time integer 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x02 0.--3. " BGI ,Block guard time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x03 "UART2_WP7816C_T1,UART 7816 Wait Parameter Register C"
|
|
bitfld.byte 0x03 0.--4. " CWI_2 ,Character wait time integer 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
rgroup.byte 0x3C++0x03
|
|
line.byte 0x00 "UART2_WP7816A_T1,UART 7816 Wait Parameter Register A"
|
|
line.byte 0x01 "UART2_WP7816B_T1,UART 7816 Wait Parameter Register B"
|
|
line.byte 0x02 "UART2_WGP7816_T1,UART 7816 Wait And Guard Parameter Register"
|
|
bitfld.byte 0x02 4.--7. " CWI_1 ,Character wait time integer 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x02 0.--3. " BGI ,Block guard time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x03 "UART2_WP7816C_T1,UART 7816 Wait Parameter Register C"
|
|
bitfld.byte 0x03 0.--4. " CWI_2 ,Character wait time integer 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
elif cpuis("MKL28Z*")
|
|
tree.open "LPUART (Low Power UART)"
|
|
base ad:0x400C4000
|
|
width 18.
|
|
sif cpuis("MKL28Z*")
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "LPUART_VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor Version Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature Identification Number"
|
|
line.long 0x04 "LPUART_PARAM,Parameter Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " RXFIFO ,Receive FIFO Size"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TXFIFO ,Transmit FIFO Size"
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "LPUART_GLOBAL,LPUART Global Register"
|
|
bitfld.long 0x00 1. " RST ,Software Reset" "Not reset,Reset"
|
|
line.long 0x04 "LPUART_PINCFG,LPUART Pin Configuration Register"
|
|
bitfld.long 0x04 0.--1. " TRGSEL ,Trigger Select" "Disabled,RXD,CTS,TXD"
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "LPUART_BAUD,LPUART Baud Rate Register"
|
|
bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " M10 ,10-bit mode select" "8bit/9bit,10bit"
|
|
newline
|
|
bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x"
|
|
bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address match,Idle match,Match on/off,RWU enabled"
|
|
bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both"
|
|
bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor"
|
|
line.long 0x04 "LPUART_STAT,LPUART Status Register"
|
|
eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected"
|
|
eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected"
|
|
bitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
newline
|
|
bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected"
|
|
bitfld.long 0x04 26. " BRK13 ,Break character generation length" "10/11/12/13bit,13/14/15/16bit"
|
|
newline
|
|
bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "10/11/12/13bit,11/12/14/15bit"
|
|
rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty"
|
|
newline
|
|
rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle"
|
|
rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full"
|
|
eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Receive overrun"
|
|
eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x04 17. " FE ,Framing error flag" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x04 16. " PF ,Parity error flag" "Not detected,Detected"
|
|
eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal"
|
|
eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal"
|
|
if (((per.l(ad:0x400C4000+0x08))&0x80)==0x80)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "LPUART_CTRL,LPUART Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in single-wire mode" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby"
|
|
newline
|
|
bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break"
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars"
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop"
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected"
|
|
bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8bit,9bit"
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark"
|
|
newline
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit"
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "LPUART_CTRL,LPUART Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in single-wire mode" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby"
|
|
newline
|
|
bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break"
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars"
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop"
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8bit,9bit"
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark"
|
|
newline
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit"
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd"
|
|
endif
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "LPUART_DATA,LPUART Data Register"
|
|
in
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "LPUART_MATCH,LPUART Match Address Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " MA2 ,Match address 2"
|
|
hexmask.long.word 0x00 0.--9. 1. " MA1 ,Match address 1"
|
|
group.long 0x14++0x0B
|
|
line.long 0x00 "LPUART_MODIR,LPUART Modem Irda Register"
|
|
bitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RTSWATER ,Receive RTS configuration"
|
|
newline
|
|
bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS Source" "LPUART_CTS pin,Receiver Match"
|
|
bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "Start,Idle"
|
|
bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "No effect,RTSWATER"
|
|
newline
|
|
bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High"
|
|
bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "No effect,Enabled"
|
|
bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled"
|
|
line.long 0x04 "LPUART_FIFO,LPUART FIFO Register"
|
|
rbitfld.long 0x04 23. " TXEMPT ,Transmit buffer/fifo empty" "Not empty,Empty"
|
|
rbitfld.long 0x04 22. " RXEMPT ,Receive buffer/fifo empty" "Not empty,Empty"
|
|
eventfld.long 0x04 17. " TXOF ,Transmitter buffer overflow flag" "No occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 16. " RXUF ,Receiver buffer underflow flag" "No occurred,Occurred"
|
|
bitfld.long 0x04 15. " TXFLUSH ,Transmit fifo/buffer flush" "No effect,Clear"
|
|
bitfld.long 0x04 14. " RXFLUSH ,Receive fifo/buffer flush" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled,1 char.,2 char.,4 char.,8 char.,16 char.,32 char.,64 char."
|
|
bitfld.long 0x04 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " RXUFE ,Receive FIFO underflow interrupt enable" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled"
|
|
rbitfld.long 0x04 4.--6. " TXFIFOSIZE ,Transmit FIFO. Buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,256 datawords"
|
|
bitfld.long 0x04 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x04 0.--2. " RXFIFOSIZE ,Receive FIFO. Buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,256 datawords"
|
|
line.long 0x08 "LPUART_WATER,LPUART Watermark Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " RXCOUNT ,Receive counter"
|
|
hexmask.long.byte 0x08 16.--23. 1. " RXWATER ,Receive watermark"
|
|
hexmask.long.byte 0x08 8.--15. 1. " TXCOUNT ,Transmit counter"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. " TXWATER ,Transmit watermark"
|
|
else
|
|
width 18.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "LPUART0_BAUD,LPUART0 Baud Rate Register"
|
|
bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " M10 ,10-bit mode select" "8bit/9bit,10bit"
|
|
newline
|
|
bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x"
|
|
sif !cpuis("MKL03Z*")
|
|
bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address match,Idle match,Match on/off,RWU enabled"
|
|
bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both"
|
|
bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor"
|
|
line.long 0x04 "LPUART0_STAT,LPUART0 Status Register"
|
|
eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected"
|
|
eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected"
|
|
bitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first"
|
|
newline
|
|
bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected"
|
|
bitfld.long 0x04 26. " BRK13 ,Break character generation length" "10/11/12/13bit,13/14/15/16bit"
|
|
newline
|
|
bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "10/11/12/13bit,11/12/14/15bit"
|
|
rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active"
|
|
rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty"
|
|
newline
|
|
rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle"
|
|
rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full"
|
|
eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Receive overrun"
|
|
eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected"
|
|
eventfld.long 0x04 17. " FE ,Framing error flag" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x04 16. " PF ,Parity error flag" "Not detected,Detected"
|
|
eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal"
|
|
eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal"
|
|
if (((per.l(ad:0x400C4000+0x08))&0x80)==0x80)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "LPUART0_CTRL,LPUART0 Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in single-wire mode" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby"
|
|
newline
|
|
bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break"
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars"
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop"
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected"
|
|
bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8bit,9bit"
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark"
|
|
newline
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit"
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "LPUART0_CTRL,LPUART0 Control Register"
|
|
bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High"
|
|
bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High"
|
|
bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in single-wire mode" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby"
|
|
newline
|
|
bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break"
|
|
bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars"
|
|
bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop"
|
|
bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8bit,9bit"
|
|
bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark"
|
|
newline
|
|
bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit"
|
|
bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd"
|
|
endif
|
|
sif cpuis("MKL03Z*")||cpuis("MKL13Z*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MKL82Z*")
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "LPUART0_DATA,LPUART0 Data Register"
|
|
in
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "LPUART0_DATA,LPUART0 Data Register"
|
|
rbitfld.long 0x00 15. " NOISY ,DATA[R9:R0] received with noise" "No,Yes"
|
|
rbitfld.long 0x00 14. " PARITYE ,DATA[R9:R0] was received with a parity error" "No,Yes"
|
|
bitfld.long 0x00 13. " FRETSC ,Frame error / transmit special character" "No error/normal char,Error/idle char"
|
|
newline
|
|
rbitfld.long 0x00 12. " RXEMPT ,Receive buffer empty" "Valid data,Not data"
|
|
rbitfld.long 0x00 11. " IDLINE ,Idle line" "Not idle,Idle"
|
|
bitfld.long 0x00 9. " R9T9 ,Read receive data buffer 9 or write transmit data buffer 9" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 8. " R8T8 ,Read receive data buffer 8 or write transmit data buffer 8" "Low,High"
|
|
bitfld.long 0x00 7. " R7T7 ,Read receive data buffer 7 or write transmit data buffer 7" "Low,High"
|
|
bitfld.long 0x00 6. " R6T6 ,Read receive data buffer 6 or write transmit data buffer 6" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " R5T5 ,Read receive data buffer 5 or write transmit data buffer 5" "Low,High"
|
|
bitfld.long 0x00 4. " R4T4 ,Read receive data buffer 4 or write transmit data buffer 4" "Low,High"
|
|
bitfld.long 0x00 3. " R3T3 ,Read receive data buffer 3 or write transmit data buffer 3" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " R2T2 ,Read receive data buffer 2 or write transmit data buffer 2" "Low,High"
|
|
bitfld.long 0x00 1. " R1T1 ,Read receive data buffer 1 or write transmit data buffer 1" "Low,High"
|
|
bitfld.long 0x00 0. " R0T0 ,Read receive data buffer 0 or write transmit data buffer 0" "Low,High"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "LPUART0_MATCH,LPUART0 Match Address Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " MA2 ,Match address 2"
|
|
hexmask.long.word 0x00 0.--9. 1. " MA1 ,Match address 1"
|
|
endif
|
|
sif cpuis("MKL82Z*")
|
|
group.long 0x14++0x0B
|
|
line.long 0x00 "LPUART0_MODIR,LPUART0 Modem Irda Register"
|
|
bitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RTSWATER ,Receive RTS configuration"
|
|
newline
|
|
bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS Source" "LPUART_CTS pin,Receiver Match"
|
|
bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "Start,Idle"
|
|
bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "No effect,RTSWATER"
|
|
newline
|
|
bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High"
|
|
bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "No effect,Enabled"
|
|
bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled"
|
|
line.long 0x04 "LPUART0_FIFO,LPUART0 FIFO Register"
|
|
rbitfld.long 0x04 23. " TXEMPT ,Transmit buffer/fifo empty" "Not empty,Empty"
|
|
rbitfld.long 0x04 22. " RXEMPT ,Receive buffer/fifo empty" "Not empty,Empty"
|
|
eventfld.long 0x04 17. " TXOF ,Transmitter buffer overflow flag" "No occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 16. " RXUF ,Receiver buffer underflow flag" "No occurred,Occurred"
|
|
bitfld.long 0x04 15. " TXFLUSH ,Transmit fifo/buffer flush" "No effect,Clear"
|
|
bitfld.long 0x04 14. " RXFLUSH ,Receive fifo/buffer flush" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 10.--12. " RXIDEN ,Receiver idle empty enable" "Disabled,1 char.,2 char.,4 char.,8 char.,16 char.,32 char.,64 char."
|
|
bitfld.long 0x04 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " RXUFE ,Receive FIFO underflow interrupt enable" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled"
|
|
rbitfld.long 0x04 4.--6. " TXFIFOSIZE ,Transmit FIFO. Buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,256 datawords"
|
|
bitfld.long 0x04 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x04 0.--2. " RXFIFOSIZE ,Receive FIFO. Buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,256 datawords"
|
|
line.long 0x08 "LPUART0_WATER,LPUART0 Watermark Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " RXCOUNT ,Receive counter"
|
|
hexmask.long.byte 0x08 16.--23. 1. " RXWATER ,Receive watermark"
|
|
hexmask.long.byte 0x08 8.--15. 1. " TXCOUNT ,Transmit counter"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. " TXWATER ,Transmit watermark"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree.open "UART (Universal Asynchronous Receiver/Transmitter)"
|
|
tree "UART_0"
|
|
base ad:0x4006A000
|
|
width 13.
|
|
tree "UART 0 Standard Features Registers"
|
|
group.byte 0x00++0x03
|
|
line.byte 0x00 "UART0_BDH,UART Baud Rate Register High"
|
|
bitfld.byte 0x00 7. " LBKDIE ,LIN break detect interrupt or DMA request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RXEDGIE ,Rxd input active edge interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("MKL02*")||cpuis("MKL04*")||cpuis("MKL05*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")
|
|
bitfld.byte 0x00 5. " SBNS ,Stop bit number select" "One,Two"
|
|
newline
|
|
endif
|
|
bitfld.byte 0x00 0.--4. " SBR ,UART baud rate bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x01 "UART0_BDL,UART Baud Rate Register Low"
|
|
line.byte 0x02 "UART0_C1,UART Control Register 1"
|
|
bitfld.byte 0x02 7. " LOOPS ,Loop mode select" "Not selected,Selected"
|
|
newline
|
|
sif (cpu()=="VF7XX-CM4"||cpu()=="VF6XX-CM4"||cpu()=="VF7XX-CA5"||cpu()=="VF6XX-CA5"||cpu()=="VF5XX-CA5"||cpu()=="VF4XX-CA5"||cpu()=="VF3XX-CA5")
|
|
bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Internal loop-back mode,Single-wire UART"
|
|
newline
|
|
elif cpuis("MKL02*")||cpuis("MKL04*")||cpuis("MKL05*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")
|
|
bitfld.byte 0x02 6. " DOZEEN ,Doze enable (wait mode)" "Enabled,Disabled"
|
|
bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Internal loop-back mode,Single-wire UART"
|
|
newline
|
|
elif (cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")||cpuis("MK40D*ZV*10")
|
|
bitfld.byte 0x02 6. " UARTSWAI ,UART stops in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Internal loop-back mode,Single-wire UART"
|
|
newline
|
|
else
|
|
bitfld.byte 0x02 6. " SCISWAI ,UART stops in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Internal loop-back mode,Single-wire UART"
|
|
newline
|
|
endif
|
|
bitfld.byte 0x02 4. " M ,9-bit or 8-bit mode select" "Normal 8 bits+stop,Use 9 bits+stop"
|
|
bitfld.byte 0x02 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark"
|
|
bitfld.byte 0x02 2. " ILT ,Idle line type select" "After start bit,After stop bit"
|
|
newline
|
|
bitfld.byte 0x02 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 0. " PT ,Parity type" "Even,Odd"
|
|
line.byte 0x03 "UART0_C2,UART Control Register 2"
|
|
bitfld.byte 0x03 7. " TIE ,Transmitter interrupt or DMA transfer enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 6. " TCIE ,Transmission complete interrupt or DMA transfer enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 5. " RIE ,Receiver full interrupt or DMA transfer enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x03 4. " ILIE ,Idle line interrupt or DMA transfer enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x03 1. " RWU ,Receiver wakeup control" "Normal,Wake-up"
|
|
bitfld.byte 0x03 0. " SBK ,Send break" "Normal,Break"
|
|
sif cpuis("MKL02*")||cpuis("MKL04*")||cpuis("MKL05*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "UART0_S1,UART Status Register 1"
|
|
rbitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred"
|
|
rbitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred"
|
|
rbitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred"
|
|
else
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "UART0_S1,UART Status Register 1"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred"
|
|
endif
|
|
group.byte 0x05++0x01
|
|
line.byte 0x00 "UART0_S2,UART Status Register 2"
|
|
sif cpuis("MKL02*")||cpuis("MKL04*")||cpuis("MKL05*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")||cpuis("MK40D*ZV*10")
|
|
eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,Rxd pin active edge interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
else
|
|
bitfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 6. " RXEDGIF ,Rxd pin active edge interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL02*")||cpuis("MKL04*")||cpuis("MKL05*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")
|
|
bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first"
|
|
newline
|
|
else
|
|
bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first"
|
|
newline
|
|
endif
|
|
bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected"
|
|
newline
|
|
sif cpuis("MKL02*")||cpuis("MKL04*")||cpuis("MKL05*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")
|
|
bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12/13 bit long,13/14/15/16 bit long"
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "10/11/12/13 bit times,11/12/14/15 bit times"
|
|
newline
|
|
elif (cpu()=="MK21DX128VLK5")||(cpu()=="MK21DX256VLK5")||(cpu()=="MK21DN512VLK5")||(cpu()=="MK21DX128VMC5")||(cpu()=="MK21DX256VMC5")||(cpu()=="MK21DN512VMC5")||(cpu()=="MK22DX128VLF5")||(cpu()=="MK22DX256VLF5")||(cpu()=="MK22DX128VLH5")||(cpu()=="MK22DX256VLH5")||(cpu()=="MK22DN512VLH5")||(cpu()=="MK22DX128VLK5")||(cpu()=="MK22DX256VLK5")||(cpu()=="MK22DN512VLK5")||(cpu()=="MK22DX128VMC5")||(cpu()=="MK22DX256VMC5")||(cpu()=="MK22DN512VMC5")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")
|
|
bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bit long,13/14 bit long"
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable (detected at lenght of)" "10/11/12 bit times,11/12 bit times"
|
|
newline
|
|
else
|
|
bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bit long,13/14 bit long"
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "10 bit times,11 bit times"
|
|
newline
|
|
endif
|
|
sif (cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")||cpuis("MKL02*")||cpuis("MKL04*")||cpuis("MKL05*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")||cpuis("MK40D*ZV*10")
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active"
|
|
else
|
|
bitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active"
|
|
endif
|
|
line.byte 0x01 "UART0_C3,UART Control Register 3"
|
|
sif cpuis("MKL02*")||cpuis("MKL04*")||cpuis("MKL05*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")
|
|
bitfld.byte 0x01 7. " R8T9 ,Receive bit 8 / transmit bit 9" "No RX,RX"
|
|
bitfld.byte 0x01 6. " R9T8 ,Receive bit 9 / transmit bit 8" "No TX,TX"
|
|
newline
|
|
else
|
|
sif (cpu()=="VF7XX-CM4"||cpu()=="VF6XX-CM4"||cpu()=="VF7XX-CA5"||cpu()=="VF6XX-CA5"||cpu()=="VF5XX-CA5"||cpu()=="VF4XX-CA5"||cpu()=="VF3XX-CA5")||(cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")||cpuis("MK40D*ZV*10")
|
|
rbitfld.byte 0x01 7. " R8 ,Received bit 8" "No RX,RX"
|
|
else
|
|
bitfld.byte 0x01 7. " R8 ,Received bit 8" "No RX,RX"
|
|
endif
|
|
bitfld.byte 0x01 6. " T8 ,Transmit bit 8" "No TX,TX"
|
|
newline
|
|
endif
|
|
bitfld.byte 0x01 5. " TXDIR ,Transmitter pin data direction in single-wire mode" "Input,Output"
|
|
newline
|
|
bitfld.byte 0x01 4. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x01 3. " ORIE ,Overrun error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x01 1. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
sif (cpu()=="MK21DX128VLK5")||(cpu()=="MK21DX256VLK5")||(cpu()=="MK21DN512VLK5")||(cpu()=="MK21DX128VMC5")||(cpu()=="MK21DX256VMC5")||(cpu()=="MK21DN512VMC5")||(cpu()=="MK22DX128VLF5")||(cpu()=="MK22DX256VLF5")||(cpu()=="MK22DX128VLH5")||(cpu()=="MK22DX256VLH5")||(cpu()=="MK22DN512VLH5")||(cpu()=="MK22DX128VLK5")||(cpu()=="MK22DX256VLK5")||(cpu()=="MK22DN512VLK5")||(cpu()=="MK22DX128VMC5")||(cpu()=="MK22DX256VMC5")||(cpu()=="MK22DN512VMC5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")||cpuis("MKL02*")||cpuis("MKL04*")||cpuis("MKL05*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")
|
|
hgroup.byte 0x07++0x00
|
|
hide.byte 0x00 "UART0_D,UART Data Register"
|
|
in
|
|
else
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "UART0_D,UART Data Register"
|
|
endif
|
|
sif cpuis("MKL02*")||cpuis("MKL04*")||cpuis("MKL05*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")
|
|
group.byte 0x08++0x03
|
|
line.byte 0x00 "UART0_MA1,UART Match Address Registers 1"
|
|
line.byte 0x01 "UART0_MA2,UART Match Address Registers 2"
|
|
line.byte 0x02 "UART0_C4,UART Control Register 4"
|
|
bitfld.byte 0x02 7. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled"
|
|
bitfld.byte 0x02 6. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled"
|
|
bitfld.byte 0x02 5. " M10 ,10-bit mode select" "Not selected,Selected"
|
|
newline
|
|
bitfld.byte 0x02 0.--4. " OSR ,Over sampling ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x03 "UART0_C5,UART Control Register 5"
|
|
sif !cpuis("MKL02*")
|
|
bitfld.byte 0x03 7. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 5. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.byte 0x03 1. " BOTHEDGE ,Both edge sampling" "No,Yes"
|
|
bitfld.byte 0x03 0. " RESYNCDIS ,Resynchronization disable" "No,Yes"
|
|
else
|
|
group.byte 0x08++0x03
|
|
line.byte 0x00 "UART0_MA1,UART Match Address Registers 1"
|
|
line.byte 0x01 "UART0_MA2,UART Match Address Registers 2"
|
|
line.byte 0x02 "UART0_C4,UART Control Register 4"
|
|
bitfld.byte 0x02 7. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled"
|
|
bitfld.byte 0x02 6. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled"
|
|
bitfld.byte 0x02 5. " M10 ,10-bit mode select" "Not selected,Selected"
|
|
newline
|
|
bitfld.byte 0x02 0.--4. " BRFA ,Baud rate fine adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x03 "UART0_C5,UART Control Register 5"
|
|
bitfld.byte 0x03 7. " TDMAS ,Transmitter DMA select" "Interrupt service,DMA transfer"
|
|
bitfld.byte 0x03 5. " RDMAS ,Receiver full DMA select" "Interrupt service,DMA transfer"
|
|
endif
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL04*")&&!cpuis("MKL05*")&&!cpuis("MK14*")&&!cpuis("MKL14*")&&!cpuis("MKL24*")&&!cpuis("MK15*")&&!cpuis("MKL15*")&&!cpuis("MKL25*")&&!cpuis("MKL36Z*")&&!cpuis("MKL46Z*")&&!cpuis("MKL34Z*")&&!cpuis("MKL16*")&&!cpuis("MKL26*")
|
|
rgroup.byte 0x0C++0x00
|
|
line.byte 0x00 "UART0_ED,UART Extended Data Register"
|
|
bitfld.byte 0x00 7. " NOISY ,The current received dataword contained in D and C3[R8] was received with noise" "Without noise,With noise"
|
|
bitfld.byte 0x00 6. " PARITYE ,The current received dataword contained in D and C3[R8] was received with a parity error" "Without parity error,With parity error"
|
|
group.byte 0x0D++0x01
|
|
line.byte 0x00 "UART0_MODEM,UART Modem Register"
|
|
bitfld.byte 0x00 3. " RXRTSE ,Receiver request-to-send enable (num of char in RCV data reg fifo>=rwfifo(rxwater)/num of char in RCV data reg FIFO<=RWFIFO(RXWATER))" "No effect,Deasserted/asserted"
|
|
bitfld.byte 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high"
|
|
bitfld.byte 0x00 1. " TXRTSE ,Transmitter request-to-send enable (char placed in empty fifo/after all characters placed to FIFO)" "No effect,Asserted/deasserted"
|
|
newline
|
|
bitfld.byte 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled"
|
|
line.byte 0x01 "UART0_IR,UART Infrared Register"
|
|
bitfld.byte 0x01 2. " IREN ,Infrared enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0.--1. " TNP ,Transmitter narrow pulse" "3/16,1/16,1/32,1/4"
|
|
endif
|
|
tree.end
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL04*")&&!cpuis("MKL05*")&&!cpuis("MK14*")&&!cpuis("MKL14*")&&!cpuis("MKL24*")&&!cpuis("MK15*")&&!cpuis("MKL15*")&&!cpuis("MKL25*")&&!cpuis("MKL36Z*")&&!cpuis("MKL46Z*")&&!cpuis("MKL34Z*")&&!cpuis("MKL16*")&&!cpuis("MKL26*")
|
|
width 16.
|
|
tree "UART 0 FIFO Registers"
|
|
group.byte 0x10++0x03
|
|
line.byte 0x00 "UART0_PFIFO,UART FIFO Parameters"
|
|
bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpu()=="VF7XX-CM4"||cpu()=="VF6XX-CM4"||cpu()=="VF7XX-CA5"||cpu()=="VF6XX-CA5"||cpu()=="VF5XX-CA5"||cpu()=="VF4XX-CA5"||cpu()=="VF3XX-CA5")||(cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")||cpuis("MK40D*ZV*10")
|
|
rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..."
|
|
bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..."
|
|
else
|
|
bitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..."
|
|
bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..."
|
|
endif
|
|
line.byte 0x01 "UART0_CFIFO,UART FIFO Control Register"
|
|
bitfld.byte 0x01 7. " TXFLUSH ,Transmit fifo/buffer flush" "Not flushed,Flushed"
|
|
bitfld.byte 0x01 6. " RXFLUSH ,Receive fifo/buffer flush" "Not flushed,Flushed"
|
|
sif (cpu()=="VF7XX-CM4"||cpu()=="VF6XX-CM4"||cpu()=="VF7XX-CA5"||cpu()=="VF6XX-CA5"||cpu()=="VF5XX-CA5"||cpu()=="VF4XX-CA5"||cpu()=="VF3XX-CA5")||(cpu()=="MK21DX128VLK5")||(cpu()=="MK21DX256VLK5")||(cpu()=="MK21DN512VLK5")||(cpu()=="MK21DX128VMC5")||(cpu()=="MK21DX256VMC5")||(cpu()=="MK21DN512VMC5")||(cpu()=="MK22DX128VLF5")||(cpu()=="MK22DX256VLF5")||(cpu()=="MK22DX128VLH5")||(cpu()=="MK22DX256VLH5")||(cpu()=="MK22DN512VLH5")||(cpu()=="MK22DX128VLK5")||(cpu()=="MK22DX256VLK5")||(cpu()=="MK22DN512VLK5")||(cpu()=="MK22DX128VMC5")||(cpu()=="MK22DX256VMC5")||(cpu()=="MK22DN512VMC5")||(cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")
|
|
newline
|
|
bitfld.byte 0x01 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Not generated,Generated"
|
|
bitfld.byte 0x01 1. " TXOFE ,Transmit FIFO overflow interrupt enable" "Not generated,Generated"
|
|
else
|
|
newline
|
|
bitfld.byte 0x01 1. " TXOFE ,Transmit FIFO overflow interrupt enable" "Not generated,Generated"
|
|
endif
|
|
newline
|
|
bitfld.byte 0x01 0. " RXUFE ,Receive FIFO underflow interrupt enable" "Not generated,Generated"
|
|
line.byte 0x02 "UART0_SFIFO,UART FIFO Status Register"
|
|
sif (cpu()=="VF7XX-CM4"||cpu()=="VF6XX-CM4"||cpu()=="VF7XX-CA5"||cpu()=="VF6XX-CA5"||cpu()=="VF5XX-CA5"||cpu()=="VF4XX-CA5"||cpu()=="VF3XX-CA5")||(cpu()=="MK21DX128VLK5")||(cpu()=="MK21DX256VLK5")||(cpu()=="MK21DN512VLK5")||(cpu()=="MK21DX128VMC5")||(cpu()=="MK21DX256VMC5")||(cpu()=="MK21DN512VMC5")||(cpu()=="MK22DX128VLF5")||(cpu()=="MK22DX256VLF5")||(cpu()=="MK22DX128VLH5")||(cpu()=="MK22DX256VLH5")||(cpu()=="MK22DN512VLH5")||(cpu()=="MK22DX128VLK5")||(cpu()=="MK22DX256VLK5")||(cpu()=="MK22DN512VLK5")||(cpu()=="MK22DX128VMC5")||(cpu()=="MK22DX256VMC5")||(cpu()=="MK22DN512VMC5")||(cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")||cpuis("MK40D*ZV*10")
|
|
rbitfld.byte 0x02 7. " TXEMPT ,Transmit buffer/fifo empty" "Not empty,Empty"
|
|
rbitfld.byte 0x02 6. " RXEMPT ,Receive buffer/fifo empty" "Not empty,Empty"
|
|
newline
|
|
sif !cpuis("MK40D*ZV*10")
|
|
eventfld.byte 0x02 2. " RXOF ,Receiver buffer overflow flag" "No overflow,Overflow"
|
|
newline
|
|
endif
|
|
eventfld.byte 0x02 1. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow"
|
|
else
|
|
bitfld.byte 0x02 7. " TXEMPT ,Transmit buffer/fifo empty" "Not empty,Empty"
|
|
bitfld.byte 0x02 6. " RXEMPT ,Receive buffer/fifo empty" "Not empty,Empty"
|
|
eventfld.byte 0x02 1. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow"
|
|
endif
|
|
newline
|
|
eventfld.byte 0x02 0. " RXUF ,Receiver buffer underflow flag" "No overflow,Overflow"
|
|
line.byte 0x03 "UART0_TWFIFO,UART FIFO Transmit Watermark"
|
|
rgroup.byte 0x14++0x00
|
|
line.byte 0x00 "UART0_TCFIFO,UART FIFO Transmit Count"
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "UART0_RWFIFO,UART FIFO Receive Watermark"
|
|
rgroup.byte 0x16++0x00
|
|
line.byte 0x00 "UART0_RCFIFO,UART FIFO Receive Count"
|
|
tree.end
|
|
sif (cpu()=="VF7XX-CM4"||cpu()=="VF6XX-CM4"||cpu()=="VF7XX-CA5"||cpu()=="VF6XX-CA5"||cpu()=="VF5XX-CA5"||cpu()=="VF4XX-CA5"||cpu()=="VF3XX-CA5")
|
|
width 16.
|
|
tree "UART 0 ISO7816 Registers"
|
|
group.byte 0x18++0x02
|
|
line.byte 0x00 "UART0_C7816,UART 7816 Control Register"
|
|
bitfld.byte 0x00 4. " ONACK ,Generate NACK on overflow" "Not generated,Generated"
|
|
bitfld.byte 0x00 3. " ANACK ,Generate NACK on error" "Not generated,Generated"
|
|
bitfld.byte 0x00 2. " INIT ,Detect initial character" "Not detected,Detected"
|
|
newline
|
|
bitfld.byte 0x00 1. " TTYPE ,Transfer type" "0 per the ISO-7816,1 per the ISO-7816"
|
|
bitfld.byte 0x00 0. " ISO_7816E ,ISO-7816 functionality enabled" "Disabled,Enabled"
|
|
line.byte 0x01 "UART0_IE7816,UART 7816 Interrupt Enable Register"
|
|
bitfld.byte 0x01 7. " WTE ,Wait timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " CWTE ,Character wait timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 5. " BWTE ,Block wait timer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x01 4. " INITDE ,Initial character detected interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " GTVE ,Guard timer violated interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 1. " TXTE ,Transmit threshold exceeded interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x01 0. " RXTE ,Receive threshold exceeded interrupt enable" "Disabled,Enabled"
|
|
line.byte 0x02 "UART0_IS7816,UART 7816 Interrupt Status Register"
|
|
eventfld.byte 0x02 7. " WT ,Wait timer interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 6. " CWT ,Character wait timer interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 5. " BWT ,Block wait timer interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x02 4. " INITD ,Initial character detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 2. " GTV ,Guard timer violated interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 1. " TXT ,Transmit threshold exceeded interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x02 0. " RXT ,Receive threshold exceeded interrupt" "No interrupt,Interrupt"
|
|
if ((per.b(ad:0x4006A000+0x18)&0x2)==0x0)
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "UART0_WP7816T0,UART 7816 Wait Parameter Register"
|
|
else
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "UART0_WP7816T1,UART 7816 Wait Parameter Register"
|
|
bitfld.byte 0x00 4.--7. " CWI ,Character wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " BWI ,Block wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.byte 0x1C++0x02
|
|
line.byte 0x00 "UART0_WN7816,UART 7816 Wait N Register"
|
|
line.byte 0x01 "UART0_WF7816,UART 7816 Wait FD Register"
|
|
line.byte 0x02 "UART0_ET7816,UART 7816 Error Threshold Register"
|
|
bitfld.byte 0x02 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x02 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if ((per.b(ad:0x4006A000+0x18)&0x2)==0x0)
|
|
hgroup.byte 0x1F++0x00
|
|
hide.byte 0x00 "UART0_TL7816,UART 7816 Transmit Length Register"
|
|
else
|
|
group.byte 0x1F++0x00
|
|
line.byte 0x00 "UART0_TL7816,UART 7816 Transmit Length Register"
|
|
endif
|
|
tree.end
|
|
elif (cpu()=="MK40DN512ZVLQ10")||(cpu()=="MK40DN512ZVMD10")||(cpu()=="MK40DX128ZVLQ10")||(cpu()=="MK40DX256ZVLQ10")||(cpu()=="MK40DX256ZVMD10")||(cpu()=="MK40DN512ZVLL10")
|
|
width 19.
|
|
tree "UART 0 ISO7816 Registers"
|
|
group.byte 0x18++0x02
|
|
line.byte 0x00 "UART0_C7816,UART 7816 Control Register"
|
|
bitfld.byte 0x00 4. " ONACK ,Generate NACK on overflow" "Not generated,Generated"
|
|
bitfld.byte 0x00 3. " ANACK ,Generate NACK on error" "Not generated,Generated"
|
|
bitfld.byte 0x00 2. " INIT ,Detect initial character" "Not detected,Detected"
|
|
newline
|
|
bitfld.byte 0x00 1. " TTYPE ,Transfer type" "0 per the ISO-7816,1 per the ISO-7816"
|
|
bitfld.byte 0x00 0. " ISO_7816E ,ISO-7816 functionality enabled" "Disabled,Enabled"
|
|
line.byte 0x01 "UART0_IE7816,UART 7816 Interrupt Enable Register"
|
|
bitfld.byte 0x01 7. " WTE ,Wait timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " CWTE ,Character wait timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 5. " BWTE ,Block wait timer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x01 4. " INITDE ,Initial character detected interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " GTVE ,Guard timer violated interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 1. " TXTE ,Transmit threshold exceeded interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x01 0. " RXTE ,Receive threshold exceeded interrupt enable" "Disabled,Enabled"
|
|
line.byte 0x02 "UART0_IS7816,UART 7816 Interrupt Status Register"
|
|
eventfld.byte 0x02 7. " WT ,Wait timer interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 6. " CWT ,Character wait timer interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 5. " BWT ,Block wait timer interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x02 4. " INITD ,Initial character detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 2. " GTV ,Guard timer violated interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 1. " TXT ,Transmit threshold exceeded interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x02 0. " RXT ,Receive threshold exceeded interrupt" "No interrupt,Interrupt"
|
|
if ((per.b(ad:0x4006A000+0x18)&0x1)==0x1)
|
|
if ((per.b(ad:0x4006A000+0x18)&0x2)==0x0)
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "UART0_WP7816T0,UART 7816 Wait Parameter Register"
|
|
else
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "UART0_WP7816T1,UART 7816 Wait Parameter Register"
|
|
bitfld.byte 0x00 4.--7. " CWI ,Character wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " BWI ,Block wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
rgroup.byte 0x1C++0x02
|
|
line.byte 0x00 "UART0_WN7816,UART 7816 Wait N Register"
|
|
line.byte 0x01 "UART0_WF7816,UART 7816 Wait FD Register"
|
|
line.byte 0x02 "UART0_ET7816,UART 7816 Error Threshold Register"
|
|
bitfld.byte 0x02 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x02 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
if ((per.b(ad:0x4006A000+0x18)&0x2)==0x0)
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "UART0_WP7816T0,UART 7816 Wait Parameter Register"
|
|
else
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "UART0_WP7816T1,UART 7816 Wait Parameter Register"
|
|
bitfld.byte 0x00 4.--7. " CWI ,Character wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " BWI ,Block wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.byte 0x1C++0x02
|
|
line.byte 0x00 "UART0_WN7816,UART 7816 Wait N Register"
|
|
line.byte 0x01 "UART0_WF7816,UART 7816 Wait FD Register"
|
|
line.byte 0x02 "UART0_ET7816,UART 7816 Error Threshold Register"
|
|
bitfld.byte 0x02 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x02 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if ((per.b(ad:0x4006A000+0x03)&0x8)==0x8)
|
|
if ((per.b(ad:0x4006A000+0x18)&0x2)==0x0)
|
|
hgroup.byte 0x1F++0x00
|
|
hide.byte 0x00 "UART0_TL7816,UART 7816 Transmit Length Register"
|
|
else
|
|
group.byte 0x1F++0x00
|
|
line.byte 0x00 "UART0_TL7816,UART 7816 Transmit Length Register"
|
|
endif
|
|
else
|
|
if ((per.b(ad:0x4006A000+0x18)&0x2)==0x0)
|
|
hgroup.byte 0x1F++0x00
|
|
hide.byte 0x00 "UART0_TL7816,UART 7816 Transmit Length Register"
|
|
else
|
|
rgroup.byte 0x1F++0x00
|
|
line.byte 0x00 "UART0_TL7816,UART 7816 Transmit Length Register"
|
|
endif
|
|
endif
|
|
tree.end
|
|
else
|
|
tree "UART 0 ISO7816 Registers"
|
|
group.byte 0x18++0x02
|
|
line.byte 0x00 "UART0_C7816,UART 7816 Control Register"
|
|
bitfld.byte 0x00 4. " ONACK ,Generate NACK on overflow" "Not generated,Generated"
|
|
bitfld.byte 0x00 3. " ANACK ,Generate NACK on error" "Not generated,Generated"
|
|
bitfld.byte 0x00 2. " INIT ,Detect initial character" "Not detected,Detected"
|
|
newline
|
|
bitfld.byte 0x00 1. " TTYPE ,Transfer type" "0 per the ISO-7816,1 per the ISO-7816"
|
|
bitfld.byte 0x00 0. " ISO_7816E ,ISO-7816 functionality enabled" "Disabled,Enabled"
|
|
line.byte 0x01 "UART0_IE7816,UART 7816 Interrupt Enable Register"
|
|
bitfld.byte 0x01 7. " WTE ,Wait timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " CWTE ,Character wait timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 5. " BWTE ,Block wait timer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x01 4. " INITDE ,Initial character detected interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " GTVE ,Guard timer violated interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 1. " TXTE ,Transmit threshold exceeded interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x01 0. " RXTE ,Receive threshold exceeded interrupt enable" "Disabled,Enabled"
|
|
line.byte 0x02 "UART0_IS7816,UART 7816 Interrupt Status Register"
|
|
eventfld.byte 0x02 7. " WT ,Wait timer interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 6. " CWT ,Character wait timer interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 5. " BWT ,Block wait timer interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x02 4. " INITD ,Initial character detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 2. " GTV ,Guard timer violated interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 1. " TXT ,Transmit threshold exceeded interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x02 0. " RXT ,Receive threshold exceeded interrupt" "No interrupt,Interrupt"
|
|
if ((per.b(ad:0x4006A000+0x18)&0x2)==0x0)
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "UART0_WP7816T0,UART 7816 Wait Parameter Register"
|
|
else
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "UART0_WP7816T1,UART 7816 Wait Parameter Register"
|
|
bitfld.byte 0x00 4.--7. " CWI ,Character wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " BWI ,Block wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif (cpu()!="MK50DX128CMC7")||(cpu()!="MK50DX256CMC7")
|
|
group.byte 0x1C++0x02
|
|
line.byte 0x00 "UART0_WN7816,UART 7816 Wait N Register"
|
|
line.byte 0x01 "UART0_WF7816,UART 7816 Wait FD Register"
|
|
line.byte 0x02 "UART0_ET7816,UART 7816 Error Threshold Register"
|
|
bitfld.byte 0x02 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x02 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
if ((per.b(ad:0x4006A000+0x18)&0x2)==0x0)
|
|
group.byte 0x1C++0x02
|
|
line.byte 0x00 "UART0_WN7816,UART 7816 Wait N Register"
|
|
line.byte 0x01 "UART0_WF7816,UART 7816 Wait FD Register"
|
|
line.byte 0x02 "UART0_ET7816,UART 7816 Error Threshold Register"
|
|
bitfld.byte 0x02 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x02 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
if ((per.b(ad:0x4006A000+0x18)&0x2)==0x0)
|
|
hgroup.byte 0x1F++0x00
|
|
hide.byte 0x00 "UART0_TL7816,UART 7816 Transmit Length Register"
|
|
else
|
|
group.byte 0x1F++0x00
|
|
line.byte 0x00 "UART0_TL7816,UART 7816 Transmit Length Register"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("K70*"))
|
|
group.byte 0x21++0x10
|
|
line.byte 0x00 "UART0_C6,UART CEA709.1-B Control Register 6"
|
|
bitfld.byte 0x00 7. " EN709 ,Enable CEA709.1-B feature" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TX709 ,Enable CEA709.1-B transmission" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 5. " CE ,Collision enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " CP ,Collision signal polarity" "Active low,Active high"
|
|
line.byte 0x01 "UART0_PCTH,UART CEA709.1-B Packet Cycle Time Counter High Register"
|
|
line.byte 0x02 "UART0_PCTL,UART CEA709.1-B Packet Cycle Time Counter Low Register"
|
|
line.byte 0x03 "UART0_B1T,UART CEA709.1-B Beta1 Timer Register"
|
|
line.byte 0x04 "UART0_SDTH,UART CEA709.1-B Secondary Delay Timer High Register"
|
|
line.byte 0x05 "UART0_SDTL,UART CEA709.1-B Secondary Delay Timer Low Register"
|
|
line.byte 0x06 "UART0_PRE,UART CEA709.1-B Preamble Register"
|
|
line.byte 0x07 "UART0_TPL,UART CEA709.1-B Transmit Packet Length Register"
|
|
line.byte 0x08 "UART0_IE,UART CEA709.1-B Interrupt Enable Register"
|
|
bitfld.byte 0x08 6. " WBEIE ,Wbase expired interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x08 5. " ISDIE ,Initial sync detection interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x08 4. " PRXIE ,Packet received interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x08 3. " PTXIE ,Packet transmitted interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x08 2. " PCTEIE ,Packet cycle timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x08 1. " PSIE ,Preamble start interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x08 0. " TXFIE ,Transmission fail interrupt enable" "Disabled,Enabled"
|
|
line.byte 0x09 "UART0_WB,UART CEA709.1-B WBASE Register"
|
|
line.byte 0x0A "UART0_S3,UART CEA709.1-B Status Register"
|
|
bitfld.byte 0x0A 7. " PEF ,Preamble error interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x0A 6. " WBEF ,Wbase expired interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.byte 0x0A 5. " ISD ,Initial sync detection interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.byte 0x0A 4. " PRXF ,Packet received interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.byte 0x0A 3. " PTXF ,Packet transmitted interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x0A 2. " PCTEF ,Packet cycle timer expired interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.byte 0x0A 1. " PSF ,Preamble start interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x0A 0. " TXFF ,Transmission fail interrupt flag" "No interrupt,Interrupt"
|
|
line.byte 0x0B "UART0_S4,UART CEA709.1-B Status Register"
|
|
bitfld.byte 0x0B 4. " INITF ,Initial synchronization fail flag" "Not falled,Falled"
|
|
bitfld.byte 0x0B 2.--3. " CDET ,Collision occuring during transmission" "No collision,Preamble,Data,Line code violation"
|
|
newline
|
|
bitfld.byte 0x0B 1. " ILCV ,Improper line code violation" "Proper,Not proper"
|
|
bitfld.byte 0x0B 0. " FE ,Framing error flag" "No error,Error"
|
|
line.byte 0x0C "UART0_RPL,UART CEA709.1-B Received Packet Length Register"
|
|
line.byte 0x0D "UART0_RPREL,UART CEA709.1-B Received Preamble Length Register"
|
|
line.byte 0x0E "UART0_CPW,UART CEA709.1-B Collision Pulse Width Register"
|
|
line.byte 0x0F "UART0_RIDT,UART CEA709.1-B Receive Indeterminate Time Register"
|
|
line.byte 0x10 "UART0_TIDT,UART CEA709.1-B Transmit Indeterminate Time Register"
|
|
elif (cpu()=="VF7XX-CM4"||cpu()=="VF6XX-CM4"||cpu()=="VF7XX-CA5"||cpu()=="VF6XX-CA5"||cpu()=="VF5XX-CA5"||cpu()=="VF4XX-CA5"||cpu()=="VF3XX-CA5")||(cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")
|
|
tree "UART 0 CEA709.1-B Registers"
|
|
group.byte 0x21++0x09
|
|
line.byte 0x00 "UART0_C6,UART CEA709.1-B Control Register 6"
|
|
bitfld.byte 0x00 7. " EN709 ,Enable CEA709.1-B feature" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TX709 ,Enable CEA709.1-B transmission" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 5. " CE ,Collision enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " CP ,Collision signal polarity" "Active low,Active high"
|
|
line.byte 0x01 "UART0_PCTH,UART CEA709.1-B Packet Cycle Time Counter High Register"
|
|
line.byte 0x02 "UART0_PCTL,UART CEA709.1-B Packet Cycle Time Counter Low Register"
|
|
line.byte 0x03 "UART0_B1T,UART CEA709.1-B Beta1 Timer Register"
|
|
line.byte 0x04 "UART0_SDTH,UART CEA709.1-B Secondary Delay Timer High Register"
|
|
line.byte 0x05 "UART0_SDTL,UART CEA709.1-B Secondary Delay Timer Low Register"
|
|
line.byte 0x06 "UART0_PRE,UART CEA709.1-B Preamble Register"
|
|
line.byte 0x07 "UART0_TPL,UART CEA709.1-B Transmit Packet Length Register"
|
|
line.byte 0x08 "UART0_IE,UART CEA709.1-B Interrupt Enable Register"
|
|
bitfld.byte 0x08 6. " WBEIE ,Wbase expired interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x08 5. " ISDIE ,Initial sync detection interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x08 4. " PRXIE ,Packet received interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x08 3. " PTXIE ,Packet transmitted interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x08 2. " PCTEIE ,Packet cycle timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x08 1. " PSIE ,Preamble start interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x08 0. " TXFIE ,Transmission fail interrupt enable" "Disabled,Enabled"
|
|
line.byte 0x09 "UART0_WB,UART CEA709.1-B WBASE"
|
|
group.byte 0x2B++0x01
|
|
line.byte 0x00 "UART0_S3,UART CEA709.1-B Status Register"
|
|
bitfld.byte 0x00 7. " PEF ,Preamble error interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 6. " WBEF ,Wbase expired interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.byte 0x00 5. " ISD ,Initial sync detection interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 4. " PRXF ,Packet received interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.byte 0x00 3. " PTXF ,Packet transmitted interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 2. " PCTEF ,Packet cycle timer expired interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.byte 0x00 1. " PSF ,Preamble start interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " TXFF ,Transmission fail interrupt flag" "No interrupt,Interrupt"
|
|
line.byte 0x01 "UART0_S4,UART CEA709.1-B Status Register"
|
|
rbitfld.byte 0x01 4. " INITF ,Initial synchronization fail flag" "Not falled,Falled"
|
|
bitfld.byte 0x01 2.--3. " CDET ,Collision occuring during transmission" "No collision,Preamble,Data,Line code violation"
|
|
newline
|
|
bitfld.byte 0x01 1. " ILCV ,Improper line code violation" "Proper,Not proper"
|
|
bitfld.byte 0x01 0. " FE ,Framing error flag" "No error,Error"
|
|
rgroup.byte 0x2D++0x01
|
|
line.byte 0x00 "UART0_RPL,UART CEA709.1-B Received Packet Length Register"
|
|
line.byte 0x01 "UART0_RPREL,UART CEA709.1-B Received Preamble Length Register"
|
|
group.byte 0x2F++0x02
|
|
line.byte 0x00 "UART0_CPW,UART CEA709.1-B Collision Pulse Width Register"
|
|
line.byte 0x01 "UART0_RIDT,UART CEA709.1-B Receive Indeterminate Time Register"
|
|
line.byte 0x02 "UART0_TIDT,UART CEA709.1-B Transmit Indeterminate Time Register"
|
|
tree.end
|
|
elif (cpu()=="MK21DX128VLK5")||(cpu()=="MK21DX256VLK5")||(cpu()=="MK21DN512VLK5")||(cpu()=="MK21DX128VMC5")||(cpu()=="MK21DX256VMC5")||(cpu()=="MK21DN512VMC5")||(cpu()=="MK22DX128VLF5")||(cpu()=="MK22DX256VLF5")||(cpu()=="MK22DX128VLH5")||(cpu()=="MK22DX256VLH5")||(cpu()=="MK22DN512VLH5")||(cpu()=="MK22DX128VLK5")||(cpu()=="MK22DX256VLK5")||(cpu()=="MK22DN512VLK5")||(cpu()=="MK22DX128VMC5")||(cpu()=="MK22DX256VMC5")||(cpu()=="MK22DN512VMC5")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")
|
|
tree "UART 0 CEA709.1-B Registers"
|
|
group.byte 0x21++0x07
|
|
line.byte 0x00 "UART0_C6,UART CEA709.1-B Control Register 6"
|
|
bitfld.byte 0x00 7. " EN709 ,Enable CEA709.1-B feature" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TX709 ,Enable CEA709.1-B transmission" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 5. " CE ,Collision enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " CP ,Collision signal polarity" "Active low,Active high"
|
|
line.byte 0x01 "UART0_PCTH,UART CEA709.1-B Packet Cycle Time Counter High Register"
|
|
line.byte 0x02 "UART0_PCTL,UART CEA709.1-B Packet Cycle Time Counter Low Register"
|
|
line.byte 0x03 "UART0_B1T,UART CEA709.1-B Beta1 Timer Register"
|
|
line.byte 0x04 "UART0_SDTH,UART CEA709.1-B Secondary Delay Timer High Register"
|
|
line.byte 0x05 "UART0_SDTL,UART CEA709.1-B Secondary Delay Timer Low Register"
|
|
line.byte 0x06 "UART0_PRE,UART CEA709.1-B Preamble Register"
|
|
line.byte 0x07 "UART0_TPL,UART CEA709.1-B Transmit Packet Length Register"
|
|
sif (cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")
|
|
group.byte 0x29++0x00
|
|
line.byte 0x00 "UART0_IE,UART CEA709.1-B Interrupt Enable Register"
|
|
bitfld.byte 0x00 7. " PEF ,Preamble error interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 6. " WBEF ,Wbase expired interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.byte 0x00 5. " ISD ,Initial sync detection interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 4. " PRXF ,Packet received interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.byte 0x00 3. " PTXF ,Packet transmitted interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 2. " PCTEF ,Packet cycle timer expired interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.byte 0x00 1. " PSF ,Preamble start interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " TXFF ,Transmission fail interrupt flag" "No interrupt,Interrupt"
|
|
endif
|
|
group.byte 0x2A++0x02
|
|
line.byte 0x00 "UART0_WB,UART CEA709.1-B WBASE Register"
|
|
line.byte 0x01 "UART0_S3,UART CEA709.1-B Status Register"
|
|
eventfld.byte 0x01 7. " PEF ,Preamble error interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.byte 0x01 6. " WBEF ,Wbase expired interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
sif (cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")
|
|
rbitfld.byte 0x01 5. " ISD ,Initial sync detection interrupt enable" "No interrupt,Interrupt"
|
|
else
|
|
bitfld.byte 0x01 5. " ISD ,Initial sync detection interrupt enable" "No interrupt,Interrupt"
|
|
endif
|
|
eventfld.byte 0x01 4. " PRXF ,Packet received interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x01 3. " PTXF ,Packet transmitted interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.byte 0x01 2. " PCTEF ,Packet cycle timer expired interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x01 1. " PSF ,Preamble start interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.byte 0x01 0. " TXFF ,Transmission fail interrupt flag" "No interrupt,Interrupt"
|
|
line.byte 0x02 "UART0_S4,UART CEA709.1-B Status Register"
|
|
bitfld.byte 0x02 4. " INITF ,Initial synchronization fail flag" "Not falled,Falled"
|
|
bitfld.byte 0x02 2.--3. " CDET ,Collision occuring during transmission" "No collision,Preamble,Byte sync or data,Line code violation"
|
|
newline
|
|
eventfld.byte 0x02 1. " ILCV ,Improper line code violation" "Proper,Not proper"
|
|
eventfld.byte 0x02 0. " FE ,Framing error flag" "No error,Error"
|
|
rgroup.byte 0x2D++0x01
|
|
line.byte 0x00 "UART0_RPL,UART CEA709.1-B Received Packet Length Register"
|
|
line.byte 0x01 "UART0_RPREL,UART CEA709.1-B Received Preamble Length Register"
|
|
group.byte 0x2F++0x02
|
|
line.byte 0x00 "UART0_CPW,UART CEA709.1-B Collision Pulse Width Register"
|
|
line.byte 0x01 "UART0_RIDT,UART CEA709.1-B Receive Indeterminate Time Register"
|
|
line.byte 0x02 "UART0_TIDT,UART CEA709.1-B Transmit Indeterminate Time Register"
|
|
tree.end
|
|
elif (cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "UART0_B1T,UART CEA709.1-B Beta1 Timer"
|
|
group.byte 0x30++0x01
|
|
line.byte 0x00 "UART0_RIDT,UART CEA709.1-B Receive Indeterminate Time"
|
|
line.byte 0x01 "UARTX_TIDT,UART CEA709.1-B Transmit Indeterminate Time"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL04*")&&!cpuis("MKL05*")
|
|
tree "UART_1"
|
|
base ad:0x4006B000
|
|
width 13.
|
|
tree "UART 1 Standard Features Registers"
|
|
group.byte 0x00++0x03
|
|
line.byte 0x00 "UART1_BDH,UART Baud Rate Register High"
|
|
bitfld.byte 0x00 7. " LBKDIE ,LIN break detect interrupt or DMA request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RXEDGIE ,Rxd input active edge interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("MKL02*")||cpuis("MKL04*")||cpuis("MKL05*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")
|
|
bitfld.byte 0x00 5. " SBNS ,Stop bit number select" "One,Two"
|
|
newline
|
|
endif
|
|
bitfld.byte 0x00 0.--4. " SBR ,UART baud rate bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x01 "UART1_BDL,UART Baud Rate Register Low"
|
|
line.byte 0x02 "UART1_C1,UART Control Register 1"
|
|
bitfld.byte 0x02 7. " LOOPS ,Loop mode select" "Not selected,Selected"
|
|
newline
|
|
sif (cpu()=="VF7XX-CM4"||cpu()=="VF6XX-CM4"||cpu()=="VF7XX-CA5"||cpu()=="VF6XX-CA5"||cpu()=="VF5XX-CA5"||cpu()=="VF4XX-CA5"||cpu()=="VF3XX-CA5")
|
|
bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Internal loop-back mode,Single-wire UART"
|
|
newline
|
|
elif cpuis("MKL02*")||cpuis("MKL04*")||cpuis("MKL05*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")
|
|
bitfld.byte 0x02 6. " UARTSWAI ,UART stops in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Internal loop-back mode,Single-wire UART"
|
|
newline
|
|
elif (cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")||cpuis("MK40D*ZV*10")
|
|
bitfld.byte 0x02 6. " UARTSWAI ,UART stops in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Internal loop-back mode,Single-wire UART"
|
|
newline
|
|
else
|
|
bitfld.byte 0x02 6. " SCISWAI ,UART stops in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Internal loop-back mode,Single-wire UART"
|
|
newline
|
|
endif
|
|
bitfld.byte 0x02 4. " M ,9-bit or 8-bit mode select" "Normal 8 bits+stop,Use 9 bits+stop"
|
|
bitfld.byte 0x02 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark"
|
|
bitfld.byte 0x02 2. " ILT ,Idle line type select" "After start bit,After stop bit"
|
|
newline
|
|
bitfld.byte 0x02 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 0. " PT ,Parity type" "Even,Odd"
|
|
line.byte 0x03 "UART1_C2,UART Control Register 2"
|
|
bitfld.byte 0x03 7. " TIE ,Transmitter interrupt or DMA transfer enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 6. " TCIE ,Transmission complete interrupt or DMA transfer enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 5. " RIE ,Receiver full interrupt or DMA transfer enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x03 4. " ILIE ,Idle line interrupt or DMA transfer enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x03 1. " RWU ,Receiver wakeup control" "Normal,Wake-up"
|
|
bitfld.byte 0x03 0. " SBK ,Send break" "Normal,Break"
|
|
sif cpuis("MKL02*")||cpuis("MKL04*")||cpuis("MKL05*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "UART1_S1,UART Status Register 1"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred"
|
|
else
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "UART1_S1,UART Status Register 1"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred"
|
|
endif
|
|
group.byte 0x05++0x01
|
|
line.byte 0x00 "UART1_S2,UART Status Register 2"
|
|
sif cpuis("MKL02*")||cpuis("MKL04*")||cpuis("MKL05*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")||cpuis("MK40D*ZV*10")
|
|
eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,Rxd pin active edge interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
else
|
|
bitfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 6. " RXEDGIF ,Rxd pin active edge interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL02*")||cpuis("MKL04*")||cpuis("MKL05*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")
|
|
else
|
|
bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first"
|
|
newline
|
|
endif
|
|
bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected"
|
|
newline
|
|
sif cpuis("MKL02*")||cpuis("MKL04*")||cpuis("MKL05*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")
|
|
bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bit long,13/14/15 bit long"
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "10/11/12 bit times,11/12/14 bit times"
|
|
newline
|
|
elif (cpu()=="MK21DX128VLK5")||(cpu()=="MK21DX256VLK5")||(cpu()=="MK21DN512VLK5")||(cpu()=="MK21DX128VMC5")||(cpu()=="MK21DX256VMC5")||(cpu()=="MK21DN512VMC5")||(cpu()=="MK22DX128VLF5")||(cpu()=="MK22DX256VLF5")||(cpu()=="MK22DX128VLH5")||(cpu()=="MK22DX256VLH5")||(cpu()=="MK22DN512VLH5")||(cpu()=="MK22DX128VLK5")||(cpu()=="MK22DX256VLK5")||(cpu()=="MK22DN512VLK5")||(cpu()=="MK22DX128VMC5")||(cpu()=="MK22DX256VMC5")||(cpu()=="MK22DN512VMC5")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")
|
|
bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bit long,13/14 bit long"
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable (detected at lenght of)" "10/11/12 bit times,11/12 bit times"
|
|
newline
|
|
else
|
|
bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bit long,13/14 bit long"
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "10 bit times,11 bit times"
|
|
newline
|
|
endif
|
|
sif (cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")||cpuis("MKL02*")||cpuis("MKL04*")||cpuis("MKL05*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")||cpuis("MK40D*ZV*10")
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active"
|
|
else
|
|
bitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active"
|
|
endif
|
|
line.byte 0x01 "UART1_C3,UART Control Register 3"
|
|
sif cpuis("MKL02*")||cpuis("MKL04*")||cpuis("MKL05*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")
|
|
rbitfld.byte 0x01 7. " R8 ,Received bit 8" "No RX,RX"
|
|
bitfld.byte 0x01 6. " T8 ,Transmit bit 8" "No TX,TX"
|
|
newline
|
|
else
|
|
sif (cpu()=="VF7XX-CM4"||cpu()=="VF6XX-CM4"||cpu()=="VF7XX-CA5"||cpu()=="VF6XX-CA5"||cpu()=="VF5XX-CA5"||cpu()=="VF4XX-CA5"||cpu()=="VF3XX-CA5")||(cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")||cpuis("MK40D*ZV*10")
|
|
rbitfld.byte 0x01 7. " R8 ,Received bit 8" "No RX,RX"
|
|
else
|
|
bitfld.byte 0x01 7. " R8 ,Received bit 8" "No RX,RX"
|
|
endif
|
|
bitfld.byte 0x01 6. " T8 ,Transmit bit 8" "No TX,TX"
|
|
newline
|
|
endif
|
|
bitfld.byte 0x01 5. " TXDIR ,Transmitter pin data direction in single-wire mode" "Input,Output"
|
|
newline
|
|
bitfld.byte 0x01 4. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x01 3. " ORIE ,Overrun error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x01 1. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
sif (cpu()=="MK21DX128VLK5")||(cpu()=="MK21DX256VLK5")||(cpu()=="MK21DN512VLK5")||(cpu()=="MK21DX128VMC5")||(cpu()=="MK21DX256VMC5")||(cpu()=="MK21DN512VMC5")||(cpu()=="MK22DX128VLF5")||(cpu()=="MK22DX256VLF5")||(cpu()=="MK22DX128VLH5")||(cpu()=="MK22DX256VLH5")||(cpu()=="MK22DN512VLH5")||(cpu()=="MK22DX128VLK5")||(cpu()=="MK22DX256VLK5")||(cpu()=="MK22DN512VLK5")||(cpu()=="MK22DX128VMC5")||(cpu()=="MK22DX256VMC5")||(cpu()=="MK22DN512VMC5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")||cpuis("MKL02*")||cpuis("MKL04*")||cpuis("MKL05*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")
|
|
hgroup.byte 0x07++0x00
|
|
hide.byte 0x00 "UART1_D,UART Data Register"
|
|
in
|
|
else
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "UART1_D,UART Data Register"
|
|
endif
|
|
sif cpuis("MKL02*")||cpuis("MKL04*")||cpuis("MKL05*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "UART1_C4,UART Control Register 4"
|
|
bitfld.byte 0x00 7. " TDMAS ,Transmitter DMA select" "Interrupt service,DMA transfer"
|
|
bitfld.byte 0x00 5. " RDMAS ,Receiver full DMA select" "Interrupt service,DMA transfer"
|
|
newline
|
|
else
|
|
group.byte 0x08++0x03
|
|
line.byte 0x00 "UART1_MA1,UART Match Address Registers 1"
|
|
line.byte 0x01 "UART1_MA2,UART Match Address Registers 2"
|
|
line.byte 0x02 "UART1_C4,UART Control Register 4"
|
|
bitfld.byte 0x02 7. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled"
|
|
bitfld.byte 0x02 6. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled"
|
|
bitfld.byte 0x02 5. " M10 ,10-bit mode select" "Not selected,Selected"
|
|
newline
|
|
bitfld.byte 0x02 0.--4. " BRFA ,Baud rate fine adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x03 "UART1_C5,UART Control Register 5"
|
|
bitfld.byte 0x03 7. " TDMAS ,Transmitter DMA select" "Interrupt service,DMA transfer"
|
|
bitfld.byte 0x03 5. " RDMAS ,Receiver full DMA select" "Interrupt service,DMA transfer"
|
|
endif
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL04*")&&!cpuis("MKL05*")&&!cpuis("MK14*")&&!cpuis("MKL14*")&&!cpuis("MKL24*")&&!cpuis("MK15*")&&!cpuis("MKL15*")&&!cpuis("MKL25*")&&!cpuis("MKL36Z*")&&!cpuis("MKL46Z*")&&!cpuis("MKL34Z*")&&!cpuis("MKL16*")&&!cpuis("MKL26*")
|
|
rgroup.byte 0x0C++0x00
|
|
line.byte 0x00 "UART1_ED,UART Extended Data Register"
|
|
bitfld.byte 0x00 7. " NOISY ,The current received dataword contained in D and C3[R8] was received with noise" "Without noise,With noise"
|
|
bitfld.byte 0x00 6. " PARITYE ,The current received dataword contained in D and C3[R8] was received with a parity error" "Without parity error,With parity error"
|
|
group.byte 0x0D++0x01
|
|
line.byte 0x00 "UART1_MODEM,UART Modem Register"
|
|
bitfld.byte 0x00 3. " RXRTSE ,Receiver request-to-send enable (num of char in RCV data reg fifo>=rwfifo(rxwater)/num of char in RCV data reg FIFO<=RWFIFO(RXWATER))" "No effect,Deasserted/asserted"
|
|
bitfld.byte 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high"
|
|
bitfld.byte 0x00 1. " TXRTSE ,Transmitter request-to-send enable (char placed in empty fifo/after all characters placed to FIFO)" "No effect,Asserted/deasserted"
|
|
newline
|
|
bitfld.byte 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled"
|
|
line.byte 0x01 "UART1_IR,UART Infrared Register"
|
|
bitfld.byte 0x01 2. " IREN ,Infrared enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0.--1. " TNP ,Transmitter narrow pulse" "3/16,1/16,1/32,1/4"
|
|
endif
|
|
tree.end
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL04*")&&!cpuis("MKL05*")&&!cpuis("MK14*")&&!cpuis("MKL14*")&&!cpuis("MKL24*")&&!cpuis("MK15*")&&!cpuis("MKL15*")&&!cpuis("MKL25*")&&!cpuis("MKL36Z*")&&!cpuis("MKL46Z*")&&!cpuis("MKL34Z*")&&!cpuis("MKL16*")&&!cpuis("MKL26*")
|
|
width 16.
|
|
tree "UART 1 FIFO Registers"
|
|
group.byte 0x10++0x03
|
|
line.byte 0x00 "UART1_PFIFO,UART FIFO Parameters"
|
|
bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpu()=="VF7XX-CM4"||cpu()=="VF6XX-CM4"||cpu()=="VF7XX-CA5"||cpu()=="VF6XX-CA5"||cpu()=="VF5XX-CA5"||cpu()=="VF4XX-CA5"||cpu()=="VF3XX-CA5")||(cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")||cpuis("MK40D*ZV*10")
|
|
rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..."
|
|
bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..."
|
|
else
|
|
bitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..."
|
|
bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..."
|
|
endif
|
|
line.byte 0x01 "UART1_CFIFO,UART FIFO Control Register"
|
|
bitfld.byte 0x01 7. " TXFLUSH ,Transmit fifo/buffer flush" "Not flushed,Flushed"
|
|
bitfld.byte 0x01 6. " RXFLUSH ,Receive fifo/buffer flush" "Not flushed,Flushed"
|
|
sif (cpu()=="VF7XX-CM4"||cpu()=="VF6XX-CM4"||cpu()=="VF7XX-CA5"||cpu()=="VF6XX-CA5"||cpu()=="VF5XX-CA5"||cpu()=="VF4XX-CA5"||cpu()=="VF3XX-CA5")||(cpu()=="MK21DX128VLK5")||(cpu()=="MK21DX256VLK5")||(cpu()=="MK21DN512VLK5")||(cpu()=="MK21DX128VMC5")||(cpu()=="MK21DX256VMC5")||(cpu()=="MK21DN512VMC5")||(cpu()=="MK22DX128VLF5")||(cpu()=="MK22DX256VLF5")||(cpu()=="MK22DX128VLH5")||(cpu()=="MK22DX256VLH5")||(cpu()=="MK22DN512VLH5")||(cpu()=="MK22DX128VLK5")||(cpu()=="MK22DX256VLK5")||(cpu()=="MK22DN512VLK5")||(cpu()=="MK22DX128VMC5")||(cpu()=="MK22DX256VMC5")||(cpu()=="MK22DN512VMC5")||(cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")
|
|
newline
|
|
bitfld.byte 0x01 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Not generated,Generated"
|
|
bitfld.byte 0x01 1. " TXOFE ,Transmit FIFO overflow interrupt enable" "Not generated,Generated"
|
|
else
|
|
newline
|
|
bitfld.byte 0x01 1. " TXOFE ,Transmit FIFO overflow interrupt enable" "Not generated,Generated"
|
|
endif
|
|
newline
|
|
bitfld.byte 0x01 0. " RXUFE ,Receive FIFO underflow interrupt enable" "Not generated,Generated"
|
|
line.byte 0x02 "UART1_SFIFO,UART FIFO Status Register"
|
|
sif (cpu()=="VF7XX-CM4"||cpu()=="VF6XX-CM4"||cpu()=="VF7XX-CA5"||cpu()=="VF6XX-CA5"||cpu()=="VF5XX-CA5"||cpu()=="VF4XX-CA5"||cpu()=="VF3XX-CA5")||(cpu()=="MK21DX128VLK5")||(cpu()=="MK21DX256VLK5")||(cpu()=="MK21DN512VLK5")||(cpu()=="MK21DX128VMC5")||(cpu()=="MK21DX256VMC5")||(cpu()=="MK21DN512VMC5")||(cpu()=="MK22DX128VLF5")||(cpu()=="MK22DX256VLF5")||(cpu()=="MK22DX128VLH5")||(cpu()=="MK22DX256VLH5")||(cpu()=="MK22DN512VLH5")||(cpu()=="MK22DX128VLK5")||(cpu()=="MK22DX256VLK5")||(cpu()=="MK22DN512VLK5")||(cpu()=="MK22DX128VMC5")||(cpu()=="MK22DX256VMC5")||(cpu()=="MK22DN512VMC5")||(cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")||cpuis("MK40D*ZV*10")
|
|
rbitfld.byte 0x02 7. " TXEMPT ,Transmit buffer/fifo empty" "Not empty,Empty"
|
|
rbitfld.byte 0x02 6. " RXEMPT ,Receive buffer/fifo empty" "Not empty,Empty"
|
|
newline
|
|
sif !cpuis("MK40D*ZV*10")
|
|
eventfld.byte 0x02 2. " RXOF ,Receiver buffer overflow flag" "No overflow,Overflow"
|
|
newline
|
|
endif
|
|
eventfld.byte 0x02 1. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow"
|
|
else
|
|
bitfld.byte 0x02 7. " TXEMPT ,Transmit buffer/fifo empty" "Not empty,Empty"
|
|
bitfld.byte 0x02 6. " RXEMPT ,Receive buffer/fifo empty" "Not empty,Empty"
|
|
eventfld.byte 0x02 1. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow"
|
|
endif
|
|
newline
|
|
eventfld.byte 0x02 0. " RXUF ,Receiver buffer underflow flag" "No overflow,Overflow"
|
|
line.byte 0x03 "UART1_TWFIFO,UART FIFO Transmit Watermark"
|
|
rgroup.byte 0x14++0x00
|
|
line.byte 0x00 "UART1_TCFIFO,UART FIFO Transmit Count"
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "UART1_RWFIFO,UART FIFO Receive Watermark"
|
|
rgroup.byte 0x16++0x00
|
|
line.byte 0x00 "UART1_RCFIFO,UART FIFO Receive Count"
|
|
tree.end
|
|
sif (cpu()=="VF7XX-CM4"||cpu()=="VF6XX-CM4"||cpu()=="VF7XX-CA5"||cpu()=="VF6XX-CA5"||cpu()=="VF5XX-CA5"||cpu()=="VF4XX-CA5"||cpu()=="VF3XX-CA5")
|
|
width 16.
|
|
tree "UART 1 ISO7816 Registers"
|
|
group.byte 0x18++0x02
|
|
line.byte 0x00 "UART1_C7816,UART 7816 Control Register"
|
|
bitfld.byte 0x00 4. " ONACK ,Generate NACK on overflow" "Not generated,Generated"
|
|
bitfld.byte 0x00 3. " ANACK ,Generate NACK on error" "Not generated,Generated"
|
|
bitfld.byte 0x00 2. " INIT ,Detect initial character" "Not detected,Detected"
|
|
newline
|
|
bitfld.byte 0x00 1. " TTYPE ,Transfer type" "0 per the ISO-7816,1 per the ISO-7816"
|
|
bitfld.byte 0x00 0. " ISO_7816E ,ISO-7816 functionality enabled" "Disabled,Enabled"
|
|
line.byte 0x01 "UART1_IE7816,UART 7816 Interrupt Enable Register"
|
|
bitfld.byte 0x01 7. " WTE ,Wait timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " CWTE ,Character wait timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 5. " BWTE ,Block wait timer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x01 4. " INITDE ,Initial character detected interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " GTVE ,Guard timer violated interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 1. " TXTE ,Transmit threshold exceeded interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x01 0. " RXTE ,Receive threshold exceeded interrupt enable" "Disabled,Enabled"
|
|
line.byte 0x02 "UART1_IS7816,UART 7816 Interrupt Status Register"
|
|
eventfld.byte 0x02 7. " WT ,Wait timer interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 6. " CWT ,Character wait timer interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 5. " BWT ,Block wait timer interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x02 4. " INITD ,Initial character detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 2. " GTV ,Guard timer violated interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 1. " TXT ,Transmit threshold exceeded interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x02 0. " RXT ,Receive threshold exceeded interrupt" "No interrupt,Interrupt"
|
|
if ((per.b(ad:0x4006B000+0x18)&0x2)==0x0)
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "UART1_WP7816T0,UART 7816 Wait Parameter Register"
|
|
else
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "UART1_WP7816T1,UART 7816 Wait Parameter Register"
|
|
bitfld.byte 0x00 4.--7. " CWI ,Character wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " BWI ,Block wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.byte 0x1C++0x02
|
|
line.byte 0x00 "UART1_WN7816,UART 7816 Wait N Register"
|
|
line.byte 0x01 "UART1_WF7816,UART 7816 Wait FD Register"
|
|
line.byte 0x02 "UART1_ET7816,UART 7816 Error Threshold Register"
|
|
bitfld.byte 0x02 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x02 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if ((per.b(ad:0x4006B000+0x18)&0x2)==0x0)
|
|
hgroup.byte 0x1F++0x00
|
|
hide.byte 0x00 "UART1_TL7816,UART 7816 Transmit Length Register"
|
|
else
|
|
group.byte 0x1F++0x00
|
|
line.byte 0x00 "UART1_TL7816,UART 7816 Transmit Length Register"
|
|
endif
|
|
tree.end
|
|
elif (cpu()=="MK40DN512ZVLQ10")||(cpu()=="MK40DN512ZVMD10")||(cpu()=="MK40DX128ZVLQ10")||(cpu()=="MK40DX256ZVLQ10")||(cpu()=="MK40DX256ZVMD10")||(cpu()=="MK40DN512ZVLL10")
|
|
width 19.
|
|
tree "UART 1 ISO7816 Registers"
|
|
group.byte 0x18++0x02
|
|
line.byte 0x00 "UART1_C7816,UART 7816 Control Register"
|
|
bitfld.byte 0x00 4. " ONACK ,Generate NACK on overflow" "Not generated,Generated"
|
|
bitfld.byte 0x00 3. " ANACK ,Generate NACK on error" "Not generated,Generated"
|
|
bitfld.byte 0x00 2. " INIT ,Detect initial character" "Not detected,Detected"
|
|
newline
|
|
bitfld.byte 0x00 1. " TTYPE ,Transfer type" "0 per the ISO-7816,1 per the ISO-7816"
|
|
bitfld.byte 0x00 0. " ISO_7816E ,ISO-7816 functionality enabled" "Disabled,Enabled"
|
|
line.byte 0x01 "UART1_IE7816,UART 7816 Interrupt Enable Register"
|
|
bitfld.byte 0x01 7. " WTE ,Wait timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " CWTE ,Character wait timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 5. " BWTE ,Block wait timer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x01 4. " INITDE ,Initial character detected interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " GTVE ,Guard timer violated interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 1. " TXTE ,Transmit threshold exceeded interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x01 0. " RXTE ,Receive threshold exceeded interrupt enable" "Disabled,Enabled"
|
|
line.byte 0x02 "UART1_IS7816,UART 7816 Interrupt Status Register"
|
|
eventfld.byte 0x02 7. " WT ,Wait timer interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 6. " CWT ,Character wait timer interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 5. " BWT ,Block wait timer interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x02 4. " INITD ,Initial character detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 2. " GTV ,Guard timer violated interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 1. " TXT ,Transmit threshold exceeded interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x02 0. " RXT ,Receive threshold exceeded interrupt" "No interrupt,Interrupt"
|
|
if ((per.b(ad:0x4006B000+0x18)&0x1)==0x1)
|
|
if ((per.b(ad:0x4006B000+0x18)&0x2)==0x0)
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "UART1_WP7816T0,UART 7816 Wait Parameter Register"
|
|
else
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "UART1_WP7816T1,UART 7816 Wait Parameter Register"
|
|
bitfld.byte 0x00 4.--7. " CWI ,Character wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " BWI ,Block wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
rgroup.byte 0x1C++0x02
|
|
line.byte 0x00 "UART1_WN7816,UART 7816 Wait N Register"
|
|
line.byte 0x01 "UART1_WF7816,UART 7816 Wait FD Register"
|
|
line.byte 0x02 "UART1_ET7816,UART 7816 Error Threshold Register"
|
|
bitfld.byte 0x02 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x02 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
if ((per.b(ad:0x4006B000+0x18)&0x2)==0x0)
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "UART1_WP7816T0,UART 7816 Wait Parameter Register"
|
|
else
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "UART1_WP7816T1,UART 7816 Wait Parameter Register"
|
|
bitfld.byte 0x00 4.--7. " CWI ,Character wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " BWI ,Block wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.byte 0x1C++0x02
|
|
line.byte 0x00 "UART1_WN7816,UART 7816 Wait N Register"
|
|
line.byte 0x01 "UART1_WF7816,UART 7816 Wait FD Register"
|
|
line.byte 0x02 "UART1_ET7816,UART 7816 Error Threshold Register"
|
|
bitfld.byte 0x02 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x02 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if ((per.b(ad:0x4006B000+0x03)&0x8)==0x8)
|
|
if ((per.b(ad:0x4006B000+0x18)&0x2)==0x0)
|
|
hgroup.byte 0x1F++0x00
|
|
hide.byte 0x00 "UART1_TL7816,UART 7816 Transmit Length Register"
|
|
else
|
|
group.byte 0x1F++0x00
|
|
line.byte 0x00 "UART1_TL7816,UART 7816 Transmit Length Register"
|
|
endif
|
|
else
|
|
if ((per.b(ad:0x4006B000+0x18)&0x2)==0x0)
|
|
hgroup.byte 0x1F++0x00
|
|
hide.byte 0x00 "UART1_TL7816,UART 7816 Transmit Length Register"
|
|
else
|
|
rgroup.byte 0x1F++0x00
|
|
line.byte 0x00 "UART1_TL7816,UART 7816 Transmit Length Register"
|
|
endif
|
|
endif
|
|
tree.end
|
|
else
|
|
endif
|
|
sif (cpuis("K70*"))
|
|
group.byte 0x21++0x10
|
|
line.byte 0x00 "UART1_C6,UART CEA709.1-B Control Register 6"
|
|
bitfld.byte 0x00 7. " EN709 ,Enable CEA709.1-B feature" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TX709 ,Enable CEA709.1-B transmission" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 5. " CE ,Collision enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " CP ,Collision signal polarity" "Active low,Active high"
|
|
line.byte 0x01 "UART1_PCTH,UART CEA709.1-B Packet Cycle Time Counter High Register"
|
|
line.byte 0x02 "UART1_PCTL,UART CEA709.1-B Packet Cycle Time Counter Low Register"
|
|
line.byte 0x03 "UART1_B1T,UART CEA709.1-B Beta1 Timer Register"
|
|
line.byte 0x04 "UART1_SDTH,UART CEA709.1-B Secondary Delay Timer High Register"
|
|
line.byte 0x05 "UART1_SDTL,UART CEA709.1-B Secondary Delay Timer Low Register"
|
|
line.byte 0x06 "UART1_PRE,UART CEA709.1-B Preamble Register"
|
|
line.byte 0x07 "UART1_TPL,UART CEA709.1-B Transmit Packet Length Register"
|
|
line.byte 0x08 "UART1_IE,UART CEA709.1-B Interrupt Enable Register"
|
|
bitfld.byte 0x08 6. " WBEIE ,Wbase expired interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x08 5. " ISDIE ,Initial sync detection interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x08 4. " PRXIE ,Packet received interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x08 3. " PTXIE ,Packet transmitted interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x08 2. " PCTEIE ,Packet cycle timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x08 1. " PSIE ,Preamble start interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x08 0. " TXFIE ,Transmission fail interrupt enable" "Disabled,Enabled"
|
|
line.byte 0x09 "UART1_WB,UART CEA709.1-B WBASE Register"
|
|
line.byte 0x0A "UART1_S3,UART CEA709.1-B Status Register"
|
|
bitfld.byte 0x0A 7. " PEF ,Preamble error interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x0A 6. " WBEF ,Wbase expired interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.byte 0x0A 5. " ISD ,Initial sync detection interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.byte 0x0A 4. " PRXF ,Packet received interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.byte 0x0A 3. " PTXF ,Packet transmitted interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x0A 2. " PCTEF ,Packet cycle timer expired interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.byte 0x0A 1. " PSF ,Preamble start interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x0A 0. " TXFF ,Transmission fail interrupt flag" "No interrupt,Interrupt"
|
|
line.byte 0x0B "UART1_S4,UART CEA709.1-B Status Register"
|
|
bitfld.byte 0x0B 4. " INITF ,Initial synchronization fail flag" "Not falled,Falled"
|
|
bitfld.byte 0x0B 2.--3. " CDET ,Collision occuring during transmission" "No collision,Preamble,Data,Line code violation"
|
|
newline
|
|
bitfld.byte 0x0B 1. " ILCV ,Improper line code violation" "Proper,Not proper"
|
|
bitfld.byte 0x0B 0. " FE ,Framing error flag" "No error,Error"
|
|
line.byte 0x0C "UART1_RPL,UART CEA709.1-B Received Packet Length Register"
|
|
line.byte 0x0D "UART1_RPREL,UART CEA709.1-B Received Preamble Length Register"
|
|
line.byte 0x0E "UART1_CPW,UART CEA709.1-B Collision Pulse Width Register"
|
|
line.byte 0x0F "UART1_RIDT,UART CEA709.1-B Receive Indeterminate Time Register"
|
|
line.byte 0x10 "UART1_TIDT,UART CEA709.1-B Transmit Indeterminate Time Register"
|
|
elif (cpu()=="VF7XX-CM4"||cpu()=="VF6XX-CM4"||cpu()=="VF7XX-CA5"||cpu()=="VF6XX-CA5"||cpu()=="VF5XX-CA5"||cpu()=="VF4XX-CA5"||cpu()=="VF3XX-CA5")||(cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")
|
|
tree "UART 1 CEA709.1-B Registers"
|
|
group.byte 0x21++0x09
|
|
line.byte 0x00 "UART1_C6,UART CEA709.1-B Control Register 6"
|
|
bitfld.byte 0x00 7. " EN709 ,Enable CEA709.1-B feature" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TX709 ,Enable CEA709.1-B transmission" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 5. " CE ,Collision enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " CP ,Collision signal polarity" "Active low,Active high"
|
|
line.byte 0x01 "UART1_PCTH,UART CEA709.1-B Packet Cycle Time Counter High Register"
|
|
line.byte 0x02 "UART1_PCTL,UART CEA709.1-B Packet Cycle Time Counter Low Register"
|
|
line.byte 0x03 "UART1_B1T,UART CEA709.1-B Beta1 Timer Register"
|
|
line.byte 0x04 "UART1_SDTH,UART CEA709.1-B Secondary Delay Timer High Register"
|
|
line.byte 0x05 "UART1_SDTL,UART CEA709.1-B Secondary Delay Timer Low Register"
|
|
line.byte 0x06 "UART1_PRE,UART CEA709.1-B Preamble Register"
|
|
line.byte 0x07 "UART1_TPL,UART CEA709.1-B Transmit Packet Length Register"
|
|
line.byte 0x08 "UART1_IE,UART CEA709.1-B Interrupt Enable Register"
|
|
bitfld.byte 0x08 6. " WBEIE ,Wbase expired interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x08 5. " ISDIE ,Initial sync detection interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x08 4. " PRXIE ,Packet received interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x08 3. " PTXIE ,Packet transmitted interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x08 2. " PCTEIE ,Packet cycle timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x08 1. " PSIE ,Preamble start interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x08 0. " TXFIE ,Transmission fail interrupt enable" "Disabled,Enabled"
|
|
line.byte 0x09 "UART1_WB,UART CEA709.1-B WBASE"
|
|
group.byte 0x2B++0x01
|
|
line.byte 0x00 "UART1_S3,UART CEA709.1-B Status Register"
|
|
bitfld.byte 0x00 7. " PEF ,Preamble error interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 6. " WBEF ,Wbase expired interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.byte 0x00 5. " ISD ,Initial sync detection interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 4. " PRXF ,Packet received interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.byte 0x00 3. " PTXF ,Packet transmitted interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 2. " PCTEF ,Packet cycle timer expired interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.byte 0x00 1. " PSF ,Preamble start interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " TXFF ,Transmission fail interrupt flag" "No interrupt,Interrupt"
|
|
line.byte 0x01 "UART1_S4,UART CEA709.1-B Status Register"
|
|
rbitfld.byte 0x01 4. " INITF ,Initial synchronization fail flag" "Not falled,Falled"
|
|
bitfld.byte 0x01 2.--3. " CDET ,Collision occuring during transmission" "No collision,Preamble,Data,Line code violation"
|
|
newline
|
|
bitfld.byte 0x01 1. " ILCV ,Improper line code violation" "Proper,Not proper"
|
|
bitfld.byte 0x01 0. " FE ,Framing error flag" "No error,Error"
|
|
rgroup.byte 0x2D++0x01
|
|
line.byte 0x00 "UART1_RPL,UART CEA709.1-B Received Packet Length Register"
|
|
line.byte 0x01 "UART1_RPREL,UART CEA709.1-B Received Preamble Length Register"
|
|
group.byte 0x2F++0x02
|
|
line.byte 0x00 "UART1_CPW,UART CEA709.1-B Collision Pulse Width Register"
|
|
line.byte 0x01 "UART1_RIDT,UART CEA709.1-B Receive Indeterminate Time Register"
|
|
line.byte 0x02 "UART1_TIDT,UART CEA709.1-B Transmit Indeterminate Time Register"
|
|
tree.end
|
|
elif (cpu()=="MK21DX128VLK5")||(cpu()=="MK21DX256VLK5")||(cpu()=="MK21DN512VLK5")||(cpu()=="MK21DX128VMC5")||(cpu()=="MK21DX256VMC5")||(cpu()=="MK21DN512VMC5")||(cpu()=="MK22DX128VLF5")||(cpu()=="MK22DX256VLF5")||(cpu()=="MK22DX128VLH5")||(cpu()=="MK22DX256VLH5")||(cpu()=="MK22DN512VLH5")||(cpu()=="MK22DX128VLK5")||(cpu()=="MK22DX256VLK5")||(cpu()=="MK22DN512VLK5")||(cpu()=="MK22DX128VMC5")||(cpu()=="MK22DX256VMC5")||(cpu()=="MK22DN512VMC5")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")
|
|
elif (cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART_2"
|
|
base ad:0x4006C000
|
|
width 13.
|
|
tree "UART 2 Standard Features Registers"
|
|
group.byte 0x00++0x03
|
|
line.byte 0x00 "UART2_BDH,UART Baud Rate Register High"
|
|
bitfld.byte 0x00 7. " LBKDIE ,LIN break detect interrupt or DMA request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RXEDGIE ,Rxd input active edge interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("MKL02*")||cpuis("MKL04*")||cpuis("MKL05*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")
|
|
bitfld.byte 0x00 5. " SBNS ,Stop bit number select" "One,Two"
|
|
newline
|
|
endif
|
|
bitfld.byte 0x00 0.--4. " SBR ,UART baud rate bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x01 "UART2_BDL,UART Baud Rate Register Low"
|
|
line.byte 0x02 "UART2_C1,UART Control Register 1"
|
|
bitfld.byte 0x02 7. " LOOPS ,Loop mode select" "Not selected,Selected"
|
|
newline
|
|
sif (cpu()=="VF7XX-CM4"||cpu()=="VF6XX-CM4"||cpu()=="VF7XX-CA5"||cpu()=="VF6XX-CA5"||cpu()=="VF5XX-CA5"||cpu()=="VF4XX-CA5"||cpu()=="VF3XX-CA5")
|
|
bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Internal loop-back mode,Single-wire UART"
|
|
newline
|
|
elif cpuis("MKL02*")||cpuis("MKL04*")||cpuis("MKL05*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")
|
|
bitfld.byte 0x02 6. " UARTSWAI ,UART stops in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Internal loop-back mode,Single-wire UART"
|
|
newline
|
|
elif (cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")||cpuis("MK40D*ZV*10")
|
|
bitfld.byte 0x02 6. " UARTSWAI ,UART stops in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Internal loop-back mode,Single-wire UART"
|
|
newline
|
|
else
|
|
bitfld.byte 0x02 6. " SCISWAI ,UART stops in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Internal loop-back mode,Single-wire UART"
|
|
newline
|
|
endif
|
|
bitfld.byte 0x02 4. " M ,9-bit or 8-bit mode select" "Normal 8 bits+stop,Use 9 bits+stop"
|
|
bitfld.byte 0x02 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark"
|
|
bitfld.byte 0x02 2. " ILT ,Idle line type select" "After start bit,After stop bit"
|
|
newline
|
|
bitfld.byte 0x02 1. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 0. " PT ,Parity type" "Even,Odd"
|
|
line.byte 0x03 "UART2_C2,UART Control Register 2"
|
|
bitfld.byte 0x03 7. " TIE ,Transmitter interrupt or DMA transfer enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 6. " TCIE ,Transmission complete interrupt or DMA transfer enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 5. " RIE ,Receiver full interrupt or DMA transfer enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x03 4. " ILIE ,Idle line interrupt or DMA transfer enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x03 1. " RWU ,Receiver wakeup control" "Normal,Wake-up"
|
|
bitfld.byte 0x03 0. " SBK ,Send break" "Normal,Break"
|
|
sif cpuis("MKL02*")||cpuis("MKL04*")||cpuis("MKL05*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "UART2_S1,UART Status Register 1"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred"
|
|
else
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "UART2_S1,UART Status Register 1"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred"
|
|
endif
|
|
group.byte 0x05++0x01
|
|
line.byte 0x00 "UART2_S2,UART Status Register 2"
|
|
sif cpuis("MKL02*")||cpuis("MKL04*")||cpuis("MKL05*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")||cpuis("MK40D*ZV*10")
|
|
eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,Rxd pin active edge interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
else
|
|
bitfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 6. " RXEDGIF ,Rxd pin active edge interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL02*")||cpuis("MKL04*")||cpuis("MKL05*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")
|
|
else
|
|
bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first"
|
|
newline
|
|
endif
|
|
bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected"
|
|
newline
|
|
sif cpuis("MKL02*")||cpuis("MKL04*")||cpuis("MKL05*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")
|
|
bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bit long,13/14/15 bit long"
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "10/11/12 bit times,11/12/14 bit times"
|
|
newline
|
|
elif (cpu()=="MK21DX128VLK5")||(cpu()=="MK21DX256VLK5")||(cpu()=="MK21DN512VLK5")||(cpu()=="MK21DX128VMC5")||(cpu()=="MK21DX256VMC5")||(cpu()=="MK21DN512VMC5")||(cpu()=="MK22DX128VLF5")||(cpu()=="MK22DX256VLF5")||(cpu()=="MK22DX128VLH5")||(cpu()=="MK22DX256VLH5")||(cpu()=="MK22DN512VLH5")||(cpu()=="MK22DX128VLK5")||(cpu()=="MK22DX256VLK5")||(cpu()=="MK22DN512VLK5")||(cpu()=="MK22DX128VMC5")||(cpu()=="MK22DX256VMC5")||(cpu()=="MK22DN512VMC5")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")
|
|
bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bit long,13/14 bit long"
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable (detected at lenght of)" "10/11/12 bit times,11/12 bit times"
|
|
newline
|
|
else
|
|
bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bit long,13/14 bit long"
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "10 bit times,11 bit times"
|
|
newline
|
|
endif
|
|
sif (cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")||cpuis("MKL02*")||cpuis("MKL04*")||cpuis("MKL05*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")||cpuis("MK40D*ZV*10")
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active"
|
|
else
|
|
bitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active"
|
|
endif
|
|
line.byte 0x01 "UART2_C3,UART Control Register 3"
|
|
sif cpuis("MKL02*")||cpuis("MKL04*")||cpuis("MKL05*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")
|
|
rbitfld.byte 0x01 7. " R8 ,Received bit 8" "No RX,RX"
|
|
bitfld.byte 0x01 6. " T8 ,Transmit bit 8" "No TX,TX"
|
|
newline
|
|
else
|
|
sif (cpu()=="VF7XX-CM4"||cpu()=="VF6XX-CM4"||cpu()=="VF7XX-CA5"||cpu()=="VF6XX-CA5"||cpu()=="VF5XX-CA5"||cpu()=="VF4XX-CA5"||cpu()=="VF3XX-CA5")||(cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")||cpuis("MK40D*ZV*10")
|
|
rbitfld.byte 0x01 7. " R8 ,Received bit 8" "No RX,RX"
|
|
else
|
|
bitfld.byte 0x01 7. " R8 ,Received bit 8" "No RX,RX"
|
|
endif
|
|
bitfld.byte 0x01 6. " T8 ,Transmit bit 8" "No TX,TX"
|
|
newline
|
|
endif
|
|
bitfld.byte 0x01 5. " TXDIR ,Transmitter pin data direction in single-wire mode" "Input,Output"
|
|
newline
|
|
bitfld.byte 0x01 4. " TXINV ,Transmit data inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x01 3. " ORIE ,Overrun error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " NEIE ,Noise error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x01 1. " FEIE ,Framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " PEIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
sif (cpu()=="MK21DX128VLK5")||(cpu()=="MK21DX256VLK5")||(cpu()=="MK21DN512VLK5")||(cpu()=="MK21DX128VMC5")||(cpu()=="MK21DX256VMC5")||(cpu()=="MK21DN512VMC5")||(cpu()=="MK22DX128VLF5")||(cpu()=="MK22DX256VLF5")||(cpu()=="MK22DX128VLH5")||(cpu()=="MK22DX256VLH5")||(cpu()=="MK22DN512VLH5")||(cpu()=="MK22DX128VLK5")||(cpu()=="MK22DX256VLK5")||(cpu()=="MK22DN512VLK5")||(cpu()=="MK22DX128VMC5")||(cpu()=="MK22DX256VMC5")||(cpu()=="MK22DN512VMC5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")||cpuis("MKL02*")||cpuis("MKL04*")||cpuis("MKL05*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")
|
|
hgroup.byte 0x07++0x00
|
|
hide.byte 0x00 "UART2_D,UART Data Register"
|
|
in
|
|
else
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "UART2_D,UART Data Register"
|
|
endif
|
|
sif cpuis("MKL02*")||cpuis("MKL04*")||cpuis("MKL05*")||cpuis("MK14*")||cpuis("MKL14*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "UART2_C4,UART Control Register 4"
|
|
bitfld.byte 0x00 7. " TDMAS ,Transmitter DMA select" "Interrupt service,DMA transfer"
|
|
bitfld.byte 0x00 5. " RDMAS ,Receiver full DMA select" "Interrupt service,DMA transfer"
|
|
newline
|
|
else
|
|
group.byte 0x08++0x03
|
|
line.byte 0x00 "UART2_MA1,UART Match Address Registers 1"
|
|
line.byte 0x01 "UART2_MA2,UART Match Address Registers 2"
|
|
line.byte 0x02 "UART2_C4,UART Control Register 4"
|
|
bitfld.byte 0x02 7. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled"
|
|
bitfld.byte 0x02 6. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled"
|
|
bitfld.byte 0x02 5. " M10 ,10-bit mode select" "Not selected,Selected"
|
|
newline
|
|
bitfld.byte 0x02 0.--4. " BRFA ,Baud rate fine adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x03 "UART2_C5,UART Control Register 5"
|
|
bitfld.byte 0x03 7. " TDMAS ,Transmitter DMA select" "Interrupt service,DMA transfer"
|
|
bitfld.byte 0x03 5. " RDMAS ,Receiver full DMA select" "Interrupt service,DMA transfer"
|
|
endif
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL04*")&&!cpuis("MKL05*")&&!cpuis("MK14*")&&!cpuis("MKL14*")&&!cpuis("MKL24*")&&!cpuis("MK15*")&&!cpuis("MKL15*")&&!cpuis("MKL25*")&&!cpuis("MKL36Z*")&&!cpuis("MKL46Z*")&&!cpuis("MKL34Z*")&&!cpuis("MKL16*")&&!cpuis("MKL26*")
|
|
rgroup.byte 0x0C++0x00
|
|
line.byte 0x00 "UART2_ED,UART Extended Data Register"
|
|
bitfld.byte 0x00 7. " NOISY ,The current received dataword contained in D and C3[R8] was received with noise" "Without noise,With noise"
|
|
bitfld.byte 0x00 6. " PARITYE ,The current received dataword contained in D and C3[R8] was received with a parity error" "Without parity error,With parity error"
|
|
group.byte 0x0D++0x01
|
|
line.byte 0x00 "UART2_MODEM,UART Modem Register"
|
|
bitfld.byte 0x00 3. " RXRTSE ,Receiver request-to-send enable (num of char in RCV data reg fifo>=rwfifo(rxwater)/num of char in RCV data reg FIFO<=RWFIFO(RXWATER))" "No effect,Deasserted/asserted"
|
|
bitfld.byte 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high"
|
|
bitfld.byte 0x00 1. " TXRTSE ,Transmitter request-to-send enable (char placed in empty fifo/after all characters placed to FIFO)" "No effect,Asserted/deasserted"
|
|
newline
|
|
bitfld.byte 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled"
|
|
line.byte 0x01 "UART2_IR,UART Infrared Register"
|
|
bitfld.byte 0x01 2. " IREN ,Infrared enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0.--1. " TNP ,Transmitter narrow pulse" "3/16,1/16,1/32,1/4"
|
|
endif
|
|
tree.end
|
|
sif !cpuis("MKL02*")&&!cpuis("MKL04*")&&!cpuis("MKL05*")&&!cpuis("MK14*")&&!cpuis("MKL14*")&&!cpuis("MKL24*")&&!cpuis("MK15*")&&!cpuis("MKL15*")&&!cpuis("MKL25*")&&!cpuis("MKL36Z*")&&!cpuis("MKL46Z*")&&!cpuis("MKL34Z*")&&!cpuis("MKL16*")&&!cpuis("MKL26*")
|
|
width 16.
|
|
tree "UART 2 FIFO Registers"
|
|
group.byte 0x10++0x03
|
|
line.byte 0x00 "UART2_PFIFO,UART FIFO Parameters"
|
|
bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpu()=="VF7XX-CM4"||cpu()=="VF6XX-CM4"||cpu()=="VF7XX-CA5"||cpu()=="VF6XX-CA5"||cpu()=="VF5XX-CA5"||cpu()=="VF4XX-CA5"||cpu()=="VF3XX-CA5")||(cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")||cpuis("MK40D*ZV*10")
|
|
rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..."
|
|
bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..."
|
|
else
|
|
bitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..."
|
|
bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..."
|
|
endif
|
|
line.byte 0x01 "UART2_CFIFO,UART FIFO Control Register"
|
|
bitfld.byte 0x01 7. " TXFLUSH ,Transmit fifo/buffer flush" "Not flushed,Flushed"
|
|
bitfld.byte 0x01 6. " RXFLUSH ,Receive fifo/buffer flush" "Not flushed,Flushed"
|
|
sif (cpu()=="VF7XX-CM4"||cpu()=="VF6XX-CM4"||cpu()=="VF7XX-CA5"||cpu()=="VF6XX-CA5"||cpu()=="VF5XX-CA5"||cpu()=="VF4XX-CA5"||cpu()=="VF3XX-CA5")||(cpu()=="MK21DX128VLK5")||(cpu()=="MK21DX256VLK5")||(cpu()=="MK21DN512VLK5")||(cpu()=="MK21DX128VMC5")||(cpu()=="MK21DX256VMC5")||(cpu()=="MK21DN512VMC5")||(cpu()=="MK22DX128VLF5")||(cpu()=="MK22DX256VLF5")||(cpu()=="MK22DX128VLH5")||(cpu()=="MK22DX256VLH5")||(cpu()=="MK22DN512VLH5")||(cpu()=="MK22DX128VLK5")||(cpu()=="MK22DX256VLK5")||(cpu()=="MK22DN512VLK5")||(cpu()=="MK22DX128VMC5")||(cpu()=="MK22DX256VMC5")||(cpu()=="MK22DN512VMC5")||(cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")
|
|
newline
|
|
bitfld.byte 0x01 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Not generated,Generated"
|
|
bitfld.byte 0x01 1. " TXOFE ,Transmit FIFO overflow interrupt enable" "Not generated,Generated"
|
|
else
|
|
newline
|
|
bitfld.byte 0x01 1. " TXOFE ,Transmit FIFO overflow interrupt enable" "Not generated,Generated"
|
|
endif
|
|
newline
|
|
bitfld.byte 0x01 0. " RXUFE ,Receive FIFO underflow interrupt enable" "Not generated,Generated"
|
|
line.byte 0x02 "UART2_SFIFO,UART FIFO Status Register"
|
|
sif (cpu()=="VF7XX-CM4"||cpu()=="VF6XX-CM4"||cpu()=="VF7XX-CA5"||cpu()=="VF6XX-CA5"||cpu()=="VF5XX-CA5"||cpu()=="VF4XX-CA5"||cpu()=="VF3XX-CA5")||(cpu()=="MK21DX128VLK5")||(cpu()=="MK21DX256VLK5")||(cpu()=="MK21DN512VLK5")||(cpu()=="MK21DX128VMC5")||(cpu()=="MK21DX256VMC5")||(cpu()=="MK21DN512VMC5")||(cpu()=="MK22DX128VLF5")||(cpu()=="MK22DX256VLF5")||(cpu()=="MK22DX128VLH5")||(cpu()=="MK22DX256VLH5")||(cpu()=="MK22DN512VLH5")||(cpu()=="MK22DX128VLK5")||(cpu()=="MK22DX256VLK5")||(cpu()=="MK22DN512VLK5")||(cpu()=="MK22DX128VMC5")||(cpu()=="MK22DX256VMC5")||(cpu()=="MK22DN512VMC5")||(cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")||(cpu()=="MK20DN512ZCAB10")||(cpu()=="MK20DN512ZAB10")||cpuis("MK40D*ZV*10")
|
|
rbitfld.byte 0x02 7. " TXEMPT ,Transmit buffer/fifo empty" "Not empty,Empty"
|
|
rbitfld.byte 0x02 6. " RXEMPT ,Receive buffer/fifo empty" "Not empty,Empty"
|
|
newline
|
|
sif !cpuis("MK40D*ZV*10")
|
|
eventfld.byte 0x02 2. " RXOF ,Receiver buffer overflow flag" "No overflow,Overflow"
|
|
newline
|
|
endif
|
|
eventfld.byte 0x02 1. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow"
|
|
else
|
|
bitfld.byte 0x02 7. " TXEMPT ,Transmit buffer/fifo empty" "Not empty,Empty"
|
|
bitfld.byte 0x02 6. " RXEMPT ,Receive buffer/fifo empty" "Not empty,Empty"
|
|
eventfld.byte 0x02 1. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow"
|
|
endif
|
|
newline
|
|
eventfld.byte 0x02 0. " RXUF ,Receiver buffer underflow flag" "No overflow,Overflow"
|
|
line.byte 0x03 "UART2_TWFIFO,UART FIFO Transmit Watermark"
|
|
rgroup.byte 0x14++0x00
|
|
line.byte 0x00 "UART2_TCFIFO,UART FIFO Transmit Count"
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "UART2_RWFIFO,UART FIFO Receive Watermark"
|
|
rgroup.byte 0x16++0x00
|
|
line.byte 0x00 "UART2_RCFIFO,UART FIFO Receive Count"
|
|
tree.end
|
|
sif (cpu()=="VF7XX-CM4"||cpu()=="VF6XX-CM4"||cpu()=="VF7XX-CA5"||cpu()=="VF6XX-CA5"||cpu()=="VF5XX-CA5"||cpu()=="VF4XX-CA5"||cpu()=="VF3XX-CA5")
|
|
elif (cpu()=="MK40DN512ZVLQ10")||(cpu()=="MK40DN512ZVMD10")||(cpu()=="MK40DX128ZVLQ10")||(cpu()=="MK40DX256ZVLQ10")||(cpu()=="MK40DX256ZVMD10")||(cpu()=="MK40DN512ZVLL10")
|
|
width 19.
|
|
tree "UART 2 ISO7816 Registers"
|
|
group.byte 0x18++0x02
|
|
line.byte 0x00 "UART2_C7816,UART 7816 Control Register"
|
|
bitfld.byte 0x00 4. " ONACK ,Generate NACK on overflow" "Not generated,Generated"
|
|
bitfld.byte 0x00 3. " ANACK ,Generate NACK on error" "Not generated,Generated"
|
|
bitfld.byte 0x00 2. " INIT ,Detect initial character" "Not detected,Detected"
|
|
newline
|
|
bitfld.byte 0x00 1. " TTYPE ,Transfer type" "0 per the ISO-7816,1 per the ISO-7816"
|
|
bitfld.byte 0x00 0. " ISO_7816E ,ISO-7816 functionality enabled" "Disabled,Enabled"
|
|
line.byte 0x01 "UART2_IE7816,UART 7816 Interrupt Enable Register"
|
|
bitfld.byte 0x01 7. " WTE ,Wait timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " CWTE ,Character wait timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 5. " BWTE ,Block wait timer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x01 4. " INITDE ,Initial character detected interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " GTVE ,Guard timer violated interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 1. " TXTE ,Transmit threshold exceeded interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x01 0. " RXTE ,Receive threshold exceeded interrupt enable" "Disabled,Enabled"
|
|
line.byte 0x02 "UART2_IS7816,UART 7816 Interrupt Status Register"
|
|
eventfld.byte 0x02 7. " WT ,Wait timer interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 6. " CWT ,Character wait timer interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 5. " BWT ,Block wait timer interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x02 4. " INITD ,Initial character detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 2. " GTV ,Guard timer violated interrupt" "No interrupt,Interrupt"
|
|
eventfld.byte 0x02 1. " TXT ,Transmit threshold exceeded interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.byte 0x02 0. " RXT ,Receive threshold exceeded interrupt" "No interrupt,Interrupt"
|
|
if ((per.b(ad:0x4006C000+0x18)&0x1)==0x1)
|
|
if ((per.b(ad:0x4006C000+0x18)&0x2)==0x0)
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "UART2_WP7816T0,UART 7816 Wait Parameter Register"
|
|
else
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "UART2_WP7816T1,UART 7816 Wait Parameter Register"
|
|
bitfld.byte 0x00 4.--7. " CWI ,Character wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " BWI ,Block wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
rgroup.byte 0x1C++0x02
|
|
line.byte 0x00 "UART2_WN7816,UART 7816 Wait N Register"
|
|
line.byte 0x01 "UART2_WF7816,UART 7816 Wait FD Register"
|
|
line.byte 0x02 "UART2_ET7816,UART 7816 Error Threshold Register"
|
|
bitfld.byte 0x02 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x02 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
if ((per.b(ad:0x4006C000+0x18)&0x2)==0x0)
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "UART2_WP7816T0,UART 7816 Wait Parameter Register"
|
|
else
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "UART2_WP7816T1,UART 7816 Wait Parameter Register"
|
|
bitfld.byte 0x00 4.--7. " CWI ,Character wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " BWI ,Block wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.byte 0x1C++0x02
|
|
line.byte 0x00 "UART2_WN7816,UART 7816 Wait N Register"
|
|
line.byte 0x01 "UART2_WF7816,UART 7816 Wait FD Register"
|
|
line.byte 0x02 "UART2_ET7816,UART 7816 Error Threshold Register"
|
|
bitfld.byte 0x02 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x02 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if ((per.b(ad:0x4006C000+0x03)&0x8)==0x8)
|
|
if ((per.b(ad:0x4006C000+0x18)&0x2)==0x0)
|
|
hgroup.byte 0x1F++0x00
|
|
hide.byte 0x00 "UART2_TL7816,UART 7816 Transmit Length Register"
|
|
else
|
|
group.byte 0x1F++0x00
|
|
line.byte 0x00 "UART2_TL7816,UART 7816 Transmit Length Register"
|
|
endif
|
|
else
|
|
if ((per.b(ad:0x4006C000+0x18)&0x2)==0x0)
|
|
hgroup.byte 0x1F++0x00
|
|
hide.byte 0x00 "UART2_TL7816,UART 7816 Transmit Length Register"
|
|
else
|
|
rgroup.byte 0x1F++0x00
|
|
line.byte 0x00 "UART2_TL7816,UART 7816 Transmit Length Register"
|
|
endif
|
|
endif
|
|
tree.end
|
|
else
|
|
endif
|
|
sif (cpuis("K70*"))
|
|
group.byte 0x21++0x10
|
|
line.byte 0x00 "UART2_C6,UART CEA709.1-B Control Register 6"
|
|
bitfld.byte 0x00 7. " EN709 ,Enable CEA709.1-B feature" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TX709 ,Enable CEA709.1-B transmission" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 5. " CE ,Collision enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " CP ,Collision signal polarity" "Active low,Active high"
|
|
line.byte 0x01 "UART2_PCTH,UART CEA709.1-B Packet Cycle Time Counter High Register"
|
|
line.byte 0x02 "UART2_PCTL,UART CEA709.1-B Packet Cycle Time Counter Low Register"
|
|
line.byte 0x03 "UART2_B1T,UART CEA709.1-B Beta1 Timer Register"
|
|
line.byte 0x04 "UART2_SDTH,UART CEA709.1-B Secondary Delay Timer High Register"
|
|
line.byte 0x05 "UART2_SDTL,UART CEA709.1-B Secondary Delay Timer Low Register"
|
|
line.byte 0x06 "UART2_PRE,UART CEA709.1-B Preamble Register"
|
|
line.byte 0x07 "UART2_TPL,UART CEA709.1-B Transmit Packet Length Register"
|
|
line.byte 0x08 "UART2_IE,UART CEA709.1-B Interrupt Enable Register"
|
|
bitfld.byte 0x08 6. " WBEIE ,Wbase expired interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x08 5. " ISDIE ,Initial sync detection interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x08 4. " PRXIE ,Packet received interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x08 3. " PTXIE ,Packet transmitted interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x08 2. " PCTEIE ,Packet cycle timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x08 1. " PSIE ,Preamble start interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x08 0. " TXFIE ,Transmission fail interrupt enable" "Disabled,Enabled"
|
|
line.byte 0x09 "UART2_WB,UART CEA709.1-B WBASE Register"
|
|
line.byte 0x0A "UART2_S3,UART CEA709.1-B Status Register"
|
|
bitfld.byte 0x0A 7. " PEF ,Preamble error interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x0A 6. " WBEF ,Wbase expired interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.byte 0x0A 5. " ISD ,Initial sync detection interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.byte 0x0A 4. " PRXF ,Packet received interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.byte 0x0A 3. " PTXF ,Packet transmitted interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x0A 2. " PCTEF ,Packet cycle timer expired interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.byte 0x0A 1. " PSF ,Preamble start interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x0A 0. " TXFF ,Transmission fail interrupt flag" "No interrupt,Interrupt"
|
|
line.byte 0x0B "UART2_S4,UART CEA709.1-B Status Register"
|
|
bitfld.byte 0x0B 4. " INITF ,Initial synchronization fail flag" "Not falled,Falled"
|
|
bitfld.byte 0x0B 2.--3. " CDET ,Collision occuring during transmission" "No collision,Preamble,Data,Line code violation"
|
|
newline
|
|
bitfld.byte 0x0B 1. " ILCV ,Improper line code violation" "Proper,Not proper"
|
|
bitfld.byte 0x0B 0. " FE ,Framing error flag" "No error,Error"
|
|
line.byte 0x0C "UART2_RPL,UART CEA709.1-B Received Packet Length Register"
|
|
line.byte 0x0D "UART2_RPREL,UART CEA709.1-B Received Preamble Length Register"
|
|
line.byte 0x0E "UART2_CPW,UART CEA709.1-B Collision Pulse Width Register"
|
|
line.byte 0x0F "UART2_RIDT,UART CEA709.1-B Receive Indeterminate Time Register"
|
|
line.byte 0x10 "UART2_TIDT,UART CEA709.1-B Transmit Indeterminate Time Register"
|
|
elif (cpu()=="VF7XX-CM4"||cpu()=="VF6XX-CM4"||cpu()=="VF7XX-CA5"||cpu()=="VF6XX-CA5"||cpu()=="VF5XX-CA5"||cpu()=="VF4XX-CA5"||cpu()=="VF3XX-CA5")||(cpu()=="MK50DX128CMC7")||(cpu()=="MK50DX256CMC7")||(cpu()=="MK51DX128CMC7")||(cpu()=="MK51DX256CMC7")||(cpu()=="MK40DX64VMC7")||(cpu()=="MK40DX128VMC7")||(cpu()=="MK40DX256VMC7")
|
|
tree "UART 2 CEA709.1-B Registers"
|
|
group.byte 0x21++0x09
|
|
line.byte 0x00 "UART2_C6,UART CEA709.1-B Control Register 6"
|
|
bitfld.byte 0x00 7. " EN709 ,Enable CEA709.1-B feature" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " TX709 ,Enable CEA709.1-B transmission" "Disabled,Enabled"
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|
newline
|
|
bitfld.byte 0x00 5. " CE ,Collision enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " CP ,Collision signal polarity" "Active low,Active high"
|
|
line.byte 0x01 "UART2_PCTH,UART CEA709.1-B Packet Cycle Time Counter High Register"
|
|
line.byte 0x02 "UART2_PCTL,UART CEA709.1-B Packet Cycle Time Counter Low Register"
|
|
line.byte 0x03 "UART2_B1T,UART CEA709.1-B Beta1 Timer Register"
|
|
line.byte 0x04 "UART2_SDTH,UART CEA709.1-B Secondary Delay Timer High Register"
|
|
line.byte 0x05 "UART2_SDTL,UART CEA709.1-B Secondary Delay Timer Low Register"
|
|
line.byte 0x06 "UART2_PRE,UART CEA709.1-B Preamble Register"
|
|
line.byte 0x07 "UART2_TPL,UART CEA709.1-B Transmit Packet Length Register"
|
|
line.byte 0x08 "UART2_IE,UART CEA709.1-B Interrupt Enable Register"
|
|
bitfld.byte 0x08 6. " WBEIE ,Wbase expired interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x08 5. " ISDIE ,Initial sync detection interrupt enable" "Disabled,Enabled"
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|
newline
|
|
bitfld.byte 0x08 4. " PRXIE ,Packet received interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x08 3. " PTXIE ,Packet transmitted interrupt enable" "Disabled,Enabled"
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|
newline
|
|
bitfld.byte 0x08 2. " PCTEIE ,Packet cycle timer interrupt enable" "Disabled,Enabled"
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|
bitfld.byte 0x08 1. " PSIE ,Preamble start interrupt enable" "Disabled,Enabled"
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|
newline
|
|
bitfld.byte 0x08 0. " TXFIE ,Transmission fail interrupt enable" "Disabled,Enabled"
|
|
line.byte 0x09 "UART2_WB,UART CEA709.1-B WBASE"
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|
group.byte 0x2B++0x01
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line.byte 0x00 "UART2_S3,UART CEA709.1-B Status Register"
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bitfld.byte 0x00 7. " PEF ,Preamble error interrupt flag" "No interrupt,Interrupt"
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|
bitfld.byte 0x00 6. " WBEF ,Wbase expired interrupt flag" "No interrupt,Interrupt"
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|
newline
|
|
rbitfld.byte 0x00 5. " ISD ,Initial sync detection interrupt enable" "No interrupt,Interrupt"
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|
bitfld.byte 0x00 4. " PRXF ,Packet received interrupt flag" "No interrupt,Interrupt"
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|
newline
|
|
bitfld.byte 0x00 3. " PTXF ,Packet transmitted interrupt flag" "No interrupt,Interrupt"
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|
bitfld.byte 0x00 2. " PCTEF ,Packet cycle timer expired interrupt flag" "No interrupt,Interrupt"
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|
newline
|
|
bitfld.byte 0x00 1. " PSF ,Preamble start interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " TXFF ,Transmission fail interrupt flag" "No interrupt,Interrupt"
|
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line.byte 0x01 "UART2_S4,UART CEA709.1-B Status Register"
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rbitfld.byte 0x01 4. " INITF ,Initial synchronization fail flag" "Not falled,Falled"
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bitfld.byte 0x01 2.--3. " CDET ,Collision occuring during transmission" "No collision,Preamble,Data,Line code violation"
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|
newline
|
|
bitfld.byte 0x01 1. " ILCV ,Improper line code violation" "Proper,Not proper"
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|
bitfld.byte 0x01 0. " FE ,Framing error flag" "No error,Error"
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|
rgroup.byte 0x2D++0x01
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line.byte 0x00 "UART2_RPL,UART CEA709.1-B Received Packet Length Register"
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|
line.byte 0x01 "UART2_RPREL,UART CEA709.1-B Received Preamble Length Register"
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|
group.byte 0x2F++0x02
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line.byte 0x00 "UART2_CPW,UART CEA709.1-B Collision Pulse Width Register"
|
|
line.byte 0x01 "UART2_RIDT,UART CEA709.1-B Receive Indeterminate Time Register"
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line.byte 0x02 "UART2_TIDT,UART CEA709.1-B Transmit Indeterminate Time Register"
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|
tree.end
|
|
elif (cpu()=="MK21DX128VLK5")||(cpu()=="MK21DX256VLK5")||(cpu()=="MK21DN512VLK5")||(cpu()=="MK21DX128VMC5")||(cpu()=="MK21DX256VMC5")||(cpu()=="MK21DN512VMC5")||(cpu()=="MK22DX128VLF5")||(cpu()=="MK22DX256VLF5")||(cpu()=="MK22DX128VLH5")||(cpu()=="MK22DX256VLH5")||(cpu()=="MK22DN512VLH5")||(cpu()=="MK22DX128VLK5")||(cpu()=="MK22DX256VLK5")||(cpu()=="MK22DN512VLK5")||(cpu()=="MK22DX128VMC5")||(cpu()=="MK22DX256VMC5")||(cpu()=="MK22DN512VMC5")||(cpu()=="MK30DX64VMC7")||(cpu()=="MK30DX128VMC7")||(cpu()=="MK30DX256VMC7")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DN32VMP5")||(cpu()=="MK20DN64VMP5")||(cpu()=="MK20DN128VMP5")||(cpu()=="MK20DX32VMP5")||(cpu()=="MK20DX64VMP5")||(cpu()=="MK20DX128VMC7")||(cpu()=="MK20DX256VMC7")||(cpu()=="MK20DX64VMC7")
|
|
elif (cpu()=="MK60DN512ZAB10")||(cpu()=="MK60DN512ZCAB10")
|
|
endif
|
|
endif
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|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("MKL13Z*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MKL82Z*")
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|
tree "FLEXIO"
|
|
base ad:0x4005F000
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width 12.
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rgroup.long 0x00++0x07 "Common Registers"
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line.long 0x00 "VERID,Version ID Register"
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hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major revision number"
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|
hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor revision number"
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hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number"
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|
line.long 0x04 "PARAM,Parameter Register"
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|
hexmask.long.byte 0x04 24.--31. 1. " TRIGGER ,Number of external triggers implemented"
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|
hexmask.long.byte 0x04 16.--23. 1. " PIN ,Number of pins implemented"
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|
hexmask.long.byte 0x04 8.--15. 1. " TIMER ,Number of timers implemented"
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|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. " SHIFTER ,Number of shifters implemented"
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|
group.long 0x08++0x03
|
|
line.long 0x00 "CTRL,Flexio Control Register"
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bitfld.long 0x00 31. " DOZEN ,Disables flexio operation in doze modes" "Flexio enabled,Flexio disabled"
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|
bitfld.long 0x00 30. " DBGE ,Enables flexio operation in debug mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FASTACC ,Enables fast register accesses to flexio registers" "Normal access,Fast access"
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|
newline
|
|
bitfld.long 0x00 1. " SWRST ,Software reset" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FLEXEN ,Flexio module enable" "Disabled,Enabled"
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|
newline
|
|
sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*")||cpuis("IMXRT1021")
|
|
rgroup.long 0x0C++0x03
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|
line.long 0x00 "PIN,Pin State Register"
|
|
bitfld.long 0x00 31. " PDI[31] ,Pin 31 data input" "0,1"
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|
bitfld.long 0x00 30. " PDI[30] ,Pin 30 data input" "0,1"
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|
bitfld.long 0x00 29. " PDI[29] ,Pin 29 data input" "0,1"
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bitfld.long 0x00 28. " PDI[28] ,Pin 28 data input" "0,1"
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newline
|
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bitfld.long 0x00 27. " PDI[27] ,Pin 27 data input" "0,1"
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bitfld.long 0x00 26. " PDI[26] ,Pin 26 data input" "0,1"
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bitfld.long 0x00 25. " PDI[25] ,Pin 25 data input" "0,1"
|
|
bitfld.long 0x00 24. " PDI[24] ,Pin 24 data input" "0,1"
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|
newline
|
|
bitfld.long 0x00 23. " PDI[23] ,Pin 23 data input" "0,1"
|
|
bitfld.long 0x00 22. " PDI[22] ,Pin 22 data input" "0,1"
|
|
bitfld.long 0x00 21. " PDI[21] ,Pin 21 data input" "0,1"
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|
bitfld.long 0x00 20. " PDI[20] ,Pin 20 data input" "0,1"
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|
newline
|
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bitfld.long 0x00 19. " PDI[19] ,Pin 19 data input" "0,1"
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bitfld.long 0x00 18. " PDI[18] ,Pin 18 data input" "0,1"
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bitfld.long 0x00 17. " PDI[17] ,Pin 17 data input" "0,1"
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bitfld.long 0x00 16. " PDI[16] ,Pin 16 data input" "0,1"
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|
newline
|
|
bitfld.long 0x00 15. " PDI[15] ,Pin 15 data input" "0,1"
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bitfld.long 0x00 14. " PDI[14] ,Pin 14 data input" "0,1"
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bitfld.long 0x00 13. " PDI[13] ,Pin 13 data input" "0,1"
|
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bitfld.long 0x00 12. " PDI[12] ,Pin 12 data input" "0,1"
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|
newline
|
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bitfld.long 0x00 11. " PDI[11] ,Pin 11 data input" "0,1"
|
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bitfld.long 0x00 10. " PDI[10] ,Pin 10 data input" "0,1"
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bitfld.long 0x00 9. " PDI[9] ,Pin 9 data input" "0,1"
|
|
bitfld.long 0x00 8. " PDI[8] ,Pin 8 data input" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. " PDI[7] ,Pin 7 data input" "0,1"
|
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bitfld.long 0x00 6. " PDI[6] ,Pin 6 data input" "0,1"
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bitfld.long 0x00 5. " PDI[5] ,Pin 5 data input" "0,1"
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bitfld.long 0x00 4. " PDI[4] ,Pin 4 data input" "0,1"
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|
newline
|
|
bitfld.long 0x00 3. " PDI[3] ,Pin 3 data input" "0,1"
|
|
bitfld.long 0x00 2. " PDI[2] ,Pin 2 data input" "0,1"
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|
bitfld.long 0x00 1. " PDI[1] ,Pin 1 data input" "0,1"
|
|
bitfld.long 0x00 0. " PDI[0] ,Pin 0 data input" "0,1"
|
|
endif
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "SHIFTSTAT,Shifter Status Register"
|
|
sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*")
|
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eventfld.long 0x00 7. " SSF[7] ,Shifter 7 status flag" "Cleared,Set"
|
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eventfld.long 0x00 6. " SSF[6] ,Shifter 6 status flag" "Cleared,Set"
|
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eventfld.long 0x00 5. " SSF[5] ,Shifter 5 status flag" "Cleared,Set"
|
|
eventfld.long 0x00 4. " SSF[4] ,Shifter 4 status flag" "Cleared,Set"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 3. " SSF[3] ,Shifter 3 status flag" "Cleared,Set"
|
|
eventfld.long 0x00 2. " SSF[2] ,Shifter 2 status flag" "Cleared,Set"
|
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eventfld.long 0x00 1. " SSF[1] ,Shifter 1 status flag" "Cleared,Set"
|
|
eventfld.long 0x00 0. " SSF[0] ,Shifter 0 status flag" "Cleared,Set"
|
|
line.long 0x04 "SHIFTERR,Shifter Error Register"
|
|
sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*")
|
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eventfld.long 0x04 7. " SEF[7] ,Shifter 7 error flags" "Cleared,Set"
|
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eventfld.long 0x04 6. " SEF[6] ,Shifter 6 error flags" "Cleared,Set"
|
|
eventfld.long 0x04 5. " SEF[5] ,Shifter 5 error flags" "Cleared,Set"
|
|
eventfld.long 0x04 4. " SEF[4] ,Shifter 4 error flags" "Cleared,Set"
|
|
newline
|
|
endif
|
|
eventfld.long 0x04 3. " SEF[3] ,Shifter 3 error flags" "Cleared,Set"
|
|
eventfld.long 0x04 2. " SEF[2] ,Shifter 2 error flags" "Cleared,Set"
|
|
eventfld.long 0x04 1. " SEF[1] ,Shifter 1 error flags" "Cleared,Set"
|
|
eventfld.long 0x04 0. " SEF[0] ,Shifter 0 error flags" "Cleared,Set"
|
|
line.long 0x08 "TIMSTAT,Timer Status Register"
|
|
sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*")
|
|
eventfld.long 0x08 7. " TSF[7] ,Timer 7 status flags" "Cleared,Set"
|
|
eventfld.long 0x08 6. " TSF[6] ,Timer 6 status flags" "Cleared,Set"
|
|
eventfld.long 0x08 5. " TSF[5] ,Timer 5 status flags" "Cleared,Set"
|
|
eventfld.long 0x08 4. " TSF[4] ,Timer 4 status flags" "Cleared,Set"
|
|
newline
|
|
endif
|
|
eventfld.long 0x08 3. " TSF[3] ,Timer 3 status flags" "Cleared,Set"
|
|
eventfld.long 0x08 2. " TSF[2] ,Timer 2 status flags" "Cleared,Set"
|
|
eventfld.long 0x08 1. " TSF[1] ,Timer 1 status flags" "Cleared,Set"
|
|
eventfld.long 0x08 0. " TSF[0] ,Timer 0 status flags" "Cleared,Set"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "SHIFTSIEN,Shifter Status Interrupt Enable Register"
|
|
sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*")
|
|
bitfld.long 0x00 7. " SSIE[7] ,Enables interrupt generation when SSF[7] is set" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SSIE[6] ,Enables interrupt generation when SSF[6] is set" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SSIE[5] ,Enables interrupt generation when SSF[5] is set" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SSIE[4] ,Enables interrupt generation when SSF[4] is set" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " SSIE[3] ,Enables interrupt generation when SSF[3] is set" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SSIE[2] ,Enables interrupt generation when SSF[2] is set" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SSIE[1] ,Enables interrupt generation when SSF[1] is set" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSIE[0] ,Enables interrupt generation when SSF[0] is set" "Disabled,Enabled"
|
|
line.long 0x04 "SHIFTEIEN,Shifter Error Interrupt Enable Register"
|
|
sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*")
|
|
bitfld.long 0x04 7. " SEIE[7] ,Enables interrupt generation when SEF[7] is set" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " SEIE[6] ,Enables interrupt generation when SEF[6] is set" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " SEIE[5] ,Enables interrupt generation when SEF[5] is set" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " SEIE[4] ,Enables interrupt generation when SEF[4] is set" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 3. " SEIE[3] ,Enables interrupt generation when SEF[3] is set" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SEIE[2] ,Enables interrupt generation when SEF[2] is set" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " SEIE[1] ,Enables interrupt generation when SEF[1] is set" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " SEIE[0] ,Enables interrupt generation when SEF[0] is set" "Disabled,Enabled"
|
|
line.long 0x08 "TIMIEN,Timer Interrupt Enable Register"
|
|
sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*")
|
|
bitfld.long 0x08 7. " TEIE[7] ,Enables interrupt generation when TSF[7] is set" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " TEIE[6] ,Enables interrupt generation when TSF[6] is set" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " TEIE[5] ,Enables interrupt generation when TSF[5] is set" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TEIE[4] ,Enables interrupt generation when TSF[4] is set" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x08 3. " TEIE[3] ,Enables interrupt generation when TSF[3] is set" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " TEIE[2] ,Enables interrupt generation when TSF[2] is set" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " TEIE[1] ,Enables interrupt generation when TSF[1] is set" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TEIE[0] ,Enables interrupt generation when TSF[0] is set" "Disabled,Enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SHIFTSDEN,Shifter Status DMA Enable Register"
|
|
sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*")
|
|
bitfld.long 0x00 7. " SSDE[7] ,Enables DMA request generation when SSF[7] is set" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SSDE[6] ,Enables DMA request generation when SSF[6] is set" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SSDE[5] ,Enables DMA request generation when SSF[5] is set" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SSDE[4] ,Enables DMA request generation when SSF[4] is set" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " SSDE[3] ,Enables DMA request generation when SSF[3] is set" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SSDE[2] ,Enables DMA request generation when SSF[2] is set" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SSDE[1] ,Enables DMA request generation when SSF[1] is set" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSDE[0] ,Enables DMA request generation when SSF[0] is set" "Disabled,Enabled"
|
|
sif cpuis("MK84FN2M0CAU15R")
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SHIFTSTATE,Shifter State Register"
|
|
bitfld.long 0x00 0.--3. " STATE ,Current state pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
elif cpuis("MK8?FN256V*")||cpuis("MKL82Z*")||cpuis("IMXRT1021")
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SHIFTSTATE,Shifter State Register"
|
|
bitfld.long 0x00 0.--2. " STATE ,Current state pointer" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*")
|
|
width 17.
|
|
tree "Shifter Registers"
|
|
group.long (0x0+0x80)++0x03
|
|
line.long 0x00 "SHIFTCTL_0,Shifter Control 0 Register"
|
|
bitfld.long 0x00 24.--26. " TIMSEL ,Selects which timer is used for controlling the logic/shift register and generating the shift clock" "Timer 0,Timer 1,Timer 2,Timer 3,Timer 4,Timer 5,Timer 6,Timer 7"
|
|
bitfld.long 0x00 23. " TIMPOL ,Timer polarity" "Posedge,Negedge"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Shifter pin configuration" "Disabled,Open drain or bidir/Out,Bidir/Out data,Output"
|
|
newline
|
|
bitfld.long 0x00 8.--12. " PINSEL ,Shifter pin select" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7,FXIO0_D8,FXIO0_D9,FXIO0_D10,FXIO0_D11,FXIO0_D12,FXIO0_D13,FXIO0_D14,FXIO0_D15,FXIO0_D16,FXIO0_D17,FXIO0_D18,FXIO0_D19,FXIO0_D20,FXIO0_D21,FXIO0_D22,FXIO0_D23,FXIO0_D24,FXIO0_D25,FXIO0_D26,FXIO0_D27,FXIO0_D28,FXIO0_D29,FXIO0_D30,FXIO0_D31"
|
|
bitfld.long 0x00 7. " PINPOL ,Shifter pin polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0.--2. " SMOD ,Configures the mode of the shifter" "Disabled,Receive mode,Transmit mode,,Match store,Match continuous,State mode,Logic mode"
|
|
newline
|
|
if (((per.l(ad:0x4005F000+0x80+0x0))&0x07)==0x05)
|
|
group.long (0x0+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_0,Shifter Configuration 0 Register"
|
|
bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit shift,4-bit shift,4-bit shift,4-bit shift,8-bit shift,8-bit shift,8-bit shift,8-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift"
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
group.long (0x0+0x200)++0x03
|
|
line.long 0x00 "SHIFTBUF_0,Shifter Buffer 0 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " SHIFTBUF[31:16] ,Shift buffer data to match"
|
|
newline
|
|
bitfld.long 0x00 15. " SHIFTBUF[15] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " SHIFTBUF[14] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 13. " SHIFTBUF[13] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " SHIFTBUF[12] ,Shift buffer mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 11. " SHIFTBUF[11] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " SHIFTBUF[10] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " SHIFTBUF[9] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " SHIFTBUF[8] ,Shift buffer mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 7. " SHIFTBUF[7] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " SHIFTBUF[6] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " SHIFTBUF[5] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " SHIFTBUF[4] ,Shift buffer mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 3. " SHIFTBUF[3] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " SHIFTBUF[2] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " SHIFTBUF[1] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " SHIFTBUF[0] ,Shift buffer mask" "Not masked,Masked"
|
|
group.long (0x0+0x280)++0x03
|
|
line.long 0x00 "SHIFTBUFBIS_0,Shifter Buffer 0 Bit Swapped Register"
|
|
group.long (0x0+0x300)++0x03
|
|
line.long 0x00 "SHIFTBUFBYS_0,Shifter Buffer 0 Byte Swapped Register"
|
|
group.long (0x0+0x380)++0x03
|
|
line.long 0x00 "SHIFTBUFBBS_0,Shifter Buffer 0 Bit Byte Swapped Register"
|
|
else
|
|
group.long (0x0+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_0,Shifter Configuration 0 Register"
|
|
bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit shift,4-bit shift,4-bit shift,4-bit shift,8-bit shift,8-bit shift,8-bit shift,8-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift"
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,0 on store,1 on store"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled / load on enable,Disabled / load on first shift,0 before first shift,1 before first shift"
|
|
group.long (0x0+0x200)++0x03
|
|
line.long 0x00 "SHIFTBUF_0,Shifter Buffer 0 Register"
|
|
group.long (0x0+0x280)++0x03
|
|
line.long 0x00 "SHIFTBUFBIS_0,Shifter Buffer 0 Bit Swapped Register"
|
|
group.long (0x0+0x300)++0x03
|
|
line.long 0x00 "SHIFTBUFBYS_0,Shifter Buffer 0 Byte Swapped Register"
|
|
group.long (0x0+0x380)++0x03
|
|
line.long 0x00 "SHIFTBUFBBS_0,Shifter Buffer 0 Bit Byte Swapped Register"
|
|
endif
|
|
group.long (0x4+0x80)++0x03
|
|
line.long 0x00 "SHIFTCTL_1,Shifter Control 1 Register"
|
|
bitfld.long 0x00 24.--26. " TIMSEL ,Selects which timer is used for controlling the logic/shift register and generating the shift clock" "Timer 0,Timer 1,Timer 2,Timer 3,Timer 4,Timer 5,Timer 6,Timer 7"
|
|
bitfld.long 0x00 23. " TIMPOL ,Timer polarity" "Posedge,Negedge"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Shifter pin configuration" "Disabled,Open drain or bidir/Out,Bidir/Out data,Output"
|
|
newline
|
|
bitfld.long 0x00 8.--12. " PINSEL ,Shifter pin select" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7,FXIO0_D8,FXIO0_D9,FXIO0_D10,FXIO0_D11,FXIO0_D12,FXIO0_D13,FXIO0_D14,FXIO0_D15,FXIO0_D16,FXIO0_D17,FXIO0_D18,FXIO0_D19,FXIO0_D20,FXIO0_D21,FXIO0_D22,FXIO0_D23,FXIO0_D24,FXIO0_D25,FXIO0_D26,FXIO0_D27,FXIO0_D28,FXIO0_D29,FXIO0_D30,FXIO0_D31"
|
|
bitfld.long 0x00 7. " PINPOL ,Shifter pin polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0.--2. " SMOD ,Configures the mode of the shifter" "Disabled,Receive mode,Transmit mode,,Match store,Match continuous,State mode,Logic mode"
|
|
newline
|
|
if (((per.l(ad:0x4005F000+0x80+0x4))&0x07)==0x05)
|
|
group.long (0x4+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_1,Shifter Configuration 1 Register"
|
|
bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit shift,4-bit shift,4-bit shift,4-bit shift,8-bit shift,8-bit shift,8-bit shift,8-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift"
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
group.long (0x4+0x200)++0x03
|
|
line.long 0x00 "SHIFTBUF_1,Shifter Buffer 1 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " SHIFTBUF[31:16] ,Shift buffer data to match"
|
|
newline
|
|
bitfld.long 0x00 15. " SHIFTBUF[15] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " SHIFTBUF[14] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 13. " SHIFTBUF[13] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " SHIFTBUF[12] ,Shift buffer mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 11. " SHIFTBUF[11] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " SHIFTBUF[10] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " SHIFTBUF[9] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " SHIFTBUF[8] ,Shift buffer mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 7. " SHIFTBUF[7] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " SHIFTBUF[6] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " SHIFTBUF[5] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " SHIFTBUF[4] ,Shift buffer mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 3. " SHIFTBUF[3] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " SHIFTBUF[2] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " SHIFTBUF[1] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " SHIFTBUF[0] ,Shift buffer mask" "Not masked,Masked"
|
|
group.long (0x4+0x280)++0x03
|
|
line.long 0x00 "SHIFTBUFBIS_1,Shifter Buffer 1 Bit Swapped Register"
|
|
group.long (0x4+0x300)++0x03
|
|
line.long 0x00 "SHIFTBUFBYS_1,Shifter Buffer 1 Byte Swapped Register"
|
|
group.long (0x4+0x380)++0x03
|
|
line.long 0x00 "SHIFTBUFBBS_1,Shifter Buffer 1 Bit Byte Swapped Register"
|
|
else
|
|
group.long (0x4+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_1,Shifter Configuration 1 Register"
|
|
bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit shift,4-bit shift,4-bit shift,4-bit shift,8-bit shift,8-bit shift,8-bit shift,8-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift"
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,0 on store,1 on store"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled / load on enable,Disabled / load on first shift,0 before first shift,1 before first shift"
|
|
group.long (0x4+0x200)++0x03
|
|
line.long 0x00 "SHIFTBUF_1,Shifter Buffer 1 Register"
|
|
group.long (0x4+0x280)++0x03
|
|
line.long 0x00 "SHIFTBUFBIS_1,Shifter Buffer 1 Bit Swapped Register"
|
|
group.long (0x4+0x300)++0x03
|
|
line.long 0x00 "SHIFTBUFBYS_1,Shifter Buffer 1 Byte Swapped Register"
|
|
group.long (0x4+0x380)++0x03
|
|
line.long 0x00 "SHIFTBUFBBS_1,Shifter Buffer 1 Bit Byte Swapped Register"
|
|
endif
|
|
group.long (0x8+0x80)++0x03
|
|
line.long 0x00 "SHIFTCTL_2,Shifter Control 2 Register"
|
|
bitfld.long 0x00 24.--26. " TIMSEL ,Selects which timer is used for controlling the logic/shift register and generating the shift clock" "Timer 0,Timer 1,Timer 2,Timer 3,Timer 4,Timer 5,Timer 6,Timer 7"
|
|
bitfld.long 0x00 23. " TIMPOL ,Timer polarity" "Posedge,Negedge"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Shifter pin configuration" "Disabled,Open drain or bidir/Out,Bidir/Out data,Output"
|
|
newline
|
|
bitfld.long 0x00 8.--12. " PINSEL ,Shifter pin select" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7,FXIO0_D8,FXIO0_D9,FXIO0_D10,FXIO0_D11,FXIO0_D12,FXIO0_D13,FXIO0_D14,FXIO0_D15,FXIO0_D16,FXIO0_D17,FXIO0_D18,FXIO0_D19,FXIO0_D20,FXIO0_D21,FXIO0_D22,FXIO0_D23,FXIO0_D24,FXIO0_D25,FXIO0_D26,FXIO0_D27,FXIO0_D28,FXIO0_D29,FXIO0_D30,FXIO0_D31"
|
|
bitfld.long 0x00 7. " PINPOL ,Shifter pin polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0.--2. " SMOD ,Configures the mode of the shifter" "Disabled,Receive mode,Transmit mode,,Match store,Match continuous,State mode,Logic mode"
|
|
newline
|
|
if (((per.l(ad:0x4005F000+0x80+0x8))&0x07)==0x05)
|
|
group.long (0x8+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_2,Shifter Configuration 2 Register"
|
|
bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit shift,4-bit shift,4-bit shift,4-bit shift,8-bit shift,8-bit shift,8-bit shift,8-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift"
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
group.long (0x8+0x200)++0x03
|
|
line.long 0x00 "SHIFTBUF_2,Shifter Buffer 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " SHIFTBUF[31:16] ,Shift buffer data to match"
|
|
newline
|
|
bitfld.long 0x00 15. " SHIFTBUF[15] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " SHIFTBUF[14] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 13. " SHIFTBUF[13] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " SHIFTBUF[12] ,Shift buffer mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 11. " SHIFTBUF[11] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " SHIFTBUF[10] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " SHIFTBUF[9] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " SHIFTBUF[8] ,Shift buffer mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 7. " SHIFTBUF[7] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " SHIFTBUF[6] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " SHIFTBUF[5] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " SHIFTBUF[4] ,Shift buffer mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 3. " SHIFTBUF[3] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " SHIFTBUF[2] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " SHIFTBUF[1] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " SHIFTBUF[0] ,Shift buffer mask" "Not masked,Masked"
|
|
group.long (0x8+0x280)++0x03
|
|
line.long 0x00 "SHIFTBUFBIS_2,Shifter Buffer 2 Bit Swapped Register"
|
|
group.long (0x8+0x300)++0x03
|
|
line.long 0x00 "SHIFTBUFBYS_2,Shifter Buffer 2 Byte Swapped Register"
|
|
group.long (0x8+0x380)++0x03
|
|
line.long 0x00 "SHIFTBUFBBS_2,Shifter Buffer 2 Bit Byte Swapped Register"
|
|
else
|
|
group.long (0x8+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_2,Shifter Configuration 2 Register"
|
|
bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit shift,4-bit shift,4-bit shift,4-bit shift,8-bit shift,8-bit shift,8-bit shift,8-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift"
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,0 on store,1 on store"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled / load on enable,Disabled / load on first shift,0 before first shift,1 before first shift"
|
|
group.long (0x8+0x200)++0x03
|
|
line.long 0x00 "SHIFTBUF_2,Shifter Buffer 2 Register"
|
|
group.long (0x8+0x280)++0x03
|
|
line.long 0x00 "SHIFTBUFBIS_2,Shifter Buffer 2 Bit Swapped Register"
|
|
group.long (0x8+0x300)++0x03
|
|
line.long 0x00 "SHIFTBUFBYS_2,Shifter Buffer 2 Byte Swapped Register"
|
|
group.long (0x8+0x380)++0x03
|
|
line.long 0x00 "SHIFTBUFBBS_2,Shifter Buffer 2 Bit Byte Swapped Register"
|
|
endif
|
|
group.long (0xC+0x80)++0x03
|
|
line.long 0x00 "SHIFTCTL_3,Shifter Control 3 Register"
|
|
bitfld.long 0x00 24.--26. " TIMSEL ,Selects which timer is used for controlling the logic/shift register and generating the shift clock" "Timer 0,Timer 1,Timer 2,Timer 3,Timer 4,Timer 5,Timer 6,Timer 7"
|
|
bitfld.long 0x00 23. " TIMPOL ,Timer polarity" "Posedge,Negedge"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Shifter pin configuration" "Disabled,Open drain or bidir/Out,Bidir/Out data,Output"
|
|
newline
|
|
bitfld.long 0x00 8.--12. " PINSEL ,Shifter pin select" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7,FXIO0_D8,FXIO0_D9,FXIO0_D10,FXIO0_D11,FXIO0_D12,FXIO0_D13,FXIO0_D14,FXIO0_D15,FXIO0_D16,FXIO0_D17,FXIO0_D18,FXIO0_D19,FXIO0_D20,FXIO0_D21,FXIO0_D22,FXIO0_D23,FXIO0_D24,FXIO0_D25,FXIO0_D26,FXIO0_D27,FXIO0_D28,FXIO0_D29,FXIO0_D30,FXIO0_D31"
|
|
bitfld.long 0x00 7. " PINPOL ,Shifter pin polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0.--2. " SMOD ,Configures the mode of the shifter" "Disabled,Receive mode,Transmit mode,,Match store,Match continuous,State mode,Logic mode"
|
|
newline
|
|
if (((per.l(ad:0x4005F000+0x80+0xC))&0x07)==0x05)
|
|
group.long (0xC+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_3,Shifter Configuration 3 Register"
|
|
bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit shift,4-bit shift,4-bit shift,4-bit shift,8-bit shift,8-bit shift,8-bit shift,8-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift"
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
group.long (0xC+0x200)++0x03
|
|
line.long 0x00 "SHIFTBUF_3,Shifter Buffer 3 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " SHIFTBUF[31:16] ,Shift buffer data to match"
|
|
newline
|
|
bitfld.long 0x00 15. " SHIFTBUF[15] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " SHIFTBUF[14] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 13. " SHIFTBUF[13] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " SHIFTBUF[12] ,Shift buffer mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 11. " SHIFTBUF[11] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " SHIFTBUF[10] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " SHIFTBUF[9] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " SHIFTBUF[8] ,Shift buffer mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 7. " SHIFTBUF[7] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " SHIFTBUF[6] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " SHIFTBUF[5] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " SHIFTBUF[4] ,Shift buffer mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 3. " SHIFTBUF[3] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " SHIFTBUF[2] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " SHIFTBUF[1] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " SHIFTBUF[0] ,Shift buffer mask" "Not masked,Masked"
|
|
group.long (0xC+0x280)++0x03
|
|
line.long 0x00 "SHIFTBUFBIS_3,Shifter Buffer 3 Bit Swapped Register"
|
|
group.long (0xC+0x300)++0x03
|
|
line.long 0x00 "SHIFTBUFBYS_3,Shifter Buffer 3 Byte Swapped Register"
|
|
group.long (0xC+0x380)++0x03
|
|
line.long 0x00 "SHIFTBUFBBS_3,Shifter Buffer 3 Bit Byte Swapped Register"
|
|
else
|
|
group.long (0xC+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_3,Shifter Configuration 3 Register"
|
|
bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit shift,4-bit shift,4-bit shift,4-bit shift,8-bit shift,8-bit shift,8-bit shift,8-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift"
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,0 on store,1 on store"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled / load on enable,Disabled / load on first shift,0 before first shift,1 before first shift"
|
|
group.long (0xC+0x200)++0x03
|
|
line.long 0x00 "SHIFTBUF_3,Shifter Buffer 3 Register"
|
|
group.long (0xC+0x280)++0x03
|
|
line.long 0x00 "SHIFTBUFBIS_3,Shifter Buffer 3 Bit Swapped Register"
|
|
group.long (0xC+0x300)++0x03
|
|
line.long 0x00 "SHIFTBUFBYS_3,Shifter Buffer 3 Byte Swapped Register"
|
|
group.long (0xC+0x380)++0x03
|
|
line.long 0x00 "SHIFTBUFBBS_3,Shifter Buffer 3 Bit Byte Swapped Register"
|
|
endif
|
|
group.long (0x10+0x80)++0x03
|
|
line.long 0x00 "SHIFTCTL_4,Shifter Control 4 Register"
|
|
bitfld.long 0x00 24.--26. " TIMSEL ,Selects which timer is used for controlling the logic/shift register and generating the shift clock" "Timer 0,Timer 1,Timer 2,Timer 3,Timer 4,Timer 5,Timer 6,Timer 7"
|
|
bitfld.long 0x00 23. " TIMPOL ,Timer polarity" "Posedge,Negedge"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Shifter pin configuration" "Disabled,Open drain or bidir/Out,Bidir/Out data,Output"
|
|
newline
|
|
bitfld.long 0x00 8.--12. " PINSEL ,Shifter pin select" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7,FXIO0_D8,FXIO0_D9,FXIO0_D10,FXIO0_D11,FXIO0_D12,FXIO0_D13,FXIO0_D14,FXIO0_D15,FXIO0_D16,FXIO0_D17,FXIO0_D18,FXIO0_D19,FXIO0_D20,FXIO0_D21,FXIO0_D22,FXIO0_D23,FXIO0_D24,FXIO0_D25,FXIO0_D26,FXIO0_D27,FXIO0_D28,FXIO0_D29,FXIO0_D30,FXIO0_D31"
|
|
bitfld.long 0x00 7. " PINPOL ,Shifter pin polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0.--2. " SMOD ,Configures the mode of the shifter" "Disabled,Receive mode,Transmit mode,,Match store,Match continuous,State mode,Logic mode"
|
|
newline
|
|
if (((per.l(ad:0x4005F000+0x80+0x10))&0x07)==0x05)
|
|
group.long (0x10+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_4,Shifter Configuration 4 Register"
|
|
bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit shift,4-bit shift,4-bit shift,4-bit shift,8-bit shift,8-bit shift,8-bit shift,8-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift"
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
group.long (0x10+0x200)++0x03
|
|
line.long 0x00 "SHIFTBUF_4,Shifter Buffer 4 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " SHIFTBUF[31:16] ,Shift buffer data to match"
|
|
newline
|
|
bitfld.long 0x00 15. " SHIFTBUF[15] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " SHIFTBUF[14] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 13. " SHIFTBUF[13] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " SHIFTBUF[12] ,Shift buffer mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 11. " SHIFTBUF[11] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " SHIFTBUF[10] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " SHIFTBUF[9] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " SHIFTBUF[8] ,Shift buffer mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 7. " SHIFTBUF[7] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " SHIFTBUF[6] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " SHIFTBUF[5] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " SHIFTBUF[4] ,Shift buffer mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 3. " SHIFTBUF[3] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " SHIFTBUF[2] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " SHIFTBUF[1] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " SHIFTBUF[0] ,Shift buffer mask" "Not masked,Masked"
|
|
group.long (0x10+0x280)++0x03
|
|
line.long 0x00 "SHIFTBUFBIS_4,Shifter Buffer 4 Bit Swapped Register"
|
|
group.long (0x10+0x300)++0x03
|
|
line.long 0x00 "SHIFTBUFBYS_4,Shifter Buffer 4 Byte Swapped Register"
|
|
group.long (0x10+0x380)++0x03
|
|
line.long 0x00 "SHIFTBUFBBS_4,Shifter Buffer 4 Bit Byte Swapped Register"
|
|
else
|
|
group.long (0x10+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_4,Shifter Configuration 4 Register"
|
|
bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit shift,4-bit shift,4-bit shift,4-bit shift,8-bit shift,8-bit shift,8-bit shift,8-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift"
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,0 on store,1 on store"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled / load on enable,Disabled / load on first shift,0 before first shift,1 before first shift"
|
|
group.long (0x10+0x200)++0x03
|
|
line.long 0x00 "SHIFTBUF_4,Shifter Buffer 4 Register"
|
|
group.long (0x10+0x280)++0x03
|
|
line.long 0x00 "SHIFTBUFBIS_4,Shifter Buffer 4 Bit Swapped Register"
|
|
group.long (0x10+0x300)++0x03
|
|
line.long 0x00 "SHIFTBUFBYS_4,Shifter Buffer 4 Byte Swapped Register"
|
|
group.long (0x10+0x380)++0x03
|
|
line.long 0x00 "SHIFTBUFBBS_4,Shifter Buffer 4 Bit Byte Swapped Register"
|
|
endif
|
|
group.long (0x14+0x80)++0x03
|
|
line.long 0x00 "SHIFTCTL_5,Shifter Control 5 Register"
|
|
bitfld.long 0x00 24.--26. " TIMSEL ,Selects which timer is used for controlling the logic/shift register and generating the shift clock" "Timer 0,Timer 1,Timer 2,Timer 3,Timer 4,Timer 5,Timer 6,Timer 7"
|
|
bitfld.long 0x00 23. " TIMPOL ,Timer polarity" "Posedge,Negedge"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Shifter pin configuration" "Disabled,Open drain or bidir/Out,Bidir/Out data,Output"
|
|
newline
|
|
bitfld.long 0x00 8.--12. " PINSEL ,Shifter pin select" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7,FXIO0_D8,FXIO0_D9,FXIO0_D10,FXIO0_D11,FXIO0_D12,FXIO0_D13,FXIO0_D14,FXIO0_D15,FXIO0_D16,FXIO0_D17,FXIO0_D18,FXIO0_D19,FXIO0_D20,FXIO0_D21,FXIO0_D22,FXIO0_D23,FXIO0_D24,FXIO0_D25,FXIO0_D26,FXIO0_D27,FXIO0_D28,FXIO0_D29,FXIO0_D30,FXIO0_D31"
|
|
bitfld.long 0x00 7. " PINPOL ,Shifter pin polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0.--2. " SMOD ,Configures the mode of the shifter" "Disabled,Receive mode,Transmit mode,,Match store,Match continuous,State mode,Logic mode"
|
|
newline
|
|
if (((per.l(ad:0x4005F000+0x80+0x14))&0x07)==0x05)
|
|
group.long (0x14+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_5,Shifter Configuration 5 Register"
|
|
bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit shift,4-bit shift,4-bit shift,4-bit shift,8-bit shift,8-bit shift,8-bit shift,8-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift"
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
group.long (0x14+0x200)++0x03
|
|
line.long 0x00 "SHIFTBUF_5,Shifter Buffer 5 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " SHIFTBUF[31:16] ,Shift buffer data to match"
|
|
newline
|
|
bitfld.long 0x00 15. " SHIFTBUF[15] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " SHIFTBUF[14] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 13. " SHIFTBUF[13] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " SHIFTBUF[12] ,Shift buffer mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 11. " SHIFTBUF[11] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " SHIFTBUF[10] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " SHIFTBUF[9] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " SHIFTBUF[8] ,Shift buffer mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 7. " SHIFTBUF[7] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " SHIFTBUF[6] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " SHIFTBUF[5] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " SHIFTBUF[4] ,Shift buffer mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 3. " SHIFTBUF[3] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " SHIFTBUF[2] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " SHIFTBUF[1] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " SHIFTBUF[0] ,Shift buffer mask" "Not masked,Masked"
|
|
group.long (0x14+0x280)++0x03
|
|
line.long 0x00 "SHIFTBUFBIS_5,Shifter Buffer 5 Bit Swapped Register"
|
|
group.long (0x14+0x300)++0x03
|
|
line.long 0x00 "SHIFTBUFBYS_5,Shifter Buffer 5 Byte Swapped Register"
|
|
group.long (0x14+0x380)++0x03
|
|
line.long 0x00 "SHIFTBUFBBS_5,Shifter Buffer 5 Bit Byte Swapped Register"
|
|
else
|
|
group.long (0x14+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_5,Shifter Configuration 5 Register"
|
|
bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit shift,4-bit shift,4-bit shift,4-bit shift,8-bit shift,8-bit shift,8-bit shift,8-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift"
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,0 on store,1 on store"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled / load on enable,Disabled / load on first shift,0 before first shift,1 before first shift"
|
|
group.long (0x14+0x200)++0x03
|
|
line.long 0x00 "SHIFTBUF_5,Shifter Buffer 5 Register"
|
|
group.long (0x14+0x280)++0x03
|
|
line.long 0x00 "SHIFTBUFBIS_5,Shifter Buffer 5 Bit Swapped Register"
|
|
group.long (0x14+0x300)++0x03
|
|
line.long 0x00 "SHIFTBUFBYS_5,Shifter Buffer 5 Byte Swapped Register"
|
|
group.long (0x14+0x380)++0x03
|
|
line.long 0x00 "SHIFTBUFBBS_5,Shifter Buffer 5 Bit Byte Swapped Register"
|
|
endif
|
|
group.long (0x18+0x80)++0x03
|
|
line.long 0x00 "SHIFTCTL_6,Shifter Control 6 Register"
|
|
bitfld.long 0x00 24.--26. " TIMSEL ,Selects which timer is used for controlling the logic/shift register and generating the shift clock" "Timer 0,Timer 1,Timer 2,Timer 3,Timer 4,Timer 5,Timer 6,Timer 7"
|
|
bitfld.long 0x00 23. " TIMPOL ,Timer polarity" "Posedge,Negedge"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Shifter pin configuration" "Disabled,Open drain or bidir/Out,Bidir/Out data,Output"
|
|
newline
|
|
bitfld.long 0x00 8.--12. " PINSEL ,Shifter pin select" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7,FXIO0_D8,FXIO0_D9,FXIO0_D10,FXIO0_D11,FXIO0_D12,FXIO0_D13,FXIO0_D14,FXIO0_D15,FXIO0_D16,FXIO0_D17,FXIO0_D18,FXIO0_D19,FXIO0_D20,FXIO0_D21,FXIO0_D22,FXIO0_D23,FXIO0_D24,FXIO0_D25,FXIO0_D26,FXIO0_D27,FXIO0_D28,FXIO0_D29,FXIO0_D30,FXIO0_D31"
|
|
bitfld.long 0x00 7. " PINPOL ,Shifter pin polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0.--2. " SMOD ,Configures the mode of the shifter" "Disabled,Receive mode,Transmit mode,,Match store,Match continuous,State mode,Logic mode"
|
|
newline
|
|
if (((per.l(ad:0x4005F000+0x80+0x18))&0x07)==0x05)
|
|
group.long (0x18+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_6,Shifter Configuration 6 Register"
|
|
bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit shift,4-bit shift,4-bit shift,4-bit shift,8-bit shift,8-bit shift,8-bit shift,8-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift"
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
group.long (0x18+0x200)++0x03
|
|
line.long 0x00 "SHIFTBUF_6,Shifter Buffer 6 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " SHIFTBUF[31:16] ,Shift buffer data to match"
|
|
newline
|
|
bitfld.long 0x00 15. " SHIFTBUF[15] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " SHIFTBUF[14] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 13. " SHIFTBUF[13] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " SHIFTBUF[12] ,Shift buffer mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 11. " SHIFTBUF[11] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " SHIFTBUF[10] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " SHIFTBUF[9] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " SHIFTBUF[8] ,Shift buffer mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 7. " SHIFTBUF[7] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " SHIFTBUF[6] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " SHIFTBUF[5] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " SHIFTBUF[4] ,Shift buffer mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 3. " SHIFTBUF[3] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " SHIFTBUF[2] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " SHIFTBUF[1] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " SHIFTBUF[0] ,Shift buffer mask" "Not masked,Masked"
|
|
group.long (0x18+0x280)++0x03
|
|
line.long 0x00 "SHIFTBUFBIS_6,Shifter Buffer 6 Bit Swapped Register"
|
|
group.long (0x18+0x300)++0x03
|
|
line.long 0x00 "SHIFTBUFBYS_6,Shifter Buffer 6 Byte Swapped Register"
|
|
group.long (0x18+0x380)++0x03
|
|
line.long 0x00 "SHIFTBUFBBS_6,Shifter Buffer 6 Bit Byte Swapped Register"
|
|
else
|
|
group.long (0x18+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_6,Shifter Configuration 6 Register"
|
|
bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit shift,4-bit shift,4-bit shift,4-bit shift,8-bit shift,8-bit shift,8-bit shift,8-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift"
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,0 on store,1 on store"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled / load on enable,Disabled / load on first shift,0 before first shift,1 before first shift"
|
|
group.long (0x18+0x200)++0x03
|
|
line.long 0x00 "SHIFTBUF_6,Shifter Buffer 6 Register"
|
|
group.long (0x18+0x280)++0x03
|
|
line.long 0x00 "SHIFTBUFBIS_6,Shifter Buffer 6 Bit Swapped Register"
|
|
group.long (0x18+0x300)++0x03
|
|
line.long 0x00 "SHIFTBUFBYS_6,Shifter Buffer 6 Byte Swapped Register"
|
|
group.long (0x18+0x380)++0x03
|
|
line.long 0x00 "SHIFTBUFBBS_6,Shifter Buffer 6 Bit Byte Swapped Register"
|
|
endif
|
|
group.long (0x1C+0x80)++0x03
|
|
line.long 0x00 "SHIFTCTL_7,Shifter Control 7 Register"
|
|
bitfld.long 0x00 24.--26. " TIMSEL ,Selects which timer is used for controlling the logic/shift register and generating the shift clock" "Timer 0,Timer 1,Timer 2,Timer 3,Timer 4,Timer 5,Timer 6,Timer 7"
|
|
bitfld.long 0x00 23. " TIMPOL ,Timer polarity" "Posedge,Negedge"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Shifter pin configuration" "Disabled,Open drain or bidir/Out,Bidir/Out data,Output"
|
|
newline
|
|
bitfld.long 0x00 8.--12. " PINSEL ,Shifter pin select" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7,FXIO0_D8,FXIO0_D9,FXIO0_D10,FXIO0_D11,FXIO0_D12,FXIO0_D13,FXIO0_D14,FXIO0_D15,FXIO0_D16,FXIO0_D17,FXIO0_D18,FXIO0_D19,FXIO0_D20,FXIO0_D21,FXIO0_D22,FXIO0_D23,FXIO0_D24,FXIO0_D25,FXIO0_D26,FXIO0_D27,FXIO0_D28,FXIO0_D29,FXIO0_D30,FXIO0_D31"
|
|
bitfld.long 0x00 7. " PINPOL ,Shifter pin polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0.--2. " SMOD ,Configures the mode of the shifter" "Disabled,Receive mode,Transmit mode,,Match store,Match continuous,State mode,Logic mode"
|
|
newline
|
|
if (((per.l(ad:0x4005F000+0x80+0x1C))&0x07)==0x05)
|
|
group.long (0x1C+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_7,Shifter Configuration 7 Register"
|
|
bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit shift,4-bit shift,4-bit shift,4-bit shift,8-bit shift,8-bit shift,8-bit shift,8-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift"
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
group.long (0x1C+0x200)++0x03
|
|
line.long 0x00 "SHIFTBUF_7,Shifter Buffer 7 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " SHIFTBUF[31:16] ,Shift buffer data to match"
|
|
newline
|
|
bitfld.long 0x00 15. " SHIFTBUF[15] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " SHIFTBUF[14] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 13. " SHIFTBUF[13] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " SHIFTBUF[12] ,Shift buffer mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 11. " SHIFTBUF[11] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " SHIFTBUF[10] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " SHIFTBUF[9] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " SHIFTBUF[8] ,Shift buffer mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 7. " SHIFTBUF[7] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " SHIFTBUF[6] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " SHIFTBUF[5] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " SHIFTBUF[4] ,Shift buffer mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 3. " SHIFTBUF[3] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " SHIFTBUF[2] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " SHIFTBUF[1] ,Shift buffer mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " SHIFTBUF[0] ,Shift buffer mask" "Not masked,Masked"
|
|
group.long (0x1C+0x280)++0x03
|
|
line.long 0x00 "SHIFTBUFBIS_7,Shifter Buffer 7 Bit Swapped Register"
|
|
group.long (0x1C+0x300)++0x03
|
|
line.long 0x00 "SHIFTBUFBYS_7,Shifter Buffer 7 Byte Swapped Register"
|
|
group.long (0x1C+0x380)++0x03
|
|
line.long 0x00 "SHIFTBUFBBS_7,Shifter Buffer 7 Bit Byte Swapped Register"
|
|
else
|
|
group.long (0x1C+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_7,Shifter Configuration 7 Register"
|
|
bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit shift,4-bit shift,4-bit shift,4-bit shift,8-bit shift,8-bit shift,8-bit shift,8-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift"
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,0 on store,1 on store"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled / load on enable,Disabled / load on first shift,0 before first shift,1 before first shift"
|
|
group.long (0x1C+0x200)++0x03
|
|
line.long 0x00 "SHIFTBUF_7,Shifter Buffer 7 Register"
|
|
group.long (0x1C+0x280)++0x03
|
|
line.long 0x00 "SHIFTBUFBIS_7,Shifter Buffer 7 Bit Swapped Register"
|
|
group.long (0x1C+0x300)++0x03
|
|
line.long 0x00 "SHIFTBUFBYS_7,Shifter Buffer 7 Byte Swapped Register"
|
|
group.long (0x1C+0x380)++0x03
|
|
line.long 0x00 "SHIFTBUFBBS_7,Shifter Buffer 7 Bit Byte Swapped Register"
|
|
endif
|
|
tree.end
|
|
width 10.
|
|
tree "Timer Registers"
|
|
if (((per.l(ad:0x4005F000+0x400+0x0))&0x400000)==0x400000)
|
|
group.long (0x0+0x400)++0x03
|
|
line.long 0x00 "TIMCTL_0,Timer Control 0 Register"
|
|
bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,CMP_1,,PIT_0,PIT_1,PIT_2,PIT_3,FTM_0,FTM_1,FTM_2,FTM_3,RTC alarm,RTC seconds,LPTMR,?..."
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7"
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit"
|
|
else
|
|
group.long (0x0+0x400)++0x03
|
|
line.long 0x00 "TIMCTL_0,Timer Control 0 Register"
|
|
bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "FXIO0_D0,Shifter 0 status flag,FXIO0_D1,Timer 0 trigger output,FXIO0_D2,Shifter 1 status flag,FXIO0_D3,Timer 1 trigger output,FXIO0_D4,Shifter 2 status flag,FXIO0_D5,Timer 2 trigger output,FXIO0_D6,Shifter 3 status flag,FXIO0_D7,Timer 3 trigger output,FXIO0_D8,Shifter 4 status flag,FXIO0_D9,Timer 4 trigger output,FXIO0_D10,Shifter 5 status flag,FXIO0_D11,Timer 5 trigger output,FXIO0_D12,Shifter 6 status flag,FXIO0_D13,Timer 6 trigger output,FXIO0_D14,Shifter 7 status flag,FXIO0_D15,Timer 7 trigger output,FXIO0_D16,,FXIO0_D17,,FXIO0_D18,,FXIO0_D19,,FXIO0_D20,,FXIO0_D21,,FXIO0_D22,,FXIO0_D23,,FXIO0_D24,,FXIO0_D25,,FXIO0_D26,,FXIO0_D27,,FXIO0_D28,,FXIO0_D29,,FXIO0_D30,,FXIO0_D31,?..."
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7"
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit"
|
|
endif
|
|
group.long (0x0+0x480)++0x03
|
|
line.long 0x00 "TIMCFG_0,Timer Configuration 0 Register"
|
|
bitfld.long 0x00 24.--25. " TIMOUT ,Configures the initial state of the timer output and whether it is affected by the timer reset" "1 not affected,0 not affected,1 on reset,0 on reset"
|
|
bitfld.long 0x00 20.--21. " TIMDEC ,Configures the source of the timer decrement and the source of the shift clock" "Flexio clk / shift clk = timer out,Trigger input / shift clk = timer out,Pin input / shift clk = pin input,Trigger input / shift clk = trigger input"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " TIMRST ,Configures the condition that causes the timer counter (and optionally the timer output) to be reset" "Never,,Pin == timer output,Trigger == timer output,Pin rising,,Trigger rising,Trigger rising or falling"
|
|
bitfld.long 0x00 12.--14. " TIMDIS ,Configures the condition that causes the timer to be disabled and stop decrementing" "Never,Timer N+1 dis.,Timer cmp.,Timer cmp. & trigger low,Pin both edges,Pin both edges & trigger high,Trigger falling,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. " TIMENA ,Configures the condition that causes the timer to be enabled and start decrementing" "Always enabled,Timer N-1 enable,Trigger high,Trigger & pin high,Pin rising,Pin rising & trigger high,Trigger rising,Trigger both edges"
|
|
bitfld.long 0x00 4.--5. " TSTOP ,Timer stop bit" "Disabled,On timer cmp.,On timer disable,On timer cmp. & disable"
|
|
newline
|
|
bitfld.long 0x00 1. " TSTART ,Timer start bit enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x4005F000+0x400+0x0))&0x3)==0x1)
|
|
group.long (0x0+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_0,Timer Compare 0 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the number of bits in each word equal to (CMP[15:8] + 1)/2"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the baud rate divider equal to (CMP[7:0] + 1) * 2"
|
|
elif (((per.l(ad:0x4005F000+0x400+0x0))&0x3)==0x2)
|
|
group.long (0x0+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_0,Timer Compare 0 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the low period of the output to (CMP[15:8] + 1) * 2"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the high period of the output to (CMP[7:0] + 1) * 2"
|
|
elif (((per.l(ad:0x4005F000+0x400+0x0))&0x3)==0x3)
|
|
group.long (0x0+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_0,Timer Compare 0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Baud rate divider (If shift clock source is timer output) to equal (CMP[15:0] + 1)*2 or"
|
|
else
|
|
group.long (0x0+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_0,Timer Compare 0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Timer compare value"
|
|
endif
|
|
if (((per.l(ad:0x4005F000+0x400+0x4))&0x400000)==0x400000)
|
|
group.long (0x4+0x400)++0x03
|
|
line.long 0x00 "TIMCTL_1,Timer Control 1 Register"
|
|
bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,CMP_1,,PIT_0,PIT_1,PIT_2,PIT_3,FTM_0,FTM_1,FTM_2,FTM_3,RTC alarm,RTC seconds,LPTMR,?..."
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7"
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit"
|
|
else
|
|
group.long (0x4+0x400)++0x03
|
|
line.long 0x00 "TIMCTL_1,Timer Control 1 Register"
|
|
bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "FXIO0_D0,Shifter 0 status flag,FXIO0_D1,Timer 0 trigger output,FXIO0_D2,Shifter 1 status flag,FXIO0_D3,Timer 1 trigger output,FXIO0_D4,Shifter 2 status flag,FXIO0_D5,Timer 2 trigger output,FXIO0_D6,Shifter 3 status flag,FXIO0_D7,Timer 3 trigger output,FXIO0_D8,Shifter 4 status flag,FXIO0_D9,Timer 4 trigger output,FXIO0_D10,Shifter 5 status flag,FXIO0_D11,Timer 5 trigger output,FXIO0_D12,Shifter 6 status flag,FXIO0_D13,Timer 6 trigger output,FXIO0_D14,Shifter 7 status flag,FXIO0_D15,Timer 7 trigger output,FXIO0_D16,,FXIO0_D17,,FXIO0_D18,,FXIO0_D19,,FXIO0_D20,,FXIO0_D21,,FXIO0_D22,,FXIO0_D23,,FXIO0_D24,,FXIO0_D25,,FXIO0_D26,,FXIO0_D27,,FXIO0_D28,,FXIO0_D29,,FXIO0_D30,,FXIO0_D31,?..."
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7"
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit"
|
|
endif
|
|
group.long (0x4+0x480)++0x03
|
|
line.long 0x00 "TIMCFG_1,Timer Configuration 1 Register"
|
|
bitfld.long 0x00 24.--25. " TIMOUT ,Configures the initial state of the timer output and whether it is affected by the timer reset" "1 not affected,0 not affected,1 on reset,0 on reset"
|
|
bitfld.long 0x00 20.--21. " TIMDEC ,Configures the source of the timer decrement and the source of the shift clock" "Flexio clk / shift clk = timer out,Trigger input / shift clk = timer out,Pin input / shift clk = pin input,Trigger input / shift clk = trigger input"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " TIMRST ,Configures the condition that causes the timer counter (and optionally the timer output) to be reset" "Never,,Pin == timer output,Trigger == timer output,Pin rising,,Trigger rising,Trigger rising or falling"
|
|
bitfld.long 0x00 12.--14. " TIMDIS ,Configures the condition that causes the timer to be disabled and stop decrementing" "Never,Timer N+1 dis.,Timer cmp.,Timer cmp. & trigger low,Pin both edges,Pin both edges & trigger high,Trigger falling,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. " TIMENA ,Configures the condition that causes the timer to be enabled and start decrementing" "Always enabled,Timer N-1 enable,Trigger high,Trigger & pin high,Pin rising,Pin rising & trigger high,Trigger rising,Trigger both edges"
|
|
bitfld.long 0x00 4.--5. " TSTOP ,Timer stop bit" "Disabled,On timer cmp.,On timer disable,On timer cmp. & disable"
|
|
newline
|
|
bitfld.long 0x00 1. " TSTART ,Timer start bit enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x4005F000+0x400+0x4))&0x3)==0x1)
|
|
group.long (0x4+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_1,Timer Compare 1 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the number of bits in each word equal to (CMP[15:8] + 1)/2"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the baud rate divider equal to (CMP[7:0] + 1) * 2"
|
|
elif (((per.l(ad:0x4005F000+0x400+0x4))&0x3)==0x2)
|
|
group.long (0x4+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_1,Timer Compare 1 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the low period of the output to (CMP[15:8] + 1) * 2"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the high period of the output to (CMP[7:0] + 1) * 2"
|
|
elif (((per.l(ad:0x4005F000+0x400+0x4))&0x3)==0x3)
|
|
group.long (0x4+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_1,Timer Compare 1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Baud rate divider (If shift clock source is timer output) to equal (CMP[15:0] + 1)*2 or"
|
|
else
|
|
group.long (0x4+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_1,Timer Compare 1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Timer compare value"
|
|
endif
|
|
if (((per.l(ad:0x4005F000+0x400+0x8))&0x400000)==0x400000)
|
|
group.long (0x8+0x400)++0x03
|
|
line.long 0x00 "TIMCTL_2,Timer Control 2 Register"
|
|
bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,CMP_1,,PIT_0,PIT_1,PIT_2,PIT_3,FTM_0,FTM_1,FTM_2,FTM_3,RTC alarm,RTC seconds,LPTMR,?..."
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7"
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit"
|
|
else
|
|
group.long (0x8+0x400)++0x03
|
|
line.long 0x00 "TIMCTL_2,Timer Control 2 Register"
|
|
bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "FXIO0_D0,Shifter 0 status flag,FXIO0_D1,Timer 0 trigger output,FXIO0_D2,Shifter 1 status flag,FXIO0_D3,Timer 1 trigger output,FXIO0_D4,Shifter 2 status flag,FXIO0_D5,Timer 2 trigger output,FXIO0_D6,Shifter 3 status flag,FXIO0_D7,Timer 3 trigger output,FXIO0_D8,Shifter 4 status flag,FXIO0_D9,Timer 4 trigger output,FXIO0_D10,Shifter 5 status flag,FXIO0_D11,Timer 5 trigger output,FXIO0_D12,Shifter 6 status flag,FXIO0_D13,Timer 6 trigger output,FXIO0_D14,Shifter 7 status flag,FXIO0_D15,Timer 7 trigger output,FXIO0_D16,,FXIO0_D17,,FXIO0_D18,,FXIO0_D19,,FXIO0_D20,,FXIO0_D21,,FXIO0_D22,,FXIO0_D23,,FXIO0_D24,,FXIO0_D25,,FXIO0_D26,,FXIO0_D27,,FXIO0_D28,,FXIO0_D29,,FXIO0_D30,,FXIO0_D31,?..."
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7"
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit"
|
|
endif
|
|
group.long (0x8+0x480)++0x03
|
|
line.long 0x00 "TIMCFG_2,Timer Configuration 2 Register"
|
|
bitfld.long 0x00 24.--25. " TIMOUT ,Configures the initial state of the timer output and whether it is affected by the timer reset" "1 not affected,0 not affected,1 on reset,0 on reset"
|
|
bitfld.long 0x00 20.--21. " TIMDEC ,Configures the source of the timer decrement and the source of the shift clock" "Flexio clk / shift clk = timer out,Trigger input / shift clk = timer out,Pin input / shift clk = pin input,Trigger input / shift clk = trigger input"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " TIMRST ,Configures the condition that causes the timer counter (and optionally the timer output) to be reset" "Never,,Pin == timer output,Trigger == timer output,Pin rising,,Trigger rising,Trigger rising or falling"
|
|
bitfld.long 0x00 12.--14. " TIMDIS ,Configures the condition that causes the timer to be disabled and stop decrementing" "Never,Timer N+1 dis.,Timer cmp.,Timer cmp. & trigger low,Pin both edges,Pin both edges & trigger high,Trigger falling,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. " TIMENA ,Configures the condition that causes the timer to be enabled and start decrementing" "Always enabled,Timer N-1 enable,Trigger high,Trigger & pin high,Pin rising,Pin rising & trigger high,Trigger rising,Trigger both edges"
|
|
bitfld.long 0x00 4.--5. " TSTOP ,Timer stop bit" "Disabled,On timer cmp.,On timer disable,On timer cmp. & disable"
|
|
newline
|
|
bitfld.long 0x00 1. " TSTART ,Timer start bit enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x4005F000+0x400+0x8))&0x3)==0x1)
|
|
group.long (0x8+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_2,Timer Compare 2 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the number of bits in each word equal to (CMP[15:8] + 1)/2"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the baud rate divider equal to (CMP[7:0] + 1) * 2"
|
|
elif (((per.l(ad:0x4005F000+0x400+0x8))&0x3)==0x2)
|
|
group.long (0x8+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_2,Timer Compare 2 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the low period of the output to (CMP[15:8] + 1) * 2"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the high period of the output to (CMP[7:0] + 1) * 2"
|
|
elif (((per.l(ad:0x4005F000+0x400+0x8))&0x3)==0x3)
|
|
group.long (0x8+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_2,Timer Compare 2 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Baud rate divider (If shift clock source is timer output) to equal (CMP[15:0] + 1)*2 or"
|
|
else
|
|
group.long (0x8+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_2,Timer Compare 2 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Timer compare value"
|
|
endif
|
|
if (((per.l(ad:0x4005F000+0x400+0xC))&0x400000)==0x400000)
|
|
group.long (0xC+0x400)++0x03
|
|
line.long 0x00 "TIMCTL_3,Timer Control 3 Register"
|
|
bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,CMP_1,,PIT_0,PIT_1,PIT_2,PIT_3,FTM_0,FTM_1,FTM_2,FTM_3,RTC alarm,RTC seconds,LPTMR,?..."
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7"
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit"
|
|
else
|
|
group.long (0xC+0x400)++0x03
|
|
line.long 0x00 "TIMCTL_3,Timer Control 3 Register"
|
|
bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "FXIO0_D0,Shifter 0 status flag,FXIO0_D1,Timer 0 trigger output,FXIO0_D2,Shifter 1 status flag,FXIO0_D3,Timer 1 trigger output,FXIO0_D4,Shifter 2 status flag,FXIO0_D5,Timer 2 trigger output,FXIO0_D6,Shifter 3 status flag,FXIO0_D7,Timer 3 trigger output,FXIO0_D8,Shifter 4 status flag,FXIO0_D9,Timer 4 trigger output,FXIO0_D10,Shifter 5 status flag,FXIO0_D11,Timer 5 trigger output,FXIO0_D12,Shifter 6 status flag,FXIO0_D13,Timer 6 trigger output,FXIO0_D14,Shifter 7 status flag,FXIO0_D15,Timer 7 trigger output,FXIO0_D16,,FXIO0_D17,,FXIO0_D18,,FXIO0_D19,,FXIO0_D20,,FXIO0_D21,,FXIO0_D22,,FXIO0_D23,,FXIO0_D24,,FXIO0_D25,,FXIO0_D26,,FXIO0_D27,,FXIO0_D28,,FXIO0_D29,,FXIO0_D30,,FXIO0_D31,?..."
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7"
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit"
|
|
endif
|
|
group.long (0xC+0x480)++0x03
|
|
line.long 0x00 "TIMCFG_3,Timer Configuration 3 Register"
|
|
bitfld.long 0x00 24.--25. " TIMOUT ,Configures the initial state of the timer output and whether it is affected by the timer reset" "1 not affected,0 not affected,1 on reset,0 on reset"
|
|
bitfld.long 0x00 20.--21. " TIMDEC ,Configures the source of the timer decrement and the source of the shift clock" "Flexio clk / shift clk = timer out,Trigger input / shift clk = timer out,Pin input / shift clk = pin input,Trigger input / shift clk = trigger input"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " TIMRST ,Configures the condition that causes the timer counter (and optionally the timer output) to be reset" "Never,,Pin == timer output,Trigger == timer output,Pin rising,,Trigger rising,Trigger rising or falling"
|
|
bitfld.long 0x00 12.--14. " TIMDIS ,Configures the condition that causes the timer to be disabled and stop decrementing" "Never,Timer N+1 dis.,Timer cmp.,Timer cmp. & trigger low,Pin both edges,Pin both edges & trigger high,Trigger falling,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. " TIMENA ,Configures the condition that causes the timer to be enabled and start decrementing" "Always enabled,Timer N-1 enable,Trigger high,Trigger & pin high,Pin rising,Pin rising & trigger high,Trigger rising,Trigger both edges"
|
|
bitfld.long 0x00 4.--5. " TSTOP ,Timer stop bit" "Disabled,On timer cmp.,On timer disable,On timer cmp. & disable"
|
|
newline
|
|
bitfld.long 0x00 1. " TSTART ,Timer start bit enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x4005F000+0x400+0xC))&0x3)==0x1)
|
|
group.long (0xC+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_3,Timer Compare 3 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the number of bits in each word equal to (CMP[15:8] + 1)/2"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the baud rate divider equal to (CMP[7:0] + 1) * 2"
|
|
elif (((per.l(ad:0x4005F000+0x400+0xC))&0x3)==0x2)
|
|
group.long (0xC+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_3,Timer Compare 3 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the low period of the output to (CMP[15:8] + 1) * 2"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the high period of the output to (CMP[7:0] + 1) * 2"
|
|
elif (((per.l(ad:0x4005F000+0x400+0xC))&0x3)==0x3)
|
|
group.long (0xC+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_3,Timer Compare 3 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Baud rate divider (If shift clock source is timer output) to equal (CMP[15:0] + 1)*2 or"
|
|
else
|
|
group.long (0xC+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_3,Timer Compare 3 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Timer compare value"
|
|
endif
|
|
if (((per.l(ad:0x4005F000+0x400+0x10))&0x400000)==0x400000)
|
|
group.long (0x10+0x400)++0x03
|
|
line.long 0x00 "TIMCTL_4,Timer Control 4 Register"
|
|
bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,CMP_1,,PIT_0,PIT_1,PIT_2,PIT_3,FTM_0,FTM_1,FTM_2,FTM_3,RTC alarm,RTC seconds,LPTMR,?..."
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7"
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit"
|
|
else
|
|
group.long (0x10+0x400)++0x03
|
|
line.long 0x00 "TIMCTL_4,Timer Control 4 Register"
|
|
bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "FXIO0_D0,Shifter 0 status flag,FXIO0_D1,Timer 0 trigger output,FXIO0_D2,Shifter 1 status flag,FXIO0_D3,Timer 1 trigger output,FXIO0_D4,Shifter 2 status flag,FXIO0_D5,Timer 2 trigger output,FXIO0_D6,Shifter 3 status flag,FXIO0_D7,Timer 3 trigger output,FXIO0_D8,Shifter 4 status flag,FXIO0_D9,Timer 4 trigger output,FXIO0_D10,Shifter 5 status flag,FXIO0_D11,Timer 5 trigger output,FXIO0_D12,Shifter 6 status flag,FXIO0_D13,Timer 6 trigger output,FXIO0_D14,Shifter 7 status flag,FXIO0_D15,Timer 7 trigger output,FXIO0_D16,,FXIO0_D17,,FXIO0_D18,,FXIO0_D19,,FXIO0_D20,,FXIO0_D21,,FXIO0_D22,,FXIO0_D23,,FXIO0_D24,,FXIO0_D25,,FXIO0_D26,,FXIO0_D27,,FXIO0_D28,,FXIO0_D29,,FXIO0_D30,,FXIO0_D31,?..."
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7"
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit"
|
|
endif
|
|
group.long (0x10+0x480)++0x03
|
|
line.long 0x00 "TIMCFG_4,Timer Configuration 4 Register"
|
|
bitfld.long 0x00 24.--25. " TIMOUT ,Configures the initial state of the timer output and whether it is affected by the timer reset" "1 not affected,0 not affected,1 on reset,0 on reset"
|
|
bitfld.long 0x00 20.--21. " TIMDEC ,Configures the source of the timer decrement and the source of the shift clock" "Flexio clk / shift clk = timer out,Trigger input / shift clk = timer out,Pin input / shift clk = pin input,Trigger input / shift clk = trigger input"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " TIMRST ,Configures the condition that causes the timer counter (and optionally the timer output) to be reset" "Never,,Pin == timer output,Trigger == timer output,Pin rising,,Trigger rising,Trigger rising or falling"
|
|
bitfld.long 0x00 12.--14. " TIMDIS ,Configures the condition that causes the timer to be disabled and stop decrementing" "Never,Timer N+1 dis.,Timer cmp.,Timer cmp. & trigger low,Pin both edges,Pin both edges & trigger high,Trigger falling,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. " TIMENA ,Configures the condition that causes the timer to be enabled and start decrementing" "Always enabled,Timer N-1 enable,Trigger high,Trigger & pin high,Pin rising,Pin rising & trigger high,Trigger rising,Trigger both edges"
|
|
bitfld.long 0x00 4.--5. " TSTOP ,Timer stop bit" "Disabled,On timer cmp.,On timer disable,On timer cmp. & disable"
|
|
newline
|
|
bitfld.long 0x00 1. " TSTART ,Timer start bit enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x4005F000+0x400+0x10))&0x3)==0x1)
|
|
group.long (0x10+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_4,Timer Compare 4 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the number of bits in each word equal to (CMP[15:8] + 1)/2"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the baud rate divider equal to (CMP[7:0] + 1) * 2"
|
|
elif (((per.l(ad:0x4005F000+0x400+0x10))&0x3)==0x2)
|
|
group.long (0x10+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_4,Timer Compare 4 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the low period of the output to (CMP[15:8] + 1) * 2"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the high period of the output to (CMP[7:0] + 1) * 2"
|
|
elif (((per.l(ad:0x4005F000+0x400+0x10))&0x3)==0x3)
|
|
group.long (0x10+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_4,Timer Compare 4 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Baud rate divider (If shift clock source is timer output) to equal (CMP[15:0] + 1)*2 or"
|
|
else
|
|
group.long (0x10+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_4,Timer Compare 4 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Timer compare value"
|
|
endif
|
|
if (((per.l(ad:0x4005F000+0x400+0x14))&0x400000)==0x400000)
|
|
group.long (0x14+0x400)++0x03
|
|
line.long 0x00 "TIMCTL_5,Timer Control 5 Register"
|
|
bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,CMP_1,,PIT_0,PIT_1,PIT_2,PIT_3,FTM_0,FTM_1,FTM_2,FTM_3,RTC alarm,RTC seconds,LPTMR,?..."
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7"
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit"
|
|
else
|
|
group.long (0x14+0x400)++0x03
|
|
line.long 0x00 "TIMCTL_5,Timer Control 5 Register"
|
|
bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "FXIO0_D0,Shifter 0 status flag,FXIO0_D1,Timer 0 trigger output,FXIO0_D2,Shifter 1 status flag,FXIO0_D3,Timer 1 trigger output,FXIO0_D4,Shifter 2 status flag,FXIO0_D5,Timer 2 trigger output,FXIO0_D6,Shifter 3 status flag,FXIO0_D7,Timer 3 trigger output,FXIO0_D8,Shifter 4 status flag,FXIO0_D9,Timer 4 trigger output,FXIO0_D10,Shifter 5 status flag,FXIO0_D11,Timer 5 trigger output,FXIO0_D12,Shifter 6 status flag,FXIO0_D13,Timer 6 trigger output,FXIO0_D14,Shifter 7 status flag,FXIO0_D15,Timer 7 trigger output,FXIO0_D16,,FXIO0_D17,,FXIO0_D18,,FXIO0_D19,,FXIO0_D20,,FXIO0_D21,,FXIO0_D22,,FXIO0_D23,,FXIO0_D24,,FXIO0_D25,,FXIO0_D26,,FXIO0_D27,,FXIO0_D28,,FXIO0_D29,,FXIO0_D30,,FXIO0_D31,?..."
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7"
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit"
|
|
endif
|
|
group.long (0x14+0x480)++0x03
|
|
line.long 0x00 "TIMCFG_5,Timer Configuration 5 Register"
|
|
bitfld.long 0x00 24.--25. " TIMOUT ,Configures the initial state of the timer output and whether it is affected by the timer reset" "1 not affected,0 not affected,1 on reset,0 on reset"
|
|
bitfld.long 0x00 20.--21. " TIMDEC ,Configures the source of the timer decrement and the source of the shift clock" "Flexio clk / shift clk = timer out,Trigger input / shift clk = timer out,Pin input / shift clk = pin input,Trigger input / shift clk = trigger input"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " TIMRST ,Configures the condition that causes the timer counter (and optionally the timer output) to be reset" "Never,,Pin == timer output,Trigger == timer output,Pin rising,,Trigger rising,Trigger rising or falling"
|
|
bitfld.long 0x00 12.--14. " TIMDIS ,Configures the condition that causes the timer to be disabled and stop decrementing" "Never,Timer N+1 dis.,Timer cmp.,Timer cmp. & trigger low,Pin both edges,Pin both edges & trigger high,Trigger falling,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. " TIMENA ,Configures the condition that causes the timer to be enabled and start decrementing" "Always enabled,Timer N-1 enable,Trigger high,Trigger & pin high,Pin rising,Pin rising & trigger high,Trigger rising,Trigger both edges"
|
|
bitfld.long 0x00 4.--5. " TSTOP ,Timer stop bit" "Disabled,On timer cmp.,On timer disable,On timer cmp. & disable"
|
|
newline
|
|
bitfld.long 0x00 1. " TSTART ,Timer start bit enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x4005F000+0x400+0x14))&0x3)==0x1)
|
|
group.long (0x14+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_5,Timer Compare 5 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the number of bits in each word equal to (CMP[15:8] + 1)/2"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the baud rate divider equal to (CMP[7:0] + 1) * 2"
|
|
elif (((per.l(ad:0x4005F000+0x400+0x14))&0x3)==0x2)
|
|
group.long (0x14+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_5,Timer Compare 5 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the low period of the output to (CMP[15:8] + 1) * 2"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the high period of the output to (CMP[7:0] + 1) * 2"
|
|
elif (((per.l(ad:0x4005F000+0x400+0x14))&0x3)==0x3)
|
|
group.long (0x14+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_5,Timer Compare 5 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Baud rate divider (If shift clock source is timer output) to equal (CMP[15:0] + 1)*2 or"
|
|
else
|
|
group.long (0x14+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_5,Timer Compare 5 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Timer compare value"
|
|
endif
|
|
if (((per.l(ad:0x4005F000+0x400+0x18))&0x400000)==0x400000)
|
|
group.long (0x18+0x400)++0x03
|
|
line.long 0x00 "TIMCTL_6,Timer Control 6 Register"
|
|
bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,CMP_1,,PIT_0,PIT_1,PIT_2,PIT_3,FTM_0,FTM_1,FTM_2,FTM_3,RTC alarm,RTC seconds,LPTMR,?..."
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7"
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit"
|
|
else
|
|
group.long (0x18+0x400)++0x03
|
|
line.long 0x00 "TIMCTL_6,Timer Control 6 Register"
|
|
bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "FXIO0_D0,Shifter 0 status flag,FXIO0_D1,Timer 0 trigger output,FXIO0_D2,Shifter 1 status flag,FXIO0_D3,Timer 1 trigger output,FXIO0_D4,Shifter 2 status flag,FXIO0_D5,Timer 2 trigger output,FXIO0_D6,Shifter 3 status flag,FXIO0_D7,Timer 3 trigger output,FXIO0_D8,Shifter 4 status flag,FXIO0_D9,Timer 4 trigger output,FXIO0_D10,Shifter 5 status flag,FXIO0_D11,Timer 5 trigger output,FXIO0_D12,Shifter 6 status flag,FXIO0_D13,Timer 6 trigger output,FXIO0_D14,Shifter 7 status flag,FXIO0_D15,Timer 7 trigger output,FXIO0_D16,,FXIO0_D17,,FXIO0_D18,,FXIO0_D19,,FXIO0_D20,,FXIO0_D21,,FXIO0_D22,,FXIO0_D23,,FXIO0_D24,,FXIO0_D25,,FXIO0_D26,,FXIO0_D27,,FXIO0_D28,,FXIO0_D29,,FXIO0_D30,,FXIO0_D31,?..."
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7"
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit"
|
|
endif
|
|
group.long (0x18+0x480)++0x03
|
|
line.long 0x00 "TIMCFG_6,Timer Configuration 6 Register"
|
|
bitfld.long 0x00 24.--25. " TIMOUT ,Configures the initial state of the timer output and whether it is affected by the timer reset" "1 not affected,0 not affected,1 on reset,0 on reset"
|
|
bitfld.long 0x00 20.--21. " TIMDEC ,Configures the source of the timer decrement and the source of the shift clock" "Flexio clk / shift clk = timer out,Trigger input / shift clk = timer out,Pin input / shift clk = pin input,Trigger input / shift clk = trigger input"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " TIMRST ,Configures the condition that causes the timer counter (and optionally the timer output) to be reset" "Never,,Pin == timer output,Trigger == timer output,Pin rising,,Trigger rising,Trigger rising or falling"
|
|
bitfld.long 0x00 12.--14. " TIMDIS ,Configures the condition that causes the timer to be disabled and stop decrementing" "Never,Timer N+1 dis.,Timer cmp.,Timer cmp. & trigger low,Pin both edges,Pin both edges & trigger high,Trigger falling,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. " TIMENA ,Configures the condition that causes the timer to be enabled and start decrementing" "Always enabled,Timer N-1 enable,Trigger high,Trigger & pin high,Pin rising,Pin rising & trigger high,Trigger rising,Trigger both edges"
|
|
bitfld.long 0x00 4.--5. " TSTOP ,Timer stop bit" "Disabled,On timer cmp.,On timer disable,On timer cmp. & disable"
|
|
newline
|
|
bitfld.long 0x00 1. " TSTART ,Timer start bit enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x4005F000+0x400+0x18))&0x3)==0x1)
|
|
group.long (0x18+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_6,Timer Compare 6 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the number of bits in each word equal to (CMP[15:8] + 1)/2"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the baud rate divider equal to (CMP[7:0] + 1) * 2"
|
|
elif (((per.l(ad:0x4005F000+0x400+0x18))&0x3)==0x2)
|
|
group.long (0x18+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_6,Timer Compare 6 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the low period of the output to (CMP[15:8] + 1) * 2"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the high period of the output to (CMP[7:0] + 1) * 2"
|
|
elif (((per.l(ad:0x4005F000+0x400+0x18))&0x3)==0x3)
|
|
group.long (0x18+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_6,Timer Compare 6 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Baud rate divider (If shift clock source is timer output) to equal (CMP[15:0] + 1)*2 or"
|
|
else
|
|
group.long (0x18+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_6,Timer Compare 6 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Timer compare value"
|
|
endif
|
|
if (((per.l(ad:0x4005F000+0x400+0x1C))&0x400000)==0x400000)
|
|
group.long (0x1C+0x400)++0x03
|
|
line.long 0x00 "TIMCTL_7,Timer Control 7 Register"
|
|
bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,CMP_1,,PIT_0,PIT_1,PIT_2,PIT_3,FTM_0,FTM_1,FTM_2,FTM_3,RTC alarm,RTC seconds,LPTMR,?..."
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7"
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit"
|
|
else
|
|
group.long (0x1C+0x400)++0x03
|
|
line.long 0x00 "TIMCTL_7,Timer Control 7 Register"
|
|
bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "FXIO0_D0,Shifter 0 status flag,FXIO0_D1,Timer 0 trigger output,FXIO0_D2,Shifter 1 status flag,FXIO0_D3,Timer 1 trigger output,FXIO0_D4,Shifter 2 status flag,FXIO0_D5,Timer 2 trigger output,FXIO0_D6,Shifter 3 status flag,FXIO0_D7,Timer 3 trigger output,FXIO0_D8,Shifter 4 status flag,FXIO0_D9,Timer 4 trigger output,FXIO0_D10,Shifter 5 status flag,FXIO0_D11,Timer 5 trigger output,FXIO0_D12,Shifter 6 status flag,FXIO0_D13,Timer 6 trigger output,FXIO0_D14,Shifter 7 status flag,FXIO0_D15,Timer 7 trigger output,FXIO0_D16,,FXIO0_D17,,FXIO0_D18,,FXIO0_D19,,FXIO0_D20,,FXIO0_D21,,FXIO0_D22,,FXIO0_D23,,FXIO0_D24,,FXIO0_D25,,FXIO0_D26,,FXIO0_D27,,FXIO0_D28,,FXIO0_D29,,FXIO0_D30,,FXIO0_D31,?..."
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7"
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit"
|
|
endif
|
|
group.long (0x1C+0x480)++0x03
|
|
line.long 0x00 "TIMCFG_7,Timer Configuration 7 Register"
|
|
bitfld.long 0x00 24.--25. " TIMOUT ,Configures the initial state of the timer output and whether it is affected by the timer reset" "1 not affected,0 not affected,1 on reset,0 on reset"
|
|
bitfld.long 0x00 20.--21. " TIMDEC ,Configures the source of the timer decrement and the source of the shift clock" "Flexio clk / shift clk = timer out,Trigger input / shift clk = timer out,Pin input / shift clk = pin input,Trigger input / shift clk = trigger input"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " TIMRST ,Configures the condition that causes the timer counter (and optionally the timer output) to be reset" "Never,,Pin == timer output,Trigger == timer output,Pin rising,,Trigger rising,Trigger rising or falling"
|
|
bitfld.long 0x00 12.--14. " TIMDIS ,Configures the condition that causes the timer to be disabled and stop decrementing" "Never,Timer N+1 dis.,Timer cmp.,Timer cmp. & trigger low,Pin both edges,Pin both edges & trigger high,Trigger falling,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. " TIMENA ,Configures the condition that causes the timer to be enabled and start decrementing" "Always enabled,Timer N-1 enable,Trigger high,Trigger & pin high,Pin rising,Pin rising & trigger high,Trigger rising,Trigger both edges"
|
|
bitfld.long 0x00 4.--5. " TSTOP ,Timer stop bit" "Disabled,On timer cmp.,On timer disable,On timer cmp. & disable"
|
|
newline
|
|
bitfld.long 0x00 1. " TSTART ,Timer start bit enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x4005F000+0x400+0x1C))&0x3)==0x1)
|
|
group.long (0x1C+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_7,Timer Compare 7 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the number of bits in each word equal to (CMP[15:8] + 1)/2"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the baud rate divider equal to (CMP[7:0] + 1) * 2"
|
|
elif (((per.l(ad:0x4005F000+0x400+0x1C))&0x3)==0x2)
|
|
group.long (0x1C+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_7,Timer Compare 7 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the low period of the output to (CMP[15:8] + 1) * 2"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the high period of the output to (CMP[7:0] + 1) * 2"
|
|
elif (((per.l(ad:0x4005F000+0x400+0x1C))&0x3)==0x3)
|
|
group.long (0x1C+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_7,Timer Compare 7 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Baud rate divider (If shift clock source is timer output) to equal (CMP[15:0] + 1)*2 or"
|
|
else
|
|
group.long (0x1C+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_7,Timer Compare 7 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Timer compare value"
|
|
endif
|
|
tree.end
|
|
width 15.
|
|
tree "Shifter Buffers"
|
|
group.long (0x0+0x680)++0x03
|
|
line.long 0x00 "SHIFTBUFNBS_0,Shifter Buffer 0 Nibble Byte Swapped Register"
|
|
group.long (0x0+0x700)++0x03
|
|
line.long 0x00 "SHIFTBUFHWS_0,Shifter Buffer 0 Half Word Swapped Register"
|
|
group.long (0x0+0x780)++0x03
|
|
line.long 0x00 "SHIFTBUFNIS_0,Shifter Buffer 0 Nibble Swapped Register"
|
|
group.long (0x4+0x680)++0x03
|
|
line.long 0x00 "SHIFTBUFNBS_1,Shifter Buffer 1 Nibble Byte Swapped Register"
|
|
group.long (0x4+0x700)++0x03
|
|
line.long 0x00 "SHIFTBUFHWS_1,Shifter Buffer 1 Half Word Swapped Register"
|
|
group.long (0x4+0x780)++0x03
|
|
line.long 0x00 "SHIFTBUFNIS_1,Shifter Buffer 1 Nibble Swapped Register"
|
|
group.long (0x8+0x680)++0x03
|
|
line.long 0x00 "SHIFTBUFNBS_2,Shifter Buffer 2 Nibble Byte Swapped Register"
|
|
group.long (0x8+0x700)++0x03
|
|
line.long 0x00 "SHIFTBUFHWS_2,Shifter Buffer 2 Half Word Swapped Register"
|
|
group.long (0x8+0x780)++0x03
|
|
line.long 0x00 "SHIFTBUFNIS_2,Shifter Buffer 2 Nibble Swapped Register"
|
|
group.long (0xC+0x680)++0x03
|
|
line.long 0x00 "SHIFTBUFNBS_3,Shifter Buffer 3 Nibble Byte Swapped Register"
|
|
group.long (0xC+0x700)++0x03
|
|
line.long 0x00 "SHIFTBUFHWS_3,Shifter Buffer 3 Half Word Swapped Register"
|
|
group.long (0xC+0x780)++0x03
|
|
line.long 0x00 "SHIFTBUFNIS_3,Shifter Buffer 3 Nibble Swapped Register"
|
|
group.long (0x10+0x680)++0x03
|
|
line.long 0x00 "SHIFTBUFNBS_4,Shifter Buffer 4 Nibble Byte Swapped Register"
|
|
group.long (0x10+0x700)++0x03
|
|
line.long 0x00 "SHIFTBUFHWS_4,Shifter Buffer 4 Half Word Swapped Register"
|
|
group.long (0x10+0x780)++0x03
|
|
line.long 0x00 "SHIFTBUFNIS_4,Shifter Buffer 4 Nibble Swapped Register"
|
|
group.long (0x14+0x680)++0x03
|
|
line.long 0x00 "SHIFTBUFNBS_5,Shifter Buffer 5 Nibble Byte Swapped Register"
|
|
group.long (0x14+0x700)++0x03
|
|
line.long 0x00 "SHIFTBUFHWS_5,Shifter Buffer 5 Half Word Swapped Register"
|
|
group.long (0x14+0x780)++0x03
|
|
line.long 0x00 "SHIFTBUFNIS_5,Shifter Buffer 5 Nibble Swapped Register"
|
|
group.long (0x18+0x680)++0x03
|
|
line.long 0x00 "SHIFTBUFNBS_6,Shifter Buffer 6 Nibble Byte Swapped Register"
|
|
group.long (0x18+0x700)++0x03
|
|
line.long 0x00 "SHIFTBUFHWS_6,Shifter Buffer 6 Half Word Swapped Register"
|
|
group.long (0x18+0x780)++0x03
|
|
line.long 0x00 "SHIFTBUFNIS_6,Shifter Buffer 6 Nibble Swapped Register"
|
|
group.long (0x1C+0x680)++0x03
|
|
line.long 0x00 "SHIFTBUFNBS_7,Shifter Buffer 7 Nibble Byte Swapped Register"
|
|
group.long (0x1C+0x700)++0x03
|
|
line.long 0x00 "SHIFTBUFHWS_7,Shifter Buffer 7 Half Word Swapped Register"
|
|
group.long (0x1C+0x780)++0x03
|
|
line.long 0x00 "SHIFTBUFNIS_7,Shifter Buffer 7 Nibble Swapped Register"
|
|
tree.end
|
|
else
|
|
width 15.
|
|
tree "Shifter 0"
|
|
group.long (0x0+0x80)++0x03
|
|
line.long 0x00 "SHIFTCTL_0,Shifter Control 0 Register"
|
|
bitfld.long 0x00 24.--25. " TIMSEL ,Selects which timer is used for controlling the logic/shift register and generating the shift clock" "Timer 0,Timer 1,Timer 2,Timer 3"
|
|
bitfld.long 0x00 23. " TIMPOL ,Timer polarity" "Pos. edge,Neg. edge"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Shifter pin configuration" "Disabled,Open drain or bidir/Out,Bidir/Out data,Output"
|
|
newline
|
|
sif cpuis("IMXRT1021")
|
|
bitfld.long 0x00 8.--12. " PINSEL ,Shifter pin select" "FXIO_D0,FXIO_D1,FXIO_D2,FXIO_D3,FXIO_D4,FXIO_D5,FXIO_D6,FXIO_D7,FXIO_D8,FXIO_D9,FXIO_D10,FXIO_D11,FXIO_D12,FXIO_D13,FXIO_D14,FXIO_D15,FXIO_D16,FXIO_D17,FXIO_D18,FXIO_D19,FXIO_D20,FXIO_D21,FXIO_D22,FXIO_D23,FXIO_D24,FXIO_D25,FXIO_D26,FXIO_D27,FXIO_D28,FXIO_D29,FXIO_D30,FXIO_D31"
|
|
else
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Shifter pin select" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7"
|
|
endif
|
|
bitfld.long 0x00 7. " PINPOL ,Shifter pin polarity" "Active high,Active low"
|
|
sif cpuis("IMXRT1021")
|
|
bitfld.long 0x00 0.--2. " SMOD ,Configures the mode of the shifter" "Disabled,Receive,Transmit,,Match store,Match continuous,State,Logic"
|
|
else
|
|
bitfld.long 0x00 0.--2. " SMOD ,Configures the mode of the shifter" "Disabled,Receive mode,Transmit mode,,Match store,Match continuous,?..."
|
|
endif
|
|
newline
|
|
sif cpuis("IMXRT1021")
|
|
if ((((per.l(ad:0x4005F000+0x80+0x0))&0x07)==0x05)||(((per.l(ad:0x4005F000+0x80+0x0))&0x07)==0x00))
|
|
group.long (0x0+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_0,Shifter Configuration 0 Register"
|
|
bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit,4-bit,4-bit,4-bit,8-bit,8-bit,8-bit,8-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
elif (((per.l(ad:0x4005F000+0x80+0x0))&0x07)==0x06)
|
|
group.long (0x0+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_0,Shifter Configuration 0 Register"
|
|
bitfld.long 0x00 19. " PWIDTH[3] ,Pin FXIO_D7 disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 18. " [2] ,Pin FXIO_D6 disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 17. " [1] ,Pin FXIO_D5 disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 16. " [0] ,Pin FXIO_D4 disable" "Enabled,Disabled"
|
|
newline
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
newline
|
|
bitfld.long 0x00 5. " SSTOP[1] ,Pin FXIO_D3 disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " [0] ,Pin FXIO_D2 disable" "Enabled,Disabled"
|
|
newline
|
|
bitfld.long 0x00 1. " SSTART[1] ,Pin FXIO_D1 disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin FXIO_D0 disable" "Enabled,Disabled"
|
|
elif (((per.l(ad:0x4005F000+0x80+0x0))&0x07)==0x07)
|
|
group.long (0x0+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_0,Shifter Configuration 0 Register"
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
newline
|
|
bitfld.long 0x00 5. " SSTOP[1] ,Pin FXIO_D3 mask" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " [0] ,Pin FXIO_D2 mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 1. " SSTART[1] ,Pin FXIO_D1 mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Pin FXIO_D0 mask" "Not masked,Masked"
|
|
elif ((((per.l(ad:0x4005F000+0x80+0x0))&0x07)==0x01)||(((per.l(ad:0x4005F000+0x80+0x0))&0x07)==0x02)||(((per.l(ad:0x4005F000+0x80+0x0))&0x07)==0x04))
|
|
group.long (0x0+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_0,Shifter Configuration 0 Register"
|
|
bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit,4-bit,4-bit,4-bit,8-bit,8-bit,8-bit,8-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,Output 0 / Expect 0,Output 1 / Expect 1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Load on enable,Load on 1st shift,Output 0 / Expect 0,Output 1 / Expect 1"
|
|
endif
|
|
group.long (0x0+0x200)++0x03
|
|
line.long 0x00 "SHIFTBUF_0,Shifter Buffer 0 Register"
|
|
group.long (0x0+0x280)++0x03
|
|
line.long 0x00 "SHIFTBUFBIS_0,Shifter Buffer 0 Bit Swapped Register"
|
|
group.long (0x0+0x300)++0x03
|
|
line.long 0x00 "SHIFTBUFBYS_0,Shifter Buffer 0 Byte Swapped Register"
|
|
group.long (0x0+0x380)++0x03
|
|
line.long 0x00 "SHIFTBUFBBS_0,Shifter Buffer 0 Bit Byte Swapped Register"
|
|
else
|
|
if (((per.l(ad:0x4005F000+0x80+0x0))&0x07)==0x05)
|
|
group.long (0x0+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_0,Shifter Configuration 0 Register"
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
hgroup.long (0x0+0x200)++0x03
|
|
hide.long 0x00 "SHIFTBUF_0,Shifter Buffer 0 Register"
|
|
in
|
|
hgroup.long (0x0+0x280)++0x03
|
|
hide.long 0x00 "SHIFTBUFBIS_0,Shifter Buffer 0 Bit Swapped Register"
|
|
in
|
|
hgroup.long (0x0+0x300)++0x03
|
|
hide.long 0x00 "SHIFTBUFBYS_0,Shifter Buffer 0 Byte Swapped Register"
|
|
in
|
|
hgroup.long (0x0+0x380)++0x03
|
|
hide.long 0x00 "SHIFTBUFBBS_0,Shifter Buffer 0 Bit Byte Swapped Register"
|
|
in
|
|
else
|
|
group.long (0x0+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_0,Shifter Configuration 0 Register"
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,0 on store,1 on store"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled / load on enable,Disabled / load on first shift,0 before first shift,1 before first shift"
|
|
group.long (0x0+0x200)++0x03
|
|
line.long 0x00 "SHIFTBUF_0,Shifter Buffer 0 Register"
|
|
group.long (0x0+0x280)++0x03
|
|
line.long 0x00 "SHIFTBUFBIS_0,Shifter Buffer 0 Bit Swapped Register"
|
|
group.long (0x0+0x300)++0x03
|
|
line.long 0x00 "SHIFTBUFBYS_0,Shifter Buffer 0 Byte Swapped Register"
|
|
group.long (0x0+0x380)++0x03
|
|
line.long 0x00 "SHIFTBUFBBS_0,Shifter Buffer 0 Bit Byte Swapped Register"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Shifter 1"
|
|
group.long (0x4+0x80)++0x03
|
|
line.long 0x00 "SHIFTCTL_1,Shifter Control 1 Register"
|
|
bitfld.long 0x00 24.--25. " TIMSEL ,Selects which timer is used for controlling the logic/shift register and generating the shift clock" "Timer 0,Timer 1,Timer 2,Timer 3"
|
|
bitfld.long 0x00 23. " TIMPOL ,Timer polarity" "Pos. edge,Neg. edge"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Shifter pin configuration" "Disabled,Open drain or bidir/Out,Bidir/Out data,Output"
|
|
newline
|
|
sif cpuis("IMXRT1021")
|
|
bitfld.long 0x00 8.--12. " PINSEL ,Shifter pin select" "FXIO_D0,FXIO_D1,FXIO_D2,FXIO_D3,FXIO_D4,FXIO_D5,FXIO_D6,FXIO_D7,FXIO_D8,FXIO_D9,FXIO_D10,FXIO_D11,FXIO_D12,FXIO_D13,FXIO_D14,FXIO_D15,FXIO_D16,FXIO_D17,FXIO_D18,FXIO_D19,FXIO_D20,FXIO_D21,FXIO_D22,FXIO_D23,FXIO_D24,FXIO_D25,FXIO_D26,FXIO_D27,FXIO_D28,FXIO_D29,FXIO_D30,FXIO_D31"
|
|
else
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Shifter pin select" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7"
|
|
endif
|
|
bitfld.long 0x00 7. " PINPOL ,Shifter pin polarity" "Active high,Active low"
|
|
sif cpuis("IMXRT1021")
|
|
bitfld.long 0x00 0.--2. " SMOD ,Configures the mode of the shifter" "Disabled,Receive,Transmit,,Match store,Match continuous,State,Logic"
|
|
else
|
|
bitfld.long 0x00 0.--2. " SMOD ,Configures the mode of the shifter" "Disabled,Receive mode,Transmit mode,,Match store,Match continuous,?..."
|
|
endif
|
|
newline
|
|
sif cpuis("IMXRT1021")
|
|
if ((((per.l(ad:0x4005F000+0x80+0x4))&0x07)==0x05)||(((per.l(ad:0x4005F000+0x80+0x4))&0x07)==0x00))
|
|
group.long (0x4+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_1,Shifter Configuration 1 Register"
|
|
bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit,4-bit,4-bit,4-bit,8-bit,8-bit,8-bit,8-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
elif (((per.l(ad:0x4005F000+0x80+0x4))&0x07)==0x06)
|
|
group.long (0x4+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_1,Shifter Configuration 1 Register"
|
|
bitfld.long 0x00 19. " PWIDTH[3] ,Pin FXIO_D7 disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 18. " [2] ,Pin FXIO_D6 disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 17. " [1] ,Pin FXIO_D5 disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 16. " [0] ,Pin FXIO_D4 disable" "Enabled,Disabled"
|
|
newline
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
newline
|
|
bitfld.long 0x00 5. " SSTOP[1] ,Pin FXIO_D3 disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " [0] ,Pin FXIO_D2 disable" "Enabled,Disabled"
|
|
newline
|
|
bitfld.long 0x00 1. " SSTART[1] ,Pin FXIO_D1 disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin FXIO_D0 disable" "Enabled,Disabled"
|
|
elif (((per.l(ad:0x4005F000+0x80+0x4))&0x07)==0x07)
|
|
group.long (0x4+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_1,Shifter Configuration 1 Register"
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
newline
|
|
bitfld.long 0x00 5. " SSTOP[1] ,Pin FXIO_D3 mask" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " [0] ,Pin FXIO_D2 mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 1. " SSTART[1] ,Pin FXIO_D1 mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Pin FXIO_D0 mask" "Not masked,Masked"
|
|
elif ((((per.l(ad:0x4005F000+0x80+0x4))&0x07)==0x01)||(((per.l(ad:0x4005F000+0x80+0x4))&0x07)==0x02)||(((per.l(ad:0x4005F000+0x80+0x4))&0x07)==0x04))
|
|
group.long (0x4+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_1,Shifter Configuration 1 Register"
|
|
bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit,4-bit,4-bit,4-bit,8-bit,8-bit,8-bit,8-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,Output 0 / Expect 0,Output 1 / Expect 1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Load on enable,Load on 1st shift,Output 0 / Expect 0,Output 1 / Expect 1"
|
|
endif
|
|
group.long (0x4+0x200)++0x03
|
|
line.long 0x00 "SHIFTBUF_1,Shifter Buffer 1 Register"
|
|
group.long (0x4+0x280)++0x03
|
|
line.long 0x00 "SHIFTBUFBIS_1,Shifter Buffer 1 Bit Swapped Register"
|
|
group.long (0x4+0x300)++0x03
|
|
line.long 0x00 "SHIFTBUFBYS_1,Shifter Buffer 1 Byte Swapped Register"
|
|
group.long (0x4+0x380)++0x03
|
|
line.long 0x00 "SHIFTBUFBBS_1,Shifter Buffer 1 Bit Byte Swapped Register"
|
|
else
|
|
if (((per.l(ad:0x4005F000+0x80+0x4))&0x07)==0x05)
|
|
group.long (0x4+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_1,Shifter Configuration 1 Register"
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
hgroup.long (0x4+0x200)++0x03
|
|
hide.long 0x00 "SHIFTBUF_1,Shifter Buffer 1 Register"
|
|
in
|
|
hgroup.long (0x4+0x280)++0x03
|
|
hide.long 0x00 "SHIFTBUFBIS_1,Shifter Buffer 1 Bit Swapped Register"
|
|
in
|
|
hgroup.long (0x4+0x300)++0x03
|
|
hide.long 0x00 "SHIFTBUFBYS_1,Shifter Buffer 1 Byte Swapped Register"
|
|
in
|
|
hgroup.long (0x4+0x380)++0x03
|
|
hide.long 0x00 "SHIFTBUFBBS_1,Shifter Buffer 1 Bit Byte Swapped Register"
|
|
in
|
|
else
|
|
group.long (0x4+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_1,Shifter Configuration 1 Register"
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,0 on store,1 on store"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled / load on enable,Disabled / load on first shift,0 before first shift,1 before first shift"
|
|
group.long (0x4+0x200)++0x03
|
|
line.long 0x00 "SHIFTBUF_1,Shifter Buffer 1 Register"
|
|
group.long (0x4+0x280)++0x03
|
|
line.long 0x00 "SHIFTBUFBIS_1,Shifter Buffer 1 Bit Swapped Register"
|
|
group.long (0x4+0x300)++0x03
|
|
line.long 0x00 "SHIFTBUFBYS_1,Shifter Buffer 1 Byte Swapped Register"
|
|
group.long (0x4+0x380)++0x03
|
|
line.long 0x00 "SHIFTBUFBBS_1,Shifter Buffer 1 Bit Byte Swapped Register"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Shifter 2"
|
|
group.long (0x8+0x80)++0x03
|
|
line.long 0x00 "SHIFTCTL_2,Shifter Control 2 Register"
|
|
bitfld.long 0x00 24.--25. " TIMSEL ,Selects which timer is used for controlling the logic/shift register and generating the shift clock" "Timer 0,Timer 1,Timer 2,Timer 3"
|
|
bitfld.long 0x00 23. " TIMPOL ,Timer polarity" "Pos. edge,Neg. edge"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Shifter pin configuration" "Disabled,Open drain or bidir/Out,Bidir/Out data,Output"
|
|
newline
|
|
sif cpuis("IMXRT1021")
|
|
bitfld.long 0x00 8.--12. " PINSEL ,Shifter pin select" "FXIO_D0,FXIO_D1,FXIO_D2,FXIO_D3,FXIO_D4,FXIO_D5,FXIO_D6,FXIO_D7,FXIO_D8,FXIO_D9,FXIO_D10,FXIO_D11,FXIO_D12,FXIO_D13,FXIO_D14,FXIO_D15,FXIO_D16,FXIO_D17,FXIO_D18,FXIO_D19,FXIO_D20,FXIO_D21,FXIO_D22,FXIO_D23,FXIO_D24,FXIO_D25,FXIO_D26,FXIO_D27,FXIO_D28,FXIO_D29,FXIO_D30,FXIO_D31"
|
|
else
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Shifter pin select" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7"
|
|
endif
|
|
bitfld.long 0x00 7. " PINPOL ,Shifter pin polarity" "Active high,Active low"
|
|
sif cpuis("IMXRT1021")
|
|
bitfld.long 0x00 0.--2. " SMOD ,Configures the mode of the shifter" "Disabled,Receive,Transmit,,Match store,Match continuous,State,Logic"
|
|
else
|
|
bitfld.long 0x00 0.--2. " SMOD ,Configures the mode of the shifter" "Disabled,Receive mode,Transmit mode,,Match store,Match continuous,?..."
|
|
endif
|
|
newline
|
|
sif cpuis("IMXRT1021")
|
|
if ((((per.l(ad:0x4005F000+0x80+0x8))&0x07)==0x05)||(((per.l(ad:0x4005F000+0x80+0x8))&0x07)==0x00))
|
|
group.long (0x8+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_2,Shifter Configuration 2 Register"
|
|
bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit,4-bit,4-bit,4-bit,8-bit,8-bit,8-bit,8-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
elif (((per.l(ad:0x4005F000+0x80+0x8))&0x07)==0x06)
|
|
group.long (0x8+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_2,Shifter Configuration 2 Register"
|
|
bitfld.long 0x00 19. " PWIDTH[3] ,Pin FXIO_D7 disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 18. " [2] ,Pin FXIO_D6 disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 17. " [1] ,Pin FXIO_D5 disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 16. " [0] ,Pin FXIO_D4 disable" "Enabled,Disabled"
|
|
newline
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
newline
|
|
bitfld.long 0x00 5. " SSTOP[1] ,Pin FXIO_D3 disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " [0] ,Pin FXIO_D2 disable" "Enabled,Disabled"
|
|
newline
|
|
bitfld.long 0x00 1. " SSTART[1] ,Pin FXIO_D1 disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin FXIO_D0 disable" "Enabled,Disabled"
|
|
elif (((per.l(ad:0x4005F000+0x80+0x8))&0x07)==0x07)
|
|
group.long (0x8+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_2,Shifter Configuration 2 Register"
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
newline
|
|
bitfld.long 0x00 5. " SSTOP[1] ,Pin FXIO_D3 mask" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " [0] ,Pin FXIO_D2 mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 1. " SSTART[1] ,Pin FXIO_D1 mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Pin FXIO_D0 mask" "Not masked,Masked"
|
|
elif ((((per.l(ad:0x4005F000+0x80+0x8))&0x07)==0x01)||(((per.l(ad:0x4005F000+0x80+0x8))&0x07)==0x02)||(((per.l(ad:0x4005F000+0x80+0x8))&0x07)==0x04))
|
|
group.long (0x8+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_2,Shifter Configuration 2 Register"
|
|
bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit,4-bit,4-bit,4-bit,8-bit,8-bit,8-bit,8-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,Output 0 / Expect 0,Output 1 / Expect 1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Load on enable,Load on 1st shift,Output 0 / Expect 0,Output 1 / Expect 1"
|
|
endif
|
|
group.long (0x8+0x200)++0x03
|
|
line.long 0x00 "SHIFTBUF_2,Shifter Buffer 2 Register"
|
|
group.long (0x8+0x280)++0x03
|
|
line.long 0x00 "SHIFTBUFBIS_2,Shifter Buffer 2 Bit Swapped Register"
|
|
group.long (0x8+0x300)++0x03
|
|
line.long 0x00 "SHIFTBUFBYS_2,Shifter Buffer 2 Byte Swapped Register"
|
|
group.long (0x8+0x380)++0x03
|
|
line.long 0x00 "SHIFTBUFBBS_2,Shifter Buffer 2 Bit Byte Swapped Register"
|
|
else
|
|
if (((per.l(ad:0x4005F000+0x80+0x8))&0x07)==0x05)
|
|
group.long (0x8+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_2,Shifter Configuration 2 Register"
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
hgroup.long (0x8+0x200)++0x03
|
|
hide.long 0x00 "SHIFTBUF_2,Shifter Buffer 2 Register"
|
|
in
|
|
hgroup.long (0x8+0x280)++0x03
|
|
hide.long 0x00 "SHIFTBUFBIS_2,Shifter Buffer 2 Bit Swapped Register"
|
|
in
|
|
hgroup.long (0x8+0x300)++0x03
|
|
hide.long 0x00 "SHIFTBUFBYS_2,Shifter Buffer 2 Byte Swapped Register"
|
|
in
|
|
hgroup.long (0x8+0x380)++0x03
|
|
hide.long 0x00 "SHIFTBUFBBS_2,Shifter Buffer 2 Bit Byte Swapped Register"
|
|
in
|
|
else
|
|
group.long (0x8+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_2,Shifter Configuration 2 Register"
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,0 on store,1 on store"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled / load on enable,Disabled / load on first shift,0 before first shift,1 before first shift"
|
|
group.long (0x8+0x200)++0x03
|
|
line.long 0x00 "SHIFTBUF_2,Shifter Buffer 2 Register"
|
|
group.long (0x8+0x280)++0x03
|
|
line.long 0x00 "SHIFTBUFBIS_2,Shifter Buffer 2 Bit Swapped Register"
|
|
group.long (0x8+0x300)++0x03
|
|
line.long 0x00 "SHIFTBUFBYS_2,Shifter Buffer 2 Byte Swapped Register"
|
|
group.long (0x8+0x380)++0x03
|
|
line.long 0x00 "SHIFTBUFBBS_2,Shifter Buffer 2 Bit Byte Swapped Register"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Shifter 3"
|
|
group.long (0xC+0x80)++0x03
|
|
line.long 0x00 "SHIFTCTL_3,Shifter Control 3 Register"
|
|
bitfld.long 0x00 24.--25. " TIMSEL ,Selects which timer is used for controlling the logic/shift register and generating the shift clock" "Timer 0,Timer 1,Timer 2,Timer 3"
|
|
bitfld.long 0x00 23. " TIMPOL ,Timer polarity" "Pos. edge,Neg. edge"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Shifter pin configuration" "Disabled,Open drain or bidir/Out,Bidir/Out data,Output"
|
|
newline
|
|
sif cpuis("IMXRT1021")
|
|
bitfld.long 0x00 8.--12. " PINSEL ,Shifter pin select" "FXIO_D0,FXIO_D1,FXIO_D2,FXIO_D3,FXIO_D4,FXIO_D5,FXIO_D6,FXIO_D7,FXIO_D8,FXIO_D9,FXIO_D10,FXIO_D11,FXIO_D12,FXIO_D13,FXIO_D14,FXIO_D15,FXIO_D16,FXIO_D17,FXIO_D18,FXIO_D19,FXIO_D20,FXIO_D21,FXIO_D22,FXIO_D23,FXIO_D24,FXIO_D25,FXIO_D26,FXIO_D27,FXIO_D28,FXIO_D29,FXIO_D30,FXIO_D31"
|
|
else
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Shifter pin select" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7"
|
|
endif
|
|
bitfld.long 0x00 7. " PINPOL ,Shifter pin polarity" "Active high,Active low"
|
|
sif cpuis("IMXRT1021")
|
|
bitfld.long 0x00 0.--2. " SMOD ,Configures the mode of the shifter" "Disabled,Receive,Transmit,,Match store,Match continuous,State,Logic"
|
|
else
|
|
bitfld.long 0x00 0.--2. " SMOD ,Configures the mode of the shifter" "Disabled,Receive mode,Transmit mode,,Match store,Match continuous,?..."
|
|
endif
|
|
newline
|
|
sif cpuis("IMXRT1021")
|
|
if ((((per.l(ad:0x4005F000+0x80+0xC))&0x07)==0x05)||(((per.l(ad:0x4005F000+0x80+0xC))&0x07)==0x00))
|
|
group.long (0xC+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_3,Shifter Configuration 3 Register"
|
|
bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit,4-bit,4-bit,4-bit,8-bit,8-bit,8-bit,8-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
elif (((per.l(ad:0x4005F000+0x80+0xC))&0x07)==0x06)
|
|
group.long (0xC+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_3,Shifter Configuration 3 Register"
|
|
bitfld.long 0x00 19. " PWIDTH[3] ,Pin FXIO_D7 disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 18. " [2] ,Pin FXIO_D6 disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 17. " [1] ,Pin FXIO_D5 disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 16. " [0] ,Pin FXIO_D4 disable" "Enabled,Disabled"
|
|
newline
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
newline
|
|
bitfld.long 0x00 5. " SSTOP[1] ,Pin FXIO_D3 disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " [0] ,Pin FXIO_D2 disable" "Enabled,Disabled"
|
|
newline
|
|
bitfld.long 0x00 1. " SSTART[1] ,Pin FXIO_D1 disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin FXIO_D0 disable" "Enabled,Disabled"
|
|
elif (((per.l(ad:0x4005F000+0x80+0xC))&0x07)==0x07)
|
|
group.long (0xC+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_3,Shifter Configuration 3 Register"
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
newline
|
|
bitfld.long 0x00 5. " SSTOP[1] ,Pin FXIO_D3 mask" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " [0] ,Pin FXIO_D2 mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 1. " SSTART[1] ,Pin FXIO_D1 mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Pin FXIO_D0 mask" "Not masked,Masked"
|
|
elif ((((per.l(ad:0x4005F000+0x80+0xC))&0x07)==0x01)||(((per.l(ad:0x4005F000+0x80+0xC))&0x07)==0x02)||(((per.l(ad:0x4005F000+0x80+0xC))&0x07)==0x04))
|
|
group.long (0xC+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_3,Shifter Configuration 3 Register"
|
|
bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit,4-bit,4-bit,4-bit,8-bit,8-bit,8-bit,8-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,Output 0 / Expect 0,Output 1 / Expect 1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Load on enable,Load on 1st shift,Output 0 / Expect 0,Output 1 / Expect 1"
|
|
endif
|
|
group.long (0xC+0x200)++0x03
|
|
line.long 0x00 "SHIFTBUF_3,Shifter Buffer 3 Register"
|
|
group.long (0xC+0x280)++0x03
|
|
line.long 0x00 "SHIFTBUFBIS_3,Shifter Buffer 3 Bit Swapped Register"
|
|
group.long (0xC+0x300)++0x03
|
|
line.long 0x00 "SHIFTBUFBYS_3,Shifter Buffer 3 Byte Swapped Register"
|
|
group.long (0xC+0x380)++0x03
|
|
line.long 0x00 "SHIFTBUFBBS_3,Shifter Buffer 3 Bit Byte Swapped Register"
|
|
else
|
|
if (((per.l(ad:0x4005F000+0x80+0xC))&0x07)==0x05)
|
|
group.long (0xC+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_3,Shifter Configuration 3 Register"
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
hgroup.long (0xC+0x200)++0x03
|
|
hide.long 0x00 "SHIFTBUF_3,Shifter Buffer 3 Register"
|
|
in
|
|
hgroup.long (0xC+0x280)++0x03
|
|
hide.long 0x00 "SHIFTBUFBIS_3,Shifter Buffer 3 Bit Swapped Register"
|
|
in
|
|
hgroup.long (0xC+0x300)++0x03
|
|
hide.long 0x00 "SHIFTBUFBYS_3,Shifter Buffer 3 Byte Swapped Register"
|
|
in
|
|
hgroup.long (0xC+0x380)++0x03
|
|
hide.long 0x00 "SHIFTBUFBBS_3,Shifter Buffer 3 Bit Byte Swapped Register"
|
|
in
|
|
else
|
|
group.long (0xC+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG_3,Shifter Configuration 3 Register"
|
|
bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,0 on store,1 on store"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled / load on enable,Disabled / load on first shift,0 before first shift,1 before first shift"
|
|
group.long (0xC+0x200)++0x03
|
|
line.long 0x00 "SHIFTBUF_3,Shifter Buffer 3 Register"
|
|
group.long (0xC+0x280)++0x03
|
|
line.long 0x00 "SHIFTBUFBIS_3,Shifter Buffer 3 Bit Swapped Register"
|
|
group.long (0xC+0x300)++0x03
|
|
line.long 0x00 "SHIFTBUFBYS_3,Shifter Buffer 3 Byte Swapped Register"
|
|
group.long (0xC+0x380)++0x03
|
|
line.long 0x00 "SHIFTBUFBBS_3,Shifter Buffer 3 Bit Byte Swapped Register"
|
|
endif
|
|
endif
|
|
tree.end
|
|
width 10.
|
|
tree "Timer 0"
|
|
if (((per.l(ad:0x4005F000+0x400+0x0))&0x400000)==0x400000)
|
|
group.long (0x0+0x400)++0x03
|
|
line.long 0x00 "TIMCTL_0,Timer Control N Register"
|
|
sif cpuis("IMXRT1021")
|
|
bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "FXIO0_D0,Shifter 0 status flag,FXIO0_D1,Timer 0 trigger output,FXIO0_D2,Shifter 1 status flag,FXIO0_D3,Timer 1 trigger output,FXIO0_D4,Shifter 2 status flag,FXIO0_D5,Timer 2 trigger output,FXIO0_D6,Shifter 3 status flag,FXIO0_D7,Timer 3 trigger output,FXIO0_D8,,FXIO0_D9,,FXIO0_D10,,FXIO0_D11,,FXIO0_D12,,FXIO0_D13,,FXIO0_D14,,FXIO0_D15,,FXIO0_D16,,FXIO0_D17,,FXIO0_D18,,FXIO0_D19,,FXIO0_D20,,FXIO0_D21,,FXIO0_D22,,FXIO0_D23,,FXIO0_D24,,FXIO0_D25,,FXIO0_D26,,FXIO0_D27,,FXIO0_D28,,FXIO0_D29,,FXIO0_D30,,FXIO0_D31,?..."
|
|
else
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,,,PIT_0,PIT_1,,,TMP_0,TMP_1,TMP_2,,RTC alarm,RTC seconds,LPTMR,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output"
|
|
newline
|
|
sif cpuis("IMXRT1021")
|
|
bitfld.long 0x00 8.--12. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7,FXIO0_D8,FXIO0_D9,FXIO0_D10,FXIO0_D11,FXIO0_D12,FXIO0_D13,FXIO0_D14,FXIO0_D15,FXIO0_D16,FXIO0_D17,FXIO0_D18,FXIO0_D19,FXIO0_D20,FXIO0_D21,FXIO0_D22,FXIO0_D23,FXIO0_D24,FXIO0_D25,FXIO0_D26,FXIO0_D27,FXIO0_D28,FXIO0_D29,FXIO0_D30,FXIO0_D31"
|
|
else
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7"
|
|
endif
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low"
|
|
newline
|
|
sif cpuis("IMXRT1021")
|
|
bitfld.long 0x00 0.--1. " TIMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit"
|
|
else
|
|
bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit"
|
|
endif
|
|
else
|
|
group.long (0x0+0x400)++0x03 "Timer 0"
|
|
line.long 0x00 "TIMCTL_0,Timer Control N Register"
|
|
sif cpuis("IMXRT1021")
|
|
bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "FXIO0_D0,Shifter 0 status flag,FXIO0_D1,Timer 0 trigger output,FXIO0_D2,Shifter 1 status flag,FXIO0_D3,Timer 1 trigger output,FXIO0_D4,Shifter 2 status flag,FXIO0_D5,Timer 2 trigger output,FXIO0_D6,Shifter 3 status flag,FXIO0_D7,Timer 3 trigger output"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output"
|
|
newline
|
|
sif cpuis("IMXRT1021")
|
|
bitfld.long 0x00 8.--12. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7,FXIO0_D8,FXIO0_D9,FXIO0_D10,FXIO0_D11,FXIO0_D12,FXIO0_D13,FXIO0_D14,FXIO0_D15,FXIO0_D16,FXIO0_D17,FXIO0_D18,FXIO0_D19,FXIO0_D20,FXIO0_D21,FXIO0_D22,FXIO0_D23,FXIO0_D24,FXIO0_D25,FXIO0_D26,FXIO0_D27,FXIO0_D28,FXIO0_D29,FXIO0_D30,FXIO0_D31"
|
|
else
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7"
|
|
endif
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low"
|
|
newline
|
|
sif cpuis("IMXRT1021")
|
|
bitfld.long 0x00 0.--1. " TIMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit"
|
|
else
|
|
bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit"
|
|
endif
|
|
endif
|
|
group.long (0x0+0x480)++0x03
|
|
line.long 0x00 "TIMCFG_0,Timer Configuration 0 Register"
|
|
bitfld.long 0x00 24.--25. " TIMOUT ,Configures the initial state of the timer output and whether it is affected by the timer reset" "1 not affected,0 not affected,1 on reset,0 on reset"
|
|
bitfld.long 0x00 20.--21. " TIMDEC ,Configures the source of the timer decrement and the source of the shift clock" "Flexio clk / shift clk = timer out,Trigger input / shift clk = timer out,Pin input / shift clk = pin input,Trigger input / shift clk = trigger input"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " TIMRST ,Configures the condition that causes the timer counter (And optionally the timer output) to be reset" "Never,,Pin == timer output,Trigger == timer output,Pin rising,,Trigger rising,Trigger rising or falling"
|
|
bitfld.long 0x00 12.--14. " TIMDIS ,Configures the condition that causes the timer to be disabled and stop decrementing" "Never,Timer N+1 dis,Timer cmp,Timer cmp & trigger low,Pin both edges,Pin both edges & trigger high,Trigger falling,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. " TIMENA ,Configures the condition that causes the timer to be enabled and start decrementing" "Always enabled,Timer N-1 enable,Trigger high,Trigger & pin high,Pin rising,Pin rising & trigger high,Trigger rising,Trigger both edges"
|
|
bitfld.long 0x00 4.--5. " TSTOP ,Timer stop bit" "Disabled,On timer cmp,On timer disable,On timer cmp & disable"
|
|
newline
|
|
bitfld.long 0x00 1. " TSTART ,Timer start bit enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x4005F000+0x400+0x0))&0x3)==0x1)
|
|
group.long (0x0+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_0,Timer Compare 0 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the number of bits in each word equal to (CMP[15:8] + 1)/2"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the baud rate divider equal to (CMP[7:0] + 1) * 2"
|
|
elif (((per.l(ad:0x4005F000+0x400+0x0))&0x3)==0x2)
|
|
group.long (0x0+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_0,Timer Compare 0 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the low period of the output to (CMP[15:8] + 1) * 2"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the high period of the output to (CMP[7:0] + 1) * 2"
|
|
elif (((per.l(ad:0x4005F000+0x400+0x0))&0x3)==0x3)
|
|
group.long (0x0+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_0,Timer Compare 0 Register"
|
|
sif cpuis("IMXRT1021")
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Baud rate divider to equal (CMP[15:0] + 1)*2 (if shift clock source is timer output) or (CMP[15:0] + 1)/2 (if shift clock source is a pin or trigger input)"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Baud rate divider (If shift clock source is timer output) to equal (CMP[15:0] + 1)*2 or"
|
|
endif
|
|
else
|
|
group.long (0x0+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_0,Timer Compare 0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Timer compare value"
|
|
endif
|
|
tree.end
|
|
tree "Timer 1"
|
|
if (((per.l(ad:0x4005F000+0x400+0x4))&0x400000)==0x400000)
|
|
group.long (0x4+0x400)++0x03
|
|
line.long 0x00 "TIMCTL_1,Timer Control N Register"
|
|
sif cpuis("IMXRT1021")
|
|
bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "FXIO0_D0,Shifter 0 status flag,FXIO0_D1,Timer 0 trigger output,FXIO0_D2,Shifter 1 status flag,FXIO0_D3,Timer 1 trigger output,FXIO0_D4,Shifter 2 status flag,FXIO0_D5,Timer 2 trigger output,FXIO0_D6,Shifter 3 status flag,FXIO0_D7,Timer 3 trigger output,FXIO0_D8,,FXIO0_D9,,FXIO0_D10,,FXIO0_D11,,FXIO0_D12,,FXIO0_D13,,FXIO0_D14,,FXIO0_D15,,FXIO0_D16,,FXIO0_D17,,FXIO0_D18,,FXIO0_D19,,FXIO0_D20,,FXIO0_D21,,FXIO0_D22,,FXIO0_D23,,FXIO0_D24,,FXIO0_D25,,FXIO0_D26,,FXIO0_D27,,FXIO0_D28,,FXIO0_D29,,FXIO0_D30,,FXIO0_D31,?..."
|
|
else
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,,,PIT_0,PIT_1,,,TMP_0,TMP_1,TMP_2,,RTC alarm,RTC seconds,LPTMR,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output"
|
|
newline
|
|
sif cpuis("IMXRT1021")
|
|
bitfld.long 0x00 8.--12. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7,FXIO0_D8,FXIO0_D9,FXIO0_D10,FXIO0_D11,FXIO0_D12,FXIO0_D13,FXIO0_D14,FXIO0_D15,FXIO0_D16,FXIO0_D17,FXIO0_D18,FXIO0_D19,FXIO0_D20,FXIO0_D21,FXIO0_D22,FXIO0_D23,FXIO0_D24,FXIO0_D25,FXIO0_D26,FXIO0_D27,FXIO0_D28,FXIO0_D29,FXIO0_D30,FXIO0_D31"
|
|
else
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7"
|
|
endif
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low"
|
|
newline
|
|
sif cpuis("IMXRT1021")
|
|
bitfld.long 0x00 0.--1. " TIMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit"
|
|
else
|
|
bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit"
|
|
endif
|
|
else
|
|
group.long (0x4+0x400)++0x03 "Timer 1"
|
|
line.long 0x00 "TIMCTL_1,Timer Control N Register"
|
|
sif cpuis("IMXRT1021")
|
|
bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "FXIO0_D0,Shifter 0 status flag,FXIO0_D1,Timer 0 trigger output,FXIO0_D2,Shifter 1 status flag,FXIO0_D3,Timer 1 trigger output,FXIO0_D4,Shifter 2 status flag,FXIO0_D5,Timer 2 trigger output,FXIO0_D6,Shifter 3 status flag,FXIO0_D7,Timer 3 trigger output"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output"
|
|
newline
|
|
sif cpuis("IMXRT1021")
|
|
bitfld.long 0x00 8.--12. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7,FXIO0_D8,FXIO0_D9,FXIO0_D10,FXIO0_D11,FXIO0_D12,FXIO0_D13,FXIO0_D14,FXIO0_D15,FXIO0_D16,FXIO0_D17,FXIO0_D18,FXIO0_D19,FXIO0_D20,FXIO0_D21,FXIO0_D22,FXIO0_D23,FXIO0_D24,FXIO0_D25,FXIO0_D26,FXIO0_D27,FXIO0_D28,FXIO0_D29,FXIO0_D30,FXIO0_D31"
|
|
else
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7"
|
|
endif
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low"
|
|
newline
|
|
sif cpuis("IMXRT1021")
|
|
bitfld.long 0x00 0.--1. " TIMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit"
|
|
else
|
|
bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit"
|
|
endif
|
|
endif
|
|
group.long (0x4+0x480)++0x03
|
|
line.long 0x00 "TIMCFG_1,Timer Configuration 1 Register"
|
|
bitfld.long 0x00 24.--25. " TIMOUT ,Configures the initial state of the timer output and whether it is affected by the timer reset" "1 not affected,0 not affected,1 on reset,0 on reset"
|
|
bitfld.long 0x00 20.--21. " TIMDEC ,Configures the source of the timer decrement and the source of the shift clock" "Flexio clk / shift clk = timer out,Trigger input / shift clk = timer out,Pin input / shift clk = pin input,Trigger input / shift clk = trigger input"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " TIMRST ,Configures the condition that causes the timer counter (And optionally the timer output) to be reset" "Never,,Pin == timer output,Trigger == timer output,Pin rising,,Trigger rising,Trigger rising or falling"
|
|
bitfld.long 0x00 12.--14. " TIMDIS ,Configures the condition that causes the timer to be disabled and stop decrementing" "Never,Timer N+1 dis,Timer cmp,Timer cmp & trigger low,Pin both edges,Pin both edges & trigger high,Trigger falling,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. " TIMENA ,Configures the condition that causes the timer to be enabled and start decrementing" "Always enabled,Timer N-1 enable,Trigger high,Trigger & pin high,Pin rising,Pin rising & trigger high,Trigger rising,Trigger both edges"
|
|
bitfld.long 0x00 4.--5. " TSTOP ,Timer stop bit" "Disabled,On timer cmp,On timer disable,On timer cmp & disable"
|
|
newline
|
|
bitfld.long 0x00 1. " TSTART ,Timer start bit enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x4005F000+0x400+0x4))&0x3)==0x1)
|
|
group.long (0x4+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_1,Timer Compare 1 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the number of bits in each word equal to (CMP[15:8] + 1)/2"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the baud rate divider equal to (CMP[7:0] + 1) * 2"
|
|
elif (((per.l(ad:0x4005F000+0x400+0x4))&0x3)==0x2)
|
|
group.long (0x4+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_1,Timer Compare 1 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the low period of the output to (CMP[15:8] + 1) * 2"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the high period of the output to (CMP[7:0] + 1) * 2"
|
|
elif (((per.l(ad:0x4005F000+0x400+0x4))&0x3)==0x3)
|
|
group.long (0x4+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_1,Timer Compare 1 Register"
|
|
sif cpuis("IMXRT1021")
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Baud rate divider to equal (CMP[15:0] + 1)*2 (if shift clock source is timer output) or (CMP[15:0] + 1)/2 (if shift clock source is a pin or trigger input)"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Baud rate divider (If shift clock source is timer output) to equal (CMP[15:0] + 1)*2 or"
|
|
endif
|
|
else
|
|
group.long (0x4+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_1,Timer Compare 1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Timer compare value"
|
|
endif
|
|
tree.end
|
|
tree "Timer 2"
|
|
if (((per.l(ad:0x4005F000+0x400+0x8))&0x400000)==0x400000)
|
|
group.long (0x8+0x400)++0x03
|
|
line.long 0x00 "TIMCTL_2,Timer Control N Register"
|
|
sif cpuis("IMXRT1021")
|
|
bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "FXIO0_D0,Shifter 0 status flag,FXIO0_D1,Timer 0 trigger output,FXIO0_D2,Shifter 1 status flag,FXIO0_D3,Timer 1 trigger output,FXIO0_D4,Shifter 2 status flag,FXIO0_D5,Timer 2 trigger output,FXIO0_D6,Shifter 3 status flag,FXIO0_D7,Timer 3 trigger output,FXIO0_D8,,FXIO0_D9,,FXIO0_D10,,FXIO0_D11,,FXIO0_D12,,FXIO0_D13,,FXIO0_D14,,FXIO0_D15,,FXIO0_D16,,FXIO0_D17,,FXIO0_D18,,FXIO0_D19,,FXIO0_D20,,FXIO0_D21,,FXIO0_D22,,FXIO0_D23,,FXIO0_D24,,FXIO0_D25,,FXIO0_D26,,FXIO0_D27,,FXIO0_D28,,FXIO0_D29,,FXIO0_D30,,FXIO0_D31,?..."
|
|
else
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,,,PIT_0,PIT_1,,,TMP_0,TMP_1,TMP_2,,RTC alarm,RTC seconds,LPTMR,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output"
|
|
newline
|
|
sif cpuis("IMXRT1021")
|
|
bitfld.long 0x00 8.--12. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7,FXIO0_D8,FXIO0_D9,FXIO0_D10,FXIO0_D11,FXIO0_D12,FXIO0_D13,FXIO0_D14,FXIO0_D15,FXIO0_D16,FXIO0_D17,FXIO0_D18,FXIO0_D19,FXIO0_D20,FXIO0_D21,FXIO0_D22,FXIO0_D23,FXIO0_D24,FXIO0_D25,FXIO0_D26,FXIO0_D27,FXIO0_D28,FXIO0_D29,FXIO0_D30,FXIO0_D31"
|
|
else
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7"
|
|
endif
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low"
|
|
newline
|
|
sif cpuis("IMXRT1021")
|
|
bitfld.long 0x00 0.--1. " TIMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit"
|
|
else
|
|
bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit"
|
|
endif
|
|
else
|
|
group.long (0x8+0x400)++0x03 "Timer 2"
|
|
line.long 0x00 "TIMCTL_2,Timer Control N Register"
|
|
sif cpuis("IMXRT1021")
|
|
bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "FXIO0_D0,Shifter 0 status flag,FXIO0_D1,Timer 0 trigger output,FXIO0_D2,Shifter 1 status flag,FXIO0_D3,Timer 1 trigger output,FXIO0_D4,Shifter 2 status flag,FXIO0_D5,Timer 2 trigger output,FXIO0_D6,Shifter 3 status flag,FXIO0_D7,Timer 3 trigger output"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output"
|
|
newline
|
|
sif cpuis("IMXRT1021")
|
|
bitfld.long 0x00 8.--12. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7,FXIO0_D8,FXIO0_D9,FXIO0_D10,FXIO0_D11,FXIO0_D12,FXIO0_D13,FXIO0_D14,FXIO0_D15,FXIO0_D16,FXIO0_D17,FXIO0_D18,FXIO0_D19,FXIO0_D20,FXIO0_D21,FXIO0_D22,FXIO0_D23,FXIO0_D24,FXIO0_D25,FXIO0_D26,FXIO0_D27,FXIO0_D28,FXIO0_D29,FXIO0_D30,FXIO0_D31"
|
|
else
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7"
|
|
endif
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low"
|
|
newline
|
|
sif cpuis("IMXRT1021")
|
|
bitfld.long 0x00 0.--1. " TIMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit"
|
|
else
|
|
bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit"
|
|
endif
|
|
endif
|
|
group.long (0x8+0x480)++0x03
|
|
line.long 0x00 "TIMCFG_2,Timer Configuration 2 Register"
|
|
bitfld.long 0x00 24.--25. " TIMOUT ,Configures the initial state of the timer output and whether it is affected by the timer reset" "1 not affected,0 not affected,1 on reset,0 on reset"
|
|
bitfld.long 0x00 20.--21. " TIMDEC ,Configures the source of the timer decrement and the source of the shift clock" "Flexio clk / shift clk = timer out,Trigger input / shift clk = timer out,Pin input / shift clk = pin input,Trigger input / shift clk = trigger input"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " TIMRST ,Configures the condition that causes the timer counter (And optionally the timer output) to be reset" "Never,,Pin == timer output,Trigger == timer output,Pin rising,,Trigger rising,Trigger rising or falling"
|
|
bitfld.long 0x00 12.--14. " TIMDIS ,Configures the condition that causes the timer to be disabled and stop decrementing" "Never,Timer N+1 dis,Timer cmp,Timer cmp & trigger low,Pin both edges,Pin both edges & trigger high,Trigger falling,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. " TIMENA ,Configures the condition that causes the timer to be enabled and start decrementing" "Always enabled,Timer N-1 enable,Trigger high,Trigger & pin high,Pin rising,Pin rising & trigger high,Trigger rising,Trigger both edges"
|
|
bitfld.long 0x00 4.--5. " TSTOP ,Timer stop bit" "Disabled,On timer cmp,On timer disable,On timer cmp & disable"
|
|
newline
|
|
bitfld.long 0x00 1. " TSTART ,Timer start bit enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x4005F000+0x400+0x8))&0x3)==0x1)
|
|
group.long (0x8+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_2,Timer Compare 2 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the number of bits in each word equal to (CMP[15:8] + 1)/2"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the baud rate divider equal to (CMP[7:0] + 1) * 2"
|
|
elif (((per.l(ad:0x4005F000+0x400+0x8))&0x3)==0x2)
|
|
group.long (0x8+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_2,Timer Compare 2 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the low period of the output to (CMP[15:8] + 1) * 2"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the high period of the output to (CMP[7:0] + 1) * 2"
|
|
elif (((per.l(ad:0x4005F000+0x400+0x8))&0x3)==0x3)
|
|
group.long (0x8+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_2,Timer Compare 2 Register"
|
|
sif cpuis("IMXRT1021")
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Baud rate divider to equal (CMP[15:0] + 1)*2 (if shift clock source is timer output) or (CMP[15:0] + 1)/2 (if shift clock source is a pin or trigger input)"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Baud rate divider (If shift clock source is timer output) to equal (CMP[15:0] + 1)*2 or"
|
|
endif
|
|
else
|
|
group.long (0x8+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_2,Timer Compare 2 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Timer compare value"
|
|
endif
|
|
tree.end
|
|
tree "Timer 3"
|
|
if (((per.l(ad:0x4005F000+0x400+0xC))&0x400000)==0x400000)
|
|
group.long (0xC+0x400)++0x03
|
|
line.long 0x00 "TIMCTL_3,Timer Control N Register"
|
|
sif cpuis("IMXRT1021")
|
|
bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "FXIO0_D0,Shifter 0 status flag,FXIO0_D1,Timer 0 trigger output,FXIO0_D2,Shifter 1 status flag,FXIO0_D3,Timer 1 trigger output,FXIO0_D4,Shifter 2 status flag,FXIO0_D5,Timer 2 trigger output,FXIO0_D6,Shifter 3 status flag,FXIO0_D7,Timer 3 trigger output,FXIO0_D8,,FXIO0_D9,,FXIO0_D10,,FXIO0_D11,,FXIO0_D12,,FXIO0_D13,,FXIO0_D14,,FXIO0_D15,,FXIO0_D16,,FXIO0_D17,,FXIO0_D18,,FXIO0_D19,,FXIO0_D20,,FXIO0_D21,,FXIO0_D22,,FXIO0_D23,,FXIO0_D24,,FXIO0_D25,,FXIO0_D26,,FXIO0_D27,,FXIO0_D28,,FXIO0_D29,,FXIO0_D30,,FXIO0_D31,?..."
|
|
else
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,,,PIT_0,PIT_1,,,TMP_0,TMP_1,TMP_2,,RTC alarm,RTC seconds,LPTMR,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output"
|
|
newline
|
|
sif cpuis("IMXRT1021")
|
|
bitfld.long 0x00 8.--12. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7,FXIO0_D8,FXIO0_D9,FXIO0_D10,FXIO0_D11,FXIO0_D12,FXIO0_D13,FXIO0_D14,FXIO0_D15,FXIO0_D16,FXIO0_D17,FXIO0_D18,FXIO0_D19,FXIO0_D20,FXIO0_D21,FXIO0_D22,FXIO0_D23,FXIO0_D24,FXIO0_D25,FXIO0_D26,FXIO0_D27,FXIO0_D28,FXIO0_D29,FXIO0_D30,FXIO0_D31"
|
|
else
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7"
|
|
endif
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low"
|
|
newline
|
|
sif cpuis("IMXRT1021")
|
|
bitfld.long 0x00 0.--1. " TIMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit"
|
|
else
|
|
bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit"
|
|
endif
|
|
else
|
|
group.long (0xC+0x400)++0x03 "Timer 3"
|
|
line.long 0x00 "TIMCTL_3,Timer Control N Register"
|
|
sif cpuis("IMXRT1021")
|
|
bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "FXIO0_D0,Shifter 0 status flag,FXIO0_D1,Timer 0 trigger output,FXIO0_D2,Shifter 1 status flag,FXIO0_D3,Timer 1 trigger output,FXIO0_D4,Shifter 2 status flag,FXIO0_D5,Timer 2 trigger output,FXIO0_D6,Shifter 3 status flag,FXIO0_D7,Timer 3 trigger output"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal"
|
|
bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output"
|
|
newline
|
|
sif cpuis("IMXRT1021")
|
|
bitfld.long 0x00 8.--12. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7,FXIO0_D8,FXIO0_D9,FXIO0_D10,FXIO0_D11,FXIO0_D12,FXIO0_D13,FXIO0_D14,FXIO0_D15,FXIO0_D16,FXIO0_D17,FXIO0_D18,FXIO0_D19,FXIO0_D20,FXIO0_D21,FXIO0_D22,FXIO0_D23,FXIO0_D24,FXIO0_D25,FXIO0_D26,FXIO0_D27,FXIO0_D28,FXIO0_D29,FXIO0_D30,FXIO0_D31"
|
|
else
|
|
bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7"
|
|
endif
|
|
bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low"
|
|
newline
|
|
sif cpuis("IMXRT1021")
|
|
bitfld.long 0x00 0.--1. " TIMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit"
|
|
else
|
|
bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit"
|
|
endif
|
|
endif
|
|
group.long (0xC+0x480)++0x03
|
|
line.long 0x00 "TIMCFG_3,Timer Configuration 3 Register"
|
|
bitfld.long 0x00 24.--25. " TIMOUT ,Configures the initial state of the timer output and whether it is affected by the timer reset" "1 not affected,0 not affected,1 on reset,0 on reset"
|
|
bitfld.long 0x00 20.--21. " TIMDEC ,Configures the source of the timer decrement and the source of the shift clock" "Flexio clk / shift clk = timer out,Trigger input / shift clk = timer out,Pin input / shift clk = pin input,Trigger input / shift clk = trigger input"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " TIMRST ,Configures the condition that causes the timer counter (And optionally the timer output) to be reset" "Never,,Pin == timer output,Trigger == timer output,Pin rising,,Trigger rising,Trigger rising or falling"
|
|
bitfld.long 0x00 12.--14. " TIMDIS ,Configures the condition that causes the timer to be disabled and stop decrementing" "Never,Timer N+1 dis,Timer cmp,Timer cmp & trigger low,Pin both edges,Pin both edges & trigger high,Trigger falling,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. " TIMENA ,Configures the condition that causes the timer to be enabled and start decrementing" "Always enabled,Timer N-1 enable,Trigger high,Trigger & pin high,Pin rising,Pin rising & trigger high,Trigger rising,Trigger both edges"
|
|
bitfld.long 0x00 4.--5. " TSTOP ,Timer stop bit" "Disabled,On timer cmp,On timer disable,On timer cmp & disable"
|
|
newline
|
|
bitfld.long 0x00 1. " TSTART ,Timer start bit enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x4005F000+0x400+0xC))&0x3)==0x1)
|
|
group.long (0xC+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_3,Timer Compare 3 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the number of bits in each word equal to (CMP[15:8] + 1)/2"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the baud rate divider equal to (CMP[7:0] + 1) * 2"
|
|
elif (((per.l(ad:0x4005F000+0x400+0xC))&0x3)==0x2)
|
|
group.long (0xC+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_3,Timer Compare 3 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the low period of the output to (CMP[15:8] + 1) * 2"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the high period of the output to (CMP[7:0] + 1) * 2"
|
|
elif (((per.l(ad:0x4005F000+0x400+0xC))&0x3)==0x3)
|
|
group.long (0xC+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_3,Timer Compare 3 Register"
|
|
sif cpuis("IMXRT1021")
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Baud rate divider to equal (CMP[15:0] + 1)*2 (if shift clock source is timer output) or (CMP[15:0] + 1)/2 (if shift clock source is a pin or trigger input)"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Baud rate divider (If shift clock source is timer output) to equal (CMP[15:0] + 1)*2 or"
|
|
endif
|
|
else
|
|
group.long (0xC+0x500)++0x03
|
|
line.long 0x00 "TIMCMP_3,Timer Compare 3 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Timer compare value"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("IMXRT1021")
|
|
width 14.
|
|
newline
|
|
group.long (0x0+0x680)++0x03
|
|
line.long 0x00 "SHIFTBUFNBS0,Shifter Buffer 0 Nibble Byte Swapped"
|
|
group.long (0x0+0x700)++0x03
|
|
line.long 0x00 "SHIFTBUFHWS0,Shifter Buffer 0 Half Word Swapped"
|
|
group.long (0x0+0x780)++0x03
|
|
line.long 0x00 "SHIFTBUFNIS0,Shifter Buffer 0 Nibble Swapped"
|
|
newline
|
|
group.long (0x4+0x680)++0x03
|
|
line.long 0x00 "SHIFTBUFNBS1,Shifter Buffer 1 Nibble Byte Swapped"
|
|
group.long (0x4+0x700)++0x03
|
|
line.long 0x00 "SHIFTBUFHWS1,Shifter Buffer 1 Half Word Swapped"
|
|
group.long (0x4+0x780)++0x03
|
|
line.long 0x00 "SHIFTBUFNIS1,Shifter Buffer 1 Nibble Swapped"
|
|
newline
|
|
group.long (0x8+0x680)++0x03
|
|
line.long 0x00 "SHIFTBUFNBS2,Shifter Buffer 2 Nibble Byte Swapped"
|
|
group.long (0x8+0x700)++0x03
|
|
line.long 0x00 "SHIFTBUFHWS2,Shifter Buffer 2 Half Word Swapped"
|
|
group.long (0x8+0x780)++0x03
|
|
line.long 0x00 "SHIFTBUFNIS2,Shifter Buffer 2 Nibble Swapped"
|
|
newline
|
|
group.long (0xC+0x680)++0x03
|
|
line.long 0x00 "SHIFTBUFNBS3,Shifter Buffer 3 Nibble Byte Swapped"
|
|
group.long (0xC+0x700)++0x03
|
|
line.long 0x00 "SHIFTBUFHWS3,Shifter Buffer 3 Half Word Swapped"
|
|
group.long (0xC+0x780)++0x03
|
|
line.long 0x00 "SHIFTBUFNIS3,Shifter Buffer 3 Nibble Swapped"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif cpuis("MKL16*")||cpuis("MKL26*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")
|
|
tree "I2S (Integrated Interchip Sound)"
|
|
base ad:0x4002F000
|
|
width 8.
|
|
group.long 0x00++0x03 "Transmit Control"
|
|
line.long 0x00 "TCSR,SAI Transmit Control Register"
|
|
bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " FR ,FIFO reset" "No reset,Reset"
|
|
bitfld.long 0x00 24. " SR ,Software reset" "No reset,Reset"
|
|
newline
|
|
eventfld.long 0x00 20. " WSF ,Word start flag" "Not started,Started"
|
|
eventfld.long 0x00 19. " SEF ,Sync error flag" "No error,Error"
|
|
eventfld.long 0x00 18. " FEF ,FIFO error flag" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x00 17. " FWF ,FIFO empty warning flag" "Not empty,Empty"
|
|
sif cpuis("MKL28Z*")
|
|
rbitfld.long 0x00 16. " FRF ,FIFO request Flag" "Not occurred,Occurred"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled"
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled"
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL28Z*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TCR_1,SAI Transmit Configuration 1 Register"
|
|
bitfld.long 0x00 0.--1. " TFW ,Transmit FIFO watermark" "0,1,2,3"
|
|
endif
|
|
if (((per.l(ad:0x4002F000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TCR_2,SAI Transmit Configuration 2 Register"
|
|
bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Async.,Sync. With rx,Sync. With SAI tx,Sync. With SAI rx"
|
|
bitfld.long 0x00 29. " BCS ,Bit clock swap" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal logic clocked"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " MSEL ,Master clock select" "Bus clock,I2S0_MCLK,?..."
|
|
bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low"
|
|
bitfld.long 0x00 24. " BCD ,Bit clock direction" "External,Internal"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TCR_2,SAI Transmit Configuration 2 Register"
|
|
bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Async.,Sync. With rx,Sync. With SAI tx,Sync. With SAI rx"
|
|
bitfld.long 0x00 29. " BCS ,Bit clock swap" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal logic clocked"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " MSEL ,Master clock select" "Bus clock,I2S0_MCLK,?..."
|
|
bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low"
|
|
bitfld.long 0x00 24. " BCD ,Bit clock direction" "External,Internal"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide"
|
|
endif
|
|
group.long 0x0C++0x0B
|
|
line.long 0x00 "TCR_3,SAI Transmit Configuration 3 Register"
|
|
bitfld.long 0x00 16. " TCE ,Transmit channel enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.long 0x00 0.--3. " WDFL ,Word flag configuration" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
else
|
|
bitfld.long 0x00 0. " WDFL ,World flag configuration" "First,Second"
|
|
endif
|
|
if (((per.l(ad:0x4002F000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x10++0x07
|
|
line.long 0x00 "TCR_4,SAI Transmit Configuration 4 Register"
|
|
sif cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MKL28Z*")
|
|
bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Next frame,Same word"
|
|
bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit FIFO,16-bit FIFO"
|
|
newline
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.long 0x00 16.--19. " FRSZ ,Frame size" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
else
|
|
bitfld.long 0x00 16. " FRSZ ,Frame size" "One word,Two words"
|
|
endif
|
|
else
|
|
bitfld.long 0x00 16. " FRSZ ,Frame size" "One word,Two words"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 8.--12. " SYWD ,Sync width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4. " MF ,Specify whether the LSB or the MSB is transmitted first" "LSB,MSB"
|
|
bitfld.long 0x00 3. " FSE ,Frame sync assertion" "With first,Before first"
|
|
newline
|
|
sif cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MKL28Z*")
|
|
bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,FIFO wrn. Flag clr"
|
|
bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " FSD ,Frame sync direction" "External,Internal"
|
|
else
|
|
bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " FSD ,Frame sync direction" "External,Internal"
|
|
endif
|
|
line.long 0x04 "TCR_5,SAI Transmit Configuration 5 Register"
|
|
bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 16.--20. " W0W ,Word 0 width" ",,,,,,,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "TCR_4,SAI Transmit Configuration 4 Register"
|
|
sif cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MKL28Z*")
|
|
bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Next frame,Same word"
|
|
bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit FIFO,16-bit FIFO"
|
|
newline
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.long 0x00 16.--19. " FRSZ ,Frame size" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
else
|
|
bitfld.long 0x00 16. " FRSZ ,Frame size" "One word,Two words"
|
|
endif
|
|
else
|
|
bitfld.long 0x00 16. " FRSZ ,Frame size" "One word,Two words"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 8.--12. " SYWD ,Sync width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4. " MF ,Specify whether the LSB or the MSB is transmitted first" "LSB,MSB"
|
|
bitfld.long 0x00 3. " FSE ,Frame sync assertion" "With first,Before first"
|
|
newline
|
|
sif cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MKL28Z*")
|
|
bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,FIFO wrn. Flag clr"
|
|
bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " FSD ,Frame sync direction" "External,Internal"
|
|
else
|
|
bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " FSD ,Frame sync direction" "External,Internal"
|
|
endif
|
|
line.long 0x04 "TCR_5,SAI Transmit Configuration 5 Register"
|
|
bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 16.--20. " W0W ,Word 0 width" ",,,,,,,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "TDR_0,SAI Transmit Data 0 Register"
|
|
sif cpuis("MKL28Z*")
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "TFR_0,SAI Transmit FIFO 0 Register"
|
|
bitfld.long 0x00 16.--18. " WFP ,Write FIFO pointer" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TMR,SAI Transmit Mask Register"
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.long 0x00 15. " TWM_15 ,Transmit word mask 15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " TWM_14 ,Transmit word mask 14" "Not masked,Masked"
|
|
bitfld.long 0x00 13. " TWM_13 ,Transmit word mask 13" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 12. " TWM_12 ,Transmit word mask 12" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " TWM_11 ,Transmit word mask 11" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " TWM_10 ,Transmit word mask 10" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 9. " TWM_9 ,Transmit word mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " TWM_8 ,Transmit word mask 8" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " TWM_7 ,Transmit word mask 7" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 6. " TWM_6 ,Transmit word mask 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " TWM_5 ,Transmit word mask 5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " TWM_4 ,Transmit word mask 4" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 3. " TWM_3 ,Transmit word mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " TWM_2 ,Transmit word mask 2" "Not masked,Masked"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " TWM_1 ,Transmit word mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " TWM_0 ,Transmit word mask 0" "Not masked,Masked"
|
|
group.long 0x80++0x03 "Receive Control"
|
|
line.long 0x00 "RCSR,SAI Receive Control Register"
|
|
bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " FR ,FIFO reset" "No reset,Reset"
|
|
bitfld.long 0x00 24. " SR ,Software reset" "No reset,Reset"
|
|
newline
|
|
eventfld.long 0x00 20. " WSF ,Word start flag" "Not started,Started"
|
|
eventfld.long 0x00 19. " SEF ,Sync error flag" "No error,Error"
|
|
eventfld.long 0x00 18. " FEF ,FIFO error flag" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x00 17. " FWF ,FIFO warning flag" "Not full,Full"
|
|
sif cpuis("MKL28Z*")
|
|
newline
|
|
rbitfld.long 0x00 16. " FRF ,FIFO request flag" "Not reached,Reached"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled"
|
|
sif cpuis("MKL28Z*")
|
|
newline
|
|
bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "RCR_2,SAI Receive Configuration 2 Register"
|
|
bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Async.,Sync. With rx,Sync. With SAI tx,Sync. With SAI rx"
|
|
bitfld.long 0x00 29. " BCS ,Bit clock swap" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal logic clocked"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " MSEL ,Master clock select" "Bus clock,I2S0_MCLK,?..."
|
|
bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low"
|
|
bitfld.long 0x00 24. " BCD ,Bit clock direction" "External,Internal"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide"
|
|
group.long 0x8C++0x0B
|
|
line.long 0x00 "RCR_3,SAI Receive Configuration 3 Register"
|
|
bitfld.long 0x00 16. " RCE ,Receive channel enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.long 0x00 0.--3. " WDFL ,Word flag configuration" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
else
|
|
bitfld.long 0x00 0. " WDFL ,World flag configuration" "First,Second"
|
|
endif
|
|
line.long 0x04 "RCR_4,SAI Receive Configuration 4 Register"
|
|
sif cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MKL28Z*")
|
|
bitfld.long 0x04 28. " FCONT ,FIFO continue on error" "Next frame,Same word"
|
|
bitfld.long 0x04 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit FIFO,16-bit FIFO"
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.long 0x04 16.--19. " FRSZ ,Frame size" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
else
|
|
bitfld.long 0x04 16. " FRSZ ,Frame size" "One word,Two words"
|
|
endif
|
|
else
|
|
bitfld.long 0x04 16. " FRSZ ,Frame size" "One word,Two words"
|
|
endif
|
|
newline
|
|
bitfld.long 0x04 8.--12. " SYWD ,Sync width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 4. " MF ,Specify whether the LSB or the MSB is transmitted first" "LSB,MSB"
|
|
bitfld.long 0x04 3. " FSE ,Frame sync assertion" "With first,Before first"
|
|
newline
|
|
sif cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MKL28Z*")
|
|
bitfld.long 0x04 2. " ONDEM ,On demand mode" "Continuously,FIFO wrn. Flag clr"
|
|
bitfld.long 0x04 1. " FSP ,Frame sync polarity" "Active high,Active low"
|
|
bitfld.long 0x04 0. " FSD ,Frame sync direction" "External,Internal"
|
|
else
|
|
bitfld.long 0x04 1. " FSP ,Frame sync polarity" "Active high,Active low"
|
|
bitfld.long 0x04 0. " FSD ,Frame sync direction" "External,Internal"
|
|
endif
|
|
line.long 0x08 "RCR_5,SAI Receive Configuration 5 Register"
|
|
bitfld.long 0x08 24.--28. " WNW ,Word N width" ",,,,,,,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 16.--20. " W0W ,Word 0 width" ",,,,,,,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("MKL17Z*")||cpuis("MKL26Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MKL28Z*")
|
|
hgroup.long 0xA0++0x03
|
|
hide.long 0x00 "RDR_0,SAI Receive Data 0 Register"
|
|
in
|
|
else
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "RDR_0,SAI Receive Data 0 Register"
|
|
endif
|
|
sif cpuis("MKL28Z*")
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "RFR_0,SAI Receive FIFO Register"
|
|
bitfld.long 0x00 16.--18. " WFP ,Write FIFO Pointer" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "RMR,SAI Receive Mask Register"
|
|
bitfld.long 0x00 1. " RWM_1 ,Receive word mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " RWM_0 ,Receive word mask 0" "Not masked,Masked"
|
|
sif cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")
|
|
if (((per.l(ad:0x4002F000+0x100)&0x40000000))==0x40000000)
|
|
group.long 0x100++0x03 "MCLK Control"
|
|
line.long 0x00 "MCR,SAI MCLK Control Register"
|
|
rbitfld.long 0x00 31. " DUF ,Divider update flag" "Not updating,Updating"
|
|
bitfld.long 0x00 30. " MOE ,MCLK output enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MICS ,MCLK input clock select" "System clock,OSCERCLK,MCGIRCLK,MCGPCLK"
|
|
else
|
|
group.long 0x100++0x03 "MCLK Control"
|
|
line.long 0x00 "MCR,SAI MCLK Control Register"
|
|
rbitfld.long 0x00 31. " DUF ,Divider update flag" "Not updating,Updating"
|
|
bitfld.long 0x00 30. " MOE ,MCLK output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MICS ,MCLK input clock select" "System clock,OSCERCLK,MCGIRCLK,MCGPCLK"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4002F000+0x100)&0x40000000))==0x40000000)
|
|
group.long 0x100++0x07 "MCLK Control"
|
|
line.long 0x00 "MCR,SAI MCLK Control Register"
|
|
rbitfld.long 0x00 31. " DUF ,Divider update flag" "Not updating,Updating"
|
|
bitfld.long 0x00 30. " MOE ,MCLK output enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MICS ,MCLK input clock select" "System clock,OSCERCLK,,MCGPLLCLK/2 or MCGFLLCLK"
|
|
line.long 0x04 "MDR,SAI MCLK Divide Register"
|
|
hexmask.long.byte 0x04 12.--19. 1. " FRACT ,MCLK fraction"
|
|
hexmask.long.word 0x04 0.--11. 1. " DIVIDE ,MCLK divide"
|
|
else
|
|
group.long 0x100++0x07 "MCLK Control"
|
|
line.long 0x00 "MCR,SAI MCLK Control Register"
|
|
rbitfld.long 0x00 31. " DUF ,Divider update flag" "Not updating,Updating"
|
|
bitfld.long 0x00 30. " MOE ,MCLK output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MICS ,MCLK input clock select" "System clock,OSCERCLK,,MCGPLLCLK/2 or MCGFLLCLK"
|
|
line.long 0x04 "MDR,SAI MCLK Divide Register"
|
|
hexmask.long.byte 0x04 12.--19. 1. " FRACT ,MCLK fraction"
|
|
hexmask.long.word 0x04 0.--11. 1. " DIVIDE ,MCLK divide"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
elif cpuis("MKL17Z128*")||cpuis("MKL17Z256*")||cpuis("MKL27Z128*")||cpuis("MKL27Z256*")||cpuis("MKL33Z128*")||cpuis("MKL33Z256*")||cpuis("MKL43Z*")||cpuis("MKL28Z*")
|
|
tree "SAI (I2S) (Synchronous Audio Interface)"
|
|
base ad:0x4002F000
|
|
width 8.
|
|
group.long 0x00++0x03 "Transmit Control"
|
|
line.long 0x00 "TCSR,SAI Transmit Control Register"
|
|
bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " FR ,FIFO reset" "No reset,Reset"
|
|
bitfld.long 0x00 24. " SR ,Software reset" "No reset,Reset"
|
|
newline
|
|
eventfld.long 0x00 20. " WSF ,Word start flag" "Not started,Started"
|
|
eventfld.long 0x00 19. " SEF ,Sync error flag" "No error,Error"
|
|
eventfld.long 0x00 18. " FEF ,FIFO error flag" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x00 17. " FWF ,FIFO empty warning flag" "Not empty,Empty"
|
|
sif cpuis("MKL28Z*")
|
|
rbitfld.long 0x00 16. " FRF ,FIFO request Flag" "Not occurred,Occurred"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled"
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled"
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif cpuis("MKL28Z*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TCR_1,SAI Transmit Configuration 1 Register"
|
|
bitfld.long 0x00 0.--1. " TFW ,Transmit FIFO watermark" "0,1,2,3"
|
|
endif
|
|
if (((per.l(ad:0x4002F000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TCR_2,SAI Transmit Configuration 2 Register"
|
|
bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Async.,Sync. With rx,Sync. With SAI tx,Sync. With SAI rx"
|
|
bitfld.long 0x00 29. " BCS ,Bit clock swap" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal logic clocked"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " MSEL ,Master clock select" "Bus clock,I2S0_MCLK,?..."
|
|
bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low"
|
|
bitfld.long 0x00 24. " BCD ,Bit clock direction" "External,Internal"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TCR_2,SAI Transmit Configuration 2 Register"
|
|
bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Async.,Sync. With rx,Sync. With SAI tx,Sync. With SAI rx"
|
|
bitfld.long 0x00 29. " BCS ,Bit clock swap" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal logic clocked"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " MSEL ,Master clock select" "Bus clock,I2S0_MCLK,?..."
|
|
bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low"
|
|
bitfld.long 0x00 24. " BCD ,Bit clock direction" "External,Internal"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide"
|
|
endif
|
|
group.long 0x0C++0x0B
|
|
line.long 0x00 "TCR_3,SAI Transmit Configuration 3 Register"
|
|
bitfld.long 0x00 16. " TCE ,Transmit channel enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.long 0x00 0.--3. " WDFL ,Word flag configuration" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
else
|
|
bitfld.long 0x00 0. " WDFL ,World flag configuration" "First,Second"
|
|
endif
|
|
if (((per.l(ad:0x4002F000))&0x80000000)==0x80000000)
|
|
rgroup.long 0x10++0x07
|
|
line.long 0x00 "TCR_4,SAI Transmit Configuration 4 Register"
|
|
sif cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MKL28Z*")
|
|
bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Next frame,Same word"
|
|
bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit FIFO,16-bit FIFO"
|
|
newline
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.long 0x00 16.--19. " FRSZ ,Frame size" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
else
|
|
bitfld.long 0x00 16. " FRSZ ,Frame size" "One word,Two words"
|
|
endif
|
|
else
|
|
bitfld.long 0x00 16. " FRSZ ,Frame size" "One word,Two words"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 8.--12. " SYWD ,Sync width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4. " MF ,Specify whether the LSB or the MSB is transmitted first" "LSB,MSB"
|
|
bitfld.long 0x00 3. " FSE ,Frame sync assertion" "With first,Before first"
|
|
newline
|
|
sif cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MKL28Z*")
|
|
bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,FIFO wrn. Flag clr"
|
|
bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " FSD ,Frame sync direction" "External,Internal"
|
|
else
|
|
bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " FSD ,Frame sync direction" "External,Internal"
|
|
endif
|
|
line.long 0x04 "TCR_5,SAI Transmit Configuration 5 Register"
|
|
bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 16.--20. " W0W ,Word 0 width" ",,,,,,,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "TCR_4,SAI Transmit Configuration 4 Register"
|
|
sif cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MKL28Z*")
|
|
bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Next frame,Same word"
|
|
bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit FIFO,16-bit FIFO"
|
|
newline
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.long 0x00 16.--19. " FRSZ ,Frame size" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
else
|
|
bitfld.long 0x00 16. " FRSZ ,Frame size" "One word,Two words"
|
|
endif
|
|
else
|
|
bitfld.long 0x00 16. " FRSZ ,Frame size" "One word,Two words"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 8.--12. " SYWD ,Sync width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4. " MF ,Specify whether the LSB or the MSB is transmitted first" "LSB,MSB"
|
|
bitfld.long 0x00 3. " FSE ,Frame sync assertion" "With first,Before first"
|
|
newline
|
|
sif cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MKL28Z*")
|
|
bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,FIFO wrn. Flag clr"
|
|
bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " FSD ,Frame sync direction" "External,Internal"
|
|
else
|
|
bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " FSD ,Frame sync direction" "External,Internal"
|
|
endif
|
|
line.long 0x04 "TCR_5,SAI Transmit Configuration 5 Register"
|
|
bitfld.long 0x04 24.--28. " WNW ,Word N width" ",,,,,,,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 16.--20. " W0W ,Word 0 width" ",,,,,,,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "TDR_0,SAI Transmit Data 0 Register"
|
|
sif cpuis("MKL28Z*")
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "TFR_0,SAI Transmit FIFO 0 Register"
|
|
bitfld.long 0x00 16.--18. " WFP ,Write FIFO pointer" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TMR,SAI Transmit Mask Register"
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.long 0x00 15. " TWM_15 ,Transmit word mask 15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " TWM_14 ,Transmit word mask 14" "Not masked,Masked"
|
|
bitfld.long 0x00 13. " TWM_13 ,Transmit word mask 13" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 12. " TWM_12 ,Transmit word mask 12" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " TWM_11 ,Transmit word mask 11" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " TWM_10 ,Transmit word mask 10" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 9. " TWM_9 ,Transmit word mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " TWM_8 ,Transmit word mask 8" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " TWM_7 ,Transmit word mask 7" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 6. " TWM_6 ,Transmit word mask 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " TWM_5 ,Transmit word mask 5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " TWM_4 ,Transmit word mask 4" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 3. " TWM_3 ,Transmit word mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " TWM_2 ,Transmit word mask 2" "Not masked,Masked"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " TWM_1 ,Transmit word mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " TWM_0 ,Transmit word mask 0" "Not masked,Masked"
|
|
group.long 0x80++0x03 "Receive Control"
|
|
line.long 0x00 "RCSR,SAI Receive Control Register"
|
|
bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " FR ,FIFO reset" "No reset,Reset"
|
|
bitfld.long 0x00 24. " SR ,Software reset" "No reset,Reset"
|
|
newline
|
|
eventfld.long 0x00 20. " WSF ,Word start flag" "Not started,Started"
|
|
eventfld.long 0x00 19. " SEF ,Sync error flag" "No error,Error"
|
|
eventfld.long 0x00 18. " FEF ,FIFO error flag" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x00 17. " FWF ,FIFO warning flag" "Not full,Full"
|
|
sif cpuis("MKL28Z*")
|
|
newline
|
|
rbitfld.long 0x00 16. " FRF ,FIFO request flag" "Not reached,Reached"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled"
|
|
sif cpuis("MKL28Z*")
|
|
newline
|
|
bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "RCR_2,SAI Receive Configuration 2 Register"
|
|
bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Async.,Sync. With rx,Sync. With SAI tx,Sync. With SAI rx"
|
|
bitfld.long 0x00 29. " BCS ,Bit clock swap" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,Internal logic clocked"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " MSEL ,Master clock select" "Bus clock,I2S0_MCLK,?..."
|
|
bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low"
|
|
bitfld.long 0x00 24. " BCD ,Bit clock direction" "External,Internal"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide"
|
|
group.long 0x8C++0x0B
|
|
line.long 0x00 "RCR_3,SAI Receive Configuration 3 Register"
|
|
bitfld.long 0x00 16. " RCE ,Receive channel enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.long 0x00 0.--3. " WDFL ,Word flag configuration" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
else
|
|
bitfld.long 0x00 0. " WDFL ,World flag configuration" "First,Second"
|
|
endif
|
|
line.long 0x04 "RCR_4,SAI Receive Configuration 4 Register"
|
|
sif cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MKL28Z*")
|
|
bitfld.long 0x04 28. " FCONT ,FIFO continue on error" "Next frame,Same word"
|
|
bitfld.long 0x04 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit FIFO,16-bit FIFO"
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.long 0x04 16.--19. " FRSZ ,Frame size" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
else
|
|
bitfld.long 0x04 16. " FRSZ ,Frame size" "One word,Two words"
|
|
endif
|
|
else
|
|
bitfld.long 0x04 16. " FRSZ ,Frame size" "One word,Two words"
|
|
endif
|
|
newline
|
|
bitfld.long 0x04 8.--12. " SYWD ,Sync width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 4. " MF ,Specify whether the LSB or the MSB is transmitted first" "LSB,MSB"
|
|
bitfld.long 0x04 3. " FSE ,Frame sync assertion" "With first,Before first"
|
|
newline
|
|
sif cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MKL28Z*")
|
|
bitfld.long 0x04 2. " ONDEM ,On demand mode" "Continuously,FIFO wrn. Flag clr"
|
|
bitfld.long 0x04 1. " FSP ,Frame sync polarity" "Active high,Active low"
|
|
bitfld.long 0x04 0. " FSD ,Frame sync direction" "External,Internal"
|
|
else
|
|
bitfld.long 0x04 1. " FSP ,Frame sync polarity" "Active high,Active low"
|
|
bitfld.long 0x04 0. " FSD ,Frame sync direction" "External,Internal"
|
|
endif
|
|
line.long 0x08 "RCR_5,SAI Receive Configuration 5 Register"
|
|
bitfld.long 0x08 24.--28. " WNW ,Word N width" ",,,,,,,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 16.--20. " W0W ,Word 0 width" ",,,,,,,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("MKL17Z*")||cpuis("MKL26Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MKL28Z*")
|
|
hgroup.long 0xA0++0x03
|
|
hide.long 0x00 "RDR_0,SAI Receive Data 0 Register"
|
|
in
|
|
else
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "RDR_0,SAI Receive Data 0 Register"
|
|
endif
|
|
sif cpuis("MKL28Z*")
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "RFR_0,SAI Receive FIFO Register"
|
|
bitfld.long 0x00 16.--18. " WFP ,Write FIFO Pointer" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "RMR,SAI Receive Mask Register"
|
|
bitfld.long 0x00 1. " RWM_1 ,Receive word mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " RWM_0 ,Receive word mask 0" "Not masked,Masked"
|
|
sif cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")
|
|
if (((per.l(ad:0x4002F000+0x100)&0x40000000))==0x40000000)
|
|
group.long 0x100++0x03 "MCLK Control"
|
|
line.long 0x00 "MCR,SAI MCLK Control Register"
|
|
rbitfld.long 0x00 31. " DUF ,Divider update flag" "Not updating,Updating"
|
|
bitfld.long 0x00 30. " MOE ,MCLK output enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MICS ,MCLK input clock select" "System clock,OSCERCLK,MCGIRCLK,MCGPCLK"
|
|
else
|
|
group.long 0x100++0x03 "MCLK Control"
|
|
line.long 0x00 "MCR,SAI MCLK Control Register"
|
|
rbitfld.long 0x00 31. " DUF ,Divider update flag" "Not updating,Updating"
|
|
bitfld.long 0x00 30. " MOE ,MCLK output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MICS ,MCLK input clock select" "System clock,OSCERCLK,MCGIRCLK,MCGPCLK"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4002F000+0x100)&0x40000000))==0x40000000)
|
|
group.long 0x100++0x07 "MCLK Control"
|
|
line.long 0x00 "MCR,SAI MCLK Control Register"
|
|
rbitfld.long 0x00 31. " DUF ,Divider update flag" "Not updating,Updating"
|
|
bitfld.long 0x00 30. " MOE ,MCLK output enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MICS ,MCLK input clock select" "System clock,OSCERCLK,,MCGPLLCLK/2 or MCGFLLCLK"
|
|
line.long 0x04 "MDR,SAI MCLK Divide Register"
|
|
hexmask.long.byte 0x04 12.--19. 1. " FRACT ,MCLK fraction"
|
|
hexmask.long.word 0x04 0.--11. 1. " DIVIDE ,MCLK divide"
|
|
else
|
|
group.long 0x100++0x07 "MCLK Control"
|
|
line.long 0x00 "MCR,SAI MCLK Control Register"
|
|
rbitfld.long 0x00 31. " DUF ,Divider update flag" "Not updating,Updating"
|
|
bitfld.long 0x00 30. " MOE ,MCLK output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MICS ,MCLK input clock select" "System clock,OSCERCLK,,MCGPLLCLK/2 or MCGFLLCLK"
|
|
line.long 0x04 "MDR,SAI MCLK Divide Register"
|
|
hexmask.long.byte 0x04 12.--19. 1. " FRACT ,MCLK fraction"
|
|
hexmask.long.word 0x04 0.--11. 1. " DIVIDE ,MCLK divide"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.open "GPIO (General-Purpose Input/Output)"
|
|
base ad:0x400FF000
|
|
sif cpuis("MKL02Z*")||cpuis("MKL03Z*")||cpuis("MKL04Z*")||cpuis("MKL05Z*")
|
|
width 12.
|
|
sif cpuis("MKL*VFG*")
|
|
width 14.
|
|
tree "GPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "GPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "GPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "GPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL*CAF*")||cpuis("KKL*AF*")
|
|
width 14.
|
|
tree "GPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "GPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "GPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "GPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL*VFK*")
|
|
width 14.
|
|
tree "GPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "GPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "GPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "GPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL*VLC*")||cpuis("MKL*VFM*")
|
|
width 14.
|
|
tree "GPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "GPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "GPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "GPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL*VLF*")
|
|
width 14.
|
|
tree "GPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PDO[14]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "GPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 15. " PTTO[15] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " PTTO[14] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 15. " PDI[15] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 14. " PDI[14] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 15. " PDD[15] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 14. " PDD[14] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PDO[14]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "GPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 15. " PTTO[15] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 14. " PTTO[14] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "GPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 15. " PDI[15] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 14. " PDI[14] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 15. " PDD[15] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 14. " PDD[14] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
endif
|
|
width 0x0B
|
|
elif cpuis("MKL13Z*")||cpuis("MKL14Z*")||cpuis("MK14LN*")||cpuis("MKL15Z*")||cpuis("MK15LN*")||cpuis("MKL16Z*")||cpuis("MKL17Z*")||cpuis("KKL15*")
|
|
width 12.
|
|
sif cpuis("MK?1*VFM*")
|
|
width 14.
|
|
tree "GPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "GPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "GPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "GPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "GPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "GPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "GPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "GPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "GPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "GPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "GPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "GPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "GPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "GPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "GPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MK?1*CAD*")
|
|
width 14.
|
|
tree "GPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "GPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "GPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "GPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "GPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "GPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "GPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "GPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "GPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "GPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "GPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "GPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "GPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " PTTO[29] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "GPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "GPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MK?1*VDA*")
|
|
width 14.
|
|
tree "GPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "GPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "GPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "GPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "GPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "GPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "GPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "GPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "GPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "GPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "GPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "GPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "GPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "GPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "GPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MK?1*VFT*")
|
|
width 14.
|
|
tree "GPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "GPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "GPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "GPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "GPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "GPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "GPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "GPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "GPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "GPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "GPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "GPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO[25]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "GPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " PTTO[29] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 25. " PTTO[25] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 24. " PTTO[24] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "GPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 25. " PDI[25] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 24. " PDI[24] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "GPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 25. " PDD[25] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 24. " PDD[24] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MK?1*VLH*")||cpuis("MKL?*VMP*")
|
|
width 14.
|
|
tree "GPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "GPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "GPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "GPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "GPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "GPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "GPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "GPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "GPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "GPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "GPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "GPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " PDO[31]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO[25]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "GPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 31. " PTTO[31] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " PTTO[29] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 25. " PTTO[25] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 24. " PTTO[24] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "GPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 31. " PDI[31] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 25. " PDI[25] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 24. " PDI[24] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "GPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 31. " PDD[31] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 25. " PDD[25] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 24. " PDD[24] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MK?1*VLK*")
|
|
width 14.
|
|
tree "GPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PDO[14]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "GPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 15. " PTTO[15] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 14. " PTTO[14] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 15. " PDI[15] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 14. " PDI[14] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 15. " PDD[15] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 14. " PDD[14] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "GPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "GPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "GPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "GPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "GPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "GPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "GPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "GPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "GPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "GPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " PDO[31]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO[25]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "GPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 31. " PTTO[31] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " PTTO[29] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 25. " PTTO[25] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 24. " PTTO[24] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "GPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 31. " PDI[31] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 25. " PDI[25] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 24. " PDI[24] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "GPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 31. " PDD[31] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 25. " PDD[25] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 24. " PDD[24] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
endif
|
|
width 0x0B
|
|
elif cpuis("MKL24Z*")||cpuis("MKL25Z*")||cpuis("MKL26Z*")||cpuis("MKL27Z*")||cpuis("MKL28Z*")
|
|
width 12.
|
|
sif cpuis("MKL*VFM*")
|
|
width 14.
|
|
tree "GPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "GPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "GPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "GPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "GPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "GPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "GPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "GPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "GPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "GPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "GPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_E"
|
|
sif cpuis("MKL27Z32*")||cpuis("MKL27Z64*")
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "GPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "GPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "GPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "GPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "GPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "GPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "GPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "GPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL*CAL*")
|
|
width 14.
|
|
tree "GPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "GPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "GPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "GPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "GPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "GPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "GPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "GPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "GPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "GPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "GPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "GPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "GPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "GPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "GPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL*VDA*")
|
|
width 14.
|
|
tree "GPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "GPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "GPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "GPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "GPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "GPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "GPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "GPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "GPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "GPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "GPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "GPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "GPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "GPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "GPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL*VFT*")
|
|
width 14.
|
|
tree "GPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "GPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "GPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "GPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "GPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "GPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "GPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "GPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "GPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "GPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "GPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_E"
|
|
sif cpuis("MKL27Z32*")||cpuis("MKL27Z64*")
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "GPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO[25]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "GPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " PTTO[29] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 25. " PTTO[25] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 24. " PTTO[24] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "GPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 25. " PDI[25] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 24. " PDI[24] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "GPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 25. " PDD[25] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 24. " PDD[24] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "GPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO[25]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "GPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " PTTO[29] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 25. " PTTO[25] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 24. " PTTO[24] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "GPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 25. " PDI[25] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 24. " PDI[24] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "GPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 25. " PDD[25] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 24. " PDD[24] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL*VLH*")||cpuis("MKL*VMP*")
|
|
width 14.
|
|
tree "GPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "GPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "GPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "GPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "GPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "GPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "GPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "GPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "GPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "GPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "GPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_E"
|
|
group.long 0x100++0x03
|
|
sif cpuis("MKL27Z32*")||cpuis("MKL27Z64*")
|
|
line.long 0x00 "GPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " PDO[31]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO[25]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
else
|
|
line.long 0x00 "GPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " PDO[31]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO[25]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
endif
|
|
wgroup.long 0x10C++0x03
|
|
sif cpuis("MKL27Z32*")||cpuis("MKL27Z64*")
|
|
line.long 0x00 "GPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 31. " PTTO[31] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " PTTO[29] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 25. " PTTO[25] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 24. " PTTO[24] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
else
|
|
line.long 0x00 "GPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 31. " PTTO[31] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " PTTO[29] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 25. " PTTO[25] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 24. " PTTO[24] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
endif
|
|
rgroup.long 0x110++0x03
|
|
sif cpuis("MKL27Z32*")||cpuis("MKL27Z64*")
|
|
line.long 0x00 "GPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 31. " PDI[31] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 25. " PDI[25] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 24. " PDI[24] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
else
|
|
line.long 0x00 "GPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 31. " PDI[31] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 25. " PDI[25] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 24. " PDI[24] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
endif
|
|
group.long 0x114++0x03
|
|
sif cpuis("MKL27Z32*")||cpuis("MKL27Z64*")
|
|
line.long 0x00 "GPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 31. " PDD[31] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 25. " PDD[25] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 24. " PDD[24] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
else
|
|
line.long 0x00 "GPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 31. " PDD[31] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 25. " PDD[25] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 24. " PDD[24] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL*VLK*")
|
|
width 14.
|
|
tree "GPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PDO[14]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "GPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 15. " PTTO[15] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 14. " PTTO[14] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 15. " PDI[15] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 14. " PDI[14] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 15. " PDD[15] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 14. " PDD[14] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "GPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "GPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "GPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "GPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "GPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "GPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "GPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "GPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "GPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "GPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " PDO[31]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO[25]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "GPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 31. " PTTO[31] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " PTTO[29] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 25. " PTTO[25] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 24. " PTTO[24] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "GPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 31. " PDI[31] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 25. " PDI[25] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 24. " PDI[24] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "GPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 31. " PDD[31] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 25. " PDD[25] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 24. " PDD[24] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL*VLL*")||cpuis("MKL*VMC*")||cpuis("MKL*VDC*")
|
|
width 14.
|
|
tree "GPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PDO[14]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
sif cpuis("MKL28Z*VDC*")
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "GPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 15. " PTTO[15] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 14. " PTTO[14] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
sif cpuis("MKL28Z*VDC*")
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 15. " PDI[15] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 14. " PDI[14] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
newline
|
|
sif cpuis("MKL28Z*VDC*")
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 15. " PDD[15] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 14. " PDD[14] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
newline
|
|
sif cpuis("MKL28Z*VDC*")
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
sif cpuis("MKL28Z*VDC*")
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "GPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
sif cpuis("MKL28Z*VDC*")
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "GPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
sif cpuis("MKL28Z*VDC*")
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
sif cpuis("MKL28Z*VDC*")
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPIO_C_PDOR,Port Data Output Register"
|
|
sif (cpu()=="MKL26Z128VMC4")||(cpu()=="MKL26Z256VMC4")
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
elif cpuis("MKL28Z*VDC*")
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
sif cpuis("MKL28Z*")
|
|
newline
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15]_SET/CLR ,Port data output" "Low,High"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "GPIO_C_PTOR,Port Toggle Output Register"
|
|
sif (cpu()=="MKL26Z128VMC4")||(cpu()=="MKL26Z256VMC4")
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
elif cpuis("MKL28Z*VDC*")
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
sif cpuis("MKL28Z*")
|
|
newline
|
|
bitfld.long 0x00 15. " PTTO[15] ,Port toggle output" "No effect,Toggle"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "GPIO_C_PDIR,Port Data Input Register"
|
|
sif (cpu()=="MKL26Z128VMC4")||(cpu()=="MKL26Z256VMC4")
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
newline
|
|
elif cpuis("MKL28Z*VDC*")
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
sif cpuis("MKL28Z*")
|
|
newline
|
|
bitfld.long 0x00 15. " PDI[15] ,Port data input" "Low,High"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "GPIO_C_PDDR,Port Data Direction Register"
|
|
sif (cpu()=="MKL26Z128VMC4")||(cpu()=="MKL26Z256VMC4")
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
newline
|
|
elif cpuis("MKL28Z*VDC*")
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
sif cpuis("MKL28Z*")
|
|
newline
|
|
bitfld.long 0x00 15. " PDD[15] ,Port data direction" "Input,Output"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "GPIO_D_PDOR,Port Data Output Register"
|
|
sif cpuis("MKL28Z*VDC*")
|
|
setclrfld.long 0x00 15. 0x012 15. 0x00 15. " PDO[15]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 14. 0x012 14. 0x00 14. " PDO[14]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 13. 0x012 13. 0x00 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x012 12. 0x00 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x012 11. 0x00 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x012 10. 0x00 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x012 9. 0x00 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x012 8. 0x00 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "GPIO_D_PTOR,Port Toggle Output Register"
|
|
sif cpuis("MKL28Z*VDC*")
|
|
bitfld.long 0x00 15. " PTTO[15] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " PTTO[14] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "GPIO_D_PDIR,Port Data Input Register"
|
|
sif cpuis("MKL28Z*VDC*")
|
|
bitfld.long 0x00 15. " PDI[15] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 14. " PDI[14] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "GPIO_D_PDDR,Port Data Direction Register"
|
|
sif cpuis("MKL28Z*VDC*")
|
|
bitfld.long 0x00 15. " PDD[15] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 14. " PDD[14] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "GPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " PDO[31]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " PDO[26]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO[25]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "GPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 31. " PTTO[31] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " PTTO[29] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 26. " PTTO[26] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 25. " PTTO[25] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 24. " PTTO[24] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "GPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 31. " PDI[31] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 26. " PDI[26] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 25. " PDI[25] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 24. " PDI[24] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "GPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 31. " PDD[31] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 26. " PDD[26] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 25. " PDD[25] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 24. " PDD[24] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
endif
|
|
width 0x0B
|
|
elif cpuis("MKL33Z*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")
|
|
width 12.
|
|
sif cpuis("MKL*VLH*")||cpuis("MKL*VMP*")
|
|
width 13.
|
|
tree "GPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "GPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "GPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "GPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_C"
|
|
sif cpuis("MKL33Z*")
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "GPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "GPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "GPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "GPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "GPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "GPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
endif
|
|
tree.end
|
|
tree "GPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "GPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "GPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "GPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "GPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "GPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " PDO[31]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO[25]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[18]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "GPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 31. " PTTO[31] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " PTTO[29] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 25. " PTTO[25] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 24. " PTTO[24] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "GPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 31. " PDI[31] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 25. " PDI[25] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 24. " PDI[24] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "GPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 31. " PDD[31] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 25. " PDD[25] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 24. " PDD[24] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0xB
|
|
elif cpuis("MKL*VLL*")||cpuis("MKL*VMC*")
|
|
width 13.
|
|
tree "GPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PDO[14]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "GPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 15. " PTTO[15] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 14. " PTTO[14] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 15. " PDI[15] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 14. " PDI[14] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 15. " PDD[15] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 14. " PDD[14] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "GPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "GPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "GPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "GPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "GPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "GPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "GPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "GPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "GPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "GPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " PDO[31]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " PDO[26]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO[25]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "GPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 31. " PTTO[31] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " PTTO[29] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 26. " PTTO[26] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 25. " PTTO[25] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 24. " PTTO[24] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "GPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 31. " PDI[31] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 26. " PDI[26] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 25. " PDI[25] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 24. " PDI[24] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "GPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 31. " PDD[31] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 26. " PDD[26] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 25. " PDD[25] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 24. " PDD[24] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL*VFT*")
|
|
width 13.
|
|
tree "GPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "GPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "GPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "GPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "GPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "GPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "GPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "GPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "GPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "GPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "GPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "GPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[18]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "GPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " PTTO[29] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 24. " PTTO[24] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "GPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 24. " PDI[24] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "GPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 24. " PDD[24] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0xB
|
|
elif cpuis("MKL*VLK*")
|
|
width 13.
|
|
tree "GPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PDO[14]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "GPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 15. " PTTO[15] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 14. " PTTO[14] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 15. " PDI[15] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 14. " PDI[14] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 15. " PDD[15] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 14. " PDD[14] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "GPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "GPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "GPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "GPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "GPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "GPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "GPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "GPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "GPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "GPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " PDO[31]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "GPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 31. " PTTO[31] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " PTTO[29] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 24. " PTTO[24] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "GPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 31. " PDI[31] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 24. " PDI[24] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "GPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 31. " PDD[31] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 24. " PDD[24] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0xB
|
|
endif
|
|
width 0x0B
|
|
elif cpuis("MKL46Z*")||cpuis("MKL43Z*")
|
|
width 12.
|
|
sif cpuis("MKL*VLH*")||cpuis("MKL*VMP*")
|
|
width 13.
|
|
tree "GPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "GPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "GPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "GPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_C"
|
|
sif cpuis("MKL43Z*")
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "GPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "GPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "GPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "GPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "GPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "GPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
endif
|
|
tree.end
|
|
tree "GPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "GPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "GPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "GPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "GPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "GPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " PDO[31]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO[25]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "GPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 31. " PTTO[31] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " PTTO[29] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 25. " PTTO[25] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 24. " PTTO[24] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "GPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 31. " PDI[31] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 25. " PDI[25] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 24. " PDI[24] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "GPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 31. " PDD[31] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 25. " PDD[25] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 24. " PDD[24] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL*VLL*")||cpuis("MKL*VMC*")
|
|
width 13.
|
|
tree "GPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PDO[14]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "GPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 15. " PTTO[15] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 14. " PTTO[14] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 15. " PDI[15] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 14. " PDI[14] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 15. " PDD[15] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 14. " PDD[14] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "GPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "GPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "GPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "GPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "GPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "GPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "GPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "GPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "GPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "GPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " PDO[31]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " PDO[26]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO[25]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "GPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 31. " PTTO[31] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " PTTO[29] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 26. " PTTO[26] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 25. " PTTO[25] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 24. " PTTO[24] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "GPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 31. " PDI[31] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 26. " PDI[26] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 25. " PDI[25] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 24. " PDI[24] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "GPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 31. " PDD[31] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 26. " PDD[26] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 25. " PDD[25] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 24. " PDD[24] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
endif
|
|
width 0x0B
|
|
elif cpuis("MKL82Z*")
|
|
width 12.
|
|
sif cpuis("MKL*VLH*")||cpuis("MKL*VMP*")
|
|
width 13.
|
|
tree "GPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "GPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "GPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "GPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "GPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "GPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "GPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "GPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "GPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "GPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "GPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "GPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "GPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "GPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "GPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL*VLL*")||cpuis("MKL*VMC*")
|
|
width 13.
|
|
tree "GPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIO_A_PDOR,Port Data Output Register"
|
|
sif cpuis("MKL*VMC*")
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PDO[14]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
sif cpuis("MKL*VMC*")
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "GPIO_A_PTOR,Port Toggle Output Register"
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 29. " PTTO[29] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 15. " PTTO[15] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " PTTO[14] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIO_A_PDIR,Port Data Input Register"
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 29. " PDI[29] ,Port data input" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 15. " PDI[15] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 14. " PDI[14] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
newline
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIO_A_PDDR,Port Data Direction Register"
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 29. " PDD[29] ,Port data direction" "Input,Output"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 15. " PDD[15] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 14. " PDD[14] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
newline
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
sif cpuis("MKL*VMC*")
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "GPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "GPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
newline
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
newline
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPIO_C_PDOR,Port Data Output Register"
|
|
sif cpuis("MKL*VMC*")
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
sif cpuis("MKL*VMC*")
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PDO[14]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "GPIO_C_PTOR,Port Toggle Output Register"
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15. " PTTO[15] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " PTTO[14] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "GPIO_C_PDIR,Port Data Input Register"
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15. " PDI[15] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 14. " PDI[14] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "GPIO_C_PDDR,Port Data Direction Register"
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15. " PDD[15] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 14. " PDD[14] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "GPIO_D_PDOR,Port Data Output Register"
|
|
sif cpuis("MKL*VMC*")
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PDO[14]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "GPIO_D_PTOR,Port Toggle Output Register"
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 15. " PTTO[15] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " PTTO[14] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "GPIO_D_PDIR,Port Data Input Register"
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 15. " PDI[15] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 14. " PDI[14] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
endif
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "GPIO_D_PDDR,Port Data Direction Register"
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 15. " PDD[15] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 14. " PDD[14] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
endif
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "GPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "GPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "GPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[98] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "GPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL*VLK*")
|
|
width 13.
|
|
tree "GPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PDO[14]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "GPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 15. " PTTO[15] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " PTTO[14] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 15. " PDI[15] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 14. " PDI[14] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 15. " PDD[15] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 14. " PDD[14] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "GPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "GPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "GPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "GPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "GPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "GPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "GPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "GPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "GPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "GPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "GPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "GPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "GPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "GPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
tree.open "FGPIO (Fast General-Purpose Input/Output)"
|
|
sif cpuis("MKL02*")||cpuis("MKL03Z*")||cpuis("MKL16*")||cpuis("MKL26*")||cpuis("MKL33Z*")||cpuis("MKL82Z*")
|
|
base ad:0xF8000000
|
|
elif cpuis("MKL04*")||cpuis("MKL05*")||cpuis("MKL14*")||cpuis("MK14LN*")||cpuis("MKL15*")||cpuis("MK15LN*")||cpuis("MKL24*")||cpuis("MKL25*")||cpuis("KKL15*")
|
|
base ad:0xF80FF000
|
|
endif
|
|
sif cpuis("MKL02Z*")||cpuis("MKL03Z*")||cpuis("MKL04Z*")||cpuis("MKL05Z*")
|
|
width 12.
|
|
sif cpuis("MKL*VFG*")
|
|
width 14.
|
|
tree "FGPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FGPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "FGPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FGPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FGPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FGPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "FGPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FGPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FGPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL*CAF*")||cpuis("KKL*AF*")
|
|
width 14.
|
|
tree "FGPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FGPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "FGPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FGPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FGPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FGPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "FGPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FGPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FGPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL*VFK*")
|
|
width 14.
|
|
tree "FGPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FGPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "FGPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FGPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FGPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FGPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "FGPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FGPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FGPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL*VLC*")||cpuis("MKL*VFM*")
|
|
width 14.
|
|
tree "FGPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FGPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "FGPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FGPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FGPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FGPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "FGPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FGPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FGPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL*VLF*")
|
|
width 14.
|
|
tree "FGPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FGPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PDO[14]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "FGPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 15. " PTTO[15] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " PTTO[14] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FGPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 15. " PDI[15] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 14. " PDI[14] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FGPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 15. " PDD[15] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 14. " PDD[14] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FGPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PDO[14]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "FGPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 15. " PTTO[15] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 14. " PTTO[14] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FGPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 15. " PDI[15] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 14. " PDI[14] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FGPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 15. " PDD[15] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 14. " PDD[14] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
endif
|
|
width 0x0B
|
|
elif cpuis("MKL13Z*")||cpuis("MKL14Z*")||cpuis("MK14LN*")||cpuis("MKL15Z*")||cpuis("MK15LN*")||cpuis("MKL16Z*")||cpuis("MKL17Z*")
|
|
width 12.
|
|
sif cpuis("MK?1*VFM*")
|
|
width 14.
|
|
tree "FGPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FGPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "FGPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FGPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FGPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FGPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "FGPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FGPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FGPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FGPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "FGPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "FGPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "FGPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "FGPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "FGPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "FGPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "FGPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "FGPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "FGPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "FGPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "FGPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MK?1*CAD*")
|
|
width 14.
|
|
tree "FGPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FGPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "FGPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FGPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FGPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FGPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "FGPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FGPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FGPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FGPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "FGPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "FGPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "FGPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "FGPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "FGPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "FGPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "FGPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "FGPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "FGPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " PTTO[29] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "FGPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "FGPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MK?1*VDA*")
|
|
width 14.
|
|
tree "FGPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FGPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "FGPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FGPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FGPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FGPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "FGPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FGPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FGPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FGPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "FGPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "FGPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "FGPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "FGPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "FGPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "FGPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "FGPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "FGPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "FGPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "FGPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "FGPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MK?1*VFT*")
|
|
width 14.
|
|
tree "FGPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FGPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "FGPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FGPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FGPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FGPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "FGPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FGPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FGPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FGPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "FGPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "FGPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "FGPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "FGPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "FGPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "FGPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "FGPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "FGPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO[25]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "FGPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " PTTO[29] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 25. " PTTO[25] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 24. " PTTO[24] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "FGPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 25. " PDI[25] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 24. " PDI[24] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "FGPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 25. " PDD[25] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 24. " PDD[24] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MK?1*VLH*")||cpuis("MKL?*VMP*")
|
|
width 14.
|
|
tree "FGPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FGPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "FGPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FGPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FGPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FGPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "FGPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FGPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FGPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FGPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "FGPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "FGPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "FGPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "FGPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "FGPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "FGPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "FGPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "FGPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " PDO[31]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO[25]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "FGPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 31. " PTTO[31] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " PTTO[29] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 25. " PTTO[25] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 24. " PTTO[24] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "FGPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 31. " PDI[31] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 25. " PDI[25] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 24. " PDI[24] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "FGPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 31. " PDD[31] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 25. " PDD[25] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 24. " PDD[24] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MK?1*VLK*")
|
|
width 14.
|
|
tree "FGPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FGPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PDO[14]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "FGPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 15. " PTTO[15] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 14. " PTTO[14] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FGPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 15. " PDI[15] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 14. " PDI[14] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FGPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 15. " PDD[15] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 14. " PDD[14] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FGPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "FGPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FGPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FGPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FGPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "FGPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "FGPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "FGPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "FGPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "FGPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "FGPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "FGPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "FGPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " PDO[31]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO[25]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "FGPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 31. " PTTO[31] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " PTTO[29] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 25. " PTTO[25] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 24. " PTTO[24] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "FGPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 31. " PDI[31] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 25. " PDI[25] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 24. " PDI[24] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "FGPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 31. " PDD[31] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 25. " PDD[25] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 24. " PDD[24] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
endif
|
|
width 0x0B
|
|
elif cpuis("MKL24Z*")||cpuis("MKL25Z*")||cpuis("MKL26Z*")||cpuis("MKL27Z*")
|
|
width 12.
|
|
sif cpuis("MKL*VFM*")
|
|
width 14.
|
|
tree "FGPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FGPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "FGPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FGPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FGPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FGPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "FGPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FGPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FGPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FGPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "FGPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "FGPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "FGPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "FGPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "FGPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "FGPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "FGPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_E"
|
|
sif cpuis("MKL27Z32*")||cpuis("MKL27Z64*")
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "FGPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "FGPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "FGPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "FGPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "FGPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "FGPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "FGPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "FGPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL*CAL*")
|
|
width 14.
|
|
tree "FGPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FGPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "FGPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FGPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FGPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FGPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "FGPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FGPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FGPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FGPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "FGPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "FGPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "FGPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "FGPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "FGPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "FGPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "FGPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "FGPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "FGPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "FGPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "FGPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL*VDA*")
|
|
width 14.
|
|
tree "FGPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FGPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "FGPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FGPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FGPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FGPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "FGPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FGPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FGPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FGPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "FGPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "FGPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "FGPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "FGPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "FGPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "FGPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "FGPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "FGPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "FGPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "FGPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "FGPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL*VFT*")
|
|
width 14.
|
|
tree "FGPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FGPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "FGPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FGPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FGPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FGPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "FGPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FGPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FGPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FGPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "FGPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "FGPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "FGPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "FGPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "FGPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "FGPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "FGPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_E"
|
|
sif cpuis("MKL27Z32*")||cpuis("MKL27Z64*")
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "FGPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO[25]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "FGPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " PTTO[29] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 25. " PTTO[25] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 24. " PTTO[24] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "FGPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 25. " PDI[25] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 24. " PDI[24] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "FGPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 25. " PDD[25] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 24. " PDD[24] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "FGPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO[25]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "FGPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " PTTO[29] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 25. " PTTO[25] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 24. " PTTO[24] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "FGPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 25. " PDI[25] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 24. " PDI[24] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "FGPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 25. " PDD[25] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 24. " PDD[24] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL*VLH*")||cpuis("MKL*VMP*")
|
|
width 14.
|
|
tree "FGPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FGPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "FGPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FGPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FGPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FGPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "FGPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FGPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FGPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FGPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "FGPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "FGPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "FGPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "FGPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "FGPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "FGPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "FGPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_E"
|
|
group.long 0x100++0x03
|
|
sif cpuis("MKL27Z32*")||cpuis("MKL27Z64*")
|
|
line.long 0x00 "FGPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " PDO[31]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO[25]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
else
|
|
line.long 0x00 "FGPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " PDO[31]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO[25]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
endif
|
|
wgroup.long 0x10C++0x03
|
|
sif cpuis("MKL27Z32*")||cpuis("MKL27Z64*")
|
|
line.long 0x00 "FGPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 31. " PTTO[31] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " PTTO[29] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 25. " PTTO[25] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 24. " PTTO[24] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
else
|
|
line.long 0x00 "FGPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 31. " PTTO[31] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " PTTO[29] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 25. " PTTO[25] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 24. " PTTO[24] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
endif
|
|
rgroup.long 0x110++0x03
|
|
sif cpuis("MKL27Z32*")||cpuis("MKL27Z64*")
|
|
line.long 0x00 "FGPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 31. " PDI[31] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 25. " PDI[25] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 24. " PDI[24] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
else
|
|
line.long 0x00 "FGPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 31. " PDI[31] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 25. " PDI[25] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 24. " PDI[24] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
endif
|
|
group.long 0x114++0x03
|
|
sif cpuis("MKL27Z32*")||cpuis("MKL27Z64*")
|
|
line.long 0x00 "FGPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 31. " PDD[31] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 25. " PDD[25] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 24. " PDD[24] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
else
|
|
line.long 0x00 "FGPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 31. " PDD[31] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 25. " PDD[25] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 24. " PDD[24] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL*VLK*")
|
|
width 14.
|
|
tree "FGPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FGPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PDO[14]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "FGPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 15. " PTTO[15] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 14. " PTTO[14] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FGPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 15. " PDI[15] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 14. " PDI[14] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FGPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 15. " PDD[15] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 14. " PDD[14] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FGPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "FGPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FGPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FGPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FGPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "FGPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "FGPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "FGPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "FGPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "FGPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "FGPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "FGPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "FGPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " PDO[31]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO[25]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "FGPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 31. " PTTO[31] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " PTTO[29] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 25. " PTTO[25] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 24. " PTTO[24] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "FGPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 31. " PDI[31] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 25. " PDI[25] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 24. " PDI[24] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "FGPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 31. " PDD[31] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 25. " PDD[25] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 24. " PDD[24] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL*VLL*")||cpuis("MKL*VMC*")||cpuis("MKL*VDC*")
|
|
width 14.
|
|
tree "FGPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FGPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PDO[14]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
sif cpuis("MKL28Z*VDC*")
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "FGPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 15. " PTTO[15] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 14. " PTTO[14] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
sif cpuis("MKL28Z*VDC*")
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FGPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 15. " PDI[15] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 14. " PDI[14] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
newline
|
|
sif cpuis("MKL28Z*VDC*")
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FGPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 15. " PDD[15] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 14. " PDD[14] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
newline
|
|
sif cpuis("MKL28Z*VDC*")
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FGPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
sif cpuis("MKL28Z*VDC*")
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "FGPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
sif cpuis("MKL28Z*VDC*")
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FGPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
sif cpuis("MKL28Z*VDC*")
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FGPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
sif cpuis("MKL28Z*VDC*")
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FGPIO_C_PDOR,Port Data Output Register"
|
|
sif (cpu()=="MKL26Z128VMC4")||(cpu()=="MKL26Z256VMC4")
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
elif cpuis("MKL28Z*VDC*")
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
sif cpuis("MKL28Z*")
|
|
newline
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15]_SET/CLR ,Port data output" "Low,High"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "FGPIO_C_PTOR,Port Toggle Output Register"
|
|
sif (cpu()=="MKL26Z128VMC4")||(cpu()=="MKL26Z256VMC4")
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
elif cpuis("MKL28Z*VDC*")
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
sif cpuis("MKL28Z*")
|
|
newline
|
|
bitfld.long 0x00 15. " PTTO[15] ,Port toggle output" "No effect,Toggle"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "FGPIO_C_PDIR,Port Data Input Register"
|
|
sif (cpu()=="MKL26Z128VMC4")||(cpu()=="MKL26Z256VMC4")
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
newline
|
|
elif cpuis("MKL28Z*VDC*")
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
sif cpuis("MKL28Z*")
|
|
newline
|
|
bitfld.long 0x00 15. " PDI[15] ,Port data input" "Low,High"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "FGPIO_C_PDDR,Port Data Direction Register"
|
|
sif (cpu()=="MKL26Z128VMC4")||(cpu()=="MKL26Z256VMC4")
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
newline
|
|
elif cpuis("MKL28Z*VDC*")
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
sif cpuis("MKL28Z*")
|
|
newline
|
|
bitfld.long 0x00 15. " PDD[15] ,Port data direction" "Input,Output"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "FGPIO_D_PDOR,Port Data Output Register"
|
|
sif cpuis("MKL28Z*VDC*")
|
|
setclrfld.long 0x00 15. 0x012 15. 0x00 15. " PDO[15]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 14. 0x012 14. 0x00 14. " PDO[14]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 13. 0x012 13. 0x00 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x012 12. 0x00 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x012 11. 0x00 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x012 10. 0x00 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x012 9. 0x00 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x012 8. 0x00 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "FGPIO_D_PTOR,Port Toggle Output Register"
|
|
sif cpuis("MKL28Z*VDC*")
|
|
bitfld.long 0x00 15. " PTTO[15] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " PTTO[14] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "FGPIO_D_PDIR,Port Data Input Register"
|
|
sif cpuis("MKL28Z*VDC*")
|
|
bitfld.long 0x00 15. " PDI[15] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 14. " PDI[14] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "FGPIO_D_PDDR,Port Data Direction Register"
|
|
sif cpuis("MKL28Z*VDC*")
|
|
bitfld.long 0x00 15. " PDD[15] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 14. " PDD[14] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "FGPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " PDO[31]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " PDO[26]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO[25]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "FGPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 31. " PTTO[31] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " PTTO[29] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 26. " PTTO[26] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 25. " PTTO[25] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 24. " PTTO[24] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "FGPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 31. " PDI[31] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 26. " PDI[26] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 25. " PDI[25] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 24. " PDI[24] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "FGPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 31. " PDD[31] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 26. " PDD[26] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 25. " PDD[25] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 24. " PDD[24] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
endif
|
|
width 0x0B
|
|
elif cpuis("MKL33Z*")||cpuis("MKL34Z*")||cpuis("MKL36Z*")
|
|
width 12.
|
|
sif cpuis("MKL*VLH*")||cpuis("MKL*VMP*")
|
|
width 13.
|
|
tree "FGPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FGPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "FGPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FGPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FGPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FGPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "FGPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FGPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FGPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_C"
|
|
sif cpuis("MKL33Z*")
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FGPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "FGPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "FGPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "FGPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FGPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "FGPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "FGPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "FGPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
endif
|
|
tree.end
|
|
tree "FGPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "FGPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "FGPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "FGPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "FGPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "FGPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " PDO[31]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO[25]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[18]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "FGPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 31. " PTTO[31] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " PTTO[29] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 25. " PTTO[25] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 24. " PTTO[24] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "FGPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 31. " PDI[31] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 25. " PDI[25] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 24. " PDI[24] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "FGPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 31. " PDD[31] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 25. " PDD[25] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 24. " PDD[24] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0xB
|
|
elif cpuis("MKL*VLL*")||cpuis("MKL*VMC*")
|
|
width 13.
|
|
tree "FGPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FGPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PDO[14]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "FGPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 15. " PTTO[15] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 14. " PTTO[14] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FGPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 15. " PDI[15] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 14. " PDI[14] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FGPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 15. " PDD[15] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 14. " PDD[14] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FGPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "FGPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FGPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FGPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FGPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "FGPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "FGPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "FGPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "FGPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "FGPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "FGPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "FGPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "FGPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " PDO[31]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " PDO[26]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO[25]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "FGPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 31. " PTTO[31] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " PTTO[29] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 26. " PTTO[26] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 25. " PTTO[25] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 24. " PTTO[24] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "FGPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 31. " PDI[31] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 26. " PDI[26] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 25. " PDI[25] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 24. " PDI[24] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "FGPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 31. " PDD[31] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 26. " PDD[26] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 25. " PDD[25] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 24. " PDD[24] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL*VFT*")
|
|
width 13.
|
|
tree "FGPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FGPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "FGPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FGPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FGPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FGPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "FGPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FGPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FGPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FGPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "FGPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "FGPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "FGPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "FGPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "FGPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "FGPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "FGPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "FGPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[18]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "FGPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " PTTO[29] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 24. " PTTO[24] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "FGPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 24. " PDI[24] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "FGPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 24. " PDD[24] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0xB
|
|
elif cpuis("MKL*VLK*")
|
|
width 13.
|
|
tree "FGPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FGPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PDO[14]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "FGPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 15. " PTTO[15] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 14. " PTTO[14] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FGPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 15. " PDI[15] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 14. " PDI[14] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FGPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 15. " PDD[15] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 14. " PDD[14] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FGPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "FGPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FGPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FGPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FGPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "FGPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "FGPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "FGPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "FGPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "FGPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "FGPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "FGPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "FGPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " PDO[31]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "FGPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 31. " PTTO[31] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " PTTO[29] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 24. " PTTO[24] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "FGPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 31. " PDI[31] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 24. " PDI[24] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "FGPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 31. " PDD[31] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 24. " PDD[24] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0xB
|
|
endif
|
|
width 0x0B
|
|
elif cpuis("MKL82Z*")
|
|
width 12.
|
|
sif cpuis("MKL*VLH*")||cpuis("MKL*VMP*")
|
|
width 13.
|
|
tree "FGPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FGPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "FGPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FGPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FGPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FGPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "FGPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FGPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FGPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FGPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "FGPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "FGPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "FGPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "FGPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "FGPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "FGPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "FGPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "FGPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "FGPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "FGPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "FGPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL*VLL*")||cpuis("MKL*VMC*")
|
|
width 13.
|
|
tree "FGPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FGPIO_A_PDOR,Port Data Output Register"
|
|
sif cpuis("MKL*VMC*")
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PDO[14]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
sif cpuis("MKL*VMC*")
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "FGPIO_A_PTOR,Port Toggle Output Register"
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 29. " PTTO[29] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 15. " PTTO[15] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " PTTO[14] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FGPIO_A_PDIR,Port Data Input Register"
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 29. " PDI[29] ,Port data input" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 15. " PDI[15] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 14. " PDI[14] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
newline
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FGPIO_A_PDDR,Port Data Direction Register"
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 29. " PDD[29] ,Port data direction" "Input,Output"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 15. " PDD[15] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 14. " PDD[14] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
newline
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FGPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
sif cpuis("MKL*VMC*")
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "FGPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 23. " PTTO[23] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " PTTO[22] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " PTTO[21] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 20. " PTTO[20] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FGPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 23. " PDI[23] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 22. " PDI[22] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 20. " PDI[20] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
newline
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FGPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 23. " PDD[23] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 22. " PDD[22] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 20. " PDD[20] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
newline
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FGPIO_C_PDOR,Port Data Output Register"
|
|
sif cpuis("MKL*VMC*")
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
sif cpuis("MKL*VMC*")
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PDO[14]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "FGPIO_C_PTOR,Port Toggle Output Register"
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15. " PTTO[15] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " PTTO[14] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "FGPIO_C_PDIR,Port Data Input Register"
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15. " PDI[15] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 14. " PDI[14] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "FGPIO_C_PDDR,Port Data Direction Register"
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15. " PDD[15] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 14. " PDD[14] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "FGPIO_D_PDOR,Port Data Output Register"
|
|
sif cpuis("MKL*VMC*")
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PDO[14]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "FGPIO_D_PTOR,Port Toggle Output Register"
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 15. " PTTO[15] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " PTTO[14] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "FGPIO_D_PDIR,Port Data Input Register"
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 15. " PDI[15] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 14. " PDI[14] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
endif
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "FGPIO_D_PDDR,Port Data Direction Register"
|
|
sif cpuis("MKL*VMC*")
|
|
bitfld.long 0x00 15. " PDD[15] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 14. " PDD[14] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
endif
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "FGPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_SET/CLR ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_SET/CLR ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "FGPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "FGPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[98] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "FGPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
elif cpuis("MKL*VLK*")
|
|
width 13.
|
|
tree "FGPIO_A"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FGPIO_A_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PDO[14]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "FGPIO_A_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 15. " PTTO[15] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " PTTO[14] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FGPIO_A_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 15. " PDI[15] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 14. " PDI[14] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FGPIO_A_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 15. " PDD[15] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 14. " PDD[14] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_B"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FGPIO_B_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "FGPIO_B_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " PTTO[18] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FGPIO_B_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FGPIO_B_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_C"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FGPIO_C_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "FGPIO_C_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 17. " PTTO[17] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " PTTO[16] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " PTTO[13] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " PTTO[12] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " PTTO[10] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " PTTO[9] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "FGPIO_C_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " PDI[16] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "FGPIO_C_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " PDD[16] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_D"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "FGPIO_D_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "FGPIO_D_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " PTTO[6] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "FGPIO_D_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "FGPIO_D_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
tree "FGPIO_E"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "FGPIO_E_PDOR,Port Data Output Register"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1]_set/clr ,Port data output" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0]_set/clr ,Port data output" "Low,High"
|
|
newline
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "FGPIO_E_PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " PTTO[8] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. " PTTO[5] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " PTTO[4] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 3. " PTTO[3] ,Port toggle output" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. " PTTO[2] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " PTTO[1] ,Port toggle output" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " PTTO[0] ,Port toggle output" "No effect,Toggle"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "FGPIO_E_PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " PDI[5] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port data input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " PDI[2] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port data input" "Low,High"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port data input" "Low,High"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "FGPIO_E_PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. " PDD[5] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port data direction" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " PDD[2] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port data direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port data direction" "Input,Output"
|
|
tree.end
|
|
width 0x0B
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
sif cpuis("MKL05*")||cpuis("MK15*")||cpuis("MKL15*")||cpuis("MKL16*")||cpuis("MKL25*")||cpuis("MKL26*")||cpuis("MKL36*")||cpuis("MKL46*")||cpuis("MKL82Z*")||cpuis("KKL15*")
|
|
tree "TSI (Touch Sense Input)"
|
|
base ad:0x40045000
|
|
width 7.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "GENCS,TSI General Control And Status Register"
|
|
eventfld.long 0x00 31. " OUTRGF ,Out of range flag" "No,Yes"
|
|
bitfld.long 0x00 28. " ESOR ,End-of-scan or out-of-range interrupt selection" "Out-of-range,End-of-scan"
|
|
newline
|
|
bitfld.long 0x00 24.--27. " MODE ,TSI analog modes setup and status bits" "Capacitive sensing,,,,Single thresh. Noise & disabled freq. Limit. Circuit,,,,Single thresh. Noise & enabled freq. Limit. Circuit,,,,Automatic noise detection,?..."
|
|
newline
|
|
bitfld.long 0x00 21.--23. " REFCHRG ,Reference oscillator charge and discharge current value" "500nA,1uA,2uA,4uA,8uA,16uA,32uA,64uA"
|
|
bitfld.long 0x00 19.--20. " DVOLT ,Oscillator's voltage rails (DV/VP/VM)" "1.03/1.33/0.30 V,0.73/1.18/0.45 V,0.43/1.03/0.60 V,0.29/0.95/0.67 V"
|
|
bitfld.long 0x00 16.--18. " EXTCHRG ,Electrode oscillator charge and discharge current value" "500nA,1uA,2uA,4uA,8uA,16uA,32uA,64uA"
|
|
newline
|
|
bitfld.long 0x00 13.--15. " PS ,Prescaler of the output of electrode oscillator" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
bitfld.long 0x00 8.--12. " NSCN ,Scan number for each electrode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 7. " TSIEN ,Touch sensing input module enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " TSIIEN ,Touch sensing input interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " STPE ,TSI stop enable" "Disabled,Running"
|
|
bitfld.long 0x00 4. " STM ,Scan trigger mode" "Software,Hardware"
|
|
newline
|
|
rbitfld.long 0x00 3. " SCNIP ,Scan in progress status" "Not in progress,In progress"
|
|
eventfld.long 0x00 2. " EOSF ,End of scan flag" "Not completed,Completed"
|
|
bitfld.long 0x00 1. " CURSW ,Swaps current sources of electrode oscillator and reference oscillator" "Not swapped,Swapped"
|
|
sif cpuis("MKL28Z*")||cpuis("MKL82Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " EOSDMEO ,End-of-Scan DMA transfer request enable only" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "DATA,TSI DATA Register"
|
|
sif cpuis("MKL05*FK*")
|
|
bitfld.long 0x04 28.--31. " TSICH ,Current channel measured" "0,1,2,3,4,5,6,7,?..."
|
|
newline
|
|
elif cpuis("MK15*FM*")||cpuis("MKL25*FM*")||cpuis("MKL15*FM*")||cpuis("MKL26Z128CAL4")
|
|
bitfld.long 0x04 28.--31. " TSICH ,Current channel measured" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
elif cpuis("MKL05*LF*")||cpuis("MKL05*FM*")||cpuis("MKL05*LC*")
|
|
bitfld.long 0x04 28.--31. " TSICH ,Current channel measured" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
newline
|
|
elif cpuis("MK15*FT*")||cpuis("MKL25*FT*")||cpuis("MKL15*FT*")
|
|
bitfld.long 0x04 28.--31. " TSICH ,Current channel measured" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,?..."
|
|
newline
|
|
elif cpuis("MK*LH*")||cpuis("MK*LK*")||cpuis("MK*MP*")||cpuis("MK*LL*")||cpuis("MK*MC*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")||cpuis("MKL28Z*")||cpuis("MKL82?Z*")
|
|
bitfld.long 0x04 28.--31. " TSICH ,Current channel measured" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
elif cpuis("MKL26*FT*")||cpuis("MKL16*FT*")
|
|
bitfld.long 0x04 28.--31. " TSICH ,Current channel measured" "0,1,2,3,4,5,6,7,8,9,10,,,13,14,15"
|
|
newline
|
|
elif cpuis("MKL26*FM*")||cpuis("MKL16*FM*")
|
|
bitfld.long 0x04 28.--31. " TSICH ,Current channel measured" "0,1,2,3,4,5,6,,,,,,,,14,15"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 23. " DMAEN ,DMA transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " SWTS ,Software trigger start" "No effect,Start"
|
|
newline
|
|
hexmask.long.word 0x04 0.--15. 1. " TSICN ,TSI conversion counter value"
|
|
line.long 0x08 "TSHD,TSI Threshold Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " THRESH ,TSI wakeup channel high-threshold"
|
|
hexmask.long.word 0x08 0.--15. 1. " THRESL ,TSI wakeup channel low-threshold"
|
|
width 0x0B
|
|
tree.end
|
|
elif cpuis("MKL28Z*")
|
|
tree "TSI (Touch Sense Input)"
|
|
base ad:0x40062000
|
|
width 7.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "GENCS,TSI General Control And Status Register"
|
|
eventfld.long 0x00 31. " OUTRGF ,Out of range flag" "No,Yes"
|
|
bitfld.long 0x00 28. " ESOR ,End-of-scan or out-of-range interrupt selection" "Out-of-range,End-of-scan"
|
|
newline
|
|
bitfld.long 0x00 24.--27. " MODE ,TSI analog modes setup and status bits" "Capacitive sensing,,,,Single thresh. Noise & disabled freq. Limit. Circuit,,,,Single thresh. Noise & enabled freq. Limit. Circuit,,,,Automatic noise detection,?..."
|
|
newline
|
|
bitfld.long 0x00 21.--23. " REFCHRG ,Reference oscillator charge and discharge current value" "500nA,1uA,2uA,4uA,8uA,16uA,32uA,64uA"
|
|
bitfld.long 0x00 19.--20. " DVOLT ,Oscillator's voltage rails (DV/VP/VM)" "1.03/1.33/0.30 V,0.73/1.18/0.45 V,0.43/1.03/0.60 V,0.29/0.95/0.67 V"
|
|
bitfld.long 0x00 16.--18. " EXTCHRG ,Electrode oscillator charge and discharge current value" "500nA,1uA,2uA,4uA,8uA,16uA,32uA,64uA"
|
|
newline
|
|
bitfld.long 0x00 13.--15. " PS ,Prescaler of the output of electrode oscillator" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
bitfld.long 0x00 8.--12. " NSCN ,Scan number for each electrode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 7. " TSIEN ,Touch sensing input module enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " TSIIEN ,Touch sensing input interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " STPE ,TSI stop enable" "Disabled,Running"
|
|
bitfld.long 0x00 4. " STM ,Scan trigger mode" "Software,Hardware"
|
|
newline
|
|
rbitfld.long 0x00 3. " SCNIP ,Scan in progress status" "Not in progress,In progress"
|
|
eventfld.long 0x00 2. " EOSF ,End of scan flag" "Not completed,Completed"
|
|
bitfld.long 0x00 1. " CURSW ,Swaps current sources of electrode oscillator and reference oscillator" "Not swapped,Swapped"
|
|
sif cpuis("MKL28Z*")||cpuis("MKL82Z*")
|
|
newline
|
|
bitfld.long 0x00 0. " EOSDMEO ,End-of-Scan DMA transfer request enable only" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "DATA,TSI DATA Register"
|
|
sif cpuis("MKL05*FK*")
|
|
bitfld.long 0x04 28.--31. " TSICH ,Current channel measured" "0,1,2,3,4,5,6,7,?..."
|
|
newline
|
|
elif cpuis("MK15*FM*")||cpuis("MKL25*FM*")||cpuis("MKL15*FM*")||cpuis("MKL26Z128CAL4")
|
|
bitfld.long 0x04 28.--31. " TSICH ,Current channel measured" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
elif cpuis("MKL05*LF*")||cpuis("MKL05*FM*")||cpuis("MKL05*LC*")
|
|
bitfld.long 0x04 28.--31. " TSICH ,Current channel measured" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
newline
|
|
elif cpuis("MK15*FT*")||cpuis("MKL25*FT*")||cpuis("MKL15*FT*")
|
|
bitfld.long 0x04 28.--31. " TSICH ,Current channel measured" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,?..."
|
|
newline
|
|
elif cpuis("MK*LH*")||cpuis("MK*LK*")||cpuis("MK*MP*")||cpuis("MK*LL*")||cpuis("MK*MC*")||cpuis("MKL36Z*")||cpuis("MKL46Z*")||cpuis("MKL28Z*")||cpuis("MKL82?Z*")
|
|
bitfld.long 0x04 28.--31. " TSICH ,Current channel measured" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
elif cpuis("MKL26*FT*")||cpuis("MKL16*FT*")
|
|
bitfld.long 0x04 28.--31. " TSICH ,Current channel measured" "0,1,2,3,4,5,6,7,8,9,10,,,13,14,15"
|
|
newline
|
|
elif cpuis("MKL26*FM*")||cpuis("MKL16*FM*")
|
|
bitfld.long 0x04 28.--31. " TSICH ,Current channel measured" "0,1,2,3,4,5,6,,,,,,,,14,15"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 23. " DMAEN ,DMA transfer enabled" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " SWTS ,Software trigger start" "No effect,Start"
|
|
newline
|
|
hexmask.long.word 0x04 0.--15. 1. " TSICN ,TSI conversion counter value"
|
|
line.long 0x08 "TSHD,TSI Threshold Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " THRESH ,TSI wakeup channel high-threshold"
|
|
hexmask.long.word 0x08 0.--15. 1. " THRESL ,TSI wakeup channel low-threshold"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif cpuis("MKL34Z*")||cpuis("MKL33Z*")||cpuis("MKL36Z*")||cpuis("MKL43Z*")||cpuis("MKL46Z*")
|
|
tree "SLCD (LCD Controller)"
|
|
base ad:0x40053000
|
|
width 8.
|
|
sif cpuis("MKL33Z32*4")||cpuis("MKL33Z64*4")
|
|
if ((per.l(ad:0x40053000)&0x800080)==0x80)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GCR,LCD General Control Register"
|
|
bitfld.long 0x00 31. " RVEN ,Regulated voltage enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " RVTRIM ,Regulated voltage trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 23. " CPSEL ,Charge pump or resistor bias select" "Resistor network,Charge pump"
|
|
bitfld.long 0x00 20.--21. " LADJ ,Load adjust (adjust the resistor bias network for different LCD glass capacitance)" "Low load(glass capacitance <=2000pf),Low load(glass capacitance <=2000pf),High load(glass capacitance <=8000pf),High load(glass capacitance <=8000pf)"
|
|
newline
|
|
rbitfld.long 0x00 17. " VSUPPLY ,Voltage supply control" "Int. Vdd,Ext. Vdd/int. Vireg"
|
|
bitfld.long 0x00 15. " PADSAFE ,Pad safe state enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FDCIEN ,LCD fault detection complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " ALTDIV ,LCD alternate clock divider" "No divide,Div by 64,Div by 256,Div by 512"
|
|
newline
|
|
bitfld.long 0x00 11. " ALTSOURCE ,Select the alternate clock source" "1,2"
|
|
bitfld.long 0x00 10. " FFR ,Fast frame rate select" "Standard,Fast"
|
|
newline
|
|
bitfld.long 0x00 9. " LCDDOZE ,LCD driver" "Not stopped,Stopped"
|
|
bitfld.long 0x00 8. " LCDSTP ,LCD driver" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 7. " LCDEN ,LCD driver enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " SOURCE ,LCD clock source select" "Default,Alternate"
|
|
newline
|
|
rbitfld.long 0x00 3.--5. " LCLK ,LCD clock prescaler" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DUTY ,LCD duty select" "1 BP,2 BP,3 BP,4 BP,5 BP,6 BP,7 BP,8 BP"
|
|
elif ((per.l(ad:0x40053000)&0x800080)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GCR,LCD General Control Register"
|
|
bitfld.long 0x00 31. " RVEN ,Regulated voltage enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " RVTRIM ,Regulated voltage trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 23. " CPSEL ,Charge pump or resistor bias select" "Resistor network,Charge pump"
|
|
bitfld.long 0x00 20.--21. " LADJ ,Load adjust (adjust the resistor bias network for different LCD glass capacitance)" "Low load(glass capacitance <=2000pf),Low load(glass capacitance <=2000pf),High load(glass capacitance <=8000pf),High load(glass capacitance <=8000pf)"
|
|
newline
|
|
bitfld.long 0x00 17. " VSUPPLY ,Voltage supply control" "Int. Vdd,Ext. Vdd/int. Vireg"
|
|
bitfld.long 0x00 15. " PADSAFE ,Pad safe state enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FDCIEN ,LCD fault detection complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " ALTDIV ,LCD alternate clock divider" "No divide,Div by 64,Div by 256,Div by 512"
|
|
newline
|
|
bitfld.long 0x00 11. " ALTSOURCE ,Select the alternate clock source" "1,2"
|
|
bitfld.long 0x00 10. " FFR ,Fast frame rate select" "Standard,Fast"
|
|
newline
|
|
bitfld.long 0x00 9. " LCDDOZE ,LCD driver" "Not stopped,Stopped"
|
|
bitfld.long 0x00 8. " LCDSTP ,LCD driver" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 7. " LCDEN ,LCD driver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SOURCE ,LCD clock source select" "Default,Alternate"
|
|
newline
|
|
bitfld.long 0x00 3.--5. " LCLK ,LCD clock prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DUTY ,LCD duty select" "1 BP,2 BP,3 BP,4 BP,5 BP,6 BP,7 BP,8 BP"
|
|
elif ((per.l(ad:0x40053000)&0x800080)==0x800080)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GCR,LCD General Control Register"
|
|
bitfld.long 0x00 31. " RVEN ,Regulated voltage enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " RVTRIM ,Regulated voltage trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 23. " CPSEL ,Charge pump or resistor bias select" "Resistor network,Charge pump"
|
|
bitfld.long 0x00 20.--21. " LADJ ,Load adjust (adjust the clock source for the charge pump)" "Fastest clock(glass capacitance <=8000pf),Intermediate clock(glass capacitance <=4000pf),Intermediate clock(glass capacitance <=2000pf),Slowest clock(glass capacitance <=1000pf)"
|
|
newline
|
|
rbitfld.long 0x00 17. " VSUPPLY ,Voltage supply control" "Int. Vdd,Ext. Vdd/int. Vireg"
|
|
bitfld.long 0x00 15. " PADSAFE ,Pad safe state enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FDCIEN ,LCD fault detection complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " ALTDIV ,LCD alternate clock divider" "No divide,Div by 64,Div by 256,Div by 512"
|
|
newline
|
|
bitfld.long 0x00 11. " ALTSOURCE ,Select the alternate clock source" "1,2"
|
|
bitfld.long 0x00 10. " FFR ,Fast frame rate select" "Standard,Fast"
|
|
newline
|
|
bitfld.long 0x00 9. " LCDDOZE ,LCD driver" "Not stopped,Stopped"
|
|
bitfld.long 0x00 8. " LCDSTP ,LCD driver" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 7. " LCDEN ,LCD driver enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " SOURCE ,LCD clock source select" "Default,Alternate"
|
|
newline
|
|
rbitfld.long 0x00 3.--5. " LCLK ,LCD clock prescaler" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DUTY ,LCD duty select" "1 BP,2 BP,3 BP,4 BP,5 BP,6 BP,7 BP,8 BP"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GCR,LCD General Control Register"
|
|
bitfld.long 0x00 31. " RVEN ,Regulated voltage enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " RVTRIM ,Regulated voltage trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 23. " CPSEL ,Charge pump or resistor bias select" "Resistor network,Charge pump"
|
|
bitfld.long 0x00 20.--21. " LADJ ,Load adjust (adjust the clock source for the charge pump)" "Fastest clock(glass capacitance <=8000pf),Intermediate clock(glass capacitance <=4000pf),Intermediate clock(glass capacitance <=2000pf),Slowest clock(glass capacitance <=1000pf)"
|
|
newline
|
|
bitfld.long 0x00 17. " VSUPPLY ,Voltage supply control" "Int. Vdd,Ext. Vdd/int. Vireg"
|
|
bitfld.long 0x00 15. " PADSAFE ,Pad safe state enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FDCIEN ,LCD fault detection complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " ALTDIV ,LCD alternate clock divider" "No divide,Div by 64,Div by 256,Div by 512"
|
|
newline
|
|
bitfld.long 0x00 11. " ALTSOURCE ,Select the alternate clock source" "1,2"
|
|
bitfld.long 0x00 10. " FFR ,Fast frame rate select" "Standard,Fast"
|
|
newline
|
|
bitfld.long 0x00 9. " LCDDOZE ,LCD driver" "Not stopped,Stopped"
|
|
bitfld.long 0x00 8. " LCDSTP ,LCD driver" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 7. " LCDEN ,LCD driver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SOURCE ,LCD clock source select" "Default,Alternate"
|
|
newline
|
|
bitfld.long 0x00 3.--5. " LCLK ,LCD clock prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DUTY ,LCD duty select" "1 BP,2 BP,3 BP,4 BP,5 BP,6 BP,7 BP,8 BP"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40053000)&0x800080)==0x80)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GCR,LCD General Control Register"
|
|
bitfld.long 0x00 31. " RVEN ,Regulated voltage enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " RVTRIM ,Regulated voltage trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 23. " CPSEL ,Charge pump or resistor bias select" "Resistor network,Charge pump"
|
|
bitfld.long 0x00 20.--21. " LADJ ,Load adjust (adjust the resistor bias network for different LCD glass capacitance)" "Low load(glass capacitance <=2000pf),Low load(glass capacitance <=2000pf),High load(glass capacitance <=8000pf),High load(glass capacitance <=8000pf)"
|
|
newline
|
|
rbitfld.long 0x00 17. " VSUPPLY ,Voltage supply control" "Int. Vdd,Ext. Vdd/int. Vireg"
|
|
bitfld.long 0x00 15. " PADSAFE ,Pad safe state enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FDCIEN ,LCD fault detection complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " ALTDIV ,LCD alternate clock divider" "No divide,Div by 64,Div by 256,Div by 512"
|
|
newline
|
|
bitfld.long 0x00 11. " ALTSOURCE ,Select the alternate clock source" "1,2"
|
|
bitfld.long 0x00 10. " FFR ,Fast frame rate select" "Standard,Fast"
|
|
newline
|
|
bitfld.long 0x00 9. " LCDDOZE ,LCD driver" "Not stopped,Stopped"
|
|
bitfld.long 0x00 8. " LCDSTP ,LCD driver" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 7. " LCDEN ,LCD driver enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " SOURCE ,LCD clock source select" "Default,Alternate"
|
|
newline
|
|
rbitfld.long 0x00 3.--5. " LCLK ,LCD clock prescaler" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DUTY ,LCD duty select" "1 BP,2 BP,3 BP,4 BP,,,,8 BP"
|
|
elif ((per.l(ad:0x40053000)&0x800080)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GCR,LCD General Control Register"
|
|
bitfld.long 0x00 31. " RVEN ,Regulated voltage enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " RVTRIM ,Regulated voltage trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 23. " CPSEL ,Charge pump or resistor bias select" "Resistor network,Charge pump"
|
|
bitfld.long 0x00 20.--21. " LADJ ,Load adjust (adjust the resistor bias network for different LCD glass capacitance)" "Low load(glass capacitance <=2000pf),Low load(glass capacitance <=2000pf),High load(glass capacitance <=8000pf),High load(glass capacitance <=8000pf)"
|
|
newline
|
|
bitfld.long 0x00 17. " VSUPPLY ,Voltage supply control" "Int. Vdd,Ext. Vdd/int. Vireg"
|
|
bitfld.long 0x00 15. " PADSAFE ,Pad safe state enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FDCIEN ,LCD fault detection complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " ALTDIV ,LCD alternate clock divider" "No divide,Div by 64,Div by 256,Div by 512"
|
|
newline
|
|
bitfld.long 0x00 11. " ALTSOURCE ,Select the alternate clock source" "1,2"
|
|
bitfld.long 0x00 10. " FFR ,Fast frame rate select" "Standard,Fast"
|
|
newline
|
|
bitfld.long 0x00 9. " LCDDOZE ,LCD driver" "Not stopped,Stopped"
|
|
bitfld.long 0x00 8. " LCDSTP ,LCD driver" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 7. " LCDEN ,LCD driver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SOURCE ,LCD clock source select" "Default,Alternate"
|
|
newline
|
|
bitfld.long 0x00 3.--5. " LCLK ,LCD clock prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DUTY ,LCD duty select" "1 BP,2 BP,3 BP,4 BP,,,,8 BP"
|
|
elif ((per.l(ad:0x40053000)&0x800080)==0x800080)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GCR,LCD General Control Register"
|
|
bitfld.long 0x00 31. " RVEN ,Regulated voltage enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " RVTRIM ,Regulated voltage trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 23. " CPSEL ,Charge pump or resistor bias select" "Resistor network,Charge pump"
|
|
bitfld.long 0x00 20.--21. " LADJ ,Load adjust (adjust the clock source for the charge pump)" "Fastest clock(glass capacitance <=8000pf),Intermediate clock(glass capacitance <=4000pf),Intermediate clock(glass capacitance <=2000pf),Slowest clock(glass capacitance <=1000pf)"
|
|
newline
|
|
rbitfld.long 0x00 17. " VSUPPLY ,Voltage supply control" "Int. Vdd,Ext. Vdd/int. Vireg"
|
|
bitfld.long 0x00 15. " PADSAFE ,Pad safe state enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FDCIEN ,LCD fault detection complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " ALTDIV ,LCD alternate clock divider" "No divide,Div by 64,Div by 256,Div by 512"
|
|
newline
|
|
bitfld.long 0x00 11. " ALTSOURCE ,Select the alternate clock source" "1,2"
|
|
bitfld.long 0x00 10. " FFR ,Fast frame rate select" "Standard,Fast"
|
|
newline
|
|
bitfld.long 0x00 9. " LCDDOZE ,LCD driver" "Not stopped,Stopped"
|
|
bitfld.long 0x00 8. " LCDSTP ,LCD driver" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 7. " LCDEN ,LCD driver enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " SOURCE ,LCD clock source select" "Default,Alternate"
|
|
newline
|
|
rbitfld.long 0x00 3.--5. " LCLK ,LCD clock prescaler" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DUTY ,LCD duty select" "1 BP,2 BP,3 BP,4 BP,,,,8 BP"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GCR,LCD General Control Register"
|
|
bitfld.long 0x00 31. " RVEN ,Regulated voltage enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " RVTRIM ,Regulated voltage trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 23. " CPSEL ,Charge pump or resistor bias select" "Resistor network,Charge pump"
|
|
bitfld.long 0x00 20.--21. " LADJ ,Load adjust (adjust the clock source for the charge pump)" "Fastest clock(glass capacitance <=8000pf),Intermediate clock(glass capacitance <=4000pf),Intermediate clock(glass capacitance <=2000pf),Slowest clock(glass capacitance <=1000pf)"
|
|
newline
|
|
bitfld.long 0x00 17. " VSUPPLY ,Voltage supply control" "Int. Vdd,Ext. Vdd/int. Vireg"
|
|
bitfld.long 0x00 15. " PADSAFE ,Pad safe state enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FDCIEN ,LCD fault detection complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " ALTDIV ,LCD alternate clock divider" "No divide,Div by 64,Div by 256,Div by 512"
|
|
newline
|
|
bitfld.long 0x00 11. " ALTSOURCE ,Select the alternate clock source" "1,2"
|
|
bitfld.long 0x00 10. " FFR ,Fast frame rate select" "Standard,Fast"
|
|
newline
|
|
bitfld.long 0x00 9. " LCDDOZE ,LCD driver" "Not stopped,Stopped"
|
|
bitfld.long 0x00 8. " LCDSTP ,LCD driver" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 7. " LCDEN ,LCD driver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SOURCE ,LCD clock source select" "Default,Alternate"
|
|
newline
|
|
bitfld.long 0x00 3.--5. " LCLK ,LCD clock prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DUTY ,LCD duty select" "1 BP,2 BP,3 BP,4 BP,,,,8 BP"
|
|
endif
|
|
endif
|
|
group.long 0x04++0x1F
|
|
line.long 0x00 "AR,LCD Auxiliary Register"
|
|
bitfld.long 0x00 7. " BLINK ,Blink command" "Stopped,Started"
|
|
bitfld.long 0x00 6. " ALT ,Alternate display mode" "Normal,Alternate"
|
|
newline
|
|
bitfld.long 0x00 5. " BLANK ,Blank display mode" "Normal,Blank"
|
|
bitfld.long 0x00 3. " BMODE ,Blink mode" "Blank,Alternate"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " BRATE ,Blink-rate configuration" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "FDCR,LCD Fault Detect Control Register"
|
|
bitfld.long 0x04 12.--14. " FDPRS ,Fault detect clock prescaler" "No div,Div by 2,Div by 4,Div by 8,Div by 16,Div by 32,Div by 64,Div by 128"
|
|
bitfld.long 0x04 9.--11. " FDSWW ,Fault detect sample window width" "4 sample clock cycles,8 sample clock cycles,16 sample clock cycles,32 sample clock cycles,64 sample clock cycles,128 sample clock cycles,256 sample clock cycles,512 sample clock cycles"
|
|
newline
|
|
bitfld.long 0x04 7. " FDEN ,Fault detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " FDBPEN ,Fault detect backplane enable" "Disabled,Enabled"
|
|
sif cpuis("MKL33Z*VLH*")||cpuis("MKL33Z*VMP*")||cpuis("MKL34Z*VLH*")||cpuis("MKL36Z*VLH*")||cpuis("MKL36Z*VMP*")
|
|
newline
|
|
bitfld.long 0x04 0.--5. " FDPINID ,Fault detect pin ID" "P0,P1,P2,P3,P4,P5,P6,,,,,,P12,P13,P14,P15,,,,,P20,P21,P22,P23,P24,P25,P26,P27,,,,,,,,,,,,P39,P40,P41,P42,P43,P44,P45,P46,P47,P48,P49,,,,,,P55,P56,P57,P58,P59,P60,?..."
|
|
elif cpuis("MKL33Z*VFT*")
|
|
newline
|
|
bitfld.long 0x04 0.--5. " FDPINID ,Fault detect pin ID" "P0,P1,P2,P3,P4,P5,P6,,,,,,,,,,,,,,P20,P21,P22,P23,P24,P25,P26,P27,,,,,,,,,,,,P39,,,,,P44,P45,P46,P47,P48,P49,,,,,,P55,P56,P57,P58,P59,P60,?..."
|
|
elif cpuis("MKL33Z*VLK*")
|
|
newline
|
|
bitfld.long 0x04 0.--5. " FDPINID ,Fault detect pin ID" "P0,P1,P2,P3,P4,P5,P6,,P8,P9,P10,P11,P12,P13,P14,P15,,,,,P20,P21,P22,P23,P24,P25,P26,P27,P28,P29,P30,P31,,,,,,,,P39,P40,P41,P42,P43,P44,P45,P46,P47,P48,P49,P50,P51,P52,P53,,P55,P56,P57,P58,P59,P60,?..."
|
|
elif cpuis("MKL43Z*VLH*")||cpuis("MKL43Z*VMP*")||cpuis("MKL46Z*VLH*")||cpuis("MKL46Z*VMP*")
|
|
newline
|
|
bitfld.long 0x04 0.--5. " FDPINID ,Fault detect pin ID" "P0,P1,P2,P3,P4,P5,P6,,,,,,P12,P13,P14,P15,,,,,P20,P21,P22,P23,P24,P25,P26,P27,,,,,,,,,,,,P39,P40,P41,P42,P43,P44,P45,P46,P47,P48,P49,,,,,,,,,,P59,P60,?..."
|
|
else
|
|
newline
|
|
bitfld.long 0x04 0.--5. " FDPINID ,Fault detect pin ID" "P0,P1,P2,P3,P4,P5,P6,P7,P8,P9,P10,P11,P12,P13,P14,P15,P16,P17,P18,P19,P20,P21,P22,P23,P24,P25,P26,P27,P28,P29,P30,P31,P32,P33,P34,P35,P36,P37,P38,P39,P40,P41,P42,P43,P44,P45,P46,P47,P48,P49,P50,P51,P52,P53,P54,P55,P56,P57,P58,P59,P60,?..."
|
|
endif
|
|
line.long 0x08 "FDSR,LCD Fault Detect Status Register"
|
|
eventfld.long 0x08 15. " FDCF ,Fault detection complete flag" "Not completed,Completed"
|
|
hexmask.long.byte 0x08 0.--7. 1. " FDCNT ,Fault detect counter"
|
|
newline
|
|
line.long 0x0C "PEN_L,LCD Pin Enable Low Register"
|
|
sif !cpuis("MKL33Z*VFT*")&&!cpuis("MKL33Z*VLH*")&&!cpuis("MKL33Z*VMP*")&&!cpuis("MKL34Z*VLH*")&&!cpuis("MKL36Z*VLH*")&&!cpuis("MKL36Z*VMP*")&&!cpuis("MKL43Z*VLH*")&&!cpuis("MKL43Z*VMP*")&&!cpuis("MKL46Z*VLH*")&&!cpuis("MKL46Z*VMP*")
|
|
bitfld.long 0x0C 31. " PEN_31 ,LCD pin 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " PEN_30 ,LCD pin 30 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " PEN_29 ,LCD pin 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " PEN_28 ,LCD pin 28 enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0C 27. " PEN_27 ,LCD pin 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " PEN_26 ,LCD pin 26 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 25. " PEN_25 ,LCD pin 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " PEN_24 ,LCD pin 24 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 23. " PEN_23 ,LCD pin 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " PEN_22 ,LCD pin 22 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " PEN_21 ,LCD pin 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " PEN_20 ,LCD pin 20 enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("MKL33Z*VFT*")
|
|
bitfld.long 0x0C 15. " PEN_15 ,LCD pin 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " PEN_14 ,LCD pin 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " PEN_13 ,LCD pin 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " PEN_12 ,LCD pin 12 enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif !cpuis("MKL33Z*VFT*")&&!cpuis("MKL33Z*VLH*")&&!cpuis("MKL33Z*VMP*")&&!cpuis("MKL34Z*VLH*")&&!cpuis("MKL36Z*VLH*")&&!cpuis("MKL36Z*VMP*")&&!cpuis("MKL43Z*VLH*")&&!cpuis("MKL43Z*VMP*")&&!cpuis("MKL46Z*VLH*")&&!cpuis("MKL46Z*VMP*")
|
|
bitfld.long 0x0C 11. " PEN_11 ,LCD pin 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " PEN_10 ,LCD pin 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " PEN_9 ,LCD pin 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " PEN_8 ,LCD pin 8 enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif !cpuis("MKL33Z*VFT*")&&!cpuis("MKL33Z*VLH*")&&!cpuis("MKL33Z*VMP*")&&!cpuis("MKL33Z*VLK*")&&!cpuis("MKL34Z*VLH*")&&!cpuis("MKL36Z*VLH*")&&!cpuis("MKL36Z*VMP*")&&!cpuis("MKL43Z*VLH*")&&!cpuis("MKL43Z*VMP*")&&!cpuis("MKL46Z*VLH*")&&!cpuis("MKL46Z*VMP*")
|
|
bitfld.long 0x0C 7. " PEN_7 ,LCD pin 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " PEN_6 ,LCD pin 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " PEN_5 ,LCD pin 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " PEN_4 ,LCD pin 4 enable" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x0C 6. " PEN_6 ,LCD pin 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " PEN_5 ,LCD pin 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " PEN_4 ,LCD pin 4 enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0C 3. " PEN_3 ,LCD pin 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " PEN_2 ,LCD pin 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " PEN_1 ,LCD pin 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PEN_0 ,LCD pin 0 enable" "Disabled,Enabled"
|
|
line.long 0x10 "PEN_H,LCD Pin Enable High Register"
|
|
sif cpuis("MKL43Z*VLH*")||cpuis("MKL43Z*VMP*")||cpuis("MKL46Z*VLH*")||cpuis("MKL46Z*VMP*")
|
|
bitfld.long 0x10 28. " PEN_60 ,LCD pin 60 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 27. " PEN_59 ,LCD pin 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " PEN_49 ,LCD pin 49 enable" "Disabled,Enabled"
|
|
newline
|
|
elif cpuis("MKL33Z*VFT*")||cpuis("MKL33Z*VLH*")||cpuis("MKL33Z*VMP*")||cpuis("MKL34Z*VLH*")||cpuis("MKL36Z*VLH*")||cpuis("MKL36Z*VMP*")
|
|
bitfld.long 0x10 28. " PEN_60 ,LCD pin 60 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 27. " PEN_59 ,LCD pin 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " PEN_58 ,LCD pin 58 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 25. " PEN_57 ,LCD pin 57 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 24. " PEN_56 ,LCD pin 56 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 23. " PEN_55 ,LCD pin 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " PEN_49 ,LCD pin 49 enable" "Disabled,Enabled"
|
|
newline
|
|
elif cpuis("MKL33Z*VLK*")
|
|
bitfld.long 0x10 28. " PEN_60 ,LCD pin 60 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 27. " PEN_59 ,LCD pin 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " PEN_58 ,LCD pin 58 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 25. " PEN_57 ,LCD pin 57 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 24. " PEN_56 ,LCD pin 56 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 23. " PEN_55 ,LCD pin 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " PEN_53 ,LCD pin 53 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 20. " PEN_52 ,LCD pin 52 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 19. " PEN_51 ,LCD pin 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " PEN_50 ,LCD pin 50 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " PEN_49 ,LCD pin 49 enable" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x10 28. " PEN_60 ,LCD pin 60 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 27. " PEN_59 ,LCD pin 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " PEN_58 ,LCD pin 58 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 25. " PEN_57 ,LCD pin 57 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 24. " PEN_56 ,LCD pin 56 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 23. " PEN_55 ,LCD pin 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " PEN_54 ,LCD pin 54 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " PEN_53 ,LCD pin 53 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 20. " PEN_52 ,LCD pin 52 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 19. " PEN_51 ,LCD pin 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " PEN_50 ,LCD pin 50 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " PEN_49 ,LCD pin 49 enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x10 16. " PEN_48 ,LCD pin 48 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 15. " PEN_47 ,LCD pin 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " PEN_46 ,LCD pin 46 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 13. " PEN_45 ,LCD pin 45 enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("MKL33Z*VFT*")
|
|
bitfld.long 0x10 12. " PEN_44 ,LCD pin 44 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 7. " PEN_39 ,LCD pin 39 enable" "Disabled,Enabled"
|
|
newline
|
|
elif cpuis("MKL33Z*VLH*")||cpuis("MKL33Z*VMP*")||cpuis("MKL33Z*VLK*")||cpuis("MKL34Z*VLH*")||cpuis("MKL36Z*VLH*")||cpuis("MKL36Z*VMP*")||cpuis("MKL43Z*VLH*")||cpuis("MKL43Z*VMP*")||cpuis("MKL46Z*VLH*")||cpuis("MKL46Z*VMP*")
|
|
bitfld.long 0x10 12. " PEN_44 ,LCD pin 44 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 11. " PEN_43 ,LCD pin 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " PEN_42 ,LCD pin 42 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " PEN_41 ,LCD pin 41 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 8. " PEN_40 ,LCD pin 40 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 7. " PEN_39 ,LCD pin 39 enable" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x10 12. " PEN_44 ,LCD pin 44 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 11. " PEN_43 ,LCD pin 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " PEN_42 ,LCD pin 42 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " PEN_41 ,LCD pin 41 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 8. " PEN_40 ,LCD pin 40 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 7. " PEN_39 ,LCD pin 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " PEN_38 ,LCD pin 38 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " PEN_37 ,LCD pin 37 enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif !cpuis("MKL33Z*VFT*")&&!cpuis("MKL33Z*VLH*")&&!cpuis("MKL33Z*VMP*")&&!cpuis("MKL33Z*VLK*")&&!cpuis("MKL34Z*VLH*")&&!cpuis("MKL36Z*VLH*")&&!cpuis("MKL36Z*VMP*")&&!cpuis("MKL43Z*VLH*")&&!cpuis("MKL43Z*VMP*")&&!cpuis("MKL46Z*VLH*")&&!cpuis("MKL46Z*VMP*")
|
|
bitfld.long 0x10 4. " PEN_36 ,LCD pin 36 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 3. " PEN_35 ,LCD pin 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " PEN_34 ,LCD pin 34 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " PEN_33 ,LCD pin 33 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 0. " PEN_32 ,LCD pin 32 enable" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x14 "BPEN_L,LCD Backplane Enable Low Register"
|
|
sif !cpuis("MKL33Z*VFT*")&&!cpuis("MKL33Z*VLH*")&&!cpuis("MKL33Z*VMP*")&&!cpuis("MKL34Z*VLH*")&&!cpuis("MKL36Z*VLH*")&&!cpuis("MKL36Z*VMP*")&&!cpuis("MKL43Z*VLH*")&&!cpuis("MKL43Z*VMP*")&&!cpuis("MKL46Z*VLH*")&&!cpuis("MKL46Z*VMP*")
|
|
bitfld.long 0x14 31. " BPEN_31 ,Backplane on LCD pin 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 30. " BPEN_30 ,Backplane on LCD pin 30 enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 29. " BPEN_29 ,Backplane on LCD pin 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 28. " BPEN_28 ,Backplane on LCD pin 28 enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x14 27. " BPEN_27 ,Backplane on LCD pin 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 26. " BPEN_26 ,Backplane on LCD pin 26 enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 25. " BPEN_25 ,Backplane on LCD pin 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 24. " BPEN_24 ,Backplane on LCD pin 24 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 23. " BPEN_23 ,Backplane on LCD pin 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 22. " BPEN_22 ,Backplane on LCD pin 22 enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 21. " BPEN_21 ,Backplane on LCD pin 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 20. " BPEN_20 ,Backplane on LCD pin 20 enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("MKL33Z*VFT*")
|
|
bitfld.long 0x14 15. " BPEN_15 ,Backplane on LCD pin 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " BPEN_14 ,Backplane on LCD pin 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 13. " BPEN_13 ,Backplane on LCD pin 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 12. " BPEN_12 ,Backplane on LCD pin 12 enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif !cpuis("MKL33Z*VFT*")&&!cpuis("MKL33Z*VLH*")&&!cpuis("MKL33Z*VMP*")&&!cpuis("MKL34Z*VLH*")&&!cpuis("MKL36Z*VLH*")&&!cpuis("MKL36Z*VMP*")&&!cpuis("MKL43Z*VLH*")&&!cpuis("MKL43Z*VMP*")&&!cpuis("MKL46Z*VLH*")&&!cpuis("MKL46Z*VMP*")
|
|
bitfld.long 0x14 11. " BPEN_11 ,Backplane on LCD pin 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " BPEN_10 ,Backplane on LCD pin 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 9. " BPEN_9 ,Backplane on LCD pin 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " BPEN_8 ,Backplane on LCD pin 8 enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif !cpuis("MKL33Z*VFT*")&&!cpuis("MKL33Z*VLH*")&&!cpuis("MKL33Z*VMP*")&&!cpuis("MKL33Z*VLK*")&&!cpuis("MKL34Z*VLH*")&&!cpuis("MKL36Z*VLH*")&&!cpuis("MKL36Z*VMP*")&&!cpuis("MKL43Z*VLH*")&&!cpuis("MKL43Z*VMP*")&&!cpuis("MKL46Z*VLH*")&&!cpuis("MKL46Z*VMP*")
|
|
bitfld.long 0x14 7. " BPEN_7 ,Backplane on LCD pin 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " BPEN_6 ,Backplane on LCD pin 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " BPEN_5 ,Backplane on LCD pin 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " BPEN_4 ,Backplane on LCD pin 4 enable" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x14 6. " BPEN_6 ,Backplane on LCD pin 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " BPEN_5 ,Backplane on LCD pin 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " BPEN_4 ,Backplane on LCD pin 4 enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x14 3. " BPEN_3 ,Backplane on LCD pin 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " BPEN_2 ,Backplane on LCD pin 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " BPEN_1 ,Backplane on LCD pin 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " BPEN_0 ,Backplane on LCD pin 0 enable" "Disabled,Enabled"
|
|
line.long 0x18 "BPEN_H,LCD Backplane Enable High Register"
|
|
sif cpuis("MKL43Z*VLH*")||cpuis("MKL43Z*VMP*")||cpuis("MKL46Z*VLH*")||cpuis("MKL46Z*VMP*")
|
|
bitfld.long 0x18 28. " BPEN_60 ,Backplane on LCD pin 60 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 27. " BPEN_59 ,Backplane on LCD pin 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 17. " BPEN_49 ,Backplane on LCD pin 49 enable" "Disabled,Enabled"
|
|
newline
|
|
elif cpuis("MKL33Z*VFT*")||cpuis("MKL33Z*VLH*")||cpuis("MKL33Z*VMP*")||cpuis("MKL34Z*VLH*")||cpuis("MKL36Z*VLH*")||cpuis("MKL36Z*VMP*")
|
|
bitfld.long 0x18 28. " BPEN_60 ,Backplane on LCD pin 60 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 27. " BPEN_59 ,Backplane on LCD pin 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 26. " BPEN_58 ,Backplane on LCD pin 58 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 25. " BPEN_57 ,Backplane on LCD pin 57 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 24. " BPEN_56 ,Backplane on LCD pin 56 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 23. " BPEN_55 ,Backplane on LCD pin 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 17. " BPEN_49 ,Backplane on LCD pin 49 enable" "Disabled,Enabled"
|
|
newline
|
|
elif cpuis("MKL33Z*VLK*")
|
|
bitfld.long 0x18 28. " BPEN_60 ,Backplane on LCD pin 60 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 27. " BPEN_59 ,Backplane on LCD pin 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 26. " BPEN_58 ,Backplane on LCD pin 58 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 25. " BPEN_57 ,Backplane on LCD pin 57 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 24. " BPEN_56 ,Backplane on LCD pin 56 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 23. " BPEN_55 ,Backplane on LCD pin 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 21. " BPEN_53 ,Backplane on LCD pin 53 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 20. " BPEN_52 ,Backplane on LCD pin 52 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 19. " BPEN_51 ,Backplane on LCD pin 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 18. " BPEN_50 ,Backplane on LCD pin 50 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 17. " BPEN_49 ,Backplane on LCD pin 49 enable" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x18 28. " BPEN_60 ,Backplane on LCD pin 60 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 27. " BPEN_59 ,Backplane on LCD pin 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 26. " BPEN_58 ,Backplane on LCD pin 58 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 25. " BPEN_57 ,Backplane on LCD pin 57 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 24. " BPEN_56 ,Backplane on LCD pin 56 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 23. " BPEN_55 ,Backplane on LCD pin 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 22. " BPEN_54 ,Backplane on LCD pin 54 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 21. " BPEN_53 ,Backplane on LCD pin 53 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 20. " BPEN_52 ,Backplane on LCD pin 52 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 19. " BPEN_51 ,Backplane on LCD pin 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 18. " BPEN_50 ,Backplane on LCD pin 50 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 17. " BPEN_49 ,Backplane on LCD pin 49 enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 16. " BPEN_48 ,Backplane on LCD pin 48 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 15. " BPEN_47 ,Backplane on LCD pin 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 14. " BPEN_46 ,Backplane on LCD pin 46 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 13. " BPEN_45 ,Backplane on LCD pin 45 enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("MKL33Z*VFT*")
|
|
bitfld.long 0x18 12. " BPEN_44 ,Backplane on LCD pin 44 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 7. " BPEN_39 ,Backplane on LCD pin 39 enable" "Disabled,Enabled"
|
|
newline
|
|
elif cpuis("MKL33Z*VLH*")||cpuis("MKL33Z*VMP*")||cpuis("MKL33Z*VLK*")||cpuis("MKL34Z*VLH*")||cpuis("MKL36Z*VLH*")||cpuis("MKL36Z*VMP*")||cpuis("MKL43Z*VLH*")||cpuis("MKL43Z*VMP*")||cpuis("MKL46Z*VLH*")||cpuis("MKL46Z*VMP*")
|
|
bitfld.long 0x18 12. " BPEN_44 ,Backplane on LCD pin 44 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 11. " BPEN_43 ,Backplane on LCD pin 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 10. " BPEN_42 ,Backplane on LCD pin 42 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 9. " BPEN_41 ,Backplane on LCD pin 41 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 8. " BPEN_40 ,Backplane on LCD pin 40 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 7. " BPEN_39 ,Backplane on LCD pin 39 enable" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x18 12. " BPEN_44 ,Backplane on LCD pin 44 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 11. " BPEN_43 ,Backplane on LCD pin 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 10. " BPEN_42 ,Backplane on LCD pin 42 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 9. " BPEN_41 ,Backplane on LCD pin 41 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 8. " BPEN_40 ,Backplane on LCD pin 40 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 7. " BPEN_39 ,Backplane on LCD pin 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " BPEN_38 ,Backplane on LCD pin 38 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " BPEN_37 ,Backplane on LCD pin 37 enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif !cpuis("MKL33Z*VFT*")&&!cpuis("MKL33Z*VLH*")&&!cpuis("MKL33Z*VMP*")&&!cpuis("MKL33Z*VLK*")&&!cpuis("MKL34Z*VLH*")&&!cpuis("MKL36Z*VLH*")&&!cpuis("MKL36Z*VMP*")&&!cpuis("MKL43Z*VLH*")&&!cpuis("MKL43Z*VMP*")&&!cpuis("MKL46Z*VLH*")&&!cpuis("MKL46Z*VMP*")
|
|
bitfld.long 0x18 4. " BPEN_36 ,Backplane on LCD pin 36 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 3. " BPEN_35 ,Backplane on LCD pin 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " BPEN_34 ,Backplane on LCD pin 34 enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 1. " BPEN_33 ,Backplane on LCD pin 33 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 0. " BPEN_32 ,Backplane on LCD pin 32 enable" "Disabled,Enabled"
|
|
endif
|
|
width 7.
|
|
tree "LCD Waveform Registers"
|
|
sif cpuis("MKL33Z*VLH*")||cpuis("MKL33Z*VMP*")||cpuis("MKL34Z*VLH*")||cpuis("MKL36Z*VLH*")||cpuis("MKL36Z*VMP*")
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "WF_0,LCD Waveform Register 0"
|
|
bitfld.byte 0x00 7. " WF_0[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_0[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_0[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_0[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_0[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_0[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_0[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_0[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "WF_1,LCD Waveform Register 1"
|
|
bitfld.byte 0x00 7. " WF_1[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_1[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_1[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_1[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_1[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_1[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_1[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_1[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x22++0x00
|
|
line.byte 0x00 "WF_2,LCD Waveform Register 2"
|
|
bitfld.byte 0x00 7. " WF_2[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_2[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_2[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_2[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_2[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_2[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_2[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_2[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x23++0x00
|
|
line.byte 0x00 "WF_3,LCD Waveform Register 3"
|
|
bitfld.byte 0x00 7. " WF_3[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_3[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_3[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_3[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_3[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_3[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_3[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_3[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "WF_4,LCD Waveform Register 4"
|
|
bitfld.byte 0x00 7. " WF_4[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_4[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_4[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_4[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_4[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_4[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_4[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_4[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x25++0x00
|
|
line.byte 0x00 "WF_5,LCD Waveform Register 5"
|
|
bitfld.byte 0x00 7. " WF_5[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_5[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_5[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_5[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_5[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_5[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_5[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_5[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "WF_6,LCD Waveform Register 6"
|
|
bitfld.byte 0x00 7. " WF_6[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_6[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_6[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_6[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_6[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_6[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_6[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_6[A] ,Segment-on front/back plane operation" "Off,On"
|
|
hgroup.byte 0x27++0x00
|
|
hide.byte 0x00 "WF_7,LCD Waveform Register 7"
|
|
hgroup.byte 0x28++0x00
|
|
hide.byte 0x00 "WF_8,LCD Waveform Register 8"
|
|
hgroup.byte 0x29++0x00
|
|
hide.byte 0x00 "WF_9,LCD Waveform Register 9"
|
|
hgroup.byte 0x2A++0x00
|
|
hide.byte 0x00 "WF_10,LCD Waveform Register 10"
|
|
hgroup.byte 0x2B++0x00
|
|
hide.byte 0x00 "WF_11,LCD Waveform Register 11"
|
|
group.byte 0x2C++0x00
|
|
line.byte 0x00 "WF_12,LCD Waveform Register 12"
|
|
bitfld.byte 0x00 7. " WF_12[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_12[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_12[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_12[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_12[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_12[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_12[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_12[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x2D++0x00
|
|
line.byte 0x00 "WF_13,LCD Waveform Register 13"
|
|
bitfld.byte 0x00 7. " WF_13[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_13[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_13[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_13[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_13[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_13[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_13[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_13[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x2E++0x00
|
|
line.byte 0x00 "WF_14,LCD Waveform Register 14"
|
|
bitfld.byte 0x00 7. " WF_14[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_14[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_14[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_14[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_14[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_14[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_14[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_14[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x2F++0x00
|
|
line.byte 0x00 "WF_15,LCD Waveform Register 15"
|
|
bitfld.byte 0x00 7. " WF_15[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_15[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_15[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_15[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_15[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_15[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_15[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_15[A] ,Segment-on front/back plane operation" "Off,On"
|
|
hgroup.byte 0x30++0x00
|
|
hide.byte 0x00 "WF_16,LCD Waveform Register 16"
|
|
hgroup.byte 0x31++0x00
|
|
hide.byte 0x00 "WF_17,LCD Waveform Register 17"
|
|
hgroup.byte 0x32++0x00
|
|
hide.byte 0x00 "WF_18,LCD Waveform Register 18"
|
|
hgroup.byte 0x33++0x00
|
|
hide.byte 0x00 "WF_19,LCD Waveform Register 19"
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "WF_20,LCD Waveform Register 20"
|
|
bitfld.byte 0x00 7. " WF_20[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_20[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_20[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_20[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_20[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_20[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_20[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_20[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x35++0x00
|
|
line.byte 0x00 "WF_21,LCD Waveform Register 21"
|
|
bitfld.byte 0x00 7. " WF_21[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_21[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_21[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_21[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_21[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_21[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_21[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_21[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x36++0x00
|
|
line.byte 0x00 "WF_22,LCD Waveform Register 22"
|
|
bitfld.byte 0x00 7. " WF_22[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_22[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_22[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_22[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_22[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_22[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_22[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_22[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x37++0x00
|
|
line.byte 0x00 "WF_23,LCD Waveform Register 23"
|
|
bitfld.byte 0x00 7. " WF_23[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_23[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_23[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_23[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_23[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_23[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_23[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_23[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x38++0x00
|
|
line.byte 0x00 "WF_24,LCD Waveform Register 24"
|
|
bitfld.byte 0x00 7. " WF_24[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_24[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_24[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_24[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_24[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_24[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_24[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_24[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x39++0x00
|
|
line.byte 0x00 "WF_25,LCD Waveform Register 25"
|
|
bitfld.byte 0x00 7. " WF_25[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_25[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_25[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_25[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_25[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_25[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_25[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_25[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x3A++0x00
|
|
line.byte 0x00 "WF_26,LCD Waveform Register 26"
|
|
bitfld.byte 0x00 7. " WF_26[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_26[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_26[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_26[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_26[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_26[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_26[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_26[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x3B++0x00
|
|
line.byte 0x00 "WF_27,LCD Waveform Register 27"
|
|
bitfld.byte 0x00 7. " WF_27[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_27[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_27[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_27[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_27[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_27[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_27[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_27[A] ,Segment-on front/back plane operation" "Off,On"
|
|
hgroup.byte 0x3C++0x00
|
|
hide.byte 0x00 "WF_28,LCD Waveform Register 28"
|
|
hgroup.byte 0x3D++0x00
|
|
hide.byte 0x00 "WF_29,LCD Waveform Register 29"
|
|
hgroup.byte 0x3E++0x00
|
|
hide.byte 0x00 "WF_30,LCD Waveform Register 30"
|
|
hgroup.byte 0x3F++0x00
|
|
hide.byte 0x00 "WF_31,LCD Waveform Register 31"
|
|
hgroup.byte 0x40++0x00
|
|
hide.byte 0x00 "WF_32,LCD Waveform Register 32"
|
|
hgroup.byte 0x41++0x00
|
|
hide.byte 0x00 "WF_33,LCD Waveform Register 33"
|
|
hgroup.byte 0x42++0x00
|
|
hide.byte 0x00 "WF_34,LCD Waveform Register 34"
|
|
hgroup.byte 0x43++0x00
|
|
hide.byte 0x00 "WF_35,LCD Waveform Register 35"
|
|
hgroup.byte 0x44++0x00
|
|
hide.byte 0x00 "WF_36,LCD Waveform Register 36"
|
|
hgroup.byte 0x45++0x00
|
|
hide.byte 0x00 "WF_37,LCD Waveform Register 37"
|
|
hgroup.byte 0x46++0x00
|
|
hide.byte 0x00 "WF_38,LCD Waveform Register 38"
|
|
group.byte 0x47++0x00
|
|
line.byte 0x00 "WF_39,LCD Waveform Register 39"
|
|
bitfld.byte 0x00 7. " WF_39[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_39[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_39[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_39[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_39[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_39[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_39[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_39[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x48++0x00
|
|
line.byte 0x00 "WF_40,LCD Waveform Register 40"
|
|
bitfld.byte 0x00 7. " WF_40[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_40[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_40[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_40[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_40[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_40[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_40[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_40[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x49++0x00
|
|
line.byte 0x00 "WF_41,LCD Waveform Register 41"
|
|
bitfld.byte 0x00 7. " WF_41[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_41[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_41[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_41[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_41[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_41[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_41[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_41[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x4A++0x00
|
|
line.byte 0x00 "WF_42,LCD Waveform Register 42"
|
|
bitfld.byte 0x00 7. " WF_42[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_42[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_42[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_42[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_42[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_42[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_42[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_42[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x4B++0x00
|
|
line.byte 0x00 "WF_43,LCD Waveform Register 43"
|
|
bitfld.byte 0x00 7. " WF_43[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_43[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_43[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_43[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_43[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_43[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_43[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_43[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x4C++0x00
|
|
line.byte 0x00 "WF_44,LCD Waveform Register 44"
|
|
bitfld.byte 0x00 7. " WF_44[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_44[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_44[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_44[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_44[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_44[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_44[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_44[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x4D++0x00
|
|
line.byte 0x00 "WF_45,LCD Waveform Register 45"
|
|
bitfld.byte 0x00 7. " WF_45[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_45[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_45[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_45[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_45[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_45[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_45[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_45[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x4E++0x00
|
|
line.byte 0x00 "WF_46,LCD Waveform Register 46"
|
|
bitfld.byte 0x00 7. " WF_46[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_46[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_46[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_46[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_46[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_46[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_46[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_46[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x4F++0x00
|
|
line.byte 0x00 "WF_47,LCD Waveform Register 47"
|
|
bitfld.byte 0x00 7. " WF_47[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_47[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_47[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_47[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_47[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_47[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_47[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_47[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x50++0x00
|
|
line.byte 0x00 "WF_48,LCD Waveform Register 48"
|
|
bitfld.byte 0x00 7. " WF_48[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_48[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_48[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_48[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_48[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_48[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_48[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_48[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x51++0x00
|
|
line.byte 0x00 "WF_49,LCD Waveform Register 49"
|
|
bitfld.byte 0x00 7. " WF_49[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_49[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_49[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_49[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_49[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_49[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_49[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_49[A] ,Segment-on front/back plane operation" "Off,On"
|
|
hgroup.byte 0x52++0x00
|
|
hide.byte 0x00 "WF_50,LCD Waveform Register 50"
|
|
hgroup.byte 0x53++0x00
|
|
hide.byte 0x00 "WF_51,LCD Waveform Register 51"
|
|
hgroup.byte 0x54++0x00
|
|
hide.byte 0x00 "WF_52,LCD Waveform Register 52"
|
|
hgroup.byte 0x55++0x00
|
|
hide.byte 0x00 "WF_53,LCD Waveform Register 53"
|
|
hgroup.byte 0x56++0x00
|
|
hide.byte 0x00 "WF_54,LCD Waveform Register 54"
|
|
group.byte 0x57++0x00
|
|
line.byte 0x00 "WF_55,LCD Waveform Register 55"
|
|
bitfld.byte 0x00 7. " WF_55[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_55[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_55[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_55[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_55[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_55[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_55[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_55[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x58++0x00
|
|
line.byte 0x00 "WF_56,LCD Waveform Register 56"
|
|
bitfld.byte 0x00 7. " WF_56[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_56[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_56[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_56[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_56[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_56[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_56[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_56[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x59++0x00
|
|
line.byte 0x00 "WF_57,LCD Waveform Register 57"
|
|
bitfld.byte 0x00 7. " WF_57[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_57[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_57[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_57[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_57[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_57[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_57[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_57[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x5A++0x00
|
|
line.byte 0x00 "WF_58,LCD Waveform Register 58"
|
|
bitfld.byte 0x00 7. " WF_58[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_58[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_58[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_58[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_58[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_58[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_58[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_58[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x5B++0x00
|
|
line.byte 0x00 "WF_59,LCD Waveform Register 59"
|
|
bitfld.byte 0x00 7. " WF_59[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_59[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_59[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_59[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_59[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_59[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_59[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_59[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x5C++0x00
|
|
line.byte 0x00 "WF_60,LCD Waveform Register 60"
|
|
bitfld.byte 0x00 7. " WF_60[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_60[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_60[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_60[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_60[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_60[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_60[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_60[A] ,Segment-on front/back plane operation" "Off,On"
|
|
hgroup.byte 0x5D++0x00
|
|
hide.byte 0x00 "WF_61,LCD Waveform Register 61"
|
|
hgroup.byte 0x5E++0x00
|
|
hide.byte 0x00 "WF_62,LCD Waveform Register 62"
|
|
hgroup.byte 0x5F++0x00
|
|
hide.byte 0x00 "WF_63,LCD Waveform Register 63"
|
|
elif cpuis("MKL33Z*VFT*")
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "WF_0,LCD Waveform Register 0"
|
|
bitfld.byte 0x00 7. " WF_0[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_0[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_0[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_0[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_0[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_0[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_0[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_0[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "WF_1,LCD Waveform Register 1"
|
|
bitfld.byte 0x00 7. " WF_1[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_1[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_1[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_1[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_1[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_1[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_1[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_1[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x22++0x00
|
|
line.byte 0x00 "WF_2,LCD Waveform Register 2"
|
|
bitfld.byte 0x00 7. " WF_2[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_2[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_2[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_2[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_2[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_2[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_2[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_2[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x23++0x00
|
|
line.byte 0x00 "WF_3,LCD Waveform Register 3"
|
|
bitfld.byte 0x00 7. " WF_3[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_3[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_3[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_3[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_3[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_3[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_3[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_3[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "WF_4,LCD Waveform Register 4"
|
|
bitfld.byte 0x00 7. " WF_4[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_4[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_4[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_4[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_4[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_4[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_4[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_4[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x25++0x00
|
|
line.byte 0x00 "WF_5,LCD Waveform Register 5"
|
|
bitfld.byte 0x00 7. " WF_5[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_5[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_5[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_5[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_5[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_5[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_5[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_5[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "WF_6,LCD Waveform Register 6"
|
|
bitfld.byte 0x00 7. " WF_6[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_6[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_6[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_6[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_6[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_6[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_6[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_6[A] ,Segment-on front/back plane operation" "Off,On"
|
|
hgroup.byte 0x27++0x00
|
|
hide.byte 0x00 "WF_7,LCD Waveform Register 7"
|
|
hgroup.byte 0x28++0x00
|
|
hide.byte 0x00 "WF_8,LCD Waveform Register 8"
|
|
hgroup.byte 0x29++0x00
|
|
hide.byte 0x00 "WF_9,LCD Waveform Register 9"
|
|
hgroup.byte 0x2A++0x00
|
|
hide.byte 0x00 "WF_10,LCD Waveform Register 10"
|
|
hgroup.byte 0x2B++0x00
|
|
hide.byte 0x00 "WF_11,LCD Waveform Register 11"
|
|
hgroup.byte 0x2C++0x00
|
|
hide.byte 0x00 "WF_12,LCD Waveform Register 12"
|
|
hgroup.byte 0x2D++0x00
|
|
hide.byte 0x00 "WF_13,LCD Waveform Register 13"
|
|
hgroup.byte 0x2E++0x00
|
|
hide.byte 0x00 "WF_14,LCD Waveform Register 14"
|
|
hgroup.byte 0x2F++0x00
|
|
hide.byte 0x00 "WF_15,LCD Waveform Register 15"
|
|
hgroup.byte 0x30++0x00
|
|
hide.byte 0x00 "WF_16,LCD Waveform Register 16"
|
|
hgroup.byte 0x31++0x00
|
|
hide.byte 0x00 "WF_17,LCD Waveform Register 17"
|
|
hgroup.byte 0x32++0x00
|
|
hide.byte 0x00 "WF_18,LCD Waveform Register 18"
|
|
hgroup.byte 0x33++0x00
|
|
hide.byte 0x00 "WF_19,LCD Waveform Register 19"
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "WF_20,LCD Waveform Register 20"
|
|
bitfld.byte 0x00 7. " WF_20[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_20[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_20[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_20[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_20[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_20[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_20[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_20[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x35++0x00
|
|
line.byte 0x00 "WF_21,LCD Waveform Register 21"
|
|
bitfld.byte 0x00 7. " WF_21[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_21[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_21[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_21[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_21[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_21[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_21[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_21[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x36++0x00
|
|
line.byte 0x00 "WF_22,LCD Waveform Register 22"
|
|
bitfld.byte 0x00 7. " WF_22[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_22[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_22[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_22[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_22[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_22[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_22[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_22[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x37++0x00
|
|
line.byte 0x00 "WF_23,LCD Waveform Register 23"
|
|
bitfld.byte 0x00 7. " WF_23[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_23[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_23[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_23[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_23[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_23[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_23[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_23[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x38++0x00
|
|
line.byte 0x00 "WF_24,LCD Waveform Register 24"
|
|
bitfld.byte 0x00 7. " WF_24[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_24[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_24[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_24[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_24[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_24[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_24[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_24[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x39++0x00
|
|
line.byte 0x00 "WF_25,LCD Waveform Register 25"
|
|
bitfld.byte 0x00 7. " WF_25[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_25[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_25[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_25[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_25[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_25[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_25[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_25[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x3A++0x00
|
|
line.byte 0x00 "WF_26,LCD Waveform Register 26"
|
|
bitfld.byte 0x00 7. " WF_26[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_26[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_26[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_26[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_26[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_26[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_26[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_26[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x3B++0x00
|
|
line.byte 0x00 "WF_27,LCD Waveform Register 27"
|
|
bitfld.byte 0x00 7. " WF_27[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_27[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_27[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_27[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_27[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_27[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_27[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_27[A] ,Segment-on front/back plane operation" "Off,On"
|
|
hgroup.byte 0x3C++0x00
|
|
hide.byte 0x00 "WF_28,LCD Waveform Register 28"
|
|
hgroup.byte 0x3D++0x00
|
|
hide.byte 0x00 "WF_29,LCD Waveform Register 29"
|
|
hgroup.byte 0x3E++0x00
|
|
hide.byte 0x00 "WF_30,LCD Waveform Register 30"
|
|
hgroup.byte 0x3F++0x00
|
|
hide.byte 0x00 "WF_31,LCD Waveform Register 31"
|
|
hgroup.byte 0x40++0x00
|
|
hide.byte 0x00 "WF_32,LCD Waveform Register 32"
|
|
hgroup.byte 0x41++0x00
|
|
hide.byte 0x00 "WF_33,LCD Waveform Register 33"
|
|
hgroup.byte 0x42++0x00
|
|
hide.byte 0x00 "WF_34,LCD Waveform Register 34"
|
|
hgroup.byte 0x43++0x00
|
|
hide.byte 0x00 "WF_35,LCD Waveform Register 35"
|
|
hgroup.byte 0x44++0x00
|
|
hide.byte 0x00 "WF_36,LCD Waveform Register 36"
|
|
hgroup.byte 0x45++0x00
|
|
hide.byte 0x00 "WF_37,LCD Waveform Register 37"
|
|
hgroup.byte 0x46++0x00
|
|
hide.byte 0x00 "WF_38,LCD Waveform Register 38"
|
|
group.byte 0x47++0x00
|
|
line.byte 0x00 "WF_39,LCD Waveform Register 39"
|
|
bitfld.byte 0x00 7. " WF_39[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_39[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_39[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_39[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_39[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_39[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_39[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_39[A] ,Segment-on front/back plane operation" "Off,On"
|
|
hgroup.byte 0x48++0x00
|
|
hide.byte 0x00 "WF_40,LCD Waveform Register 40"
|
|
hgroup.byte 0x49++0x00
|
|
hide.byte 0x00 "WF_41,LCD Waveform Register 41"
|
|
hgroup.byte 0x4A++0x00
|
|
hide.byte 0x00 "WF_42,LCD Waveform Register 42"
|
|
hgroup.byte 0x4B++0x00
|
|
hide.byte 0x00 "WF_43,LCD Waveform Register 43"
|
|
group.byte 0x4C++0x00
|
|
line.byte 0x00 "WF_44,LCD Waveform Register 44"
|
|
bitfld.byte 0x00 7. " WF_44[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_44[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_44[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_44[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_44[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_44[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_44[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_44[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x4D++0x00
|
|
line.byte 0x00 "WF_45,LCD Waveform Register 45"
|
|
bitfld.byte 0x00 7. " WF_45[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_45[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_45[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_45[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_45[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_45[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_45[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_45[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x4E++0x00
|
|
line.byte 0x00 "WF_46,LCD Waveform Register 46"
|
|
bitfld.byte 0x00 7. " WF_46[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_46[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_46[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_46[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_46[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_46[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_46[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_46[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x4F++0x00
|
|
line.byte 0x00 "WF_47,LCD Waveform Register 47"
|
|
bitfld.byte 0x00 7. " WF_47[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_47[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_47[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_47[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_47[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_47[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_47[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_47[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x50++0x00
|
|
line.byte 0x00 "WF_48,LCD Waveform Register 48"
|
|
bitfld.byte 0x00 7. " WF_48[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_48[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_48[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_48[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_48[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_48[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_48[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_48[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x51++0x00
|
|
line.byte 0x00 "WF_49,LCD Waveform Register 49"
|
|
bitfld.byte 0x00 7. " WF_49[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_49[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_49[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_49[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_49[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_49[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_49[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_49[A] ,Segment-on front/back plane operation" "Off,On"
|
|
hgroup.byte 0x52++0x00
|
|
hide.byte 0x00 "WF_50,LCD Waveform Register 50"
|
|
hgroup.byte 0x53++0x00
|
|
hide.byte 0x00 "WF_51,LCD Waveform Register 51"
|
|
hgroup.byte 0x54++0x00
|
|
hide.byte 0x00 "WF_52,LCD Waveform Register 52"
|
|
hgroup.byte 0x55++0x00
|
|
hide.byte 0x00 "WF_53,LCD Waveform Register 53"
|
|
hgroup.byte 0x56++0x00
|
|
hide.byte 0x00 "WF_54,LCD Waveform Register 54"
|
|
group.byte 0x57++0x00
|
|
line.byte 0x00 "WF_55,LCD Waveform Register 55"
|
|
bitfld.byte 0x00 7. " WF_55[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_55[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_55[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_55[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_55[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_55[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_55[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_55[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x58++0x00
|
|
line.byte 0x00 "WF_56,LCD Waveform Register 56"
|
|
bitfld.byte 0x00 7. " WF_56[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_56[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_56[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_56[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_56[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_56[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_56[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_56[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x59++0x00
|
|
line.byte 0x00 "WF_57,LCD Waveform Register 57"
|
|
bitfld.byte 0x00 7. " WF_57[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_57[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_57[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_57[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_57[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_57[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_57[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_57[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x5A++0x00
|
|
line.byte 0x00 "WF_58,LCD Waveform Register 58"
|
|
bitfld.byte 0x00 7. " WF_58[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_58[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_58[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_58[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_58[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_58[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_58[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_58[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x5B++0x00
|
|
line.byte 0x00 "WF_59,LCD Waveform Register 59"
|
|
bitfld.byte 0x00 7. " WF_59[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_59[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_59[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_59[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_59[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_59[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_59[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_59[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x5C++0x00
|
|
line.byte 0x00 "WF_60,LCD Waveform Register 60"
|
|
bitfld.byte 0x00 7. " WF_60[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_60[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_60[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_60[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_60[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_60[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_60[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_60[A] ,Segment-on front/back plane operation" "Off,On"
|
|
hgroup.byte 0x5D++0x00
|
|
hide.byte 0x00 "WF_61,LCD Waveform Register 61"
|
|
hgroup.byte 0x5E++0x00
|
|
hide.byte 0x00 "WF_62,LCD Waveform Register 62"
|
|
hgroup.byte 0x5F++0x00
|
|
hide.byte 0x00 "WF_63,LCD Waveform Register 63"
|
|
elif cpuis("MKL33Z*VLK*")
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "WF_0,LCD Waveform Register 0"
|
|
bitfld.byte 0x00 7. " WF_0[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_0[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_0[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_0[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_0[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_0[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_0[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_0[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "WF_1,LCD Waveform Register 1"
|
|
bitfld.byte 0x00 7. " WF_1[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_1[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_1[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_1[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_1[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_1[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_1[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_1[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x22++0x00
|
|
line.byte 0x00 "WF_2,LCD Waveform Register 2"
|
|
bitfld.byte 0x00 7. " WF_2[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_2[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_2[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_2[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_2[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_2[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_2[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_2[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x23++0x00
|
|
line.byte 0x00 "WF_3,LCD Waveform Register 3"
|
|
bitfld.byte 0x00 7. " WF_3[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_3[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_3[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_3[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_3[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_3[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_3[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_3[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "WF_4,LCD Waveform Register 4"
|
|
bitfld.byte 0x00 7. " WF_4[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_4[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_4[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_4[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_4[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_4[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_4[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_4[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x25++0x00
|
|
line.byte 0x00 "WF_5,LCD Waveform Register 5"
|
|
bitfld.byte 0x00 7. " WF_5[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_5[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_5[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_5[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_5[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_5[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_5[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_5[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "WF_6,LCD Waveform Register 6"
|
|
bitfld.byte 0x00 7. " WF_6[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_6[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_6[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_6[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_6[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_6[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_6[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_6[A] ,Segment-on front/back plane operation" "Off,On"
|
|
hgroup.byte 0x27++0x00
|
|
hide.byte 0x00 "WF_7,LCD Waveform Register 7"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "WF_8,LCD Waveform Register 8"
|
|
bitfld.byte 0x00 7. " WF_8[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_8[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_8[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_8[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_8[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_8[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_8[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_8[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x29++0x00
|
|
line.byte 0x00 "WF_9,LCD Waveform Register 9"
|
|
bitfld.byte 0x00 7. " WF_9[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_9[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_9[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_9[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_9[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_9[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_9[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_9[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x2A++0x00
|
|
line.byte 0x00 "WF_10,LCD Waveform Register 10"
|
|
bitfld.byte 0x00 7. " WF_10[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_10[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_10[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_10[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_10[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_10[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_10[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_10[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x2B++0x00
|
|
line.byte 0x00 "WF_11,LCD Waveform Register 11"
|
|
bitfld.byte 0x00 7. " WF_11[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_11[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_11[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_11[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_11[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_11[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_11[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_11[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x2C++0x00
|
|
line.byte 0x00 "WF_12,LCD Waveform Register 12"
|
|
bitfld.byte 0x00 7. " WF_12[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_12[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_12[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_12[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_12[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_12[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_12[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_12[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x2D++0x00
|
|
line.byte 0x00 "WF_13,LCD Waveform Register 13"
|
|
bitfld.byte 0x00 7. " WF_13[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_13[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_13[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_13[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_13[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_13[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_13[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_13[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x2E++0x00
|
|
line.byte 0x00 "WF_14,LCD Waveform Register 14"
|
|
bitfld.byte 0x00 7. " WF_14[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_14[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_14[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_14[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_14[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_14[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_14[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_14[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x2F++0x00
|
|
line.byte 0x00 "WF_15,LCD Waveform Register 15"
|
|
bitfld.byte 0x00 7. " WF_15[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_15[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_15[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_15[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_15[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_15[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_15[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_15[A] ,Segment-on front/back plane operation" "Off,On"
|
|
hgroup.byte 0x30++0x00
|
|
hide.byte 0x00 "WF_16,LCD Waveform Register 16"
|
|
hgroup.byte 0x31++0x00
|
|
hide.byte 0x00 "WF_17,LCD Waveform Register 17"
|
|
hgroup.byte 0x32++0x00
|
|
hide.byte 0x00 "WF_18,LCD Waveform Register 18"
|
|
hgroup.byte 0x33++0x00
|
|
hide.byte 0x00 "WF_19,LCD Waveform Register 19"
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "WF_20,LCD Waveform Register 20"
|
|
bitfld.byte 0x00 7. " WF_20[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_20[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_20[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_20[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_20[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_20[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_20[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_20[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x35++0x00
|
|
line.byte 0x00 "WF_21,LCD Waveform Register 21"
|
|
bitfld.byte 0x00 7. " WF_21[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_21[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_21[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_21[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_21[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_21[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_21[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_21[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x36++0x00
|
|
line.byte 0x00 "WF_22,LCD Waveform Register 22"
|
|
bitfld.byte 0x00 7. " WF_22[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_22[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_22[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_22[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_22[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_22[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_22[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_22[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x37++0x00
|
|
line.byte 0x00 "WF_23,LCD Waveform Register 23"
|
|
bitfld.byte 0x00 7. " WF_23[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_23[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_23[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_23[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_23[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_23[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_23[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_23[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x38++0x00
|
|
line.byte 0x00 "WF_24,LCD Waveform Register 24"
|
|
bitfld.byte 0x00 7. " WF_24[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_24[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_24[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_24[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_24[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_24[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_24[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_24[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x39++0x00
|
|
line.byte 0x00 "WF_25,LCD Waveform Register 25"
|
|
bitfld.byte 0x00 7. " WF_25[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_25[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_25[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_25[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_25[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_25[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_25[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_25[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x3A++0x00
|
|
line.byte 0x00 "WF_26,LCD Waveform Register 26"
|
|
bitfld.byte 0x00 7. " WF_26[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_26[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_26[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_26[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_26[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_26[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_26[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_26[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x3B++0x00
|
|
line.byte 0x00 "WF_27,LCD Waveform Register 27"
|
|
bitfld.byte 0x00 7. " WF_27[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_27[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_27[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_27[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_27[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_27[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_27[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_27[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x3C++0x00
|
|
line.byte 0x00 "WF_28,LCD Waveform Register 28"
|
|
bitfld.byte 0x00 7. " WF_28[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_28[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_28[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_28[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_28[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_28[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_28[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_28[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x3D++0x00
|
|
line.byte 0x00 "WF_29,LCD Waveform Register 29"
|
|
bitfld.byte 0x00 7. " WF_29[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_29[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_29[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_29[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_29[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_29[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_29[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_29[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x3E++0x00
|
|
line.byte 0x00 "WF_30,LCD Waveform Register 30"
|
|
bitfld.byte 0x00 7. " WF_30[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_30[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_30[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_30[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_30[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_30[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_30[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_30[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x3F++0x00
|
|
line.byte 0x00 "WF_31,LCD Waveform Register 31"
|
|
bitfld.byte 0x00 7. " WF_31[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_31[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_31[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_31[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_31[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_31[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_31[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_31[A] ,Segment-on front/back plane operation" "Off,On"
|
|
hgroup.byte 0x40++0x00
|
|
hide.byte 0x00 "WF_32,LCD Waveform Register 32"
|
|
hgroup.byte 0x41++0x00
|
|
hide.byte 0x00 "WF_33,LCD Waveform Register 33"
|
|
hgroup.byte 0x42++0x00
|
|
hide.byte 0x00 "WF_34,LCD Waveform Register 34"
|
|
hgroup.byte 0x43++0x00
|
|
hide.byte 0x00 "WF_35,LCD Waveform Register 35"
|
|
hgroup.byte 0x44++0x00
|
|
hide.byte 0x00 "WF_36,LCD Waveform Register 36"
|
|
hgroup.byte 0x45++0x00
|
|
hide.byte 0x00 "WF_37,LCD Waveform Register 37"
|
|
hgroup.byte 0x46++0x00
|
|
hide.byte 0x00 "WF_38,LCD Waveform Register 38"
|
|
group.byte 0x47++0x00
|
|
line.byte 0x00 "WF_39,LCD Waveform Register 39"
|
|
bitfld.byte 0x00 7. " WF_39[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_39[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_39[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_39[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_39[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_39[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_39[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_39[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x48++0x00
|
|
line.byte 0x00 "WF_40,LCD Waveform Register 40"
|
|
bitfld.byte 0x00 7. " WF_40[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_40[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_40[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_40[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_40[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_40[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_40[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_40[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x49++0x00
|
|
line.byte 0x00 "WF_41,LCD Waveform Register 41"
|
|
bitfld.byte 0x00 7. " WF_41[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_41[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_41[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_41[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_41[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_41[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_41[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_41[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x4A++0x00
|
|
line.byte 0x00 "WF_42,LCD Waveform Register 42"
|
|
bitfld.byte 0x00 7. " WF_42[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_42[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_42[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_42[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_42[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_42[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_42[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_42[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x4B++0x00
|
|
line.byte 0x00 "WF_43,LCD Waveform Register 43"
|
|
bitfld.byte 0x00 7. " WF_43[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_43[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_43[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_43[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_43[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_43[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_43[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_43[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x4C++0x00
|
|
line.byte 0x00 "WF_44,LCD Waveform Register 44"
|
|
bitfld.byte 0x00 7. " WF_44[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_44[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_44[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_44[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_44[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_44[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_44[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_44[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x4D++0x00
|
|
line.byte 0x00 "WF_45,LCD Waveform Register 45"
|
|
bitfld.byte 0x00 7. " WF_45[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_45[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_45[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_45[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_45[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_45[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_45[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_45[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x4E++0x00
|
|
line.byte 0x00 "WF_46,LCD Waveform Register 46"
|
|
bitfld.byte 0x00 7. " WF_46[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_46[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_46[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_46[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_46[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_46[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_46[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_46[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x4F++0x00
|
|
line.byte 0x00 "WF_47,LCD Waveform Register 47"
|
|
bitfld.byte 0x00 7. " WF_47[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_47[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_47[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_47[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_47[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_47[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_47[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_47[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x50++0x00
|
|
line.byte 0x00 "WF_48,LCD Waveform Register 48"
|
|
bitfld.byte 0x00 7. " WF_48[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_48[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_48[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_48[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_48[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_48[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_48[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_48[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x51++0x00
|
|
line.byte 0x00 "WF_49,LCD Waveform Register 49"
|
|
bitfld.byte 0x00 7. " WF_49[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_49[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_49[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_49[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_49[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_49[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_49[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_49[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x52++0x00
|
|
line.byte 0x00 "WF_50,LCD Waveform Register 50"
|
|
bitfld.byte 0x00 7. " WF_50[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_50[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_50[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_50[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_50[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_50[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_50[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_50[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x53++0x00
|
|
line.byte 0x00 "WF_51,LCD Waveform Register 51"
|
|
bitfld.byte 0x00 7. " WF_51[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_51[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_51[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_51[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_51[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_51[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_51[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_51[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x54++0x00
|
|
line.byte 0x00 "WF_52,LCD Waveform Register 52"
|
|
bitfld.byte 0x00 7. " WF_52[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_52[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_52[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_52[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_52[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_52[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_52[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_52[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x55++0x00
|
|
line.byte 0x00 "WF_53,LCD Waveform Register 53"
|
|
bitfld.byte 0x00 7. " WF_53[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_53[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_53[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_53[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_53[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_53[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_53[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_53[A] ,Segment-on front/back plane operation" "Off,On"
|
|
hgroup.byte 0x56++0x00
|
|
hide.byte 0x00 "WF_54,LCD Waveform Register 54"
|
|
group.byte 0x57++0x00
|
|
line.byte 0x00 "WF_55,LCD Waveform Register 55"
|
|
bitfld.byte 0x00 7. " WF_55[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_55[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_55[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_55[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_55[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_55[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_55[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_55[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x58++0x00
|
|
line.byte 0x00 "WF_56,LCD Waveform Register 56"
|
|
bitfld.byte 0x00 7. " WF_56[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_56[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_56[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_56[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_56[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_56[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_56[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_56[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x59++0x00
|
|
line.byte 0x00 "WF_57,LCD Waveform Register 57"
|
|
bitfld.byte 0x00 7. " WF_57[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_57[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_57[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_57[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_57[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_57[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_57[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_57[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x5A++0x00
|
|
line.byte 0x00 "WF_58,LCD Waveform Register 58"
|
|
bitfld.byte 0x00 7. " WF_58[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_58[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_58[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_58[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_58[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_58[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_58[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_58[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x5B++0x00
|
|
line.byte 0x00 "WF_59,LCD Waveform Register 59"
|
|
bitfld.byte 0x00 7. " WF_59[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_59[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_59[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_59[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_59[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_59[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_59[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_59[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x5C++0x00
|
|
line.byte 0x00 "WF_60,LCD Waveform Register 60"
|
|
bitfld.byte 0x00 7. " WF_60[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_60[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_60[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_60[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_60[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_60[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_60[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_60[A] ,Segment-on front/back plane operation" "Off,On"
|
|
hgroup.byte 0x5D++0x00
|
|
hide.byte 0x00 "WF_61,LCD Waveform Register 61"
|
|
hgroup.byte 0x5E++0x00
|
|
hide.byte 0x00 "WF_62,LCD Waveform Register 62"
|
|
hgroup.byte 0x5F++0x00
|
|
hide.byte 0x00 "WF_63,LCD Waveform Register 63"
|
|
elif cpuis("MKL43Z*VLH*")||cpuis("MKL43Z*VMP*")||cpuis("MKL46Z*VLH*")||cpuis("MKL46Z*VMP*")
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "WF_0,LCD Waveform Register 0"
|
|
bitfld.byte 0x00 7. " WF_0[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_0[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_0[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_0[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_0[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_0[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_0[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_0[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "WF_1,LCD Waveform Register 1"
|
|
bitfld.byte 0x00 7. " WF_1[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_1[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_1[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_1[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_1[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_1[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_1[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_1[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x22++0x00
|
|
line.byte 0x00 "WF_2,LCD Waveform Register 2"
|
|
bitfld.byte 0x00 7. " WF_2[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_2[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_2[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_2[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_2[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_2[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_2[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_2[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x23++0x00
|
|
line.byte 0x00 "WF_3,LCD Waveform Register 3"
|
|
bitfld.byte 0x00 7. " WF_3[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_3[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_3[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_3[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_3[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_3[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_3[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_3[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "WF_4,LCD Waveform Register 4"
|
|
bitfld.byte 0x00 7. " WF_4[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_4[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_4[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_4[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_4[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_4[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_4[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_4[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x25++0x00
|
|
line.byte 0x00 "WF_5,LCD Waveform Register 5"
|
|
bitfld.byte 0x00 7. " WF_5[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_5[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_5[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_5[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_5[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_5[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_5[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_5[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "WF_6,LCD Waveform Register 6"
|
|
bitfld.byte 0x00 7. " WF_6[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_6[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_6[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_6[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_6[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_6[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_6[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_6[A] ,Segment-on front/back plane operation" "Off,On"
|
|
hgroup.byte 0x27++0x00
|
|
hide.byte 0x00 "WF_7,LCD Waveform Register 7"
|
|
hgroup.byte 0x28++0x00
|
|
hide.byte 0x00 "WF_8,LCD Waveform Register 8"
|
|
hgroup.byte 0x29++0x00
|
|
hide.byte 0x00 "WF_9,LCD Waveform Register 9"
|
|
hgroup.byte 0x2A++0x00
|
|
hide.byte 0x00 "WF_10,LCD Waveform Register 10"
|
|
hgroup.byte 0x2B++0x00
|
|
hide.byte 0x00 "WF_11,LCD Waveform Register 11"
|
|
group.byte 0x2C++0x00
|
|
line.byte 0x00 "WF_12,LCD Waveform Register 12"
|
|
bitfld.byte 0x00 7. " WF_12[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_12[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_12[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_12[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_12[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_12[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_12[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_12[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x2D++0x00
|
|
line.byte 0x00 "WF_13,LCD Waveform Register 13"
|
|
bitfld.byte 0x00 7. " WF_13[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_13[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_13[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_13[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_13[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_13[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_13[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_13[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x2E++0x00
|
|
line.byte 0x00 "WF_14,LCD Waveform Register 14"
|
|
bitfld.byte 0x00 7. " WF_14[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_14[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_14[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_14[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_14[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_14[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_14[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_14[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x2F++0x00
|
|
line.byte 0x00 "WF_15,LCD Waveform Register 15"
|
|
bitfld.byte 0x00 7. " WF_15[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_15[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_15[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_15[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_15[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_15[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_15[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_15[A] ,Segment-on front/back plane operation" "Off,On"
|
|
hgroup.byte 0x30++0x00
|
|
hide.byte 0x00 "WF_16,LCD Waveform Register 16"
|
|
hgroup.byte 0x31++0x00
|
|
hide.byte 0x00 "WF_17,LCD Waveform Register 17"
|
|
hgroup.byte 0x32++0x00
|
|
hide.byte 0x00 "WF_18,LCD Waveform Register 18"
|
|
hgroup.byte 0x33++0x00
|
|
hide.byte 0x00 "WF_19,LCD Waveform Register 19"
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "WF_20,LCD Waveform Register 20"
|
|
bitfld.byte 0x00 7. " WF_20[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_20[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_20[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_20[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_20[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_20[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_20[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_20[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x35++0x00
|
|
line.byte 0x00 "WF_21,LCD Waveform Register 21"
|
|
bitfld.byte 0x00 7. " WF_21[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_21[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_21[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_21[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_21[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_21[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_21[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_21[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x36++0x00
|
|
line.byte 0x00 "WF_22,LCD Waveform Register 22"
|
|
bitfld.byte 0x00 7. " WF_22[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_22[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_22[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_22[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_22[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_22[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_22[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_22[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x37++0x00
|
|
line.byte 0x00 "WF_23,LCD Waveform Register 23"
|
|
bitfld.byte 0x00 7. " WF_23[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_23[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_23[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_23[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_23[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_23[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_23[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_23[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x38++0x00
|
|
line.byte 0x00 "WF_24,LCD Waveform Register 24"
|
|
bitfld.byte 0x00 7. " WF_24[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_24[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_24[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_24[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_24[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_24[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_24[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_24[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x39++0x00
|
|
line.byte 0x00 "WF_25,LCD Waveform Register 25"
|
|
bitfld.byte 0x00 7. " WF_25[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_25[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_25[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_25[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_25[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_25[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_25[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_25[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x3A++0x00
|
|
line.byte 0x00 "WF_26,LCD Waveform Register 26"
|
|
bitfld.byte 0x00 7. " WF_26[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_26[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_26[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_26[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_26[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_26[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_26[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_26[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x3B++0x00
|
|
line.byte 0x00 "WF_27,LCD Waveform Register 27"
|
|
bitfld.byte 0x00 7. " WF_27[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_27[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_27[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_27[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_27[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_27[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_27[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_27[A] ,Segment-on front/back plane operation" "Off,On"
|
|
hgroup.byte 0x3C++0x00
|
|
hide.byte 0x00 "WF_28,LCD Waveform Register 28"
|
|
hgroup.byte 0x3D++0x00
|
|
hide.byte 0x00 "WF_29,LCD Waveform Register 29"
|
|
hgroup.byte 0x3E++0x00
|
|
hide.byte 0x00 "WF_30,LCD Waveform Register 30"
|
|
hgroup.byte 0x3F++0x00
|
|
hide.byte 0x00 "WF_31,LCD Waveform Register 31"
|
|
hgroup.byte 0x40++0x00
|
|
hide.byte 0x00 "WF_32,LCD Waveform Register 32"
|
|
hgroup.byte 0x41++0x00
|
|
hide.byte 0x00 "WF_33,LCD Waveform Register 33"
|
|
hgroup.byte 0x42++0x00
|
|
hide.byte 0x00 "WF_34,LCD Waveform Register 34"
|
|
hgroup.byte 0x43++0x00
|
|
hide.byte 0x00 "WF_35,LCD Waveform Register 35"
|
|
hgroup.byte 0x44++0x00
|
|
hide.byte 0x00 "WF_36,LCD Waveform Register 36"
|
|
hgroup.byte 0x45++0x00
|
|
hide.byte 0x00 "WF_37,LCD Waveform Register 37"
|
|
hgroup.byte 0x46++0x00
|
|
hide.byte 0x00 "WF_38,LCD Waveform Register 38"
|
|
group.byte 0x47++0x00
|
|
line.byte 0x00 "WF_39,LCD Waveform Register 39"
|
|
bitfld.byte 0x00 7. " WF_39[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_39[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_39[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_39[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_39[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_39[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_39[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_39[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x48++0x00
|
|
line.byte 0x00 "WF_40,LCD Waveform Register 40"
|
|
bitfld.byte 0x00 7. " WF_40[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_40[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_40[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_40[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_40[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_40[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_40[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_40[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x49++0x00
|
|
line.byte 0x00 "WF_41,LCD Waveform Register 41"
|
|
bitfld.byte 0x00 7. " WF_41[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_41[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_41[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_41[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_41[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_41[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_41[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_41[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x4A++0x00
|
|
line.byte 0x00 "WF_42,LCD Waveform Register 42"
|
|
bitfld.byte 0x00 7. " WF_42[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_42[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_42[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_42[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_42[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_42[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_42[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_42[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x4B++0x00
|
|
line.byte 0x00 "WF_43,LCD Waveform Register 43"
|
|
bitfld.byte 0x00 7. " WF_43[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_43[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_43[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_43[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_43[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_43[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_43[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_43[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x4C++0x00
|
|
line.byte 0x00 "WF_44,LCD Waveform Register 44"
|
|
bitfld.byte 0x00 7. " WF_44[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_44[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_44[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_44[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_44[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_44[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_44[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_44[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x4D++0x00
|
|
line.byte 0x00 "WF_45,LCD Waveform Register 45"
|
|
bitfld.byte 0x00 7. " WF_45[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_45[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_45[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_45[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_45[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_45[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_45[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_45[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x4E++0x00
|
|
line.byte 0x00 "WF_46,LCD Waveform Register 46"
|
|
bitfld.byte 0x00 7. " WF_46[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_46[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_46[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_46[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_46[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_46[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_46[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_46[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x4F++0x00
|
|
line.byte 0x00 "WF_47,LCD Waveform Register 47"
|
|
bitfld.byte 0x00 7. " WF_47[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_47[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_47[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_47[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_47[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_47[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_47[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_47[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x50++0x00
|
|
line.byte 0x00 "WF_48,LCD Waveform Register 48"
|
|
bitfld.byte 0x00 7. " WF_48[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_48[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_48[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_48[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_48[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_48[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_48[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_48[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x51++0x00
|
|
line.byte 0x00 "WF_49,LCD Waveform Register 49"
|
|
bitfld.byte 0x00 7. " WF_49[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_49[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_49[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_49[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_49[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_49[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_49[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_49[A] ,Segment-on front/back plane operation" "Off,On"
|
|
hgroup.byte 0x52++0x00
|
|
hide.byte 0x00 "WF_50,LCD Waveform Register 50"
|
|
hgroup.byte 0x53++0x00
|
|
hide.byte 0x00 "WF_51,LCD Waveform Register 51"
|
|
hgroup.byte 0x54++0x00
|
|
hide.byte 0x00 "WF_52,LCD Waveform Register 52"
|
|
hgroup.byte 0x55++0x00
|
|
hide.byte 0x00 "WF_53,LCD Waveform Register 53"
|
|
hgroup.byte 0x56++0x00
|
|
hide.byte 0x00 "WF_54,LCD Waveform Register 54"
|
|
hgroup.byte 0x57++0x00
|
|
hide.byte 0x00 "WF_55,LCD Waveform Register 55"
|
|
hgroup.byte 0x58++0x00
|
|
hide.byte 0x00 "WF_56,LCD Waveform Register 56"
|
|
hgroup.byte 0x59++0x00
|
|
hide.byte 0x00 "WF_57,LCD Waveform Register 57"
|
|
hgroup.byte 0x5A++0x00
|
|
hide.byte 0x00 "WF_58,LCD Waveform Register 58"
|
|
group.byte 0x5B++0x00
|
|
line.byte 0x00 "WF_59,LCD Waveform Register 59"
|
|
bitfld.byte 0x00 7. " WF_59[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_59[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_59[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_59[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_59[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_59[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_59[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_59[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x5C++0x00
|
|
line.byte 0x00 "WF_60,LCD Waveform Register 60"
|
|
bitfld.byte 0x00 7. " WF_60[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_60[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_60[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_60[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_60[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_60[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_60[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_60[A] ,Segment-on front/back plane operation" "Off,On"
|
|
hgroup.byte 0x5D++0x00
|
|
hide.byte 0x00 "WF_61,LCD Waveform Register 61"
|
|
hgroup.byte 0x5E++0x00
|
|
hide.byte 0x00 "WF_62,LCD Waveform Register 62"
|
|
hgroup.byte 0x5F++0x00
|
|
hide.byte 0x00 "WF_63,LCD Waveform Register 63"
|
|
else
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "WF_0,LCD Waveform Register 0"
|
|
bitfld.byte 0x00 7. " WF_0[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_0[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_0[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_0[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_0[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_0[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_0[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_0[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "WF_1,LCD Waveform Register 1"
|
|
bitfld.byte 0x00 7. " WF_1[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_1[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_1[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_1[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_1[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_1[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_1[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_1[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x22++0x00
|
|
line.byte 0x00 "WF_2,LCD Waveform Register 2"
|
|
bitfld.byte 0x00 7. " WF_2[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_2[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_2[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_2[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_2[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_2[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_2[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_2[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x23++0x00
|
|
line.byte 0x00 "WF_3,LCD Waveform Register 3"
|
|
bitfld.byte 0x00 7. " WF_3[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_3[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_3[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_3[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_3[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_3[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_3[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_3[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "WF_4,LCD Waveform Register 4"
|
|
bitfld.byte 0x00 7. " WF_4[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_4[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_4[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_4[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_4[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_4[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_4[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_4[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x25++0x00
|
|
line.byte 0x00 "WF_5,LCD Waveform Register 5"
|
|
bitfld.byte 0x00 7. " WF_5[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_5[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_5[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_5[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_5[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_5[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_5[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_5[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "WF_6,LCD Waveform Register 6"
|
|
bitfld.byte 0x00 7. " WF_6[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_6[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_6[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_6[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_6[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_6[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_6[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_6[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x27++0x00
|
|
line.byte 0x00 "WF_7,LCD Waveform Register 7"
|
|
bitfld.byte 0x00 7. " WF_7[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_7[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_7[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_7[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_7[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_7[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_7[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_7[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "WF_8,LCD Waveform Register 8"
|
|
bitfld.byte 0x00 7. " WF_8[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_8[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_8[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_8[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_8[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_8[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_8[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_8[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x29++0x00
|
|
line.byte 0x00 "WF_9,LCD Waveform Register 9"
|
|
bitfld.byte 0x00 7. " WF_9[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_9[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_9[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_9[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_9[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_9[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_9[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_9[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x2A++0x00
|
|
line.byte 0x00 "WF_10,LCD Waveform Register 10"
|
|
bitfld.byte 0x00 7. " WF_10[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_10[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_10[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_10[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_10[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_10[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_10[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_10[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x2B++0x00
|
|
line.byte 0x00 "WF_11,LCD Waveform Register 11"
|
|
bitfld.byte 0x00 7. " WF_11[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_11[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_11[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_11[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_11[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_11[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_11[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_11[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x2C++0x00
|
|
line.byte 0x00 "WF_12,LCD Waveform Register 12"
|
|
bitfld.byte 0x00 7. " WF_12[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_12[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_12[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_12[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_12[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_12[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_12[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_12[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x2D++0x00
|
|
line.byte 0x00 "WF_13,LCD Waveform Register 13"
|
|
bitfld.byte 0x00 7. " WF_13[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_13[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_13[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_13[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_13[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_13[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_13[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_13[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x2E++0x00
|
|
line.byte 0x00 "WF_14,LCD Waveform Register 14"
|
|
bitfld.byte 0x00 7. " WF_14[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_14[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_14[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_14[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_14[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_14[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_14[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_14[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x2F++0x00
|
|
line.byte 0x00 "WF_15,LCD Waveform Register 15"
|
|
bitfld.byte 0x00 7. " WF_15[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_15[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_15[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_15[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_15[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_15[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_15[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_15[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x30++0x00
|
|
line.byte 0x00 "WF_16,LCD Waveform Register 16"
|
|
bitfld.byte 0x00 7. " WF_16[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_16[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_16[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_16[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_16[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_16[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_16[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_16[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x31++0x00
|
|
line.byte 0x00 "WF_17,LCD Waveform Register 17"
|
|
bitfld.byte 0x00 7. " WF_17[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_17[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_17[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_17[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_17[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_17[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_17[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_17[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x32++0x00
|
|
line.byte 0x00 "WF_18,LCD Waveform Register 18"
|
|
bitfld.byte 0x00 7. " WF_18[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_18[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_18[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_18[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_18[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_18[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_18[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_18[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x33++0x00
|
|
line.byte 0x00 "WF_19,LCD Waveform Register 19"
|
|
bitfld.byte 0x00 7. " WF_19[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_19[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_19[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_19[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_19[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_19[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_19[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_19[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "WF_20,LCD Waveform Register 20"
|
|
bitfld.byte 0x00 7. " WF_20[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_20[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_20[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_20[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_20[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_20[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_20[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_20[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x35++0x00
|
|
line.byte 0x00 "WF_21,LCD Waveform Register 21"
|
|
bitfld.byte 0x00 7. " WF_21[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_21[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_21[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_21[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_21[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_21[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_21[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_21[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x36++0x00
|
|
line.byte 0x00 "WF_22,LCD Waveform Register 22"
|
|
bitfld.byte 0x00 7. " WF_22[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_22[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_22[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_22[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_22[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_22[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_22[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_22[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x37++0x00
|
|
line.byte 0x00 "WF_23,LCD Waveform Register 23"
|
|
bitfld.byte 0x00 7. " WF_23[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_23[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_23[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_23[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_23[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_23[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_23[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_23[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x38++0x00
|
|
line.byte 0x00 "WF_24,LCD Waveform Register 24"
|
|
bitfld.byte 0x00 7. " WF_24[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_24[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_24[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_24[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_24[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_24[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_24[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_24[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x39++0x00
|
|
line.byte 0x00 "WF_25,LCD Waveform Register 25"
|
|
bitfld.byte 0x00 7. " WF_25[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_25[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_25[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_25[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_25[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_25[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_25[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_25[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x3A++0x00
|
|
line.byte 0x00 "WF_26,LCD Waveform Register 26"
|
|
bitfld.byte 0x00 7. " WF_26[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_26[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_26[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_26[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_26[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_26[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_26[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_26[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x3B++0x00
|
|
line.byte 0x00 "WF_27,LCD Waveform Register 27"
|
|
bitfld.byte 0x00 7. " WF_27[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_27[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_27[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_27[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_27[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_27[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_27[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_27[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x3C++0x00
|
|
line.byte 0x00 "WF_28,LCD Waveform Register 28"
|
|
bitfld.byte 0x00 7. " WF_28[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_28[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_28[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_28[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_28[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_28[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_28[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_28[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x3D++0x00
|
|
line.byte 0x00 "WF_29,LCD Waveform Register 29"
|
|
bitfld.byte 0x00 7. " WF_29[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_29[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_29[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_29[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_29[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_29[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_29[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_29[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x3E++0x00
|
|
line.byte 0x00 "WF_30,LCD Waveform Register 30"
|
|
bitfld.byte 0x00 7. " WF_30[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_30[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_30[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_30[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_30[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_30[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_30[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_30[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x3F++0x00
|
|
line.byte 0x00 "WF_31,LCD Waveform Register 31"
|
|
bitfld.byte 0x00 7. " WF_31[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_31[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_31[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_31[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_31[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_31[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_31[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_31[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x40++0x00
|
|
line.byte 0x00 "WF_32,LCD Waveform Register 32"
|
|
bitfld.byte 0x00 7. " WF_32[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_32[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_32[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_32[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_32[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_32[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_32[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_32[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x41++0x00
|
|
line.byte 0x00 "WF_33,LCD Waveform Register 33"
|
|
bitfld.byte 0x00 7. " WF_33[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_33[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_33[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_33[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_33[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_33[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_33[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_33[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x42++0x00
|
|
line.byte 0x00 "WF_34,LCD Waveform Register 34"
|
|
bitfld.byte 0x00 7. " WF_34[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_34[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_34[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_34[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_34[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_34[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_34[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_34[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x43++0x00
|
|
line.byte 0x00 "WF_35,LCD Waveform Register 35"
|
|
bitfld.byte 0x00 7. " WF_35[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_35[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_35[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_35[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_35[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_35[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_35[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_35[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x44++0x00
|
|
line.byte 0x00 "WF_36,LCD Waveform Register 36"
|
|
bitfld.byte 0x00 7. " WF_36[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_36[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_36[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_36[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_36[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_36[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_36[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_36[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x45++0x00
|
|
line.byte 0x00 "WF_37,LCD Waveform Register 37"
|
|
bitfld.byte 0x00 7. " WF_37[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_37[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_37[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_37[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_37[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_37[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_37[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_37[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x46++0x00
|
|
line.byte 0x00 "WF_38,LCD Waveform Register 38"
|
|
bitfld.byte 0x00 7. " WF_38[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_38[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_38[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_38[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_38[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_38[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_38[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_38[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x47++0x00
|
|
line.byte 0x00 "WF_39,LCD Waveform Register 39"
|
|
bitfld.byte 0x00 7. " WF_39[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_39[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_39[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_39[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_39[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_39[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_39[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_39[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x48++0x00
|
|
line.byte 0x00 "WF_40,LCD Waveform Register 40"
|
|
bitfld.byte 0x00 7. " WF_40[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_40[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_40[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_40[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_40[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_40[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_40[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_40[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x49++0x00
|
|
line.byte 0x00 "WF_41,LCD Waveform Register 41"
|
|
bitfld.byte 0x00 7. " WF_41[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_41[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_41[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_41[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_41[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_41[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_41[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_41[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x4A++0x00
|
|
line.byte 0x00 "WF_42,LCD Waveform Register 42"
|
|
bitfld.byte 0x00 7. " WF_42[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_42[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_42[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_42[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_42[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_42[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_42[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_42[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x4B++0x00
|
|
line.byte 0x00 "WF_43,LCD Waveform Register 43"
|
|
bitfld.byte 0x00 7. " WF_43[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_43[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_43[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_43[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_43[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_43[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_43[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_43[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x4C++0x00
|
|
line.byte 0x00 "WF_44,LCD Waveform Register 44"
|
|
bitfld.byte 0x00 7. " WF_44[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_44[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_44[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_44[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_44[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_44[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_44[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_44[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x4D++0x00
|
|
line.byte 0x00 "WF_45,LCD Waveform Register 45"
|
|
bitfld.byte 0x00 7. " WF_45[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_45[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_45[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_45[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_45[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_45[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_45[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_45[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x4E++0x00
|
|
line.byte 0x00 "WF_46,LCD Waveform Register 46"
|
|
bitfld.byte 0x00 7. " WF_46[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_46[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_46[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_46[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_46[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_46[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_46[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_46[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x4F++0x00
|
|
line.byte 0x00 "WF_47,LCD Waveform Register 47"
|
|
bitfld.byte 0x00 7. " WF_47[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_47[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_47[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_47[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_47[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_47[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_47[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_47[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x50++0x00
|
|
line.byte 0x00 "WF_48,LCD Waveform Register 48"
|
|
bitfld.byte 0x00 7. " WF_48[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_48[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_48[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_48[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_48[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_48[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_48[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_48[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x51++0x00
|
|
line.byte 0x00 "WF_49,LCD Waveform Register 49"
|
|
bitfld.byte 0x00 7. " WF_49[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_49[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_49[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_49[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_49[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_49[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_49[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_49[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x52++0x00
|
|
line.byte 0x00 "WF_50,LCD Waveform Register 50"
|
|
bitfld.byte 0x00 7. " WF_50[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_50[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_50[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_50[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_50[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_50[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_50[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_50[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x53++0x00
|
|
line.byte 0x00 "WF_51,LCD Waveform Register 51"
|
|
bitfld.byte 0x00 7. " WF_51[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_51[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_51[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_51[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_51[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_51[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_51[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_51[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x54++0x00
|
|
line.byte 0x00 "WF_52,LCD Waveform Register 52"
|
|
bitfld.byte 0x00 7. " WF_52[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_52[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_52[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_52[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_52[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_52[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_52[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_52[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x55++0x00
|
|
line.byte 0x00 "WF_53,LCD Waveform Register 53"
|
|
bitfld.byte 0x00 7. " WF_53[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_53[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_53[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_53[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_53[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_53[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_53[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_53[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x56++0x00
|
|
line.byte 0x00 "WF_54,LCD Waveform Register 54"
|
|
bitfld.byte 0x00 7. " WF_54[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_54[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_54[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_54[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_54[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_54[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_54[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_54[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x57++0x00
|
|
line.byte 0x00 "WF_55,LCD Waveform Register 55"
|
|
bitfld.byte 0x00 7. " WF_55[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_55[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_55[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_55[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_55[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_55[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_55[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_55[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x58++0x00
|
|
line.byte 0x00 "WF_56,LCD Waveform Register 56"
|
|
bitfld.byte 0x00 7. " WF_56[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_56[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_56[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_56[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_56[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_56[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_56[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_56[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x59++0x00
|
|
line.byte 0x00 "WF_57,LCD Waveform Register 57"
|
|
bitfld.byte 0x00 7. " WF_57[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_57[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_57[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_57[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_57[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_57[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_57[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_57[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x5A++0x00
|
|
line.byte 0x00 "WF_58,LCD Waveform Register 58"
|
|
bitfld.byte 0x00 7. " WF_58[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_58[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_58[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_58[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_58[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_58[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_58[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_58[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x5B++0x00
|
|
line.byte 0x00 "WF_59,LCD Waveform Register 59"
|
|
bitfld.byte 0x00 7. " WF_59[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_59[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_59[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_59[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_59[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_59[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_59[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_59[A] ,Segment-on front/back plane operation" "Off,On"
|
|
group.byte 0x5C++0x00
|
|
line.byte 0x00 "WF_60,LCD Waveform Register 60"
|
|
bitfld.byte 0x00 7. " WF_60[H] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 6. " WF_60[G] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 5. " WF_60[F] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 4. " WF_60[E] ,Segment-on front/back plane operation" "Off,On"
|
|
newline
|
|
bitfld.byte 0x00 3. " WF_60[D] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 2. " WF_60[C] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 1. " WF_60[B] ,Segment-on front/back plane operation" "Off,On"
|
|
bitfld.byte 0x00 0. " WF_60[A] ,Segment-on front/back plane operation" "Off,On"
|
|
hgroup.byte 0x5D++0x00
|
|
hide.byte 0x00 "WF_61,LCD Waveform Register 61"
|
|
hgroup.byte 0x5E++0x00
|
|
hide.byte 0x00 "WF_62,LCD Waveform Register 62"
|
|
hgroup.byte 0x5F++0x00
|
|
hide.byte 0x00 "WF_63,LCD Waveform Register 63"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif cpuis("MKL28Z*")||cpuis("MKL82Z*")
|
|
sif cpuis("MKL28Z*")
|
|
tree "CAU (Cryptographic Acceleration Unit)"
|
|
base ad:0xF00050000
|
|
width 11.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CAU0_CASR,Status Register"
|
|
bitfld.long 0x00 28.--31. " VER ,CAU Version" "Initial,Second,?..."
|
|
bitfld.long 0x00 1. " DPE ,DES Parity Error" "No error,Error"
|
|
bitfld.long 0x00 0. " IC ,Illegal Command" "No illegal,Illegal"
|
|
line.long 0x04 "CAU0_CAA,Accumulator"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "CAU0_CA0,General Purpose Register 0"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "CAU0_CA1,General Purpose Register 1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CAU0_CA2,General Purpose Register 2"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CAU0_CA3,General Purpose Register 3"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CAU0_CA4,General Purpose Register 4"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CAU0_CA5,General Purpose Register 5"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CAU0_CA6,General Purpose Register 6"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CAU0_CA7,General Purpose Register 7"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CAU0_CA8,General Purpose Register 8"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EMV SIM (Smart Card Interface Module)"
|
|
base ad:0x4004E000
|
|
width 12.
|
|
sif cpuis("IMX8Q")||cpuis("IMX8Q*")||cpuis("IMX8QM*")||cpuis("IMX8QP*")||cpuis("MKL28Z*")||cpuis("MKL82Z*")
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "VER_ID,Version ID Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " VER_MAJ ,Major version ID of the module"
|
|
hexmask.long.word 0x00 0.--15. 1. " VER_MIN ,Minor version ID of the module"
|
|
line.long 0x04 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " TX_FIFO_DEPTH ,Transmit FIFO depth"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RX_FIFO_DEPTH ,Receive FIFO depth"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "VER_ID,Version ID Register"
|
|
line.long 0x04 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " TX_FIFO_DEPTH ,Transmit FIFO depth"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RX_FIFO_DEPTH ,Receive FIFO depth"
|
|
endif
|
|
group.long 0x08++0x17
|
|
line.long 0x00 "CLKCFG,Clock Configuration Register"
|
|
bitfld.long 0x00 10.--11. " GPCNT0_CLK_SEL ,General purpose counter 0 clock select" "Disabled,Card,Receive,ETU"
|
|
bitfld.long 0x00 8.--9. " GPCNT1_CLK_SEL ,General purpose counter 1 clock select" "Disabled,Card,Receive,ETU"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLK_PRSC ,Clock prescaler value"
|
|
line.long 0x04 "DIVISOR,Baud Rate Divisor Register"
|
|
hexmask.long.word 0x04 0.--8. 1. " DIVISOR_VALUE ,Baud rate divisor register"
|
|
line.long 0x08 "CTRL,Control Register"
|
|
bitfld.long 0x08 31. " BWT_EN ,Block wait time counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " XMT_CRC_LRC ,Transmit CRC or LRC enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " CRC_EN ,CRC enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " LRC_EN ,LRC enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 27. " CWT_EN ,Character wait time counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " CRC_IN_FLIP ,CRC input byte's bit reversal or flip control" "Not reversed,Reversed"
|
|
bitfld.long 0x08 25. " CRC_OUT_FLIP ,CRC output value bit reversal or flip" "Not reversed,Reversed"
|
|
bitfld.long 0x08 24. " INV_CRC_VAL ,Invert bits in the CRC output value" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x08 20. " TX_DMA_EN ,Transmit DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 19. " RX_DMA_EN ,Receive DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " RCVR_11 ,Receiver 11 ETU mode enable" "ETU 12,ETU 11"
|
|
bitfld.long 0x08 17. " XMT_EN ,Transmitter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 16. " RCV_EN ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " STOP_EN ,STOP enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " DOZE_EN ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " KILL_CLOCKS ,Kill all internal clocks" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 10. " SW_RST ,Software reset bit" "No reset,Reset"
|
|
bitfld.long 0x08 9. " FLSH_TX ,Flush transmitter bit" "No reset,Reset"
|
|
bitfld.long 0x08 8. " FLSH_RX ,Flush receiver bit" "No reset,Reset"
|
|
bitfld.long 0x08 3. " ONACK ,Overrun NACK enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 2. " ANACK ,Auto NACK enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " ICM ,Initial character mode" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " IC ,Inverse convention" "Disabled,Enabled"
|
|
line.long 0x0C "INT_MASK,Interrupt Mask Register"
|
|
bitfld.long 0x0C 15. " PEF_MASK ,Parity error interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 14. " RX_DATA_IM ,Receive data interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 13. " GPCNT1_IM ,General purpose counter 1 timeout interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 12. " BGT_ERR_IM ,Block guard time error interrupt" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 11. " BWT_ERR_IM ,Block wait time error interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 10. " RNACK_IM ,Receiver NACK threshold interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 9. " CWT_ERR_IM ,Character wait time error interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 8. " GPCNT0_IM ,General purpose timer 0 timeout interrupt mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 7. " TDT_IM ,Transmit data threshold interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 6. " TFF_IM ,Transmit FIFO full interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 5. " TNACK_IM ,Transmit NACK threshold interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 4. " TFE_IM ,Transmit FIFO empty interrupt mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 3. " ETC_IM ,Early transmit complete interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 2. " RFO_IM ,Receive FIFO overflow interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 1. " TC_IM ,Transmit complete interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 0. " RDT_IM ,Receive data threshold interrupt mask" "Not masked,Masked"
|
|
line.long 0x10 "RX_THD,Receiver Threshold Register"
|
|
bitfld.long 0x10 8.--11. " RNCK_THD ,Receiver NACK threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 0.--3. " RDT ,Receiver data threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14 "TX_THD,Transmitter Threshold Register"
|
|
bitfld.long 0x14 8.--11. " TNCK_THD ,Transmitter NACK threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " TDT ,Transmitter data threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "RX_STATUS,Receive Status Register"
|
|
sif cpuis("MKL28Z*")
|
|
rbitfld.long 0x00 22.--24. " RX_CNT ,Receive FIFO byte count" "Empty,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 16.--17. " RX_WPTR ,Receive FIFO write pointer value" "0,1,2,3"
|
|
elif cpuis("MKL82Z*")
|
|
hexmask.long.byte 0x00 24.--31. 1. " RX_CNT ,Receive FIFO byte count"
|
|
rbitfld.long 0x00 16.--19. " RX_WPTR ,Receive FIFO write pointer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
elif cpuis("IMX8Q")||cpuis("IMX8Q*")||cpuis("IMX8QM*")||cpuis("IMX8QP*")
|
|
rbitfld.long 0x00 24.--27. " RX_CNT ,Receive FIFO byte count" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 16.--19. " RX_WPTR ,Receive FIFO write pointer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rbitfld.long 0x00 24.--28. " RX_CNT ,Receive FIFO byte count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--19. 1. " RX_WPTR ,Receive FIFO write pointer value"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 13. " FEF ,Frame error flag" "No error,Error"
|
|
eventfld.long 0x00 12. " PEF ,Parity error flag" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 11. " BGT_ERR ,Block guard time error flag" "No error,Error"
|
|
eventfld.long 0x00 10. " BWT_ERR ,Block wait time error flag" "No error,Error"
|
|
eventfld.long 0x00 9. " RTE ,Received NACK threshold error flag" "No error,Error"
|
|
eventfld.long 0x00 8. " CWT_ERR ,Character Wait time error flag" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x00 7. " CRC_OK ,CRC check OK flag" "Not match,Match"
|
|
rbitfld.long 0x00 6. " LRC_OK ,LRC check OK flag" "Not match,Match"
|
|
rbitfld.long 0x00 5. " RDTF ,Receive data threshold interrupt flag" "Less,Greater"
|
|
eventfld.long 0x00 4. " RX_DATA ,Receive data interrupt flag" "Received,Received and stored"
|
|
newline
|
|
eventfld.long 0x00 0. " RFO ,Receive FIFO overflow flag" "Not occurred,Occurred"
|
|
line.long 0x04 "TX_STATUS,Transmitter Status Register"
|
|
sif cpuis("MKL28Z*")
|
|
rbitfld.long 0x04 22.--24. " TX_CNT ,Transmit FIFO byte count" "Empty,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x04 16.--17. " TX_RPTR ,Transmit FIFO read pointer" "0,1,2,3"
|
|
elif cpuis("MKL82Z*")
|
|
hexmask.long.byte 0x04 24.--31. 1. " TX_CNT ,Transmit FIFO byte count"
|
|
rbitfld.long 0x04 16.--19. " TX_RPTR ,Transmit FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
elif cpuis("IMX8Q")||cpuis("IMX8Q*")||cpuis("IMX8QM*")||cpuis("IMX8QP*")
|
|
rbitfld.long 0x04 24.--27. " TX_CNT ,Transmit FIFO byte count" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x04 16.--19. " TX_RPTR ,Transmit FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rbitfld.long 0x04 24.--28. " TX_CNT ,Transmit FIFO byte count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x04 16.--19. 1. " TX_RPTR ,Transmit FIFO read pointer"
|
|
endif
|
|
newline
|
|
eventfld.long 0x04 9. " GPCNT1_TO ,General purpose counter 1 timeout flag" "Not occurred,Occurred"
|
|
eventfld.long 0x04 8. " GPCNT0_TO ,General purpose counter 0 timeout flag" "Not occurred,Occurred"
|
|
newline
|
|
rbitfld.long 0x04 7. " TDTF ,Transmit data threshold flag" "Greater,Less"
|
|
eventfld.long 0x04 6. " TFF ,Transmit FIFO full flag" "Not occurred,Occurred"
|
|
eventfld.long 0x04 5. " TCF ,Transmit complete flag" "In progress,Completed"
|
|
eventfld.long 0x04 4. " ETCF ,Early transmit complete flag" "In progress,Completed"
|
|
newline
|
|
eventfld.long 0x04 3. " TFE ,Transmit FIFO empty flag" "Not empty,Empty"
|
|
eventfld.long 0x04 0. " TNTE ,Transmit NACK threshold error flag" "Not reached,Reached"
|
|
line.long 0x08 "PCSR,Port Control and Status Register"
|
|
bitfld.long 0x08 27. " SPDES ,SIM presence detect edge select" "Falling,Rising"
|
|
rbitfld.long 0x08 26. " SPDP ,Smart card presence detect pin status" "Low,High"
|
|
eventfld.long 0x08 25. " SPDIF ,Smart card presence detect interrupt flag" "Not detected,Detected"
|
|
bitfld.long 0x08 24. " SPDIM ,Smart card presence detect interrupt mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 7. " SPD ,Auto power down control" "No effect,Enabled"
|
|
bitfld.long 0x08 5. " SCSP ,Smart card clock stop polarity" "0,1"
|
|
bitfld.long 0x08 4. " SCEN ,Clock enable for smart card" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " SRST ,Reset to smart card" "Asserted,De-asserted"
|
|
newline
|
|
bitfld.long 0x08 2. " VCCENP ,VCC enable polarity control" "Unchanged,Inverted"
|
|
bitfld.long 0x08 1. " SVCC_EN ,VCC enable for smart card" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " SAPD ,Auto power down enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "RX_BUF,Receive Data Read Buffer"
|
|
in
|
|
newline
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "TX_BUF,Transmit Data Buffer"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TX_BYTE ,Transmit data byte"
|
|
group.long 0x34++0x17
|
|
line.long 0x00 "TX_GETU,Transmitter Guard ETU Value Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GETU ,Transmitter guard time value in ETU"
|
|
line.long 0x04 "CWT_VAL,Character Wait Time Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CWT ,Character wait time value"
|
|
line.long 0x08 "BWT_VAL,Block Wait Time Value Register"
|
|
line.long 0x0C "BGT_VAL,Block Guard Time Value Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " BGT ,Block guard time value"
|
|
line.long 0x10 "GPCNT0_VAL,General Purpose Counter 0 Timeout Value Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " GPCNT0 ,General purpose counter 0 timeout value"
|
|
line.long 0x14 "GPCNT1_VAL,General Purpose Counter 1 Timeout Value Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " GPCNT1 ,General purpose counter 1 timeout value"
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree.open "EMV SIM (Smart Card Interface Module)"
|
|
tree "EMV_SIM0"
|
|
base ad:0x4004E000
|
|
width 12.
|
|
sif cpuis("IMX8Q")||cpuis("IMX8Q*")||cpuis("IMX8QM*")||cpuis("IMX8QP*")||cpuis("MKL28Z*")||cpuis("MKL82Z*")
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "VER_ID,Version ID Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " VER_MAJ ,Major version ID of the module"
|
|
hexmask.long.word 0x00 0.--15. 1. " VER_MIN ,Minor version ID of the module"
|
|
line.long 0x04 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " TX_FIFO_DEPTH ,Transmit FIFO depth"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RX_FIFO_DEPTH ,Receive FIFO depth"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "VER_ID,Version ID Register"
|
|
line.long 0x04 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " TX_FIFO_DEPTH ,Transmit FIFO depth"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RX_FIFO_DEPTH ,Receive FIFO depth"
|
|
endif
|
|
group.long 0x08++0x17
|
|
line.long 0x00 "CLKCFG,Clock Configuration Register"
|
|
bitfld.long 0x00 10.--11. " GPCNT0_CLK_SEL ,General purpose counter 0 clock select" "Disabled,Card,Receive,ETU"
|
|
bitfld.long 0x00 8.--9. " GPCNT1_CLK_SEL ,General purpose counter 1 clock select" "Disabled,Card,Receive,ETU"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLK_PRSC ,Clock prescaler value"
|
|
line.long 0x04 "DIVISOR,Baud Rate Divisor Register"
|
|
hexmask.long.word 0x04 0.--8. 1. " DIVISOR_VALUE ,Baud rate divisor register"
|
|
line.long 0x08 "CTRL,Control Register"
|
|
bitfld.long 0x08 31. " BWT_EN ,Block wait time counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " XMT_CRC_LRC ,Transmit CRC or LRC enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " CRC_EN ,CRC enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " LRC_EN ,LRC enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 27. " CWT_EN ,Character wait time counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " CRC_IN_FLIP ,CRC input byte's bit reversal or flip control" "Not reversed,Reversed"
|
|
bitfld.long 0x08 25. " CRC_OUT_FLIP ,CRC output value bit reversal or flip" "Not reversed,Reversed"
|
|
bitfld.long 0x08 24. " INV_CRC_VAL ,Invert bits in the CRC output value" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x08 20. " TX_DMA_EN ,Transmit DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 19. " RX_DMA_EN ,Receive DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " RCVR_11 ,Receiver 11 ETU mode enable" "ETU 12,ETU 11"
|
|
bitfld.long 0x08 17. " XMT_EN ,Transmitter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 16. " RCV_EN ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " STOP_EN ,STOP enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " DOZE_EN ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " KILL_CLOCKS ,Kill all internal clocks" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 10. " SW_RST ,Software reset bit" "No reset,Reset"
|
|
bitfld.long 0x08 9. " FLSH_TX ,Flush transmitter bit" "No reset,Reset"
|
|
bitfld.long 0x08 8. " FLSH_RX ,Flush receiver bit" "No reset,Reset"
|
|
bitfld.long 0x08 3. " ONACK ,Overrun NACK enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 2. " ANACK ,Auto NACK enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " ICM ,Initial character mode" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " IC ,Inverse convention" "Disabled,Enabled"
|
|
line.long 0x0C "INT_MASK,Interrupt Mask Register"
|
|
bitfld.long 0x0C 15. " PEF_MASK ,Parity error interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 14. " RX_DATA_IM ,Receive data interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 13. " GPCNT1_IM ,General purpose counter 1 timeout interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 12. " BGT_ERR_IM ,Block guard time error interrupt" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 11. " BWT_ERR_IM ,Block wait time error interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 10. " RNACK_IM ,Receiver NACK threshold interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 9. " CWT_ERR_IM ,Character wait time error interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 8. " GPCNT0_IM ,General purpose timer 0 timeout interrupt mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 7. " TDT_IM ,Transmit data threshold interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 6. " TFF_IM ,Transmit FIFO full interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 5. " TNACK_IM ,Transmit NACK threshold interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 4. " TFE_IM ,Transmit FIFO empty interrupt mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 3. " ETC_IM ,Early transmit complete interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 2. " RFO_IM ,Receive FIFO overflow interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 1. " TC_IM ,Transmit complete interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 0. " RDT_IM ,Receive data threshold interrupt mask" "Not masked,Masked"
|
|
line.long 0x10 "RX_THD,Receiver Threshold Register"
|
|
bitfld.long 0x10 8.--11. " RNCK_THD ,Receiver NACK threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 0.--3. " RDT ,Receiver data threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14 "TX_THD,Transmitter Threshold Register"
|
|
bitfld.long 0x14 8.--11. " TNCK_THD ,Transmitter NACK threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " TDT ,Transmitter data threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "RX_STATUS,Receive Status Register"
|
|
sif cpuis("MKL28Z*")
|
|
rbitfld.long 0x00 22.--24. " RX_CNT ,Receive FIFO byte count" "Empty,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 16.--17. " RX_WPTR ,Receive FIFO write pointer value" "0,1,2,3"
|
|
elif cpuis("MKL82Z*")
|
|
hexmask.long.byte 0x00 24.--31. 1. " RX_CNT ,Receive FIFO byte count"
|
|
rbitfld.long 0x00 16.--19. " RX_WPTR ,Receive FIFO write pointer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
elif cpuis("IMX8Q")||cpuis("IMX8Q*")||cpuis("IMX8QM*")||cpuis("IMX8QP*")
|
|
rbitfld.long 0x00 24.--27. " RX_CNT ,Receive FIFO byte count" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 16.--19. " RX_WPTR ,Receive FIFO write pointer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rbitfld.long 0x00 24.--28. " RX_CNT ,Receive FIFO byte count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--19. 1. " RX_WPTR ,Receive FIFO write pointer value"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 13. " FEF ,Frame error flag" "No error,Error"
|
|
eventfld.long 0x00 12. " PEF ,Parity error flag" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 11. " BGT_ERR ,Block guard time error flag" "No error,Error"
|
|
eventfld.long 0x00 10. " BWT_ERR ,Block wait time error flag" "No error,Error"
|
|
eventfld.long 0x00 9. " RTE ,Received NACK threshold error flag" "No error,Error"
|
|
eventfld.long 0x00 8. " CWT_ERR ,Character Wait time error flag" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x00 7. " CRC_OK ,CRC check OK flag" "Not match,Match"
|
|
rbitfld.long 0x00 6. " LRC_OK ,LRC check OK flag" "Not match,Match"
|
|
rbitfld.long 0x00 5. " RDTF ,Receive data threshold interrupt flag" "Less,Greater"
|
|
eventfld.long 0x00 4. " RX_DATA ,Receive data interrupt flag" "Received,Received and stored"
|
|
newline
|
|
eventfld.long 0x00 0. " RFO ,Receive FIFO overflow flag" "Not occurred,Occurred"
|
|
line.long 0x04 "TX_STATUS,Transmitter Status Register"
|
|
sif cpuis("MKL28Z*")
|
|
rbitfld.long 0x04 22.--24. " TX_CNT ,Transmit FIFO byte count" "Empty,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x04 16.--17. " TX_RPTR ,Transmit FIFO read pointer" "0,1,2,3"
|
|
elif cpuis("MKL82Z*")
|
|
hexmask.long.byte 0x04 24.--31. 1. " TX_CNT ,Transmit FIFO byte count"
|
|
rbitfld.long 0x04 16.--19. " TX_RPTR ,Transmit FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
elif cpuis("IMX8Q")||cpuis("IMX8Q*")||cpuis("IMX8QM*")||cpuis("IMX8QP*")
|
|
rbitfld.long 0x04 24.--27. " TX_CNT ,Transmit FIFO byte count" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x04 16.--19. " TX_RPTR ,Transmit FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rbitfld.long 0x04 24.--28. " TX_CNT ,Transmit FIFO byte count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x04 16.--19. 1. " TX_RPTR ,Transmit FIFO read pointer"
|
|
endif
|
|
newline
|
|
eventfld.long 0x04 9. " GPCNT1_TO ,General purpose counter 1 timeout flag" "Not occurred,Occurred"
|
|
eventfld.long 0x04 8. " GPCNT0_TO ,General purpose counter 0 timeout flag" "Not occurred,Occurred"
|
|
newline
|
|
rbitfld.long 0x04 7. " TDTF ,Transmit data threshold flag" "Greater,Less"
|
|
eventfld.long 0x04 6. " TFF ,Transmit FIFO full flag" "Not occurred,Occurred"
|
|
eventfld.long 0x04 5. " TCF ,Transmit complete flag" "In progress,Completed"
|
|
eventfld.long 0x04 4. " ETCF ,Early transmit complete flag" "In progress,Completed"
|
|
newline
|
|
eventfld.long 0x04 3. " TFE ,Transmit FIFO empty flag" "Not empty,Empty"
|
|
eventfld.long 0x04 0. " TNTE ,Transmit NACK threshold error flag" "Not reached,Reached"
|
|
line.long 0x08 "PCSR,Port Control and Status Register"
|
|
bitfld.long 0x08 27. " SPDES ,SIM presence detect edge select" "Falling,Rising"
|
|
rbitfld.long 0x08 26. " SPDP ,Smart card presence detect pin status" "Low,High"
|
|
eventfld.long 0x08 25. " SPDIF ,Smart card presence detect interrupt flag" "Not detected,Detected"
|
|
bitfld.long 0x08 24. " SPDIM ,Smart card presence detect interrupt mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 7. " SPD ,Auto power down control" "No effect,Enabled"
|
|
bitfld.long 0x08 5. " SCSP ,Smart card clock stop polarity" "0,1"
|
|
bitfld.long 0x08 4. " SCEN ,Clock enable for smart card" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " SRST ,Reset to smart card" "Asserted,De-asserted"
|
|
newline
|
|
bitfld.long 0x08 2. " VCCENP ,VCC enable polarity control" "Unchanged,Inverted"
|
|
bitfld.long 0x08 1. " SVCC_EN ,VCC enable for smart card" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " SAPD ,Auto power down enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "RX_BUF,Receive Data Read Buffer"
|
|
in
|
|
newline
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "TX_BUF,Transmit Data Buffer"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TX_BYTE ,Transmit data byte"
|
|
group.long 0x34++0x17
|
|
line.long 0x00 "TX_GETU,Transmitter Guard ETU Value Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GETU ,Transmitter guard time value in ETU"
|
|
line.long 0x04 "CWT_VAL,Character Wait Time Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CWT ,Character wait time value"
|
|
line.long 0x08 "BWT_VAL,Block Wait Time Value Register"
|
|
line.long 0x0C "BGT_VAL,Block Guard Time Value Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " BGT ,Block guard time value"
|
|
line.long 0x10 "GPCNT0_VAL,General Purpose Counter 0 Timeout Value Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " GPCNT0 ,General purpose counter 0 timeout value"
|
|
line.long 0x14 "GPCNT1_VAL,General Purpose Counter 1 Timeout Value Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " GPCNT1 ,General purpose counter 1 timeout value"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EMV_SIM1"
|
|
base ad:0x4004F000
|
|
width 12.
|
|
sif cpuis("IMX8Q")||cpuis("IMX8Q*")||cpuis("IMX8QM*")||cpuis("IMX8QP*")||cpuis("MKL28Z*")||cpuis("MKL82Z*")
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "VER_ID,Version ID Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " VER_MAJ ,Major version ID of the module"
|
|
hexmask.long.word 0x00 0.--15. 1. " VER_MIN ,Minor version ID of the module"
|
|
line.long 0x04 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " TX_FIFO_DEPTH ,Transmit FIFO depth"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RX_FIFO_DEPTH ,Receive FIFO depth"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "VER_ID,Version ID Register"
|
|
line.long 0x04 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " TX_FIFO_DEPTH ,Transmit FIFO depth"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RX_FIFO_DEPTH ,Receive FIFO depth"
|
|
endif
|
|
group.long 0x08++0x17
|
|
line.long 0x00 "CLKCFG,Clock Configuration Register"
|
|
bitfld.long 0x00 10.--11. " GPCNT0_CLK_SEL ,General purpose counter 0 clock select" "Disabled,Card,Receive,ETU"
|
|
bitfld.long 0x00 8.--9. " GPCNT1_CLK_SEL ,General purpose counter 1 clock select" "Disabled,Card,Receive,ETU"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLK_PRSC ,Clock prescaler value"
|
|
line.long 0x04 "DIVISOR,Baud Rate Divisor Register"
|
|
hexmask.long.word 0x04 0.--8. 1. " DIVISOR_VALUE ,Baud rate divisor register"
|
|
line.long 0x08 "CTRL,Control Register"
|
|
bitfld.long 0x08 31. " BWT_EN ,Block wait time counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " XMT_CRC_LRC ,Transmit CRC or LRC enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " CRC_EN ,CRC enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " LRC_EN ,LRC enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 27. " CWT_EN ,Character wait time counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " CRC_IN_FLIP ,CRC input byte's bit reversal or flip control" "Not reversed,Reversed"
|
|
bitfld.long 0x08 25. " CRC_OUT_FLIP ,CRC output value bit reversal or flip" "Not reversed,Reversed"
|
|
bitfld.long 0x08 24. " INV_CRC_VAL ,Invert bits in the CRC output value" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x08 20. " TX_DMA_EN ,Transmit DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 19. " RX_DMA_EN ,Receive DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " RCVR_11 ,Receiver 11 ETU mode enable" "ETU 12,ETU 11"
|
|
bitfld.long 0x08 17. " XMT_EN ,Transmitter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 16. " RCV_EN ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " STOP_EN ,STOP enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " DOZE_EN ,Doze enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " KILL_CLOCKS ,Kill all internal clocks" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 10. " SW_RST ,Software reset bit" "No reset,Reset"
|
|
bitfld.long 0x08 9. " FLSH_TX ,Flush transmitter bit" "No reset,Reset"
|
|
bitfld.long 0x08 8. " FLSH_RX ,Flush receiver bit" "No reset,Reset"
|
|
bitfld.long 0x08 3. " ONACK ,Overrun NACK enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 2. " ANACK ,Auto NACK enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " ICM ,Initial character mode" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " IC ,Inverse convention" "Disabled,Enabled"
|
|
line.long 0x0C "INT_MASK,Interrupt Mask Register"
|
|
bitfld.long 0x0C 15. " PEF_MASK ,Parity error interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 14. " RX_DATA_IM ,Receive data interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 13. " GPCNT1_IM ,General purpose counter 1 timeout interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 12. " BGT_ERR_IM ,Block guard time error interrupt" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 11. " BWT_ERR_IM ,Block wait time error interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 10. " RNACK_IM ,Receiver NACK threshold interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 9. " CWT_ERR_IM ,Character wait time error interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 8. " GPCNT0_IM ,General purpose timer 0 timeout interrupt mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 7. " TDT_IM ,Transmit data threshold interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 6. " TFF_IM ,Transmit FIFO full interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 5. " TNACK_IM ,Transmit NACK threshold interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 4. " TFE_IM ,Transmit FIFO empty interrupt mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 3. " ETC_IM ,Early transmit complete interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 2. " RFO_IM ,Receive FIFO overflow interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 1. " TC_IM ,Transmit complete interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 0. " RDT_IM ,Receive data threshold interrupt mask" "Not masked,Masked"
|
|
line.long 0x10 "RX_THD,Receiver Threshold Register"
|
|
bitfld.long 0x10 8.--11. " RNCK_THD ,Receiver NACK threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 0.--3. " RDT ,Receiver data threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14 "TX_THD,Transmitter Threshold Register"
|
|
bitfld.long 0x14 8.--11. " TNCK_THD ,Transmitter NACK threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " TDT ,Transmitter data threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "RX_STATUS,Receive Status Register"
|
|
sif cpuis("MKL28Z*")
|
|
rbitfld.long 0x00 22.--24. " RX_CNT ,Receive FIFO byte count" "Empty,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 16.--17. " RX_WPTR ,Receive FIFO write pointer value" "0,1,2,3"
|
|
elif cpuis("MKL82Z*")
|
|
hexmask.long.byte 0x00 24.--31. 1. " RX_CNT ,Receive FIFO byte count"
|
|
rbitfld.long 0x00 16.--19. " RX_WPTR ,Receive FIFO write pointer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
elif cpuis("IMX8Q")||cpuis("IMX8Q*")||cpuis("IMX8QM*")||cpuis("IMX8QP*")
|
|
rbitfld.long 0x00 24.--27. " RX_CNT ,Receive FIFO byte count" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 16.--19. " RX_WPTR ,Receive FIFO write pointer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rbitfld.long 0x00 24.--28. " RX_CNT ,Receive FIFO byte count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--19. 1. " RX_WPTR ,Receive FIFO write pointer value"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 13. " FEF ,Frame error flag" "No error,Error"
|
|
eventfld.long 0x00 12. " PEF ,Parity error flag" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 11. " BGT_ERR ,Block guard time error flag" "No error,Error"
|
|
eventfld.long 0x00 10. " BWT_ERR ,Block wait time error flag" "No error,Error"
|
|
eventfld.long 0x00 9. " RTE ,Received NACK threshold error flag" "No error,Error"
|
|
eventfld.long 0x00 8. " CWT_ERR ,Character Wait time error flag" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x00 7. " CRC_OK ,CRC check OK flag" "Not match,Match"
|
|
rbitfld.long 0x00 6. " LRC_OK ,LRC check OK flag" "Not match,Match"
|
|
rbitfld.long 0x00 5. " RDTF ,Receive data threshold interrupt flag" "Less,Greater"
|
|
eventfld.long 0x00 4. " RX_DATA ,Receive data interrupt flag" "Received,Received and stored"
|
|
newline
|
|
eventfld.long 0x00 0. " RFO ,Receive FIFO overflow flag" "Not occurred,Occurred"
|
|
line.long 0x04 "TX_STATUS,Transmitter Status Register"
|
|
sif cpuis("MKL28Z*")
|
|
rbitfld.long 0x04 22.--24. " TX_CNT ,Transmit FIFO byte count" "Empty,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x04 16.--17. " TX_RPTR ,Transmit FIFO read pointer" "0,1,2,3"
|
|
elif cpuis("MKL82Z*")
|
|
hexmask.long.byte 0x04 24.--31. 1. " TX_CNT ,Transmit FIFO byte count"
|
|
rbitfld.long 0x04 16.--19. " TX_RPTR ,Transmit FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
elif cpuis("IMX8Q")||cpuis("IMX8Q*")||cpuis("IMX8QM*")||cpuis("IMX8QP*")
|
|
rbitfld.long 0x04 24.--27. " TX_CNT ,Transmit FIFO byte count" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x04 16.--19. " TX_RPTR ,Transmit FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rbitfld.long 0x04 24.--28. " TX_CNT ,Transmit FIFO byte count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x04 16.--19. 1. " TX_RPTR ,Transmit FIFO read pointer"
|
|
endif
|
|
newline
|
|
eventfld.long 0x04 9. " GPCNT1_TO ,General purpose counter 1 timeout flag" "Not occurred,Occurred"
|
|
eventfld.long 0x04 8. " GPCNT0_TO ,General purpose counter 0 timeout flag" "Not occurred,Occurred"
|
|
newline
|
|
rbitfld.long 0x04 7. " TDTF ,Transmit data threshold flag" "Greater,Less"
|
|
eventfld.long 0x04 6. " TFF ,Transmit FIFO full flag" "Not occurred,Occurred"
|
|
eventfld.long 0x04 5. " TCF ,Transmit complete flag" "In progress,Completed"
|
|
eventfld.long 0x04 4. " ETCF ,Early transmit complete flag" "In progress,Completed"
|
|
newline
|
|
eventfld.long 0x04 3. " TFE ,Transmit FIFO empty flag" "Not empty,Empty"
|
|
eventfld.long 0x04 0. " TNTE ,Transmit NACK threshold error flag" "Not reached,Reached"
|
|
line.long 0x08 "PCSR,Port Control and Status Register"
|
|
bitfld.long 0x08 27. " SPDES ,SIM presence detect edge select" "Falling,Rising"
|
|
rbitfld.long 0x08 26. " SPDP ,Smart card presence detect pin status" "Low,High"
|
|
eventfld.long 0x08 25. " SPDIF ,Smart card presence detect interrupt flag" "Not detected,Detected"
|
|
bitfld.long 0x08 24. " SPDIM ,Smart card presence detect interrupt mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 7. " SPD ,Auto power down control" "No effect,Enabled"
|
|
bitfld.long 0x08 5. " SCSP ,Smart card clock stop polarity" "0,1"
|
|
bitfld.long 0x08 4. " SCEN ,Clock enable for smart card" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " SRST ,Reset to smart card" "Asserted,De-asserted"
|
|
newline
|
|
bitfld.long 0x08 2. " VCCENP ,VCC enable polarity control" "Unchanged,Inverted"
|
|
bitfld.long 0x08 1. " SVCC_EN ,VCC enable for smart card" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " SAPD ,Auto power down enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "RX_BUF,Receive Data Read Buffer"
|
|
in
|
|
newline
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "TX_BUF,Transmit Data Buffer"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TX_BYTE ,Transmit data byte"
|
|
group.long 0x34++0x17
|
|
line.long 0x00 "TX_GETU,Transmitter Guard ETU Value Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GETU ,Transmitter guard time value in ETU"
|
|
line.long 0x04 "CWT_VAL,Character Wait Time Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CWT ,Character wait time value"
|
|
line.long 0x08 "BWT_VAL,Block Wait Time Value Register"
|
|
line.long 0x0C "BGT_VAL,Block Guard Time Value Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " BGT ,Block guard time value"
|
|
line.long 0x10 "GPCNT0_VAL,General Purpose Counter 0 Timeout Value Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " GPCNT0 ,General purpose counter 0 timeout value"
|
|
line.long 0x14 "GPCNT1_VAL,General Purpose Counter 1 Timeout Value Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " GPCNT1 ,General purpose counter 1 timeout value"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree "INTMUX (Interrupt Multiplexer)"
|
|
base ad:0x40024000
|
|
width 15.
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "CH0_CSR,Channel 0 Control Status Register"
|
|
bitfld.long 0x00 31. " IRQP ,Channel Interrupt Request Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 8.--11. " CHIN ,Channel Instance Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--5. " IRQN ,Channel Input Number" "32,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND"
|
|
bitfld.long 0x00 0. " RST ,Software Reset" "No operation,Perform a software reset"
|
|
rgroup.long (0x0+0x04)++0x03
|
|
line.long 0x00 "CH0_VEC,Channel 0 Vector Number Register"
|
|
hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector Number"
|
|
group.long (0x0+0x10)++0x03
|
|
line.long 0x00 "CH0_IER_31_0,Channel 0 Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " CH0_IER[31] ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Channel 0 interrupt enable" "Disabled,Enabled"
|
|
rgroup.long (0x0+0x20)++0x03
|
|
line.long 0x00 "CH0_IPR_31_0,Channel 0 Interrupt Pending Register"
|
|
bitfld.long 0x00 31. " CH0_IPR[31] ,Channel 0 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " [30] ,Channel 0 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " [29] ,Channel 0 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " [28] ,Channel 0 interrupt pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Channel 0 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " [26] ,Channel 0 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 25. " [25] ,Channel 0 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " [24] ,Channel 0 interrupt pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Channel 0 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " [22] ,Channel 0 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " [21] ,Channel 0 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " [20] ,Channel 0 interrupt pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Channel 0 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " [18] ,Channel 0 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " [17] ,Channel 0 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " [16] ,Channel 0 interrupt pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Channel 0 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " [14] ,Channel 0 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " [13] ,Channel 0 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " [12] ,Channel 0 interrupt pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Channel 0 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " [10] ,Channel 0 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " [9] ,Channel 0 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " [8] ,Channel 0 interrupt pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Channel 0 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " [6] ,Channel 0 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " [5] ,Channel 0 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " [4] ,Channel 0 interrupt pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Channel 0 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " [2] ,Channel 0 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " [1] ,Channel 0 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " [0] ,Channel 0 interrupt pending" "Not pending,Pending"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CH1_CSR,Channel 1 Control Status Register"
|
|
bitfld.long 0x00 31. " IRQP ,Channel Interrupt Request Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 8.--11. " CHIN ,Channel Instance Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--5. " IRQN ,Channel Input Number" "32,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND"
|
|
bitfld.long 0x00 0. " RST ,Software Reset" "No operation,Perform a software reset"
|
|
rgroup.long (0x40+0x04)++0x03
|
|
line.long 0x00 "CH1_VEC,Channel 1 Vector Number Register"
|
|
hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector Number"
|
|
group.long (0x40+0x10)++0x03
|
|
line.long 0x00 "CH1_IER_31_0,Channel 1 Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " CH1_IER[31] ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Channel 1 interrupt enable" "Disabled,Enabled"
|
|
rgroup.long (0x40+0x20)++0x03
|
|
line.long 0x00 "CH1_IPR_31_0,Channel 1 Interrupt Pending Register"
|
|
bitfld.long 0x00 31. " CH1_IPR[31] ,Channel 1 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " [30] ,Channel 1 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " [29] ,Channel 1 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " [28] ,Channel 1 interrupt pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Channel 1 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " [26] ,Channel 1 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 25. " [25] ,Channel 1 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " [24] ,Channel 1 interrupt pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Channel 1 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " [22] ,Channel 1 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " [21] ,Channel 1 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " [20] ,Channel 1 interrupt pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Channel 1 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " [18] ,Channel 1 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " [17] ,Channel 1 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " [16] ,Channel 1 interrupt pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Channel 1 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " [14] ,Channel 1 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " [13] ,Channel 1 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " [12] ,Channel 1 interrupt pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Channel 1 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " [10] ,Channel 1 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " [9] ,Channel 1 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " [8] ,Channel 1 interrupt pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Channel 1 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " [6] ,Channel 1 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " [5] ,Channel 1 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " [4] ,Channel 1 interrupt pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Channel 1 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " [2] ,Channel 1 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " [1] ,Channel 1 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " [0] ,Channel 1 interrupt pending" "Not pending,Pending"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CH2_CSR,Channel 2 Control Status Register"
|
|
bitfld.long 0x00 31. " IRQP ,Channel Interrupt Request Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 8.--11. " CHIN ,Channel Instance Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--5. " IRQN ,Channel Input Number" "32,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND"
|
|
bitfld.long 0x00 0. " RST ,Software Reset" "No operation,Perform a software reset"
|
|
rgroup.long (0x80+0x04)++0x03
|
|
line.long 0x00 "CH2_VEC,Channel 2 Vector Number Register"
|
|
hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector Number"
|
|
group.long (0x80+0x10)++0x03
|
|
line.long 0x00 "CH2_IER_31_0,Channel 2 Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " CH2_IER[31] ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Channel 2 interrupt enable" "Disabled,Enabled"
|
|
rgroup.long (0x80+0x20)++0x03
|
|
line.long 0x00 "CH2_IPR_31_0,Channel 2 Interrupt Pending Register"
|
|
bitfld.long 0x00 31. " CH2_IPR[31] ,Channel 2 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " [30] ,Channel 2 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " [29] ,Channel 2 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " [28] ,Channel 2 interrupt pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Channel 2 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " [26] ,Channel 2 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 25. " [25] ,Channel 2 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " [24] ,Channel 2 interrupt pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Channel 2 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " [22] ,Channel 2 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " [21] ,Channel 2 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " [20] ,Channel 2 interrupt pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Channel 2 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " [18] ,Channel 2 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " [17] ,Channel 2 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " [16] ,Channel 2 interrupt pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Channel 2 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " [14] ,Channel 2 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " [13] ,Channel 2 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " [12] ,Channel 2 interrupt pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Channel 2 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " [10] ,Channel 2 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " [9] ,Channel 2 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " [8] ,Channel 2 interrupt pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Channel 2 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " [6] ,Channel 2 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " [5] ,Channel 2 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " [4] ,Channel 2 interrupt pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Channel 2 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " [2] ,Channel 2 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " [1] ,Channel 2 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " [0] ,Channel 2 interrupt pending" "Not pending,Pending"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CH3_CSR,Channel 3 Control Status Register"
|
|
bitfld.long 0x00 31. " IRQP ,Channel Interrupt Request Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 8.--11. " CHIN ,Channel Instance Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--5. " IRQN ,Channel Input Number" "32,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " AND ,Logic AND" "OR,AND"
|
|
bitfld.long 0x00 0. " RST ,Software Reset" "No operation,Perform a software reset"
|
|
rgroup.long (0xC0+0x04)++0x03
|
|
line.long 0x00 "CH3_VEC,Channel 3 Vector Number Register"
|
|
hexmask.long.word 0x00 2.--13. 1. " VECN ,Vector Number"
|
|
group.long (0xC0+0x10)++0x03
|
|
line.long 0x00 "CH3_IER_31_0,Channel 3 Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " CH3_IER[31] ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Channel 3 interrupt enable" "Disabled,Enabled"
|
|
rgroup.long (0xC0+0x20)++0x03
|
|
line.long 0x00 "CH3_IPR_31_0,Channel 3 Interrupt Pending Register"
|
|
bitfld.long 0x00 31. " CH3_IPR[31] ,Channel 3 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " [30] ,Channel 3 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " [29] ,Channel 3 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " [28] ,Channel 3 interrupt pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Channel 3 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " [26] ,Channel 3 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 25. " [25] ,Channel 3 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " [24] ,Channel 3 interrupt pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Channel 3 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " [22] ,Channel 3 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " [21] ,Channel 3 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " [20] ,Channel 3 interrupt pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Channel 3 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " [18] ,Channel 3 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " [17] ,Channel 3 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " [16] ,Channel 3 interrupt pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Channel 3 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " [14] ,Channel 3 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " [13] ,Channel 3 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " [12] ,Channel 3 interrupt pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Channel 3 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " [10] ,Channel 3 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " [9] ,Channel 3 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " [8] ,Channel 3 interrupt pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Channel 3 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " [6] ,Channel 3 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " [5] ,Channel 3 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " [4] ,Channel 3 interrupt pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Channel 3 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " [2] ,Channel 3 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " [1] ,Channel 3 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " [0] ,Channel 3 interrupt pending" "Not pending,Pending"
|
|
width 0x0B
|
|
tree.end
|
|
tree "MMDVSQ (Memory-Mapped Divide and Square Root)"
|
|
base ad:0xF0004000
|
|
width 8.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DEND,Dividend Register"
|
|
line.long 0x04 "DSOR,Divisor Register"
|
|
line.long 0x08 "CSR,Control/Status Register"
|
|
rbitfld.long 0x08 31. " BUSY ,Busy" "Idle,Busy"
|
|
rbitfld.long 0x08 30. " DIVIDE ,Divide" "Not divided,Divided"
|
|
rbitfld.long 0x08 29. " SQRT ,Square root" "Was not a square root,Was a square root"
|
|
newline
|
|
bitfld.long 0x08 5. " DFS ,Disable fast start" "DSOR,CSR"
|
|
rbitfld.long 0x08 4. " DZ ,Divide-by-zero" "Non-zero divisor,Zero divisor"
|
|
bitfld.long 0x08 3. " DZE ,Divide-by-zero-enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 2. " REM ,Remainder calculation" "Return quotient,Return reminder"
|
|
bitfld.long 0x08 1. " USGN ,Unsigned calculation" "Signed divide,Unsigned divide"
|
|
bitfld.long 0x08 0. " SRT ,Start" "No effect,Start"
|
|
newline
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "RES,Result Register"
|
|
in
|
|
newline
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "RCND,Radicand Register"
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("MKL28Z*")
|
|
tree.open "PCC (Peripheral Clock Controller)"
|
|
tree "PCC1"
|
|
base ad:0x4007A000
|
|
width 14.
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PCC_DMA0,PCC DMA Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "PCC_FLASH,PCC FLASH Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
line.long 0x04 "PCC_DMAMUX0,PCC DMAMUX Register"
|
|
rbitfld.long 0x04 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x04 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x04 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "PCC_INTMUX,PCC INTMUX Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
if (((per.l(ad:0x4007A000+0xB8))&0x40000000)==0x40000000)
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "PCC_TPM2,PCC TPM1 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "PCC_TPM2, PCC TPM1 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
endif
|
|
if (((per.l(ad:0x4007A000+0xC0))&0x40000000)==0x40000000)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "PCC_LPIT0,PCC LPIT0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
else
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "PCC_LPIT0,PCC LPIT0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
endif
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "PCC_LPTMR0,PCC LPTMR0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "PCC_RTC,PCC RTC Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
if (((per.l(ad:0x4007A000+0xF8))&0x40000000)==0x40000000)
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "PCC_LPSPI2,PCC LPSPI2 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "PCC_LPSPI2,PCC LPSPI2 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
endif
|
|
if (((per.l(ad:0x4007A000+0x108))&0x40000000)==0x40000000)
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "PCC_LPI2C2,PCC LPI2C2 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "PCC_LPI2C2,PCC LPI2C2 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
endif
|
|
if (((per.l(ad:0x4007A000+0x118))&0x40000000)==0x40000000)
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "PCC_LPUART2,PCC LPUART1 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "PCC_LPUART2,PCC LPUART1 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
endif
|
|
if (((per.l(ad:0x4007A000+0x130))&0x40000000)==0x40000000)
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "PCC_SAI0,PCC SAI0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "PCC_SAI0,PCC SAI0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
endif
|
|
if (((per.l(ad:0x4007A000+0x138))&0x40000000)==0x40000000)
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "PCC_EMVSIM0,PCC EMVSIM0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Clock Option 1,Clock Option 2,Clock Option 3,Clock Option 4,Clock Option 5,Clock Option 6,Clock Option 7"
|
|
else
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "PCC_EMVSIM0,PCC EMVSIM0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Clock Option 1,Clock Option 2,Clock Option 3,Clock Option 4,Clock Option 5,Clock Option 6,Clock Option 7"
|
|
endif
|
|
if (((per.l(ad:0x4007A000+0x154))&0x40000000)==0x40000000)
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "PCC_USB0FS,PCC USB0FS Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
else
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "PCC_USB0FS,PCC USB0FS Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,OSCCLK,SCGIRCLK,SCGFIRCLK,,,SCGPCLK,?..."
|
|
endif
|
|
if (((per.l(ad:0x4007A000+0x168))&0x40000000)==0x40000000)
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "PCC_PORTA,PCC PORTA Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Clock Option 1,Clock Option 2,Clock Option 3,Clock Option 4,Clock Option 5,Clock Option 6,Clock Option 7"
|
|
else
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "PCC_PORTA,PCC PORTA Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Clock Option 1,Clock Option 2,Clock Option 3,Clock Option 4,Clock Option 5,Clock Option 6,Clock Option 7"
|
|
endif
|
|
group.long 0x16C++0x0F
|
|
line.long 0x00 "PCC_PORTB,PCC PORTB Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
line.long 0x04 "PCC_PORTC,PCC PORTC Register"
|
|
rbitfld.long 0x04 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x04 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x04 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
line.long 0x08 "PCC_PORTD,PCC PORTD Register"
|
|
rbitfld.long 0x08 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x08 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x08 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
line.long 0x0C "PCC_PORTE,PCC PORTE Register"
|
|
rbitfld.long 0x0C 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x0C 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x0C 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "PCC_TSI0,PCC TSI0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
if (((per.l(ad:0x4007A000+0x198))&0x40000000)==0x40000000)
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "PCC_ADC0,PCC ADC0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Clock Option 1,Clock Option 2,Clock Option 3,Clock Option 4,Clock Option 5,Clock Option 6,Clock Option 7"
|
|
else
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "PCC_ADC0,PCC ADC0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Clock Option 1,Clock Option 2,Clock Option 3,Clock Option 4,Clock Option 5,Clock Option 6,Clock Option 7"
|
|
endif
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "PCC_DAC0,PCC DAC0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "PCC_CMP0,PCC CMP0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "PCC_VREF,PCC VREF Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "PCC_CRC,PCC CRC Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PCC2"
|
|
base ad:0x400FA000
|
|
width 14.
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "PCC_TRNG,PCC TRNG Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
if (((per.l(ad:0x400FA000+0xB0))&0x40000000)==0x40000000)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "PCC_TPM0,PCC TPM0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Clock Option 1,Clock Option 2,Clock Option 3,Clock Option 4,Clock Option 5,Clock Option 6,Clock Option 7"
|
|
else
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "PCC_TPM0,PCC TPM0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Clock Option 1,Clock Option 2,Clock Option 3,Clock Option 4,Clock Option 5,Clock Option 6,Clock Option 7"
|
|
endif
|
|
if (((per.l(ad:0x400FA000+0xB4))&0x40000000)==0x40000000)
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "PCC_TPM1,PCC TPM1 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Clock Option 1,Clock Option 2,Clock Option 3,Clock Option 4,Clock Option 5,Clock Option 6,Clock Option 7"
|
|
else
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "PCC_TPM1, PCC TPM1 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Clock Option 1,Clock Option 2,Clock Option 3,Clock Option 4,Clock Option 5,Clock Option 6,Clock Option 7"
|
|
endif
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "PCC_LPTMR1,PCC LPTMR1 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
if (((per.l(ad:0x400FA000+0xF0))&0x40000000)==0x40000000)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "PCC_LPSPI0,PCC LPSPI0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Clock Option 1,Clock Option 2,Clock Option 3,Clock Option 4,Clock Option 5,Clock Option 6,Clock Option 7"
|
|
else
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "PCC_LPSPI0, PCC LPSPI0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Clock Option 1,Clock Option 2,Clock Option 3,Clock Option 4,Clock Option 5,Clock Option 6,Clock Option 7"
|
|
endif
|
|
if (((per.l(ad:0x400FA000+0xF4))&0x40000000)==0x40000000)
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "PCC_LPSPI1,PCC LPSPI1 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Clock Option 1,Clock Option 2,Clock Option 3,Clock Option 4,Clock Option 5,Clock Option 6,Clock Option 7"
|
|
else
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "PCC_LPSPI1, PCC LPSPI1 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Clock Option 1,Clock Option 2,Clock Option 3,Clock Option 4,Clock Option 5,Clock Option 6,Clock Option 7"
|
|
endif
|
|
if (((per.l(ad:0x400FA000+0x100))&0x40000000)==0x40000000)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PCC_LPI2C0,PCC LPI2C0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Clock Option 1,Clock Option 2,Clock Option 3,Clock Option 4,Clock Option 5,Clock Option 6,Clock Option 7"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PCC_LPI2C0, PCC LPI2C0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Clock Option 1,Clock Option 2,Clock Option 3,Clock Option 4,Clock Option 5,Clock Option 6,Clock Option 7"
|
|
endif
|
|
if (((per.l(ad:0x400FA000+0x104))&0x40000000)==0x40000000)
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "PCC_LPI2C1,PCC LPI2C1 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Clock Option 1,Clock Option 2,Clock Option 3,Clock Option 4,Clock Option 5,Clock Option 6,Clock Option 7"
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "PCC_LPI2C1, PCC LPI2C1 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Clock Option 1,Clock Option 2,Clock Option 3,Clock Option 4,Clock Option 5,Clock Option 6,Clock Option 7"
|
|
endif
|
|
if (((per.l(ad:0x400FA000+0x110))&0x40000000)==0x40000000)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "PCC_LPUART0,PCC LPUART0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Clock Option 1,Clock Option 2,Clock Option 3,Clock Option 4,Clock Option 5,Clock Option 6,Clock Option 7"
|
|
else
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "PCC_LPUART0, PCC LPUART0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Clock Option 1,Clock Option 2,Clock Option 3,Clock Option 4,Clock Option 5,Clock Option 6,Clock Option 7"
|
|
endif
|
|
if (((per.l(ad:0x400FA000+0x114))&0x40000000)==0x40000000)
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "PCC_LPUART1,PCC LPUART1 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Clock Option 1,Clock Option 2,Clock Option 3,Clock Option 4,Clock Option 5,Clock Option 6,Clock Option 7"
|
|
else
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "PCC_LPUART1, PCC LPUART1 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Clock Option 1,Clock Option 2,Clock Option 3,Clock Option 4,Clock Option 5,Clock Option 6,Clock Option 7"
|
|
endif
|
|
if (((per.l(ad:0x400FA000+0x128))&0x40000000)==0x40000000)
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "PCC_FLEXIO0,PCC FLEXIO0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
rbitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Clock Option 1,Clock Option 2,Clock Option 3,Clock Option 4,Clock Option 5,Clock Option 6,Clock Option 7"
|
|
else
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "PCC_FLEXIO0, PCC FLEXIO0 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
bitfld.long 0x00 24.--26. " PCS ,Peripheral clock select" "Disabled,Clock Option 1,Clock Option 2,Clock Option 3,Clock Option 4,Clock Option 5,Clock Option 6,Clock Option 7"
|
|
endif
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "PCC_CMP1,PCC CMP1 Register"
|
|
rbitfld.long 0x00 31. " PR ,Peripheral present" "Absent,Present"
|
|
bitfld.long 0x00 30. " CGC ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " INUSE ,Peripheral in use" "Not in use,In use"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "SCG (System Clock Generator)"
|
|
base ad:0x4007B000
|
|
width 12.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
line.long 0x04 "PARAM,Parameter Register"
|
|
bitfld.long 0x04 31. " DIVPRES[31] ,DIVCORE divider present" "Absent,Present"
|
|
newline
|
|
sif (cpuis("K32W*"))
|
|
bitfld.long 0x04 30. " [30] ,DIVCORE divider present" "Absent,Present"
|
|
bitfld.long 0x04 29. " [29] ,DIVEXT divider present" "Absent,Present"
|
|
endif
|
|
sif !cpuis("MKL28Z*")
|
|
bitfld.long 0x04 28. " [28] ,DIVBUS divider present" "Absent,Present"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 27. " [27] ,DIVSLOW divider present" "Absent,Present"
|
|
newline
|
|
sif !cpuis("K32W*")
|
|
bitfld.long 0x04 6. " CLKPRES[6] ,System PLL clock present" "Absent,Present"
|
|
endif
|
|
newline
|
|
sif (cpuis("K32W*"))
|
|
bitfld.long 0x04 5. " [5] ,System PLL clock present" "Absent,Present"
|
|
bitfld.long 0x04 4. " [4] ,System PLL clock present" "Absent,Present"
|
|
endif
|
|
bitfld.long 0x04 3. " [3] ,Fast IRC clock present" "Absent,Present"
|
|
bitfld.long 0x04 2. " [2] ,Slow IRC clock present" "Absent,Present"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,System OSC clock present" "Absent,Present"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CSR,Clock Status Register"
|
|
bitfld.long 0x00 24.--27. " SCS ,System clock source" ",System OSC,Slow IRC,Fast IRC,,,System PLL,?..."
|
|
bitfld.long 0x00 16.--19. " DIVCORE ,Core clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
sif (cpuis("K32W*"))
|
|
bitfld.long 0x00 8.--11. " DIVEXT ,External clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
endif
|
|
newline
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.long 0x00 0.--3. " DIVSLOW ,Slow clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
else
|
|
bitfld.long 0x00 4.--7. " DIVBUS ,Bus clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 0.--3. " DIVSLOW ,Slow clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,?..."
|
|
endif
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "RCCR,Run Clock Control Register"
|
|
sif (cpuis("K32W*"))
|
|
bitfld.long 0x00 24.--27. " SCS ,System clock source" ",SOSC_CLK,SIRC_CLK,FIRC_CLK,ROSC_CLK,LPFLL_CLK,?..."
|
|
else
|
|
bitfld.long 0x00 24.--27. " SCS ,System clock source" ",System OSC,Slow IRC,Fast IRC,,,System PLL,?..."
|
|
endif
|
|
bitfld.long 0x00 16.--19. " DIVCORE ,Core clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
sif (cpuis("K32W*"))
|
|
bitfld.long 0x00 8.--11. " DIVEXT ,External clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
endif
|
|
newline
|
|
sif !cpuis("MKL28Z*")
|
|
bitfld.long 0x00 4.--7. " DIVBUS ,Bus clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 0.--3. " DIVSLOW ,Slow clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 0.--3. " DIVSLOW ,Slow clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
endif
|
|
line.long 0x04 "VCCR,VLPR Clock Control Register"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))
|
|
bitfld.long 0x04 24.--27. " SCS ,System clock source" ",System OSC,Slow IRC,?..."
|
|
bitfld.long 0x04 16.--19. " DIVCORE ,Core clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x04 4.--7. " DIVBUS ,Bus clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " DIVSLOW ,Slow clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
elif cpuis("MKL28Z*")
|
|
bitfld.long 0x04 24.--27. " SCS ,System clock source" ",System OSC,Slow IRC,?..."
|
|
bitfld.long 0x04 16.--19. " DIVCORE ,Core clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x04 0.--3. " DIVSLOW ,Slow clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,?..."
|
|
elif cpuis("S32MTV")
|
|
bitfld.long 0x04 24.--27. " SCS ,System clock source" ",,Slow IRC,?..."
|
|
bitfld.long 0x04 16.--19. " DIVCORE ,Core clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x04 4.--7. " DIVBUS ,Bus clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " DIVSLOW ,Slow clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,?..."
|
|
elif (cpuis("K32W*"))
|
|
bitfld.long 0x04 24.--27. " SCS ,System clock source" ",SOSC_CLK,SIRC_CLK,,ROSC_CLK,?..."
|
|
bitfld.long 0x04 16.--19. " DIVCORE ,Core clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x04 4.--7. " DIVBUS ,Bus clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " DIVSLOW ,Slow clock divide ratio" ",/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
elif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
bitfld.long 0x04 24.--27. " SCS ,System clock source" ",,Slow IRC,?..."
|
|
bitfld.long 0x04 16.--19. " DIVCORE ,Core clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x04 4.--7. " DIVBUS ,Bus clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x04 0.--3. " DIVSLOW ,Slow clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,?..."
|
|
else
|
|
bitfld.long 0x04 24.--27. " SCS ,System clock source" ",,Slow IRC,?..."
|
|
bitfld.long 0x04 16.--19. " DIVCORE ,Core clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x04 8.--11. " DIVEXT ,External Clock Divide Ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " DIVBUS ,Bus clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x04 0.--3. " DIVSLOW ,Slow clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,?..."
|
|
endif
|
|
sif (!cpuis("S32MTV"))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "HCCR,HSRUN Clock Control Register"
|
|
sif (cpuis("K32W*"))
|
|
bitfld.long 0x00 24.--27. " SCS ,System clock source" ",SOSC_CLK,SIRC_CLK,FIRC_CLK,ROSC_CLK,LPFLL_CLK,?..."
|
|
else
|
|
bitfld.long 0x00 24.--27. " SCS ,System clock source" ",System OSC,Slow IRC,Fast IRC,,,System PLL,?..."
|
|
endif
|
|
bitfld.long 0x00 16.--19. " DIVCORE ,Core clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
sif (cpuis("K32W*"))
|
|
bitfld.long 0x00 8.--11. " DIVEXT ,External clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
endif
|
|
newline
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.long 0x00 0.--3. " DIVSLOW ,Slow clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
elif (cpuis("K32W*"))
|
|
bitfld.long 0x00 4.--7. " DIVBUS ,Bus clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 0.--3. " DIVSLOW ,Slow clock divide ratio" ",/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
else
|
|
bitfld.long 0x00 4.--7. " DIVBUS ,Bus clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 0.--3. " DIVSLOW ,Slow clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,?..."
|
|
endif
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CLKOUTCNFG,SCG CLKOUT Configuration Register"
|
|
sif (cpuis("K32W*"))
|
|
bitfld.long 0x00 24.--27. " CLKOUTSEL ,SCG clkout select" "SCG_EXTERNAL_CLOCK,SOSC_CLK,SIRC_CLK,FIRC_CLK,ROSC_CLK,LPFLL_CLK,?..."
|
|
else
|
|
bitfld.long 0x00 24.--27. " CLKOUTSEL ,SCG clkout select" "SCG SLOW clock,System OSC,Slow IRC,Fast IRC,,,System PLL,?..."
|
|
endif
|
|
if (((per.l(ad:0x4007B000+0x100))&0x800000)==0x800000)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SOSCCSR,System OSC Control Status Register"
|
|
rbitfld.long 0x00 26. " SOSCERR ,System OSC clock error" "No error,Error"
|
|
rbitfld.long 0x00 25. " SOSCSEL ,System OSC selected" "Not selected,Selected"
|
|
rbitfld.long 0x00 24. " SOSCVLD ,System OSC valid" "Invalid,Valid"
|
|
bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked"
|
|
newline
|
|
rbitfld.long 0x00 17. " SOSCCMRE ,System OSC clock monitor reset enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16. " SOSCCM ,System OSC clock monitor" "Disabled,Enabled"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("K32W*"))
|
|
newline
|
|
rbitfld.long 0x00 2. " SOSCLPEN ,System OSC low power enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 1. " SOSCSTEN ,System OSC stop enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " SOSCEN ,System OSC enable" "Disabled,Enabled"
|
|
elif cpuis("MKL28Z*")
|
|
newline
|
|
bitfld.long 0x00 3. " SOSCERCLKEN ,System OSC 3V ERCLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SOSCLPEN ,System OSC low power enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " SOSCSTEN ,System OSC stop enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SOSCEN ,System OSC enable" "Disabled,Enabled"
|
|
else
|
|
rbitfld.long 0x00 0. " SOSCEN ,System OSC enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SOSCCSR,System OSC Control Status Register"
|
|
eventfld.long 0x00 26. " SOSCERR ,System OSC clock error" "No error,Error"
|
|
rbitfld.long 0x00 25. " SOSCSEL ,System OSC selected" "Not selected,Selected"
|
|
rbitfld.long 0x00 24. " SOSCVLD ,System OSC valid" "Invalid,Valid"
|
|
bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 17. " SOSCCMRE ,System OSC clock monitor reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SOSCCM ,System OSC clock monitor" "Disabled,Enabled"
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("K32W*"))
|
|
newline
|
|
bitfld.long 0x00 2. " SOSCLPEN ,System OSC low power enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " SOSCSTEN ,System OSC stop enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SOSCEN ,System OSC enable" "Disabled,Enabled"
|
|
elif cpuis("MKL28Z*")
|
|
newline
|
|
bitfld.long 0x00 3. " SOSCERCLKEN ,System OSC 3V ERCLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SOSCLPEN ,System OSC low power enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " SOSCSTEN ,System OSC stop enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SOSCEN ,System OSC enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 0. " SOSCEN ,System OSC enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x4007B000+0x100))&0x01)==0x01)
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "SOSCDIV,System OSC Divide Register"
|
|
sif (cpuis("K32W*"))||cpuis("MKL28Z*")
|
|
bitfld.long 0x00 16.--18. " SOSCDIV3 ,System OSC clock divide 3" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8.--10. " SOSCDIV2 ,System OSC clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
bitfld.long 0x00 0.--2. " SOSCDIV1 ,System OSC clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
sif (!cpuis("K32W*"))
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "SOSCCFG,System Oscillator Configuration Register"
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.long 0x00 11. " SC2P ,Oscillator 2 pF capacitor load" "0,1"
|
|
bitfld.long 0x00 10. " SC4P ,Oscillator 4 pF capacitor load" "0,1"
|
|
bitfld.long 0x00 9. " SC8P ,Oscillator 8 pF capacitor load" "0,1"
|
|
bitfld.long 0x00 8. " SC16P ,Oscillator 16 pF capacitor load" "0,1"
|
|
newline
|
|
endif
|
|
sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
bitfld.long 0x00 4.--5. " RANGE ,System OSC range select" ",,4 Mhz-8 Mhz,8 Mhz-40 Mhz"
|
|
else
|
|
bitfld.long 0x00 4.--5. " RANGE ,System OSC range select" ",32 kHz-40 kHz,1 Mhz-8 Mhz,8 Mhz-32 Mhz"
|
|
endif
|
|
bitfld.long 0x00 3. " HGO ,High gain oscillator select" "Low-gain,High-gain"
|
|
bitfld.long 0x00 2. " EREFS ,External reference select" "External,Internal"
|
|
endif
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "SOSCDIV,System OSC Divide Register"
|
|
sif (cpuis("K32W*"))||cpuis("MKL28Z*")
|
|
bitfld.long 0x00 16.--18. " SOSCDIV3 ,System OSC clock divide 3" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8.--10. " SOSCDIV2 ,System OSC clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
bitfld.long 0x00 0.--2. " SOSCDIV1 ,System OSC clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
sif (!cpuis("K32W*"))
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "SOSCCFG,System Oscillator Configuration Register"
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.long 0x00 11. " SC2P ,Oscillator 2 pF capacitor load" "0,1"
|
|
bitfld.long 0x00 10. " SC4P ,Oscillator 4 pF capacitor load" "0,1"
|
|
bitfld.long 0x00 9. " SC8P ,Oscillator 8 pF capacitor load" "0,1"
|
|
bitfld.long 0x00 8. " SC16P ,Oscillator 16 pF capacitor load" "0,1"
|
|
newline
|
|
endif
|
|
sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
bitfld.long 0x00 4.--5. " RANGE ,System OSC range select" ",,4 Mhz-8 Mhz,8 Mhz-40 Mhz"
|
|
else
|
|
bitfld.long 0x00 4.--5. " RANGE ,System OSC range select" ",32 kHz-40 kHz,1 Mhz-8 Mhz,8 Mhz-32 Mhz"
|
|
endif
|
|
bitfld.long 0x00 3. " HGO ,High gain oscillator select" "Low-gain,High-gain"
|
|
bitfld.long 0x00 2. " EREFS ,External reference select" "External,Internal"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x4007B000+0x200))&0x800000)==0x800000)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SIRCCSR,Slow IRC Control Status Register"
|
|
rbitfld.long 0x00 25. " SIRCSEL ,Slow IRC selected" "Not selected,Selected"
|
|
rbitfld.long 0x00 24. " SIRCVLD ,Slow IRC valid" "Invalid,Valid"
|
|
bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked"
|
|
rbitfld.long 0x00 2. " SIRCLPEN ,Slow IRC low power enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 1. " SIRCSTEN ,Slow IRC stop enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " SIRCEN ,Slow IRC enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SIRCCSR,Slow IRC Control Status Register"
|
|
rbitfld.long 0x00 25. " SIRCSEL ,Slow IRC selected" "Not selected,Selected"
|
|
rbitfld.long 0x00 24. " SIRCVLD ,Slow IRC valid" "Invalid,Valid"
|
|
bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked"
|
|
bitfld.long 0x00 2. " SIRCLPEN ,Slow IRC low power enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " SIRCSTEN ,Slow IRC stop enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SIRCEN ,Slow IRC enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x4007B000+0x200))&0x01)==0x01)
|
|
rgroup.long 0x204++0x07
|
|
line.long 0x00 "SIRCDIV,Slow IRC Divide Register"
|
|
sif (cpuis("K32W*"))||cpuis("MKL28Z*")
|
|
bitfld.long 0x00 16.--18. " SOSCDIV3 ,System OSC clock divide 3" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8.--10. " SIRCDIV2 ,Slow IRC clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
bitfld.long 0x00 0.--2. " SIRCDIV1 ,Slow IRC clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
line.long 0x04 "SIRCCFG,Slow IRC Configuration Register"
|
|
sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
bitfld.long 0x04 0. " RANGE ,Frequency range" ",8 MHz"
|
|
else
|
|
bitfld.long 0x04 0. " RANGE ,Frequency range" "2 MHz,8 MHz"
|
|
endif
|
|
else
|
|
group.long 0x204++0x07
|
|
line.long 0x00 "SIRCDIV,Slow IRC Divide Register"
|
|
sif (cpuis("K32W*"))||cpuis("MKL28Z*")
|
|
bitfld.long 0x00 16.--18. " SOSCDIV3 ,System OSC clock divide 3" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8.--10. " SIRCDIV2 ,Slow IRC clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
bitfld.long 0x00 0.--2. " SIRCDIV1 ,Slow IRC clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
line.long 0x04 "SIRCCFG,Slow IRC Configuration Register"
|
|
sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
bitfld.long 0x04 0. " RANGE ,Frequency range" ",8 MHz"
|
|
else
|
|
bitfld.long 0x04 0. " RANGE ,Frequency range" "2 MHz,8 MHz"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x4007B000+0x300))&0x800000)==0x800000)
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "FIRCCSR,Fast IRC Control Status Register"
|
|
rbitfld.long 0x00 26. " FIRCERR ,Fast IRC clock error" "No error,Error"
|
|
rbitfld.long 0x00 25. " FIRCSEL ,Fast IRC selected" "Not selected,Selected"
|
|
rbitfld.long 0x00 24. " FIRCVLD ,Fast IRC valid" "Invalid,Valid"
|
|
bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked"
|
|
newline
|
|
sif (!cpuis("S32MTV"))
|
|
rbitfld.long 0x00 9. " FIRCTRUP ,Fast IRC trim update" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " FIRCTREN ,Fast IRC trim enable" "Disabled,Enabled"
|
|
endif
|
|
rbitfld.long 0x00 3. " FIRCREGOFF ,Fast IRC regulator enable" "Enabled,Disabled"
|
|
newline
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("K32W*"))||cpuis("MKL28Z*")
|
|
rbitfld.long 0x00 2. " FIRCLPEN ,Fast IRC low power enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 1. " FIRCSTEN ,Fast IRC stop enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " FIRCEN ,Fast IRC enable" "Disabled,Enabled"
|
|
else
|
|
rbitfld.long 0x00 0. " FIRCEN ,Fast IRC enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "FIRCCSR,Fast IRC Control Status Register"
|
|
eventfld.long 0x00 26. " FIRCERR ,Fast IRC clock error" "No error,Error"
|
|
rbitfld.long 0x00 25. " FIRCSEL ,Fast IRC selected" "Not selected,Selected"
|
|
rbitfld.long 0x00 24. " FIRCVLD ,Fast IRC valid" "Invalid,Valid"
|
|
bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked"
|
|
newline
|
|
sif (!cpuis("S32MTV"))
|
|
bitfld.long 0x00 9. " FIRCTRUP ,Fast IRC trim update" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FIRCTREN ,Fast IRC trim enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " FIRCREGOFF ,Fast IRC regulator enable" "Enabled,Disabled"
|
|
newline
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))||cpuis("MKL28Z*")
|
|
bitfld.long 0x00 2. " FIRCLPEN ,Fast IRC low power enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " FIRCSTEN ,Fast IRC stop enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FIRCEN ,Fast IRC enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 0. " FIRCEN ,Fast IRC enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x4007B000+0x300))&0x01)==0x01)
|
|
rgroup.long 0x304++0x07
|
|
line.long 0x00 "FIRCDIV,Fast IRC Divide Register"
|
|
sif cpuis("MKL28Z*")||cpuis("K32W*")
|
|
bitfld.long 0x00 16.--18. " FIRCDIV3 ,Fast IRC clock divider 3" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8.--10. " FIRCDIV2 ,Fast IRC clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
bitfld.long 0x00 0.--2. " FIRCDIV1 ,Fast IRC clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
line.long 0x04 "FIRCCFG,Fast IRC Configuration Register"
|
|
sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
bitfld.long 0x04 0.--1. " RANGE ,Frequency range" "48 MHz,?..."
|
|
else
|
|
bitfld.long 0x04 0.--1. " RANGE ,Frequency range" "48 MHz,52 MHz,56 MHz,60 MHz"
|
|
endif
|
|
else
|
|
group.long 0x304++0x07
|
|
line.long 0x00 "FIRCDIV,Fast IRC Divide Register"
|
|
sif cpuis("MKL28Z*")||cpuis("K32W*")
|
|
bitfld.long 0x00 16.--18. " FIRCDIV3 ,Fast IRC clock divider 3" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8.--10. " FIRCDIV2 ,Fast IRC clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
bitfld.long 0x00 0.--2. " FIRCDIV1 ,Fast IRC clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
line.long 0x04 "FIRCCFG,Fast IRC Configuration Register"
|
|
sif cpuis("MWCT1014S")||cpuis("MWCT1015S")||cpuis("MWCT1016S")
|
|
bitfld.long 0x04 0.--1. " RANGE ,Frequency range" "48 MHz,?..."
|
|
else
|
|
bitfld.long 0x04 0.--1. " RANGE ,Frequency range" "48 MHz,52 MHz,56 MHz,60 MHz"
|
|
endif
|
|
endif
|
|
sif (!cpuis("S32MTV")&&!cpuis("MWCT1014S")&&!cpuis("MWCT1015S")&&!cpuis("MWCT1016S"))
|
|
if (((per.l(ad:0x4007B000+0x300))&0x01)==0x01)
|
|
rgroup.long 0x30C++0x03
|
|
line.long 0x00 "FIRCTCFG,Fast IRC Trim Configuration Register"
|
|
bitfld.long 0x00 8.--10. " TRIMDIV ,Fast IRC trim predivide" "/1,/128,/256,/512,/1024,/2048,?..."
|
|
bitfld.long 0x00 0.--1. " TRIMSRC ,Trim source" ",,System OSC,RTC_OSC"
|
|
else
|
|
rgroup.long 0x30C++0x03
|
|
line.long 0x00 "FIRCTCFG,Fast IRC Trim Configuration Register"
|
|
bitfld.long 0x00 8.--10. " TRIMDIV ,Fast IRC trim predivide" "/1,/128,/256,/512,/1024,/2048,?..."
|
|
bitfld.long 0x00 0.--1. " TRIMSRC ,Trim source" ",,System OSC,RTC_OSC"
|
|
endif
|
|
endif
|
|
sif (cpuis("K32W*"))||cpuis("MKL28Z*")
|
|
if (((per.l(ad:0x4007B000+0x318))&0x200)==0x000)&&(((per.l(ad:0x4007B000+0x318))&0x100)==0x000)
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "FIRCSTAT,Fast IRC Status Register"
|
|
hexmask.long.byte 0x00 8.--13. 1. " TRIMCOAR ,Trim coarse"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TRIMFINE ,Trim fine status"
|
|
else
|
|
rgroup.long 0x318++0x03
|
|
line.long 0x00 "FIRCSTAT,Fast IRC Status Register"
|
|
hexmask.long.byte 0x00 8.--13. 1. " TRIMCOAR ,Trim coarse"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TRIMFINE ,Trim fine status"
|
|
endif
|
|
sif ((!cpuis("MKL28Z*"))&&!cpuis("S32MTV"))
|
|
group.long 0x400++0x0B
|
|
line.long 0x00 "ROSCCSR,RTC OSC Control Status Register"
|
|
bitfld.long 0x00 26. " ROSCERR ,RTC OSC clock error" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " ROSCSEL ,RTC OSC selected" "Not the system,The system"
|
|
bitfld.long 0x00 24. " ROSCVLD ,RTC OSC valid" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked"
|
|
bitfld.long 0x00 17. " ROSCCMRE ,RTC OSC clock monitor reset enable" "Interrupt,Reset"
|
|
bitfld.long 0x00 16. " ROSCCM ,RTC OSC clock monitor" "Disabled,Enabled"
|
|
line.long 0x04 "LPFLLCSR,Low Power FLL Control Status Register"
|
|
bitfld.long 0x04 26. " LPFLLERR ,LPFLL clock error" "Not detected,Detected"
|
|
bitfld.long 0x04 25. " LPFLLSEL ,LPFLL selected" "Not the system,The system"
|
|
bitfld.long 0x04 24. " LPFLLVLD ,LPFLL valid" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " LK ,Lock register" "Unlocked,Locked"
|
|
bitfld.long 0x04 17. " LPFLLCMRE ,LPFLL clock monitor reset enable" "Interrupt,Reset"
|
|
bitfld.long 0x04 16. " LPFLLCM ,LPFLL clock monitor" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " LPFLLTRMLOCK ,LPFLL trim LOCK" "Not locked,Locked"
|
|
bitfld.long 0x04 9. " LPFLLVLD ,LPFLL trim update" "AUTOTRIM,Referenced"
|
|
bitfld.long 0x04 8. " LPFLLTREN ,LPFLL trim enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " LPFLLSTEN ,LPFLL stop enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " LPFLLEN ,LPFLL enable" "Disabled,Enabled"
|
|
line.long 0x08 "LPFLLDIV,Low Power FLL Divide Register"
|
|
bitfld.long 0x08 16.--18. " LPFLLDIV3 ,LPFLL clock divide 3" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
bitfld.long 0x08 8.--10. " LPFLLDIV2 ,LPFLL clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
bitfld.long 0x08 0.--2. " LPFLLDIV1 ,LPFLL clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
group.long 0x508++0x03
|
|
line.long 0x00 "LPFLLCFG,Low Power FLL Configuration Register"
|
|
bitfld.long 0x00 0.--1. " FSEL ,Frequency select" "48 MHZ,72 MHZ,?..."
|
|
group.long 0x50C++0x03
|
|
line.long 0x00 "LPFLLTCFG,Low Power FLL Trim Configuration Register"
|
|
bitfld.long 0x00 16. " LOCKW2LSB ,Lock LPFLL with 2 LSBS" "1LSB,2LSB"
|
|
bitfld.long 0x00 8.--12. " TRIMDIV ,LPFLL trim predivide" "Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7,Divide by 8,Divide by 9,Divide by 10,Divide by 11,Divide by 12,Divide by 13,Divide by 14,Divide by 15,Divide by 16,Divide by 17,Divide by 18,Divide by 19,Divide by 20,Divide by 21,Divide by 22,Divide by 23,Divide by 24,Divide by 25,Divide by 26,Divide by 27,Divide by 28,Divide by 29,Divide by 30,Divide by 31,Divide by 32"
|
|
bitfld.long 0x00 0.--1. " TRIMSRC ,Trim source" "SIRC,FIRC,System OSC,RTC OSC"
|
|
group.long 0x514++0x03
|
|
line.long 0x00 "LPFLLSTAT,Low Power FLL Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AUTOTRIM ,Auto tune trim status"
|
|
endif
|
|
endif
|
|
sif (!cpuis("K32W*"))
|
|
if (((per.l(ad:0x4007B000+0x600))&0x800000)==0x800000)
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "SPLLCSR,System PLL Control Status Register"
|
|
rbitfld.long 0x00 26. " SPLLERR ,System PLL clock error" "No error,Error"
|
|
rbitfld.long 0x00 25. " SPLLSEL ,System PLL selected" "Not selected,Selected"
|
|
rbitfld.long 0x00 24. " SPLLVLD ,System PLL valid" "Invalid,Valid"
|
|
bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked"
|
|
newline
|
|
rbitfld.long 0x00 17. " SPLLCMRE ,System PLL clock monitor reset enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16. " SPLLCM ,System PLL clock monitor" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))||cpuis("MKL28Z*")
|
|
rbitfld.long 0x00 1. " SPLLSTEN ,System PLL stop enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " SPLLEN ,System PLL enable" "Disabled,Enabled"
|
|
else
|
|
rbitfld.long 0x00 0. " SPLLEN ,System PLL enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "SPLLCSR,System PLL Control Status Register"
|
|
eventfld.long 0x00 26. " SPLLERR ,System PLL clock error" "No error,Error"
|
|
rbitfld.long 0x00 25. " SPLLSEL ,System PLL selected" "Not selected,Selected"
|
|
rbitfld.long 0x00 24. " SPLLVLD ,System PLL valid" "Invalid,Valid"
|
|
bitfld.long 0x00 23. " LK ,Lock register" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 17. " SPLLCMRE ,System PLL clock monitor reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SPLLCM ,System PLL clock monitor" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*"))||cpuis("MKL28Z*")
|
|
bitfld.long 0x00 1. " SPLLSTEN ,System PLL stop enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SPLLEN ,System PLL enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 0. " SPLLEN ,System PLL enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x4007B000+0x600))&0x01)==0x01)
|
|
rgroup.long 0x604++0x07
|
|
line.long 0x00 "SPLLDIV,System PLL Divide Register"
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.long 0x00 16.--18. " SPLLDIV3 ,System PLL clock divide 3" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8.--10. " SPLLDIV2 ,System PLL clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
bitfld.long 0x00 0.--2. " SPLLDIV1 ,System PLL clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
line.long 0x04 "SPLLCFG,System PLL Configuration Register"
|
|
bitfld.long 0x04 16.--20. " MULT ,System PLL multiplier" "16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47"
|
|
bitfld.long 0x04 8.--10. " PREDIV ,PLL reference clock divider" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
newline
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKL28Z*")||cpuis("S32MTV"))
|
|
bitfld.long 0x04 0. " SOURCE ,Clock source" "SOSC,FIRC"
|
|
endif
|
|
else
|
|
group.long 0x604++0x07
|
|
line.long 0x00 "SPLLDIV,System PLL Divide Register"
|
|
sif cpuis("MKL28Z*")
|
|
bitfld.long 0x00 16.--18. " SPLLDIV3 ,System PLL clock divide 3" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8.--10. " SPLLDIV2 ,System PLL clock divide 2" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
bitfld.long 0x00 0.--2. " SPLLDIV1 ,System PLL clock divide 1" "Disabled,/1,/2,/4,/8,/16,/32,/64"
|
|
line.long 0x04 "SPLLCFG,System PLL Configuration Register"
|
|
bitfld.long 0x04 16.--20. " MULT ,System PLL multiplier" "16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47"
|
|
bitfld.long 0x04 8.--10. " PREDIV ,PLL reference clock divider" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
newline
|
|
sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKL28Z*")||cpuis("S32MTV"))
|
|
bitfld.long 0x04 0. " SOURCE ,Clock source" "SOSC,FIRC"
|
|
endif
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "TRGMUX (Trigger MUX)"
|
|
tree "TRGMUX1"
|
|
base ad:0x40027000
|
|
width 12.
|
|
if (((per.l(ad:0x40027000))&0x80000000)==0x00000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DMAMUX0,TRGMUX DMAMUX0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
else
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DMAMUX0,TRGMUX DMAMUX0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
endif
|
|
if (((per.l(ad:0x40027000+0x04))&0x80000000)==0x00000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "LPIT0,TRGMUX LPIT0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "LPIT0,TRGMUX LPIT0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
endif
|
|
if (((per.l(ad:0x40027000+0x10))&0x80000000)==0x00000000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TPM2,TRGMUX TPM2 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TPM2,TRGMUX TPM2 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
endif
|
|
if (((per.l(ad:0x40027000+0x10))&0x80000000)==0x00000000)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ADC0,TRGMUX ADC0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ADC0,TRGMUX ADC0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
endif
|
|
if (((per.l(ad:0x40027000+0x14))&0x80000000)==0x00000000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "LPUART2,TRGMUX LPUART2 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "LPUART2,TRGMUX LPUART2 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
endif
|
|
if (((per.l(ad:0x40027000+0x1C))&0x80000000)==0x00000000)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LPI2C2,TRGMUX LPI2C2 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
else
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "LPI2C2,TRGMUX LPI2C2 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
endif
|
|
if (((per.l(ad:0x40027000+0x24))&0x80000000)==0x00000000)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "LPSPI2,TRGMUX LPSPI2 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
else
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "LPSPI2,TRGMUX LPSPI2 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
endif
|
|
if (((per.l(ad:0x40027000+0x2C))&0x80000000)==0x00000000)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CMP0,TRGMUX CMP0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "CMP0,TRGMUX CMP0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
endif
|
|
if (((per.l(ad:0x40027000+0x30))&0x80000000)==0x00000000)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CMP1,TRGMUX CMP1 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "CMP1,TRGMUX CMP1 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
endif
|
|
if (((per.l(ad:0x40027000+0x34))&0x80000000)==0x00000000)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DAC0,TRGMUX DAC0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
else
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DAC0,TRGMUX DAC0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "TRGMUX2"
|
|
base ad:0x400A7000
|
|
width 12.
|
|
if (((per.l(ad:0x400A7000+0x08))&0x80000000)==0x00000000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TPM0,TRGMUX TPM0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TPM0,TRGMUX TPM0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
endif
|
|
if (((per.l(ad:0x400A7000+0x0C))&0x80000000)==0x00000000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TPM1,TRGMUX TPM1 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "TPM1,TRGMUX TPM1 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
endif
|
|
if (((per.l(ad:0x400A7000+0x10))&0x80000000)==0x00000000)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FLEXIO0,TRGMUX FLEXIO0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FLEXIO0,TRGMUX FLEXIO0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 24.--29. " SEL3 ,Trigger MUX Input 3 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 16.--21. " SEL2 ,Trigger MUX Input 2 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 8.--13. " SEL1 ,Trigger MUX Input 1 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
endif
|
|
if (((per.l(ad:0x400A7000+0x14))&0x80000000)==0x00000000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "LPUART0,TRGMUX LPUART0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "LPUART0,TRGMUX LPUART0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
endif
|
|
if (((per.l(ad:0x400A7000+0x18))&0x80000000)==0x00000000)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "LPUART1,TRGMUX LPUART1 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
else
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "LPUART1,TRGMUX LPUART1 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
endif
|
|
if (((per.l(ad:0x400A7000+0x1C))&0x80000000)==0x00000000)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LPI2C0,TRGMUX LPI2C0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
else
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "LPI2C0,TRGMUX LPI2C0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
endif
|
|
if (((per.l(ad:0x400A7000+0x20))&0x80000000)==0x00000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "LPI2C1,TRGMUX LPI2C1 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "LPI2C1,TRGMUX LPI2C1 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
endif
|
|
if (((per.l(ad:0x400A7000+0x24))&0x80000000)==0x00000000)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "LPSPI0,TRGMUX LPSPI0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
else
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "LPSPI0,TRGMUX LPSPI0 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
endif
|
|
if (((per.l(ad:0x400A7000+0x28))&0x80000000)==0x00000000)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "LPSPI1,TRGMUX LPSPI1 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "LPSPI1,TRGMUX LPSPI1 Register"
|
|
bitfld.long 0x00 31. " LK ,Register locked enable" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " SEL0 ,Trigger MUX Input 0 Source Select" ",LLWU0,LPIT0,LPIT0,LPIT0,LPIT0,RTC,RTC,LPTMR0,LPTMR1,TPM0,TPM0,TPM0,TPM1,TPM1,TPM1,TPM2,TPM2,TPM2,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,FLEXIO0,LPI2C0,LPI2C0,LPI2C1,LPI2C1,LPI2C2,LPI2C2,I2S0,I2S0,LPSPI0,LPSPI0,LPSPI1,LPSPI1,LPSPI2,LPSPI2,LPUART0,LPUART0,LPUART0,LPUART1,LPUART1,LPUART1,LPUART2,LPUART2,LPUART2,USB,PORTA,PORTB,PORTC,PORTD,LPCMP0,LPI2C3,LPI2C3,LPSPI3,LPSPI3,LPUART3,LPUART3,LPUART3,PORTE"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("MKL82Z*")
|
|
tree "TRNG (True Random Number Generator)"
|
|
base ad:0x400A5000
|
|
width 12.
|
|
if (((per.l(ad:0x40025000))&0x10000)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCTL,TRNG Miscellaneous Control Register"
|
|
bitfld.long 0x00 16. " PRGM ,Programming mode select" "Run mode,Program mode"
|
|
rbitfld.long 0x00 13. " TSTOP_OK ,RNG ring oscillator (used for entropy generation) is not running" "Running,Not running"
|
|
eventfld.long 0x00 12. " ERR ,Read: error status (read/write)" "No error/No effect,Error/Clear"
|
|
newline
|
|
rbitfld.long 0x00 11. " TST_OUT ,Test point inside ring oscillator" "0,1"
|
|
rbitfld.long 0x00 10. " ENT_VAL ,Entropy valid" "Not valid,Valid"
|
|
rbitfld.long 0x00 9. " FCT_VAL ,Frequency count valid" "Not valid,Valid"
|
|
newline
|
|
rbitfld.long 0x00 8. " FCT_FAIL ,Frequency count fail" "Not failed,Failed"
|
|
rbitfld.long 0x00 7. " FOR_SCLK ,Force system clock" "Ring oscillator,System clock"
|
|
rbitfld.long 0x00 6. " RST_DEF ,Reset defaults" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 5. " TRNG_ACC ,TRNG access mode" "No effect,Generate entropy value"
|
|
rbitfld.long 0x00 2.--3. " OSC_DIV ,Oscillator divide" "/1,/2,/4,/8"
|
|
rbitfld.long 0x00 0.--1. " SAMP_MODE ,Sample mode (data into: entropy shifter / statistical checker)" "Von Neumann both,Raw data both,Von Neumann/Raw data,?..."
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCTL,RNG TRNG Miscellaneous Control Register"
|
|
bitfld.long 0x00 16. " PRGM ,Programming mode select" "Run mode,Program mode"
|
|
rbitfld.long 0x00 13. " TSTOP_OK ,RNG ring oscillator (used for entropy generation) is not running" "Running,Not running"
|
|
eventfld.long 0x00 12. " ERR ,Read: error status (read/write)" "No error/No effect,Error/Clear"
|
|
newline
|
|
rbitfld.long 0x00 11. " TST_OUT ,Test point inside ring oscillator" "0,1"
|
|
rbitfld.long 0x00 10. " ENT_VAL ,Entropy valid" "Not valid,Valid"
|
|
rbitfld.long 0x00 9. " FCT_VAL ,Frequency count valid" "Not valid,Valid"
|
|
newline
|
|
rbitfld.long 0x00 8. " FCT_FAIL ,Frequency count fail" "Not failed,Failed"
|
|
bitfld.long 0x00 7. " FOR_SCLK ,Force system clock" "Ring oscillator,System clock"
|
|
bitfld.long 0x00 6. " RST_DEF ,Reset defaults" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 5. " TRNG_ACC ,TRNG access mode" "No effect,Generate entropy value"
|
|
bitfld.long 0x00 2.--3. " OSC_DIV ,Ring oscillator divide" "/1,/2,/4,/8"
|
|
bitfld.long 0x00 0.--1. " SAMP_MODE ,Sample mode (data into: entropy shifter / statistical checker)" "Von Neumann both,Raw data both,Von Neumann/Raw data,?..."
|
|
endif
|
|
if (((per.l(ad:0x40025000))&0x10000)==0x00)
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "SCMISC,TRNG Statistical Check Miscellaneous Register"
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "PKRRNG,TRNG Poker Range Register"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "PKRSQ,TRNG Poker Square Calculation Result Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " PKR_SQ ,Poker square calculation result"
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SDCTL,TRNG Seed Control Register"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "TOTSAM,Total Samples Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " TOT_SAM ,Total samples"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "FRQMIN,TRNG Frequency Count Minimum Limit Register"
|
|
if (((per.l(ad:0x40025000))&0x20)==0x20)
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "FRQCNT,TRNG Frequency Count Register"
|
|
hexmask.long.tbyte 0x00 0.--21. 1. " FRQ_CNT ,Frequency count"
|
|
else
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "FRQCNT,TRNG Frequency Count Register"
|
|
endif
|
|
rgroup.long 0x20++0x1B
|
|
line.long 0x00 "SCMC,TRNG Statistical Check Monobit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " MONO_CNT ,Monobit count"
|
|
line.long 0x04 "SCR1C,TRNG Statistical Check Run Length 1 Count Register"
|
|
hexmask.long.word 0x04 16.--30. 1. " R1_1_COUNT ,Runs of one (length 1 count)"
|
|
hexmask.long.word 0x04 0.--14. 1. " R1_0_COUNT ,Runs of zero (length 1 count)"
|
|
line.long 0x08 "SCR2C,TRNG Statistical Check Run Length 2 Count Register"
|
|
hexmask.long.word 0x08 16.--29. 1. " R2_1_COUNT ,Runs of one (length 2 count)"
|
|
hexmask.long.word 0x08 0.--13. 1. " R2_0_COUNT ,Runs of zero (length 2 count)"
|
|
line.long 0x0C "SCR3C,TRNG Statistical Check Run Length 3 Count Register"
|
|
hexmask.long.word 0x0C 16.--28. 1. " R3_1_COUNT ,Runs of ones (length 3 count)"
|
|
hexmask.long.word 0x0C 0.--12. 1. " R3_0_COUNT ,Runs of zeroes (length 3 count)"
|
|
line.long 0x10 "SCR4C,TRNG Statistical Check Run Length 4 Count Register"
|
|
hexmask.long.word 0x10 16.--27. 1. " R4_1_COUNT ,Runs of one (length 4 count)"
|
|
hexmask.long.word 0x10 0.--11. 1. " R4_0_COUNT ,Runs of zero (length 4 count)"
|
|
line.long 0x14 "SCR5C,TRNG Statistical Check Run Length 5 Count Register"
|
|
hexmask.long.word 0x14 16.--26. 1. " R5_1_COUNT ,Runs of one (length 5 count)"
|
|
hexmask.long.word 0x14 0.--10. 1. " R5_0_COUNT ,Runs of zero (length 5 count)"
|
|
line.long 0x18 "SCR6PC,TRNG Statistical Check Run Length 6+ Count Register"
|
|
hexmask.long.word 0x18 16.--26. 1. " R6P_1_COUNT ,Runs of one (length 6+ count)"
|
|
hexmask.long.word 0x18 0.--10. 1. " R6P_0_COUNT ,Runs of zero (length 6+ count)"
|
|
else
|
|
group.long 0x04++0x37
|
|
line.long 0x00 "SCMISC,TRNG Statistical Check Miscellaneous Register"
|
|
bitfld.long 0x00 16.--19. " RTY_CNT ,Retry count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LRUN_MAX ,Long run max limit"
|
|
line.long 0x04 "PKRRNG,TRNG Poker Range Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " PKR_RNG ,Poker range"
|
|
line.long 0x08 "PKRMAX,TRNG Poker Maximum Limit Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " PKR_MAX ,Poker maximum limit"
|
|
line.long 0x0C "SDCTL,TRNG Seed Control Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " ENT_DLY ,Entropy delay"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SAMP_SIZE ,Sample size"
|
|
line.long 0x10 "SBLIM,TRNG Sparse Bit Limit Register"
|
|
hexmask.long.word 0x10 0.--9. 1. " SB_LIM ,Sparse bit limit"
|
|
line.long 0x14 "FRQMIN,TRNG Frequency Count Minimum Limit Register"
|
|
hexmask.long.tbyte 0x14 0.--21. 1. " FRQ_MIN ,Frequency Count minimum limit"
|
|
line.long 0x18 "FRQMAX,TRNG Frequency Count Maximum Limit Register"
|
|
hexmask.long.tbyte 0x18 0.--21. 1. " FRQ_MAX ,Frequency Counter maximum limit"
|
|
line.long 0x1C "SCML,TRNG Statistical Check Monobit Limit Register"
|
|
hexmask.long.word 0x1C 16.--31. 1. " MONO_RNG ,Monobit range"
|
|
hexmask.long.word 0x1C 0.--15. 1. " MONO_MAX ,Monobit maximum limit"
|
|
line.long 0x20 "SCR1L,TRNG Statistical Check Run Length 1 Limit Register"
|
|
hexmask.long.word 0x20 16.--30. 1. " RUN1_RNG ,Run length 1 range"
|
|
hexmask.long.word 0x20 0.--14. 1. " RUN1_MAX ,Run length 1 maximum limit"
|
|
line.long 0x24 "SCR2L,TRNG Statistical Check Run Length 2 Limit Register"
|
|
hexmask.long.word 0x24 16.--29. 1. " RUN2_RNG ,Run length 2 range"
|
|
hexmask.long.word 0x24 0.--13. 1. " RUN2_MAX ,Run length 2 maximum limit"
|
|
line.long 0x28 "SCR3L,TRNG Statistical Check Run Length 3 Limit Register"
|
|
hexmask.long.word 0x28 16.--28. 1. " RUN3_RNG ,Run length 3 range"
|
|
hexmask.long.word 0x28 0.--12. 1. " RUN3_MAX ,Run length 3 maximum limit"
|
|
line.long 0x2C "SCR4L,TRNG Statistical Check Run Length 4 Limit Register"
|
|
hexmask.long.word 0x2C 16.--27. 1. " RUN4_RNG ,Run length 4 range"
|
|
hexmask.long.word 0x2C 0.--11. 1. " RUN4_MAX ,Run length 4 maximum limit"
|
|
line.long 0x30 "SCR5L,TRNG Statistical Check Run Length 5 Limit Register"
|
|
hexmask.long.word 0x30 16.--26. 1. " RUN5_RNG ,Run length 5 range"
|
|
hexmask.long.word 0x30 0.--10. 1. " RUN5_MAX ,Run length 5 maximum limit"
|
|
line.long 0x34 "SCR6PL,TRNG Statistical Check Run Length 6+ Limit Register"
|
|
hexmask.long.word 0x34 16.--26. 1. " RUN6P_RNG ,Run length 6+ range"
|
|
hexmask.long.word 0x34 0.--10. 1. " RUN6P_MAX ,Run length 6+ maximum limit"
|
|
endif
|
|
if (((per.l(ad:0x40025000))&0x10000)==0x10000)
|
|
hgroup.long 0x3C++0x03
|
|
hide.long 0x00 "STATUS,TRNG Status Register"
|
|
else
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "STATUS,TRNG Status Register"
|
|
bitfld.long 0x00 16.--19. " RETRY_COUNT ,Retry count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " TFMB ,Mono bit test fail" "Not failed,Failed"
|
|
bitfld.long 0x00 14. " TFP ,Poker test fail" "Not failed,Failed"
|
|
newline
|
|
bitfld.long 0x00 13. " TFLR ,Long run test fail" "Not failed,Failed"
|
|
bitfld.long 0x00 12. " TFSB ,Sparse bit test fail" "Not failed,Failed"
|
|
bitfld.long 0x00 11. " TF6PBR1 ,6 Plus bit run (sampling 1s) test fail" "Not failed,Failed"
|
|
newline
|
|
bitfld.long 0x00 10. " TF6PBR0 ,6 Plus bit run (sampling 0s) test fail" "Not failed,Failed"
|
|
bitfld.long 0x00 9. " TF5BR1 ,5-bit run (sampling 1s) test fail" "Not failed,Failed"
|
|
bitfld.long 0x00 8. " TF5BR0 ,5-bit run (sampling 0s) test fail" "Not failed,Failed"
|
|
newline
|
|
bitfld.long 0x00 7. " TF4BR1 ,4-bit run (sampling 1s) test fail" "Not failed,Failed"
|
|
bitfld.long 0x00 6. " TF4BR0 ,4-bit run (sampling 0s) test fail" "Not failed,Failed"
|
|
bitfld.long 0x00 5. " TF3BR1 ,3-bit run (sampling 1s) test fail" "Not failed,Failed"
|
|
newline
|
|
bitfld.long 0x00 4. " TF3BR0 ,3-bit run (sampling 0s) test fail" "Not failed,Failed"
|
|
bitfld.long 0x00 3. " TF2BR1 ,2-bit run (sampling 1s) test fail" "Not failed,Failed"
|
|
bitfld.long 0x00 2. " TF2BR0 ,2-bit run (sampling 0s) test fail" "Not failed,Failed"
|
|
newline
|
|
bitfld.long 0x00 1. " TF1BR1 ,1-bit run (sampling 1s) test fail" "Not failed,Failed"
|
|
bitfld.long 0x00 0. " TF1BR0 ,1-bit run (sampling 0s) test fail" "Not failed,Failed"
|
|
endif
|
|
sif (cpuis("IMX7ULP-CM4")||cpuis("IMX7ULP-CM4"))
|
|
if (((per.l(ad:0x40025000))&0x10420)==0x420)
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "ENT0,TRNG Entropy Read Register 0"
|
|
else
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "ENT0,TRNG Entropy Read Register 0"
|
|
endif
|
|
if (((per.l(ad:0x40025000))&0x10420)==0x420)
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "ENT1,TRNG Entropy Read Register 1"
|
|
else
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "ENT1,TRNG Entropy Read Register 1"
|
|
endif
|
|
if (((per.l(ad:0x40025000))&0x10420)==0x420)
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "ENT2,TRNG Entropy Read Register 2"
|
|
else
|
|
hgroup.long 0x48++0x03
|
|
hide.long 0x00 "ENT2,TRNG Entropy Read Register 2"
|
|
endif
|
|
if (((per.l(ad:0x40025000))&0x10420)==0x420)
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "ENT3,TRNG Entropy Read Register 3"
|
|
else
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "ENT3,TRNG Entropy Read Register 3"
|
|
endif
|
|
if (((per.l(ad:0x40025000))&0x10420)==0x420)
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "ENT4,TRNG Entropy Read Register 4"
|
|
else
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "ENT4,TRNG Entropy Read Register 4"
|
|
endif
|
|
if (((per.l(ad:0x40025000))&0x10420)==0x420)
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "ENT5,TRNG Entropy Read Register 5"
|
|
else
|
|
hgroup.long 0x54++0x03
|
|
hide.long 0x00 "ENT5,TRNG Entropy Read Register 5"
|
|
endif
|
|
if (((per.l(ad:0x40025000))&0x10420)==0x420)
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "ENT6,TRNG Entropy Read Register 6"
|
|
else
|
|
hgroup.long 0x58++0x03
|
|
hide.long 0x00 "ENT6,TRNG Entropy Read Register 6"
|
|
endif
|
|
if (((per.l(ad:0x40025000))&0x10420)==0x420)
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "ENT7,TRNG Entropy Read Register 7"
|
|
else
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "ENT7,TRNG Entropy Read Register 7"
|
|
endif
|
|
if (((per.l(ad:0x40025000))&0x10420)==0x420)
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "ENT8,TRNG Entropy Read Register 8"
|
|
else
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "ENT8,TRNG Entropy Read Register 8"
|
|
endif
|
|
if (((per.l(ad:0x40025000))&0x10420)==0x420)
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "ENT9,TRNG Entropy Read Register 9"
|
|
else
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "ENT9,TRNG Entropy Read Register 9"
|
|
endif
|
|
if (((per.l(ad:0x40025000))&0x10420)==0x420)
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "ENT10,TRNG Entropy Read Register 10"
|
|
else
|
|
hgroup.long 0x68++0x03
|
|
hide.long 0x00 "ENT10,TRNG Entropy Read Register 10"
|
|
endif
|
|
if (((per.l(ad:0x40025000))&0x10420)==0x420)
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "ENT11,TRNG Entropy Read Register 11"
|
|
else
|
|
hgroup.long 0x6C++0x03
|
|
hide.long 0x00 "ENT11,TRNG Entropy Read Register 11"
|
|
endif
|
|
if (((per.l(ad:0x40025000))&0x10420)==0x420)
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "ENT12,TRNG Entropy Read Register 12"
|
|
else
|
|
hgroup.long 0x70++0x03
|
|
hide.long 0x00 "ENT12,TRNG Entropy Read Register 12"
|
|
endif
|
|
if (((per.l(ad:0x40025000))&0x10420)==0x420)
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "ENT13,TRNG Entropy Read Register 13"
|
|
else
|
|
hgroup.long 0x74++0x03
|
|
hide.long 0x00 "ENT13,TRNG Entropy Read Register 13"
|
|
endif
|
|
if (((per.l(ad:0x40025000))&0x10420)==0x420)
|
|
rgroup.long 0x78++0x03
|
|
line.long 0x00 "ENT14,TRNG Entropy Read Register 14"
|
|
else
|
|
hgroup.long 0x78++0x03
|
|
hide.long 0x00 "ENT14,TRNG Entropy Read Register 14"
|
|
endif
|
|
if (((per.l(ad:0x40025000))&0x10420)==0x420)
|
|
hgroup.long 0x7C++0x03
|
|
hide.long 0x00 "ENT15,TRNG Entropy Read Register 15"
|
|
in
|
|
else
|
|
hgroup.long 0x7C++0x03
|
|
hide.long 0x00 "ENT15,TRNG Entropy Read Register 15"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40025000))&0x10420)==0x420)
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "ENT0,TRNG Entropy Read Register 0"
|
|
in
|
|
else
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "ENT0,TRNG Entropy Read Register 0"
|
|
endif
|
|
if (((per.l(ad:0x40025000))&0x10420)==0x420)
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "ENT1,TRNG Entropy Read Register 1"
|
|
in
|
|
else
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "ENT1,TRNG Entropy Read Register 1"
|
|
endif
|
|
if (((per.l(ad:0x40025000))&0x10420)==0x420)
|
|
hgroup.long 0x48++0x03
|
|
hide.long 0x00 "ENT2,TRNG Entropy Read Register 2"
|
|
in
|
|
else
|
|
hgroup.long 0x48++0x03
|
|
hide.long 0x00 "ENT2,TRNG Entropy Read Register 2"
|
|
endif
|
|
if (((per.l(ad:0x40025000))&0x10420)==0x420)
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "ENT3,TRNG Entropy Read Register 3"
|
|
in
|
|
else
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "ENT3,TRNG Entropy Read Register 3"
|
|
endif
|
|
if (((per.l(ad:0x40025000))&0x10420)==0x420)
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "ENT4,TRNG Entropy Read Register 4"
|
|
in
|
|
else
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "ENT4,TRNG Entropy Read Register 4"
|
|
endif
|
|
if (((per.l(ad:0x40025000))&0x10420)==0x420)
|
|
hgroup.long 0x54++0x03
|
|
hide.long 0x00 "ENT5,TRNG Entropy Read Register 5"
|
|
in
|
|
else
|
|
hgroup.long 0x54++0x03
|
|
hide.long 0x00 "ENT5,TRNG Entropy Read Register 5"
|
|
endif
|
|
if (((per.l(ad:0x40025000))&0x10420)==0x420)
|
|
hgroup.long 0x58++0x03
|
|
hide.long 0x00 "ENT6,TRNG Entropy Read Register 6"
|
|
in
|
|
else
|
|
hgroup.long 0x58++0x03
|
|
hide.long 0x00 "ENT6,TRNG Entropy Read Register 6"
|
|
endif
|
|
if (((per.l(ad:0x40025000))&0x10420)==0x420)
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "ENT7,TRNG Entropy Read Register 7"
|
|
in
|
|
else
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "ENT7,TRNG Entropy Read Register 7"
|
|
endif
|
|
if (((per.l(ad:0x40025000))&0x10420)==0x420)
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "ENT8,TRNG Entropy Read Register 8"
|
|
in
|
|
else
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "ENT8,TRNG Entropy Read Register 8"
|
|
endif
|
|
if (((per.l(ad:0x40025000))&0x10420)==0x420)
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "ENT9,TRNG Entropy Read Register 9"
|
|
in
|
|
else
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "ENT9,TRNG Entropy Read Register 9"
|
|
endif
|
|
if (((per.l(ad:0x40025000))&0x10420)==0x420)
|
|
hgroup.long 0x68++0x03
|
|
hide.long 0x00 "ENT10,TRNG Entropy Read Register 10"
|
|
in
|
|
else
|
|
hgroup.long 0x68++0x03
|
|
hide.long 0x00 "ENT10,TRNG Entropy Read Register 10"
|
|
endif
|
|
if (((per.l(ad:0x40025000))&0x10420)==0x420)
|
|
hgroup.long 0x6C++0x03
|
|
hide.long 0x00 "ENT11,TRNG Entropy Read Register 11"
|
|
in
|
|
else
|
|
hgroup.long 0x6C++0x03
|
|
hide.long 0x00 "ENT11,TRNG Entropy Read Register 11"
|
|
endif
|
|
if (((per.l(ad:0x40025000))&0x10420)==0x420)
|
|
hgroup.long 0x70++0x03
|
|
hide.long 0x00 "ENT12,TRNG Entropy Read Register 12"
|
|
in
|
|
else
|
|
hgroup.long 0x70++0x03
|
|
hide.long 0x00 "ENT12,TRNG Entropy Read Register 12"
|
|
endif
|
|
if (((per.l(ad:0x40025000))&0x10420)==0x420)
|
|
hgroup.long 0x74++0x03
|
|
hide.long 0x00 "ENT13,TRNG Entropy Read Register 13"
|
|
in
|
|
else
|
|
hgroup.long 0x74++0x03
|
|
hide.long 0x00 "ENT13,TRNG Entropy Read Register 13"
|
|
endif
|
|
if (((per.l(ad:0x40025000))&0x10420)==0x420)
|
|
hgroup.long 0x78++0x03
|
|
hide.long 0x00 "ENT14,TRNG Entropy Read Register 14"
|
|
in
|
|
else
|
|
hgroup.long 0x78++0x03
|
|
hide.long 0x00 "ENT14,TRNG Entropy Read Register 14"
|
|
endif
|
|
if (((per.l(ad:0x40025000))&0x10420)==0x420)
|
|
hgroup.long 0x7C++0x03
|
|
hide.long 0x00 "ENT15,TRNG Entropy Read Register 15"
|
|
in
|
|
else
|
|
hgroup.long 0x7C++0x03
|
|
hide.long 0x00 "ENT15,TRNG Entropy Read Register 15"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40025000))&0x10000)==0x0)
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "PKRCNT10,TRNG Statistical Check Poker Count 1 And 0 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PKR_1_CT ,Poker 1h count"
|
|
hexmask.long.word 0x00 0.--15. 1. " PKR_0_CT ,Poker 0h count"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "PKRCNT32,TRNG Statistical Check Poker Count 3 And 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PKR_3_CT ,Poker 3h count"
|
|
hexmask.long.word 0x00 0.--15. 1. " PKR_2_CT ,Poker 2h count"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "PKRCNT54,TRNG Statistical Check Poker Count 5 And 4 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PKR_5_CT ,Poker 5h count"
|
|
hexmask.long.word 0x00 0.--15. 1. " PKR_4_CT ,Poker 4h count"
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "PKRCNT76,TRNG Statistical Check Poker Count 7 And 6 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PKR_7_CT ,Poker 7h count"
|
|
hexmask.long.word 0x00 0.--15. 1. " PKR_6_CT ,Poker 6h count"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "PKRCNT98,TRNG Statistical Check Poker Count 9 And 8 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PKR_9_CT ,Poker 9h count"
|
|
hexmask.long.word 0x00 0.--15. 1. " PKR_8_CT ,Poker 8h count"
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "PKRCNTBA,TRNG Statistical Check Poker Count B And A Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PKR_B_CT ,Poker Bh count"
|
|
hexmask.long.word 0x00 0.--15. 1. " PKR_A_CT ,Poker Ah count"
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "PKRCNTDC,TRNG Statistical Check Poker Count D And C Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PKR_D_CT ,Poker Dh count"
|
|
hexmask.long.word 0x00 0.--15. 1. " PKR_C_CT ,Poker Ch count"
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "PKRCNTFE,TRNG Statistical Check Poker Count F And E Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PKR_F_CT ,Poker Fh count"
|
|
hexmask.long.word 0x00 0.--15. 1. " PKR_E_CT ,Poker Eh count"
|
|
else
|
|
hgroup.long 0x80++0x03
|
|
hide.long 0x00 "PKRCNT10,TRNG Statistical Check Poker Count 1 And 0 Register"
|
|
hgroup.long 0x84++0x03
|
|
hide.long 0x00 "PKRCNT32,TRNG Statistical Check Poker Count 3 And 2 Register"
|
|
hgroup.long 0x88++0x03
|
|
hide.long 0x00 "PKRCNT54,TRNG Statistical Check Poker Count 5 And 4 Register"
|
|
hgroup.long 0x8C++0x03
|
|
hide.long 0x00 "PKRCNT76,TRNG Statistical Check Poker Count 7 And 6 Register"
|
|
hgroup.long 0x90++0x03
|
|
hide.long 0x00 "PKRCNT98,TRNG Statistical Check Poker Count 9 And 8 Register"
|
|
hgroup.long 0x94++0x03
|
|
hide.long 0x00 "PKRCNTBA,TRNG Statistical Check Poker Count B And A Register"
|
|
hgroup.long 0x98++0x03
|
|
hide.long 0x00 "PKRCNTDC,TRNG Statistical Check Poker Count D And C Register"
|
|
hgroup.long 0x9C++0x03
|
|
hide.long 0x00 "PKRCNTFE,TRNG Statistical Check Poker Count F And E Register"
|
|
endif
|
|
sif (cpuis("MK8?FN256V*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKV5*"))
|
|
group.long 0xB0++0x0F
|
|
line.long 0x00 "SEC_CFG,TRNG Security Configuration Register"
|
|
bitfld.long 0x00 1. " NO_PRGM ,TRNG registers cannot be programmed" "No,Yes"
|
|
line.long 0x04 "INT_CTRL,TRNG Interrupt Control Register"
|
|
bitfld.long 0x04 2. " FRQ_CT_FAIL ,Frequency count fail interrupt control status" "Cleared,Active"
|
|
bitfld.long 0x04 1. " ENT_VAL ,Entropy valid interrupt control status" "Cleared,Active"
|
|
bitfld.long 0x04 0. " HW_ERR ,HW error interrupt control status" "Cleared,Active"
|
|
line.long 0x08 "INT_MASK,TRNG Mask Register"
|
|
bitfld.long 0x08 2. " FRQ_CT_FAIL ,Frequency count fail interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x08 1. " ENT_VAL ,Entropy valid interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " HW_ERR ,HW error interrupt mask" "Masked,Not masked"
|
|
line.long 0x0C "INT_STATUS,TRNG Interrupt Status Register"
|
|
bitfld.long 0x0C 2. " FRQ_CT_FAIL ,Frequency count fail interrupt status" "Not failed,Failed"
|
|
rbitfld.long 0x0C 1. " ENT_VAL ,Entropy valid interrupt status" "Invalid,Valid"
|
|
rbitfld.long 0x0C 0. " HW_ERR ,HW error interrupt status" "No error,Error"
|
|
else
|
|
group.long 0xA0++0x0F
|
|
line.long 0x00 "SEC_CFG,TRNG Security Configuration Register"
|
|
bitfld.long 0x00 1. " NO_PRGM ,TRNG registers cannot be programmed" "No,Yes"
|
|
line.long 0x04 "INT_CTRL,TRNG Interrupt Control Register"
|
|
bitfld.long 0x04 2. " FRQ_CT_FAIL ,Frequency count fail interrupt control status" "Cleared,Active"
|
|
bitfld.long 0x04 1. " ENT_VAL ,Entropy valid interrupt control status" "Cleared,Active"
|
|
bitfld.long 0x04 0. " HW_ERR ,HW error interrupt control status" "Cleared,Active"
|
|
line.long 0x08 "INT_MASK,TRNG Mask Register"
|
|
bitfld.long 0x08 2. " FRQ_CT_FAIL ,Frequency count fail interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x08 1. " ENT_VAL ,Entropy valid interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " HW_ERR ,HW error interrupt mask" "Masked,Not masked"
|
|
line.long 0x0C "INT_STATUS,TRNG Interrupt Status Register"
|
|
sif (cpuis("K32W0?2S1M*")||cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4"))
|
|
rbitfld.long 0x0C 2. " FRQ_CT_FAIL ,Frequency count fail interrupt status" "Not failed,Failed"
|
|
else
|
|
bitfld.long 0x0C 2. " FRQ_CT_FAIL ,Frequency count fail interrupt status" "Not failed,Failed"
|
|
endif
|
|
newline
|
|
rbitfld.long 0x0C 1. " ENT_VAL ,Entropy valid interrupt status" "Invalid,Valid"
|
|
rbitfld.long 0x0C 0. " HW_ERR ,HW error interrupt status" "No error,Error"
|
|
endif
|
|
rgroup.long 0xF0++0x07
|
|
line.long 0x00 "VID1,Version ID (MS) Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TRNG_IP_ID ,Shows IP ID"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TRNG_MAJ_REV ,Shows IP's major revision of the TRNG"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TRNG_MIN_REV ,Shows IP's minor revision of the TRNG"
|
|
line.long 0x04 "VID2,Version ID (LS) Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " TRNG_ERA ,Shows compile options for the TRNG"
|
|
hexmask.long.byte 0x04 16.--23. 1. " TRNG_INTG_OPT ,Shows integration options for the TRNG"
|
|
hexmask.long.byte 0x04 8.--15. 1. " TRNG_ECO_REV ,Shows IP's ECO revision of the TRNG"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. " TRNG_CONFIG_OPT ,Shows IP's Configuration options for the TRNG"
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "SA-TRNG (Standalone True Random Number Generator)"
|
|
base ad:0x400A5000
|
|
width 12.
|
|
if (((per.l(ad:0x400A5000))&0x10000)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCTL,TRNG Miscellaneous Control Register"
|
|
bitfld.long 0x00 16. " PRGM ,Programming mode select" "Run mode,Program mode"
|
|
rbitfld.long 0x00 13. " TSTOP_OK ,RNG ring oscillator (used for entropy generation) is not running" "Running,Not running"
|
|
eventfld.long 0x00 12. " ERR ,Read: error status (read/write)" "No error/No effect,Error/Clear"
|
|
newline
|
|
rbitfld.long 0x00 11. " TST_OUT ,Test point inside ring oscillator" "0,1"
|
|
rbitfld.long 0x00 10. " ENT_VAL ,Entropy valid" "Not valid,Valid"
|
|
rbitfld.long 0x00 9. " FCT_VAL ,Frequency count valid" "Not valid,Valid"
|
|
newline
|
|
rbitfld.long 0x00 8. " FCT_FAIL ,Frequency count fail" "Not failed,Failed"
|
|
rbitfld.long 0x00 7. " FOR_SCLK ,Force system clock" "Ring oscillator,System clock"
|
|
rbitfld.long 0x00 6. " RST_DEF ,Reset defaults" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 5. " TRNG_ACC ,TRNG access mode" "No effect,Generate entropy value"
|
|
rbitfld.long 0x00 2.--3. " OSC_DIV ,Oscillator divide" "/1,/2,/4,/8"
|
|
rbitfld.long 0x00 0.--1. " SAMP_MODE ,Sample mode (data into: entropy shifter / statistical checker)" "Von Neumann both,Raw data both,Von Neumann/Raw data,?..."
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCTL,RNG TRNG Miscellaneous Control Register"
|
|
bitfld.long 0x00 16. " PRGM ,Programming mode select" "Run mode,Program mode"
|
|
rbitfld.long 0x00 13. " TSTOP_OK ,RNG ring oscillator (used for entropy generation) is not running" "Running,Not running"
|
|
eventfld.long 0x00 12. " ERR ,Read: error status (read/write)" "No error/No effect,Error/Clear"
|
|
newline
|
|
rbitfld.long 0x00 11. " TST_OUT ,Test point inside ring oscillator" "0,1"
|
|
rbitfld.long 0x00 10. " ENT_VAL ,Entropy valid" "Not valid,Valid"
|
|
rbitfld.long 0x00 9. " FCT_VAL ,Frequency count valid" "Not valid,Valid"
|
|
newline
|
|
rbitfld.long 0x00 8. " FCT_FAIL ,Frequency count fail" "Not failed,Failed"
|
|
bitfld.long 0x00 7. " FOR_SCLK ,Force system clock" "Ring oscillator,System clock"
|
|
bitfld.long 0x00 6. " RST_DEF ,Reset defaults" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 5. " TRNG_ACC ,TRNG access mode" "No effect,Generate entropy value"
|
|
bitfld.long 0x00 2.--3. " OSC_DIV ,Ring oscillator divide" "/1,/2,/4,/8"
|
|
bitfld.long 0x00 0.--1. " SAMP_MODE ,Sample mode (data into: entropy shifter / statistical checker)" "Von Neumann both,Raw data both,Von Neumann/Raw data,?..."
|
|
endif
|
|
if (((per.l(ad:0x400A5000))&0x10000)==0x00)
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "SCMISC,TRNG Statistical Check Miscellaneous Register"
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "PKRRNG,TRNG Poker Range Register"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "PKRSQ,TRNG Poker Square Calculation Result Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " PKR_SQ ,Poker square calculation result"
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SDCTL,TRNG Seed Control Register"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "TOTSAM,Total Samples Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " TOT_SAM ,Total samples"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "FRQMIN,TRNG Frequency Count Minimum Limit Register"
|
|
if (((per.l(ad:0x400A5000))&0x20)==0x20)
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "FRQCNT,TRNG Frequency Count Register"
|
|
hexmask.long.tbyte 0x00 0.--21. 1. " FRQ_CNT ,Frequency count"
|
|
else
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "FRQCNT,TRNG Frequency Count Register"
|
|
endif
|
|
rgroup.long 0x20++0x1B
|
|
line.long 0x00 "SCMC,TRNG Statistical Check Monobit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " MONO_CNT ,Monobit count"
|
|
line.long 0x04 "SCR1C,TRNG Statistical Check Run Length 1 Count Register"
|
|
hexmask.long.word 0x04 16.--30. 1. " R1_1_COUNT ,Runs of one (length 1 count)"
|
|
hexmask.long.word 0x04 0.--14. 1. " R1_0_COUNT ,Runs of zero (length 1 count)"
|
|
line.long 0x08 "SCR2C,TRNG Statistical Check Run Length 2 Count Register"
|
|
hexmask.long.word 0x08 16.--29. 1. " R2_1_COUNT ,Runs of one (length 2 count)"
|
|
hexmask.long.word 0x08 0.--13. 1. " R2_0_COUNT ,Runs of zero (length 2 count)"
|
|
line.long 0x0C "SCR3C,TRNG Statistical Check Run Length 3 Count Register"
|
|
hexmask.long.word 0x0C 16.--28. 1. " R3_1_COUNT ,Runs of ones (length 3 count)"
|
|
hexmask.long.word 0x0C 0.--12. 1. " R3_0_COUNT ,Runs of zeroes (length 3 count)"
|
|
line.long 0x10 "SCR4C,TRNG Statistical Check Run Length 4 Count Register"
|
|
hexmask.long.word 0x10 16.--27. 1. " R4_1_COUNT ,Runs of one (length 4 count)"
|
|
hexmask.long.word 0x10 0.--11. 1. " R4_0_COUNT ,Runs of zero (length 4 count)"
|
|
line.long 0x14 "SCR5C,TRNG Statistical Check Run Length 5 Count Register"
|
|
hexmask.long.word 0x14 16.--26. 1. " R5_1_COUNT ,Runs of one (length 5 count)"
|
|
hexmask.long.word 0x14 0.--10. 1. " R5_0_COUNT ,Runs of zero (length 5 count)"
|
|
line.long 0x18 "SCR6PC,TRNG Statistical Check Run Length 6+ Count Register"
|
|
hexmask.long.word 0x18 16.--26. 1. " R6P_1_COUNT ,Runs of one (length 6+ count)"
|
|
hexmask.long.word 0x18 0.--10. 1. " R6P_0_COUNT ,Runs of zero (length 6+ count)"
|
|
else
|
|
group.long 0x04++0x37
|
|
line.long 0x00 "SCMISC,TRNG Statistical Check Miscellaneous Register"
|
|
bitfld.long 0x00 16.--19. " RTY_CNT ,Retry count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LRUN_MAX ,Long run max limit"
|
|
line.long 0x04 "PKRRNG,TRNG Poker Range Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " PKR_RNG ,Poker range"
|
|
line.long 0x08 "PKRMAX,TRNG Poker Maximum Limit Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " PKR_MAX ,Poker maximum limit"
|
|
line.long 0x0C "SDCTL,TRNG Seed Control Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " ENT_DLY ,Entropy delay"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SAMP_SIZE ,Sample size"
|
|
line.long 0x10 "SBLIM,TRNG Sparse Bit Limit Register"
|
|
hexmask.long.word 0x10 0.--9. 1. " SB_LIM ,Sparse bit limit"
|
|
line.long 0x14 "FRQMIN,TRNG Frequency Count Minimum Limit Register"
|
|
hexmask.long.tbyte 0x14 0.--21. 1. " FRQ_MIN ,Frequency Count minimum limit"
|
|
line.long 0x18 "FRQMAX,TRNG Frequency Count Maximum Limit Register"
|
|
hexmask.long.tbyte 0x18 0.--21. 1. " FRQ_MAX ,Frequency Counter maximum limit"
|
|
line.long 0x1C "SCML,TRNG Statistical Check Monobit Limit Register"
|
|
hexmask.long.word 0x1C 16.--31. 1. " MONO_RNG ,Monobit range"
|
|
hexmask.long.word 0x1C 0.--15. 1. " MONO_MAX ,Monobit maximum limit"
|
|
line.long 0x20 "SCR1L,TRNG Statistical Check Run Length 1 Limit Register"
|
|
hexmask.long.word 0x20 16.--30. 1. " RUN1_RNG ,Run length 1 range"
|
|
hexmask.long.word 0x20 0.--14. 1. " RUN1_MAX ,Run length 1 maximum limit"
|
|
line.long 0x24 "SCR2L,TRNG Statistical Check Run Length 2 Limit Register"
|
|
hexmask.long.word 0x24 16.--29. 1. " RUN2_RNG ,Run length 2 range"
|
|
hexmask.long.word 0x24 0.--13. 1. " RUN2_MAX ,Run length 2 maximum limit"
|
|
line.long 0x28 "SCR3L,TRNG Statistical Check Run Length 3 Limit Register"
|
|
hexmask.long.word 0x28 16.--28. 1. " RUN3_RNG ,Run length 3 range"
|
|
hexmask.long.word 0x28 0.--12. 1. " RUN3_MAX ,Run length 3 maximum limit"
|
|
line.long 0x2C "SCR4L,TRNG Statistical Check Run Length 4 Limit Register"
|
|
hexmask.long.word 0x2C 16.--27. 1. " RUN4_RNG ,Run length 4 range"
|
|
hexmask.long.word 0x2C 0.--11. 1. " RUN4_MAX ,Run length 4 maximum limit"
|
|
line.long 0x30 "SCR5L,TRNG Statistical Check Run Length 5 Limit Register"
|
|
hexmask.long.word 0x30 16.--26. 1. " RUN5_RNG ,Run length 5 range"
|
|
hexmask.long.word 0x30 0.--10. 1. " RUN5_MAX ,Run length 5 maximum limit"
|
|
line.long 0x34 "SCR6PL,TRNG Statistical Check Run Length 6+ Limit Register"
|
|
hexmask.long.word 0x34 16.--26. 1. " RUN6P_RNG ,Run length 6+ range"
|
|
hexmask.long.word 0x34 0.--10. 1. " RUN6P_MAX ,Run length 6+ maximum limit"
|
|
endif
|
|
if (((per.l(ad:0x400A5000))&0x10000)==0x10000)
|
|
hgroup.long 0x3C++0x03
|
|
hide.long 0x00 "STATUS,TRNG Status Register"
|
|
else
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "STATUS,TRNG Status Register"
|
|
bitfld.long 0x00 16.--19. " RETRY_COUNT ,Retry count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " TFMB ,Mono bit test fail" "Not failed,Failed"
|
|
bitfld.long 0x00 14. " TFP ,Poker test fail" "Not failed,Failed"
|
|
newline
|
|
bitfld.long 0x00 13. " TFLR ,Long run test fail" "Not failed,Failed"
|
|
bitfld.long 0x00 12. " TFSB ,Sparse bit test fail" "Not failed,Failed"
|
|
bitfld.long 0x00 11. " TF6PBR1 ,6 Plus bit run (sampling 1s) test fail" "Not failed,Failed"
|
|
newline
|
|
bitfld.long 0x00 10. " TF6PBR0 ,6 Plus bit run (sampling 0s) test fail" "Not failed,Failed"
|
|
bitfld.long 0x00 9. " TF5BR1 ,5-bit run (sampling 1s) test fail" "Not failed,Failed"
|
|
bitfld.long 0x00 8. " TF5BR0 ,5-bit run (sampling 0s) test fail" "Not failed,Failed"
|
|
newline
|
|
bitfld.long 0x00 7. " TF4BR1 ,4-bit run (sampling 1s) test fail" "Not failed,Failed"
|
|
bitfld.long 0x00 6. " TF4BR0 ,4-bit run (sampling 0s) test fail" "Not failed,Failed"
|
|
bitfld.long 0x00 5. " TF3BR1 ,3-bit run (sampling 1s) test fail" "Not failed,Failed"
|
|
newline
|
|
bitfld.long 0x00 4. " TF3BR0 ,3-bit run (sampling 0s) test fail" "Not failed,Failed"
|
|
bitfld.long 0x00 3. " TF2BR1 ,2-bit run (sampling 1s) test fail" "Not failed,Failed"
|
|
bitfld.long 0x00 2. " TF2BR0 ,2-bit run (sampling 0s) test fail" "Not failed,Failed"
|
|
newline
|
|
bitfld.long 0x00 1. " TF1BR1 ,1-bit run (sampling 1s) test fail" "Not failed,Failed"
|
|
bitfld.long 0x00 0. " TF1BR0 ,1-bit run (sampling 0s) test fail" "Not failed,Failed"
|
|
endif
|
|
sif (cpuis("IMX7ULP-CM4")||cpuis("IMX7ULP-CM4"))
|
|
if (((per.l(ad:0x400A5000))&0x10420)==0x420)
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "ENT0,TRNG Entropy Read Register 0"
|
|
else
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "ENT0,TRNG Entropy Read Register 0"
|
|
endif
|
|
if (((per.l(ad:0x400A5000))&0x10420)==0x420)
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "ENT1,TRNG Entropy Read Register 1"
|
|
else
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "ENT1,TRNG Entropy Read Register 1"
|
|
endif
|
|
if (((per.l(ad:0x400A5000))&0x10420)==0x420)
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "ENT2,TRNG Entropy Read Register 2"
|
|
else
|
|
hgroup.long 0x48++0x03
|
|
hide.long 0x00 "ENT2,TRNG Entropy Read Register 2"
|
|
endif
|
|
if (((per.l(ad:0x400A5000))&0x10420)==0x420)
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "ENT3,TRNG Entropy Read Register 3"
|
|
else
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "ENT3,TRNG Entropy Read Register 3"
|
|
endif
|
|
if (((per.l(ad:0x400A5000))&0x10420)==0x420)
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "ENT4,TRNG Entropy Read Register 4"
|
|
else
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "ENT4,TRNG Entropy Read Register 4"
|
|
endif
|
|
if (((per.l(ad:0x400A5000))&0x10420)==0x420)
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "ENT5,TRNG Entropy Read Register 5"
|
|
else
|
|
hgroup.long 0x54++0x03
|
|
hide.long 0x00 "ENT5,TRNG Entropy Read Register 5"
|
|
endif
|
|
if (((per.l(ad:0x400A5000))&0x10420)==0x420)
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "ENT6,TRNG Entropy Read Register 6"
|
|
else
|
|
hgroup.long 0x58++0x03
|
|
hide.long 0x00 "ENT6,TRNG Entropy Read Register 6"
|
|
endif
|
|
if (((per.l(ad:0x400A5000))&0x10420)==0x420)
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "ENT7,TRNG Entropy Read Register 7"
|
|
else
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "ENT7,TRNG Entropy Read Register 7"
|
|
endif
|
|
if (((per.l(ad:0x400A5000))&0x10420)==0x420)
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "ENT8,TRNG Entropy Read Register 8"
|
|
else
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "ENT8,TRNG Entropy Read Register 8"
|
|
endif
|
|
if (((per.l(ad:0x400A5000))&0x10420)==0x420)
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "ENT9,TRNG Entropy Read Register 9"
|
|
else
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "ENT9,TRNG Entropy Read Register 9"
|
|
endif
|
|
if (((per.l(ad:0x400A5000))&0x10420)==0x420)
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "ENT10,TRNG Entropy Read Register 10"
|
|
else
|
|
hgroup.long 0x68++0x03
|
|
hide.long 0x00 "ENT10,TRNG Entropy Read Register 10"
|
|
endif
|
|
if (((per.l(ad:0x400A5000))&0x10420)==0x420)
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "ENT11,TRNG Entropy Read Register 11"
|
|
else
|
|
hgroup.long 0x6C++0x03
|
|
hide.long 0x00 "ENT11,TRNG Entropy Read Register 11"
|
|
endif
|
|
if (((per.l(ad:0x400A5000))&0x10420)==0x420)
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "ENT12,TRNG Entropy Read Register 12"
|
|
else
|
|
hgroup.long 0x70++0x03
|
|
hide.long 0x00 "ENT12,TRNG Entropy Read Register 12"
|
|
endif
|
|
if (((per.l(ad:0x400A5000))&0x10420)==0x420)
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "ENT13,TRNG Entropy Read Register 13"
|
|
else
|
|
hgroup.long 0x74++0x03
|
|
hide.long 0x00 "ENT13,TRNG Entropy Read Register 13"
|
|
endif
|
|
if (((per.l(ad:0x400A5000))&0x10420)==0x420)
|
|
rgroup.long 0x78++0x03
|
|
line.long 0x00 "ENT14,TRNG Entropy Read Register 14"
|
|
else
|
|
hgroup.long 0x78++0x03
|
|
hide.long 0x00 "ENT14,TRNG Entropy Read Register 14"
|
|
endif
|
|
if (((per.l(ad:0x400A5000))&0x10420)==0x420)
|
|
hgroup.long 0x7C++0x03
|
|
hide.long 0x00 "ENT15,TRNG Entropy Read Register 15"
|
|
in
|
|
else
|
|
hgroup.long 0x7C++0x03
|
|
hide.long 0x00 "ENT15,TRNG Entropy Read Register 15"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x400A5000))&0x10420)==0x420)
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "ENT0,TRNG Entropy Read Register 0"
|
|
in
|
|
else
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "ENT0,TRNG Entropy Read Register 0"
|
|
endif
|
|
if (((per.l(ad:0x400A5000))&0x10420)==0x420)
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "ENT1,TRNG Entropy Read Register 1"
|
|
in
|
|
else
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "ENT1,TRNG Entropy Read Register 1"
|
|
endif
|
|
if (((per.l(ad:0x400A5000))&0x10420)==0x420)
|
|
hgroup.long 0x48++0x03
|
|
hide.long 0x00 "ENT2,TRNG Entropy Read Register 2"
|
|
in
|
|
else
|
|
hgroup.long 0x48++0x03
|
|
hide.long 0x00 "ENT2,TRNG Entropy Read Register 2"
|
|
endif
|
|
if (((per.l(ad:0x400A5000))&0x10420)==0x420)
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "ENT3,TRNG Entropy Read Register 3"
|
|
in
|
|
else
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "ENT3,TRNG Entropy Read Register 3"
|
|
endif
|
|
if (((per.l(ad:0x400A5000))&0x10420)==0x420)
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "ENT4,TRNG Entropy Read Register 4"
|
|
in
|
|
else
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "ENT4,TRNG Entropy Read Register 4"
|
|
endif
|
|
if (((per.l(ad:0x400A5000))&0x10420)==0x420)
|
|
hgroup.long 0x54++0x03
|
|
hide.long 0x00 "ENT5,TRNG Entropy Read Register 5"
|
|
in
|
|
else
|
|
hgroup.long 0x54++0x03
|
|
hide.long 0x00 "ENT5,TRNG Entropy Read Register 5"
|
|
endif
|
|
if (((per.l(ad:0x400A5000))&0x10420)==0x420)
|
|
hgroup.long 0x58++0x03
|
|
hide.long 0x00 "ENT6,TRNG Entropy Read Register 6"
|
|
in
|
|
else
|
|
hgroup.long 0x58++0x03
|
|
hide.long 0x00 "ENT6,TRNG Entropy Read Register 6"
|
|
endif
|
|
if (((per.l(ad:0x400A5000))&0x10420)==0x420)
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "ENT7,TRNG Entropy Read Register 7"
|
|
in
|
|
else
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "ENT7,TRNG Entropy Read Register 7"
|
|
endif
|
|
if (((per.l(ad:0x400A5000))&0x10420)==0x420)
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "ENT8,TRNG Entropy Read Register 8"
|
|
in
|
|
else
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "ENT8,TRNG Entropy Read Register 8"
|
|
endif
|
|
if (((per.l(ad:0x400A5000))&0x10420)==0x420)
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "ENT9,TRNG Entropy Read Register 9"
|
|
in
|
|
else
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "ENT9,TRNG Entropy Read Register 9"
|
|
endif
|
|
if (((per.l(ad:0x400A5000))&0x10420)==0x420)
|
|
hgroup.long 0x68++0x03
|
|
hide.long 0x00 "ENT10,TRNG Entropy Read Register 10"
|
|
in
|
|
else
|
|
hgroup.long 0x68++0x03
|
|
hide.long 0x00 "ENT10,TRNG Entropy Read Register 10"
|
|
endif
|
|
if (((per.l(ad:0x400A5000))&0x10420)==0x420)
|
|
hgroup.long 0x6C++0x03
|
|
hide.long 0x00 "ENT11,TRNG Entropy Read Register 11"
|
|
in
|
|
else
|
|
hgroup.long 0x6C++0x03
|
|
hide.long 0x00 "ENT11,TRNG Entropy Read Register 11"
|
|
endif
|
|
if (((per.l(ad:0x400A5000))&0x10420)==0x420)
|
|
hgroup.long 0x70++0x03
|
|
hide.long 0x00 "ENT12,TRNG Entropy Read Register 12"
|
|
in
|
|
else
|
|
hgroup.long 0x70++0x03
|
|
hide.long 0x00 "ENT12,TRNG Entropy Read Register 12"
|
|
endif
|
|
if (((per.l(ad:0x400A5000))&0x10420)==0x420)
|
|
hgroup.long 0x74++0x03
|
|
hide.long 0x00 "ENT13,TRNG Entropy Read Register 13"
|
|
in
|
|
else
|
|
hgroup.long 0x74++0x03
|
|
hide.long 0x00 "ENT13,TRNG Entropy Read Register 13"
|
|
endif
|
|
if (((per.l(ad:0x400A5000))&0x10420)==0x420)
|
|
hgroup.long 0x78++0x03
|
|
hide.long 0x00 "ENT14,TRNG Entropy Read Register 14"
|
|
in
|
|
else
|
|
hgroup.long 0x78++0x03
|
|
hide.long 0x00 "ENT14,TRNG Entropy Read Register 14"
|
|
endif
|
|
if (((per.l(ad:0x400A5000))&0x10420)==0x420)
|
|
hgroup.long 0x7C++0x03
|
|
hide.long 0x00 "ENT15,TRNG Entropy Read Register 15"
|
|
in
|
|
else
|
|
hgroup.long 0x7C++0x03
|
|
hide.long 0x00 "ENT15,TRNG Entropy Read Register 15"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x400A5000))&0x10000)==0x0)
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "PKRCNT10,TRNG Statistical Check Poker Count 1 And 0 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PKR_1_CT ,Poker 1h count"
|
|
hexmask.long.word 0x00 0.--15. 1. " PKR_0_CT ,Poker 0h count"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "PKRCNT32,TRNG Statistical Check Poker Count 3 And 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PKR_3_CT ,Poker 3h count"
|
|
hexmask.long.word 0x00 0.--15. 1. " PKR_2_CT ,Poker 2h count"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "PKRCNT54,TRNG Statistical Check Poker Count 5 And 4 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PKR_5_CT ,Poker 5h count"
|
|
hexmask.long.word 0x00 0.--15. 1. " PKR_4_CT ,Poker 4h count"
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "PKRCNT76,TRNG Statistical Check Poker Count 7 And 6 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PKR_7_CT ,Poker 7h count"
|
|
hexmask.long.word 0x00 0.--15. 1. " PKR_6_CT ,Poker 6h count"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "PKRCNT98,TRNG Statistical Check Poker Count 9 And 8 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PKR_9_CT ,Poker 9h count"
|
|
hexmask.long.word 0x00 0.--15. 1. " PKR_8_CT ,Poker 8h count"
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "PKRCNTBA,TRNG Statistical Check Poker Count B And A Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PKR_B_CT ,Poker Bh count"
|
|
hexmask.long.word 0x00 0.--15. 1. " PKR_A_CT ,Poker Ah count"
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "PKRCNTDC,TRNG Statistical Check Poker Count D And C Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PKR_D_CT ,Poker Dh count"
|
|
hexmask.long.word 0x00 0.--15. 1. " PKR_C_CT ,Poker Ch count"
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "PKRCNTFE,TRNG Statistical Check Poker Count F And E Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PKR_F_CT ,Poker Fh count"
|
|
hexmask.long.word 0x00 0.--15. 1. " PKR_E_CT ,Poker Eh count"
|
|
else
|
|
hgroup.long 0x80++0x03
|
|
hide.long 0x00 "PKRCNT10,TRNG Statistical Check Poker Count 1 And 0 Register"
|
|
hgroup.long 0x84++0x03
|
|
hide.long 0x00 "PKRCNT32,TRNG Statistical Check Poker Count 3 And 2 Register"
|
|
hgroup.long 0x88++0x03
|
|
hide.long 0x00 "PKRCNT54,TRNG Statistical Check Poker Count 5 And 4 Register"
|
|
hgroup.long 0x8C++0x03
|
|
hide.long 0x00 "PKRCNT76,TRNG Statistical Check Poker Count 7 And 6 Register"
|
|
hgroup.long 0x90++0x03
|
|
hide.long 0x00 "PKRCNT98,TRNG Statistical Check Poker Count 9 And 8 Register"
|
|
hgroup.long 0x94++0x03
|
|
hide.long 0x00 "PKRCNTBA,TRNG Statistical Check Poker Count B And A Register"
|
|
hgroup.long 0x98++0x03
|
|
hide.long 0x00 "PKRCNTDC,TRNG Statistical Check Poker Count D And C Register"
|
|
hgroup.long 0x9C++0x03
|
|
hide.long 0x00 "PKRCNTFE,TRNG Statistical Check Poker Count F And E Register"
|
|
endif
|
|
sif (cpuis("MK8?FN256V*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKV5*"))
|
|
group.long 0xB0++0x0F
|
|
line.long 0x00 "SEC_CFG,TRNG Security Configuration Register"
|
|
bitfld.long 0x00 1. " NO_PRGM ,TRNG registers cannot be programmed" "No,Yes"
|
|
line.long 0x04 "INT_CTRL,TRNG Interrupt Control Register"
|
|
bitfld.long 0x04 2. " FRQ_CT_FAIL ,Frequency count fail interrupt control status" "Cleared,Active"
|
|
bitfld.long 0x04 1. " ENT_VAL ,Entropy valid interrupt control status" "Cleared,Active"
|
|
bitfld.long 0x04 0. " HW_ERR ,HW error interrupt control status" "Cleared,Active"
|
|
line.long 0x08 "INT_MASK,TRNG Mask Register"
|
|
bitfld.long 0x08 2. " FRQ_CT_FAIL ,Frequency count fail interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x08 1. " ENT_VAL ,Entropy valid interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " HW_ERR ,HW error interrupt mask" "Masked,Not masked"
|
|
line.long 0x0C "INT_STATUS,TRNG Interrupt Status Register"
|
|
bitfld.long 0x0C 2. " FRQ_CT_FAIL ,Frequency count fail interrupt status" "Not failed,Failed"
|
|
rbitfld.long 0x0C 1. " ENT_VAL ,Entropy valid interrupt status" "Invalid,Valid"
|
|
rbitfld.long 0x0C 0. " HW_ERR ,HW error interrupt status" "No error,Error"
|
|
else
|
|
group.long 0xA0++0x0F
|
|
line.long 0x00 "SEC_CFG,TRNG Security Configuration Register"
|
|
bitfld.long 0x00 1. " NO_PRGM ,TRNG registers cannot be programmed" "No,Yes"
|
|
line.long 0x04 "INT_CTRL,TRNG Interrupt Control Register"
|
|
bitfld.long 0x04 2. " FRQ_CT_FAIL ,Frequency count fail interrupt control status" "Cleared,Active"
|
|
bitfld.long 0x04 1. " ENT_VAL ,Entropy valid interrupt control status" "Cleared,Active"
|
|
bitfld.long 0x04 0. " HW_ERR ,HW error interrupt control status" "Cleared,Active"
|
|
line.long 0x08 "INT_MASK,TRNG Mask Register"
|
|
bitfld.long 0x08 2. " FRQ_CT_FAIL ,Frequency count fail interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x08 1. " ENT_VAL ,Entropy valid interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " HW_ERR ,HW error interrupt mask" "Masked,Not masked"
|
|
line.long 0x0C "INT_STATUS,TRNG Interrupt Status Register"
|
|
sif (cpuis("K32W0?2S1M*")||cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4"))
|
|
rbitfld.long 0x0C 2. " FRQ_CT_FAIL ,Frequency count fail interrupt status" "Not failed,Failed"
|
|
else
|
|
bitfld.long 0x0C 2. " FRQ_CT_FAIL ,Frequency count fail interrupt status" "Not failed,Failed"
|
|
endif
|
|
newline
|
|
rbitfld.long 0x0C 1. " ENT_VAL ,Entropy valid interrupt status" "Invalid,Valid"
|
|
rbitfld.long 0x0C 0. " HW_ERR ,HW error interrupt status" "No error,Error"
|
|
endif
|
|
rgroup.long 0xF0++0x07
|
|
line.long 0x00 "VID1,Version ID (MS) Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TRNG_IP_ID ,Shows IP ID"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TRNG_MAJ_REV ,Shows IP's major revision of the TRNG"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TRNG_MIN_REV ,Shows IP's minor revision of the TRNG"
|
|
line.long 0x04 "VID2,Version ID (LS) Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " TRNG_ERA ,Shows compile options for the TRNG"
|
|
hexmask.long.byte 0x04 16.--23. 1. " TRNG_INTG_OPT ,Shows integration options for the TRNG"
|
|
hexmask.long.byte 0x04 8.--15. 1. " TRNG_ECO_REV ,Shows IP's ECO revision of the TRNG"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. " TRNG_CONFIG_OPT ,Shows IP's Configuration options for the TRNG"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "TSTMR (Time Stamp Timer Module)"
|
|
base ad:0x400750F0
|
|
width 6.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "LOW,Time Stamp Timer Register Low"
|
|
line.long 0x04 "HIGH,Time Stamp Timer Register High"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. "VALUE ,Time stamp timer high"
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("MKL82Z*")
|
|
tree "WDOG (Watchdog timer)"
|
|
base ad:0x40052000
|
|
width 9.
|
|
group.word 0x00++0x17
|
|
line.word 0x00 "STCTRLH,Watchdog Status And Control Register High"
|
|
bitfld.word 0x00 14. " DISTESTWDOG ,WDOG functional test mode disable" "No,Yes"
|
|
bitfld.word 0x00 12.--13. " BYTESEL ,Select the byte to be tested" "Byte 0,Byte 1,Byte 2,Byte 3"
|
|
bitfld.word 0x00 11. " TESTSEL ,Selects the test to be run on the watchdog timer" "Quick test,Byte test"
|
|
newline
|
|
bitfld.word 0x00 10. " TESTWDOG ,Functional test mode enable" "Disabled,Enabled"
|
|
sif cpuis("MK20DN512*AB10R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK40D*Z*10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK60DX256ZVMC10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10")||cpuis("MK20DX256ZVLQ10R")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("KK60DN512ZCAB10R")
|
|
newline
|
|
bitfld.word 0x00 8. " STNDBYEN ,Enables WDOG in standby mode" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.word 0x00 7. " WAIT_EN ,Enables WDOG in wait mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " STOPEN ,Enables WDOG in stop mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " DBGEN ,Enables WDOG in debug mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 4. " ALLOWUPDATE ,Enables updates to watchdog write once registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " WINEN ,Enable windowing mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " IRQRSTEN ,Enable the debug breadcrumbs feature" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " CLKSRC ,Selects clock source for the WDOG timer and other internal timing operations" "LPO Osc,Alternate"
|
|
bitfld.word 0x00 0. " WDOGEN ,Enables the WDOG operation" "Disabled,Enabled"
|
|
line.word 0x02 "STCTRLL,Watchdog Status And Control Register Low"
|
|
eventfld.word 0x02 15. " INTFLG ,Interrupt flag" "No interrupt,Interrupt"
|
|
line.word 0x04 "TOVALH,Watchdog Time-out Value Register High"
|
|
line.word 0x06 "TOVALL,Watchdog Time-out Value Register Low"
|
|
line.word 0x08 "WINH,Watchdog Window Register High"
|
|
line.word 0x0A "WINL,Watchdog Window Register Low"
|
|
line.word 0x0C "REFRESH,Watchdog Refresh Register"
|
|
line.word 0x0E "UNLOCK,Watchdog Unlock Register"
|
|
line.word 0x10 "TMROUTH,Watchdog Timer Output Register High"
|
|
line.word 0x12 "TMROUTL,Watchdog Timer Output Register Low"
|
|
line.word 0x14 "RSTCNT,Watchdog Reset Count Register"
|
|
line.word 0x16 "PRESC,Watchdog Prescaler Register"
|
|
bitfld.word 0x16 8.--10. " PRESCVAL ,3-bit prescaler for the watchdog clock source" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "WDOG (Watchdog timer)"
|
|
base ad:0x40076000
|
|
width 7.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "CS,Watchdog Control and Status Register"
|
|
bitfld.long 0x00 15. " WIN ,Watchdog window" "Disabled,Enabled"
|
|
eventfld.long 0x00 14. " FLG ,Watchdog interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CMD32EN ,Enables or disables WDOG support for 32-bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PRES ,Watchdog prescaler" "Disabled,Enabled"
|
|
sif !cpuis("MKL28Z*")
|
|
rbitfld.long 0x00 11. " ULK ,Unlock status" "Locked,Unlocked"
|
|
rbitfld.long 0x00 10. " RCS ,Reconfiguration success" "In progress,Succeeded"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CLK ,Watchdog clock" "Bus clock,LPO clock,INTCLK,ERCLK"
|
|
bitfld.long 0x00 7. " EN ,Watchdog enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INT ,Watchdog interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " UPDATE ,Allow updates" "Not allowed,Allowed"
|
|
bitfld.long 0x00 3.--4. " TST ,Watchdog test" "Disabled,User mode,Test mode/low byte,Test mode/high byte"
|
|
bitfld.long 0x00 2. " DBG ,Debug enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WAIT ,Wait enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " STOP ,Stop enable" "Disabled,Enabled"
|
|
line.long 0x04 "CNT,Watchdog Counter Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " CNTHIGH ,High byte of the watchdog counter"
|
|
hexmask.long.byte 0x04 0.--7. 1. " CNTLOW ,Low byte of the watchdog counter"
|
|
line.long 0x08 "TOVAL,Watchdog Timeout Value Register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " TOVALHIGH ,High byte of the timeout value"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TOVALLOW ,Low byte of the timeout value"
|
|
line.long 0x0C "WIN,Watchdog Window Register"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " WINHIGH ,High byte of watchdog window"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " WINLOW ,Low byte of watchdog window"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
endif
|
|
textline ""
|