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Gen4_R-Car_Trace32/2_Trunk/pergd32e5xx.per
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

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; --------------------------------------------------------------------------------
; @Title: GD32E5XX On-Chip Peripherals
; @Props: Released
; @Author: KWI, ADR
; @Changelog: 2021-04-22 KWI
; 2021-01-26 ADR
; @Manufacturer: GigaDevice - GigaDevice Semiconductor Inc.
; @Doc: SVD generated based on GD32E50x_CL.svd, GD32E50x_HD.svd
; @Core: Cortex-M33F
; @Chip: GD32E503CC, GD32E503CE, GD32E503RC, GD32E503RE, GD32E503VC, GD32E503VE,
; GD32E503ZC, GD32E503ZE, GD32E505RB, GD32E505RC, GD32E505RE, GD32E505VC,
; GD32E505VE, GD32E505ZC, GD32E505ZE, GD32E507RC, GD32E507RE, GD32E507VC,
; GD32E507VE, GD32E507ZC
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: pergd32e5xx.per 17736 2024-04-08 09:26:07Z kwisniewski $
tree.close "Core Registers (Cortex-M33F)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
group.long 0x08++0x03
line.long 0x00 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 29. " EXTEXCLALL ,Allows external exclusive operations to be used in a configuration with no MPU" "No,Yes"
bitfld.long 0x00 12. " DISITMATBFLUSH ,Disables ITM and DWT ATB flush" "No,Yes"
bitfld.long 0x00 10. " FPEXCODIS ,Disables FPU exception outputs" "No,Yes"
textline " "
bitfld.long 0x00 9. " DISOOFP ,Disables floating-point" "No,Yes"
bitfld.long 0x00 2. " DISFOLD ,Disables dual-issue functionality" "No,Yes"
bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle" "No,Yes"
group.long 0x0C++0x0F
line.long 0x00 "CPPWR,Coprocessor Power Control Register"
bitfld.long 0x00 21. " SUS10 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 20. " SU10 ,This bit indicates and allows modification of whether the state associated with the floating point unit is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 15. " SUS7 ,State unknown Secure only" "Both states,Secure only"
textline " "
bitfld.long 0x00 14. " SU7 ,This bit indicates and allows modification of whether the state associated with the coprocessor 7 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 13. " SUS6 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 12. " SU6 ,This bit indicates and allows modification of whether the state associated with the coprocessor 6 is permitted to become UNKNOWN" "Not permitted,Permitted"
textline " "
bitfld.long 0x00 11. " SUS5 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 10. " SU5 ,This bit indicates and allows modification of whether the state associated with the coprocessor 5 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 9. " SUS4 ,State unknown Secure only" "Both states,Secure only"
textline " "
bitfld.long 0x00 8. " SU4 ,This bit indicates and allows modification of whether the state associated with the coprocessor 4 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 7. " SUS3 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 6. " SU3 ,This bit indicates and allows modification of whether the state associated with the coprocessor 3 is permitted to become UNKNOWN" "Not permitted,Permitted"
textline " "
bitfld.long 0x00 5. " SUS2 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 4. " SU2 ,This bit indicates and allows modification of whether the state associated with the coprocessor 2 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 3. " SUS1 ,State unknown Secure only" "Both states,Secure only"
textline " "
bitfld.long 0x00 2. " SU1 ,This bit indicates and allows modification of whether the state associated with the coprocessor 1 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 1. " SUS0 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 0. " SU0 ,This bit indicates and allows modification of whether the state associated with the coprocessor 0 is permitted to become UNKNOWN" "Not permitted,Permitted"
line.long 0x04 "SYST_CSR,SysTick Control and Status Register"
rbitfld.long 0x04 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
bitfld.long 0x04 2. " CLKSOURCE ,SysTick clock source" "External,Core"
bitfld.long 0x04 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
textline " "
bitfld.long 0x04 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
line.long 0x08 "SYST_RVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
line.long 0x0C "SYST_CVR,SysTick Current Value Register"
hexmask.long.tbyte 0x0C 0.--23. 1. " CURRENT ,Current counter value"
rgroup.long 0x1C++0x03
line.long 0x00 "SYST_CALIB,SysTick Calibration value Register"
bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
rgroup.long 0xD00++0x03
line.long 0x00 "CPUID,CPUID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Indicates implementer"
bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8-M w/ Main extension"
textline " "
hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "Reserved,Reserved,Patch 2,?..."
group.long 0xD04++0x23
line.long 0x00 "ICSR,Interrupt Control and State Register"
setclrfld.long 0x00 31. 0x00 31. 0x00 30. " PENDNMISET , On writes allows the NMI exception to be set as pending. On reads indicates whether the NMI exception is pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET , On writes allows the PendSV exception for the selected Security state to be set as pending. On reads indicates whether the PendSV for the selected Security state exception is pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
textline " "
bitfld.long 0x00 24. " STTNS ,Controls whether in a single SysTick implementation the SysTick is Secure or Non-secure" "Secure,Non-secure"
rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending"
textline " "
hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt"
rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
line.long 0x04 "VTOR,Vector Table Offset Register"
hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address"
line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key"
rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian"
bitfld.long 0x08 14. " PRIS ,Prioritize Secure exceptions" "Disabled,Enabled"
textline " "
bitfld.long 0x08 13. " BFHFNMINS ,BusFault BusFault HardFault and NMI Non-secure enable" "Disabled,Enabled"
bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
bitfld.long 0x08 3. " SYSRESETREQS ,System reset request Secure only" "Both states,Secure only"
textline " "
bitfld.long 0x08 2. " SYSRESETREQ ,System reset request" "Not requested,Requested"
bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
line.long 0x0C "SCR,System Control Register"
bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x0C 3. " SLEEPDEEPS ,Controls whether the SLEEPDEEP bit is only accessible from the secure state" "Both states,Secure only"
bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline " "
bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
line.long 0x10 "CCR,Configuration and Control Register"
bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
textline " "
bitfld.long 0x10 10. " STKOFHFNMIGN ,Controls the effect of a stack limit violation while executing at a requested priority less than 0" "Not ignored,Ignored"
bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise busfaults on handlers running at a requested priority less than 0" "Not ignored,Ignored"
bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled"
textline " "
bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
line.long 0x14 "SHPR1,System Handler Priority Register 1"
hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of system handler 7, SecureFault"
hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6, UsageFault"
hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5, BusFault"
textline " "
hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4, MemManage"
line.long 0x18 "SHPR2,System Handler Priority Register 2"
hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11, SVCall"
line.long 0x1C "SHPR3,System Handler Priority Register 3"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of system handler 15, SysTick"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of system handler 14, PendSV"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of system handler 12, DebugMonitor"
line.long 0x20 "SHCSR,System Handler Control and State Register"
bitfld.long 0x20 21. " HARDFAULTPENDED ,HardFault exception status" "Not pending,Pending"
bitfld.long 0x20 20. " SECUREFAULTPENDED ,SecureFault exception status" "Not pending,Pending"
bitfld.long 0x20 19. " SECUREFAULTENA ,SecureFault exception enable" "Disabled,Enabled"
textline " "
bitfld.long 0x20 18. " USGFAULTENA ,UsageFault exception enable" "Disabled,Enabled"
bitfld.long 0x20 17. " BUSFAULTENA ,BusFault exception enable" "Disabled,Enabled"
bitfld.long 0x20 16. " MEMFAULTENA ,MemManage exception enable" "Disabled,Enabled"
textline " "
bitfld.long 0x20 15. " SVCALLPENDED ,SVCall exception status" "Not pending,Pending"
bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault exception status" "Not pending,Pending"
bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage exception status" "Not pending,Pending"
textline " "
bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault exception status" "Not pending,Pending"
bitfld.long 0x20 11. " SYSTICKACT ,SysTick exception status" "Not active,Active"
bitfld.long 0x20 10. " PENDSVACT ,PendSV exception status" "Not active,Active"
textline " "
bitfld.long 0x20 8. " MONITORACT ,Monitor exception status" "Not active,Active"
bitfld.long 0x20 7. " SVCALLACT ,SVCall exception status" "Not active,Active"
bitfld.long 0x20 5. " NMIACT ,NMI exception status" "Not active,Active"
textline " "
bitfld.long 0x20 4. " SECUREFAULTACT ,SecureFault exception status" "Not active,Active"
bitfld.long 0x20 3. " USGFAULTACT ,UsageFault exception status" "Not active,Active"
bitfld.long 0x20 2. " HARDFAULTACT ,HardFault exception status for the selected Security state" "Not active,Active"
textline " "
bitfld.long 0x20 1. " BUSFAULTACT ,BusFault exception status" "Not active,Active"
bitfld.long 0x20 0. " MEMFAULTACT ,MemManage exception status" "Not active,Active"
group.byte 0xD28++0x1
line.byte 0x00 "MMFSR,MemManage Status Register"
bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x00 4. " MSTKERR ,Stacking Access Violations" "Not occurred,Occurred"
textline " "
bitfld.byte 0x00 3. " MUNSTKERR ,Unstacking Access Violations" "Not occurred,Occurred"
bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
line.byte 0x01 "BFSR,Bus Fault Status Register"
bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x01 4. " STKERR ,Derived bus fault (exception entry)" "Not occurred,Occurred"
textline " "
bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault (exception return)" "Not occurred,Occurred"
bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
textline " "
bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
group.word 0xD2A++0x1
line.word 0x00 "UFSR,Usage Fault Status Register"
eventfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
eventfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
eventfld.word 0x00 4. " STKOF ,Stack overflow error" "No error,Error"
textline " "
eventfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
eventfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
eventfld.word 0x00 1. " INVSTATE , Invalid Combination of EPSR and Instruction" "No error,Error"
textline " "
eventfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
group.long 0xD2C++0x03
line.long 0x00 "HFSR,HardFault Status Register"
bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred"
bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
group.long 0xD34++0x0B
line.long 0x00 "MMFAR,MemManage Fault Address Register"
line.long 0x04 "BFAR,BusFault Address Register"
line.long 0x08 "AFSR,Auxiliary Fault Status Register"
group.long 0xD88++0x03
line.long 0x00 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Denied,Privileged,,Full"
bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Denied,Privileged,,Full"
textline " "
bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Denied,Privileged,,Full"
bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Denied,Privileged,,Full"
bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Denied,Privileged,,Full"
textline " "
bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Denied,Privileged,,Full"
bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Denied,Privileged,,Full"
bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Denied,Privileged,,Full"
textline " "
bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Denied,Privileged,,Full"
if PER.ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD48)
group.long 0xD8C++0x03
line.long 0x00 "NSACR,Non-Secure Access Control Register"
bitfld.long 0x00 11. " CP11 ,Enables Non-secure access to coprocessor CP11" "Disabled,Enabled"
bitfld.long 0x00 10. " CP10 ,Enables Non-secure access to coprocessor CP10" "Disabled,Enabled"
bitfld.long 0x00 7. " CP7 ,Enables Non-secure access to coprocessor CP7" "Disabled,Enabled"
textline " "
bitfld.long 0x00 6. " CP6 ,Enables Non-secure access to coprocessor CP6" "Disabled,Enabled"
bitfld.long 0x00 5. " CP5 ,Enables Non-secure access to coprocessor CP5" "Disabled,Enabled"
bitfld.long 0x00 4. " CP4 ,Enables Non-secure access to coprocessor CP4" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " CP3 ,Enables Non-secure access to coprocessor CP3" "Disabled,Enabled"
bitfld.long 0x00 2. " CP2 ,Enables Non-secure access to coprocessor CP2" "Disabled,Enabled"
bitfld.long 0x00 1. " CP1 ,Enables Non-secure access to coprocessor CP1" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " CP0 ,Enables Non-secure access to coprocessor CP0" "Disabled,Enabled"
else
hgroup.long 0xD8C++0x03
hide.long 0x00 "NSACR,Non-Secure Access Control Register (not accessible)"
endif
wgroup.long 0xF00++0x03
line.long 0x00 "STIR,Software Triggered Interrupt Register"
hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be pended"
tree "Memory System"
width 10.
rgroup.long 0xD78++0x03
line.long 0x00 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 30.--31. " ICB ,Inner cache boundary" "Not disclosed,L1 cache highest,L2 cache highest,L3 cache highest"
bitfld.long 0x00 27.--29. " LOU ,LOUU" "Level 1,Level 2,?..."
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,?..."
textline " "
bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,Instr. only,Data only,Data and Instr.,Unified cache,?..."
bitfld.long 0x00 15.--17. " CL6 ,Cache type field level 6" "No cache,?..."
bitfld.long 0x00 12.--14. " CL5 ,Cache type field level 5" "No cache,?..."
textline " "
bitfld.long 0x00 9.--11. " CL4 ,Cache type field level 4" "No cache,?..."
bitfld.long 0x00 6.--8. " CL3 ,Cache type field level 3" "No cache,?..."
bitfld.long 0x00 3.--5. " CL2 ,Cache type field level 2" "No cache,?..."
textline " "
bitfld.long 0x00 0.--2. " CL1 ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..."
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD7C)&0xE0000000)==0x80000000)
rgroup.long 0xD7C++0x03
line.long 0x00 "CTR,Cache Type Register"
bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..."
bitfld.long 0x00 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,?..."
bitfld.long 0x00 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,?..."
textline " "
bitfld.long 0x00 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
rgroup.long 0xD7C++0x03
line.long 0x00 "CTR,Cache Type Register"
bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..."
endif
rgroup.long 0xD80++0x03
line.long 0x00 "CCSIDR,Cache Size ID Register"
bitfld.long 0x00 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported"
bitfld.long 0x00 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported"
bitfld.long 0x00 29. " RA ,Indicates support available for read allocation" "Not supported,Supported"
textline " "
bitfld.long 0x00 28. " WA ,Indicates support available for write allocation" "Not supported,Supported"
hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1"
hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
textline " "
bitfld.long 0x00 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512"
group.long 0xD84++0x03
line.long 0x00 "CSSELR,Cache Size Selection Register"
bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,?..."
bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data/Unified,Instruction"
wgroup.long 0xF50++0x03
line.long 0x00 "ICIALLU,I-Cache Invalidate All to PoU"
wgroup.long 0xF58++0x23
line.long 0x00 "ICIMVAU,I-Cache Invalidate by MVA to PoU"
line.long 0x04 "DCIMVAC,D-Cache Invalidate by MVA to PoC"
line.long 0x08 "DCISW,D-Cache Invalidate by Set-Way"
hexmask.long 0x08 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
bitfld.long 0x08 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
line.long 0x0C "DCCMVAU,D-Cache Clean by MVA to PoU"
line.long 0x10 "DCCMVAC,D-Cache Clean by MVA to PoC"
line.long 0x14 "DCCSW,D-Cache Clean by Set-Way"
hexmask.long 0x14 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
bitfld.long 0x14 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
line.long 0x18 "DCCIMVAC,D-Cache Clean and Invalidate by MVA to PoC"
line.long 0x1C "DCCISW,D-Cache Clean and Invalidate by Set-Way"
hexmask.long 0x1C 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
bitfld.long 0x1C 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
line.long 0x20 "BPIALL,Branch Predictor Invalidate All"
tree.end
tree "Feature Registers"
width 10.
rgroup.long 0xD40++0x0B
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 4.--7. " STATE1 ,T32 instruction set support" ",,,Supported,?..."
bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
bitfld.long 0x04 4.--7. " SECURITY ,Security support" "Not implemented,Implemented,?..."
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x08 20.--23. " MPROFDBG ,M-profile debug. Indicates the supported M-profile debug architecture" "Not supported,ARMv8-M Debug architecture,?..."
rgroup.long 0xD4C++0x03
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long 0xD50++0x03
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,Supported,?..."
bitfld.long 0x00 16.--19. " TCM ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "1 level,2 levels,?..."
textline " "
bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,HW coherency,,,,,,,,,,,,,,Ignored"
bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,,PMSAv8,?..."
rgroup.long 0xD54++0x03
line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
rgroup.long 0xD58++0x03
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
rgroup.long 0xD5C++0x03
line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3"
bitfld.long 0x00 8.--11. " BPMAINT ,Indicates the supported branch predictor maintenance" "Not supported,Supported,?..."
bitfld.long 0x00 4.--7. " CMAINTSW ,Indicates the supported cache maintenance operations by set/way" "Not supported,Supported,?..."
bitfld.long 0x00 0.--3. " CMAINTVA ,Indicates the supported cache maintenance operations by virtual-address" "Not supported,Supported,?..."
rgroup.long 0xD60++0x03
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
rgroup.long 0xD64++0x03
line.long 0x00 "ID_ISAR1,Instruction Set Attributes Register 1"
bitfld.long 0x00 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
bitfld.long 0x00 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
bitfld.long 0x00 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
textline " "
bitfld.long 0x00 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Basic,Extended,?..."
rgroup.long 0xD68++0x03
line.long 0x00 "ID_ISAR2,Instruction Set Attributes Register 2"
bitfld.long 0x00 28.--31. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
bitfld.long 0x00 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
bitfld.long 0x00 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,SMULL/SMLAL,,SMULL/SMLAL/DSP,?..."
textline " "
bitfld.long 0x00 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MUL,MUL/MLA/MLS,?..."
bitfld.long 0x00 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
bitfld.long 0x00 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
textline " "
bitfld.long 0x00 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,,Load-acquire/Store-release/Exclusive,?..."
rgroup.long 0xD6C++0x03
line.long 0x00 "ID_ISAR3,Instruction Set Attributes Register 3"
bitfld.long 0x00 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
bitfld.long 0x00 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
bitfld.long 0x00 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
textline " "
bitfld.long 0x00 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,?..."
bitfld.long 0x00 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
bitfld.long 0x00 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Extended,?..."
textline " "
bitfld.long 0x00 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB/Q-bit,?..."
rgroup.long 0xD70++0x03
line.long 0x00 "ID_ISAR4,Instruction Set Attributes Register 4"
bitfld.long 0x00 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,CPS/MRS/MSR,?..."
bitfld.long 0x00 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" ",,,Supported,?..."
bitfld.long 0x00 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,,,DMB/DSB/ISB,?..."
textline " "
bitfld.long 0x00 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
bitfld.long 0x00 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,,,Load/store,?..."
bitfld.long 0x00 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,?..."
tree.end
tree "CoreSight Identification Registers"
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 11.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xFBC))&0x100000)==0x100000)
rgroup.long 0xFBC++0x03
line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register"
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
else
rgroup.long 0xFBC++0x03
line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
endif
rgroup.long 0xFE0++0x0F
line.long 0x00 "DPIDR0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "DPIDR1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "DPIDR2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "DPIDR3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "DCIDR0,Component ID0 (Preamble)"
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
line.long 0x04 "DCIDR1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
line.long 0x08 "DCIDR2,Component ID2"
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
line.long 0x0c "DCIDR3,Component ID3"
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
tree.end
width 0xB
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit (MPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,?..."
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
group.long 0xD9C++0x03 "Region 8"
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
group.long 0xD9C++0x03 "Region 9"
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
group.long 0xD9C++0x03 "Region 10"
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
group.long 0xD9C++0x03 "Region 11"
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
group.long 0xD9C++0x03 "Region 12"
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
group.long 0xD9C++0x03 "Region 13"
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
group.long 0xD9C++0x03 "Region 14"
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
group.long 0xD9C++0x03 "Region 15"
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
endif
tree.end
newline
group.long 0xDC0++0x07
line.long 0x00 "MPU_MAIR0,MPU Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. " ATTR3H ,Attribute 3 High. Outer memory attributes for MPU regions with an AttrIndex of 3" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 24.--27. " ATTR3L ,Attribute 3 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 3 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x00 20.--23. " ATTR2H ,Attribute 2 High. Outer memory attributes for MPU regions with an AttrIndex of 2" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 16.--19. " ATTR2L ,Attribute 2 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 2 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x00 12.--15. " ATTR1H ,Attribute 1 High. Outer memory attributes for MPU regions with an AttrIndex of 1" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 8.--11. " ATTR1L ,Attribute 1 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 1 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x00 4.--7. " ATTR0H ,Attribute 0 High. Outer memory attributes for MPU regions with an AttrIndex of 0" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 0.--3. " ATTR0L ,Attribute 0 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 0 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
line.long 0x04 "MPU_MAIR1,MPU Memory Attribute Indirection Register 1"
bitfld.long 0x04 28.--31. " ATTR7H ,Attribute 7 High. Outer memory attributes for MPU regions with an AttrIndex of 7" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 24.--27. " ATTR7L ,Attribute 7 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 7 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x04 20.--23. " ATTR6H ,Attribute 6 High. Outer memory attributes for MPU regions with an AttrIndex of 6" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 16.--19. " ATTR6L ,Attribute 6 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 6 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x04 12.--15. " ATTR5H ,Attribute 5 High. Outer memory attributes for MPU regions with an AttrIndex of 5" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 8.--11. " ATTR5L ,Attribute 5 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 5 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x04 4.--7. " ATTR4H ,Attribute 4 High. Outer memory attributes for MPU regions with an AttrIndex of 4" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 0.--3. " ATTR4L ,Attribute 4 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 4 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Security Attribution Unit (SAU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
group.long 0xDD0++0x03
line.long 0x00 "SAU_CTRL,SAU Control Register"
bitfld.long 0x00 1. " ALLNS ,When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure" "Secure,Non-Secure"
bitfld.long 0x00 0. " ENABLE ,Enables the SAU" "Disabled,Enabled"
rgroup.long 0xDD4++0x03
line.long 0x00 "SAU_TYPE,SAU Type Register"
bitfld.long 0x00 0.--7. " SREGION ,The number of implemented SAU regions" "0,1,2,3,4,5,6,7,8,?..."
group.long 0xDD8++0x03
line.long 0x00 "SAU_RNR,SAU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " SAU_RNR ,Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR"
tree.close "SAU regions"
if PER.ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD0)
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x0
group.long 0xDDC++0x03 "Region 0"
saveout 0xDD8 %l 0x0
line.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x0
line.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 0 (not implemented)"
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x1
group.long 0xDDC++0x03 "Region 1"
saveout 0xDD8 %l 0x1
line.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x1
line.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 1 (not implemented)"
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x2
group.long 0xDDC++0x03 "Region 2"
saveout 0xDD8 %l 0x2
line.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x2
line.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 2 (not implemented)"
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x3
group.long 0xDDC++0x03 "Region 3"
saveout 0xDD8 %l 0x3
line.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x3
line.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 3 (not implemented)"
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x4
group.long 0xDDC++0x03 "Region 4"
saveout 0xDD8 %l 0x4
line.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x4
line.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 4 (not implemented)"
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x5
group.long 0xDDC++0x03 "Region 5"
saveout 0xDD8 %l 0x5
line.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x5
line.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 5 (not implemented)"
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x6
group.long 0xDDC++0x03 "Region 6"
saveout 0xDD8 %l 0x6
line.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x6
line.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 6 (not implemented)"
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x7
group.long 0xDDC++0x03 "Region 7"
saveout 0xDD8 %l 0x7
line.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x7
line.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 7 (not implemented)"
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
endif
else
hgroup.long 0xDDC++0x03 "Region 0 (not accessible)"
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
hgroup.long 0xDDC++0x03 "Region 1 (not accessible)"
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
hgroup.long 0xDDC++0x03 "Region 2 (not accessible)"
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
hgroup.long 0xDDC++0x03 "Region 3 (not accessible)"
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
hgroup.long 0xDDC++0x03 "Region 4 (not accessible)"
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
hgroup.long 0xDDC++0x03 "Region 5 (not accessible)"
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
hgroup.long 0xDDC++0x03 "Region 6 (not accessible)"
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
hgroup.long 0xDDC++0x03 "Region 7 (not accessible)"
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
endif
tree.end
group.long 0xDE4++0x03
line.long 0x00 "SFSR,Secure Fault Status Register"
bitfld.long 0x00 7. " LSERR ,Lazy state error flag" "Not occurred,Occurred"
bitfld.long 0x00 6. " SFARVALID ,Secure fault address valid" "Not valid,Valid"
bitfld.long 0x00 5. " LSPERR ,Lazy state preservation error flag" "Not occurred,Occurred"
textline " "
bitfld.long 0x00 4. " INVTRAN ,Invalid transition flag" "Not occurred,Occurred"
bitfld.long 0x00 3. " AUVIOL ,Attribution unit violation flag" "Not occurred,Occurred"
bitfld.long 0x00 2. " INVER ,Invalid exception return flag" "Not occurred,Occurred"
textline " "
bitfld.long 0x00 1. " INVIS ,Invalid integrity signature flag" "Not occurred,Occurred"
bitfld.long 0x00 0. " INVEP ,Invalid entry point" "Not occurred,Occurred"
group.long 0xDE8++0x03
line.long 0x00 "SFAR,Secure Fault Address Register"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 6.
group.long 0x04++0x03
line.long 0x00 "ICTR,Interrupt Controller Type Register"
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,0-64,0-96,0-128,0-160,0-192,0-224,0-255,0-287,0-319,0-351,0-383,0-415,0-447,0-479,0-511"
width 24.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x104++0x03
line.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x104++0x03
hide.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x108++0x03
line.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x108++0x03
hide.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x10C++0x03
line.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x10C++0x03
hide.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x110++0x03
line.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x110++0x03
hide.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x114++0x03
line.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x114++0x03
hide.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x118++0x03
line.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x118++0x03
hide.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x11C++0x03
line.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA255 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA254 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA253 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA252 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA251 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA250 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA249 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA248 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA247 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA246 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA245 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA244 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA243 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA242 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA241 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA240 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x11C++0x03
hide.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x120++0x03
line.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA287 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA286 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA285 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA284 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA283 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA282 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA281 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA280 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA279 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA278 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA277 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA276 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA275 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA274 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA273 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA272 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA271 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA270 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA269 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA268 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA267 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA266 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA265 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA264 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA263 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA262 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA261 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA260 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA259 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA258 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA257 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA256 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x120++0x03
hide.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x124++0x03
line.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA319 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA318 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA317 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA316 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA315 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA314 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA313 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA312 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA311 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA310 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA309 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA308 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA307 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA306 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA305 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA304 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA303 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA302 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA301 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA300 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA299 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA298 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA297 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA296 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA295 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA294 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA293 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA292 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA291 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA290 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA289 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA288 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x124++0x03
hide.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x128++0x03
line.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA351 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA350 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA349 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA348 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA347 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA346 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA345 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA344 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA343 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA342 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA341 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA340 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA339 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA338 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA337 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA336 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA335 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA334 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA333 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA332 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA331 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA330 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA329 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA328 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA327 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA326 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA325 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA324 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA323 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA322 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA321 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA320 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x128++0x03
hide.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x12C++0x03
line.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA383 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA382 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA381 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA380 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA379 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA378 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA377 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA376 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA375 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA374 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA373 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA372 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA371 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA370 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA369 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA368 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA367 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA366 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA365 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA364 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA363 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA362 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA361 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA360 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA359 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA358 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA357 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA356 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA355 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA354 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA353 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA352 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x12C++0x03
hide.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x130++0x03
line.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA415 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA414 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA413 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA412 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA411 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA410 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA409 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA408 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA407 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA406 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA405 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA404 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA403 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA402 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA401 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA400 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA399 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA398 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA397 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA396 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA395 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA394 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA393 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA392 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA391 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA390 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA389 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA388 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA387 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA386 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA385 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA384 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x130++0x03
hide.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x134++0x03
line.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA447 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA446 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA445 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA444 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA443 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA442 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA441 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA440 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA439 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA438 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA437 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA436 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA435 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA434 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA433 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA432 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA431 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA430 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA429 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA428 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA427 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA426 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA425 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA424 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA423 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA422 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA421 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA420 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA419 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA418 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA417 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA416 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x134++0x03
hide.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x138++0x03
line.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA479 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA478 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA477 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA476 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA475 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA474 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA473 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA472 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA471 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA470 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA469 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA468 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA467 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA466 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA465 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA464 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA463 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA462 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA461 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA460 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA459 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA458 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA457 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA456 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA455 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA454 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA453 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA452 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA451 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA450 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA449 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA448 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x138++0x03
hide.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
group.long 0x13C++0x03
line.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA511 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA510 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA509 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA508 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA507 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA506 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA505 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA504 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA503 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA502 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA501 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA500 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA499 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA498 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA497 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA496 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA495 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA494 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA493 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA492 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA491 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA490 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA489 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA488 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA487 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA486 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA485 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA484 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA483 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA482 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA481 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA480 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x13C++0x03
hide.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register"
endif
tree.end
width 24.
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x204++0x03
line.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x204++0x03
hide.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x208++0x03
line.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x208++0x03
hide.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x20C++0x03
line.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x20C++0x03
hide.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x210++0x03
line.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x210++0x03
hide.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x214++0x03
line.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x214++0x03
hide.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x218++0x03
line.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x218++0x03
hide.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x21C++0x03
line.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN255 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN254 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN253 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN252 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN251 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN250 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN249 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN248 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN247 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN246 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN245 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN244 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN243 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN242 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN241 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN240 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x21C++0x03
hide.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x220++0x03
line.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN287 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN286 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN285 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN284 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN283 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN282 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN281 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN280 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN279 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN278 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN277 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN276 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN275 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN274 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN273 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN272 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN271 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN270 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN269 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN268 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN267 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN266 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN265 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN264 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN263 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN262 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN261 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN260 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN259 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN258 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN257 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN256 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x220++0x03
hide.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x224++0x03
line.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN319 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN318 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN317 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN316 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN315 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN314 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN313 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN312 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN311 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN310 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN309 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN308 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN307 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN306 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN305 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN304 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN303 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN302 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN301 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN300 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN299 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN298 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN297 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN296 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN295 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN294 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN293 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN292 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN291 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN290 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN289 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN288 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x224++0x03
hide.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x228++0x03
line.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN351 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN350 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN349 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN348 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN347 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN346 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN345 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN344 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN343 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN342 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN341 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN340 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN339 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN338 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN337 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN336 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN335 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN334 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN333 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN332 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN331 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN330 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN329 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN328 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN327 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN326 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN325 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN324 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN323 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN322 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN321 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN320 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x228++0x03
hide.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x22C++0x03
line.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN383 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN382 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN381 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN380 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN379 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN378 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN377 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN376 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN375 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN374 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN373 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN372 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN371 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN370 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN369 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN368 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN367 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN366 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN365 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN364 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN363 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN362 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN361 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN360 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN359 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN358 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN357 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN356 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN355 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN354 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN353 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN352 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x22C++0x03
hide.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x230++0x03
line.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN415 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN414 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN413 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN412 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN411 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN410 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN409 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN408 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN407 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN406 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN405 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN404 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN403 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN402 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN401 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN400 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN399 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN398 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN397 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN396 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN395 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN394 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN393 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN392 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN391 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN390 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN389 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN388 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN387 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN386 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN385 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN384 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x230++0x03
hide.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x234++0x03
line.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN447 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN446 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN445 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN444 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN443 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN442 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN441 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN440 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN439 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN438 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN437 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN436 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN435 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN434 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN433 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN432 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN431 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN430 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN429 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN428 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN427 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN426 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN425 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN424 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN423 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN422 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN421 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN420 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN419 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN418 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN417 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN416 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x234++0x03
hide.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x238++0x03
line.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN479 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN478 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN477 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN476 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN475 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN474 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN473 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN472 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN471 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN470 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN469 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN468 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN467 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN466 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN465 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN464 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN463 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN462 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN461 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN460 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN459 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN458 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN457 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN456 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN455 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN454 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN453 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN452 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN451 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN450 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN449 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN448 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x238++0x03
hide.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
group.long 0x23C++0x03
line.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN511 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN510 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN509 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN508 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN507 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN506 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN505 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN504 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN503 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN502 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN501 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN500 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN499 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN498 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN497 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN496 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN495 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN494 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN493 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN492 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN491 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN490 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN489 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN488 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN487 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN486 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN485 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN484 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN483 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN482 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN481 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN480 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x23C++0x03
hide.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register"
endif
tree.end
width 11.
tree "Interrupt Active Bit Registers"
rgroup.long 0x300++0x03
line.long 0x00 "ACTIVE0,Active Bit Register 0"
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
rgroup.long 0x304++0x03
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x304++0x03
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
rgroup.long 0x308++0x03
line.long 0x00 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x00 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x308++0x03
hide.long 0x00 "ACTIVE2,Active Bit Register 2"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
rgroup.long 0x30C++0x03
line.long 0x00 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x00 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x30C++0x03
hide.long 0x00 "ACTIVE3,Active Bit Register 3"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
rgroup.long 0x310++0x03
line.long 0x00 "ACTIVE4,Active Bit Register 4"
bitfld.long 0x00 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x310++0x03
hide.long 0x00 "ACTIVE4,Active Bit Register 4"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
rgroup.long 0x314++0x03
line.long 0x00 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x00 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x314++0x03
hide.long 0x00 "ACTIVE5,Active Bit Register 5"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
rgroup.long 0x318++0x03
line.long 0x00 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x00 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x318++0x03
hide.long 0x00 "ACTIVE6,Active Bit Register 6"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
rgroup.long 0x31C++0x03
line.long 0x00 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x00 31. " ACTIVE255 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE254 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE253 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE252 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE251 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE250 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE249 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE248 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE247 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE246 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE245 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE244 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE243 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE242 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE241 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE240 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x31C++0x03
hide.long 0x00 "ACTIVE7,Active Bit Register 7"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
rgroup.long 0x320++0x03
line.long 0x00 "ACTIVE8,Active Bit Register 8"
bitfld.long 0x00 31. " ACTIVE287 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE286 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE285 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE284 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE283 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE282 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE281 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE280 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE279 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE278 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE277 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE276 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE275 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE274 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE273 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE272 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE271 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE270 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE269 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE268 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE267 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE266 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE265 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE264 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE263 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE262 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE261 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE260 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE259 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE258 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE257 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE256 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x320++0x03
hide.long 0x00 "ACTIVE8,Active Bit Register 8"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
rgroup.long 0x324++0x03
line.long 0x00 "ACTIVE9,Active Bit Register 9"
bitfld.long 0x00 31. " ACTIVE319 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE318 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE317 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE316 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE315 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE314 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE313 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE312 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE311 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE310 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE309 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE308 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE307 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE306 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE305 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE304 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE303 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE302 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE301 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE300 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE299 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE298 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE297 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE296 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE295 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE294 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE293 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE292 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE291 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE290 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE289 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE288 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x324++0x03
hide.long 0x00 "ACTIVE9,Active Bit Register 9"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
rgroup.long 0x328++0x03
line.long 0x00 "ACTIVE10,Active Bit Register 10"
bitfld.long 0x00 31. " ACTIVE351 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE350 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE349 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE348 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE347 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE346 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE345 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE344 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE343 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE342 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE341 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE340 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE339 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE338 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE337 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE336 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE335 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE334 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE333 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE332 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE331 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE330 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE329 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE328 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE327 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE326 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE325 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE324 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE323 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE322 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE321 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE320 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x328++0x03
hide.long 0x00 "ACTIVE10,Active Bit Register 10"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
rgroup.long 0x32C++0x03
line.long 0x00 "ACTIVE11,Active Bit Register 11"
bitfld.long 0x00 31. " ACTIVE383 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE382 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE381 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE380 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE379 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE378 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE377 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE376 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE375 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE374 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE373 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE372 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE371 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE370 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE369 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE368 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE367 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE366 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE365 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE364 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE363 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE362 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE361 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE360 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE359 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE358 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE357 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE356 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE355 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE354 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE353 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE352 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x32C++0x03
hide.long 0x00 "ACTIVE11,Active Bit Register 11"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
rgroup.long 0x330++0x03
line.long 0x00 "ACTIVE12,Active Bit Register 12"
bitfld.long 0x00 31. " ACTIVE415 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE414 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE413 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE412 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE411 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE410 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE409 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE408 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE407 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE406 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE405 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE404 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE403 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE402 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE401 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE400 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE399 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE398 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE397 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE396 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE395 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE394 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE393 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE392 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE391 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE390 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE389 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE388 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE387 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE386 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE385 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE384 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x330++0x03
hide.long 0x00 "ACTIVE12,Active Bit Register 12"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
rgroup.long 0x334++0x03
line.long 0x00 "ACTIVE13,Active Bit Register 13"
bitfld.long 0x00 31. " ACTIVE447 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE446 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE445 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE444 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE443 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE442 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE441 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE440 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE439 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE438 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE437 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE436 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE435 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE434 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE433 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE432 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE431 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE430 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE429 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE428 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE427 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE426 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE425 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE424 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE423 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE422 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE421 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE420 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE419 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE418 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE417 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE416 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x334++0x03
hide.long 0x00 "ACTIVE13,Active Bit Register 13"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
rgroup.long 0x338++0x03
line.long 0x00 "ACTIVE14,Active Bit Register 14"
bitfld.long 0x00 31. " ACTIVE479 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE478 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE477 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE476 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE475 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE474 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE473 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE472 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE471 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE470 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE469 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE468 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE467 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE466 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE465 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE464 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE463 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE462 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE461 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE460 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE459 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE458 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE457 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE456 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE455 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE454 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE453 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE452 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE451 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE450 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE449 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE448 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x338++0x03
hide.long 0x00 "ACTIVE14,Active Bit Register 14"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
rgroup.long 0x33C++0x03
line.long 0x00 "ACTIVE15,Active Bit Register 15"
bitfld.long 0x00 31. " ACTIVE511 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE510 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE509 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE508 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE507 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE506 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE505 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE504 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE503 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE502 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE501 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE500 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE499 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE498 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE497 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE496 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE495 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE494 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE493 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE492 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE491 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE490 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE489 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE488 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE487 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE486 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE485 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE484 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE483 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE482 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE481 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE480 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x33C++0x03
hide.long 0x00 "ACTIVE15,Active Bit Register 15"
endif
tree.end
width 13.
tree "Interrupt Target Non-Secure Registers"
group.long 0x380++0x03
line.long 0x00 "NVIC_ITNS0,Interrupt Target Non-Secure Register 0"
bitfld.long 0x00 31. " ITNS31 ,Interrupt Targets Non-secure 31" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS30 ,Interrupt Targets Non-secure 30" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS29 ,Interrupt Targets Non-secure 29" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS28 ,Interrupt Targets Non-secure 28" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS27 ,Interrupt Targets Non-secure 27" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS26 ,Interrupt Targets Non-secure 26" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS25 ,Interrupt Targets Non-secure 25" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS24 ,Interrupt Targets Non-secure 24" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS23 ,Interrupt Targets Non-secure 23" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS22 ,Interrupt Targets Non-secure 22" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS21 ,Interrupt Targets Non-secure 21" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS20 ,Interrupt Targets Non-secure 20" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS19 ,Interrupt Targets Non-secure 19" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS18 ,Interrupt Targets Non-secure 18" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS17 ,Interrupt Targets Non-secure 17" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS16 ,Interrupt Targets Non-secure 16" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS15 ,Interrupt Targets Non-secure 15" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS14 ,Interrupt Targets Non-secure 14" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS13 ,Interrupt Targets Non-secure 13" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS12 ,Interrupt Targets Non-secure 12" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS11 ,Interrupt Targets Non-secure 11" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS10 ,Interrupt Targets Non-secure 10" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS9 ,Interrupt Targets Non-secure 9" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS8 ,Interrupt Targets Non-secure 8" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS7 ,Interrupt Targets Non-secure 7" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS6 ,Interrupt Targets Non-secure 6" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS5 ,Interrupt Targets Non-secure 5" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS4 ,Interrupt Targets Non-secure 4" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS3 ,Interrupt Targets Non-secure 3" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS2 ,Interrupt Targets Non-secure 2" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS1 ,Interrupt Targets Non-secure 1" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS0 ,Interrupt Targets Non-secure 0" "Secure,Non-secure"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x384++0x03
line.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
bitfld.long 0x00 31. " ITNS63 ,Interrupt Targets Non-secure 63" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS62 ,Interrupt Targets Non-secure 62" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS61 ,Interrupt Targets Non-secure 61" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS60 ,Interrupt Targets Non-secure 60" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS59 ,Interrupt Targets Non-secure 59" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS58 ,Interrupt Targets Non-secure 58" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS57 ,Interrupt Targets Non-secure 57" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS56 ,Interrupt Targets Non-secure 56" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS55 ,Interrupt Targets Non-secure 55" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS54 ,Interrupt Targets Non-secure 54" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS53 ,Interrupt Targets Non-secure 53" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS52 ,Interrupt Targets Non-secure 52" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS51 ,Interrupt Targets Non-secure 51" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS50 ,Interrupt Targets Non-secure 50" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS49 ,Interrupt Targets Non-secure 49" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS48 ,Interrupt Targets Non-secure 48" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS47 ,Interrupt Targets Non-secure 47" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS46 ,Interrupt Targets Non-secure 46" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS45 ,Interrupt Targets Non-secure 45" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS44 ,Interrupt Targets Non-secure 44" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS43 ,Interrupt Targets Non-secure 43" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS42 ,Interrupt Targets Non-secure 42" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS41 ,Interrupt Targets Non-secure 41" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS40 ,Interrupt Targets Non-secure 40" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS39 ,Interrupt Targets Non-secure 39" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS38 ,Interrupt Targets Non-secure 38" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS37 ,Interrupt Targets Non-secure 37" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS36 ,Interrupt Targets Non-secure 36" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS35 ,Interrupt Targets Non-secure 35" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS34 ,Interrupt Targets Non-secure 34" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS33 ,Interrupt Targets Non-secure 33" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS32 ,Interrupt Targets Non-secure 32" "Secure,Non-secure"
else
hgroup.long 0x384++0x03
hide.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x388++0x03
line.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
bitfld.long 0x00 31. " ITNS95 ,Interrupt Targets Non-secure 95" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS94 ,Interrupt Targets Non-secure 94" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS93 ,Interrupt Targets Non-secure 93" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS92 ,Interrupt Targets Non-secure 92" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS91 ,Interrupt Targets Non-secure 91" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS90 ,Interrupt Targets Non-secure 90" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS89 ,Interrupt Targets Non-secure 89" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS88 ,Interrupt Targets Non-secure 88" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS87 ,Interrupt Targets Non-secure 87" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS86 ,Interrupt Targets Non-secure 86" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS85 ,Interrupt Targets Non-secure 85" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS84 ,Interrupt Targets Non-secure 84" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS83 ,Interrupt Targets Non-secure 83" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS82 ,Interrupt Targets Non-secure 82" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS81 ,Interrupt Targets Non-secure 81" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS80 ,Interrupt Targets Non-secure 80" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS79 ,Interrupt Targets Non-secure 79" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS78 ,Interrupt Targets Non-secure 78" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS77 ,Interrupt Targets Non-secure 77" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS76 ,Interrupt Targets Non-secure 76" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS75 ,Interrupt Targets Non-secure 75" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS74 ,Interrupt Targets Non-secure 74" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS73 ,Interrupt Targets Non-secure 73" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS72 ,Interrupt Targets Non-secure 72" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS71 ,Interrupt Targets Non-secure 71" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS70 ,Interrupt Targets Non-secure 70" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS69 ,Interrupt Targets Non-secure 69" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS68 ,Interrupt Targets Non-secure 68" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS67 ,Interrupt Targets Non-secure 67" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS66 ,Interrupt Targets Non-secure 66" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS65 ,Interrupt Targets Non-secure 65" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS64 ,Interrupt Targets Non-secure 64" "Secure,Non-secure"
else
hgroup.long 0x388++0x03
hide.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x38C++0x03
line.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
bitfld.long 0x00 31. " ITNS127 ,Interrupt Targets Non-secure 127" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS126 ,Interrupt Targets Non-secure 126" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS125 ,Interrupt Targets Non-secure 125" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS124 ,Interrupt Targets Non-secure 124" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS123 ,Interrupt Targets Non-secure 123" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS122 ,Interrupt Targets Non-secure 122" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS121 ,Interrupt Targets Non-secure 121" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS120 ,Interrupt Targets Non-secure 120" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS119 ,Interrupt Targets Non-secure 119" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS118 ,Interrupt Targets Non-secure 118" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS117 ,Interrupt Targets Non-secure 117" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS116 ,Interrupt Targets Non-secure 116" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS115 ,Interrupt Targets Non-secure 115" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS114 ,Interrupt Targets Non-secure 114" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS113 ,Interrupt Targets Non-secure 113" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS112 ,Interrupt Targets Non-secure 112" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS111 ,Interrupt Targets Non-secure 111" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS110 ,Interrupt Targets Non-secure 110" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS109 ,Interrupt Targets Non-secure 109" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS108 ,Interrupt Targets Non-secure 108" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS107 ,Interrupt Targets Non-secure 107" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS106 ,Interrupt Targets Non-secure 106" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS105 ,Interrupt Targets Non-secure 105" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS104 ,Interrupt Targets Non-secure 104" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS103 ,Interrupt Targets Non-secure 103" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS102 ,Interrupt Targets Non-secure 102" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS101 ,Interrupt Targets Non-secure 101" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS100 ,Interrupt Targets Non-secure 100" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS99 ,Interrupt Targets Non-secure 99" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS98 ,Interrupt Targets Non-secure 98" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS97 ,Interrupt Targets Non-secure 97" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS96 ,Interrupt Targets Non-secure 96" "Secure,Non-secure"
else
hgroup.long 0x38C++0x03
hide.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x390++0x03
line.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
bitfld.long 0x00 31. " ITNS159 ,Interrupt Targets Non-secure 159" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS158 ,Interrupt Targets Non-secure 158" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS157 ,Interrupt Targets Non-secure 157" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS156 ,Interrupt Targets Non-secure 156" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS155 ,Interrupt Targets Non-secure 155" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS154 ,Interrupt Targets Non-secure 154" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS153 ,Interrupt Targets Non-secure 153" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS152 ,Interrupt Targets Non-secure 152" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS151 ,Interrupt Targets Non-secure 151" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS150 ,Interrupt Targets Non-secure 150" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS149 ,Interrupt Targets Non-secure 149" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS148 ,Interrupt Targets Non-secure 148" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS147 ,Interrupt Targets Non-secure 147" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS146 ,Interrupt Targets Non-secure 146" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS145 ,Interrupt Targets Non-secure 145" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS144 ,Interrupt Targets Non-secure 144" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS143 ,Interrupt Targets Non-secure 143" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS142 ,Interrupt Targets Non-secure 142" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS141 ,Interrupt Targets Non-secure 141" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS140 ,Interrupt Targets Non-secure 140" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS139 ,Interrupt Targets Non-secure 139" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS138 ,Interrupt Targets Non-secure 138" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS137 ,Interrupt Targets Non-secure 137" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS136 ,Interrupt Targets Non-secure 136" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS135 ,Interrupt Targets Non-secure 135" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS134 ,Interrupt Targets Non-secure 134" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS133 ,Interrupt Targets Non-secure 133" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS132 ,Interrupt Targets Non-secure 132" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS131 ,Interrupt Targets Non-secure 131" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS130 ,Interrupt Targets Non-secure 130" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS129 ,Interrupt Targets Non-secure 129" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS128 ,Interrupt Targets Non-secure 128" "Secure,Non-secure"
else
hgroup.long 0x390++0x03
hide.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x394++0x03
line.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
bitfld.long 0x00 31. " ITNS191 ,Interrupt Targets Non-secure 191" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS190 ,Interrupt Targets Non-secure 190" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS189 ,Interrupt Targets Non-secure 189" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS188 ,Interrupt Targets Non-secure 188" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS187 ,Interrupt Targets Non-secure 187" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS186 ,Interrupt Targets Non-secure 186" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS185 ,Interrupt Targets Non-secure 185" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS184 ,Interrupt Targets Non-secure 184" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS183 ,Interrupt Targets Non-secure 183" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS182 ,Interrupt Targets Non-secure 182" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS181 ,Interrupt Targets Non-secure 181" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS180 ,Interrupt Targets Non-secure 180" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS179 ,Interrupt Targets Non-secure 179" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS178 ,Interrupt Targets Non-secure 178" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS177 ,Interrupt Targets Non-secure 177" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS176 ,Interrupt Targets Non-secure 176" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS175 ,Interrupt Targets Non-secure 175" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS174 ,Interrupt Targets Non-secure 174" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS173 ,Interrupt Targets Non-secure 173" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS172 ,Interrupt Targets Non-secure 172" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS171 ,Interrupt Targets Non-secure 171" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS170 ,Interrupt Targets Non-secure 170" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS169 ,Interrupt Targets Non-secure 169" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS168 ,Interrupt Targets Non-secure 168" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS167 ,Interrupt Targets Non-secure 167" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS166 ,Interrupt Targets Non-secure 166" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS165 ,Interrupt Targets Non-secure 165" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS164 ,Interrupt Targets Non-secure 164" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS163 ,Interrupt Targets Non-secure 163" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS162 ,Interrupt Targets Non-secure 162" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS161 ,Interrupt Targets Non-secure 161" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS160 ,Interrupt Targets Non-secure 160" "Secure,Non-secure"
else
hgroup.long 0x394++0x03
hide.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x398++0x03
line.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
bitfld.long 0x00 31. " ITNS223 ,Interrupt Targets Non-secure 223" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS222 ,Interrupt Targets Non-secure 222" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS221 ,Interrupt Targets Non-secure 221" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS220 ,Interrupt Targets Non-secure 220" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS219 ,Interrupt Targets Non-secure 219" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS218 ,Interrupt Targets Non-secure 218" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS217 ,Interrupt Targets Non-secure 217" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS216 ,Interrupt Targets Non-secure 216" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS215 ,Interrupt Targets Non-secure 215" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS214 ,Interrupt Targets Non-secure 214" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS213 ,Interrupt Targets Non-secure 213" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS212 ,Interrupt Targets Non-secure 212" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS211 ,Interrupt Targets Non-secure 211" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS210 ,Interrupt Targets Non-secure 210" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS209 ,Interrupt Targets Non-secure 209" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS208 ,Interrupt Targets Non-secure 208" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS207 ,Interrupt Targets Non-secure 207" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS206 ,Interrupt Targets Non-secure 206" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS205 ,Interrupt Targets Non-secure 205" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS204 ,Interrupt Targets Non-secure 204" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS203 ,Interrupt Targets Non-secure 203" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS202 ,Interrupt Targets Non-secure 202" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS201 ,Interrupt Targets Non-secure 201" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS200 ,Interrupt Targets Non-secure 200" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS199 ,Interrupt Targets Non-secure 199" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS198 ,Interrupt Targets Non-secure 198" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS197 ,Interrupt Targets Non-secure 197" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS196 ,Interrupt Targets Non-secure 196" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS195 ,Interrupt Targets Non-secure 195" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS194 ,Interrupt Targets Non-secure 194" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS193 ,Interrupt Targets Non-secure 193" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS192 ,Interrupt Targets Non-secure 192" "Secure,Non-secure"
else
hgroup.long 0x398++0x03
hide.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x39C++0x03
line.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
bitfld.long 0x00 31. " ITNS255 ,Interrupt Targets Non-secure 255" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS254 ,Interrupt Targets Non-secure 254" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS253 ,Interrupt Targets Non-secure 253" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS252 ,Interrupt Targets Non-secure 252" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS251 ,Interrupt Targets Non-secure 251" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS250 ,Interrupt Targets Non-secure 250" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS249 ,Interrupt Targets Non-secure 249" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS248 ,Interrupt Targets Non-secure 248" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS247 ,Interrupt Targets Non-secure 247" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS246 ,Interrupt Targets Non-secure 246" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS245 ,Interrupt Targets Non-secure 245" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS244 ,Interrupt Targets Non-secure 244" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS243 ,Interrupt Targets Non-secure 243" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS242 ,Interrupt Targets Non-secure 242" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS241 ,Interrupt Targets Non-secure 241" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS240 ,Interrupt Targets Non-secure 240" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS239 ,Interrupt Targets Non-secure 239" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS238 ,Interrupt Targets Non-secure 238" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS237 ,Interrupt Targets Non-secure 237" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS236 ,Interrupt Targets Non-secure 236" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS235 ,Interrupt Targets Non-secure 235" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS234 ,Interrupt Targets Non-secure 234" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS233 ,Interrupt Targets Non-secure 233" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS232 ,Interrupt Targets Non-secure 232" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS231 ,Interrupt Targets Non-secure 231" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS230 ,Interrupt Targets Non-secure 230" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS229 ,Interrupt Targets Non-secure 229" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS228 ,Interrupt Targets Non-secure 228" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS227 ,Interrupt Targets Non-secure 227" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS226 ,Interrupt Targets Non-secure 226" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS225 ,Interrupt Targets Non-secure 225" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS224 ,Interrupt Targets Non-secure 224" "Secure,Non-secure"
else
hgroup.long 0x39C++0x03
hide.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x3A0++0x03
line.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8"
bitfld.long 0x00 31. " ITNS287 ,Interrupt Targets Non-secure 287" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS286 ,Interrupt Targets Non-secure 286" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS285 ,Interrupt Targets Non-secure 285" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS284 ,Interrupt Targets Non-secure 284" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS283 ,Interrupt Targets Non-secure 283" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS282 ,Interrupt Targets Non-secure 282" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS281 ,Interrupt Targets Non-secure 281" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS280 ,Interrupt Targets Non-secure 280" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS279 ,Interrupt Targets Non-secure 279" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS278 ,Interrupt Targets Non-secure 278" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS277 ,Interrupt Targets Non-secure 277" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS276 ,Interrupt Targets Non-secure 276" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS275 ,Interrupt Targets Non-secure 275" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS274 ,Interrupt Targets Non-secure 274" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS273 ,Interrupt Targets Non-secure 273" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS272 ,Interrupt Targets Non-secure 272" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS271 ,Interrupt Targets Non-secure 271" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS270 ,Interrupt Targets Non-secure 270" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS269 ,Interrupt Targets Non-secure 269" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS268 ,Interrupt Targets Non-secure 268" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS267 ,Interrupt Targets Non-secure 267" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS266 ,Interrupt Targets Non-secure 266" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS265 ,Interrupt Targets Non-secure 265" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS264 ,Interrupt Targets Non-secure 264" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS263 ,Interrupt Targets Non-secure 263" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS262 ,Interrupt Targets Non-secure 262" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS261 ,Interrupt Targets Non-secure 261" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS260 ,Interrupt Targets Non-secure 260" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS259 ,Interrupt Targets Non-secure 259" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS258 ,Interrupt Targets Non-secure 258" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS257 ,Interrupt Targets Non-secure 257" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS256 ,Interrupt Targets Non-secure 256" "Secure,Non-secure"
else
hgroup.long 0x3A0++0x03
hide.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x3A4++0x03
line.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9"
bitfld.long 0x00 31. " ITNS319 ,Interrupt Targets Non-secure 319" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS318 ,Interrupt Targets Non-secure 318" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS317 ,Interrupt Targets Non-secure 317" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS316 ,Interrupt Targets Non-secure 316" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS315 ,Interrupt Targets Non-secure 315" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS314 ,Interrupt Targets Non-secure 314" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS313 ,Interrupt Targets Non-secure 313" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS312 ,Interrupt Targets Non-secure 312" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS311 ,Interrupt Targets Non-secure 311" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS310 ,Interrupt Targets Non-secure 310" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS309 ,Interrupt Targets Non-secure 309" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS308 ,Interrupt Targets Non-secure 308" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS307 ,Interrupt Targets Non-secure 307" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS306 ,Interrupt Targets Non-secure 306" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS305 ,Interrupt Targets Non-secure 305" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS304 ,Interrupt Targets Non-secure 304" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS303 ,Interrupt Targets Non-secure 303" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS302 ,Interrupt Targets Non-secure 302" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS301 ,Interrupt Targets Non-secure 301" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS300 ,Interrupt Targets Non-secure 300" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS299 ,Interrupt Targets Non-secure 299" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS298 ,Interrupt Targets Non-secure 298" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS297 ,Interrupt Targets Non-secure 297" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS296 ,Interrupt Targets Non-secure 296" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS295 ,Interrupt Targets Non-secure 295" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS294 ,Interrupt Targets Non-secure 294" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS293 ,Interrupt Targets Non-secure 293" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS292 ,Interrupt Targets Non-secure 292" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS291 ,Interrupt Targets Non-secure 291" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS290 ,Interrupt Targets Non-secure 290" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS289 ,Interrupt Targets Non-secure 289" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS288 ,Interrupt Targets Non-secure 288" "Secure,Non-secure"
else
hgroup.long 0x3A4++0x03
hide.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x3A8++0x03
line.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10"
bitfld.long 0x00 31. " ITNS351 ,Interrupt Targets Non-secure 351" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS350 ,Interrupt Targets Non-secure 350" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS349 ,Interrupt Targets Non-secure 349" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS348 ,Interrupt Targets Non-secure 348" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS347 ,Interrupt Targets Non-secure 347" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS346 ,Interrupt Targets Non-secure 346" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS345 ,Interrupt Targets Non-secure 345" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS344 ,Interrupt Targets Non-secure 344" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS343 ,Interrupt Targets Non-secure 343" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS342 ,Interrupt Targets Non-secure 342" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS341 ,Interrupt Targets Non-secure 341" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS340 ,Interrupt Targets Non-secure 340" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS339 ,Interrupt Targets Non-secure 339" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS338 ,Interrupt Targets Non-secure 338" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS337 ,Interrupt Targets Non-secure 337" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS336 ,Interrupt Targets Non-secure 336" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS335 ,Interrupt Targets Non-secure 335" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS334 ,Interrupt Targets Non-secure 334" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS333 ,Interrupt Targets Non-secure 333" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS332 ,Interrupt Targets Non-secure 332" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS331 ,Interrupt Targets Non-secure 331" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS330 ,Interrupt Targets Non-secure 330" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS329 ,Interrupt Targets Non-secure 329" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS328 ,Interrupt Targets Non-secure 328" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS327 ,Interrupt Targets Non-secure 327" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS326 ,Interrupt Targets Non-secure 326" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS325 ,Interrupt Targets Non-secure 325" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS324 ,Interrupt Targets Non-secure 324" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS323 ,Interrupt Targets Non-secure 323" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS322 ,Interrupt Targets Non-secure 322" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS321 ,Interrupt Targets Non-secure 321" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS320 ,Interrupt Targets Non-secure 320" "Secure,Non-secure"
else
hgroup.long 0x3A8++0x03
hide.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x3AC++0x03
line.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11"
bitfld.long 0x00 31. " ITNS383 ,Interrupt Targets Non-secure 383" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS382 ,Interrupt Targets Non-secure 382" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS381 ,Interrupt Targets Non-secure 381" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS380 ,Interrupt Targets Non-secure 380" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS379 ,Interrupt Targets Non-secure 379" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS378 ,Interrupt Targets Non-secure 378" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS377 ,Interrupt Targets Non-secure 377" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS376 ,Interrupt Targets Non-secure 376" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS375 ,Interrupt Targets Non-secure 375" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS374 ,Interrupt Targets Non-secure 374" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS373 ,Interrupt Targets Non-secure 373" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS372 ,Interrupt Targets Non-secure 372" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS371 ,Interrupt Targets Non-secure 371" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS370 ,Interrupt Targets Non-secure 370" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS369 ,Interrupt Targets Non-secure 369" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS368 ,Interrupt Targets Non-secure 368" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS367 ,Interrupt Targets Non-secure 367" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS366 ,Interrupt Targets Non-secure 366" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS365 ,Interrupt Targets Non-secure 365" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS364 ,Interrupt Targets Non-secure 364" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS363 ,Interrupt Targets Non-secure 363" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS362 ,Interrupt Targets Non-secure 362" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS361 ,Interrupt Targets Non-secure 361" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS360 ,Interrupt Targets Non-secure 360" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS359 ,Interrupt Targets Non-secure 359" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS358 ,Interrupt Targets Non-secure 358" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS357 ,Interrupt Targets Non-secure 357" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS356 ,Interrupt Targets Non-secure 356" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS355 ,Interrupt Targets Non-secure 355" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS354 ,Interrupt Targets Non-secure 354" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS353 ,Interrupt Targets Non-secure 353" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS352 ,Interrupt Targets Non-secure 352" "Secure,Non-secure"
else
hgroup.long 0x3AC++0x03
hide.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x3B0++0x03
line.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12"
bitfld.long 0x00 31. " ITNS415 ,Interrupt Targets Non-secure 415" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS414 ,Interrupt Targets Non-secure 414" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS413 ,Interrupt Targets Non-secure 413" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS412 ,Interrupt Targets Non-secure 412" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS411 ,Interrupt Targets Non-secure 411" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS410 ,Interrupt Targets Non-secure 410" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS409 ,Interrupt Targets Non-secure 409" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS408 ,Interrupt Targets Non-secure 408" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS407 ,Interrupt Targets Non-secure 407" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS406 ,Interrupt Targets Non-secure 406" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS405 ,Interrupt Targets Non-secure 405" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS404 ,Interrupt Targets Non-secure 404" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS403 ,Interrupt Targets Non-secure 403" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS402 ,Interrupt Targets Non-secure 402" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS401 ,Interrupt Targets Non-secure 401" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS400 ,Interrupt Targets Non-secure 400" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS399 ,Interrupt Targets Non-secure 399" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS398 ,Interrupt Targets Non-secure 398" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS397 ,Interrupt Targets Non-secure 397" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS396 ,Interrupt Targets Non-secure 396" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS395 ,Interrupt Targets Non-secure 395" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS394 ,Interrupt Targets Non-secure 394" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS393 ,Interrupt Targets Non-secure 393" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS392 ,Interrupt Targets Non-secure 392" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS391 ,Interrupt Targets Non-secure 391" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS390 ,Interrupt Targets Non-secure 390" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS389 ,Interrupt Targets Non-secure 389" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS388 ,Interrupt Targets Non-secure 388" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS387 ,Interrupt Targets Non-secure 387" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS386 ,Interrupt Targets Non-secure 386" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS385 ,Interrupt Targets Non-secure 385" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS384 ,Interrupt Targets Non-secure 384" "Secure,Non-secure"
else
hgroup.long 0x3B0++0x03
hide.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x3B4++0x03
line.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13"
bitfld.long 0x00 31. " ITNS447 ,Interrupt Targets Non-secure 447" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS446 ,Interrupt Targets Non-secure 446" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS445 ,Interrupt Targets Non-secure 445" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS444 ,Interrupt Targets Non-secure 444" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS443 ,Interrupt Targets Non-secure 443" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS442 ,Interrupt Targets Non-secure 442" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS441 ,Interrupt Targets Non-secure 441" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS440 ,Interrupt Targets Non-secure 440" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS439 ,Interrupt Targets Non-secure 439" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS438 ,Interrupt Targets Non-secure 438" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS437 ,Interrupt Targets Non-secure 437" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS436 ,Interrupt Targets Non-secure 436" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS435 ,Interrupt Targets Non-secure 435" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS434 ,Interrupt Targets Non-secure 434" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS433 ,Interrupt Targets Non-secure 433" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS432 ,Interrupt Targets Non-secure 432" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS431 ,Interrupt Targets Non-secure 431" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS430 ,Interrupt Targets Non-secure 430" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS429 ,Interrupt Targets Non-secure 429" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS428 ,Interrupt Targets Non-secure 428" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS427 ,Interrupt Targets Non-secure 427" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS426 ,Interrupt Targets Non-secure 426" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS425 ,Interrupt Targets Non-secure 425" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS424 ,Interrupt Targets Non-secure 424" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS423 ,Interrupt Targets Non-secure 423" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS422 ,Interrupt Targets Non-secure 422" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS421 ,Interrupt Targets Non-secure 421" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS420 ,Interrupt Targets Non-secure 420" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS419 ,Interrupt Targets Non-secure 419" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS418 ,Interrupt Targets Non-secure 418" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS417 ,Interrupt Targets Non-secure 417" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS416 ,Interrupt Targets Non-secure 416" "Secure,Non-secure"
else
hgroup.long 0x3B4++0x03
hide.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x3B8++0x03
line.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14"
bitfld.long 0x00 31. " ITNS479 ,Interrupt Targets Non-secure 479" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS478 ,Interrupt Targets Non-secure 478" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS477 ,Interrupt Targets Non-secure 477" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS476 ,Interrupt Targets Non-secure 476" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS475 ,Interrupt Targets Non-secure 475" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS474 ,Interrupt Targets Non-secure 474" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS473 ,Interrupt Targets Non-secure 473" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS472 ,Interrupt Targets Non-secure 472" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS471 ,Interrupt Targets Non-secure 471" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS470 ,Interrupt Targets Non-secure 470" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS469 ,Interrupt Targets Non-secure 469" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS468 ,Interrupt Targets Non-secure 468" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS467 ,Interrupt Targets Non-secure 467" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS466 ,Interrupt Targets Non-secure 466" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS465 ,Interrupt Targets Non-secure 465" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS464 ,Interrupt Targets Non-secure 464" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS463 ,Interrupt Targets Non-secure 463" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS462 ,Interrupt Targets Non-secure 462" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS461 ,Interrupt Targets Non-secure 461" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS460 ,Interrupt Targets Non-secure 460" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS459 ,Interrupt Targets Non-secure 459" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS458 ,Interrupt Targets Non-secure 458" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS457 ,Interrupt Targets Non-secure 457" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS456 ,Interrupt Targets Non-secure 456" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS455 ,Interrupt Targets Non-secure 455" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS454 ,Interrupt Targets Non-secure 454" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS453 ,Interrupt Targets Non-secure 453" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS452 ,Interrupt Targets Non-secure 452" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS451 ,Interrupt Targets Non-secure 451" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS450 ,Interrupt Targets Non-secure 450" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS449 ,Interrupt Targets Non-secure 449" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS448 ,Interrupt Targets Non-secure 448" "Secure,Non-secure"
else
hgroup.long 0x3B8++0x03
hide.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x0F)
group.long 0x3BC++0x03
line.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15"
bitfld.long 0x00 31. " ITNS511 ,Interrupt Targets Non-secure 511" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS510 ,Interrupt Targets Non-secure 510" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS509 ,Interrupt Targets Non-secure 509" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS508 ,Interrupt Targets Non-secure 508" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS507 ,Interrupt Targets Non-secure 507" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS506 ,Interrupt Targets Non-secure 506" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS505 ,Interrupt Targets Non-secure 505" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS504 ,Interrupt Targets Non-secure 504" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS503 ,Interrupt Targets Non-secure 503" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS502 ,Interrupt Targets Non-secure 502" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS501 ,Interrupt Targets Non-secure 501" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS500 ,Interrupt Targets Non-secure 500" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS499 ,Interrupt Targets Non-secure 499" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS498 ,Interrupt Targets Non-secure 498" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS497 ,Interrupt Targets Non-secure 497" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS496 ,Interrupt Targets Non-secure 496" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS495 ,Interrupt Targets Non-secure 495" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS494 ,Interrupt Targets Non-secure 494" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS493 ,Interrupt Targets Non-secure 493" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS492 ,Interrupt Targets Non-secure 492" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS491 ,Interrupt Targets Non-secure 491" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS490 ,Interrupt Targets Non-secure 490" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS489 ,Interrupt Targets Non-secure 489" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS488 ,Interrupt Targets Non-secure 488" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS487 ,Interrupt Targets Non-secure 487" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS486 ,Interrupt Targets Non-secure 486" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS485 ,Interrupt Targets Non-secure 485" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS484 ,Interrupt Targets Non-secure 484" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS483 ,Interrupt Targets Non-secure 483" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS482 ,Interrupt Targets Non-secure 482" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS481 ,Interrupt Targets Non-secure 481" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS480 ,Interrupt Targets Non-secure 480" "Secure,Non-secure"
else
hgroup.long 0x3BC++0x03
hide.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15"
endif
tree.end
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x420++0x1F
line.long 0x0 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
line.long 0x4 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
line.long 0x8 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
line.long 0xC "IPR11,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
line.long 0x10 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
line.long 0x14 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
line.long 0x18 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
line.long 0x1C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
else
hgroup.long 0x420++0x1F
hide.long 0x0 "IPR8,Interrupt Priority Register"
hide.long 0x4 "IPR9,Interrupt Priority Register"
hide.long 0x8 "IPR10,Interrupt Priority Register"
hide.long 0xC "IPR11,Interrupt Priority Register"
hide.long 0x10 "IPR12,Interrupt Priority Register"
hide.long 0x14 "IPR13,Interrupt Priority Register"
hide.long 0x18 "IPR14,Interrupt Priority Register"
hide.long 0x1C "IPR15,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x440++0x1F
line.long 0x0 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
line.long 0x4 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
line.long 0x8 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
line.long 0xC "IPR19,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
line.long 0x10 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
line.long 0x14 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
line.long 0x18 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
line.long 0x1C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
else
hgroup.long 0x440++0x1F
hide.long 0x0 "IPR16,Interrupt Priority Register"
hide.long 0x4 "IPR17,Interrupt Priority Register"
hide.long 0x8 "IPR18,Interrupt Priority Register"
hide.long 0xC "IPR19,Interrupt Priority Register"
hide.long 0x10 "IPR20,Interrupt Priority Register"
hide.long 0x14 "IPR21,Interrupt Priority Register"
hide.long 0x18 "IPR22,Interrupt Priority Register"
hide.long 0x1C "IPR23,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x460++0x1F
line.long 0x0 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
line.long 0x4 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
line.long 0x8 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
line.long 0xC "IPR27,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
line.long 0x10 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
line.long 0x14 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
line.long 0x18 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
line.long 0x1C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
else
hgroup.long 0x460++0x1F
hide.long 0x0 "IPR24,Interrupt Priority Register"
hide.long 0x4 "IPR25,Interrupt Priority Register"
hide.long 0x8 "IPR26,Interrupt Priority Register"
hide.long 0xC "IPR27,Interrupt Priority Register"
hide.long 0x10 "IPR28,Interrupt Priority Register"
hide.long 0x14 "IPR29,Interrupt Priority Register"
hide.long 0x18 "IPR30,Interrupt Priority Register"
hide.long 0x1C "IPR31,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x480++0x1F
line.long 0x0 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
line.long 0x4 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
line.long 0x8 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
line.long 0xC "IPR35,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
line.long 0x10 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
line.long 0x14 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
line.long 0x18 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
line.long 0x1C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
else
hgroup.long 0x480++0x1F
hide.long 0x0 "IPR32,Interrupt Priority Register"
hide.long 0x4 "IPR33,Interrupt Priority Register"
hide.long 0x8 "IPR34,Interrupt Priority Register"
hide.long 0xC "IPR35,Interrupt Priority Register"
hide.long 0x10 "IPR36,Interrupt Priority Register"
hide.long 0x14 "IPR37,Interrupt Priority Register"
hide.long 0x18 "IPR38,Interrupt Priority Register"
hide.long 0x1C "IPR39,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x4A0++0x1F
line.long 0x0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
line.long 0x4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
line.long 0x8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
line.long 0xC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
line.long 0x10 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
line.long 0x14 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
line.long 0x18 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
line.long 0x1C "IPR47,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
else
hgroup.long 0x4A0++0x1F
hide.long 0x0 "IPR40,Interrupt Priority Register"
hide.long 0x4 "IPR41,Interrupt Priority Register"
hide.long 0x8 "IPR42,Interrupt Priority Register"
hide.long 0xC "IPR43,Interrupt Priority Register"
hide.long 0x10 "IPR44,Interrupt Priority Register"
hide.long 0x14 "IPR45,Interrupt Priority Register"
hide.long 0x18 "IPR46,Interrupt Priority Register"
hide.long 0x1C "IPR47,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x4C0++0x1F
line.long 0x0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
line.long 0x4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
line.long 0x8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
line.long 0xC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
line.long 0x10 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
line.long 0x14 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
line.long 0x18 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
line.long 0x1C "IPR55,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
else
hgroup.long 0x4C0++0x1F
hide.long 0x0 "IPR48,Interrupt Priority Register"
hide.long 0x4 "IPR49,Interrupt Priority Register"
hide.long 0x8 "IPR50,Interrupt Priority Register"
hide.long 0xC "IPR51,Interrupt Priority Register"
hide.long 0x10 "IPR52,Interrupt Priority Register"
hide.long 0x14 "IPR53,Interrupt Priority Register"
hide.long 0x18 "IPR54,Interrupt Priority Register"
hide.long 0x1C "IPR55,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x4E0++0x1F
line.long 0x0 "IPR56,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
line.long 0x4 "IPR57,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
line.long 0x8 "IPR58,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
line.long 0xC "IPR59,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
line.long 0x10 "IPR60,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_243 ,Interrupt 243 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_242 ,Interrupt 242 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_241 ,Interrupt 241 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_240 ,Interrupt 240 Priority"
line.long 0x14 "IPR61,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_247 ,Interrupt 247 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_246 ,Interrupt 246 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_245 ,Interrupt 245 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_244 ,Interrupt 244 Priority"
line.long 0x18 "IPR62,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_251 ,Interrupt 251 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_250 ,Interrupt 250 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_249 ,Interrupt 249 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_248 ,Interrupt 248 Priority"
line.long 0x1C "IPR63,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_255 ,Interrupt 255 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_254 ,Interrupt 254 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_253 ,Interrupt 253 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_252 ,Interrupt 252 Priority"
else
hgroup.long 0x4E0++0x1F
hide.long 0x0 "IPR56,Interrupt Priority Register"
hide.long 0x4 "IPR57,Interrupt Priority Register"
hide.long 0x8 "IPR58,Interrupt Priority Register"
hide.long 0xC "IPR59,Interrupt Priority Register"
hide.long 0x10 "IPR60,Interrupt Priority Register"
hide.long 0x14 "IPR61,Interrupt Priority Register"
hide.long 0x18 "IPR62,Interrupt Priority Register"
hide.long 0x1C "IPR63,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x500++0x1F
line.long 0x0 "IPR64,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_259 ,Interrupt 259 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_258 ,Interrupt 258 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_257 ,Interrupt 257 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_256 ,Interrupt 256 Priority"
line.long 0x4 "IPR65,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_263 ,Interrupt 263 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_262 ,Interrupt 262 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_261 ,Interrupt 261 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_260 ,Interrupt 260 Priority"
line.long 0x8 "IPR66,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_267 ,Interrupt 267 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_266 ,Interrupt 266 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_265 ,Interrupt 265 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_264 ,Interrupt 264 Priority"
line.long 0xC "IPR67,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_271 ,Interrupt 271 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_270 ,Interrupt 270 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_269 ,Interrupt 269 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_268 ,Interrupt 268 Priority"
line.long 0x10 "IPR68,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_275 ,Interrupt 275 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_274 ,Interrupt 274 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_273 ,Interrupt 273 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_272 ,Interrupt 272 Priority"
line.long 0x14 "IPR69,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_279 ,Interrupt 279 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_278 ,Interrupt 278 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_277 ,Interrupt 277 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_276 ,Interrupt 276 Priority"
line.long 0x18 "IPR70,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_283 ,Interrupt 283 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_282 ,Interrupt 282 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_281 ,Interrupt 281 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_280 ,Interrupt 280 Priority"
line.long 0x1C "IPR71,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_287 ,Interrupt 287 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_286 ,Interrupt 286 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_285 ,Interrupt 285 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_284 ,Interrupt 284 Priority"
else
hgroup.long 0x500++0x1F
hide.long 0x0 "IPR64,Interrupt Priority Register"
hide.long 0x4 "IPR65,Interrupt Priority Register"
hide.long 0x8 "IPR66,Interrupt Priority Register"
hide.long 0xC "IPR67,Interrupt Priority Register"
hide.long 0x10 "IPR68,Interrupt Priority Register"
hide.long 0x14 "IPR69,Interrupt Priority Register"
hide.long 0x18 "IPR70,Interrupt Priority Register"
hide.long 0x1C "IPR71,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x520++0x1F
line.long 0x0 "IPR72,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_291 ,Interrupt 291 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_290 ,Interrupt 290 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_289 ,Interrupt 289 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_288 ,Interrupt 288 Priority"
line.long 0x4 "IPR73,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_295 ,Interrupt 295 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_294 ,Interrupt 294 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_293 ,Interrupt 293 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_292 ,Interrupt 292 Priority"
line.long 0x8 "IPR74,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_299 ,Interrupt 299 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_298 ,Interrupt 298 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_297 ,Interrupt 297 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_296 ,Interrupt 296 Priority"
line.long 0xC "IPR75,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_303 ,Interrupt 303 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_302 ,Interrupt 302 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_301 ,Interrupt 301 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_300 ,Interrupt 300 Priority"
line.long 0x10 "IPR76,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_307 ,Interrupt 307 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_306 ,Interrupt 306 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_305 ,Interrupt 305 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_304 ,Interrupt 304 Priority"
line.long 0x14 "IPR77,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_311 ,Interrupt 311 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_310 ,Interrupt 310 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_309 ,Interrupt 309 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_308 ,Interrupt 308 Priority"
line.long 0x18 "IPR78,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_315 ,Interrupt 315 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_314 ,Interrupt 314 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_313 ,Interrupt 313 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_312 ,Interrupt 312 Priority"
line.long 0x1C "IPR79,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_319 ,Interrupt 319 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_318 ,Interrupt 318 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_317 ,Interrupt 317 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_316 ,Interrupt 316 Priority"
else
hgroup.long 0x520++0x1F
hide.long 0x0 "IPR72,Interrupt Priority Register"
hide.long 0x4 "IPR73,Interrupt Priority Register"
hide.long 0x8 "IPR74,Interrupt Priority Register"
hide.long 0xC "IPR75,Interrupt Priority Register"
hide.long 0x10 "IPR76,Interrupt Priority Register"
hide.long 0x14 "IPR77,Interrupt Priority Register"
hide.long 0x18 "IPR78,Interrupt Priority Register"
hide.long 0x1C "IPR79,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x540++0x1F
line.long 0x0 "IPR80,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_323 ,Interrupt 323 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_322 ,Interrupt 322 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_321 ,Interrupt 321 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_320 ,Interrupt 320 Priority"
line.long 0x4 "IPR81,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_327 ,Interrupt 327 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_326 ,Interrupt 326 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_325 ,Interrupt 325 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_324 ,Interrupt 324 Priority"
line.long 0x8 "IPR82,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_331 ,Interrupt 331 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_330 ,Interrupt 330 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_329 ,Interrupt 329 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_328 ,Interrupt 328 Priority"
line.long 0xC "IPR83,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_335 ,Interrupt 335 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_334 ,Interrupt 334 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_333 ,Interrupt 333 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_332 ,Interrupt 332 Priority"
line.long 0x10 "IPR84,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_339 ,Interrupt 339 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_338 ,Interrupt 338 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_337 ,Interrupt 337 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_336 ,Interrupt 336 Priority"
line.long 0x14 "IPR85,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_343 ,Interrupt 343 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_342 ,Interrupt 342 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_341 ,Interrupt 341 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_340 ,Interrupt 340 Priority"
line.long 0x18 "IPR86,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_347 ,Interrupt 347 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_346 ,Interrupt 346 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_345 ,Interrupt 345 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_344 ,Interrupt 344 Priority"
line.long 0x1C "IPR87,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_351 ,Interrupt 351 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_350 ,Interrupt 350 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_349 ,Interrupt 349 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_348 ,Interrupt 348 Priority"
else
hgroup.long 0x540++0x1F
hide.long 0x0 "IPR80,Interrupt Priority Register"
hide.long 0x4 "IPR81,Interrupt Priority Register"
hide.long 0x8 "IPR82,Interrupt Priority Register"
hide.long 0xC "IPR83,Interrupt Priority Register"
hide.long 0x10 "IPR84,Interrupt Priority Register"
hide.long 0x14 "IPR85,Interrupt Priority Register"
hide.long 0x18 "IPR86,Interrupt Priority Register"
hide.long 0x1C "IPR87,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x560++0x1F
line.long 0x0 "IPR88,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_355 ,Interrupt 355 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_354 ,Interrupt 354 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_353 ,Interrupt 353 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_352 ,Interrupt 352 Priority"
line.long 0x4 "IPR89,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_359 ,Interrupt 359 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_358 ,Interrupt 358 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_357 ,Interrupt 357 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_356 ,Interrupt 356 Priority"
line.long 0x8 "IPR90,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_363 ,Interrupt 363 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_362 ,Interrupt 362 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_361 ,Interrupt 361 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_360 ,Interrupt 360 Priority"
line.long 0xC "IPR91,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_367 ,Interrupt 367 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_366 ,Interrupt 366 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_365 ,Interrupt 365 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_364 ,Interrupt 364 Priority"
line.long 0x10 "IPR92,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_371 ,Interrupt 371 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_370 ,Interrupt 370 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_369 ,Interrupt 369 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_368 ,Interrupt 368 Priority"
line.long 0x14 "IPR93,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_375 ,Interrupt 375 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_374 ,Interrupt 374 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_373 ,Interrupt 373 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_372 ,Interrupt 372 Priority"
line.long 0x18 "IPR94,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_379 ,Interrupt 379 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_378 ,Interrupt 378 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_377 ,Interrupt 377 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_376 ,Interrupt 376 Priority"
line.long 0x1C "IPR95,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_383 ,Interrupt 383 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_382 ,Interrupt 382 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_381 ,Interrupt 381 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_380 ,Interrupt 380 Priority"
else
hgroup.long 0x560++0x1F
hide.long 0x0 "IPR88,Interrupt Priority Register"
hide.long 0x4 "IPR89,Interrupt Priority Register"
hide.long 0x8 "IPR90,Interrupt Priority Register"
hide.long 0xC "IPR91,Interrupt Priority Register"
hide.long 0x10 "IPR92,Interrupt Priority Register"
hide.long 0x14 "IPR93,Interrupt Priority Register"
hide.long 0x18 "IPR94,Interrupt Priority Register"
hide.long 0x1C "IPR95,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x580++0x1F
line.long 0x0 "IPR96,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_387 ,Interrupt 387 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_386 ,Interrupt 386 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_385 ,Interrupt 385 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_384 ,Interrupt 384 Priority"
line.long 0x4 "IPR97,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_391 ,Interrupt 391 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_390 ,Interrupt 390 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_389 ,Interrupt 389 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_388 ,Interrupt 388 Priority"
line.long 0x8 "IPR98,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_395 ,Interrupt 395 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_394 ,Interrupt 394 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_393 ,Interrupt 393 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_392 ,Interrupt 392 Priority"
line.long 0xC "IPR99,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_399 ,Interrupt 399 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_398 ,Interrupt 398 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_397 ,Interrupt 397 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_396 ,Interrupt 396 Priority"
line.long 0x10 "IPR100,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_403 ,Interrupt 403 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_402 ,Interrupt 402 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_401 ,Interrupt 401 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_400 ,Interrupt 400 Priority"
line.long 0x14 "IPR101,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_407 ,Interrupt 407 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_406 ,Interrupt 406 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_405 ,Interrupt 405 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_404 ,Interrupt 404 Priority"
line.long 0x18 "IPR102,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_411 ,Interrupt 411 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_410 ,Interrupt 410 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_409 ,Interrupt 409 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_408 ,Interrupt 408 Priority"
line.long 0x1C "IPR103,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_415 ,Interrupt 415 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_414 ,Interrupt 414 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_413 ,Interrupt 413 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_412 ,Interrupt 412 Priority"
else
hgroup.long 0x580++0x1F
hide.long 0x0 "IPR96,Interrupt Priority Register"
hide.long 0x4 "IPR97,Interrupt Priority Register"
hide.long 0x8 "IPR98,Interrupt Priority Register"
hide.long 0xC "IPR99,Interrupt Priority Register"
hide.long 0x10 "IPR100,Interrupt Priority Register"
hide.long 0x14 "IPR101,Interrupt Priority Register"
hide.long 0x18 "IPR102,Interrupt Priority Register"
hide.long 0x1C "IPR103,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x5A0++0x1F
line.long 0x0 "IPR104,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_419 ,Interrupt 419 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_418 ,Interrupt 418 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_417 ,Interrupt 417 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_416 ,Interrupt 416 Priority"
line.long 0x4 "IPR105,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_423 ,Interrupt 423 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_422 ,Interrupt 422 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_421 ,Interrupt 421 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_420 ,Interrupt 420 Priority"
line.long 0x8 "IPR106,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_427 ,Interrupt 427 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_426 ,Interrupt 426 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_425 ,Interrupt 425 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_424 ,Interrupt 424 Priority"
line.long 0xC "IPR107,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_431 ,Interrupt 431 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_430 ,Interrupt 430 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_429 ,Interrupt 429 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_428 ,Interrupt 428 Priority"
line.long 0x10 "IPR108,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_435 ,Interrupt 435 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_434 ,Interrupt 434 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_433 ,Interrupt 433 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_432 ,Interrupt 432 Priority"
line.long 0x14 "IPR109,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_439 ,Interrupt 439 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_438 ,Interrupt 438 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_437 ,Interrupt 437 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_436 ,Interrupt 436 Priority"
line.long 0x18 "IPR110,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_443 ,Interrupt 443 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_442 ,Interrupt 442 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_441 ,Interrupt 441 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_440 ,Interrupt 440 Priority"
line.long 0x1C "IPR111,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_447 ,Interrupt 447 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_446 ,Interrupt 446 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_445 ,Interrupt 445 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_444 ,Interrupt 444 Priority"
else
hgroup.long 0x5A0++0x1F
hide.long 0x0 "IPR104,Interrupt Priority Register"
hide.long 0x4 "IPR105,Interrupt Priority Register"
hide.long 0x8 "IPR106,Interrupt Priority Register"
hide.long 0xC "IPR107,Interrupt Priority Register"
hide.long 0x10 "IPR108,Interrupt Priority Register"
hide.long 0x14 "IPR109,Interrupt Priority Register"
hide.long 0x18 "IPR110,Interrupt Priority Register"
hide.long 0x1C "IPR111,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x5C0++0x1F
line.long 0x0 "IPR112,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_451 ,Interrupt 451 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_450 ,Interrupt 450 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_449 ,Interrupt 449 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_448 ,Interrupt 448 Priority"
line.long 0x4 "IPR113,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_455 ,Interrupt 455 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_454 ,Interrupt 454 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_453 ,Interrupt 453 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_452 ,Interrupt 452 Priority"
line.long 0x8 "IPR114,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_459 ,Interrupt 459 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_458 ,Interrupt 458 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_457 ,Interrupt 457 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_456 ,Interrupt 456 Priority"
line.long 0xC "IPR115,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_463 ,Interrupt 463 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_462 ,Interrupt 462 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_461 ,Interrupt 461 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_460 ,Interrupt 460 Priority"
line.long 0x10 "IPR116,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_467 ,Interrupt 467 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_466 ,Interrupt 466 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_465 ,Interrupt 465 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_464 ,Interrupt 464 Priority"
line.long 0x14 "IPR117,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_471 ,Interrupt 471 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_470 ,Interrupt 470 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_469 ,Interrupt 469 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_468 ,Interrupt 468 Priority"
line.long 0x18 "IPR118,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_475 ,Interrupt 475 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_474 ,Interrupt 474 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_473 ,Interrupt 473 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_472 ,Interrupt 472 Priority"
line.long 0x1C "IPR119,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_479 ,Interrupt 479 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_478 ,Interrupt 478 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_477 ,Interrupt 477 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_476 ,Interrupt 476 Priority"
else
hgroup.long 0x5C0++0x1F
hide.long 0x0 "IPR112,Interrupt Priority Register"
hide.long 0x4 "IPR113,Interrupt Priority Register"
hide.long 0x8 "IPR114,Interrupt Priority Register"
hide.long 0xC "IPR115,Interrupt Priority Register"
hide.long 0x10 "IPR116,Interrupt Priority Register"
hide.long 0x14 "IPR117,Interrupt Priority Register"
hide.long 0x18 "IPR118,Interrupt Priority Register"
hide.long 0x1C "IPR119,Interrupt Priority Register"
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
sif (CORENAME()=="CORTEXM33F")
tree "Floating-point Unit (FPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 8.
group.long 0xF34++0x0B
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
bitfld.long 0x00 29. " LSPENS ,This bit controls whether the LSPEN bit is writeable from the Non-secure state" "Writeable,Write ignored"
newline
bitfld.long 0x00 28. " CLRONRET ,Clear floating point caller saved registers on exception return" "Disabled,Enabled"
bitfld.long 0x00 27. " CLRONRETS ,Clear on return Secure only" "Both states,Secure only"
bitfld.long 0x00 26. " TS ,Treat as Secure" "Disabled,Enabled"
newline
bitfld.long 0x00 10. " UFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the UsageFault exception to pending" "Not able,Able"
bitfld.long 0x00 9. " SPLIMVIOL ,Indicates whether the FP context violates the stack pointer limit that was active when lazy state preservation was activated" "Low,High"
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
newline
bitfld.long 0x00 7. " SFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the SecureFault exception to pending" "Not able,Able"
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
newline
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
bitfld.long 0x00 2. " S ,Indicates the FP context belongs to the specified security state" "Non-secure,Secure"
newline
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
newline
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
rgroup.long 0xF40++0x0B
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
newline
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
newline
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Fully denormalized,?..."
line.long 0x08 "MVFR2,Media and FP Feature Register 2"
bitfld.long 0x08 4.--7. " VFP_MISC ,Indicates the hardware support for FP miscellaneous features" "Not supported,,,,Supported,?..."
width 0xB
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
endif
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 13.
group.long 0xD30++0x03
line.long 0x00 "DFSR,Debug Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
newline
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
newline
hgroup.long 0xDF0++0x03
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
in
newline
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write"
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register"
group.long 0xDF8++0x03
line.long 0x00 "DCRDR,Debug Core Register Data Register"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
newline
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
newline
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
else
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
newline
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
newline
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
endif
newline
group.long 0xE04++0x07
line.long 0x00 "DAUTHCTRL,Debug Authentication Control Register"
bitfld.long 0x00 3. " INTSPNIDEN ,Internal secure non-invasive debug enable" "Disabled,Enabled"
bitfld.long 0x00 2. " SPNIDENSEL ,Secure non-invasive debug enable select.Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure non-invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPNIDEN"
bitfld.long 0x00 1. " INTSPIDEN ,Internal secure invasive debug enable" "Disabled,Enabled"
bitfld.long 0x00 0. " SPIDENSEL ,Secure invasive debug enable select. Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPIDEN"
line.long 0x04 "DSCSR,Debug Security Control and Status Register"
bitfld.long 0x04 16. " CDS ,This field indicates the current security state of the processor" "Non-secure,Secure"
bitfld.long 0x04 1. " SBRSEL ,Secure banked register select" "Non-secure,Secure"
bitfld.long 0x04 0. " SBRSELEN ,Secure banked register select enable" "Disabled,Enabled"
rgroup.long 0xFB8++0x03
line.long 0x00 "DAUTHSTATUS,Debug Authentication Status Register"
bitfld.long 0x00 7. " SNI ,Secure non-invasive debug implemented" ",Implemented"
bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enabled" "0,1"
bitfld.long 0x00 5. " SI ,Secure invasive debug features implemented" ",Implemented"
bitfld.long 0x00 4. " SE ,Secure invasive debug enabled" "0,1"
newline
bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implemented" ",Implemented"
bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enabled" "0,1"
bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implemented" ",Implemented"
bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enabled" "0,1"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Flash Patch and Breakpoint Unit (FPB)"
sif COMPonent.AVAILABLE("FPB")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
width 12.
group.long 0x00++0x03
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Reserved,Version 2,?..."
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,?..."
rbitfld.long 0x00 8.--11. " NUM_LIT ,Number of literal comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
textline " "
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x04))&0x20000000)==0x20000000)
rgroup.long 0x04++0x03
line.long 0x00 "FP_REMAP,Flash Patch Remap Register"
bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported"
hexmask.long 0x00 5.--28. 0x20 " REMAP ,Remap address"
else
rgroup.long 0x04++0x03
line.long 0x00 "FP_REMAP,Flash Patch Remap Register"
bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
tree "CoreSight Identification Registers"
width 12.
rgroup.long 0xFCC++0x03
line.long 0x00 "FP_DEVTYPE,FPB CoreSight Device Type Register"
hexmask.long.byte 0x00 4.--7. 1. " SUB ,Sub-type"
hexmask.long.byte 0x00 0.--3. 1. " MAJOR ,Major type"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xFBC))&0x100000)==0x100000)
rgroup.long 0xFBC++0x03
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
else
rgroup.long 0xFBC++0x03
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
endif
rgroup.long 0xFE0++0x0F
line.long 0x00 "FP_PIDR0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "FP_PIDR1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "FP_PIDR2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0C "FP_PIDR3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "FP_PIDR4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "FP_CIDR0,Component ID0 (Preamble)"
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
line.long 0x04 "FP_CIDR1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
line.long 0x08 "FP_CIDR2,Component ID2"
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
line.long 0x0c "FP_CIDR3,Component ID3"
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
tree.end
width 0x0b
else
newline
textline "FPB component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 16.
group.long 0x00++0x03
line.long 0x00 "DWT_CTRL,Control Register"
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,?..."
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
textline " "
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
bitfld.long 0x00 23. " CYCDISS ,Controls whether the cycle counter is prevented from incrementing while the PE is in Secure state" "No,Yes"
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
textline " "
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
textline " "
bitfld.long 0x00 12. " PCSAMPLENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
textline " "
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x1000000)==0x0000000)
group.long 0x04++0x03
line.long 0x00 "DWT_CYCCNT,Cycle Count register"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x2000000)==0x0000000)
group.long 0x08++0x17
line.long 0x00 "DWT_CPICNT,CPI Count register"
hexmask.long.byte 0x00 0.--7. 1. " CPICNT ,Base instruction overhead counter"
line.long 0x04 "DWT_EXCCNT,Exception Overhead Count Register"
hexmask.long.byte 0x04 0.--7. 1. " EXCCNT ,The exception overhead counter"
line.long 0x08 "DWT_SLEEPCNT,Sleep Count Register"
hexmask.long.byte 0x08 0.--7. 1. " SLEEPCNT ,Sleep Counter"
line.long 0x10 "DWT_LSUCNT,LSU Count Register"
hexmask.long.byte 0x10 0.--7. 1. " LSUCNT ,Load-store overhead counter"
line.long 0x14 "DWT_FOLDCNT,Folded-instruction Count register"
hexmask.long.byte 0x14 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
endif
rgroup.long 0x1C++0x03
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
textline " "
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)==0x1)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x4)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xC)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xF)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
else
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
endif
group.long (0x20+0x08)++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Register 0"
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline " "
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)==0x1)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x4)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xC)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xF)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
else
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
endif
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Register 1"
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline " "
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)==0x1)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x4)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xC)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xF)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
else
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
endif
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Register 2"
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline " "
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)==0x1)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x4)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xC)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xF)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
else
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
endif
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Register 3"
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline " "
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
tree "CoreSight Identification Registers"
width 13.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xFBC))&0x100000)==0x100000)
rgroup.long 0xFBC++0x03
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
else
rgroup.long 0xFBC++0x03
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
endif
rgroup.long 0xFCC++0x03
line.long 0x00 "DWT_DEVTYPE,Device Type Identifier register"
hexmask.long.byte 0x00 4.--7. 1. " SUB ,Sub-type"
hexmask.long.byte 0x00 0.--3. 1. " MAJOR ,Major type"
rgroup.long 0xFE0++0x0F
line.long 0x00 "DWT_PIDR0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "DWT_PIDR1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "DWT_PIDR2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "DWT_PIDR3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "DWT_PIDR4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "DWT_CIDR0,Component ID0 (Preamble)"
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
line.long 0x04 "DWT_CIDR1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
line.long 0x08 "DWT_CIDR2,Component ID2"
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
line.long 0x0c "DWT_CIDR3,Component ID3"
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
tree.end
width 0x0b
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
autoindent.on center tree
tree "ADC (Analog to digital converter)"
tree "ADC0"
base ad:0x40012400
group.long 0x00++0x03
line.long 0x00 "STAT,status register"
bitfld.long 0x00 31. "WDE2,Analog watchdog 2 event flag" "0,1"
bitfld.long 0x00 30. "WDE1,Analog watchdog 1 event flag" "0,1"
bitfld.long 0x00 4. "STRC,Start flag of regular channel group" "0,1"
bitfld.long 0x00 3. "STIC,Start flag of inserted channel group" "0,1"
newline
bitfld.long 0x00 2. "EOIC,End of inserted group conversion flag" "0,1"
bitfld.long 0x00 1. "EOC,End of group conversion flag" "0,1"
bitfld.long 0x00 0. "WDE0,Analog watchdog event flag" "0,1"
group.long 0x04++0x03
line.long 0x00 "CTL0,control register 0"
bitfld.long 0x00 31. "WDE2IE,Interrupt enable for WDE2" "0,1"
bitfld.long 0x00 30. "WDE1IE,Interrupt enable for WDE1" "0,1"
bitfld.long 0x00 23. "RWD0EN,Regular channel analog watchdog 0 enable" "0,1"
bitfld.long 0x00 22. "IWD0EN,Inserted channel analog watchdog 0 enable" "0,1"
newline
bitfld.long 0x00 16.--19. "SYNCM,sync mode selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 13.--15. "DISNUM,Number of conversions in discontinuous mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12. "DISIC,Discontinuous mode on inserted channels" "0,1"
bitfld.long 0x00 11. "DISRC,Discontinuous mode on regular channels" "0,1"
newline
bitfld.long 0x00 10. "ICA,Inserted channel group convert automatically" "0,1"
bitfld.long 0x00 9. "WD0SC,When in scan mode analog watchdog 0 is effective on a single channel" "0,1"
bitfld.long 0x00 8. "SM,Scan mode" "0,1"
bitfld.long 0x00 7. "EOICIE,Interrupt enable for EOIC" "0,1"
newline
bitfld.long 0x00 6. "WDE0IE,Interrupt enable for WDE0" "0,1"
bitfld.long 0x00 5. "EOCIE,Interrupt enable for EOC" "0,1"
bitfld.long 0x00 0.--4. "WD0CHSEL,Analog watchdog 0 channel select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x08++0x03
line.long 0x00 "CTL1,control register 1"
bitfld.long 0x00 31. "ETSRC_3,The third bit of ETSRC" "0,1"
bitfld.long 0x00 30. "ETSIC_3,The third bit of ETSIC" "0,1"
bitfld.long 0x00 23. "TSVREN,Channel 16 and 17 enable of ADC0" "0,1"
bitfld.long 0x00 22. "SWRCST,Start on regular channel" "0,1"
newline
bitfld.long 0x00 21. "SWICST,Start on inserted channel" "0,1"
bitfld.long 0x00 20. "ETERC,External trigger enable for regular channel" "0,1"
bitfld.long 0x00 17.--19. "ETSRC,External trigger select for regular channel" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 15. "ETEIC,External trigger enable for inserted channel" "0,1"
newline
bitfld.long 0x00 12.--14. "ETSIC,External trigger select for inserted channel" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 11. "DAL,Data alignment" "0,1"
bitfld.long 0x00 8. "DMA,DMA request enable" "0,1"
bitfld.long 0x00 4.--6. "CALNUM,Calibration Times" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3. "RSTCLB,Reset calibration" "0,1"
bitfld.long 0x00 2. "CLB,ADC calibration" "0,1"
bitfld.long 0x00 1. "CTN,Continuous mode" "0,1"
bitfld.long 0x00 0. "ADCON,ADC on" "0,1"
group.long 0x0C++0x03
line.long 0x00 "SAMPT0,Sample time register 0"
bitfld.long 0x00 21.--23. "SPT17,Channel 17 sample time selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "SPT16,Channel 16 sample time selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 15.--17. "SPT15,Channel 15 sample time selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "SPT14,Channel 14 sample time selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "SPT13,Channel 13 sample time selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "SPT12,Channel 12 sample time selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3.--5. "SPT11,Channel 11 sample time selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "SPT10,Channel 10 sample time selection" "0,1,2,3,4,5,6,7"
group.long 0x10++0x03
line.long 0x00 "SAMPT1,Sample time register 1"
bitfld.long 0x00 27.--29. "SPT9,Channel 9 sample time selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "SPT8,Channel 8 sample time selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 21.--23. "SPT7,Channel 7 sample time selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "SPT6,Channel 6 sample time selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "SPT5,Channel 5 sample time selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "SPT4,Channel 4 sample time selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9.--11. "SPT3,Channel 3 sample time selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "SPT2,Channel 2 sample time selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "SPT1,Channel 1 sample time selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "SPT0,Channel 0 sample time selection" "0,1,2,3,4,5,6,7"
group.long 0x14++0x03
line.long 0x00 "IOFF0,Inserted channel data offset register 0"
hexmask.long.word 0x00 0.--11. 1. "IOFF,Data offset for inserted channel 0"
group.long 0x18++0x03
line.long 0x00 "IOFF1,Inserted channel data offset register 1"
hexmask.long.word 0x00 0.--11. 1. "IOFF,Data offset for inserted channel 1"
group.long 0x1C++0x03
line.long 0x00 "IOFF2,Inserted channel data offset register 2"
hexmask.long.word 0x00 0.--11. 1. "IOFF,Data offset for inserted channel 2"
group.long 0x20++0x03
line.long 0x00 "IOFF3,Inserted channel data offset register 3"
hexmask.long.word 0x00 0.--11. 1. "IOFF,Data offset for inserted channel 3"
group.long 0x24++0x03
line.long 0x00 "WDHT0,watchdog higher threshold register 0"
hexmask.long.word 0x00 0.--11. 1. "WDHT0,Analog watchdog 0 higher threshold"
group.long 0x28++0x03
line.long 0x00 "WDLT0,watchdog lower threshold register"
hexmask.long.word 0x00 0.--11. 1. "WDLT0,Analog watchdog 0 lower threshold"
group.long 0x2C++0x03
line.long 0x00 "RSQ0,regular sequence register 0"
bitfld.long 0x00 20.--23. "RL,Regular channel group length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 15.--19. "RSQ15,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10.--14. "RSQ14,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5.--9. "RSQ13,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--4. "RSQ12,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x30++0x03
line.long 0x00 "RSQ1,regular sequence register 1"
bitfld.long 0x00 25.--29. "RSQ11,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20.--24. "RSQ10,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 15.--19. "RSQ9,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10.--14. "RSQ8,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "RSQ7,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "RSQ6,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x34++0x03
line.long 0x00 "RSQ2,regular sequence register 2"
bitfld.long 0x00 25.--29. "RSQ5,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20.--24. "RSQ4,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 15.--19. "RSQ3,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10.--14. "RSQ2,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "RSQ1,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "RSQ0,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x38++0x03
line.long 0x00 "ISQ,Inserted sequence register"
bitfld.long 0x00 20.--21. "IL,Inserted channel group length" "0,1,2,3"
bitfld.long 0x00 15.--19. "ISQ3,4th conversion in inserted sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10.--14. "ISQ2,3rd conversion in inserted sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5.--9. "ISQ1,2nd conversion in inserted sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--4. "ISQ0,1st conversion in inserted sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
rgroup.long ($2+0x3C)++0x03
line.long 0x00 "IDATA$1,Inserted data register $1"
hexmask.long.word 0x00 0.--15. 1. "IDATAn,Inserted number n conversion data"
repeat.end
rgroup.long 0x4C++0x03
line.long 0x00 "RDATA,regular data register"
hexmask.long.word 0x00 16.--31. 1. "ADC1RDTR,ADCegular channel data"
hexmask.long.word 0x00 0.--15. 1. "RDATA,Regular channel data"
group.long 0x80++0x03
line.long 0x00 "OVSAMPCTL,Oversample control register"
bitfld.long 0x00 12.--13. "DRES,ADC resolution" "0,1,2,3"
bitfld.long 0x00 9. "TOVS,Triggered Oversampling" "0,1"
bitfld.long 0x00 5.--8. "OVSS,Oversampling shift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 2.--4. "OVSR,Oversampling ratio" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "OVSEN,Oversampling Enable" "0,1"
group.long 0xA0++0x03
line.long 0x00 "WD1SR,Watchdog 1 Channel Selection Register"
hexmask.long.tbyte 0x00 0.--17. 1. "AWD1CS,Analog watchdog 1 channel selection"
group.long 0xA4++0x03
line.long 0x00 "WD2SR,Watchdog 2 Channel Selection Register"
hexmask.long.tbyte 0x00 0.--17. 1. "AWD2CS,Analog watchdog 2 channel selection"
group.long 0xA8++0x03
line.long 0x00 "WDT1,Watchdog threshold register 1"
hexmask.long.byte 0x00 16.--23. 1. "WDHT1,Analog watchdog 1 high threshold"
hexmask.long.byte 0x00 0.--7. 1. "WDLT1,Analog watchdog 1 low threshold"
group.long 0xAC++0x03
line.long 0x00 "WDT2,Watchdog threshold register 2"
hexmask.long.byte 0x00 16.--23. 1. "WDHT2,Analog watchdog 2 high threshold"
hexmask.long.byte 0x00 0.--7. 1. "WDLT2,Analog watchdog 2 low threshold"
group.long 0xB0++0x03
line.long 0x00 "DIFCTL,Differential mode control register"
rbitfld.long 0x00 15.--17. "DIFCTL_17_15,Differential mode for channel 17 to 15" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 0.--14. 1. "DIFCTL_14_0,Differential mode for channel 14 to 0"
tree.end
repeat 2. (list 1. 2.) (list ad:0x40012800 ad:0x40013C00)
tree "ADC$1"
base $2
group.long 0x00++0x03
line.long 0x00 "STAT,status register"
bitfld.long 0x00 31. "WDE2,Analog watchdog 2 event flag" "0,1"
bitfld.long 0x00 30. "WDE1,Analog watchdog 1 event flag" "0,1"
bitfld.long 0x00 4. "STRC,Start flag of regular channel group" "0,1"
bitfld.long 0x00 3. "STIC,Start flag of inserted channel group" "0,1"
newline
bitfld.long 0x00 2. "EOIC,End of inserted group conversion flag" "0,1"
bitfld.long 0x00 1. "EOC,End of group conversion flag" "0,1"
bitfld.long 0x00 0. "WDE0,Analog watchdog event flag" "0,1"
group.long 0x04++0x03
line.long 0x00 "CTL0,control register 0"
bitfld.long 0x00 31. "WDE2IE,Interrupt enable for WDE2" "0,1"
bitfld.long 0x00 30. "WDE1IE,Interrupt enable for WDE1" "0,1"
bitfld.long 0x00 23. "RWD0EN,Regular channel analog watchdog 0 enable" "0,1"
bitfld.long 0x00 22. "IWD0EN,Inserted channel analog watchdog 0 enable" "0,1"
newline
bitfld.long 0x00 13.--15. "DISNUM,Number of conversions in discontinuous mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12. "DISIC,Discontinuous mode on inserted channels" "0,1"
bitfld.long 0x00 11. "DISRC,Discontinuous mode on regular channels" "0,1"
bitfld.long 0x00 10. "ICA,Inserted channel group convert automatically" "0,1"
newline
bitfld.long 0x00 9. "WD0SC,When in scan mode analog watchdog 0 is effective on a single channel" "0,1"
bitfld.long 0x00 8. "SM,Scan mode" "0,1"
bitfld.long 0x00 7. "EOICIE,Interrupt enable for EOIC" "0,1"
bitfld.long 0x00 6. "WDE0IE,Interrupt enable for WDE0" "0,1"
newline
bitfld.long 0x00 5. "EOCIE,Interrupt enable for EOC" "0,1"
bitfld.long 0x00 0.--4. "WD0CHSEL,Analog watchdog 0 channel select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x08++0x03
line.long 0x00 "CTL1,control register 1"
bitfld.long 0x00 31. "ETSRC_3,The third bit of ETSRC" "0,1"
bitfld.long 0x00 30. "ETSIC_3,The third bit of ETSIC" "0,1"
bitfld.long 0x00 23. "TSVREN,Channel 16 and 17 enable of ADC0" "0,1"
bitfld.long 0x00 22. "SWRCST,Start on regular channel" "0,1"
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bitfld.long 0x00 21. "SWICST,Start on inserted channel" "0,1"
bitfld.long 0x00 20. "ETERC,External trigger enable for regular channel" "0,1"
bitfld.long 0x00 17.--19. "ETSRC,External trigger select for regular channel" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 15. "ETEIC,External trigger enable for inserted channel" "0,1"
newline
bitfld.long 0x00 12.--14. "ETSIC,External trigger select for inserted channel" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 11. "DAL,Data alignment" "0,1"
bitfld.long 0x00 8. "DMA,DMA request enable" "0,1"
bitfld.long 0x00 4.--6. "CALNUM,Calibration Times" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3. "RSTCLB,Reset calibration" "0,1"
bitfld.long 0x00 2. "CLB,ADC calibration" "0,1"
bitfld.long 0x00 1. "CTN,Continuous mode" "0,1"
bitfld.long 0x00 0. "ADCON,ADC on" "0,1"
group.long 0x0C++0x03
line.long 0x00 "SAMPT0,Sample time register 0"
bitfld.long 0x00 21.--23. "SPT17,Channel 17 sample time selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "SPT16,Channel 16 sample time selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 15.--17. "SPT15,Channel 15 sample time selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "SPT14,Channel 14 sample time selection" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 9.--11. "SPT13,Channel 13 sample time selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "SPT12,Channel 12 sample time selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3.--5. "SPT11,Channel 11 sample time selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "SPT10,Channel 10 sample time selection" "0,1,2,3,4,5,6,7"
group.long 0x10++0x03
line.long 0x00 "SAMPT1,Sample time register 1"
bitfld.long 0x00 27.--29. "SPT9,Channel 9 sample time selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "SPT8,Channel 8 sample time selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 21.--23. "SPT7,Channel 7 sample time selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "SPT6,Channel 6 sample time selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "SPT5,Channel 5 sample time selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "SPT4,Channel 4 sample time selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9.--11. "SPT3,Channel 3 sample time selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "SPT2,Channel 2 sample time selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "SPT1,Channel 1 sample time selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "SPT0,Channel 0 sample time selection" "0,1,2,3,4,5,6,7"
group.long 0x14++0x03
line.long 0x00 "IOFF0,Inserted channel data offset register 0"
hexmask.long.word 0x00 0.--11. 1. "IOFF,Data offset for inserted channel 0"
group.long 0x18++0x03
line.long 0x00 "IOFF1,Inserted channel data offset register 1"
hexmask.long.word 0x00 0.--11. 1. "IOFF,Data offset for inserted channel 1"
group.long 0x1C++0x03
line.long 0x00 "IOFF2,Inserted channel data offset register 2"
hexmask.long.word 0x00 0.--11. 1. "IOFF,Data offset for inserted channel 2"
group.long 0x20++0x03
line.long 0x00 "IOFF3,Inserted channel data offset register 3"
hexmask.long.word 0x00 0.--11. 1. "IOFF,Data offset for inserted channel 3"
group.long 0x24++0x03
line.long 0x00 "WDHT0,watchdog higher threshold register 0"
hexmask.long.word 0x00 0.--11. 1. "WDHT0,Analog watchdog 0 higher threshold"
group.long 0x28++0x03
line.long 0x00 "WDLT0,watchdog lower threshold register"
hexmask.long.word 0x00 0.--11. 1. "WDLT0,Analog watchdog 0 lower threshold"
group.long 0x2C++0x03
line.long 0x00 "RSQ0,regular sequence register 0"
bitfld.long 0x00 20.--23. "RL,Regular channel group length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 15.--19. "RSQ15,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10.--14. "RSQ14,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5.--9. "RSQ13,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--4. "RSQ12,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x30++0x03
line.long 0x00 "RSQ1,regular sequence register 1"
bitfld.long 0x00 25.--29. "RSQ11,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20.--24. "RSQ10,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 15.--19. "RSQ9,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10.--14. "RSQ8,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "RSQ7,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "RSQ6,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x34++0x03
line.long 0x00 "RSQ2,regular sequence register 2"
bitfld.long 0x00 25.--29. "RSQ5,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20.--24. "RSQ4,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 15.--19. "RSQ3,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10.--14. "RSQ2,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "RSQ1,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "RSQ0,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x38++0x03
line.long 0x00 "ISQ,Inserted sequence register"
bitfld.long 0x00 20.--21. "IL,Inserted channel group length" "0,1,2,3"
bitfld.long 0x00 15.--19. "ISQ3,4th conversion in inserted sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10.--14. "ISQ2,3rd conversion in inserted sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5.--9. "ISQ1,2nd conversion in inserted sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--4. "ISQ0,1st conversion in inserted sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
rgroup.long ($2+0x3C)++0x03
line.long 0x00 "IDATA$1,Inserted data register $1"
hexmask.long.word 0x00 0.--15. 1. "IDATAn,Inserted number n conversion data"
repeat.end
rgroup.long 0x4C++0x03
line.long 0x00 "RDATA,regular data register"
hexmask.long.word 0x00 16.--31. 1. "ADC1RDTR,ADCegular channel data"
hexmask.long.word 0x00 0.--15. 1. "RDATA,Regular channel data"
group.long 0x80++0x03
line.long 0x00 "OVSAMPCTL,Oversample control register"
bitfld.long 0x00 12.--13. "DRES,ADC resolution" "0,1,2,3"
bitfld.long 0x00 9. "TOVS,Triggered Oversampling" "0,1"
bitfld.long 0x00 5.--8. "OVSS,Oversampling shift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 2.--4. "OVSR,Oversampling ratio" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "OVSEN,Oversampling Enable" "0,1"
group.long 0xA0++0x03
line.long 0x00 "WD1SR,Watchdog 1 Channel Selection Register"
hexmask.long.tbyte 0x00 0.--17. 1. "AWD1CS,Analog watchdog 1 channel selection"
group.long 0xA4++0x03
line.long 0x00 "WD2SR,Watchdog 2 Channel Selection Register"
hexmask.long.tbyte 0x00 0.--17. 1. "AWD2CS,Analog watchdog 2 channel selection"
group.long 0xA8++0x03
line.long 0x00 "WDT1,Watchdog threshold register 1"
hexmask.long.byte 0x00 16.--23. 1. "WDHT1,Analog watchdog 1 high threshold"
hexmask.long.byte 0x00 0.--7. 1. "WDLT1,Analog watchdog 1 low threshold"
group.long 0xAC++0x03
line.long 0x00 "WDT2,Watchdog threshold register 2"
hexmask.long.byte 0x00 16.--23. 1. "WDHT2,Analog watchdog 2 high threshold"
hexmask.long.byte 0x00 0.--7. 1. "WDLT2,Analog watchdog 2 low threshold"
group.long 0xB0++0x03
line.long 0x00 "DIFCTL,Differential mode control register"
rbitfld.long 0x00 15.--17. "DIFCTL_17_15,Differential mode for channel 17 to 15" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 0.--14. 1. "DIFCTL_14_0,Differential mode for channel 14 to 0"
tree.end
repeat.end
tree.end
tree "AFIO (Alternate-function I/Os)"
base ad:0x40010000
group.long 0x00++0x03
line.long 0x00 "EC,Event control register"
bitfld.long 0x00 7. "EOE,Event output enable" "0,1"
bitfld.long 0x00 4.--6. "PORT,Event output port selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--3. "PIN,Event output pin selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x04++0x03
line.long 0x00 "PCF0,AFIO port configuration register 0"
bitfld.long 0x00 30. "PTP_PPS_REMAP,Ethernet PTP PPS remapping" "0,1"
bitfld.long 0x00 29. "TIMER1ITR0_REMAP,TIMER1 internal trigger 0 remapping" "0,1"
bitfld.long 0x00 28. "SPI2_REMAP,SPI2/I2S2 remapping" "0,1"
bitfld.long 0x00 24.--26. "SWJ_CFG,Serial wire JTAG configuration" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 23. "ENET_PHY_SEL,Ethernet MII or RMII PHY selection" "0,1"
bitfld.long 0x00 21. "ENET_REMAP,Ethernet MAC I/O remapping" "0,1"
bitfld.long 0x00 16. "TIMER4CH3_IREMAP,TIMER4 channel3 internal remapping" "0,1"
bitfld.long 0x00 15. "PD01_REMAP,Port D0/Port D1 mapping on OSC_IN/OSC_OUT" "0,1"
newline
bitfld.long 0x00 12. "TIMER3_REMAP,TIMER3 remapping" "0,1"
bitfld.long 0x00 10.--11. "TIMER2_REMAP,TIMER2 remapping" "0,1,2,3"
bitfld.long 0x00 8.--9. "TIMER1_REMAP,TIMER1 remapping" "0,1,2,3"
bitfld.long 0x00 6.--7. "TIMER0_REMAP,TIMER0 remapping" "0,1,2,3"
newline
bitfld.long 0x00 4.--5. "USART2_REMAP,USART2 remapping" "0,1,2,3"
bitfld.long 0x00 3. "USART1_REMAP,USART1 remapping" "0,1"
bitfld.long 0x00 2. "USART0_REMAP,USART0 remapping" "0,1"
bitfld.long 0x00 1. "I2C0_REMAP,I2C0 remapping" "0,1"
newline
bitfld.long 0x00 0. "SPI0_REMAP,SPI0 remapping" "0,1"
group.long 0x08++0x03
line.long 0x00 "EXTISS0,EXTI sources selection register 0"
bitfld.long 0x00 12.--15. "EXTI3_SS,EXTI 3 sources selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "EXTI2_SS,EXTI 2 sources selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "EXTI1_SS,EXTI 1 sources selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "EXTI0_SS,EXTI 0 sources selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x0C++0x03
line.long 0x00 "EXTISS1,EXTI sources selection register 1"
bitfld.long 0x00 12.--15. "EXTI7_SS,EXTI 7 sources selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "EXTI6_SS,EXTI 6 sources selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "EXTI5_SS,EXTI 5 sources selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "EXTI4_SS,EXTI 4 sources selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x03
line.long 0x00 "EXTISS2,EXTI sources selection register 2"
bitfld.long 0x00 12.--15. "EXTI11_SS,EXTI 11 sources selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "EXTI10_SS,EXTI 10 sources selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "EXTI9_SS,EXTI 9 sources selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "EXTI8_SS,EXTI 8 sources selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x14++0x03
line.long 0x00 "EXTISS3,EXTI sources selection register 3"
bitfld.long 0x00 12.--15. "EXTI15_SS,EXTI 15 sources selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "EXTI14_SS,EXTI 14 sources selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "EXTI13_SS,EXTI 13 sources selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "EXTI12_SS,EXTI 12 sources selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C++0x03
line.long 0x00 "PCF1,AFIO port configuration register 1"
bitfld.long 0x00 11.--12. "CTC_REMAP,CTC remapping" "0,1,2,3"
bitfld.long 0x00 10. "EXMC_NADV,EXMC_NADV connect/disconnect" "0,1"
bitfld.long 0x00 9. "TIMER13_REMAP,TIMER13 remapping" "0,1"
bitfld.long 0x00 8. "TIMER12_REMAP,TIMER12 remapping" "0,1"
newline
bitfld.long 0x00 7. "TIMER10_REMAP,TIMER10 remapping" "0,1"
bitfld.long 0x00 6. "TIMER9_REMAP,TIMER9 remapping" "0,1"
bitfld.long 0x00 5. "TIMER8_REMAP,TIMER8 remapping" "0,1"
group.long 0x20++0x03
line.long 0x00 "CPSCTL,IO compensation control register"
rbitfld.long 0x00 8. "CPS_RDY,I/O compensation cell is really or not" "0,1"
bitfld.long 0x00 0. "CPS_EN,I/O compensation cell enable" "0,1"
group.long 0x3C++0x03
line.long 0x00 "PCFA,AFIO port configuration register A"
bitfld.long 0x00 30. "PA15_AFCFG,PA15 AF function configuration bit" "0,1"
bitfld.long 0x00 24.--25. "PA12_AFCFG,PA12 AF function configuration bitse" "0,1,2,3"
bitfld.long 0x00 22.--23. "PA11_AFCFG,PA11 AF function configuration bitse" "0,1,2,3"
bitfld.long 0x00 20.--21. "PA10_AFCFG,PA10 AF function configuration bitse" "0,1,2,3"
newline
bitfld.long 0x00 18.--19. "PA9_AFCFG,PA9 AF function configuration bitse" "0,1,2,3"
bitfld.long 0x00 16.--17. "PA8_AFCFG,PA8 AF function configuration bitse" "0,1,2,3"
bitfld.long 0x00 10. "PA5_AFCFG,PA5 AF function configuration bitse" "0,1"
bitfld.long 0x00 6. "PA3_AFCFG,PA3 AF function configuration bitse" "0,1"
newline
bitfld.long 0x00 4. "PA2_AFCFG,PA2 AF function configuration bitse" "0,1"
group.long 0x40++0x03
line.long 0x00 "PCFB,AFIO port configuration register B"
bitfld.long 0x00 30. "PB15_AFCFG,PB15 AF function configuration bit" "0,1"
bitfld.long 0x00 28.--29. "PB14_AFCFG,PB14 AF function configuration bit" "0,1,2,3"
bitfld.long 0x00 26.--27. "PB13_AFCFG,PB13 AF function configuration bit" "0,1,2,3"
bitfld.long 0x00 24.--25. "PB12_AFCFG,PB12 AF function configuration bitse" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "PB11_AFCFG,PB11 AF function configuration bitse" "0,1,2,3"
bitfld.long 0x00 20.--21. "PB10_AFCFG,PB10 AF function configuration bitse" "0,1,2,3"
bitfld.long 0x00 18.--19. "PB9_AFCFG,PB9 AF function configuration bitse" "0,1,2,3"
bitfld.long 0x00 16.--17. "PB8_AFCFG,PB8 AF function configuration bitse" "0,1,2,3"
newline
bitfld.long 0x00 14. "PB7_AFCFG,PB7 AF function configuration bitse" "0,1"
bitfld.long 0x00 12. "PB6_AFCFG,PB6 AF function configuration bitse" "0,1"
bitfld.long 0x00 10.--11. "PB5_AFCFG,PB5 AF function configuration bitse" "0,1,2,3"
bitfld.long 0x00 8.--9. "PB4_AFCFG,PB4 AF function configuration bitse" "0,1,2,3"
newline
bitfld.long 0x00 6. "PB3_AFCFG,PB3 AF function configuration bitse" "0,1"
bitfld.long 0x00 4.--5. "PB2_AFCFG,PB2 AF function configuration bitse" "0,1,2,3"
bitfld.long 0x00 2.--3. "PB1_AFCFG,PB1 AF function configuration bitse" "0,1,2,3"
bitfld.long 0x00 0. "PB0_AFCFG,PB0 AF function configuration bitse" "0,1"
group.long 0x44++0x03
line.long 0x00 "PCFC,AFIO port configuration register C"
bitfld.long 0x00 24. "PC12_AFCFG,PC12 AF function configuration bitse" "0,1"
bitfld.long 0x00 22.--23. "PC11_AFCFG,PC11 AF function configuration bitse" "0,1,2,3"
bitfld.long 0x00 20. "PC10_AFCFG,PC10 AF function configuration bitse" "0,1"
bitfld.long 0x00 18.--19. "PC9_AFCFG,PC9 AF function configuration bitse" "0,1,2,3"
newline
bitfld.long 0x00 16.--17. "PC8_AFCFG,PC8 AF function configuration bitse" "0,1,2,3"
bitfld.long 0x00 14.--15. "PC7_AFCFG,PC7 AF function configuration bitse" "0,1,2,3"
bitfld.long 0x00 12.--13. "PC6_AFCFG,PC6 AF function configuration bitse" "0,1,2,3"
bitfld.long 0x00 6. "PC3_AFCFG,PC3 AF function configuration bitse" "0,1"
newline
bitfld.long 0x00 4.--5. "PC2_AFCFG,PC2 AF function configuration bitse" "0,1,2,3"
bitfld.long 0x00 0. "PC0_AFCFG,PC0 AF function configuration bitse" "0,1"
group.long 0x48++0x03
line.long 0x00 "PCFD,AFIO port configuration register D"
bitfld.long 0x00 10. "PD5_AFCFG,PD5 AF function configuration bitse" "0,1"
bitfld.long 0x00 8. "PD4_AFCFG,PD4 AF function configuration bitse" "0,1"
group.long 0x4C++0x03
line.long 0x00 "PCFE,AFIO port configuration register E"
bitfld.long 0x00 26. "PE13_AFCFG,PE13 AF function configuration bitse" "0,1"
bitfld.long 0x00 24. "PE12_AFCFG,PE12 AF function configuration bitse" "0,1"
bitfld.long 0x00 22.--23. "PE11_AFCFG,PE11 AF function configuration bitse" "0,1,2,3"
bitfld.long 0x00 20. "PE10_AFCFG,PE10 AF function configuration bitse" "0,1"
newline
bitfld.long 0x00 18.--19. "PE9_AFCFG,PE9 AF function configuration bitse" "0,1,2,3"
bitfld.long 0x00 16.--17. "PE8_AFCFG,PE8 AF function configuration bitse" "0,1,2,3"
bitfld.long 0x00 2.--3. "PE1_AFCFG,PE1 AF function configuration bitse" "0,1,2,3"
bitfld.long 0x00 0.--1. "PE0_AFCFG,PE0 AF function configuration bitse" "0,1,2,3"
group.long 0x54++0x03
line.long 0x00 "PCFG,AFIO port configuration register G"
bitfld.long 0x00 28. "PG14_AFCFG,PG14 AF function configuration bitse" "0,1"
bitfld.long 0x00 26. "PG13_AFCFG,PG13 AF function configuration bitse" "0,1"
bitfld.long 0x00 24. "PG12_AFCFG,PG12 AF function configuration bitse" "0,1"
bitfld.long 0x00 22.--23. "PG11_AFCFG,PG11 AF function configuration bitse" "0,1,2,3"
newline
bitfld.long 0x00 20. "PG10_AFCFG,PG10 AF function configuration bitse" "0,1"
bitfld.long 0x00 18.--19. "PG9_AFCFG,PG9 AF function configuration bitse" "0,1,2,3"
bitfld.long 0x00 14.--15. "PG7_AFCFG,PG7 AF function configuration bitse" "0,1,2,3"
bitfld.long 0x00 12. "PG6_AFCFG,PG6 AF function configuration bitse" "0,1"
tree.end
tree "BKP (Backup registers)"
base ad:0x40006C00
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x3C 0x40 0x44 0x48 0x4C 0x50 )
group.word ($2+0x04)++0x01
line.word 0x00 "DATA$1,Backup data register $1"
hexmask.word 0x00 0.--15. 1. "DATA,Backup data"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.word ($2+0x58)++0x01
line.word 0x00 "DATA$1,Backup data register $1"
hexmask.word 0x00 0.--15. 1. "DATA,Backup data"
repeat.end
repeat 10. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 )
group.word ($2+0x98)++0x01
line.word 0x00 "DATA$1,Backup data register $1"
hexmask.word 0x00 0.--15. 1. "DATA,Backup data"
repeat.end
group.word 0x2C++0x01
line.word 0x00 "OCTL,RTC signal output control register"
bitfld.word 0x00 15. "CALDIR,RTC clock calibration direction" "0,1"
bitfld.word 0x00 14. "CCOSEL,RTC clock output selection" "0,1"
bitfld.word 0x00 9. "ROSEL,RTC output selection" "0,1"
bitfld.word 0x00 8. "ASOEN,RTC alarm or second signal output enable" "0,1"
newline
bitfld.word 0x00 7. "COEN,RTC clock calibration output enable" "0,1"
hexmask.word.byte 0x00 0.--6. 1. "RCCV,RTC clock calibration value"
group.word 0x30++0x01
line.word 0x00 "TPCTL,Tamper pin control register"
bitfld.word 0x00 1. "TPAL,TAMPER pin active level" "0,1"
bitfld.word 0x00 0. "TPEN,TAMPER detection enable" "0,1"
group.word 0x34++0x01
line.word 0x00 "TPCS,Tamper control and status register"
bitfld.word 0x00 9. "TIF,Tamper interrupt flag" "0,1"
bitfld.word 0x00 8. "TEF,Tamper event flag" "0,1"
bitfld.word 0x00 2. "TPIE,Tamper interrupt enable" "0,1"
bitfld.word 0x00 1. "TIR,Tamper interrupt reset" "0,1"
newline
bitfld.word 0x00 0. "TER,Tamper event reset" "0,1"
tree.end
sif cpuis("GD32E50*CL")
tree "CMP (Comparator)"
base ad:0x40017C00
group.long 0x20++0x03
line.long 0x00 "CMP1_CS,CMP1 control and status register"
bitfld.long 0x00 31. "CMP1LK,Comparator 1 lock" "0,1"
rbitfld.long 0x00 30. "CMP1O,CMP1 output" "0,1"
bitfld.long 0x00 22. "CMP1MSEL_3,CMP1_IM input selection" "0,1"
bitfld.long 0x00 18.--20. "CMP1BLK,CMP1 output blanking source" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15. "CMP1PL,Polarity of comparator 1 output" "0,1"
bitfld.long 0x00 10.--13. "CMP1OSEL,Comparator 1 output selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--6. "CMP1MSEL,Comparator 1 input selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "CMP1EN,Comparator 1 enable" "0,1"
group.long 0x28++0x03
line.long 0x00 "CMP3_CS,CMP3 control and status register"
bitfld.long 0x00 31. "CMP3LK,Comparator 3 lock" "0,1"
rbitfld.long 0x00 30. "CMP3O,CMP3 output" "0,1"
bitfld.long 0x00 22. "CMP3MSEL_3,CMP3_IM input selection" "0,1"
bitfld.long 0x00 18.--20. "CMP3BLK,CMP3 output blanking source" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15. "CMP3PL,Polarity of comparator 3 output" "0,1"
bitfld.long 0x00 10.--13. "CMP3OSEL,Comparator 3 output selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--6. "CMP3MSEL,Comparator 3 input selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "CMP3EN,Comparator 3 enable" "0,1"
group.long 0x30++0x03
line.long 0x00 "CMP5_CS,CMP5 control and status register"
bitfld.long 0x00 31. "CMP5LK,Comparator 5 lock" "0,1"
rbitfld.long 0x00 30. "CMP5O,CMP5 output" "0,1"
bitfld.long 0x00 22. "CMP5MSEL_3,CMP5_IM input selection" "0,1"
bitfld.long 0x00 18.--20. "CMP5BLK,CMP5 output blanking source" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15. "CMP5PL,Polarity of comparator 5 output" "0,1"
bitfld.long 0x00 10.--13. "CMP5OSEL,Comparator 5 output selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--6. "CMP5MSEL,Comparator 5 input selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "CMP5EN,Comparator 5 enable" "0,1"
tree.end
endif
tree "CRC (cyclic redundancy check calculation unit)"
base ad:0x40023000
group.long 0x00++0x03
line.long 0x00 "DATA,Data register"
hexmask.long 0x00 0.--31. 1. "DATA,CRC calculation result bits"
group.long 0x04++0x03
line.long 0x00 "FDATA,Free data register"
hexmask.long.byte 0x00 0.--7. 1. "FDATA,Free Data Register bits"
group.long 0x08++0x03
line.long 0x00 "CTL,Control register"
bitfld.long 0x00 7. "REV_O,Reverse output data value in bit order" "0,1"
bitfld.long 0x00 5.--6. "REV_I,Reverse type for input data" "0,1,2,3"
bitfld.long 0x00 3.--4. "PS,Size of polynomial" "0,1,2,3"
bitfld.long 0x00 0. "RST,reset bit" "0,1"
group.long 0x10++0x03
line.long 0x00 "IDATA,Initialization data register"
hexmask.long 0x00 0.--31. 1. "IDATA,Configurable initial CRC data value"
group.long 0x14++0x03
line.long 0x00 "POLY,Polynomial register"
hexmask.long 0x00 0.--31. 1. "POLY,User configurable polynomial value"
tree.end
tree "CTC (Clock trim controller)"
base ad:0x4000C800
group.long 0x00++0x03
line.long 0x00 "CTL0,Control register 0"
bitfld.long 0x00 8.--13. "TRIMVALUE,IRC48M trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 7. "SWREFPUL,Software reference source sync pulse" "0,1"
bitfld.long 0x00 6. "AUTOTRIM,Hardware automatically trim mode" "0,1"
bitfld.long 0x00 5. "CNTEN,CTC counter enable" "0,1"
newline
bitfld.long 0x00 3. "EREFIE,EREFIF interrupt enable" "0,1"
bitfld.long 0x00 2. "ERRIE,Error interrupt enable" "0,1"
bitfld.long 0x00 1. "CKWARNIE,Clock trim warning interrupt enable" "0,1"
bitfld.long 0x00 0. "CKOKIE,Clock trim ok interrupt enable" "0,1"
group.long 0x04++0x03
line.long 0x00 "CTL1,Control register 1"
bitfld.long 0x00 31. "REFPOL,Reference signal source polarity" "0,1"
bitfld.long 0x00 28.--29. "REFSEL,Reference signal source selection" "0,1,2,3"
bitfld.long 0x00 24.--26. "REFPSC,Reference signal source prescaler" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 16.--23. 1. "CKLIM,Clock trim base limit value"
newline
hexmask.long.word 0x00 0.--15. 1. "RLVALUE,CTC counter reload value"
rgroup.long 0x08++0x03
line.long 0x00 "STAT,Status register"
hexmask.long.word 0x00 16.--31. 1. "REFCAP,CTC counter capture when reference sync pulse"
bitfld.long 0x00 15. "REFDIR,CTC trim counter direction when reference sync pulse" "0,1"
bitfld.long 0x00 10. "TRIMERR,Trim value error bit" "0,1"
bitfld.long 0x00 9. "REFMISS,Reference sync pulse miss" "0,1"
newline
bitfld.long 0x00 8. "CKERR,Clock trim error bit" "0,1"
bitfld.long 0x00 3. "EREFIF,Expect reference interrupt flag" "0,1"
bitfld.long 0x00 2. "ERRIF,Error interrupt flag" "0,1"
bitfld.long 0x00 1. "CKWARNIF,Clock trim warning interrupt flag" "0,1"
newline
bitfld.long 0x00 0. "CKOKIF,Clock trim OK interrupt flag" "0,1"
wgroup.long 0x0C++0x03
line.long 0x00 "INTC,Interrupt clear register"
bitfld.long 0x00 3. "EREFIC,EREFIF interrupt clear bit" "0,1"
bitfld.long 0x00 2. "ERRIC,ERRIF interrupt clear bit" "0,1"
bitfld.long 0x00 1. "CKWARNIC,CKWARNIF interrupt clear bit" "0,1"
bitfld.long 0x00 0. "CKOKIC,CKOKIF interrupt clear bit" "0,1"
tree.end
tree "DAC (Digital-to-analog converter)"
base ad:0x40007400
group.long 0x00++0x03
line.long 0x00 "CTL0,control register 0"
bitfld.long 0x00 30. "DTSEL1_3,DAC_OUT1 trigger selection bit[3] refer to DTSEL1[2:0]" "0,1"
bitfld.long 0x00 29. "DDUDRIE1,DAC_OUT1 DMA underrun interrupt enable" "0,1"
bitfld.long 0x00 28. "DDMAEN1,DAC1 DMA enable" "0,1"
bitfld.long 0x00 24.--27. "DWBW1,DAC1 noise wave bit width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22.--23. "DWM1,DAC1 noise wave mode" "0,1,2,3"
bitfld.long 0x00 19.--21. "DTSEL1,DAC1 trigger selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18. "DTEN1,DAC1 trigger enable" "0,1"
bitfld.long 0x00 17. "DBOFF1,DAC1 output buffer turn off" "0,1"
newline
bitfld.long 0x00 16. "DEN1,DAC1 enable" "0,1"
bitfld.long 0x00 14. "DTSEL0_3,DAC_OUT0 trigger selection bit[3] refer to DTSEL0[2:0]" "0,1"
bitfld.long 0x00 13. "DDUDRIE0,DAC_OUT0 DMA underrun interrupt enable" "0,1"
bitfld.long 0x00 12. "DDMAEN0,DAC0 DMA enable" "0,1"
newline
bitfld.long 0x00 8.--11. "DWBW0,DAC0 noise wave bit width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6.--7. "DWM0,DAC0 noise wave mode" "0,1,2,3"
bitfld.long 0x00 3.--5. "DTSEL0,DAC0 trigger selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. "DTEN0,DAC0 trigger enable" "0,1"
newline
bitfld.long 0x00 1. "DBOFF0,DAC0 output buffer turn off" "0,1"
bitfld.long 0x00 0. "DEN0,DAC0 enable" "0,1"
wgroup.long 0x04++0x03
line.long 0x00 "SWT,software trigger register"
bitfld.long 0x00 1. "SWTR1,DAC1 software trigger" "0,1"
bitfld.long 0x00 0. "SWTR0,DAC0 software trigger" "0,1"
group.long 0x08++0x03
line.long 0x00 "OUT0_R12DH,DAC_OUT0 12-bit right-aligned data holding register"
hexmask.long.word 0x00 0.--11. 1. "OUT0_DH,DAC_OUT0 12-bit right-aligned data"
group.long 0x0C++0x03
line.long 0x00 "OUT0_L12DH,DAC_OUT0 12-bit left-aligned data holding register"
hexmask.long.word 0x00 4.--15. 1. "OUT0_DH,DAC_OUT0 12-bit left-aligned data"
group.long 0x10++0x03
line.long 0x00 "OUT0_R8DH,DAC_OUT0 8-bit right aligned data holding register"
hexmask.long.byte 0x00 0.--7. 1. "OUT0_DH,DAC_OUT0 8-bit right-aligned data"
group.long 0x14++0x03
line.long 0x00 "OUT1_R12DH,DAC_OUT1 12-bit right-aligned data holding register"
hexmask.long.word 0x00 0.--11. 1. "OUT1_DH,DAC_OUT1 12-bit right-aligned data"
group.long 0x18++0x03
line.long 0x00 "OUT1_L12DH,DAC_OUT1 12-bit left aligned data holding register"
hexmask.long.word 0x00 4.--15. 1. "OUT1_DH,DAC_OUT1 12-bit left-aligned data"
group.long 0x1C++0x03
line.long 0x00 "OUT1_R8DH,DAC_OUT1 8-bit right aligned data holding register"
hexmask.long.byte 0x00 0.--7. 1. "OUT1_DH,DAC_OUT1 8-bit right-aligned data"
group.long 0x20++0x03
line.long 0x00 "DACC_R12DH,DAC concurrent mode 12-bit right-aligned data holding register"
hexmask.long.word 0x00 16.--27. 1. "OUT1_DH,DAC_OUT1 12-bit right-aligned data"
hexmask.long.word 0x00 0.--11. 1. "OUT0_DH,DAC_OUT0 12-bit right-aligned data"
group.long 0x24++0x03
line.long 0x00 "DACC_L12DH,DAC concurrent mode 12-bit left aligned data holding register"
hexmask.long.word 0x00 20.--31. 1. "OUT1_DH,DAC_OUT1 12-bit left-aligned data"
hexmask.long.word 0x00 4.--15. 1. "OUT0_DH,DAC_OUT0 12-bit left-aligned data"
group.long 0x28++0x03
line.long 0x00 "DACC_R8DH,DAC concurrent mode 8-bit right aligned data holding register"
hexmask.long.byte 0x00 8.--15. 1. "OUT1_DH,DAC_OUT1 8-bit right-aligned data"
hexmask.long.byte 0x00 0.--7. 1. "OUT0_DH,DAC_OUT0 8-bit right-aligned data"
rgroup.long 0x2C++0x03
line.long 0x00 "DAC0_DO,DAC_OUT0 data output register"
hexmask.long.word 0x00 0.--11. 1. "OUT0_DO,DAC_OUT0 data output"
rgroup.long 0x30++0x03
line.long 0x00 "OUT1_DO,DAC_OUT1 data output register"
hexmask.long.word 0x00 0.--11. 1. "OUT1_DO,DAC_OUT1 data output"
group.long 0x34++0x03
line.long 0x00 "STAT0,DAC Status register 0"
bitfld.long 0x00 29. "DDUDR1,DAC_OUT1 DMA underrun flag" "0,1"
bitfld.long 0x00 13. "DDUDR0,DAC_OUT0 DMA underrun flag" "0,1"
group.long 0x80++0x03
line.long 0x00 "CTL1,DAC Control Register 1"
bitfld.long 0x00 18. "FIFOUDRIE1,DAC_OUT1 FIFO underflow interrupt enable" "0,1"
bitfld.long 0x00 17. "FIFOOVRIE1,DAC_OUT1 FIFO overflow interrupt enable" "0,1"
bitfld.long 0x00 16. "FIFOEN1,DAC_OUT1 data FIFO enable" "0,1"
bitfld.long 0x00 2. "FIFOUDRIE0,DAC_OUT0 FIFO underflow interrupt enable" "0,1"
newline
bitfld.long 0x00 1. "FIFOOVRIE0,DAC_OUT0 FIFO overflow interrupt enable" "0,1"
bitfld.long 0x00 0. "FIFOEN0,DAC_OUT0 data FIFO enable" "0,1"
group.long 0x84++0x03
line.long 0x00 "STAT1,DAC Status register 1"
rbitfld.long 0x00 20.--22. "FIFONUM1,Number of data in the DAC_OUT1 FIFO" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 19. "FIFOUDR1,DAC_OUT1 FIFO underflow flag" "0,1"
bitfld.long 0x00 18. "FIFOOVR1,DAC_OUT1 FIFO overflow flag" "0,1"
rbitfld.long 0x00 17. "FE1,DAC_OUT1 FIFO empty flag" "0,1"
newline
rbitfld.long 0x00 16. "FF1,DAC_OUT1 FIFO full flag" "0,1"
rbitfld.long 0x00 4.--6. "FIFONUM0,Number of data in the DAC_OUT0 FIFO" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "FIFOUDR0,DAC_OUT0 FIFO underflow flag" "0,1"
bitfld.long 0x00 2. "FIFOOVR0,DAC_OUT0 FIFO overflow flag" "0,1"
newline
rbitfld.long 0x00 1. "FE0,DAC_OUT0 FIFO empty flag" "0,1"
rbitfld.long 0x00 0. "FF0,DAC_OUT0 FIFO full flag" "0,1"
tree.end
tree "DBG (Debug support)"
base ad:0xE0044000
rgroup.long 0x00++0x03
line.long 0x00 "ID,ID code register"
hexmask.long 0x00 0.--31. 1. "ID_CODE,DBG ID code register"
group.long 0x04++0x03
line.long 0x00 "CTL0,Control register 0"
bitfld.long 0x00 31. "SHRTIMER_HOLD,SHRTIMER hold bit" "0,1"
bitfld.long 0x00 30. "TIMER10_HOLD,TIMER 10 hold bit" "0,1"
bitfld.long 0x00 29. "TIMER9_HOLD,TIMER 9 hold bit" "0,1"
bitfld.long 0x00 28. "TIMER8_HOLD,TIMER 8 hold bit" "0,1"
newline
bitfld.long 0x00 27. "TIMER13_HOLD,TIMER 13 hold bit" "0,1"
bitfld.long 0x00 26. "TIMER12_HOLD,TIMER 12 hold bit" "0,1"
bitfld.long 0x00 25. "TIMER11_HOLD,TIMER 11 hold bit" "0,1"
bitfld.long 0x00 22. "I2C2_HOLD,I2C2 hold bit" "0,1"
newline
bitfld.long 0x00 20. "TIMER6_HOLD,TIMER 6 hold bit" "0,1"
bitfld.long 0x00 19. "TIMER5_HOLD,TIMER 5 hold bit" "0,1"
bitfld.long 0x00 18. "TIMER4_HOLD,TIMER4_HOLD" "0,1"
bitfld.long 0x00 17. "TIMER7_HOLD,TIMER7_HOLD" "0,1"
newline
bitfld.long 0x00 16. "I2C1_HOLD,I2C1 hold bit" "0,1"
bitfld.long 0x00 15. "I2C0_HOLD,I2C0 hold bit" "0,1"
bitfld.long 0x00 13. "TIMER3_HOLD,TIMER 23 hold bit" "0,1"
bitfld.long 0x00 12. "TIMER2_HOLD,TIMER 2 hold bit" "0,1"
newline
bitfld.long 0x00 11. "TIMER1_HOLD,TIMER 1 hold bit" "0,1"
bitfld.long 0x00 10. "TIMER0_HOLD,TIMER 0 hold bit" "0,1"
bitfld.long 0x00 9. "WWDGT_HOLD,WWDGT hold bit" "0,1"
bitfld.long 0x00 8. "FWDGT_HOLD,FWDGT hold bit" "0,1"
newline
bitfld.long 0x00 6.--7. "TRACE_MODE,Trace pin allocation mode" "0,1,2,3"
bitfld.long 0x00 5. "TRACE_IOEN,Trace pin allocation enable" "0,1"
bitfld.long 0x00 2. "STB_HOLD,Standby mode hold register" "0,1"
bitfld.long 0x00 1. "DSLP_HOLD,Deep-sleep mode hold register" "0,1"
newline
bitfld.long 0x00 0. "SLP_HOLD,Sleep mode hold register" "0,1"
tree.end
tree "DMA (DMA controller)"
tree "DMA0"
base ad:0x40020000
rgroup.long 0x00++0x03
line.long 0x00 "INTF,Interrupt flag register"
bitfld.long 0x00 27. "ERRIF6,Error flag of channel 6" "0,1"
bitfld.long 0x00 26. "HTFIF6,Half transfer finish flag of channel 6" "0,1"
bitfld.long 0x00 25. "FTFIF6,Full Transfer finish flag of channe 6" "0,1"
bitfld.long 0x00 24. "GIF6,Global interrupt flag of channel 6" "0,1"
newline
bitfld.long 0x00 23. "ERRIF5,Error flag of channel 5" "0,1"
bitfld.long 0x00 22. "HTFIF5,Half transfer finish flag of channel 5" "0,1"
bitfld.long 0x00 21. "FTFIF5,Full Transfer finish flag of channe 5" "0,1"
bitfld.long 0x00 20. "GIF5,Global interrupt flag of channel 5" "0,1"
newline
bitfld.long 0x00 19. "ERRIF4,Error flag of channel 4" "0,1"
bitfld.long 0x00 18. "HTFIF4,Half transfer finish flag of channel 4" "0,1"
bitfld.long 0x00 17. "FTFIF4,Full Transfer finish flag of channe 4" "0,1"
bitfld.long 0x00 16. "GIF4,Global interrupt flag of channel 4" "0,1"
newline
bitfld.long 0x00 15. "ERRIF3,Error flag of channel 3" "0,1"
bitfld.long 0x00 14. "HTFIF3,Half transfer finish flag of channel 3" "0,1"
bitfld.long 0x00 13. "FTFIF3,Full Transfer finish flag of channe 3" "0,1"
bitfld.long 0x00 12. "GIF3,Global interrupt flag of channel 3" "0,1"
newline
bitfld.long 0x00 11. "ERRIF2,Error flag of channel 2" "0,1"
bitfld.long 0x00 10. "HTFIF2,Half transfer finish flag of channel 2" "0,1"
bitfld.long 0x00 9. "FTFIF2,Full Transfer finish flag of channe 2" "0,1"
bitfld.long 0x00 8. "GIF2,Global interrupt flag of channel 2" "0,1"
newline
bitfld.long 0x00 7. "ERRIF1,Error flag of channel 1" "0,1"
bitfld.long 0x00 6. "HTFIF1,Half transfer finish flag of channel 1" "0,1"
bitfld.long 0x00 5. "FTFIF1,Full Transfer finish flag of channe 1" "0,1"
bitfld.long 0x00 4. "GIF1,Global interrupt flag of channel 1" "0,1"
newline
bitfld.long 0x00 3. "ERRIF0,Error flag of channel 0" "0,1"
bitfld.long 0x00 2. "HTFIF0,Half transfer finish flag of channel 0" "0,1"
bitfld.long 0x00 1. "FTFIF0,Full Transfer finish flag of channe 0" "0,1"
bitfld.long 0x00 0. "GIF0,Global interrupt flag of channel 0" "0,1"
wgroup.long 0x04++0x03
line.long 0x00 "INTC,Interrupt flag clear register"
bitfld.long 0x00 27. "ERRIFC6,Clear bit for error flag of channel 6" "0,1"
bitfld.long 0x00 26. "HTFIFC6,Clear bit for half transfer finish flag of channel 6" "0,1"
bitfld.long 0x00 25. "FTFIFC6,Clear bit for full transfer finish flag of channel 6" "0,1"
bitfld.long 0x00 24. "GIFC6,Clear global interrupt flag of channel 6" "0,1"
newline
bitfld.long 0x00 23. "ERRIFC5,Clear bit for error flag of channel 5" "0,1"
bitfld.long 0x00 22. "HTFIFC5,Clear bit for half transfer finish flag of channel 5" "0,1"
bitfld.long 0x00 21. "FTFIFC5,Clear bit for full transfer finish flag of channel 5" "0,1"
bitfld.long 0x00 20. "GIFC5,Clear global interrupt flag of channel 5" "0,1"
newline
bitfld.long 0x00 19. "ERRIFC4,Clear bit for error flag of channel 4" "0,1"
bitfld.long 0x00 18. "HTFIFC4,Clear bit for half transfer finish flag of channel 4" "0,1"
bitfld.long 0x00 17. "FTFIFC4,Clear bit for full transfer finish flag of channel 4" "0,1"
bitfld.long 0x00 16. "GIFC4,Clear global interrupt flag of channel 4" "0,1"
newline
bitfld.long 0x00 15. "ERRIFC3,Clear bit for error flag of channel 3" "0,1"
bitfld.long 0x00 14. "HTFIFC3,Clear bit for half transfer finish flag of channel 3" "0,1"
bitfld.long 0x00 13. "FTFIFC3,Clear bit for full transfer finish flag of channel 3" "0,1"
bitfld.long 0x00 12. "GIFC3,Clear global interrupt flag of channel 3" "0,1"
newline
bitfld.long 0x00 11. "ERRIFC2,Clear bit for error flag of channel 2" "0,1"
bitfld.long 0x00 10. "HTFIFC2,Clear bit for half transfer finish flag of channel 2" "0,1"
bitfld.long 0x00 9. "FTFIFC2,Clear bit for full transfer finish flag of channel 2" "0,1"
bitfld.long 0x00 8. "GIFC2,Clear global interrupt flag of channel 2" "0,1"
newline
bitfld.long 0x00 7. "ERRIFC1,Clear bit for error flag of channel 1" "0,1"
bitfld.long 0x00 6. "HTFIFC1,Clear bit for half transfer finish flag of channel 1" "0,1"
bitfld.long 0x00 5. "FTFIFC1,Clear bit for full transfer finish flag of channel 1" "0,1"
bitfld.long 0x00 4. "GIFC1,Clear global interrupt flag of channel 1" "0,1"
newline
bitfld.long 0x00 3. "ERRIFC0,Clear bit for error flag of channel 0" "0,1"
bitfld.long 0x00 2. "HTFIFC0,Clear bit for half transfer finish flag of channel 0" "0,1"
bitfld.long 0x00 1. "FTFIFC0,Clear bit for full transfer finish flag of channel 0" "0,1"
bitfld.long 0x00 0. "GIFC0,Clear global interrupt flag of channel 0" "0,1"
group.long 0x08++0x03
line.long 0x00 "CH0CTL,Channel 0 control register"
bitfld.long 0x00 14. "M2M,Memory to Memory Mode" "0,1"
bitfld.long 0x00 12.--13. "PRIO,Priority level" "0,1,2,3"
bitfld.long 0x00 10.--11. "MWIDTH,Transfer data size of memory" "0,1,2,3"
bitfld.long 0x00 8.--9. "PWIDTH,Transfer data size of peripheral" "0,1,2,3"
newline
bitfld.long 0x00 7. "MNAGA,Next address generation algorithm of memory" "0,1"
bitfld.long 0x00 6. "PNAGA,Next address generation algorithm of peripheral" "0,1"
bitfld.long 0x00 5. "CMEN,Circular mode enable" "0,1"
bitfld.long 0x00 4. "DIR,Transfer direction" "0,1"
newline
bitfld.long 0x00 3. "ERRIE,Enable bit for channel error interrupt" "0,1"
bitfld.long 0x00 2. "HTFIE,Enable bit for channel half transfer finish interrupt" "0,1"
bitfld.long 0x00 1. "FTFIE,Enable bit for channel full transfer finish interrupt" "0,1"
bitfld.long 0x00 0. "CHEN,Channel enable" "0,1"
group.long 0x0C++0x03
line.long 0x00 "CH0CNT,Channel 0 counter register"
hexmask.long.word 0x00 0.--15. 1. "CNT,Transfer counter"
group.long 0x10++0x03
line.long 0x00 "CH0PADDR,Channel 0 peripheral base address register"
hexmask.long 0x00 0.--31. 1. "PADDR,Peripheral base address"
group.long 0x14++0x03
line.long 0x00 "CH0MADDR,Channel 0 memory base address register"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory base address"
group.long 0x1C++0x03
line.long 0x00 "CH1CTL,Channel 1 control register"
bitfld.long 0x00 14. "M2M,Memory to Memory Mode" "0,1"
bitfld.long 0x00 12.--13. "PRIO,Priority level" "0,1,2,3"
bitfld.long 0x00 10.--11. "MWIDTH,Transfer data size of memory" "0,1,2,3"
bitfld.long 0x00 8.--9. "PWIDTH,Transfer data size of peripheral" "0,1,2,3"
newline
bitfld.long 0x00 7. "MNAGA,Next address generation algorithm of memory" "0,1"
bitfld.long 0x00 6. "PNAGA,Next address generation algorithm of peripheral" "0,1"
bitfld.long 0x00 5. "CMEN,Circular mode enable" "0,1"
bitfld.long 0x00 4. "DIR,Transfer direction" "0,1"
newline
bitfld.long 0x00 3. "ERRIE,Enable bit for channel error interrupt" "0,1"
bitfld.long 0x00 2. "HTFIE,Enable bit for channel half transfer finish interrupt" "0,1"
bitfld.long 0x00 1. "FTFIE,Enable bit for channel full transfer finish interrupt" "0,1"
bitfld.long 0x00 0. "CHEN,Channel enable" "0,1"
group.long 0x20++0x03
line.long 0x00 "CH1CNT,Channel 1 counter register"
hexmask.long.word 0x00 0.--15. 1. "CNT,Transfer counter"
group.long 0x24++0x03
line.long 0x00 "CH1PADDR,Channel 1 peripheral base address register"
hexmask.long 0x00 0.--31. 1. "PADDR,Peripheral base address"
group.long 0x28++0x03
line.long 0x00 "CH1MADDR,Channel 1 memory base address register"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory base address"
group.long 0x30++0x03
line.long 0x00 "CH2CTL,Channel 2 control register"
bitfld.long 0x00 14. "M2M,Memory to Memory Mode" "0,1"
bitfld.long 0x00 12.--13. "PRIO,Priority level" "0,1,2,3"
bitfld.long 0x00 10.--11. "MWIDTH,Transfer data size of memory" "0,1,2,3"
bitfld.long 0x00 8.--9. "PWIDTH,Transfer data size of peripheral" "0,1,2,3"
newline
bitfld.long 0x00 7. "MNAGA,Next address generation algorithm of memory" "0,1"
bitfld.long 0x00 6. "PNAGA,Next address generation algorithm of peripheral" "0,1"
bitfld.long 0x00 5. "CMEN,Circular mode enable" "0,1"
bitfld.long 0x00 4. "DIR,Transfer direction" "0,1"
newline
bitfld.long 0x00 3. "ERRIE,Enable bit for channel error interrupt" "0,1"
bitfld.long 0x00 2. "HTFIE,Enable bit for channel half transfer finish interrupt" "0,1"
bitfld.long 0x00 1. "FTFIE,Enable bit for channel full transfer finish interrupt" "0,1"
bitfld.long 0x00 0. "CHEN,Channel enable" "0,1"
group.long 0x34++0x03
line.long 0x00 "CH2CNT,Channel 2 counter register"
hexmask.long.word 0x00 0.--15. 1. "CNT,Transfer counter"
group.long 0x38++0x03
line.long 0x00 "CH2PADDR,Channel 2 peripheral base address register"
hexmask.long 0x00 0.--31. 1. "PADDR,Peripheral base address"
group.long 0x3C++0x03
line.long 0x00 "CH2MADDR,Channel 2 memory base address register"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory base address"
group.long 0x44++0x03
line.long 0x00 "CH3CTL,Channel 3 control register"
bitfld.long 0x00 14. "M2M,Memory to Memory Mode" "0,1"
bitfld.long 0x00 12.--13. "PRIO,Priority level" "0,1,2,3"
bitfld.long 0x00 10.--11. "MWIDTH,Transfer data size of memory" "0,1,2,3"
bitfld.long 0x00 8.--9. "PWIDTH,Transfer data size of peripheral" "0,1,2,3"
newline
bitfld.long 0x00 7. "MNAGA,Next address generation algorithm of memory" "0,1"
bitfld.long 0x00 6. "PNAGA,Next address generation algorithm of peripheral" "0,1"
bitfld.long 0x00 5. "CMEN,Circular mode enable" "0,1"
bitfld.long 0x00 4. "DIR,Transfer direction" "0,1"
newline
bitfld.long 0x00 3. "ERRIE,Enable bit for channel error interrupt" "0,1"
bitfld.long 0x00 2. "HTFIE,Enable bit for channel half transfer finish interrupt" "0,1"
bitfld.long 0x00 1. "FTFIE,Enable bit for channel full transfer finish interrupt" "0,1"
bitfld.long 0x00 0. "CHEN,Channel enable" "0,1"
group.long 0x48++0x03
line.long 0x00 "CH3CNT,Channel 3 counter register"
hexmask.long.word 0x00 0.--15. 1. "CNT,Transfer counter"
group.long 0x4C++0x03
line.long 0x00 "CH3PADDR,Channel 3 peripheral base address register"
hexmask.long 0x00 0.--31. 1. "PADDR,Peripheral base address"
group.long 0x50++0x03
line.long 0x00 "CH3MADDR,Channel 3 memory base address register"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory base address"
group.long 0x58++0x03
line.long 0x00 "CH4CTL,Channel 4 control register"
bitfld.long 0x00 14. "M2M,Memory to Memory Mode" "0,1"
bitfld.long 0x00 12.--13. "PRIO,Priority level" "0,1,2,3"
bitfld.long 0x00 10.--11. "MWIDTH,Transfer data size of memory" "0,1,2,3"
bitfld.long 0x00 8.--9. "PWIDTH,Transfer data size of peripheral" "0,1,2,3"
newline
bitfld.long 0x00 7. "MNAGA,Next address generation algorithm of memory" "0,1"
bitfld.long 0x00 6. "PNAGA,Next address generation algorithm of peripheral" "0,1"
bitfld.long 0x00 5. "CMEN,Circular mode enable" "0,1"
bitfld.long 0x00 4. "DIR,Transfer direction" "0,1"
newline
bitfld.long 0x00 3. "ERRIE,Enable bit for channel error interrupt" "0,1"
bitfld.long 0x00 2. "HTFIE,Enable bit for channel half transfer finish interrupt" "0,1"
bitfld.long 0x00 1. "FTFIE,Enable bit for channel full transfer finish interrupt" "0,1"
bitfld.long 0x00 0. "CHEN,Channel enable" "0,1"
group.long 0x5C++0x03
line.long 0x00 "CH4CNT,Channel 4 counter register"
hexmask.long.word 0x00 0.--15. 1. "CNT,Transfer counter"
group.long 0x60++0x03
line.long 0x00 "CH4PADDR,Channel 4 peripheral base address register"
hexmask.long 0x00 0.--31. 1. "PADDR,Peripheral base address"
group.long 0x64++0x03
line.long 0x00 "CH4MADDR,Channel 4 memory base address register"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory base address"
group.long 0x6C++0x03
line.long 0x00 "CH5CTL,Channel 5 control register"
bitfld.long 0x00 14. "M2M,Memory to Memory Mode" "0,1"
bitfld.long 0x00 12.--13. "PRIO,Priority level" "0,1,2,3"
bitfld.long 0x00 10.--11. "MWIDTH,Transfer data size of memory" "0,1,2,3"
bitfld.long 0x00 8.--9. "PWIDTH,Transfer data size of peripheral" "0,1,2,3"
newline
bitfld.long 0x00 7. "MNAGA,Next address generation algorithm of memory" "0,1"
bitfld.long 0x00 6. "PNAGA,Next address generation algorithm of peripheral" "0,1"
bitfld.long 0x00 5. "CMEN,Circular mode enable" "0,1"
bitfld.long 0x00 4. "DIR,Transfer direction" "0,1"
newline
bitfld.long 0x00 3. "ERRIE,Enable bit for channel error interrupt" "0,1"
bitfld.long 0x00 2. "HTFIE,Enable bit for channel half transfer finish interrupt" "0,1"
bitfld.long 0x00 1. "FTFIE,Enable bit for channel full transfer finish interrupt" "0,1"
bitfld.long 0x00 0. "CHEN,Channel enable" "0,1"
group.long 0x70++0x03
line.long 0x00 "CH5CNT,Channel 5 counter register"
hexmask.long.word 0x00 0.--15. 1. "CNT,Transfer counter"
group.long 0x74++0x03
line.long 0x00 "CH5PADDR,Channel 5 peripheral base address register"
hexmask.long 0x00 0.--31. 1. "PADDR,Peripheral base address"
group.long 0x78++0x03
line.long 0x00 "CH5MADDR,Channel 5 memory base address register"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory base address"
group.long 0x80++0x03
line.long 0x00 "CH6CTL,Channel 6 control register"
bitfld.long 0x00 14. "M2M,Memory to Memory Mode" "0,1"
bitfld.long 0x00 12.--13. "PRIO,Priority level" "0,1,2,3"
bitfld.long 0x00 10.--11. "MWIDTH,Transfer data size of memory" "0,1,2,3"
bitfld.long 0x00 8.--9. "PWIDTH,Transfer data size of peripheral" "0,1,2,3"
newline
bitfld.long 0x00 7. "MNAGA,Next address generation algorithm of memory" "0,1"
bitfld.long 0x00 6. "PNAGA,Next address generation algorithm of peripheral" "0,1"
bitfld.long 0x00 5. "CMEN,Circular mode enable" "0,1"
bitfld.long 0x00 4. "DIR,Transfer direction" "0,1"
newline
bitfld.long 0x00 3. "ERRIE,Enable bit for channel error interrupt" "0,1"
bitfld.long 0x00 2. "HTFIE,Enable bit for channel half transfer finish interrupt" "0,1"
bitfld.long 0x00 1. "FTFIE,Enable bit for channel full transfer finish interrupt" "0,1"
bitfld.long 0x00 0. "CHEN,Channel enable" "0,1"
group.long 0x84++0x03
line.long 0x00 "CH6CNT,Channel 6 counter register"
hexmask.long.word 0x00 0.--15. 1. "CNT,Transfer counter"
group.long 0x88++0x03
line.long 0x00 "CH6PADDR,Channel 6 peripheral base address register"
hexmask.long 0x00 0.--31. 1. "PADDR,Peripheral base address"
group.long 0x8C++0x03
line.long 0x00 "CH6MADDR,Channel 6 memory base address register"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory base address"
tree.end
tree "DMA1"
base ad:0x40020400
rgroup.long 0x00++0x03
line.long 0x00 "INTF,Interrupt flag register"
bitfld.long 0x00 19. "ERRIF4,Error flag of channel 4" "0,1"
bitfld.long 0x00 18. "HTFIF4,Half transfer finish flag of channel 4" "0,1"
bitfld.long 0x00 17. "FTFIF4,Full Transfer finish flag of channe 4" "0,1"
bitfld.long 0x00 16. "GIF4,Global interrupt flag of channel 4" "0,1"
newline
bitfld.long 0x00 15. "ERRIF3,Error flag of channel 3" "0,1"
bitfld.long 0x00 14. "HTFIF3,Half transfer finish flag of channel 3" "0,1"
bitfld.long 0x00 13. "FTFIF3,Full Transfer finish flag of channe 3" "0,1"
bitfld.long 0x00 12. "GIF3,Global interrupt flag of channel 3" "0,1"
newline
bitfld.long 0x00 11. "ERRIF2,Error flag of channel 2" "0,1"
bitfld.long 0x00 10. "HTFIF2,Half transfer finish flag of channel 2" "0,1"
bitfld.long 0x00 9. "FTFIF2,Full Transfer finish flag of channe 2" "0,1"
bitfld.long 0x00 8. "GIF2,Global interrupt flag of channel 2" "0,1"
newline
bitfld.long 0x00 7. "ERRIF1,Error flag of channel 1" "0,1"
bitfld.long 0x00 6. "HTFIF1,Half transfer finish flag of channel 1" "0,1"
bitfld.long 0x00 5. "FTFIF1,Full Transfer finish flag of channe 1" "0,1"
bitfld.long 0x00 4. "GIF1,Global interrupt flag of channel 1" "0,1"
newline
bitfld.long 0x00 3. "ERRIF0,Error flag of channel 0" "0,1"
bitfld.long 0x00 2. "HTFIF0,Half transfer finish flag of channel 0" "0,1"
bitfld.long 0x00 1. "FTFIF0,Full Transfer finish flag of channe 0" "0,1"
bitfld.long 0x00 0. "GIF0,Global interrupt flag of channel 0" "0,1"
wgroup.long 0x04++0x03
line.long 0x00 "INTC,Interrupt flag clear register"
bitfld.long 0x00 19. "ERRIFC4,Clear bit for error flag of channel 4" "0,1"
bitfld.long 0x00 18. "HTFIFC4,Clear bit for half transfer finish flag of channel 4" "0,1"
bitfld.long 0x00 17. "FTFIFC4,Clear bit for full transfer finish flag of channel 4" "0,1"
bitfld.long 0x00 16. "GIFC4,Clear global interrupt flag of channel 4" "0,1"
newline
bitfld.long 0x00 15. "ERRIFC3,Clear bit for error flag of channel 3" "0,1"
bitfld.long 0x00 14. "HTFIFC3,Clear bit for half transfer finish flag of channel 3" "0,1"
bitfld.long 0x00 13. "FTFIFC3,Clear bit for full transfer finish flag of channel 3" "0,1"
bitfld.long 0x00 12. "GIFC3,Clear global interrupt flag of channel 3" "0,1"
newline
bitfld.long 0x00 11. "ERRIFC2,Clear bit for error flag of channel 2" "0,1"
bitfld.long 0x00 10. "HTFIFC2,Clear bit for half transfer finish flag of channel 2" "0,1"
bitfld.long 0x00 9. "FTFIFC2,Clear bit for full transfer finish flag of channel 2" "0,1"
bitfld.long 0x00 8. "GIFC2,Clear global interrupt flag of channel 2" "0,1"
newline
bitfld.long 0x00 7. "ERRIFC1,Clear bit for error flag of channel 1" "0,1"
bitfld.long 0x00 6. "HTFIFC1,Clear bit for half transfer finish flag of channel 1" "0,1"
bitfld.long 0x00 5. "FTFIFC1,Clear bit for full transfer finish flag of channel 1" "0,1"
bitfld.long 0x00 4. "GIFC1,Clear global interrupt flag of channel 1" "0,1"
newline
bitfld.long 0x00 3. "ERRIFC0,Clear bit for error flag of channel 0" "0,1"
bitfld.long 0x00 2. "HTFIFC0,Clear bit for half transfer finish flag of channel 0" "0,1"
bitfld.long 0x00 1. "FTFIFC0,Clear bit for full transfer finish flag of channel 0" "0,1"
bitfld.long 0x00 0. "GIFC0,Clear global interrupt flag of channel 0" "0,1"
group.long 0x08++0x03
line.long 0x00 "CH0CTL,Channel 0 control register"
bitfld.long 0x00 14. "M2M,Memory to Memory Mode" "0,1"
bitfld.long 0x00 12.--13. "PRIO,Priority level" "0,1,2,3"
bitfld.long 0x00 10.--11. "MWIDTH,Transfer data size of memory" "0,1,2,3"
bitfld.long 0x00 8.--9. "PWIDTH,Transfer data size of peripheral" "0,1,2,3"
newline
bitfld.long 0x00 7. "MNAGA,Next address generation algorithm of memory" "0,1"
bitfld.long 0x00 6. "PNAGA,Next address generation algorithm of peripheral" "0,1"
bitfld.long 0x00 5. "CMEN,Circular mode enable" "0,1"
bitfld.long 0x00 4. "DIR,Transfer direction" "0,1"
newline
bitfld.long 0x00 3. "ERRIE,Enable bit for channel error interrupt" "0,1"
bitfld.long 0x00 2. "HTFIE,Enable bit for channel half transfer finish interrupt" "0,1"
bitfld.long 0x00 1. "FTFIE,Enable bit for channel full transfer finish interrupt" "0,1"
bitfld.long 0x00 0. "CHEN,Channel enable" "0,1"
group.long 0x0C++0x03
line.long 0x00 "CH0CNT,Channel 0 counter register"
hexmask.long.word 0x00 0.--15. 1. "CNT,Transfer counter"
group.long 0x10++0x03
line.long 0x00 "CH0PADDR,Channel 0 peripheral base address register"
hexmask.long 0x00 0.--31. 1. "PADDR,Peripheral base address"
group.long 0x14++0x03
line.long 0x00 "CH0MADDR,Channel 0 memory base address register"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory base address"
group.long 0x1C++0x03
line.long 0x00 "CH1CTL,Channel 1 control register"
bitfld.long 0x00 14. "M2M,Memory to Memory Mode" "0,1"
bitfld.long 0x00 12.--13. "PRIO,Priority level" "0,1,2,3"
bitfld.long 0x00 10.--11. "MWIDTH,Transfer data size of memory" "0,1,2,3"
bitfld.long 0x00 8.--9. "PWIDTH,Transfer data size of peripheral" "0,1,2,3"
newline
bitfld.long 0x00 7. "MNAGA,Next address generation algorithm of memory" "0,1"
bitfld.long 0x00 6. "PNAGA,Next address generation algorithm of peripheral" "0,1"
bitfld.long 0x00 5. "CMEN,Circular mode enable" "0,1"
bitfld.long 0x00 4. "DIR,Transfer direction" "0,1"
newline
bitfld.long 0x00 3. "ERRIE,Enable bit for channel error interrupt" "0,1"
bitfld.long 0x00 2. "HTFIE,Enable bit for channel half transfer finish interrupt" "0,1"
bitfld.long 0x00 1. "FTFIE,Enable bit for channel full transfer finish interrupt" "0,1"
bitfld.long 0x00 0. "CHEN,Channel enable" "0,1"
group.long 0x20++0x03
line.long 0x00 "CH1CNT,Channel 1 counter register"
hexmask.long.word 0x00 0.--15. 1. "CNT,Transfer counter"
group.long 0x24++0x03
line.long 0x00 "CH1PADDR,Channel 1 peripheral base address register"
hexmask.long 0x00 0.--31. 1. "PADDR,Peripheral base address"
group.long 0x28++0x03
line.long 0x00 "CH1MADDR,Channel 1 memory base address register"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory base address"
group.long 0x30++0x03
line.long 0x00 "CH2CTL,Channel 2 control register"
bitfld.long 0x00 14. "M2M,Memory to Memory Mode" "0,1"
bitfld.long 0x00 12.--13. "PRIO,Priority level" "0,1,2,3"
bitfld.long 0x00 10.--11. "MWIDTH,Transfer data size of memory" "0,1,2,3"
bitfld.long 0x00 8.--9. "PWIDTH,Transfer data size of peripheral" "0,1,2,3"
newline
bitfld.long 0x00 7. "MNAGA,Next address generation algorithm of memory" "0,1"
bitfld.long 0x00 6. "PNAGA,Next address generation algorithm of peripheral" "0,1"
bitfld.long 0x00 5. "CMEN,Circular mode enable" "0,1"
bitfld.long 0x00 4. "DIR,Transfer direction" "0,1"
newline
bitfld.long 0x00 3. "ERRIE,Enable bit for channel error interrupt" "0,1"
bitfld.long 0x00 2. "HTFIE,Enable bit for channel half transfer finish interrupt" "0,1"
bitfld.long 0x00 1. "FTFIE,Enable bit for channel full transfer finish interrupt" "0,1"
bitfld.long 0x00 0. "CHEN,Channel enable" "0,1"
group.long 0x34++0x03
line.long 0x00 "CH2CNT,Channel 2 counter register"
hexmask.long.word 0x00 0.--15. 1. "CNT,Transfer counter"
group.long 0x38++0x03
line.long 0x00 "CH2PADDR,Channel 2 peripheral base address register"
hexmask.long 0x00 0.--31. 1. "PADDR,Peripheral base address"
group.long 0x3C++0x03
line.long 0x00 "CH2MADDR,Channel 2 memory base address register"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory base address"
group.long 0x44++0x03
line.long 0x00 "CH3CTL,Channel 3 control register"
bitfld.long 0x00 14. "M2M,Memory to Memory Mode" "0,1"
bitfld.long 0x00 12.--13. "PRIO,Priority level" "0,1,2,3"
bitfld.long 0x00 10.--11. "MWIDTH,Transfer data size of memory" "0,1,2,3"
bitfld.long 0x00 8.--9. "PWIDTH,Transfer data size of peripheral" "0,1,2,3"
newline
bitfld.long 0x00 7. "MNAGA,Next address generation algorithm of memory" "0,1"
bitfld.long 0x00 6. "PNAGA,Next address generation algorithm of peripheral" "0,1"
bitfld.long 0x00 5. "CMEN,Circular mode enable" "0,1"
bitfld.long 0x00 4. "DIR,Transfer direction" "0,1"
newline
bitfld.long 0x00 3. "ERRIE,Enable bit for channel error interrupt" "0,1"
bitfld.long 0x00 2. "HTFIE,Enable bit for channel half transfer finish interrupt" "0,1"
bitfld.long 0x00 1. "FTFIE,Enable bit for channel full transfer finish interrupt" "0,1"
bitfld.long 0x00 0. "CHEN,Channel enable" "0,1"
group.long 0x48++0x03
line.long 0x00 "CH3CNT,Channel 3 counter register"
hexmask.long.word 0x00 0.--15. 1. "CNT,Transfer counter"
group.long 0x4C++0x03
line.long 0x00 "CH3PADDR,Channel 3 peripheral base address register"
hexmask.long 0x00 0.--31. 1. "PADDR,Peripheral base address"
group.long 0x50++0x03
line.long 0x00 "CH3MADDR,Channel 3 memory base address register"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory base address"
group.long 0x58++0x03
line.long 0x00 "CH4CTL,Channel 4 control register"
bitfld.long 0x00 14. "M2M,Memory to Memory Mode" "0,1"
bitfld.long 0x00 12.--13. "PRIO,Priority level" "0,1,2,3"
bitfld.long 0x00 10.--11. "MWIDTH,Transfer data size of memory" "0,1,2,3"
bitfld.long 0x00 8.--9. "PWIDTH,Transfer data size of peripheral" "0,1,2,3"
newline
bitfld.long 0x00 7. "MNAGA,Next address generation algorithm of memory" "0,1"
bitfld.long 0x00 6. "PNAGA,Next address generation algorithm of peripheral" "0,1"
bitfld.long 0x00 5. "CMEN,Circular mode enable" "0,1"
bitfld.long 0x00 4. "DIR,Transfer direction" "0,1"
newline
bitfld.long 0x00 3. "ERRIE,Enable bit for channel error interrupt" "0,1"
bitfld.long 0x00 2. "HTFIE,Enable bit for channel half transfer finish interrupt" "0,1"
bitfld.long 0x00 1. "FTFIE,Enable bit for channel full transfer finish interrupt" "0,1"
bitfld.long 0x00 0. "CHEN,Channel enable" "0,1"
group.long 0x5C++0x03
line.long 0x00 "CH4CNT,Channel 4 counter register"
hexmask.long.word 0x00 0.--15. 1. "CNT,Transfer counter"
group.long 0x60++0x03
line.long 0x00 "CH4PADDR,Channel 4 peripheral base address register"
hexmask.long 0x00 0.--31. 1. "PADDR,Peripheral base address"
group.long 0x64++0x03
line.long 0x00 "CH4MADDR,Channel 4 memory base address register"
hexmask.long 0x00 0.--31. 1. "MADDR,Memory base address"
tree.end
tree.end
sif cpuis("GD32E50*CL")
tree "ENET (Ethernet MAC)"
tree "ENET_DMA"
base ad:0x40029000
group.long 0x00++0x03
line.long 0x00 "DMA_BCTL,Ethernet DMA bus control register"
bitfld.long 0x00 26. "MB,Mixed burst" "0,1"
bitfld.long 0x00 25. "AA,Address-aligned" "0,1"
bitfld.long 0x00 24. "FPBL,Four times PGBL mode" "0,1"
bitfld.long 0x00 23. "UIP,Use independent PGBL" "0,1"
newline
bitfld.long 0x00 17.--22. "RXDP,Rx DMA PGBL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16. "FB,Fixed burst" "0,1"
bitfld.long 0x00 14.--15. "RTPR,RxDMA and TxDMA transfer priority ratio" "0,1,2,3"
bitfld.long 0x00 8.--13. "PGBL,Programmable burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 7. "DFM,Descriptor format mode" "0,1"
bitfld.long 0x00 2.--6. "DPSL,Descriptor skip length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1. "DAB,DMA Arbitration" "0,1"
bitfld.long 0x00 0. "SWR,Software reset" "0,1"
group.long 0x04++0x03
line.long 0x00 "DMA_TPEN,Ethernet DMA transmit poll enable register"
hexmask.long 0x00 0.--31. 1. "TPE,Transmit poll enable"
group.long 0x08++0x03
line.long 0x00 "DMA_RPEN,Ethernet DMA receive poll enable register"
hexmask.long 0x00 0.--31. 1. "RPE,Receive poll enable"
group.long 0x0C++0x03
line.long 0x00 "DMA_RDTADDR,Ethernet DMA receive descriptor table address register"
hexmask.long 0x00 0.--31. 1. "SRT,Start address of receive table"
group.long 0x10++0x03
line.long 0x00 "DMA_TDTADDR,Ethernet DMA transmit descriptor table address register"
hexmask.long 0x00 0.--31. 1. "STT,Start address of transmit table"
group.long 0x14++0x03
line.long 0x00 "DMA_STAT,Ethernet DMA status register"
rbitfld.long 0x00 29. "TST,Time stamp trigger status" "0,1"
rbitfld.long 0x00 28. "WUM,WUM status" "0,1"
rbitfld.long 0x00 27. "MSC,MSC status" "0,1"
rbitfld.long 0x00 23.--25. "EB,Error bits status" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 20.--22. "TP,Transmit process state" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 17.--19. "RP,Receive process state" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "NI,Normal interrupt summary" "0,1"
bitfld.long 0x00 15. "AI,Abnormal interrupt summary" "0,1"
newline
bitfld.long 0x00 14. "ER,Early receive status" "0,1"
bitfld.long 0x00 13. "FBE,Fatal bus error status" "0,1"
bitfld.long 0x00 10. "ET,Early transmit status" "0,1"
bitfld.long 0x00 9. "RWT,Receive watchdog timeout status" "0,1"
newline
bitfld.long 0x00 8. "RPS,Receive process stopped status" "0,1"
bitfld.long 0x00 7. "RBU,Receive buffer unavailable status" "0,1"
bitfld.long 0x00 6. "RS,Receive status" "0,1"
bitfld.long 0x00 5. "TU,Transmit underflow status" "0,1"
newline
bitfld.long 0x00 4. "RO,Receive overflow status" "0,1"
bitfld.long 0x00 3. "TJT,Transmit jabber timeout status" "0,1"
bitfld.long 0x00 2. "TBU,Transmit buffer unavailable status" "0,1"
bitfld.long 0x00 1. "TPS,Transmit process stopped status" "0,1"
newline
bitfld.long 0x00 0. "TS,Transmit status" "0,1"
group.long 0x18++0x03
line.long 0x00 "DMA_CTL,Ethernet DMA control register"
bitfld.long 0x00 26. "DTCERFD,Dropping of TCP/IP checksum error frames disable" "0,1"
bitfld.long 0x00 25. "RSFD,Receive Store-and-Forward" "0,1"
bitfld.long 0x00 24. "DAFRF,Disable flushing of received frames" "0,1"
bitfld.long 0x00 21. "TSFD,Transmit Store-and-Forward" "0,1"
newline
bitfld.long 0x00 20. "FTF,Flush transmit FIFO" "0,1"
bitfld.long 0x00 14.--16. "TTHC,Transmit threshold control" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "STE,Start/stop transmission enable" "0,1"
bitfld.long 0x00 7. "FERF,Forward error frames" "0,1"
newline
bitfld.long 0x00 6. "FUF,Forward undersized good frames" "0,1"
bitfld.long 0x00 3.--4. "RTHC,Receive threshold control" "0,1,2,3"
bitfld.long 0x00 2. "OSF,Operate on second frame" "0,1"
bitfld.long 0x00 1. "SRE,Start/stop receive enable" "0,1"
group.long 0x1C++0x03
line.long 0x00 "DMA_INTEN,Ethernet DMA interrupt enable register"
bitfld.long 0x00 16. "NIE,Normal interrupt summary enable" "0,1"
bitfld.long 0x00 15. "AIE,Abnormal interrupt summary enable" "0,1"
bitfld.long 0x00 14. "ERIE,Early receive interrupt enable" "0,1"
bitfld.long 0x00 13. "FBEIE,Fatal bus error interrupt enable" "0,1"
newline
bitfld.long 0x00 10. "ETIE,Early transmit interrupt enable" "0,1"
bitfld.long 0x00 9. "RWTIE,receive watchdog timeout interrupt enable" "0,1"
bitfld.long 0x00 8. "RPSIE,Receive process stopped interrupt enable" "0,1"
bitfld.long 0x00 7. "RBUIE,Receive buffer unavailable interrupt enable" "0,1"
newline
bitfld.long 0x00 6. "RIE,Receive interrupt enable" "0,1"
bitfld.long 0x00 5. "TUIE,Transmit underflow interrupt enable" "0,1"
bitfld.long 0x00 4. "ROIE,Receive overflow interrupt enable" "0,1"
bitfld.long 0x00 3. "TJTIE,Transmit jabber timeout interrupt enable" "0,1"
newline
bitfld.long 0x00 2. "TBUIE,Transmit buffer unavailable interrupt enable" "0,1"
bitfld.long 0x00 1. "TPSIE,Transmit process stopped interrupt enable" "0,1"
bitfld.long 0x00 0. "TIE,Transmit interrupt enable" "0,1"
rgroup.long 0x20++0x03
line.long 0x00 "DMA_MFBOCNT,Ethernet DMA missed frame and buffer overflow counter register"
hexmask.long.word 0x00 17.--27. 1. "MSFA,Missed frames by the application"
hexmask.long.word 0x00 0.--15. 1. "MSFC,Missed frames by the controller"
group.long 0x24++0x03
line.long 0x00 "DMA_RSWDC,Ethernet DMA receive state watchdog counter register"
hexmask.long.byte 0x00 0.--7. 1. "WDCFRS,Watchdog counter for receive status (RS)"
rgroup.long 0x48++0x03
line.long 0x00 "DMA_CTDADDR,DMA current transmit descriptor address register"
hexmask.long 0x00 0.--31. 1. "TDAP,transmit descriptor address pointer"
rgroup.long 0x4C++0x03
line.long 0x00 "DMA_CRDADDR,Ethernet DMA current receive descriptor address register"
hexmask.long 0x00 0.--31. 1. "RDAP,Receive descriptor address pointer"
rgroup.long 0x50++0x03
line.long 0x00 "DMA_CTBADDR,Ethernet DMA current transmit buffer address register"
hexmask.long 0x00 0.--31. 1. "TBAP,Transmit buffer address pointer"
rgroup.long 0x54++0x03
line.long 0x00 "DMA_CRBADDR,Ethernet DMA current receive buffer address register"
hexmask.long 0x00 0.--31. 1. "RBAP,receive buffer address pointer"
tree.end
tree "ENET_MAC"
base ad:0x40028000
group.long 0x00++0x03
line.long 0x00 "MAC_CFG,Ethernet MAC configuration register (MAC_CFG)"
bitfld.long 0x00 25. "TFCD,Type Frame CRC Dropping" "0,1"
bitfld.long 0x00 23. "WDD,Watchdog disable" "0,1"
bitfld.long 0x00 22. "JBD,Jabber disable" "0,1"
bitfld.long 0x00 17.--19. "IGBS,Inter frame gap bit selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16. "CSD,Carrier sense disable" "0,1"
bitfld.long 0x00 14. "SPD,Fast Ethernet speed" "0,1"
bitfld.long 0x00 13. "ROD,Receive own disable" "0,1"
bitfld.long 0x00 12. "LBM,Loopback mode" "0,1"
newline
bitfld.long 0x00 11. "DPM,Duplex mode" "0,1"
bitfld.long 0x00 10. "IPFCO,IP frame checksum offload" "0,1"
bitfld.long 0x00 9. "RTD,Retry disable" "0,1"
bitfld.long 0x00 7. "APCD,Automatic pad/CRC drop" "0,1"
newline
bitfld.long 0x00 5.--6. "BOL,Back-off limit" "0,1,2,3"
bitfld.long 0x00 4. "DFC,Deferral check" "0,1"
bitfld.long 0x00 3. "TEN,Transmitter enable" "0,1"
bitfld.long 0x00 2. "REN,Receiver enable" "0,1"
group.long 0x04++0x03
line.long 0x00 "MAC_FRMF,Ethernet MAC frame filter register (MAC_FRMF)"
bitfld.long 0x00 31. "FAR,Frames all receive" "0,1"
bitfld.long 0x00 10. "HPFLT,Hash or perfect filter" "0,1"
bitfld.long 0x00 9. "SAFLT,Source address filter" "0,1"
bitfld.long 0x00 8. "SAIFLT,Source address inverse filtering" "0,1"
newline
bitfld.long 0x00 6.--7. "PCFRM,Pass control frames" "0,1,2,3"
bitfld.long 0x00 5. "BFRMD,Broadcast frames disable" "0,1"
bitfld.long 0x00 4. "MFD,multicast filter disable" "0,1"
bitfld.long 0x00 3. "DAIFLT,Destination address inverse filtering" "0,1"
newline
bitfld.long 0x00 2. "HMF,Hash multicast filter" "0,1"
bitfld.long 0x00 1. "HUF,Hash unicast filter" "0,1"
bitfld.long 0x00 0. "PM,Promiscuous mode" "0,1"
group.long 0x08++0x03
line.long 0x00 "MAC_HLH,Ethernet MAC hash list high register"
hexmask.long 0x00 0.--31. 1. "HLH,Hash list high"
group.long 0x0C++0x03
line.long 0x00 "MAC_HLL,Ethernet MAC hash list low register"
hexmask.long 0x00 0.--31. 1. "HLL,Hash list low"
group.long 0x10++0x03
line.long 0x00 "MAC_PHY_CTL,Ethernet MAC PHY control register (MAC_PHY_CTL)"
bitfld.long 0x00 11.--15. "PA,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 6.--10. "PR,PHY register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 2.--4. "CLR,Clock range" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1. "PW,PHY" "0,1"
newline
bitfld.long 0x00 0. "PB,PHY busy" "0,1"
group.long 0x14++0x03
line.long 0x00 "MAC_PHY_DATA,Ethernet MAC MII data register (MAC_PHY_DATA)"
hexmask.long.word 0x00 0.--15. 1. "PD,PHY data"
group.long 0x18++0x03
line.long 0x00 "MAC_FCTL,Ethernet MAC flow control register (MAC_FCTL)"
hexmask.long.word 0x00 16.--31. 1. "PTM,Pause time"
bitfld.long 0x00 7. "DZQP,Disable Zero-quanta pause" "0,1"
bitfld.long 0x00 4.--5. "PLTS,Pause low threshold" "0,1,2,3"
bitfld.long 0x00 3. "UPFDT,Unicast pause frame detect" "0,1"
newline
bitfld.long 0x00 2. "RFCEN,Receive flow control enable" "0,1"
bitfld.long 0x00 1. "TFCEN,Transmit flow control enable" "0,1"
bitfld.long 0x00 0. "FLCB_BKPA,Flow control busy/back pressure activate" "0,1"
group.long 0x1C++0x03
line.long 0x00 "MAC_VLT,Ethernet MAC VLAN tag register (MAC_VLT)"
bitfld.long 0x00 16. "VLTC,12-bit VLAN tag comparison" "0,1"
hexmask.long.word 0x00 0.--15. 1. "VLTI,VLAN tag identifier (for receive frames)"
group.long 0x28++0x03
line.long 0x00 "MAC_RWFF,Ethernet MAC remote wakeup frame filter register (MAC_RWFF)"
group.long 0x2C++0x03
line.long 0x00 "MAC_WUM,Ethernet MAC wakeup management register (MAC_WUM)"
bitfld.long 0x00 31. "WUFFRPR,Wakeup frame filter register pointer reset" "0,1"
bitfld.long 0x00 9. "GU,Global unicast" "0,1"
bitfld.long 0x00 6. "WUFR,Wakeup frame received" "0,1"
bitfld.long 0x00 5. "MPKR,Magic packet received" "0,1"
newline
bitfld.long 0x00 2. "WFEN,Wakeup frame enable" "0,1"
bitfld.long 0x00 1. "MPEN,Magic Packet enable" "0,1"
bitfld.long 0x00 0. "PWD,Power down" "0,1"
rgroup.long 0x34++0x03
line.long 0x00 "MAC_DBG,Ethernet MAC debug register (MAC_DBG)"
bitfld.long 0x00 25. "TXFF,TxFIFO Full flag" "0,1"
bitfld.long 0x00 24. "TXFNE,TxFIFO not empty flag" "0,1"
bitfld.long 0x00 22. "TXFW,TxFIFO is writing" "0,1"
bitfld.long 0x00 20.--21. "TXFRS,TxFIFO read operation status" "0,1,2,3"
newline
bitfld.long 0x00 19. "PCS,Pause condition status" "0,1"
bitfld.long 0x00 17.--18. "SOMT,Status of MAC transmitter" "0,1,2,3"
bitfld.long 0x00 16. "MTNI,MAC transmit state not idle" "0,1"
bitfld.long 0x00 8.--9. "RXFS,RxFIFO state" "0,1,2,3"
newline
bitfld.long 0x00 5.--6. "RXFRS,RxFIFO read operation status" "0,1,2,3"
bitfld.long 0x00 4. "RXFW,RxFIFO is writing" "0,1"
bitfld.long 0x00 1.--2. "RXAFS,Rx asynchronous FIFO status" "0,1,2,3"
bitfld.long 0x00 0. "MRNI,MAC receive state not idle" "0,1"
rgroup.long 0x38++0x03
line.long 0x00 "MAC_INTF,Ethernet MAC interrupt flag register (MAC_INTF)"
bitfld.long 0x00 9. "TMST,Time stamp trigger status" "0,1"
bitfld.long 0x00 6. "MSCT,MSC transmit status" "0,1"
bitfld.long 0x00 5. "MSCR,MSC receive status" "0,1"
bitfld.long 0x00 4. "MSC,MSC status" "0,1"
newline
bitfld.long 0x00 3. "WUM,WUM status" "0,1"
group.long 0x3C++0x03
line.long 0x00 "MAC_INTMSK,Ethernet MAC interrupt mask register (MAC_INTMSK)"
bitfld.long 0x00 9. "TMSTIM,Time stamp trigger interrupt mask" "0,1"
bitfld.long 0x00 3. "WUMIM,WUM interrupt mask" "0,1"
group.long 0x40++0x03
line.long 0x00 "MAC_ADDR0H,Ethernet MAC address 0 high register (MAC_ADDR0H)"
bitfld.long 0x00 31. "MO,Always 1" "0,1"
hexmask.long.word 0x00 0.--15. 1. "ADDR0H,MAC address0 high"
group.long 0x44++0x03
line.long 0x00 "MAC_ADDR0L,Ethernet MAC address 0 low register"
hexmask.long 0x00 0.--31. 1. "ADDR0L,MAC address0 low"
group.long 0x48++0x03
line.long 0x00 "MAC_ADDR1H,Ethernet MAC address 1 high register (MAC_ADDR1H)"
bitfld.long 0x00 31. "AFE,Address filter enable" "0,1"
bitfld.long 0x00 30. "SAF,Source address filter" "0,1"
bitfld.long 0x00 24.--29. "MB,Mask byte" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 0.--15. 1. "ADDR1H,MAC address1 high"
group.long 0x4C++0x03
line.long 0x00 "MAC_ADDR1L,Ethernet MAC address1 low register"
hexmask.long 0x00 0.--31. 1. "ADDR1L,MAC address1 low"
group.long 0x50++0x03
line.long 0x00 "MAC_ADDR2H,Ethernet MAC address 2 high register (MAC_ADDR2H)"
bitfld.long 0x00 31. "AFE,Address filter enable" "0,1"
bitfld.long 0x00 30. "SAF,Source address filter" "0,1"
bitfld.long 0x00 24.--29. "MB,Mask byte" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 0.--15. 1. "ADDR2H,Ethernet MAC address 2 high register"
group.long 0x54++0x03
line.long 0x00 "MAC_ADDR2L,Ethernet MAC address 2 low register"
hexmask.long 0x00 0.--31. 1. "ADDR2L,MAC address2 low"
group.long 0x58++0x03
line.long 0x00 "MAC_ADDR3H,Ethernet MAC address 3 high register (MAC_ADDR3H)"
bitfld.long 0x00 31. "AFE,Address filter enable" "0,1"
bitfld.long 0x00 30. "SAF,Source address filter" "0,1"
bitfld.long 0x00 24.--29. "MB,Mask byte" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 0.--15. 1. "ADDR3H,MAC address3 high"
group.long 0x5C++0x03
line.long 0x00 "MAC_ADDR3L,Ethernet MAC address 3 low register"
hexmask.long 0x00 0.--31. 1. "ADDR3L,MAC address3 low"
tree.end
tree "ENET_MAC_FCTH"
base ad:0x40029080
group.long 0x00++0x03
line.long 0x00 "MAC_FCTH,Ethernet MAC flow control threshold register"
bitfld.long 0x00 4.--6. "RFD,Threshold of deactive flow control" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "RFA,Threshold of active flow control" "0,1,2,3,4,5,6,7"
tree.end
tree "ENET_MSC"
base ad:0x40028100
group.long 0x00++0x03
line.long 0x00 "MSC_CTL,Ethernet MSC control register (MSC_CTL)"
bitfld.long 0x00 5. "AFHPM,Almost full or half preset mode" "0,1"
bitfld.long 0x00 4. "PMC,Preset MSC counter" "0,1"
bitfld.long 0x00 3. "MCFZ,MSC counter freeze" "0,1"
bitfld.long 0x00 2. "RTOR,Reset on read" "0,1"
newline
bitfld.long 0x00 1. "CTSR,Counter stop rollover" "0,1"
bitfld.long 0x00 0. "CTR,Counter reset" "0,1"
rgroup.long 0x04++0x03
line.long 0x00 "MSC_RINTF,Ethernet MSC receive interrupt flag register (MSC_RINTF)"
bitfld.long 0x00 17. "RGUF,Received Good Unicast Frames" "0,1"
bitfld.long 0x00 6. "RFAE,Received frames alignment error" "0,1"
bitfld.long 0x00 5. "RFCE,Received frames CRC error" "0,1"
rgroup.long 0x08++0x03
line.long 0x00 "MSC_TINTF,Ethernet MSC transmit interrupt flag register (MSC_TINTF)"
bitfld.long 0x00 21. "TGF,Transmitted good frames" "0,1"
bitfld.long 0x00 15. "TGFMSC,Transmitted good frames more single collision" "0,1"
bitfld.long 0x00 14. "TGFSC,Transmitted good frames single collision" "0,1"
group.long 0x0C++0x03
line.long 0x00 "MSC_RINTMSK,Ethernet MSC receive interrupt mask register (MSC_RINTMSK)"
bitfld.long 0x00 17. "RGUFIM,Received good unicast frames interrupt mask" "0,1"
bitfld.long 0x00 6. "RFAEIM,Received frames alignment error interrupt mask" "0,1"
bitfld.long 0x00 5. "RFCEIM,Received frame CRC error interrupt mask" "0,1"
group.long 0x10++0x03
line.long 0x00 "MSC_TINTMSK,Ethernet MSC transmit interrupt mask register (MSC_TINTMSK)"
bitfld.long 0x00 21. "TGFIM,Transmitted good frames interrupt mask" "0,1"
bitfld.long 0x00 15. "TGFMSCIM,Transmitted good frames more single interrupt collision mask" "0,1"
bitfld.long 0x00 14. "TGFSCIM,Transmitted good frames single collision interrupt mask" "0,1"
rgroup.long 0x4C++0x03
line.long 0x00 "MSC_SCCNT,Ethernet MSC transmitted good frames after a single collision counter"
hexmask.long 0x00 0.--31. 1. "SCC,Transmitted good frames after a single collision counter"
rgroup.long 0x50++0x03
line.long 0x00 "MSC_MSCCNT,Ethernet MSC transmitted good frames after more than a single collision"
hexmask.long 0x00 0.--31. 1. "MSCC,Transmitted good frames after more than a single collision counter"
rgroup.long 0x68++0x03
line.long 0x00 "MSC_TGFCNT,Ethernet MSC transmitted good frames counter register"
hexmask.long 0x00 0.--31. 1. "TGF,Transmitted good frames counter"
rgroup.long 0x94++0x03
line.long 0x00 "MSC_RFCECNT,Ethernet MSC received frames with CRC error counter register"
hexmask.long 0x00 0.--31. 1. "RFCER,Received frames with CRC error counter"
rgroup.long 0x98++0x03
line.long 0x00 "MSC_RFAECNT,Ethernet MSC received frames with alignment error counter register"
hexmask.long 0x00 0.--31. 1. "RFAER,Received frames with alignment error counter"
rgroup.long 0xC4++0x03
line.long 0x00 "MSC_RGUFCNT,MSC received good unicast frames counter register"
hexmask.long 0x00 0.--31. 1. "RGUF,Received good unicast frames counter"
tree.end
tree "ENET_PTP"
base ad:0x40028700
group.long 0x00++0x03
line.long 0x00 "PTP_TSCTL,Ethernet PTP time stamp control register (PTP_TSCTL)"
bitfld.long 0x00 18. "MAFEN,MAC address filter enable for PTP frame" "0,1"
bitfld.long 0x00 16.--17. "CKNT,Clock node type for time stamp" "0,1,2,3"
bitfld.long 0x00 15. "MNMSEN,Received master node message snapshot enable" "0,1"
bitfld.long 0x00 14. "ETMSEN,Received event type message snapshot enable" "0,1"
newline
bitfld.long 0x00 13. "IP4SEN,Received IPv4 snapshot enable" "0,1"
bitfld.long 0x00 12. "IP6SEN,Received IPv6 snapshot enable" "0,1"
bitfld.long 0x00 11. "ESEN,Received Ethernet snapshot enable" "0,1"
bitfld.long 0x00 10. "PFSV,PTP frame snooping version" "0,1"
newline
bitfld.long 0x00 9. "SCROM,Subsecond counter rollover mode" "0,1"
bitfld.long 0x00 8. "ARFSEN,All received frames snapshot enable" "0,1"
bitfld.long 0x00 5. "TMSARU,Time stamp addend register update" "0,1"
bitfld.long 0x00 4. "TMSITEN,Time stamp interrupt trigger enable" "0,1"
newline
bitfld.long 0x00 3. "TMSSTU,Time stamp system time update" "0,1"
bitfld.long 0x00 2. "TMSSTI,Time stamp system time initialize" "0,1"
bitfld.long 0x00 1. "TMSFCU,Time stamp fine or coarse update" "0,1"
bitfld.long 0x00 0. "TMSEN,Time stamp enable" "0,1"
group.long 0x04++0x03
line.long 0x00 "PTP_SSINC,Ethernet PTP subsecond increment register"
hexmask.long.byte 0x00 0.--7. 1. "STMSSI,System time subsecond increment"
rgroup.long 0x08++0x03
line.long 0x00 "PTP_TSH,Ethernet PTP time stamp high register"
hexmask.long 0x00 0.--31. 1. "STMS,System time second"
rgroup.long 0x0C++0x03
line.long 0x00 "PTP_TSL,Ethernet PTP time stamp low register (PTP_TSL)"
bitfld.long 0x00 31. "STS,System time sign" "0,1"
hexmask.long 0x00 0.--30. 1. "STMSS,System time subseconds"
group.long 0x10++0x03
line.long 0x00 "PTP_TSUH,Ethernet PTP time stamp high update register"
hexmask.long 0x00 0.--31. 1. "TMSUS,Time stamp update second"
group.long 0x14++0x03
line.long 0x00 "PTP_TSUL,Ethernet PTP time stamp low update register (PTP_TSUL)"
bitfld.long 0x00 31. "TMSUPNS,Time stamp update positive or negative sign" "0,1"
hexmask.long 0x00 0.--30. 1. "TMSUSS,Time stamp update subseconds"
group.long 0x18++0x03
line.long 0x00 "PTP_TSADDEND,Ethernet PTP time stamp addend register"
hexmask.long 0x00 0.--31. 1. "TMSA,Time stamp addend"
group.long 0x1C++0x03
line.long 0x00 "PTP_ETH,Ethernet PTP expected time high register"
hexmask.long 0x00 0.--31. 1. "ETSH,Expected time stamp high"
group.long 0x20++0x03
line.long 0x00 "PTP_ETL,Ethernet PTP expected time low register"
hexmask.long 0x00 0.--31. 1. "ETSL,Expected time stamp low"
rgroup.long 0x28++0x03
line.long 0x00 "PTP_TSF,Ethernet PTP time stamp flag register"
bitfld.long 0x00 1. "TTM,Target time match" "0,1"
bitfld.long 0x00 0. "TSSCO,Timestamp second counter overflow" "0,1"
group.long 0x2C++0x03
line.long 0x00 "PTP_PPSCTL,Ethernet PTP PPS control register"
bitfld.long 0x00 0.--3. "PPSOFC,PPS output frequency configure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree.end
endif
tree "EXMC (External memory controller)"
base ad:0xA0000000
group.long 0x00++0x03
line.long 0x00 "SNCTL0,SRAM/NOR flash control register 0"
bitfld.long 0x00 19. "SYNCWR,Synchronous" "0,1"
bitfld.long 0x00 16.--18. "CPS,CRAM page size" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 15. "ASYNCWAIT,Asynchronous wait" "0,1"
bitfld.long 0x00 14. "EXMODEN,Extended mode enable" "0,1"
newline
bitfld.long 0x00 13. "NRWTEN,NWAIT signal enable" "0,1"
bitfld.long 0x00 12. "WREN,Write enable" "0,1"
bitfld.long 0x00 11. "NRWTCFG,NWAIT signal configuration only work in synchronous mode" "0,1"
bitfld.long 0x00 10. "WRAPEN,Wrapped burst mode enable" "0,1"
newline
bitfld.long 0x00 9. "NRWTPOL,NWAIT signal polarity" "0,1"
bitfld.long 0x00 8. "SBRSTEN,Synchronous burst enable" "0,1"
bitfld.long 0x00 6. "NREN,NOR Flash access enable" "0,1"
bitfld.long 0x00 4.--5. "NRW,NOR bank memory data bus width" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "NRTP,NOR bank memory type" "0,1,2,3"
bitfld.long 0x00 1. "NRMUX,NOR bank memory address/data multiplexing" "0,1"
bitfld.long 0x00 0. "NRBKEN,NOR bank enable" "0,1"
group.long 0x04++0x03
line.long 0x00 "SNTCFG0,SRAM/NOR flash timing configuration register 0"
bitfld.long 0x00 28.--29. "ASYNCMOD,Asynchronous access mode" "0,1,2,3"
bitfld.long 0x00 24.--27. "DLAT,Data latency for NOR Flash" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "CKDIV,Synchronous clock divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "BUSLAT,Bus latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 8.--15. 1. "DSET,Data setup time"
bitfld.long 0x00 4.--7. "AHLD,Address hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "ASET,Address setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x08++0x03
line.long 0x00 "SNCTL1,SRAM/NOR flash control register 1"
bitfld.long 0x00 19. "SYNCWR,Synchronous" "0,1"
bitfld.long 0x00 16.--18. "CPS,CRAM page size" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 15. "ASYNCWAIT,Asynchronous wait" "0,1"
bitfld.long 0x00 14. "EXMODEN,Extended mode enable" "0,1"
newline
bitfld.long 0x00 13. "NRWTEN,NWAIT signal enable" "0,1"
bitfld.long 0x00 12. "WREN,Write enable" "0,1"
bitfld.long 0x00 11. "NRWTCFG,NWAIT signal configuration only work in synchronous mode" "0,1"
bitfld.long 0x00 10. "WRAPEN,Wrapped burst mode enable" "0,1"
newline
bitfld.long 0x00 9. "NRWTPOL,NWAIT signal polarity" "0,1"
bitfld.long 0x00 8. "SBRSTEN,Synchronous burst enable" "0,1"
bitfld.long 0x00 6. "NREN,NOR Flash access enable" "0,1"
bitfld.long 0x00 4.--5. "NRW,NOR bank memory data bus width" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "NRTP,NOR bank memory type" "0,1,2,3"
bitfld.long 0x00 1. "NRMUX,NOR bank memory address/data multiplexing" "0,1"
bitfld.long 0x00 0. "NRBKEN,NOR bank enable" "0,1"
group.long 0x0C++0x03
line.long 0x00 "SNTCFG1,SRAM/NOR flash timing configuration register 1"
bitfld.long 0x00 28.--29. "ASYNCMOD,Asynchronous access mode" "0,1,2,3"
bitfld.long 0x00 24.--27. "DLAT,Data latency for NOR Flash" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "CKDIV,Synchronous clock divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "BUSLAT,Bus latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 8.--15. 1. "DSET,Data setup time"
bitfld.long 0x00 4.--7. "AHLD,Address hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "ASET,Address setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x03
line.long 0x00 "SNCTL2,SRAM/NOR flash control register 2"
bitfld.long 0x00 19. "SYNCWR,Synchronous" "0,1"
bitfld.long 0x00 16.--18. "CPS,CRAM page size" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 15. "ASYNCWAIT,Asynchronous wait" "0,1"
bitfld.long 0x00 14. "EXMODEN,Extended mode enable" "0,1"
newline
bitfld.long 0x00 13. "NRWTEN,NWAIT signal enable" "0,1"
bitfld.long 0x00 12. "WREN,Write enable" "0,1"
bitfld.long 0x00 11. "NRWTCFG,NWAIT signal configuration only work in synchronous mode" "0,1"
bitfld.long 0x00 10. "WRAPEN,Wrapped burst mode enable" "0,1"
newline
bitfld.long 0x00 9. "NRWTPOL,NWAIT signal polarity" "0,1"
bitfld.long 0x00 8. "SBRSTEN,Synchronous burst enable" "0,1"
bitfld.long 0x00 6. "NREN,NOR Flash access enable" "0,1"
bitfld.long 0x00 4.--5. "NRW,NOR bank memory data bus width" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "NRTP,NOR bank memory type" "0,1,2,3"
bitfld.long 0x00 1. "NRMUX,NOR bank memory address/data multiplexing" "0,1"
bitfld.long 0x00 0. "NRBKEN,NOR bank enable" "0,1"
group.long 0x14++0x03
line.long 0x00 "SNTCFG2,SRAM/NOR flash timing configuration register 2"
bitfld.long 0x00 28.--29. "ASYNCMOD,Asynchronous access mode" "0,1,2,3"
bitfld.long 0x00 24.--27. "DLAT,Data latency for NOR Flash" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "CKDIV,Synchronous clock divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "BUSLAT,Bus latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 8.--15. 1. "DSET,Data setup time"
bitfld.long 0x00 4.--7. "AHLD,Address hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "ASET,Address setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x18++0x03
line.long 0x00 "SNCTL3,SRAM/NOR flash control register 3"
bitfld.long 0x00 19. "SYNCWR,Synchronous" "0,1"
bitfld.long 0x00 16.--18. "CPS,CRAM page size" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 15. "ASYNCWAIT,Asynchronous wait" "0,1"
bitfld.long 0x00 14. "EXMODEN,Extended mode enable" "0,1"
newline
bitfld.long 0x00 13. "NRWTEN,NWAIT signal enable" "0,1"
bitfld.long 0x00 12. "WREN,Write enable" "0,1"
bitfld.long 0x00 11. "NRWTCFG,NWAIT signal configuration only work in synchronous mode" "0,1"
bitfld.long 0x00 10. "WRAPEN,Wrapped burst mode enable" "0,1"
newline
bitfld.long 0x00 9. "NRWTPOL,NWAIT signal polarity" "0,1"
bitfld.long 0x00 8. "SBRSTEN,Synchronous burst enable" "0,1"
bitfld.long 0x00 6. "NREN,NOR Flash access enable" "0,1"
bitfld.long 0x00 4.--5. "NRW,NOR bank memory data bus width" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "NRTP,NOR bank memory type" "0,1,2,3"
bitfld.long 0x00 1. "NRMUX,NOR bank memory address/data multiplexing" "0,1"
bitfld.long 0x00 0. "NRBKEN,NOR bank enable" "0,1"
group.long 0x1C++0x03
line.long 0x00 "SNTCFG3,SRAM/NOR flash timing configuration register 3"
bitfld.long 0x00 28.--29. "ASYNCMOD,Asynchronous access mode" "0,1,2,3"
bitfld.long 0x00 24.--27. "DLAT,Data latency for NOR Flash" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "CKDIV,Synchronous clock divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "BUSLAT,Bus latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 8.--15. 1. "DSET,Data setup time"
bitfld.long 0x00 4.--7. "AHLD,Address hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "ASET,Address setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x08 0x10 0x18 )
group.long ($2+0x104)++0x03
line.long 0x00 "SNWTCFG$1,SRAM/NOR flash write timing configuration register $1"
bitfld.long 0x00 28.--29. "WASYNCMOD,Asynchronous access mode" "0,1,2,3"
bitfld.long 0x00 16.--19. "WBUSLAT,Bus latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "WDSET,Data setup time"
bitfld.long 0x00 4.--7. "WAHLD,Address hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "WASET,Address setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat.end
repeat 3. (strings "1" "2" "3" )(list 0x0 0x20 0x40 )
group.long ($2+0x60)++0x03
line.long 0x00 "NPCTL$1,NAND flash/PC card control register $1"
bitfld.long 0x00 17.--19. "ECCSZ,ECC size" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13.--16. "ATR,ALE to RE delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 9.--12. "CTR,CLE to RE delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "ECCEN,ECC enable" "0,1"
newline
bitfld.long 0x00 4.--5. "NDW,NAND bank memory data bus width" "0,1,2,3"
bitfld.long 0x00 3. "NDTP,NAND bank memory type" "0,1"
bitfld.long 0x00 2. "NDBKEN,NAND bank enable" "0,1"
bitfld.long 0x00 1. "NDWTEN,Wait feature enable" "0,1"
repeat.end
repeat 3. (strings "1" "2" "3" )(list 0x0 0x20 0x40 )
group.long ($2+0x64)++0x03
line.long 0x00 "NPINTEN$1,NAND flash/PC card interrupt enable register $1"
bitfld.long 0x00 6. "FFEPT,FIFO empty flag" "0,1"
bitfld.long 0x00 5. "INTFEN,Interrupt falling edge detection enable" "0,1"
bitfld.long 0x00 4. "INTHEN,Interrupt high-level detection enable" "0,1"
bitfld.long 0x00 3. "INTREN,Interrupt rising edge detection enable bit" "0,1"
newline
bitfld.long 0x00 2. "INTFS,Interrupt falling edge status" "0,1"
bitfld.long 0x00 1. "INTHS,Interrupt high-level status" "0,1"
bitfld.long 0x00 0. "INTRS,Interrupt rising edge status" "0,1"
repeat.end
repeat 3. (strings "1" "2" "3" )(list 0x0 0x20 0x40 )
group.long ($2+0x68)++0x03
line.long 0x00 "NPCTCFG$1,NAND flash/PC card common space timing configuration register $1"
hexmask.long.byte 0x00 24.--31. 1. "COMHIZ,Common memory data bus HiZ time"
hexmask.long.byte 0x00 16.--23. 1. "COMHLD,Common memory hold time"
hexmask.long.byte 0x00 8.--15. 1. "COMWAIT,Common memory wait time"
hexmask.long.byte 0x00 0.--7. 1. "COMSET,Common memory setup time"
repeat.end
repeat 3. (strings "1" "2" "3" )(list 0x0 0x20 0x40 )
group.long ($2+0x6C)++0x03
line.long 0x00 "NPATCFG$1,NAND flash/PC card attribute space timing configuration register $1"
hexmask.long.byte 0x00 24.--31. 1. "ATTHIZ,Attribute memory data bus HiZ time"
hexmask.long.byte 0x00 16.--23. 1. "ATTHLD,Attribute memory hold time"
hexmask.long.byte 0x00 8.--15. 1. "ATTWAIT,Attribute memory wait time"
hexmask.long.byte 0x00 0.--7. 1. "ATTSET,Attribute memory setup time"
repeat.end
group.long 0xB0++0x03
line.long 0x00 "PIOTCFG3,PC card I/O space timing configuration register"
hexmask.long.byte 0x00 24.--31. 1. "IOHIZ,IO space data bus HiZ time"
hexmask.long.byte 0x00 16.--23. 1. "IOHLD,IO space hold time"
hexmask.long.byte 0x00 8.--15. 1. "IOWAIT,IO space wait time"
hexmask.long.byte 0x00 0.--7. 1. "IOSET,IO space setup time"
repeat 2. (strings "1" "2" )(list 0x0 0x20 )
group.long ($2+0x74)++0x03
line.long 0x00 "NECC$1,NAND flash ECC register $1"
hexmask.long 0x00 0.--31. 1. "ECC,ECC result"
repeat.end
tree.end
tree "EXTI (External interrupt/event controller)"
base ad:0x40010400
group.long 0x00++0x03
line.long 0x00 "INTEN,Interrupt enable register (EXTI_INTEN)"
bitfld.long 0x00 21. "INTEN21,Enable Interrupt on line 21" "0,1"
bitfld.long 0x00 20. "INTEN20,Enable Interrupt on line 20" "0,1"
bitfld.long 0x00 19. "INTEN19,Enable Interrupt on line 19" "0,1"
bitfld.long 0x00 18. "INTEN18,Enable Interrupt on line 18" "0,1"
newline
bitfld.long 0x00 17. "INTEN17,Enable Interrupt on line 17" "0,1"
bitfld.long 0x00 16. "INTEN16,Enable Interrupt on line 16" "0,1"
bitfld.long 0x00 15. "INTEN15,Enable Interrupt on line 15" "0,1"
bitfld.long 0x00 14. "INTEN14,Enable Interrupt on line 14" "0,1"
newline
bitfld.long 0x00 13. "INTEN13,Enable Interrupt on line 13" "0,1"
bitfld.long 0x00 12. "INTEN12,Enable Interrupt on line 12" "0,1"
bitfld.long 0x00 11. "INTEN11,Enable Interrupt on line 11" "0,1"
bitfld.long 0x00 10. "INTEN10,Enable Interrupt on line 10" "0,1"
newline
bitfld.long 0x00 9. "INTEN9,Enable Interrupt on line 9" "0,1"
bitfld.long 0x00 8. "INTEN8,Enable Interrupt on line 8" "0,1"
bitfld.long 0x00 7. "INTEN7,Enable Interrupt on line 7" "0,1"
bitfld.long 0x00 6. "INTEN6,Enable Interrupt on line 6" "0,1"
newline
bitfld.long 0x00 5. "INTEN5,Enable Interrupt on line 5" "0,1"
bitfld.long 0x00 4. "INTEN4,Enable Interrupt on line 4" "0,1"
bitfld.long 0x00 3. "INTEN3,Enable Interrupt on line 3" "0,1"
bitfld.long 0x00 2. "INTEN2,Enable Interrupt on line 2" "0,1"
newline
bitfld.long 0x00 1. "INTEN1,Enable Interrupt on line 1" "0,1"
bitfld.long 0x00 0. "INTEN0,Enable Interrupt on line 0" "0,1"
group.long 0x04++0x03
line.long 0x00 "EVEN,Event enable register (EXTI_EVEN)"
bitfld.long 0x00 21. "EVEN21,Enable Event on line 21" "0,1"
bitfld.long 0x00 20. "EVEN20,Enable Event on line 20" "0,1"
bitfld.long 0x00 19. "EVEN19,Enable Event on line 19" "0,1"
bitfld.long 0x00 18. "EVEN18,Enable Event on line 18" "0,1"
newline
bitfld.long 0x00 17. "EVEN17,Enable Event on line 17" "0,1"
bitfld.long 0x00 16. "EVEN16,Enable Event on line 16" "0,1"
bitfld.long 0x00 15. "EVEN15,Enable Event on line 15" "0,1"
bitfld.long 0x00 14. "EVEN14,Enable Event on line 14" "0,1"
newline
bitfld.long 0x00 13. "EVEN13,Enable Event on line 13" "0,1"
bitfld.long 0x00 12. "EVEN12,Enable Event on line 12" "0,1"
bitfld.long 0x00 11. "EVEN11,Enable Event on line 11" "0,1"
bitfld.long 0x00 10. "EVEN10,Enable Event on line 10" "0,1"
newline
bitfld.long 0x00 9. "EVEN9,Enable Event on line 9" "0,1"
bitfld.long 0x00 8. "EVEN8,Enable Event on line 8" "0,1"
bitfld.long 0x00 7. "EVEN7,Enable Event on line 7" "0,1"
bitfld.long 0x00 6. "EVEN6,Enable Event on line 6" "0,1"
newline
bitfld.long 0x00 5. "EVEN5,Enable Event on line 5" "0,1"
bitfld.long 0x00 4. "EVEN4,Enable Event on line 4" "0,1"
bitfld.long 0x00 3. "EVEN3,Enable Event on line 3" "0,1"
bitfld.long 0x00 2. "EVEN2,Enable Event on line 2" "0,1"
newline
bitfld.long 0x00 1. "EVEN1,Enable Event on line 1" "0,1"
bitfld.long 0x00 0. "EVEN0,Enable Event on line 0" "0,1"
group.long 0x08++0x03
line.long 0x00 "RTEN,Rising Edge Trigger Enable register (EXTI_RTEN)"
bitfld.long 0x00 21. "RTEN21,Rising edge trigger enable of line 21" "0,1"
bitfld.long 0x00 20. "RTEN20,Rising edge trigger enable of line 20" "0,1"
bitfld.long 0x00 19. "RTEN19,Rising edge trigger enable of line 19" "0,1"
bitfld.long 0x00 18. "RTEN18,Rising edge trigger enable of line 18" "0,1"
newline
bitfld.long 0x00 17. "RTEN17,Rising edge trigger enable of line 17" "0,1"
bitfld.long 0x00 16. "RTEN16,Rising edge trigger enable of line 16" "0,1"
bitfld.long 0x00 15. "RTEN15,Rising edge trigger enable of line 15" "0,1"
bitfld.long 0x00 14. "RTEN14,Rising edge trigger enable of line 14" "0,1"
newline
bitfld.long 0x00 13. "RTEN13,Rising edge trigger enable of line 13" "0,1"
bitfld.long 0x00 12. "RTEN12,Rising edge trigger enable of line 12" "0,1"
bitfld.long 0x00 11. "RTEN11,Rising edge trigger enable of line 11" "0,1"
bitfld.long 0x00 10. "RTEN10,Rising edge trigger enable of line 10" "0,1"
newline
bitfld.long 0x00 9. "RTEN9,Rising edge trigger enable of line 9" "0,1"
bitfld.long 0x00 8. "RTEN8,Rising edge trigger enable of line 8" "0,1"
bitfld.long 0x00 7. "RTEN7,Rising edge trigger enable of line 7" "0,1"
bitfld.long 0x00 6. "RTEN6,Rising edge trigger enable of line 6" "0,1"
newline
bitfld.long 0x00 5. "RTEN5,Rising edge trigger enable of line 5" "0,1"
bitfld.long 0x00 4. "RTEN4,Rising edge trigger enable of line 4" "0,1"
bitfld.long 0x00 3. "RTEN3,Rising edge trigger enable of line 3" "0,1"
bitfld.long 0x00 2. "RTEN2,Rising edge trigger enable of line 2" "0,1"
newline
bitfld.long 0x00 1. "RTEN1,Rising edge trigger enable of line 1" "0,1"
bitfld.long 0x00 0. "RTEN0,Rising edge trigger enable of line 0" "0,1"
group.long 0x0C++0x03
line.long 0x00 "FTEN,Falling Egde Trigger Enable register (EXTI_FTEN)"
bitfld.long 0x00 21. "FTEN21,Falling edge trigger enable of line 21" "0,1"
bitfld.long 0x00 20. "FTEN20,Falling edge trigger enable of line 20" "0,1"
bitfld.long 0x00 19. "FTEN19,Falling edge trigger enable of line 19" "0,1"
bitfld.long 0x00 18. "FTEN18,Falling edge trigger enable of line 18" "0,1"
newline
bitfld.long 0x00 17. "FTEN17,Falling edge trigger enable of line 17" "0,1"
bitfld.long 0x00 16. "FTEN16,Falling edge trigger enable of line 16" "0,1"
bitfld.long 0x00 15. "FTEN15,Falling edge trigger enable of line 15" "0,1"
bitfld.long 0x00 14. "FTEN14,Falling edge trigger enable of line 14" "0,1"
newline
bitfld.long 0x00 13. "FTEN13,Falling edge trigger enable of line 13" "0,1"
bitfld.long 0x00 12. "FTEN12,Falling edge trigger enable of line 12" "0,1"
bitfld.long 0x00 11. "FTEN11,Falling edge trigger enable of line 11" "0,1"
bitfld.long 0x00 10. "FTEN10,Falling edge trigger enable of line 10" "0,1"
newline
bitfld.long 0x00 9. "FTEN9,Falling edge trigger enable of line 9" "0,1"
bitfld.long 0x00 8. "FTEN8,Falling edge trigger enable of line 8" "0,1"
bitfld.long 0x00 7. "FTEN7,Falling edge trigger enable of line 7" "0,1"
bitfld.long 0x00 6. "FTEN6,Falling edge trigger enable of line 6" "0,1"
newline
bitfld.long 0x00 5. "FTEN5,Falling edge trigger enable of line 5" "0,1"
bitfld.long 0x00 4. "FTEN4,Falling edge trigger enable of line 4" "0,1"
bitfld.long 0x00 3. "FTEN3,Falling edge trigger enable of line 3" "0,1"
bitfld.long 0x00 2. "FTEN2,Falling edge trigger enable of line 2" "0,1"
newline
bitfld.long 0x00 1. "FTEN1,Falling edge trigger enable of line 1" "0,1"
bitfld.long 0x00 0. "FTEN0,Falling edge trigger enable of line 0" "0,1"
group.long 0x10++0x03
line.long 0x00 "SWIEV,Software interrupt event register (EXTI_SWIEV)"
bitfld.long 0x00 21. "SWIEV21,Interrupt/Event software trigger on line 21" "0,1"
bitfld.long 0x00 20. "SWIEV20,Interrupt/Event software trigger on line 20" "0,1"
bitfld.long 0x00 19. "SWIEV19,Interrupt/Event software trigger on line 19" "0,1"
bitfld.long 0x00 18. "SWIEV18,Interrupt/Event software trigger on line 18" "0,1"
newline
bitfld.long 0x00 17. "SWIEV17,Interrupt/Event software trigger on line 17" "0,1"
bitfld.long 0x00 16. "SWIEV16,Interrupt/Event software trigger on line 16" "0,1"
bitfld.long 0x00 15. "SWIEV15,Interrupt/Event software trigger on line 15" "0,1"
bitfld.long 0x00 14. "SWIEV14,Interrupt/Event software trigger on line 14" "0,1"
newline
bitfld.long 0x00 13. "SWIEV13,Interrupt/Event software trigger on line 13" "0,1"
bitfld.long 0x00 12. "SWIEV12,Interrupt/Event software trigger on line 12" "0,1"
bitfld.long 0x00 11. "SWIEV11,Interrupt/Event software trigger on line 11" "0,1"
bitfld.long 0x00 10. "SWIEV10,Interrupt/Event software trigger on line 10" "0,1"
newline
bitfld.long 0x00 9. "SWIEV9,Interrupt/Event software trigger on line 9" "0,1"
bitfld.long 0x00 8. "SWIEV8,Interrupt/Event software trigger on line 8" "0,1"
bitfld.long 0x00 7. "SWIEV7,Interrupt/Event software trigger on line 7" "0,1"
bitfld.long 0x00 6. "SWIEV6,Interrupt/Event software trigger on line 6" "0,1"
newline
bitfld.long 0x00 5. "SWIEV5,Interrupt/Event software trigger on line 5" "0,1"
bitfld.long 0x00 4. "SWIEV4,Interrupt/Event software trigger on line 4" "0,1"
bitfld.long 0x00 3. "SWIEV3,Interrupt/Event software trigger on line 3" "0,1"
bitfld.long 0x00 2. "SWIEV2,Interrupt/Event software trigger on line 2" "0,1"
newline
bitfld.long 0x00 1. "SWIEV1,Interrupt/Event software trigger on line 1" "0,1"
bitfld.long 0x00 0. "SWIEV0,Interrupt/Event software trigger on line 0" "0,1"
group.long 0x14++0x03
line.long 0x00 "PD,Pending register (EXTI_PD)"
bitfld.long 0x00 21. "PD21,Interrupt pending status of line 21" "0,1"
bitfld.long 0x00 20. "PD20,Interrupt pending status of line 20" "0,1"
bitfld.long 0x00 19. "PD19,Interrupt pending status of line 19" "0,1"
bitfld.long 0x00 18. "PD18,Interrupt pending status of line 18" "0,1"
newline
bitfld.long 0x00 17. "PD17,Interrupt pending status of line 17" "0,1"
bitfld.long 0x00 16. "PD16,Interrupt pending status of line 16" "0,1"
bitfld.long 0x00 15. "PD15,Interrupt pending status of line 15" "0,1"
bitfld.long 0x00 14. "PD14,Interrupt pending status of line 14" "0,1"
newline
bitfld.long 0x00 13. "PD13,Interrupt pending status of line 13" "0,1"
bitfld.long 0x00 12. "PD12,Interrupt pending status of line 12" "0,1"
bitfld.long 0x00 11. "PD11,Interrupt pending status of line 11" "0,1"
bitfld.long 0x00 10. "PD10,Interrupt pending status of line 10" "0,1"
newline
bitfld.long 0x00 9. "PD9,Interrupt pending status of line 9" "0,1"
bitfld.long 0x00 8. "PD8,Interrupt pending status of line 8" "0,1"
bitfld.long 0x00 7. "PD7,Interrupt pending status of line 7" "0,1"
bitfld.long 0x00 6. "PD6,Interrupt pending status of line 6" "0,1"
newline
bitfld.long 0x00 5. "PD5,Interrupt pending status of line 5" "0,1"
bitfld.long 0x00 4. "PD4,Interrupt pending status of line 4" "0,1"
bitfld.long 0x00 3. "PD3,Interrupt pending status of line 3" "0,1"
bitfld.long 0x00 2. "PD2,Interrupt pending status of line 2" "0,1"
newline
bitfld.long 0x00 1. "PD1,Interrupt pending status of line 1" "0,1"
bitfld.long 0x00 0. "PD0,Interrupt pending status of line 0" "0,1"
tree.end
tree "FMC"
base ad:0x40022000
group.long 0x00++0x03
line.long 0x00 "WS,wait state counter register"
bitfld.long 0x00 12. "DCRST,DBUS cache reset" "0,1"
bitfld.long 0x00 11. "ICRST,IBUS cache reset" "0,1"
bitfld.long 0x00 10. "DCEN,DBUS cache enable" "0,1"
bitfld.long 0x00 9. "ICEN,IBUS cache enable" "0,1"
newline
bitfld.long 0x00 4. "PFEN,Pre-fetch enable" "0,1"
bitfld.long 0x00 0.--2. "WSCNT,wait state counter register" "0,1,2,3,4,5,6,7"
wgroup.long 0x04++0x03
line.long 0x00 "KEY,Unlock key register"
hexmask.long 0x00 0.--31. 1. "KEY,FMC_CTL unlock register"
wgroup.long 0x08++0x03
line.long 0x00 "OBKEY,Option byte unlock key register"
hexmask.long 0x00 0.--31. 1. "OBKEY,FMC_ OBCTL0 option byte operation unlock register"
group.long 0x0C++0x03
line.long 0x00 "STAT,Status register"
bitfld.long 0x00 5. "ENDF,End of operation flag bit" "0,1"
bitfld.long 0x00 4. "WPERR,Erase/Program protection error flag bit" "0,1"
bitfld.long 0x00 3. "PGAERR,Program alignment error flag bit" "0,1"
bitfld.long 0x00 2. "PGERR,Program error flag bit" "0,1"
newline
rbitfld.long 0x00 0. "BUSY,The flash is busy bit" "0,1"
group.long 0x10++0x03
line.long 0x00 "CTL,Control register"
bitfld.long 0x00 12. "ENDIE,End of operation interrupt enable bit" "0,1"
bitfld.long 0x00 10. "ERRIE,Error interrupt enable bit" "0,1"
bitfld.long 0x00 9. "OBWEN,Option byte erase/program enable bit" "0,1"
bitfld.long 0x00 7. "LK,FMC_CTL0 lock bit" "0,1"
newline
bitfld.long 0x00 6. "START,Send erase command to FMC bit" "0,1"
bitfld.long 0x00 5. "OBER,Option bytes erase command bit" "0,1"
bitfld.long 0x00 4. "OBPG,Option bytes program command bit" "0,1"
bitfld.long 0x00 2. "MER,Main flash mass erase for bank0 command bit" "0,1"
newline
bitfld.long 0x00 1. "PER,Main flash page erase for bank0 command bit" "0,1"
bitfld.long 0x00 0. "PG,Main flash program for bank0 command bit" "0,1"
wgroup.long 0x14++0x03
line.long 0x00 "ADDR,Address register"
hexmask.long 0x00 0.--31. 1. "ADDR,Flash erase/program command address bits"
rgroup.long 0x1C++0x03
line.long 0x00 "OBSTAT,Option byte status register"
hexmask.long.word 0x00 10.--25. 1. "DATA,Store DATA[15:0] of option bytes block after system reset"
hexmask.long.byte 0x00 2.--9. 1. "USER,Store USER of option bytes block after system reset"
bitfld.long 0x00 1. "SPC,Option bytes security protection code" "0,1"
bitfld.long 0x00 0. "OBERR,Option bytes read error bit" "0,1"
rgroup.long 0x20++0x03
line.long 0x00 "WP,Erase/Program Protection register"
hexmask.long 0x00 0.--31. 1. "WP,Store WP[31:0] of option bytes block after system reset"
rgroup.long 0x100++0x03
line.long 0x00 "PID,Product ID register"
hexmask.long 0x00 0.--31. 1. "PID,Product reserved ID code register"
tree.end
tree "FWDGT (free watchdog timer)"
base ad:0x40003000
wgroup.long 0x00++0x03
line.long 0x00 "CTL,Control register"
hexmask.long.word 0x00 0.--15. 1. "CMD,Key value"
group.long 0x04++0x03
line.long 0x00 "PSC,Prescaler register"
bitfld.long 0x00 0.--2. "PSC,Free watchdog timer prescaler selection" "0,1,2,3,4,5,6,7"
group.long 0x08++0x03
line.long 0x00 "RLD,Reload register"
hexmask.long.word 0x00 0.--11. 1. "RLD,Free watchdog timer counter reload value"
rgroup.long 0x0C++0x03
line.long 0x00 "STAT,Status register"
bitfld.long 0x00 1. "RUD,Free watchdog timer counter reload value update" "0,1"
bitfld.long 0x00 0. "PUD,Free watchdog timer prescaler value update" "0,1"
tree.end
tree "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"
tree "GPIOA"
base ad:0x40010800
group.long 0x00++0x03
line.long 0x00 "CTL0,port control register 0"
bitfld.long 0x00 30.--31. "CTL7,Port x configuration bits (x = 7)" "0,1,2,3"
bitfld.long 0x00 28.--29. "MD7,Port x mode bits (x = 7)" "0,1,2,3"
bitfld.long 0x00 26.--27. "CTL6,Port x configuration bits (x = 6)" "0,1,2,3"
bitfld.long 0x00 24.--25. "MD6,Port x mode bits (x = 6)" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "CTL5,Port x configuration bits (x = 5)" "0,1,2,3"
bitfld.long 0x00 20.--21. "MD5,Port x mode bits (x = 5)" "0,1,2,3"
bitfld.long 0x00 18.--19. "CTL4,Port x configuration bits (x = 4)" "0,1,2,3"
bitfld.long 0x00 16.--17. "MD4,Port x mode bits (x = 4)" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "CTL3,Port x configuration bits (x = 3)" "0,1,2,3"
bitfld.long 0x00 12.--13. "MD3,Port x mode bits (x = 3 )" "0,1,2,3"
bitfld.long 0x00 10.--11. "CTL2,Port x configuration bits (x = 2)" "0,1,2,3"
bitfld.long 0x00 8.--9. "MD2,Port x mode bits (x = 2 )" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "CTL1,Port x configuration bits (x = 1)" "0,1,2,3"
bitfld.long 0x00 4.--5. "MD1,Port x mode bits (x = 1)" "0,1,2,3"
bitfld.long 0x00 2.--3. "CTL0,Port x configuration bits (x = 0)" "0,1,2,3"
bitfld.long 0x00 0.--1. "MD0,Port x mode bits (x = 0)" "0,1,2,3"
group.long 0x04++0x03
line.long 0x00 "CTL1,port control register 1"
bitfld.long 0x00 30.--31. "CTL15,Port x configuration bits (x = 15)" "0,1,2,3"
bitfld.long 0x00 28.--29. "MD15,Port x mode bits (x = 15)" "0,1,2,3"
bitfld.long 0x00 26.--27. "CTL14,Port x configuration bits (x = 14)" "0,1,2,3"
bitfld.long 0x00 24.--25. "MD14,Port x mode bits (x = 14)" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "CTL13,Port x configuration bits (x = 13)" "0,1,2,3"
bitfld.long 0x00 20.--21. "MD13,Port x mode bits (x = 13)" "0,1,2,3"
bitfld.long 0x00 18.--19. "CTL12,Port x configuration bits (x = 12)" "0,1,2,3"
bitfld.long 0x00 16.--17. "MD12,Port x mode bits (x = 12)" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "CTL11,Port x configuration bits (x = 11)" "0,1,2,3"
bitfld.long 0x00 12.--13. "MD11,Port x mode bits (x = 11 )" "0,1,2,3"
bitfld.long 0x00 10.--11. "CTL10,Port x configuration bits (x = 10)" "0,1,2,3"
bitfld.long 0x00 8.--9. "MD10,Port x mode bits (x = 10 )" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "CTL9,Port x configuration bits (x = 9)" "0,1,2,3"
bitfld.long 0x00 4.--5. "MD9,Port x mode bits (x = 9)" "0,1,2,3"
bitfld.long 0x00 2.--3. "CTL8,Port x configuration bits (x = 8)" "0,1,2,3"
bitfld.long 0x00 0.--1. "MD8,Port x mode bits (x = 8)" "0,1,2,3"
rgroup.long 0x08++0x03
line.long 0x00 "ISTAT,Port input status register"
bitfld.long 0x00 15. "ISTAT15,Port input status" "0,1"
bitfld.long 0x00 14. "ISTAT14,Port input status" "0,1"
bitfld.long 0x00 13. "ISTAT13,Port input status" "0,1"
bitfld.long 0x00 12. "ISTAT12,Port input status" "0,1"
newline
bitfld.long 0x00 11. "ISTAT11,Port input status" "0,1"
bitfld.long 0x00 10. "ISTAT10,Port input status" "0,1"
bitfld.long 0x00 9. "ISTAT9,Port input status" "0,1"
bitfld.long 0x00 8. "ISTAT8,Port input status" "0,1"
newline
bitfld.long 0x00 7. "ISTAT7,Port input status" "0,1"
bitfld.long 0x00 6. "ISTAT6,Port input status" "0,1"
bitfld.long 0x00 5. "ISTAT5,Port input status" "0,1"
bitfld.long 0x00 4. "ISTAT4,Port input status" "0,1"
newline
bitfld.long 0x00 3. "ISTAT3,Port input status" "0,1"
bitfld.long 0x00 2. "ISTAT2,Port input status" "0,1"
bitfld.long 0x00 1. "ISTAT1,Port input status" "0,1"
bitfld.long 0x00 0. "ISTAT0,Port input status" "0,1"
group.long 0x0C++0x03
line.long 0x00 "OCTL,Port output control register"
bitfld.long 0x00 15. "OCTL15,Port output control" "0,1"
bitfld.long 0x00 14. "OCTL14,Port output control" "0,1"
bitfld.long 0x00 13. "OCTL13,Port output control" "0,1"
bitfld.long 0x00 12. "OCTL12,Port output control" "0,1"
newline
bitfld.long 0x00 11. "OCTL11,Port output control" "0,1"
bitfld.long 0x00 10. "OCTL10,Port output control" "0,1"
bitfld.long 0x00 9. "OCTL9,Port output control" "0,1"
bitfld.long 0x00 8. "OCTL8,Port output control" "0,1"
newline
bitfld.long 0x00 7. "OCTL7,Port output control" "0,1"
bitfld.long 0x00 6. "OCTL6,Port output control" "0,1"
bitfld.long 0x00 5. "OCTL5,Port output control" "0,1"
bitfld.long 0x00 4. "OCTL4,Port output control" "0,1"
newline
bitfld.long 0x00 3. "OCTL3,Port output control" "0,1"
bitfld.long 0x00 2. "OCTL2,Port output control" "0,1"
bitfld.long 0x00 1. "OCTL1,Port output control" "0,1"
bitfld.long 0x00 0. "OCTL0,Port output control" "0,1"
wgroup.long 0x10++0x03
line.long 0x00 "BOP,Port bit operate register"
bitfld.long 0x00 31. "CR15,Port 15 Clear bit" "0,1"
bitfld.long 0x00 30. "CR14,Port 14 Clear bit" "0,1"
bitfld.long 0x00 29. "CR13,Port 13 Clear bit" "0,1"
bitfld.long 0x00 28. "CR12,Port 12 Clear bit" "0,1"
newline
bitfld.long 0x00 27. "CR11,Port 11 Clear bit" "0,1"
bitfld.long 0x00 26. "CR10,Port 10 Clear bit" "0,1"
bitfld.long 0x00 25. "CR9,Port 9 Clear bit" "0,1"
bitfld.long 0x00 24. "CR8,Port 8 Clear bit" "0,1"
newline
bitfld.long 0x00 23. "CR7,Port 7 Clear bit" "0,1"
bitfld.long 0x00 22. "CR6,Port 6 Clear bit" "0,1"
bitfld.long 0x00 21. "CR5,Port 5 Clear bit" "0,1"
bitfld.long 0x00 20. "CR4,Port 4 Clear bit" "0,1"
newline
bitfld.long 0x00 19. "CR3,Port 3 Clear bit" "0,1"
bitfld.long 0x00 18. "CR2,Port 2 Clear bit" "0,1"
bitfld.long 0x00 17. "CR1,Port 1 Clear bit" "0,1"
bitfld.long 0x00 16. "CR0,Port 0 Clear bit" "0,1"
newline
bitfld.long 0x00 15. "BOP15,Port 15 Set bit" "0,1"
bitfld.long 0x00 14. "BOP14,Port 14 Set bit" "0,1"
bitfld.long 0x00 13. "BOP13,Port 13 Set bit" "0,1"
bitfld.long 0x00 12. "BOP12,Port 12 Set bit" "0,1"
newline
bitfld.long 0x00 11. "BOP11,Port 11 Set bit" "0,1"
bitfld.long 0x00 10. "BOP10,Port 10 Set bit" "0,1"
bitfld.long 0x00 9. "BOP9,Port 9 Set bit" "0,1"
bitfld.long 0x00 8. "BOP8,Port 8 Set bit" "0,1"
newline
bitfld.long 0x00 7. "BOP7,Port 7 Set bit" "0,1"
bitfld.long 0x00 6. "BOP6,Port 6 Set bit" "0,1"
bitfld.long 0x00 5. "BOP5,Port 5 Set bit" "0,1"
bitfld.long 0x00 4. "BOP4,Port 4 Set bit" "0,1"
newline
bitfld.long 0x00 3. "BOP3,Port 3 Set bit" "0,1"
bitfld.long 0x00 2. "BOP2,Port 2 Set bit" "0,1"
bitfld.long 0x00 1. "BOP1,Port 1 Set bit" "0,1"
bitfld.long 0x00 0. "BOP0,Port 0 Set bit" "0,1"
wgroup.long 0x14++0x03
line.long 0x00 "BC,Port bit clear register"
bitfld.long 0x00 15. "CR15,Port 15 Clear bit" "0,1"
bitfld.long 0x00 14. "CR14,Port 14 Clear bit" "0,1"
bitfld.long 0x00 13. "CR13,Port 13 Clear bit" "0,1"
bitfld.long 0x00 12. "CR12,Port 12 Clear bit" "0,1"
newline
bitfld.long 0x00 11. "CR11,Port 11 Clear bit" "0,1"
bitfld.long 0x00 10. "CR10,Port 10 Clear bit" "0,1"
bitfld.long 0x00 9. "CR9,Port 9 Clear bit" "0,1"
bitfld.long 0x00 8. "CR8,Port 8 Clear bit" "0,1"
newline
bitfld.long 0x00 7. "CR7,Port 7 Clear bit" "0,1"
bitfld.long 0x00 6. "CR6,Port 6 Clear bit" "0,1"
bitfld.long 0x00 5. "CR5,Port 5 Clear bit" "0,1"
bitfld.long 0x00 4. "CR4,Port 4 Clear bit" "0,1"
newline
bitfld.long 0x00 3. "CR3,Port 3 Clear bit" "0,1"
bitfld.long 0x00 2. "CR2,Port 2 Clear bit" "0,1"
bitfld.long 0x00 1. "CR1,Port 1 Clear bit" "0,1"
bitfld.long 0x00 0. "CR0,Port 0 Clear bit" "0,1"
group.long 0x18++0x03
line.long 0x00 "LOCK,GPIO port configuration lock register"
bitfld.long 0x00 16. "LKK,Lock sequence key" "0,1"
bitfld.long 0x00 15. "LK15,Port Lock bit 15" "0,1"
bitfld.long 0x00 14. "LK14,Port Lock bit 14" "0,1"
bitfld.long 0x00 13. "LK13,Port Lock bit 13" "0,1"
newline
bitfld.long 0x00 12. "LK12,Port Lock bit 12" "0,1"
bitfld.long 0x00 11. "LK11,Port Lock bit 11" "0,1"
bitfld.long 0x00 10. "LK10,Port Lock bit 10" "0,1"
bitfld.long 0x00 9. "LK9,Port Lock bit 9" "0,1"
newline
bitfld.long 0x00 8. "LK8,Port Lock bit 8" "0,1"
bitfld.long 0x00 7. "LK7,Port Lock bit 7" "0,1"
bitfld.long 0x00 6. "LK6,Port Lock bit 6" "0,1"
bitfld.long 0x00 5. "LK5,Port Lock bit 5" "0,1"
newline
bitfld.long 0x00 4. "LK4,Port Lock bit 4" "0,1"
bitfld.long 0x00 3. "LK3,Port Lock bit 3" "0,1"
bitfld.long 0x00 2. "LK2,Port Lock bit 2" "0,1"
bitfld.long 0x00 1. "LK1,Port Lock bit 1" "0,1"
newline
bitfld.long 0x00 0. "LK0,Port Lock bit 0" "0,1"
group.long 0x3C++0x03
line.long 0x00 "SPD,Port bit speed register"
bitfld.long 0x00 15. "SPD15,Port 15 output max speed bits" "0,1"
bitfld.long 0x00 14. "SPD14,Port 14 output max speed bits" "0,1"
bitfld.long 0x00 13. "SPD13,Port 13 output max speed bits" "0,1"
bitfld.long 0x00 12. "SPD12,Port 12 output max speed bits" "0,1"
newline
bitfld.long 0x00 11. "SPD11,Port 11 output max speed bits" "0,1"
bitfld.long 0x00 10. "SPD10,Port 10 output max speed bits" "0,1"
bitfld.long 0x00 9. "SPD9,Port 9 output max speed bits" "0,1"
bitfld.long 0x00 8. "SPD8,Port 8 output max speed bits" "0,1"
newline
bitfld.long 0x00 7. "SPD7,Port 7 output max speed bits" "0,1"
bitfld.long 0x00 6. "SPD6,Port 6 output max speed bits" "0,1"
bitfld.long 0x00 5. "SPD5,Port 5 output max speed bits" "0,1"
bitfld.long 0x00 4. "SPD4,Port 4 output max speed bits" "0,1"
newline
bitfld.long 0x00 3. "SPD3,Port 3 output max speed bits" "0,1"
bitfld.long 0x00 2. "SPD2,Port 2 output max speed bits" "0,1"
bitfld.long 0x00 1. "SPD1,Port 1 output max speed bits" "0,1"
bitfld.long 0x00 0. "SPD0,Port 0 output max speed bits" "0,1"
tree.end
tree "GPIOB"
base ad:0x40010C00
group.long 0x00++0x03
line.long 0x00 "CTL0,port control register 0"
bitfld.long 0x00 30.--31. "CTL7,Port x configuration bits (x = 7)" "0,1,2,3"
bitfld.long 0x00 28.--29. "MD7,Port x mode bits (x = 7)" "0,1,2,3"
bitfld.long 0x00 26.--27. "CTL6,Port x configuration bits (x = 6)" "0,1,2,3"
bitfld.long 0x00 24.--25. "MD6,Port x mode bits (x = 6)" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "CTL5,Port x configuration bits (x = 5)" "0,1,2,3"
bitfld.long 0x00 20.--21. "MD5,Port x mode bits (x = 5)" "0,1,2,3"
bitfld.long 0x00 18.--19. "CTL4,Port x configuration bits (x = 4)" "0,1,2,3"
bitfld.long 0x00 16.--17. "MD4,Port x mode bits (x = 4)" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "CTL3,Port x configuration bits (x = 3)" "0,1,2,3"
bitfld.long 0x00 12.--13. "MD3,Port x mode bits (x = 3 )" "0,1,2,3"
bitfld.long 0x00 10.--11. "CTL2,Port x configuration bits (x = 2)" "0,1,2,3"
bitfld.long 0x00 8.--9. "MD2,Port x mode bits (x = 2 )" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "CTL1,Port x configuration bits (x = 1)" "0,1,2,3"
bitfld.long 0x00 4.--5. "MD1,Port x mode bits (x = 1)" "0,1,2,3"
bitfld.long 0x00 2.--3. "CTL0,Port x configuration bits (x = 0)" "0,1,2,3"
bitfld.long 0x00 0.--1. "MD0,Port x mode bits (x = 0)" "0,1,2,3"
group.long 0x04++0x03
line.long 0x00 "CTL1,port control register 1"
bitfld.long 0x00 30.--31. "CTL15,Port x configuration bits (x = 15)" "0,1,2,3"
bitfld.long 0x00 28.--29. "MD15,Port x mode bits (x = 15)" "0,1,2,3"
bitfld.long 0x00 26.--27. "CTL14,Port x configuration bits (x = 14)" "0,1,2,3"
bitfld.long 0x00 24.--25. "MD14,Port x mode bits (x = 14)" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "CTL13,Port x configuration bits (x = 13)" "0,1,2,3"
bitfld.long 0x00 20.--21. "MD13,Port x mode bits (x = 13)" "0,1,2,3"
bitfld.long 0x00 18.--19. "CTL12,Port x configuration bits (x = 12)" "0,1,2,3"
bitfld.long 0x00 16.--17. "MD12,Port x mode bits (x = 12)" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "CTL11,Port x configuration bits (x = 11)" "0,1,2,3"
bitfld.long 0x00 12.--13. "MD11,Port x mode bits (x = 11 )" "0,1,2,3"
bitfld.long 0x00 10.--11. "CTL10,Port x configuration bits (x = 10)" "0,1,2,3"
bitfld.long 0x00 8.--9. "MD10,Port x mode bits (x = 10 )" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "CTL9,Port x configuration bits (x = 9)" "0,1,2,3"
bitfld.long 0x00 4.--5. "MD9,Port x mode bits (x = 9)" "0,1,2,3"
bitfld.long 0x00 2.--3. "CTL8,Port x configuration bits (x = 8)" "0,1,2,3"
bitfld.long 0x00 0.--1. "MD8,Port x mode bits (x = 8)" "0,1,2,3"
rgroup.long 0x08++0x03
line.long 0x00 "ISTAT,Port input status register"
bitfld.long 0x00 15. "ISTAT15,Port input status" "0,1"
bitfld.long 0x00 14. "ISTAT14,Port input status" "0,1"
bitfld.long 0x00 13. "ISTAT13,Port input status" "0,1"
bitfld.long 0x00 12. "ISTAT12,Port input status" "0,1"
newline
bitfld.long 0x00 11. "ISTAT11,Port input status" "0,1"
bitfld.long 0x00 10. "ISTAT10,Port input status" "0,1"
bitfld.long 0x00 9. "ISTAT9,Port input status" "0,1"
bitfld.long 0x00 8. "ISTAT8,Port input status" "0,1"
newline
bitfld.long 0x00 7. "ISTAT7,Port input status" "0,1"
bitfld.long 0x00 6. "ISTAT6,Port input status" "0,1"
bitfld.long 0x00 5. "ISTAT5,Port input status" "0,1"
bitfld.long 0x00 4. "ISTAT4,Port input status" "0,1"
newline
bitfld.long 0x00 3. "ISTAT3,Port input status" "0,1"
bitfld.long 0x00 2. "ISTAT2,Port input status" "0,1"
bitfld.long 0x00 1. "ISTAT1,Port input status" "0,1"
bitfld.long 0x00 0. "ISTAT0,Port input status" "0,1"
group.long 0x0C++0x03
line.long 0x00 "OCTL,Port output control register"
bitfld.long 0x00 15. "OCTL15,Port output control" "0,1"
bitfld.long 0x00 14. "OCTL14,Port output control" "0,1"
bitfld.long 0x00 13. "OCTL13,Port output control" "0,1"
bitfld.long 0x00 12. "OCTL12,Port output control" "0,1"
newline
bitfld.long 0x00 11. "OCTL11,Port output control" "0,1"
bitfld.long 0x00 10. "OCTL10,Port output control" "0,1"
bitfld.long 0x00 9. "OCTL9,Port output control" "0,1"
bitfld.long 0x00 8. "OCTL8,Port output control" "0,1"
newline
bitfld.long 0x00 7. "OCTL7,Port output control" "0,1"
bitfld.long 0x00 6. "OCTL6,Port output control" "0,1"
bitfld.long 0x00 5. "OCTL5,Port output control" "0,1"
bitfld.long 0x00 4. "OCTL4,Port output control" "0,1"
newline
bitfld.long 0x00 3. "OCTL3,Port output control" "0,1"
bitfld.long 0x00 2. "OCTL2,Port output control" "0,1"
bitfld.long 0x00 1. "OCTL1,Port output control" "0,1"
bitfld.long 0x00 0. "OCTL0,Port output control" "0,1"
wgroup.long 0x10++0x03
line.long 0x00 "BOP,Port bit operate register"
bitfld.long 0x00 31. "CR15,Port 15 Clear bit" "0,1"
bitfld.long 0x00 30. "CR14,Port 14 Clear bit" "0,1"
bitfld.long 0x00 29. "CR13,Port 13 Clear bit" "0,1"
bitfld.long 0x00 28. "CR12,Port 12 Clear bit" "0,1"
newline
bitfld.long 0x00 27. "CR11,Port 11 Clear bit" "0,1"
bitfld.long 0x00 26. "CR10,Port 10 Clear bit" "0,1"
bitfld.long 0x00 25. "CR9,Port 9 Clear bit" "0,1"
bitfld.long 0x00 24. "CR8,Port 8 Clear bit" "0,1"
newline
bitfld.long 0x00 23. "CR7,Port 7 Clear bit" "0,1"
bitfld.long 0x00 22. "CR6,Port 6 Clear bit" "0,1"
bitfld.long 0x00 21. "CR5,Port 5 Clear bit" "0,1"
bitfld.long 0x00 20. "CR4,Port 4 Clear bit" "0,1"
newline
bitfld.long 0x00 19. "CR3,Port 3 Clear bit" "0,1"
bitfld.long 0x00 18. "CR2,Port 2 Clear bit" "0,1"
bitfld.long 0x00 17. "CR1,Port 1 Clear bit" "0,1"
bitfld.long 0x00 16. "CR0,Port 0 Clear bit" "0,1"
newline
bitfld.long 0x00 15. "BOP15,Port 15 Set bit" "0,1"
bitfld.long 0x00 14. "BOP14,Port 14 Set bit" "0,1"
bitfld.long 0x00 13. "BOP13,Port 13 Set bit" "0,1"
bitfld.long 0x00 12. "BOP12,Port 12 Set bit" "0,1"
newline
bitfld.long 0x00 11. "BOP11,Port 11 Set bit" "0,1"
bitfld.long 0x00 10. "BOP10,Port 10 Set bit" "0,1"
bitfld.long 0x00 9. "BOP9,Port 9 Set bit" "0,1"
bitfld.long 0x00 8. "BOP8,Port 8 Set bit" "0,1"
newline
bitfld.long 0x00 7. "BOP7,Port 7 Set bit" "0,1"
bitfld.long 0x00 6. "BOP6,Port 6 Set bit" "0,1"
bitfld.long 0x00 5. "BOP5,Port 5 Set bit" "0,1"
bitfld.long 0x00 4. "BOP4,Port 4 Set bit" "0,1"
newline
bitfld.long 0x00 3. "BOP3,Port 3 Set bit" "0,1"
bitfld.long 0x00 2. "BOP2,Port 2 Set bit" "0,1"
bitfld.long 0x00 1. "BOP1,Port 1 Set bit" "0,1"
bitfld.long 0x00 0. "BOP0,Port 0 Set bit" "0,1"
wgroup.long 0x14++0x03
line.long 0x00 "BC,Port bit clear register"
bitfld.long 0x00 15. "CR15,Port 15 Clear bit" "0,1"
bitfld.long 0x00 14. "CR14,Port 14 Clear bit" "0,1"
bitfld.long 0x00 13. "CR13,Port 13 Clear bit" "0,1"
bitfld.long 0x00 12. "CR12,Port 12 Clear bit" "0,1"
newline
bitfld.long 0x00 11. "CR11,Port 11 Clear bit" "0,1"
bitfld.long 0x00 10. "CR10,Port 10 Clear bit" "0,1"
bitfld.long 0x00 9. "CR9,Port 9 Clear bit" "0,1"
bitfld.long 0x00 8. "CR8,Port 8 Clear bit" "0,1"
newline
bitfld.long 0x00 7. "CR7,Port 7 Clear bit" "0,1"
bitfld.long 0x00 6. "CR6,Port 6 Clear bit" "0,1"
bitfld.long 0x00 5. "CR5,Port 5 Clear bit" "0,1"
bitfld.long 0x00 4. "CR4,Port 4 Clear bit" "0,1"
newline
bitfld.long 0x00 3. "CR3,Port 3 Clear bit" "0,1"
bitfld.long 0x00 2. "CR2,Port 2 Clear bit" "0,1"
bitfld.long 0x00 1. "CR1,Port 1 Clear bit" "0,1"
bitfld.long 0x00 0. "CR0,Port 0 Clear bit" "0,1"
group.long 0x18++0x03
line.long 0x00 "LOCK,GPIO port configuration lock register"
bitfld.long 0x00 16. "LKK,Lock sequence key" "0,1"
bitfld.long 0x00 15. "LK15,Port Lock bit 15" "0,1"
bitfld.long 0x00 14. "LK14,Port Lock bit 14" "0,1"
bitfld.long 0x00 13. "LK13,Port Lock bit 13" "0,1"
newline
bitfld.long 0x00 12. "LK12,Port Lock bit 12" "0,1"
bitfld.long 0x00 11. "LK11,Port Lock bit 11" "0,1"
bitfld.long 0x00 10. "LK10,Port Lock bit 10" "0,1"
bitfld.long 0x00 9. "LK9,Port Lock bit 9" "0,1"
newline
bitfld.long 0x00 8. "LK8,Port Lock bit 8" "0,1"
bitfld.long 0x00 7. "LK7,Port Lock bit 7" "0,1"
bitfld.long 0x00 6. "LK6,Port Lock bit 6" "0,1"
bitfld.long 0x00 5. "LK5,Port Lock bit 5" "0,1"
newline
bitfld.long 0x00 4. "LK4,Port Lock bit 4" "0,1"
bitfld.long 0x00 3. "LK3,Port Lock bit 3" "0,1"
bitfld.long 0x00 2. "LK2,Port Lock bit 2" "0,1"
bitfld.long 0x00 1. "LK1,Port Lock bit 1" "0,1"
newline
bitfld.long 0x00 0. "LK0,Port Lock bit 0" "0,1"
group.long 0x3C++0x03
line.long 0x00 "SPD,Port bit speed register"
bitfld.long 0x00 15. "SPD15,Port 15 output max speed bits" "0,1"
bitfld.long 0x00 14. "SPD14,Port 14 output max speed bits" "0,1"
bitfld.long 0x00 13. "SPD13,Port 13 output max speed bits" "0,1"
bitfld.long 0x00 12. "SPD12,Port 12 output max speed bits" "0,1"
newline
bitfld.long 0x00 11. "SPD11,Port 11 output max speed bits" "0,1"
bitfld.long 0x00 10. "SPD10,Port 10 output max speed bits" "0,1"
bitfld.long 0x00 9. "SPD9,Port 9 output max speed bits" "0,1"
bitfld.long 0x00 8. "SPD8,Port 8 output max speed bits" "0,1"
newline
bitfld.long 0x00 7. "SPD7,Port 7 output max speed bits" "0,1"
bitfld.long 0x00 6. "SPD6,Port 6 output max speed bits" "0,1"
bitfld.long 0x00 5. "SPD5,Port 5 output max speed bits" "0,1"
bitfld.long 0x00 4. "SPD4,Port 4 output max speed bits" "0,1"
newline
bitfld.long 0x00 3. "SPD3,Port 3 output max speed bits" "0,1"
bitfld.long 0x00 2. "SPD2,Port 2 output max speed bits" "0,1"
bitfld.long 0x00 1. "SPD1,Port 1 output max speed bits" "0,1"
bitfld.long 0x00 0. "SPD0,Port 0 output max speed bits" "0,1"
tree.end
tree "GPIOC"
base ad:0x40011000
group.long 0x00++0x03
line.long 0x00 "CTL0,port control register 0"
bitfld.long 0x00 30.--31. "CTL7,Port x configuration bits (x = 7)" "0,1,2,3"
bitfld.long 0x00 28.--29. "MD7,Port x mode bits (x = 7)" "0,1,2,3"
bitfld.long 0x00 26.--27. "CTL6,Port x configuration bits (x = 6)" "0,1,2,3"
bitfld.long 0x00 24.--25. "MD6,Port x mode bits (x = 6)" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "CTL5,Port x configuration bits (x = 5)" "0,1,2,3"
bitfld.long 0x00 20.--21. "MD5,Port x mode bits (x = 5)" "0,1,2,3"
bitfld.long 0x00 18.--19. "CTL4,Port x configuration bits (x = 4)" "0,1,2,3"
bitfld.long 0x00 16.--17. "MD4,Port x mode bits (x = 4)" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "CTL3,Port x configuration bits (x = 3)" "0,1,2,3"
bitfld.long 0x00 12.--13. "MD3,Port x mode bits (x = 3 )" "0,1,2,3"
bitfld.long 0x00 10.--11. "CTL2,Port x configuration bits (x = 2)" "0,1,2,3"
bitfld.long 0x00 8.--9. "MD2,Port x mode bits (x = 2 )" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "CTL1,Port x configuration bits (x = 1)" "0,1,2,3"
bitfld.long 0x00 4.--5. "MD1,Port x mode bits (x = 1)" "0,1,2,3"
bitfld.long 0x00 2.--3. "CTL0,Port x configuration bits (x = 0)" "0,1,2,3"
bitfld.long 0x00 0.--1. "MD0,Port x mode bits (x = 0)" "0,1,2,3"
group.long 0x04++0x03
line.long 0x00 "CTL1,port control register 1"
bitfld.long 0x00 30.--31. "CTL15,Port x configuration bits (x = 15)" "0,1,2,3"
bitfld.long 0x00 28.--29. "MD15,Port x mode bits (x = 15)" "0,1,2,3"
bitfld.long 0x00 26.--27. "CTL14,Port x configuration bits (x = 14)" "0,1,2,3"
bitfld.long 0x00 24.--25. "MD14,Port x mode bits (x = 14)" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "CTL13,Port x configuration bits (x = 13)" "0,1,2,3"
bitfld.long 0x00 20.--21. "MD13,Port x mode bits (x = 13)" "0,1,2,3"
bitfld.long 0x00 18.--19. "CTL12,Port x configuration bits (x = 12)" "0,1,2,3"
bitfld.long 0x00 16.--17. "MD12,Port x mode bits (x = 12)" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "CTL11,Port x configuration bits (x = 11)" "0,1,2,3"
bitfld.long 0x00 12.--13. "MD11,Port x mode bits (x = 11 )" "0,1,2,3"
bitfld.long 0x00 10.--11. "CTL10,Port x configuration bits (x = 10)" "0,1,2,3"
bitfld.long 0x00 8.--9. "MD10,Port x mode bits (x = 10 )" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "CTL9,Port x configuration bits (x = 9)" "0,1,2,3"
bitfld.long 0x00 4.--5. "MD9,Port x mode bits (x = 9)" "0,1,2,3"
bitfld.long 0x00 2.--3. "CTL8,Port x configuration bits (x = 8)" "0,1,2,3"
bitfld.long 0x00 0.--1. "MD8,Port x mode bits (x = 8)" "0,1,2,3"
rgroup.long 0x08++0x03
line.long 0x00 "ISTAT,Port input status register"
bitfld.long 0x00 15. "ISTAT15,Port input status" "0,1"
bitfld.long 0x00 14. "ISTAT14,Port input status" "0,1"
bitfld.long 0x00 13. "ISTAT13,Port input status" "0,1"
bitfld.long 0x00 12. "ISTAT12,Port input status" "0,1"
newline
bitfld.long 0x00 11. "ISTAT11,Port input status" "0,1"
bitfld.long 0x00 10. "ISTAT10,Port input status" "0,1"
bitfld.long 0x00 9. "ISTAT9,Port input status" "0,1"
bitfld.long 0x00 8. "ISTAT8,Port input status" "0,1"
newline
bitfld.long 0x00 7. "ISTAT7,Port input status" "0,1"
bitfld.long 0x00 6. "ISTAT6,Port input status" "0,1"
bitfld.long 0x00 5. "ISTAT5,Port input status" "0,1"
bitfld.long 0x00 4. "ISTAT4,Port input status" "0,1"
newline
bitfld.long 0x00 3. "ISTAT3,Port input status" "0,1"
bitfld.long 0x00 2. "ISTAT2,Port input status" "0,1"
bitfld.long 0x00 1. "ISTAT1,Port input status" "0,1"
bitfld.long 0x00 0. "ISTAT0,Port input status" "0,1"
group.long 0x0C++0x03
line.long 0x00 "OCTL,Port output control register"
bitfld.long 0x00 15. "OCTL15,Port output control" "0,1"
bitfld.long 0x00 14. "OCTL14,Port output control" "0,1"
bitfld.long 0x00 13. "OCTL13,Port output control" "0,1"
bitfld.long 0x00 12. "OCTL12,Port output control" "0,1"
newline
bitfld.long 0x00 11. "OCTL11,Port output control" "0,1"
bitfld.long 0x00 10. "OCTL10,Port output control" "0,1"
bitfld.long 0x00 9. "OCTL9,Port output control" "0,1"
bitfld.long 0x00 8. "OCTL8,Port output control" "0,1"
newline
bitfld.long 0x00 7. "OCTL7,Port output control" "0,1"
bitfld.long 0x00 6. "OCTL6,Port output control" "0,1"
bitfld.long 0x00 5. "OCTL5,Port output control" "0,1"
bitfld.long 0x00 4. "OCTL4,Port output control" "0,1"
newline
bitfld.long 0x00 3. "OCTL3,Port output control" "0,1"
bitfld.long 0x00 2. "OCTL2,Port output control" "0,1"
bitfld.long 0x00 1. "OCTL1,Port output control" "0,1"
bitfld.long 0x00 0. "OCTL0,Port output control" "0,1"
wgroup.long 0x10++0x03
line.long 0x00 "BOP,Port bit operate register"
bitfld.long 0x00 31. "CR15,Port 15 Clear bit" "0,1"
bitfld.long 0x00 30. "CR14,Port 14 Clear bit" "0,1"
bitfld.long 0x00 29. "CR13,Port 13 Clear bit" "0,1"
bitfld.long 0x00 28. "CR12,Port 12 Clear bit" "0,1"
newline
bitfld.long 0x00 27. "CR11,Port 11 Clear bit" "0,1"
bitfld.long 0x00 26. "CR10,Port 10 Clear bit" "0,1"
bitfld.long 0x00 25. "CR9,Port 9 Clear bit" "0,1"
bitfld.long 0x00 24. "CR8,Port 8 Clear bit" "0,1"
newline
bitfld.long 0x00 23. "CR7,Port 7 Clear bit" "0,1"
bitfld.long 0x00 22. "CR6,Port 6 Clear bit" "0,1"
bitfld.long 0x00 21. "CR5,Port 5 Clear bit" "0,1"
bitfld.long 0x00 20. "CR4,Port 4 Clear bit" "0,1"
newline
bitfld.long 0x00 19. "CR3,Port 3 Clear bit" "0,1"
bitfld.long 0x00 18. "CR2,Port 2 Clear bit" "0,1"
bitfld.long 0x00 17. "CR1,Port 1 Clear bit" "0,1"
bitfld.long 0x00 16. "CR0,Port 0 Clear bit" "0,1"
newline
bitfld.long 0x00 15. "BOP15,Port 15 Set bit" "0,1"
bitfld.long 0x00 14. "BOP14,Port 14 Set bit" "0,1"
bitfld.long 0x00 13. "BOP13,Port 13 Set bit" "0,1"
bitfld.long 0x00 12. "BOP12,Port 12 Set bit" "0,1"
newline
bitfld.long 0x00 11. "BOP11,Port 11 Set bit" "0,1"
bitfld.long 0x00 10. "BOP10,Port 10 Set bit" "0,1"
bitfld.long 0x00 9. "BOP9,Port 9 Set bit" "0,1"
bitfld.long 0x00 8. "BOP8,Port 8 Set bit" "0,1"
newline
bitfld.long 0x00 7. "BOP7,Port 7 Set bit" "0,1"
bitfld.long 0x00 6. "BOP6,Port 6 Set bit" "0,1"
bitfld.long 0x00 5. "BOP5,Port 5 Set bit" "0,1"
bitfld.long 0x00 4. "BOP4,Port 4 Set bit" "0,1"
newline
bitfld.long 0x00 3. "BOP3,Port 3 Set bit" "0,1"
bitfld.long 0x00 2. "BOP2,Port 2 Set bit" "0,1"
bitfld.long 0x00 1. "BOP1,Port 1 Set bit" "0,1"
bitfld.long 0x00 0. "BOP0,Port 0 Set bit" "0,1"
wgroup.long 0x14++0x03
line.long 0x00 "BC,Port bit clear register"
bitfld.long 0x00 15. "CR15,Port 15 Clear bit" "0,1"
bitfld.long 0x00 14. "CR14,Port 14 Clear bit" "0,1"
bitfld.long 0x00 13. "CR13,Port 13 Clear bit" "0,1"
bitfld.long 0x00 12. "CR12,Port 12 Clear bit" "0,1"
newline
bitfld.long 0x00 11. "CR11,Port 11 Clear bit" "0,1"
bitfld.long 0x00 10. "CR10,Port 10 Clear bit" "0,1"
bitfld.long 0x00 9. "CR9,Port 9 Clear bit" "0,1"
bitfld.long 0x00 8. "CR8,Port 8 Clear bit" "0,1"
newline
bitfld.long 0x00 7. "CR7,Port 7 Clear bit" "0,1"
bitfld.long 0x00 6. "CR6,Port 6 Clear bit" "0,1"
bitfld.long 0x00 5. "CR5,Port 5 Clear bit" "0,1"
bitfld.long 0x00 4. "CR4,Port 4 Clear bit" "0,1"
newline
bitfld.long 0x00 3. "CR3,Port 3 Clear bit" "0,1"
bitfld.long 0x00 2. "CR2,Port 2 Clear bit" "0,1"
bitfld.long 0x00 1. "CR1,Port 1 Clear bit" "0,1"
bitfld.long 0x00 0. "CR0,Port 0 Clear bit" "0,1"
group.long 0x18++0x03
line.long 0x00 "LOCK,GPIO port configuration lock register"
bitfld.long 0x00 16. "LKK,Lock sequence key" "0,1"
bitfld.long 0x00 15. "LK15,Port Lock bit 15" "0,1"
bitfld.long 0x00 14. "LK14,Port Lock bit 14" "0,1"
bitfld.long 0x00 13. "LK13,Port Lock bit 13" "0,1"
newline
bitfld.long 0x00 12. "LK12,Port Lock bit 12" "0,1"
bitfld.long 0x00 11. "LK11,Port Lock bit 11" "0,1"
bitfld.long 0x00 10. "LK10,Port Lock bit 10" "0,1"
bitfld.long 0x00 9. "LK9,Port Lock bit 9" "0,1"
newline
bitfld.long 0x00 8. "LK8,Port Lock bit 8" "0,1"
bitfld.long 0x00 7. "LK7,Port Lock bit 7" "0,1"
bitfld.long 0x00 6. "LK6,Port Lock bit 6" "0,1"
bitfld.long 0x00 5. "LK5,Port Lock bit 5" "0,1"
newline
bitfld.long 0x00 4. "LK4,Port Lock bit 4" "0,1"
bitfld.long 0x00 3. "LK3,Port Lock bit 3" "0,1"
bitfld.long 0x00 2. "LK2,Port Lock bit 2" "0,1"
bitfld.long 0x00 1. "LK1,Port Lock bit 1" "0,1"
newline
bitfld.long 0x00 0. "LK0,Port Lock bit 0" "0,1"
group.long 0x3C++0x03
line.long 0x00 "SPD,Port bit speed register"
bitfld.long 0x00 15. "SPD15,Port 15 output max speed bits" "0,1"
bitfld.long 0x00 14. "SPD14,Port 14 output max speed bits" "0,1"
bitfld.long 0x00 13. "SPD13,Port 13 output max speed bits" "0,1"
bitfld.long 0x00 12. "SPD12,Port 12 output max speed bits" "0,1"
newline
bitfld.long 0x00 11. "SPD11,Port 11 output max speed bits" "0,1"
bitfld.long 0x00 10. "SPD10,Port 10 output max speed bits" "0,1"
bitfld.long 0x00 9. "SPD9,Port 9 output max speed bits" "0,1"
bitfld.long 0x00 8. "SPD8,Port 8 output max speed bits" "0,1"
newline
bitfld.long 0x00 7. "SPD7,Port 7 output max speed bits" "0,1"
bitfld.long 0x00 6. "SPD6,Port 6 output max speed bits" "0,1"
bitfld.long 0x00 5. "SPD5,Port 5 output max speed bits" "0,1"
bitfld.long 0x00 4. "SPD4,Port 4 output max speed bits" "0,1"
newline
bitfld.long 0x00 3. "SPD3,Port 3 output max speed bits" "0,1"
bitfld.long 0x00 2. "SPD2,Port 2 output max speed bits" "0,1"
bitfld.long 0x00 1. "SPD1,Port 1 output max speed bits" "0,1"
bitfld.long 0x00 0. "SPD0,Port 0 output max speed bits" "0,1"
tree.end
tree "GPIOD"
base ad:0x40011400
group.long 0x00++0x03
line.long 0x00 "CTL0,port control register 0"
bitfld.long 0x00 30.--31. "CTL7,Port x configuration bits (x = 7)" "0,1,2,3"
bitfld.long 0x00 28.--29. "MD7,Port x mode bits (x = 7)" "0,1,2,3"
bitfld.long 0x00 26.--27. "CTL6,Port x configuration bits (x = 6)" "0,1,2,3"
bitfld.long 0x00 24.--25. "MD6,Port x mode bits (x = 6)" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "CTL5,Port x configuration bits (x = 5)" "0,1,2,3"
bitfld.long 0x00 20.--21. "MD5,Port x mode bits (x = 5)" "0,1,2,3"
bitfld.long 0x00 18.--19. "CTL4,Port x configuration bits (x = 4)" "0,1,2,3"
bitfld.long 0x00 16.--17. "MD4,Port x mode bits (x = 4)" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "CTL3,Port x configuration bits (x = 3)" "0,1,2,3"
bitfld.long 0x00 12.--13. "MD3,Port x mode bits (x = 3 )" "0,1,2,3"
bitfld.long 0x00 10.--11. "CTL2,Port x configuration bits (x = 2)" "0,1,2,3"
bitfld.long 0x00 8.--9. "MD2,Port x mode bits (x = 2 )" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "CTL1,Port x configuration bits (x = 1)" "0,1,2,3"
bitfld.long 0x00 4.--5. "MD1,Port x mode bits (x = 1)" "0,1,2,3"
bitfld.long 0x00 2.--3. "CTL0,Port x configuration bits (x = 0)" "0,1,2,3"
bitfld.long 0x00 0.--1. "MD0,Port x mode bits (x = 0)" "0,1,2,3"
group.long 0x04++0x03
line.long 0x00 "CTL1,port control register 1"
bitfld.long 0x00 30.--31. "CTL15,Port x configuration bits (x = 15)" "0,1,2,3"
bitfld.long 0x00 28.--29. "MD15,Port x mode bits (x = 15)" "0,1,2,3"
bitfld.long 0x00 26.--27. "CTL14,Port x configuration bits (x = 14)" "0,1,2,3"
bitfld.long 0x00 24.--25. "MD14,Port x mode bits (x = 14)" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "CTL13,Port x configuration bits (x = 13)" "0,1,2,3"
bitfld.long 0x00 20.--21. "MD13,Port x mode bits (x = 13)" "0,1,2,3"
bitfld.long 0x00 18.--19. "CTL12,Port x configuration bits (x = 12)" "0,1,2,3"
bitfld.long 0x00 16.--17. "MD12,Port x mode bits (x = 12)" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "CTL11,Port x configuration bits (x = 11)" "0,1,2,3"
bitfld.long 0x00 12.--13. "MD11,Port x mode bits (x = 11 )" "0,1,2,3"
bitfld.long 0x00 10.--11. "CTL10,Port x configuration bits (x = 10)" "0,1,2,3"
bitfld.long 0x00 8.--9. "MD10,Port x mode bits (x = 10 )" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "CTL9,Port x configuration bits (x = 9)" "0,1,2,3"
bitfld.long 0x00 4.--5. "MD9,Port x mode bits (x = 9)" "0,1,2,3"
bitfld.long 0x00 2.--3. "CTL8,Port x configuration bits (x = 8)" "0,1,2,3"
bitfld.long 0x00 0.--1. "MD8,Port x mode bits (x = 8)" "0,1,2,3"
rgroup.long 0x08++0x03
line.long 0x00 "ISTAT,Port input status register"
bitfld.long 0x00 15. "ISTAT15,Port input status" "0,1"
bitfld.long 0x00 14. "ISTAT14,Port input status" "0,1"
bitfld.long 0x00 13. "ISTAT13,Port input status" "0,1"
bitfld.long 0x00 12. "ISTAT12,Port input status" "0,1"
newline
bitfld.long 0x00 11. "ISTAT11,Port input status" "0,1"
bitfld.long 0x00 10. "ISTAT10,Port input status" "0,1"
bitfld.long 0x00 9. "ISTAT9,Port input status" "0,1"
bitfld.long 0x00 8. "ISTAT8,Port input status" "0,1"
newline
bitfld.long 0x00 7. "ISTAT7,Port input status" "0,1"
bitfld.long 0x00 6. "ISTAT6,Port input status" "0,1"
bitfld.long 0x00 5. "ISTAT5,Port input status" "0,1"
bitfld.long 0x00 4. "ISTAT4,Port input status" "0,1"
newline
bitfld.long 0x00 3. "ISTAT3,Port input status" "0,1"
bitfld.long 0x00 2. "ISTAT2,Port input status" "0,1"
bitfld.long 0x00 1. "ISTAT1,Port input status" "0,1"
bitfld.long 0x00 0. "ISTAT0,Port input status" "0,1"
group.long 0x0C++0x03
line.long 0x00 "OCTL,Port output control register"
bitfld.long 0x00 15. "OCTL15,Port output control" "0,1"
bitfld.long 0x00 14. "OCTL14,Port output control" "0,1"
bitfld.long 0x00 13. "OCTL13,Port output control" "0,1"
bitfld.long 0x00 12. "OCTL12,Port output control" "0,1"
newline
bitfld.long 0x00 11. "OCTL11,Port output control" "0,1"
bitfld.long 0x00 10. "OCTL10,Port output control" "0,1"
bitfld.long 0x00 9. "OCTL9,Port output control" "0,1"
bitfld.long 0x00 8. "OCTL8,Port output control" "0,1"
newline
bitfld.long 0x00 7. "OCTL7,Port output control" "0,1"
bitfld.long 0x00 6. "OCTL6,Port output control" "0,1"
bitfld.long 0x00 5. "OCTL5,Port output control" "0,1"
bitfld.long 0x00 4. "OCTL4,Port output control" "0,1"
newline
bitfld.long 0x00 3. "OCTL3,Port output control" "0,1"
bitfld.long 0x00 2. "OCTL2,Port output control" "0,1"
bitfld.long 0x00 1. "OCTL1,Port output control" "0,1"
bitfld.long 0x00 0. "OCTL0,Port output control" "0,1"
wgroup.long 0x10++0x03
line.long 0x00 "BOP,Port bit operate register"
bitfld.long 0x00 31. "CR15,Port 15 Clear bit" "0,1"
bitfld.long 0x00 30. "CR14,Port 14 Clear bit" "0,1"
bitfld.long 0x00 29. "CR13,Port 13 Clear bit" "0,1"
bitfld.long 0x00 28. "CR12,Port 12 Clear bit" "0,1"
newline
bitfld.long 0x00 27. "CR11,Port 11 Clear bit" "0,1"
bitfld.long 0x00 26. "CR10,Port 10 Clear bit" "0,1"
bitfld.long 0x00 25. "CR9,Port 9 Clear bit" "0,1"
bitfld.long 0x00 24. "CR8,Port 8 Clear bit" "0,1"
newline
bitfld.long 0x00 23. "CR7,Port 7 Clear bit" "0,1"
bitfld.long 0x00 22. "CR6,Port 6 Clear bit" "0,1"
bitfld.long 0x00 21. "CR5,Port 5 Clear bit" "0,1"
bitfld.long 0x00 20. "CR4,Port 4 Clear bit" "0,1"
newline
bitfld.long 0x00 19. "CR3,Port 3 Clear bit" "0,1"
bitfld.long 0x00 18. "CR2,Port 2 Clear bit" "0,1"
bitfld.long 0x00 17. "CR1,Port 1 Clear bit" "0,1"
bitfld.long 0x00 16. "CR0,Port 0 Clear bit" "0,1"
newline
bitfld.long 0x00 15. "BOP15,Port 15 Set bit" "0,1"
bitfld.long 0x00 14. "BOP14,Port 14 Set bit" "0,1"
bitfld.long 0x00 13. "BOP13,Port 13 Set bit" "0,1"
bitfld.long 0x00 12. "BOP12,Port 12 Set bit" "0,1"
newline
bitfld.long 0x00 11. "BOP11,Port 11 Set bit" "0,1"
bitfld.long 0x00 10. "BOP10,Port 10 Set bit" "0,1"
bitfld.long 0x00 9. "BOP9,Port 9 Set bit" "0,1"
bitfld.long 0x00 8. "BOP8,Port 8 Set bit" "0,1"
newline
bitfld.long 0x00 7. "BOP7,Port 7 Set bit" "0,1"
bitfld.long 0x00 6. "BOP6,Port 6 Set bit" "0,1"
bitfld.long 0x00 5. "BOP5,Port 5 Set bit" "0,1"
bitfld.long 0x00 4. "BOP4,Port 4 Set bit" "0,1"
newline
bitfld.long 0x00 3. "BOP3,Port 3 Set bit" "0,1"
bitfld.long 0x00 2. "BOP2,Port 2 Set bit" "0,1"
bitfld.long 0x00 1. "BOP1,Port 1 Set bit" "0,1"
bitfld.long 0x00 0. "BOP0,Port 0 Set bit" "0,1"
wgroup.long 0x14++0x03
line.long 0x00 "BC,Port bit clear register"
bitfld.long 0x00 15. "CR15,Port 15 Clear bit" "0,1"
bitfld.long 0x00 14. "CR14,Port 14 Clear bit" "0,1"
bitfld.long 0x00 13. "CR13,Port 13 Clear bit" "0,1"
bitfld.long 0x00 12. "CR12,Port 12 Clear bit" "0,1"
newline
bitfld.long 0x00 11. "CR11,Port 11 Clear bit" "0,1"
bitfld.long 0x00 10. "CR10,Port 10 Clear bit" "0,1"
bitfld.long 0x00 9. "CR9,Port 9 Clear bit" "0,1"
bitfld.long 0x00 8. "CR8,Port 8 Clear bit" "0,1"
newline
bitfld.long 0x00 7. "CR7,Port 7 Clear bit" "0,1"
bitfld.long 0x00 6. "CR6,Port 6 Clear bit" "0,1"
bitfld.long 0x00 5. "CR5,Port 5 Clear bit" "0,1"
bitfld.long 0x00 4. "CR4,Port 4 Clear bit" "0,1"
newline
bitfld.long 0x00 3. "CR3,Port 3 Clear bit" "0,1"
bitfld.long 0x00 2. "CR2,Port 2 Clear bit" "0,1"
bitfld.long 0x00 1. "CR1,Port 1 Clear bit" "0,1"
bitfld.long 0x00 0. "CR0,Port 0 Clear bit" "0,1"
group.long 0x18++0x03
line.long 0x00 "LOCK,GPIO port configuration lock register"
bitfld.long 0x00 16. "LKK,Lock sequence key" "0,1"
bitfld.long 0x00 15. "LK15,Port Lock bit 15" "0,1"
bitfld.long 0x00 14. "LK14,Port Lock bit 14" "0,1"
bitfld.long 0x00 13. "LK13,Port Lock bit 13" "0,1"
newline
bitfld.long 0x00 12. "LK12,Port Lock bit 12" "0,1"
bitfld.long 0x00 11. "LK11,Port Lock bit 11" "0,1"
bitfld.long 0x00 10. "LK10,Port Lock bit 10" "0,1"
bitfld.long 0x00 9. "LK9,Port Lock bit 9" "0,1"
newline
bitfld.long 0x00 8. "LK8,Port Lock bit 8" "0,1"
bitfld.long 0x00 7. "LK7,Port Lock bit 7" "0,1"
bitfld.long 0x00 6. "LK6,Port Lock bit 6" "0,1"
bitfld.long 0x00 5. "LK5,Port Lock bit 5" "0,1"
newline
bitfld.long 0x00 4. "LK4,Port Lock bit 4" "0,1"
bitfld.long 0x00 3. "LK3,Port Lock bit 3" "0,1"
bitfld.long 0x00 2. "LK2,Port Lock bit 2" "0,1"
bitfld.long 0x00 1. "LK1,Port Lock bit 1" "0,1"
newline
bitfld.long 0x00 0. "LK0,Port Lock bit 0" "0,1"
group.long 0x3C++0x03
line.long 0x00 "SPD,Port bit speed register"
bitfld.long 0x00 15. "SPD15,Port 15 output max speed bits" "0,1"
bitfld.long 0x00 14. "SPD14,Port 14 output max speed bits" "0,1"
bitfld.long 0x00 13. "SPD13,Port 13 output max speed bits" "0,1"
bitfld.long 0x00 12. "SPD12,Port 12 output max speed bits" "0,1"
newline
bitfld.long 0x00 11. "SPD11,Port 11 output max speed bits" "0,1"
bitfld.long 0x00 10. "SPD10,Port 10 output max speed bits" "0,1"
bitfld.long 0x00 9. "SPD9,Port 9 output max speed bits" "0,1"
bitfld.long 0x00 8. "SPD8,Port 8 output max speed bits" "0,1"
newline
bitfld.long 0x00 7. "SPD7,Port 7 output max speed bits" "0,1"
bitfld.long 0x00 6. "SPD6,Port 6 output max speed bits" "0,1"
bitfld.long 0x00 5. "SPD5,Port 5 output max speed bits" "0,1"
bitfld.long 0x00 4. "SPD4,Port 4 output max speed bits" "0,1"
newline
bitfld.long 0x00 3. "SPD3,Port 3 output max speed bits" "0,1"
bitfld.long 0x00 2. "SPD2,Port 2 output max speed bits" "0,1"
bitfld.long 0x00 1. "SPD1,Port 1 output max speed bits" "0,1"
bitfld.long 0x00 0. "SPD0,Port 0 output max speed bits" "0,1"
tree.end
tree "GPIOE"
base ad:0x40011800
group.long 0x00++0x03
line.long 0x00 "CTL0,port control register 0"
bitfld.long 0x00 30.--31. "CTL7,Port x configuration bits (x = 7)" "0,1,2,3"
bitfld.long 0x00 28.--29. "MD7,Port x mode bits (x = 7)" "0,1,2,3"
bitfld.long 0x00 26.--27. "CTL6,Port x configuration bits (x = 6)" "0,1,2,3"
bitfld.long 0x00 24.--25. "MD6,Port x mode bits (x = 6)" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "CTL5,Port x configuration bits (x = 5)" "0,1,2,3"
bitfld.long 0x00 20.--21. "MD5,Port x mode bits (x = 5)" "0,1,2,3"
bitfld.long 0x00 18.--19. "CTL4,Port x configuration bits (x = 4)" "0,1,2,3"
bitfld.long 0x00 16.--17. "MD4,Port x mode bits (x = 4)" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "CTL3,Port x configuration bits (x = 3)" "0,1,2,3"
bitfld.long 0x00 12.--13. "MD3,Port x mode bits (x = 3 )" "0,1,2,3"
bitfld.long 0x00 10.--11. "CTL2,Port x configuration bits (x = 2)" "0,1,2,3"
bitfld.long 0x00 8.--9. "MD2,Port x mode bits (x = 2 )" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "CTL1,Port x configuration bits (x = 1)" "0,1,2,3"
bitfld.long 0x00 4.--5. "MD1,Port x mode bits (x = 1)" "0,1,2,3"
bitfld.long 0x00 2.--3. "CTL0,Port x configuration bits (x = 0)" "0,1,2,3"
bitfld.long 0x00 0.--1. "MD0,Port x mode bits (x = 0)" "0,1,2,3"
group.long 0x04++0x03
line.long 0x00 "CTL1,port control register 1"
bitfld.long 0x00 30.--31. "CTL15,Port x configuration bits (x = 15)" "0,1,2,3"
bitfld.long 0x00 28.--29. "MD15,Port x mode bits (x = 15)" "0,1,2,3"
bitfld.long 0x00 26.--27. "CTL14,Port x configuration bits (x = 14)" "0,1,2,3"
bitfld.long 0x00 24.--25. "MD14,Port x mode bits (x = 14)" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "CTL13,Port x configuration bits (x = 13)" "0,1,2,3"
bitfld.long 0x00 20.--21. "MD13,Port x mode bits (x = 13)" "0,1,2,3"
bitfld.long 0x00 18.--19. "CTL12,Port x configuration bits (x = 12)" "0,1,2,3"
bitfld.long 0x00 16.--17. "MD12,Port x mode bits (x = 12)" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "CTL11,Port x configuration bits (x = 11)" "0,1,2,3"
bitfld.long 0x00 12.--13. "MD11,Port x mode bits (x = 11 )" "0,1,2,3"
bitfld.long 0x00 10.--11. "CTL10,Port x configuration bits (x = 10)" "0,1,2,3"
bitfld.long 0x00 8.--9. "MD10,Port x mode bits (x = 10 )" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "CTL9,Port x configuration bits (x = 9)" "0,1,2,3"
bitfld.long 0x00 4.--5. "MD9,Port x mode bits (x = 9)" "0,1,2,3"
bitfld.long 0x00 2.--3. "CTL8,Port x configuration bits (x = 8)" "0,1,2,3"
bitfld.long 0x00 0.--1. "MD8,Port x mode bits (x = 8)" "0,1,2,3"
rgroup.long 0x08++0x03
line.long 0x00 "ISTAT,Port input status register"
bitfld.long 0x00 15. "ISTAT15,Port input status" "0,1"
bitfld.long 0x00 14. "ISTAT14,Port input status" "0,1"
bitfld.long 0x00 13. "ISTAT13,Port input status" "0,1"
bitfld.long 0x00 12. "ISTAT12,Port input status" "0,1"
newline
bitfld.long 0x00 11. "ISTAT11,Port input status" "0,1"
bitfld.long 0x00 10. "ISTAT10,Port input status" "0,1"
bitfld.long 0x00 9. "ISTAT9,Port input status" "0,1"
bitfld.long 0x00 8. "ISTAT8,Port input status" "0,1"
newline
bitfld.long 0x00 7. "ISTAT7,Port input status" "0,1"
bitfld.long 0x00 6. "ISTAT6,Port input status" "0,1"
bitfld.long 0x00 5. "ISTAT5,Port input status" "0,1"
bitfld.long 0x00 4. "ISTAT4,Port input status" "0,1"
newline
bitfld.long 0x00 3. "ISTAT3,Port input status" "0,1"
bitfld.long 0x00 2. "ISTAT2,Port input status" "0,1"
bitfld.long 0x00 1. "ISTAT1,Port input status" "0,1"
bitfld.long 0x00 0. "ISTAT0,Port input status" "0,1"
group.long 0x0C++0x03
line.long 0x00 "OCTL,Port output control register"
bitfld.long 0x00 15. "OCTL15,Port output control" "0,1"
bitfld.long 0x00 14. "OCTL14,Port output control" "0,1"
bitfld.long 0x00 13. "OCTL13,Port output control" "0,1"
bitfld.long 0x00 12. "OCTL12,Port output control" "0,1"
newline
bitfld.long 0x00 11. "OCTL11,Port output control" "0,1"
bitfld.long 0x00 10. "OCTL10,Port output control" "0,1"
bitfld.long 0x00 9. "OCTL9,Port output control" "0,1"
bitfld.long 0x00 8. "OCTL8,Port output control" "0,1"
newline
bitfld.long 0x00 7. "OCTL7,Port output control" "0,1"
bitfld.long 0x00 6. "OCTL6,Port output control" "0,1"
bitfld.long 0x00 5. "OCTL5,Port output control" "0,1"
bitfld.long 0x00 4. "OCTL4,Port output control" "0,1"
newline
bitfld.long 0x00 3. "OCTL3,Port output control" "0,1"
bitfld.long 0x00 2. "OCTL2,Port output control" "0,1"
bitfld.long 0x00 1. "OCTL1,Port output control" "0,1"
bitfld.long 0x00 0. "OCTL0,Port output control" "0,1"
wgroup.long 0x10++0x03
line.long 0x00 "BOP,Port bit operate register"
bitfld.long 0x00 31. "CR15,Port 15 Clear bit" "0,1"
bitfld.long 0x00 30. "CR14,Port 14 Clear bit" "0,1"
bitfld.long 0x00 29. "CR13,Port 13 Clear bit" "0,1"
bitfld.long 0x00 28. "CR12,Port 12 Clear bit" "0,1"
newline
bitfld.long 0x00 27. "CR11,Port 11 Clear bit" "0,1"
bitfld.long 0x00 26. "CR10,Port 10 Clear bit" "0,1"
bitfld.long 0x00 25. "CR9,Port 9 Clear bit" "0,1"
bitfld.long 0x00 24. "CR8,Port 8 Clear bit" "0,1"
newline
bitfld.long 0x00 23. "CR7,Port 7 Clear bit" "0,1"
bitfld.long 0x00 22. "CR6,Port 6 Clear bit" "0,1"
bitfld.long 0x00 21. "CR5,Port 5 Clear bit" "0,1"
bitfld.long 0x00 20. "CR4,Port 4 Clear bit" "0,1"
newline
bitfld.long 0x00 19. "CR3,Port 3 Clear bit" "0,1"
bitfld.long 0x00 18. "CR2,Port 2 Clear bit" "0,1"
bitfld.long 0x00 17. "CR1,Port 1 Clear bit" "0,1"
bitfld.long 0x00 16. "CR0,Port 0 Clear bit" "0,1"
newline
bitfld.long 0x00 15. "BOP15,Port 15 Set bit" "0,1"
bitfld.long 0x00 14. "BOP14,Port 14 Set bit" "0,1"
bitfld.long 0x00 13. "BOP13,Port 13 Set bit" "0,1"
bitfld.long 0x00 12. "BOP12,Port 12 Set bit" "0,1"
newline
bitfld.long 0x00 11. "BOP11,Port 11 Set bit" "0,1"
bitfld.long 0x00 10. "BOP10,Port 10 Set bit" "0,1"
bitfld.long 0x00 9. "BOP9,Port 9 Set bit" "0,1"
bitfld.long 0x00 8. "BOP8,Port 8 Set bit" "0,1"
newline
bitfld.long 0x00 7. "BOP7,Port 7 Set bit" "0,1"
bitfld.long 0x00 6. "BOP6,Port 6 Set bit" "0,1"
bitfld.long 0x00 5. "BOP5,Port 5 Set bit" "0,1"
bitfld.long 0x00 4. "BOP4,Port 4 Set bit" "0,1"
newline
bitfld.long 0x00 3. "BOP3,Port 3 Set bit" "0,1"
bitfld.long 0x00 2. "BOP2,Port 2 Set bit" "0,1"
bitfld.long 0x00 1. "BOP1,Port 1 Set bit" "0,1"
bitfld.long 0x00 0. "BOP0,Port 0 Set bit" "0,1"
wgroup.long 0x14++0x03
line.long 0x00 "BC,Port bit clear register"
bitfld.long 0x00 15. "CR15,Port 15 Clear bit" "0,1"
bitfld.long 0x00 14. "CR14,Port 14 Clear bit" "0,1"
bitfld.long 0x00 13. "CR13,Port 13 Clear bit" "0,1"
bitfld.long 0x00 12. "CR12,Port 12 Clear bit" "0,1"
newline
bitfld.long 0x00 11. "CR11,Port 11 Clear bit" "0,1"
bitfld.long 0x00 10. "CR10,Port 10 Clear bit" "0,1"
bitfld.long 0x00 9. "CR9,Port 9 Clear bit" "0,1"
bitfld.long 0x00 8. "CR8,Port 8 Clear bit" "0,1"
newline
bitfld.long 0x00 7. "CR7,Port 7 Clear bit" "0,1"
bitfld.long 0x00 6. "CR6,Port 6 Clear bit" "0,1"
bitfld.long 0x00 5. "CR5,Port 5 Clear bit" "0,1"
bitfld.long 0x00 4. "CR4,Port 4 Clear bit" "0,1"
newline
bitfld.long 0x00 3. "CR3,Port 3 Clear bit" "0,1"
bitfld.long 0x00 2. "CR2,Port 2 Clear bit" "0,1"
bitfld.long 0x00 1. "CR1,Port 1 Clear bit" "0,1"
bitfld.long 0x00 0. "CR0,Port 0 Clear bit" "0,1"
group.long 0x18++0x03
line.long 0x00 "LOCK,GPIO port configuration lock register"
bitfld.long 0x00 16. "LKK,Lock sequence key" "0,1"
bitfld.long 0x00 15. "LK15,Port Lock bit 15" "0,1"
bitfld.long 0x00 14. "LK14,Port Lock bit 14" "0,1"
bitfld.long 0x00 13. "LK13,Port Lock bit 13" "0,1"
newline
bitfld.long 0x00 12. "LK12,Port Lock bit 12" "0,1"
bitfld.long 0x00 11. "LK11,Port Lock bit 11" "0,1"
bitfld.long 0x00 10. "LK10,Port Lock bit 10" "0,1"
bitfld.long 0x00 9. "LK9,Port Lock bit 9" "0,1"
newline
bitfld.long 0x00 8. "LK8,Port Lock bit 8" "0,1"
bitfld.long 0x00 7. "LK7,Port Lock bit 7" "0,1"
bitfld.long 0x00 6. "LK6,Port Lock bit 6" "0,1"
bitfld.long 0x00 5. "LK5,Port Lock bit 5" "0,1"
newline
bitfld.long 0x00 4. "LK4,Port Lock bit 4" "0,1"
bitfld.long 0x00 3. "LK3,Port Lock bit 3" "0,1"
bitfld.long 0x00 2. "LK2,Port Lock bit 2" "0,1"
bitfld.long 0x00 1. "LK1,Port Lock bit 1" "0,1"
newline
bitfld.long 0x00 0. "LK0,Port Lock bit 0" "0,1"
group.long 0x3C++0x03
line.long 0x00 "SPD,Port bit speed register"
bitfld.long 0x00 15. "SPD15,Port 15 output max speed bits" "0,1"
bitfld.long 0x00 14. "SPD14,Port 14 output max speed bits" "0,1"
bitfld.long 0x00 13. "SPD13,Port 13 output max speed bits" "0,1"
bitfld.long 0x00 12. "SPD12,Port 12 output max speed bits" "0,1"
newline
bitfld.long 0x00 11. "SPD11,Port 11 output max speed bits" "0,1"
bitfld.long 0x00 10. "SPD10,Port 10 output max speed bits" "0,1"
bitfld.long 0x00 9. "SPD9,Port 9 output max speed bits" "0,1"
bitfld.long 0x00 8. "SPD8,Port 8 output max speed bits" "0,1"
newline
bitfld.long 0x00 7. "SPD7,Port 7 output max speed bits" "0,1"
bitfld.long 0x00 6. "SPD6,Port 6 output max speed bits" "0,1"
bitfld.long 0x00 5. "SPD5,Port 5 output max speed bits" "0,1"
bitfld.long 0x00 4. "SPD4,Port 4 output max speed bits" "0,1"
newline
bitfld.long 0x00 3. "SPD3,Port 3 output max speed bits" "0,1"
bitfld.long 0x00 2. "SPD2,Port 2 output max speed bits" "0,1"
bitfld.long 0x00 1. "SPD1,Port 1 output max speed bits" "0,1"
bitfld.long 0x00 0. "SPD0,Port 0 output max speed bits" "0,1"
tree.end
tree "GPIOF"
base ad:0x40011C00
group.long 0x00++0x03
line.long 0x00 "CTL0,port control register 0"
bitfld.long 0x00 30.--31. "CTL7,Port x configuration bits (x = 7)" "0,1,2,3"
bitfld.long 0x00 28.--29. "MD7,Port x mode bits (x = 7)" "0,1,2,3"
bitfld.long 0x00 26.--27. "CTL6,Port x configuration bits (x = 6)" "0,1,2,3"
bitfld.long 0x00 24.--25. "MD6,Port x mode bits (x = 6)" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "CTL5,Port x configuration bits (x = 5)" "0,1,2,3"
bitfld.long 0x00 20.--21. "MD5,Port x mode bits (x = 5)" "0,1,2,3"
bitfld.long 0x00 18.--19. "CTL4,Port x configuration bits (x = 4)" "0,1,2,3"
bitfld.long 0x00 16.--17. "MD4,Port x mode bits (x = 4)" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "CTL3,Port x configuration bits (x = 3)" "0,1,2,3"
bitfld.long 0x00 12.--13. "MD3,Port x mode bits (x = 3 )" "0,1,2,3"
bitfld.long 0x00 10.--11. "CTL2,Port x configuration bits (x = 2)" "0,1,2,3"
bitfld.long 0x00 8.--9. "MD2,Port x mode bits (x = 2 )" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "CTL1,Port x configuration bits (x = 1)" "0,1,2,3"
bitfld.long 0x00 4.--5. "MD1,Port x mode bits (x = 1)" "0,1,2,3"
bitfld.long 0x00 2.--3. "CTL0,Port x configuration bits (x = 0)" "0,1,2,3"
bitfld.long 0x00 0.--1. "MD0,Port x mode bits (x = 0)" "0,1,2,3"
group.long 0x04++0x03
line.long 0x00 "CTL1,port control register 1"
bitfld.long 0x00 30.--31. "CTL15,Port x configuration bits (x = 15)" "0,1,2,3"
bitfld.long 0x00 28.--29. "MD15,Port x mode bits (x = 15)" "0,1,2,3"
bitfld.long 0x00 26.--27. "CTL14,Port x configuration bits (x = 14)" "0,1,2,3"
bitfld.long 0x00 24.--25. "MD14,Port x mode bits (x = 14)" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "CTL13,Port x configuration bits (x = 13)" "0,1,2,3"
bitfld.long 0x00 20.--21. "MD13,Port x mode bits (x = 13)" "0,1,2,3"
bitfld.long 0x00 18.--19. "CTL12,Port x configuration bits (x = 12)" "0,1,2,3"
bitfld.long 0x00 16.--17. "MD12,Port x mode bits (x = 12)" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "CTL11,Port x configuration bits (x = 11)" "0,1,2,3"
bitfld.long 0x00 12.--13. "MD11,Port x mode bits (x = 11 )" "0,1,2,3"
bitfld.long 0x00 10.--11. "CTL10,Port x configuration bits (x = 10)" "0,1,2,3"
bitfld.long 0x00 8.--9. "MD10,Port x mode bits (x = 10 )" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "CTL9,Port x configuration bits (x = 9)" "0,1,2,3"
bitfld.long 0x00 4.--5. "MD9,Port x mode bits (x = 9)" "0,1,2,3"
bitfld.long 0x00 2.--3. "CTL8,Port x configuration bits (x = 8)" "0,1,2,3"
bitfld.long 0x00 0.--1. "MD8,Port x mode bits (x = 8)" "0,1,2,3"
rgroup.long 0x08++0x03
line.long 0x00 "ISTAT,Port input status register"
bitfld.long 0x00 15. "ISTAT15,Port input status" "0,1"
bitfld.long 0x00 14. "ISTAT14,Port input status" "0,1"
bitfld.long 0x00 13. "ISTAT13,Port input status" "0,1"
bitfld.long 0x00 12. "ISTAT12,Port input status" "0,1"
newline
bitfld.long 0x00 11. "ISTAT11,Port input status" "0,1"
bitfld.long 0x00 10. "ISTAT10,Port input status" "0,1"
bitfld.long 0x00 9. "ISTAT9,Port input status" "0,1"
bitfld.long 0x00 8. "ISTAT8,Port input status" "0,1"
newline
bitfld.long 0x00 7. "ISTAT7,Port input status" "0,1"
bitfld.long 0x00 6. "ISTAT6,Port input status" "0,1"
bitfld.long 0x00 5. "ISTAT5,Port input status" "0,1"
bitfld.long 0x00 4. "ISTAT4,Port input status" "0,1"
newline
bitfld.long 0x00 3. "ISTAT3,Port input status" "0,1"
bitfld.long 0x00 2. "ISTAT2,Port input status" "0,1"
bitfld.long 0x00 1. "ISTAT1,Port input status" "0,1"
bitfld.long 0x00 0. "ISTAT0,Port input status" "0,1"
group.long 0x0C++0x03
line.long 0x00 "OCTL,Port output control register"
bitfld.long 0x00 15. "OCTL15,Port output control" "0,1"
bitfld.long 0x00 14. "OCTL14,Port output control" "0,1"
bitfld.long 0x00 13. "OCTL13,Port output control" "0,1"
bitfld.long 0x00 12. "OCTL12,Port output control" "0,1"
newline
bitfld.long 0x00 11. "OCTL11,Port output control" "0,1"
bitfld.long 0x00 10. "OCTL10,Port output control" "0,1"
bitfld.long 0x00 9. "OCTL9,Port output control" "0,1"
bitfld.long 0x00 8. "OCTL8,Port output control" "0,1"
newline
bitfld.long 0x00 7. "OCTL7,Port output control" "0,1"
bitfld.long 0x00 6. "OCTL6,Port output control" "0,1"
bitfld.long 0x00 5. "OCTL5,Port output control" "0,1"
bitfld.long 0x00 4. "OCTL4,Port output control" "0,1"
newline
bitfld.long 0x00 3. "OCTL3,Port output control" "0,1"
bitfld.long 0x00 2. "OCTL2,Port output control" "0,1"
bitfld.long 0x00 1. "OCTL1,Port output control" "0,1"
bitfld.long 0x00 0. "OCTL0,Port output control" "0,1"
wgroup.long 0x10++0x03
line.long 0x00 "BOP,Port bit operate register"
bitfld.long 0x00 31. "CR15,Port 15 Clear bit" "0,1"
bitfld.long 0x00 30. "CR14,Port 14 Clear bit" "0,1"
bitfld.long 0x00 29. "CR13,Port 13 Clear bit" "0,1"
bitfld.long 0x00 28. "CR12,Port 12 Clear bit" "0,1"
newline
bitfld.long 0x00 27. "CR11,Port 11 Clear bit" "0,1"
bitfld.long 0x00 26. "CR10,Port 10 Clear bit" "0,1"
bitfld.long 0x00 25. "CR9,Port 9 Clear bit" "0,1"
bitfld.long 0x00 24. "CR8,Port 8 Clear bit" "0,1"
newline
bitfld.long 0x00 23. "CR7,Port 7 Clear bit" "0,1"
bitfld.long 0x00 22. "CR6,Port 6 Clear bit" "0,1"
bitfld.long 0x00 21. "CR5,Port 5 Clear bit" "0,1"
bitfld.long 0x00 20. "CR4,Port 4 Clear bit" "0,1"
newline
bitfld.long 0x00 19. "CR3,Port 3 Clear bit" "0,1"
bitfld.long 0x00 18. "CR2,Port 2 Clear bit" "0,1"
bitfld.long 0x00 17. "CR1,Port 1 Clear bit" "0,1"
bitfld.long 0x00 16. "CR0,Port 0 Clear bit" "0,1"
newline
bitfld.long 0x00 15. "BOP15,Port 15 Set bit" "0,1"
bitfld.long 0x00 14. "BOP14,Port 14 Set bit" "0,1"
bitfld.long 0x00 13. "BOP13,Port 13 Set bit" "0,1"
bitfld.long 0x00 12. "BOP12,Port 12 Set bit" "0,1"
newline
bitfld.long 0x00 11. "BOP11,Port 11 Set bit" "0,1"
bitfld.long 0x00 10. "BOP10,Port 10 Set bit" "0,1"
bitfld.long 0x00 9. "BOP9,Port 9 Set bit" "0,1"
bitfld.long 0x00 8. "BOP8,Port 8 Set bit" "0,1"
newline
bitfld.long 0x00 7. "BOP7,Port 7 Set bit" "0,1"
bitfld.long 0x00 6. "BOP6,Port 6 Set bit" "0,1"
bitfld.long 0x00 5. "BOP5,Port 5 Set bit" "0,1"
bitfld.long 0x00 4. "BOP4,Port 4 Set bit" "0,1"
newline
bitfld.long 0x00 3. "BOP3,Port 3 Set bit" "0,1"
bitfld.long 0x00 2. "BOP2,Port 2 Set bit" "0,1"
bitfld.long 0x00 1. "BOP1,Port 1 Set bit" "0,1"
bitfld.long 0x00 0. "BOP0,Port 0 Set bit" "0,1"
wgroup.long 0x14++0x03
line.long 0x00 "BC,Port bit clear register"
bitfld.long 0x00 15. "CR15,Port 15 Clear bit" "0,1"
bitfld.long 0x00 14. "CR14,Port 14 Clear bit" "0,1"
bitfld.long 0x00 13. "CR13,Port 13 Clear bit" "0,1"
bitfld.long 0x00 12. "CR12,Port 12 Clear bit" "0,1"
newline
bitfld.long 0x00 11. "CR11,Port 11 Clear bit" "0,1"
bitfld.long 0x00 10. "CR10,Port 10 Clear bit" "0,1"
bitfld.long 0x00 9. "CR9,Port 9 Clear bit" "0,1"
bitfld.long 0x00 8. "CR8,Port 8 Clear bit" "0,1"
newline
bitfld.long 0x00 7. "CR7,Port 7 Clear bit" "0,1"
bitfld.long 0x00 6. "CR6,Port 6 Clear bit" "0,1"
bitfld.long 0x00 5. "CR5,Port 5 Clear bit" "0,1"
bitfld.long 0x00 4. "CR4,Port 4 Clear bit" "0,1"
newline
bitfld.long 0x00 3. "CR3,Port 3 Clear bit" "0,1"
bitfld.long 0x00 2. "CR2,Port 2 Clear bit" "0,1"
bitfld.long 0x00 1. "CR1,Port 1 Clear bit" "0,1"
bitfld.long 0x00 0. "CR0,Port 0 Clear bit" "0,1"
group.long 0x18++0x03
line.long 0x00 "LOCK,GPIO port configuration lock register"
bitfld.long 0x00 16. "LKK,Lock sequence key" "0,1"
bitfld.long 0x00 15. "LK15,Port Lock bit 15" "0,1"
bitfld.long 0x00 14. "LK14,Port Lock bit 14" "0,1"
bitfld.long 0x00 13. "LK13,Port Lock bit 13" "0,1"
newline
bitfld.long 0x00 12. "LK12,Port Lock bit 12" "0,1"
bitfld.long 0x00 11. "LK11,Port Lock bit 11" "0,1"
bitfld.long 0x00 10. "LK10,Port Lock bit 10" "0,1"
bitfld.long 0x00 9. "LK9,Port Lock bit 9" "0,1"
newline
bitfld.long 0x00 8. "LK8,Port Lock bit 8" "0,1"
bitfld.long 0x00 7. "LK7,Port Lock bit 7" "0,1"
bitfld.long 0x00 6. "LK6,Port Lock bit 6" "0,1"
bitfld.long 0x00 5. "LK5,Port Lock bit 5" "0,1"
newline
bitfld.long 0x00 4. "LK4,Port Lock bit 4" "0,1"
bitfld.long 0x00 3. "LK3,Port Lock bit 3" "0,1"
bitfld.long 0x00 2. "LK2,Port Lock bit 2" "0,1"
bitfld.long 0x00 1. "LK1,Port Lock bit 1" "0,1"
newline
bitfld.long 0x00 0. "LK0,Port Lock bit 0" "0,1"
group.long 0x3C++0x03
line.long 0x00 "SPD,Port bit speed register"
bitfld.long 0x00 15. "SPD15,Port 15 output max speed bits" "0,1"
bitfld.long 0x00 14. "SPD14,Port 14 output max speed bits" "0,1"
bitfld.long 0x00 13. "SPD13,Port 13 output max speed bits" "0,1"
bitfld.long 0x00 12. "SPD12,Port 12 output max speed bits" "0,1"
newline
bitfld.long 0x00 11. "SPD11,Port 11 output max speed bits" "0,1"
bitfld.long 0x00 10. "SPD10,Port 10 output max speed bits" "0,1"
bitfld.long 0x00 9. "SPD9,Port 9 output max speed bits" "0,1"
bitfld.long 0x00 8. "SPD8,Port 8 output max speed bits" "0,1"
newline
bitfld.long 0x00 7. "SPD7,Port 7 output max speed bits" "0,1"
bitfld.long 0x00 6. "SPD6,Port 6 output max speed bits" "0,1"
bitfld.long 0x00 5. "SPD5,Port 5 output max speed bits" "0,1"
bitfld.long 0x00 4. "SPD4,Port 4 output max speed bits" "0,1"
newline
bitfld.long 0x00 3. "SPD3,Port 3 output max speed bits" "0,1"
bitfld.long 0x00 2. "SPD2,Port 2 output max speed bits" "0,1"
bitfld.long 0x00 1. "SPD1,Port 1 output max speed bits" "0,1"
bitfld.long 0x00 0. "SPD0,Port 0 output max speed bits" "0,1"
tree.end
tree "GPIOG"
base ad:0x40012000
group.long 0x00++0x03
line.long 0x00 "CTL0,port control register 0"
bitfld.long 0x00 30.--31. "CTL7,Port x configuration bits (x = 7)" "0,1,2,3"
bitfld.long 0x00 28.--29. "MD7,Port x mode bits (x = 7)" "0,1,2,3"
bitfld.long 0x00 26.--27. "CTL6,Port x configuration bits (x = 6)" "0,1,2,3"
bitfld.long 0x00 24.--25. "MD6,Port x mode bits (x = 6)" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "CTL5,Port x configuration bits (x = 5)" "0,1,2,3"
bitfld.long 0x00 20.--21. "MD5,Port x mode bits (x = 5)" "0,1,2,3"
bitfld.long 0x00 18.--19. "CTL4,Port x configuration bits (x = 4)" "0,1,2,3"
bitfld.long 0x00 16.--17. "MD4,Port x mode bits (x = 4)" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "CTL3,Port x configuration bits (x = 3)" "0,1,2,3"
bitfld.long 0x00 12.--13. "MD3,Port x mode bits (x = 3 )" "0,1,2,3"
bitfld.long 0x00 10.--11. "CTL2,Port x configuration bits (x = 2)" "0,1,2,3"
bitfld.long 0x00 8.--9. "MD2,Port x mode bits (x = 2 )" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "CTL1,Port x configuration bits (x = 1)" "0,1,2,3"
bitfld.long 0x00 4.--5. "MD1,Port x mode bits (x = 1)" "0,1,2,3"
bitfld.long 0x00 2.--3. "CTL0,Port x configuration bits (x = 0)" "0,1,2,3"
bitfld.long 0x00 0.--1. "MD0,Port x mode bits (x = 0)" "0,1,2,3"
group.long 0x04++0x03
line.long 0x00 "CTL1,port control register 1"
bitfld.long 0x00 30.--31. "CTL15,Port x configuration bits (x = 15)" "0,1,2,3"
bitfld.long 0x00 28.--29. "MD15,Port x mode bits (x = 15)" "0,1,2,3"
bitfld.long 0x00 26.--27. "CTL14,Port x configuration bits (x = 14)" "0,1,2,3"
bitfld.long 0x00 24.--25. "MD14,Port x mode bits (x = 14)" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "CTL13,Port x configuration bits (x = 13)" "0,1,2,3"
bitfld.long 0x00 20.--21. "MD13,Port x mode bits (x = 13)" "0,1,2,3"
bitfld.long 0x00 18.--19. "CTL12,Port x configuration bits (x = 12)" "0,1,2,3"
bitfld.long 0x00 16.--17. "MD12,Port x mode bits (x = 12)" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "CTL11,Port x configuration bits (x = 11)" "0,1,2,3"
bitfld.long 0x00 12.--13. "MD11,Port x mode bits (x = 11 )" "0,1,2,3"
bitfld.long 0x00 10.--11. "CTL10,Port x configuration bits (x = 10)" "0,1,2,3"
bitfld.long 0x00 8.--9. "MD10,Port x mode bits (x = 10 )" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "CTL9,Port x configuration bits (x = 9)" "0,1,2,3"
bitfld.long 0x00 4.--5. "MD9,Port x mode bits (x = 9)" "0,1,2,3"
bitfld.long 0x00 2.--3. "CTL8,Port x configuration bits (x = 8)" "0,1,2,3"
bitfld.long 0x00 0.--1. "MD8,Port x mode bits (x = 8)" "0,1,2,3"
rgroup.long 0x08++0x03
line.long 0x00 "ISTAT,Port input status register"
bitfld.long 0x00 15. "ISTAT15,Port input status" "0,1"
bitfld.long 0x00 14. "ISTAT14,Port input status" "0,1"
bitfld.long 0x00 13. "ISTAT13,Port input status" "0,1"
bitfld.long 0x00 12. "ISTAT12,Port input status" "0,1"
newline
bitfld.long 0x00 11. "ISTAT11,Port input status" "0,1"
bitfld.long 0x00 10. "ISTAT10,Port input status" "0,1"
bitfld.long 0x00 9. "ISTAT9,Port input status" "0,1"
bitfld.long 0x00 8. "ISTAT8,Port input status" "0,1"
newline
bitfld.long 0x00 7. "ISTAT7,Port input status" "0,1"
bitfld.long 0x00 6. "ISTAT6,Port input status" "0,1"
bitfld.long 0x00 5. "ISTAT5,Port input status" "0,1"
bitfld.long 0x00 4. "ISTAT4,Port input status" "0,1"
newline
bitfld.long 0x00 3. "ISTAT3,Port input status" "0,1"
bitfld.long 0x00 2. "ISTAT2,Port input status" "0,1"
bitfld.long 0x00 1. "ISTAT1,Port input status" "0,1"
bitfld.long 0x00 0. "ISTAT0,Port input status" "0,1"
group.long 0x0C++0x03
line.long 0x00 "OCTL,Port output control register"
bitfld.long 0x00 15. "OCTL15,Port output control" "0,1"
bitfld.long 0x00 14. "OCTL14,Port output control" "0,1"
bitfld.long 0x00 13. "OCTL13,Port output control" "0,1"
bitfld.long 0x00 12. "OCTL12,Port output control" "0,1"
newline
bitfld.long 0x00 11. "OCTL11,Port output control" "0,1"
bitfld.long 0x00 10. "OCTL10,Port output control" "0,1"
bitfld.long 0x00 9. "OCTL9,Port output control" "0,1"
bitfld.long 0x00 8. "OCTL8,Port output control" "0,1"
newline
bitfld.long 0x00 7. "OCTL7,Port output control" "0,1"
bitfld.long 0x00 6. "OCTL6,Port output control" "0,1"
bitfld.long 0x00 5. "OCTL5,Port output control" "0,1"
bitfld.long 0x00 4. "OCTL4,Port output control" "0,1"
newline
bitfld.long 0x00 3. "OCTL3,Port output control" "0,1"
bitfld.long 0x00 2. "OCTL2,Port output control" "0,1"
bitfld.long 0x00 1. "OCTL1,Port output control" "0,1"
bitfld.long 0x00 0. "OCTL0,Port output control" "0,1"
wgroup.long 0x10++0x03
line.long 0x00 "BOP,Port bit operate register"
bitfld.long 0x00 31. "CR15,Port 15 Clear bit" "0,1"
bitfld.long 0x00 30. "CR14,Port 14 Clear bit" "0,1"
bitfld.long 0x00 29. "CR13,Port 13 Clear bit" "0,1"
bitfld.long 0x00 28. "CR12,Port 12 Clear bit" "0,1"
newline
bitfld.long 0x00 27. "CR11,Port 11 Clear bit" "0,1"
bitfld.long 0x00 26. "CR10,Port 10 Clear bit" "0,1"
bitfld.long 0x00 25. "CR9,Port 9 Clear bit" "0,1"
bitfld.long 0x00 24. "CR8,Port 8 Clear bit" "0,1"
newline
bitfld.long 0x00 23. "CR7,Port 7 Clear bit" "0,1"
bitfld.long 0x00 22. "CR6,Port 6 Clear bit" "0,1"
bitfld.long 0x00 21. "CR5,Port 5 Clear bit" "0,1"
bitfld.long 0x00 20. "CR4,Port 4 Clear bit" "0,1"
newline
bitfld.long 0x00 19. "CR3,Port 3 Clear bit" "0,1"
bitfld.long 0x00 18. "CR2,Port 2 Clear bit" "0,1"
bitfld.long 0x00 17. "CR1,Port 1 Clear bit" "0,1"
bitfld.long 0x00 16. "CR0,Port 0 Clear bit" "0,1"
newline
bitfld.long 0x00 15. "BOP15,Port 15 Set bit" "0,1"
bitfld.long 0x00 14. "BOP14,Port 14 Set bit" "0,1"
bitfld.long 0x00 13. "BOP13,Port 13 Set bit" "0,1"
bitfld.long 0x00 12. "BOP12,Port 12 Set bit" "0,1"
newline
bitfld.long 0x00 11. "BOP11,Port 11 Set bit" "0,1"
bitfld.long 0x00 10. "BOP10,Port 10 Set bit" "0,1"
bitfld.long 0x00 9. "BOP9,Port 9 Set bit" "0,1"
bitfld.long 0x00 8. "BOP8,Port 8 Set bit" "0,1"
newline
bitfld.long 0x00 7. "BOP7,Port 7 Set bit" "0,1"
bitfld.long 0x00 6. "BOP6,Port 6 Set bit" "0,1"
bitfld.long 0x00 5. "BOP5,Port 5 Set bit" "0,1"
bitfld.long 0x00 4. "BOP4,Port 4 Set bit" "0,1"
newline
bitfld.long 0x00 3. "BOP3,Port 3 Set bit" "0,1"
bitfld.long 0x00 2. "BOP2,Port 2 Set bit" "0,1"
bitfld.long 0x00 1. "BOP1,Port 1 Set bit" "0,1"
bitfld.long 0x00 0. "BOP0,Port 0 Set bit" "0,1"
wgroup.long 0x14++0x03
line.long 0x00 "BC,Port bit clear register"
bitfld.long 0x00 15. "CR15,Port 15 Clear bit" "0,1"
bitfld.long 0x00 14. "CR14,Port 14 Clear bit" "0,1"
bitfld.long 0x00 13. "CR13,Port 13 Clear bit" "0,1"
bitfld.long 0x00 12. "CR12,Port 12 Clear bit" "0,1"
newline
bitfld.long 0x00 11. "CR11,Port 11 Clear bit" "0,1"
bitfld.long 0x00 10. "CR10,Port 10 Clear bit" "0,1"
bitfld.long 0x00 9. "CR9,Port 9 Clear bit" "0,1"
bitfld.long 0x00 8. "CR8,Port 8 Clear bit" "0,1"
newline
bitfld.long 0x00 7. "CR7,Port 7 Clear bit" "0,1"
bitfld.long 0x00 6. "CR6,Port 6 Clear bit" "0,1"
bitfld.long 0x00 5. "CR5,Port 5 Clear bit" "0,1"
bitfld.long 0x00 4. "CR4,Port 4 Clear bit" "0,1"
newline
bitfld.long 0x00 3. "CR3,Port 3 Clear bit" "0,1"
bitfld.long 0x00 2. "CR2,Port 2 Clear bit" "0,1"
bitfld.long 0x00 1. "CR1,Port 1 Clear bit" "0,1"
bitfld.long 0x00 0. "CR0,Port 0 Clear bit" "0,1"
group.long 0x18++0x03
line.long 0x00 "LOCK,GPIO port configuration lock register"
bitfld.long 0x00 16. "LKK,Lock sequence key" "0,1"
bitfld.long 0x00 15. "LK15,Port Lock bit 15" "0,1"
bitfld.long 0x00 14. "LK14,Port Lock bit 14" "0,1"
bitfld.long 0x00 13. "LK13,Port Lock bit 13" "0,1"
newline
bitfld.long 0x00 12. "LK12,Port Lock bit 12" "0,1"
bitfld.long 0x00 11. "LK11,Port Lock bit 11" "0,1"
bitfld.long 0x00 10. "LK10,Port Lock bit 10" "0,1"
bitfld.long 0x00 9. "LK9,Port Lock bit 9" "0,1"
newline
bitfld.long 0x00 8. "LK8,Port Lock bit 8" "0,1"
bitfld.long 0x00 7. "LK7,Port Lock bit 7" "0,1"
bitfld.long 0x00 6. "LK6,Port Lock bit 6" "0,1"
bitfld.long 0x00 5. "LK5,Port Lock bit 5" "0,1"
newline
bitfld.long 0x00 4. "LK4,Port Lock bit 4" "0,1"
bitfld.long 0x00 3. "LK3,Port Lock bit 3" "0,1"
bitfld.long 0x00 2. "LK2,Port Lock bit 2" "0,1"
bitfld.long 0x00 1. "LK1,Port Lock bit 1" "0,1"
newline
bitfld.long 0x00 0. "LK0,Port Lock bit 0" "0,1"
group.long 0x3C++0x03
line.long 0x00 "SPD,Port bit speed register"
bitfld.long 0x00 15. "SPD15,Port 15 output max speed bits" "0,1"
bitfld.long 0x00 14. "SPD14,Port 14 output max speed bits" "0,1"
bitfld.long 0x00 13. "SPD13,Port 13 output max speed bits" "0,1"
bitfld.long 0x00 12. "SPD12,Port 12 output max speed bits" "0,1"
newline
bitfld.long 0x00 11. "SPD11,Port 11 output max speed bits" "0,1"
bitfld.long 0x00 10. "SPD10,Port 10 output max speed bits" "0,1"
bitfld.long 0x00 9. "SPD9,Port 9 output max speed bits" "0,1"
bitfld.long 0x00 8. "SPD8,Port 8 output max speed bits" "0,1"
newline
bitfld.long 0x00 7. "SPD7,Port 7 output max speed bits" "0,1"
bitfld.long 0x00 6. "SPD6,Port 6 output max speed bits" "0,1"
bitfld.long 0x00 5. "SPD5,Port 5 output max speed bits" "0,1"
bitfld.long 0x00 4. "SPD4,Port 4 output max speed bits" "0,1"
newline
bitfld.long 0x00 3. "SPD3,Port 3 output max speed bits" "0,1"
bitfld.long 0x00 2. "SPD2,Port 2 output max speed bits" "0,1"
bitfld.long 0x00 1. "SPD1,Port 1 output max speed bits" "0,1"
bitfld.long 0x00 0. "SPD0,Port 0 output max speed bits" "0,1"
tree.end
tree.end
tree "I2C (Inter-Integrated Circuit)"
repeat 2. (list 0. 1.) (list ad:0x40005400 ad:0x40005800)
tree "I2C$1"
base $2
group.long 0x00++0x03
line.long 0x00 "CTL0,Control register 0"
bitfld.long 0x00 15. "SRESET,Software reset" "0,1"
bitfld.long 0x00 13. "SALT,SMBus alert" "0,1"
bitfld.long 0x00 12. "PECTRANS,PEC Transfer" "0,1"
bitfld.long 0x00 11. "POAP,Position of ACK and PEC when receiving" "0,1"
newline
bitfld.long 0x00 10. "ACKEN,Whether or not to send an ACK" "0,1"
bitfld.long 0x00 9. "STOP,Generate a STOP condition on I2C bus" "0,1"
bitfld.long 0x00 8. "START,Generate a START condition on I2C bus" "0,1"
bitfld.long 0x00 7. "SS,Whether to stretch SCL low when data is not ready in slave mode" "0,1"
newline
bitfld.long 0x00 6. "GCEN,Whether or not to response to a General Call (0x00)" "0,1"
bitfld.long 0x00 5. "PECEN,PEC Calculation Switch" "0,1"
bitfld.long 0x00 4. "ARPEN,ARP protocol in SMBus switch" "0,1"
bitfld.long 0x00 3. "SMBSEL,SMBusType Selection" "0,1"
newline
bitfld.long 0x00 1. "SMBEN,SMBus/I2C mode switch" "0,1"
bitfld.long 0x00 0. "I2CEN,I2C peripheral enable" "0,1"
group.long 0x04++0x03
line.long 0x00 "CTL1,Control register 1"
bitfld.long 0x00 12. "DMALST,Flag indicating DMA last transfer" "0,1"
bitfld.long 0x00 11. "DMAON,DMA mode switch" "0,1"
bitfld.long 0x00 10. "BUFIE,Buffer interrupt enable" "0,1"
bitfld.long 0x00 9. "EVIE,Event interrupt enable" "0,1"
newline
bitfld.long 0x00 8. "ERRIE,Error interrupt enable" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "I2CCLK,I2C Peripheral clock frequency"
group.long 0x08++0x03
line.long 0x00 "SADDR0,Slave address register 0"
bitfld.long 0x00 15. "ADDFORMAT,Address mode for the I2C slave" "0,1"
bitfld.long 0x00 8.--9. "ADDRESS9_8,Highest two bits of a 10-bit address" "0,1,2,3"
hexmask.long.byte 0x00 1.--7. 1. "ADDRESS7_1,7-bit address or bits 7:1 of a 10-bit address"
bitfld.long 0x00 0. "ADDRESS0,Bit 0 of a 10-bit address" "0,1"
group.long 0x0C++0x03
line.long 0x00 "SADDR1,Slave address register 1"
hexmask.long.byte 0x00 1.--7. 1. "ADDRESS2,Second I2C address for the slave in Dual-Address mode"
bitfld.long 0x00 0. "DUADEN,Dual-Address mode switch" "0,1"
group.long 0x10++0x03
line.long 0x00 "DATA,Transfer buffer register"
hexmask.long.byte 0x00 0.--7. 1. "TRB,Transmission or reception data buffer register"
group.long 0x14++0x03
line.long 0x00 "STAT0,Transfer status register 0"
bitfld.long 0x00 15. "SMBALT,SMBus Alert status" "0,1"
bitfld.long 0x00 14. "SMBTO,Timeout signal in SMBus mode" "0,1"
bitfld.long 0x00 12. "PECERR,PEC error when receiving data" "0,1"
bitfld.long 0x00 11. "OUERR,Over-run or under-run situation occurs in slave mode" "0,1"
newline
bitfld.long 0x00 10. "AERR,Acknowledge error" "0,1"
bitfld.long 0x00 9. "LOSTARB,Arbitration Lost in master mode" "0,1"
bitfld.long 0x00 8. "BERR,A bus error occurs indication a unexpected START or STOP condition on I2C bus" "0,1"
rbitfld.long 0x00 7. "TBE,I2C_DATA is Empty during transmitting" "0,1"
newline
rbitfld.long 0x00 6. "RBNE,I2C_DATA is not Empty during receiving" "0,1"
rbitfld.long 0x00 4. "STPDET,STOP condition detected in slave mode" "0,1"
rbitfld.long 0x00 3. "ADD10SEND,Header of 10-bit address is sent in master mode" "0,1"
rbitfld.long 0x00 2. "BTC,Byte transmission completed" "0,1"
newline
rbitfld.long 0x00 1. "ADDSEND,Address is sent in master mode or received and matches in slave mode" "0,1"
rbitfld.long 0x00 0. "SBSEND,START condition sent out in master mode" "0,1"
rgroup.long 0x18++0x03
line.long 0x00 "STAT1,Transfer status register 1"
hexmask.long.byte 0x00 8.--15. 1. "PECV,Packet Error Checking Value that calculated by hardware when PEC is enabled"
bitfld.long 0x00 7. "DUMODF,Dual Flag in slave mode" "0,1"
bitfld.long 0x00 6. "HSTSMB,SMBus Host Header detected in slave mode" "0,1"
bitfld.long 0x00 5. "DEFSMB,Default address of SMBusDevice" "0,1"
newline
bitfld.long 0x00 4. "RXGC,General call address (00h) received" "0,1"
bitfld.long 0x00 2. "TR,Whether the I2C is a transmitter or a receiver" "0,1"
bitfld.long 0x00 1. "I2CBSY,Busy flag" "0,1"
bitfld.long 0x00 0. "MASTER,A flag indicating whether I2C block is in master or slave mode" "0,1"
group.long 0x1C++0x03
line.long 0x00 "CKCFG,Clock configure register"
bitfld.long 0x00 15. "FAST,I2C speed selection in master mode" "0,1"
bitfld.long 0x00 14. "DTCY,Duty cycle in fast mode" "0,1"
hexmask.long.word 0x00 0.--11. 1. "CLKC,I2C Clock control in master mode"
group.long 0x20++0x03
line.long 0x00 "RT,Rise time register"
hexmask.long.byte 0x00 0.--6. 1. "RISETIME,Maximum rise time in master mode"
group.long 0x80++0x03
line.long 0x00 "SAMCS,SAM control and status register"
bitfld.long 0x00 15. "RFR,Rxframe rise flag" "0,1"
bitfld.long 0x00 14. "RFF,Rxframe fall flag" "0,1"
bitfld.long 0x00 13. "TFR,Txframe rise flag" "0,1"
bitfld.long 0x00 12. "TFF,Txframe fall flag" "0,1"
newline
bitfld.long 0x00 9. "RXF,level of rx frame signal" "0,1"
bitfld.long 0x00 8. "TXF,level of tx frame signal" "0,1"
bitfld.long 0x00 7. "RFRIE,Rx frame rise interrupt enable" "0,1"
bitfld.long 0x00 6. "RFFIE,Rx frame fall interrupt enable" "0,1"
newline
bitfld.long 0x00 5. "TFRIE,Tx frame rise interrupt enable" "0,1"
bitfld.long 0x00 4. "TFFIE,Tx frame fall interrupt enable" "0,1"
bitfld.long 0x00 1. "STOEN,SAM_V interface timeout detect enable" "0,1"
bitfld.long 0x00 0. "SAMEN,SAM_V interface enable" "0,1"
group.long 0x90++0x03
line.long 0x00 "CTL2,Control register 2"
hexmask.long.byte 0x00 9.--15. 1. "ADDM,ingnore specify bits"
bitfld.long 0x00 8. "RADD,slave address recorde enable" "0,1"
bitfld.long 0x00 4. "TOEN,Timeout calculation enable" "0,1"
bitfld.long 0x00 1. "SETM,Start Early Termination Mode" "0,1"
newline
bitfld.long 0x00 0. "FMPEN,Fast mode plus enable" "0,1"
group.long 0x94++0x03
line.long 0x00 "CS,Control and status register"
bitfld.long 0x00 9. "STPSENDIE,Interrupt enable for stop condition sent" "0,1"
bitfld.long 0x00 8. "STLOIE,Interrupt enable for start lost" "0,1"
bitfld.long 0x00 1. "STPSEND,Stop condition sent out in master mode" "0,1"
bitfld.long 0x00 0. "STLO,Start lost flag" "0,1"
group.long 0x98++0x03
line.long 0x00 "STATC,Status clear register"
bitfld.long 0x00 15. "SRCEN,Status register clear enable" "0,1"
bitfld.long 0x00 4. "STOPFC,STOPF status clear" "0,1"
bitfld.long 0x00 3. "ADD10SENDC,ADD10SEND status clear" "0,1"
bitfld.long 0x00 2. "BTCC,BTC status clear" "0,1"
newline
bitfld.long 0x00 1. "ADDSENDC,ADDSEND status clear" "0,1"
bitfld.long 0x00 0. "SBSENDC,Start send status clear" "0,1"
tree.end
repeat.end
tree "I2C2"
base ad:0x4000C000
group.long 0x00++0x03
line.long 0x00 "CTL0,Control register 0"
bitfld.long 0x00 23. "PECEN,PEC Calculation Switch" "0,1"
bitfld.long 0x00 22. "SMBALTEN,SMBus Alert enable" "0,1"
bitfld.long 0x00 21. "SMBDAEN,SMBus device default address enable" "0,1"
bitfld.long 0x00 20. "SMBHAEN,SMBus Host address enable" "0,1"
newline
bitfld.long 0x00 19. "GCEN,Whether or not to response to a General Call" "0,1"
bitfld.long 0x00 18. "WUEN,Wakeup from Deep-sleep mode enable" "0,1"
bitfld.long 0x00 17. "SS,Whether to stretch SCL low when data is not ready in slave mode" "0,1"
bitfld.long 0x00 16. "SBCTL,Slave byte control" "0,1"
newline
bitfld.long 0x00 15. "DENR,DMA enable for reception" "0,1"
bitfld.long 0x00 14. "DENT,DMA enable for transmission" "0,1"
bitfld.long 0x00 12. "ANOFF,Analog noise filter disable" "0,1"
bitfld.long 0x00 8.--11. "DNF,Digital noise filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 7. "ERRIE,Error interrupt enable" "0,1"
bitfld.long 0x00 6. "TCIE,Transfer complete interrupt enable" "0,1"
bitfld.long 0x00 5. "STPDETIE,Stop detection interrupt enable" "0,1"
bitfld.long 0x00 4. "NACKIE,Not acknowledge received interrupt enable" "0,1"
newline
bitfld.long 0x00 3. "ADDMIE,Address match interrupt enable in slave mode" "0,1"
bitfld.long 0x00 2. "RBNEIE,Receive interrupt enable" "0,1"
bitfld.long 0x00 1. "TIE,Receive interrupt enable" "0,1"
bitfld.long 0x00 0. "I2CEN,I2C peripheral enable" "0,1"
group.long 0x04++0x03
line.long 0x00 "CTL1,Control register 1"
bitfld.long 0x00 26. "PECTRANS,PEC Transfer" "0,1"
bitfld.long 0x00 25. "AUTOEND,Automatic end mode in master mode" "0,1"
bitfld.long 0x00 24. "RELOAD,Reload mode" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "BYTENUM,Number of bytes to be transferred"
newline
bitfld.long 0x00 15. "NACKEN,Generate NACK in slave mode" "0,1"
bitfld.long 0x00 14. "STOP,Generate a STOP condition on I2C bus" "0,1"
bitfld.long 0x00 13. "START,Generate a START condition on I2C bus" "0,1"
bitfld.long 0x00 12. "HEAD10R,10-bit address header executes read direction only in master receive mode" "0,1"
newline
bitfld.long 0x00 11. "ADD10EN,10-bit addressing mode enable in master mode" "0,1"
bitfld.long 0x00 10. "TRDIR,Transfer direction in master mode" "0,1"
hexmask.long.word 0x00 0.--9. 1. "SADDRESS,Slave address to be sent"
group.long 0x08++0x03
line.long 0x00 "SADDR0,Slave address register 0"
bitfld.long 0x00 15. "ADDRESSEN,I2C address enable" "0,1"
bitfld.long 0x00 10. "ADDFORMAT,Address mode for the I2C slave" "0,1"
bitfld.long 0x00 8.--9. "ADDRESS_8_9,7-bit address or bits 7:1 of a 10-bit address" "0,1,2,3"
hexmask.long.byte 0x00 1.--7. 1. "ADDRESS_1_7,Highest two bits of a 10-bit address"
newline
bitfld.long 0x00 0. "ADDRESS_0,Bit 0 of a 10-bit address" "0,1"
group.long 0x0C++0x03
line.long 0x00 "SADDR1,Slave address register 1"
bitfld.long 0x00 15. "ADDRESS2EN,Second I2C address enable" "0,1"
bitfld.long 0x00 8.--10. "ADDMSK2,ADDRESS2[7:1] mask" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 1.--7. 1. "ADDRESS2,Second I2C address for the slave"
group.long 0x10++0x03
line.long 0x00 "TIMING,Timing register"
bitfld.long 0x00 28.--31. "PSC,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "SCLDELY,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "SDADELY,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "SCLH,SCL high period"
newline
hexmask.long.byte 0x00 0.--7. 1. "SCLL,SCL low period"
group.long 0x14++0x03
line.long 0x00 "TIMEOUT,timeout register"
bitfld.long 0x00 31. "EXTOEN,Extended clock timeout detection enable" "0,1"
hexmask.long.word 0x00 16.--27. 1. "BUSTOB,Bus timeout B"
bitfld.long 0x00 15. "TOEN,Clock timeout detection enable" "0,1"
bitfld.long 0x00 12. "TOIDLE,Idle clock timeout detection" "0,1"
newline
hexmask.long.word 0x00 0.--11. 1. "BUSTOA,Bus timeout A"
group.long 0x18++0x03
line.long 0x00 "STAT,Transfer status register"
hexmask.long.byte 0x00 17.--23. 1. "READDR,Received match address in slave mode"
bitfld.long 0x00 16. "TR,Whether the I2C is a transmitter or a receiver in slave mode" "0,1"
bitfld.long 0x00 15. "I2CBSY,Busy flag" "0,1"
bitfld.long 0x00 13. "SMBALT,SMBus Alert" "0,1"
newline
bitfld.long 0x00 12. "TIMEOUT,TIMEOUT flag" "0,1"
bitfld.long 0x00 11. "PECERR,PEC error" "0,1"
bitfld.long 0x00 10. "OUERR,Overrun/Underrun error in slave mode" "0,1"
bitfld.long 0x00 9. "LOSTARB,Arbitration Lost" "0,1"
newline
bitfld.long 0x00 8. "BERR,Bus error" "0,1"
bitfld.long 0x00 7. "TCR,Transfer complete reload" "0,1"
bitfld.long 0x00 6. "TC,Transfer complete in master mode" "0,1"
bitfld.long 0x00 5. "STPDET,STOP condition is detected on the bus" "0,1"
newline
bitfld.long 0x00 4. "NACK,Not Acknowledge flag" "0,1"
bitfld.long 0x00 3. "ADDSEND,Address received matches in slave mode" "0,1"
bitfld.long 0x00 2. "RBNE,I2C_RDATA is not empty during receiving" "0,1"
bitfld.long 0x00 1. "TI,Transmit interrupt" "0,1"
newline
bitfld.long 0x00 0. "TBE,I2C_TDATA is empty during transmitting" "0,1"
group.long 0x1C++0x03
line.long 0x00 "STATC,Status clear register"
bitfld.long 0x00 13. "SMBALTC,SMBus Alert flag clear" "0,1"
bitfld.long 0x00 12. "TIMEOUTC,TIMEOUT flag clear" "0,1"
bitfld.long 0x00 11. "PECERRC,PEC error flag clear" "0,1"
bitfld.long 0x00 10. "OUERRC,Overrun/Underrun flag clear" "0,1"
newline
bitfld.long 0x00 9. "LOSTARBC,Arbitration Lost flag clear" "0,1"
bitfld.long 0x00 8. "BERRC,Bus error flag clear" "0,1"
bitfld.long 0x00 5. "STPDETC,STPDET flag clear" "0,1"
bitfld.long 0x00 4. "NACKC,Not Acknowledge flag clear" "0,1"
newline
bitfld.long 0x00 3. "ADDSENDC,ADDSEND flag clear" "0,1"
group.long 0x20++0x03
line.long 0x00 "PEC,Packet Error Checking"
hexmask.long.byte 0x00 0.--7. 1. "PECV,Packet Error Checking Value"
group.long 0x24++0x03
line.long 0x00 "RDATA,receive data register"
hexmask.long.byte 0x00 0.--7. 1. "RDATA,Receive data value"
group.long 0x28++0x03
line.long 0x00 "TDATA,Transmit data register"
hexmask.long.byte 0x00 0.--7. 1. "TDATA,Transmit data value"
tree.end
tree.end
tree "NVIC (Nested Vectored Interrupt Controller)"
base ad:0xE000E100
group.long 0x00++0x03
line.long 0x00 "ISER,Interrupt Set Enable Register"
hexmask.long 0x00 0.--31. 1. "SETENA,SETENA"
group.long 0x80++0x03
line.long 0x00 "ICER,Interrupt Clear Enable Register"
hexmask.long 0x00 0.--31. 1. "CLRENA,CLRENA"
group.long 0x100++0x03
line.long 0x00 "ISPR,Interrupt Set-Pending Register"
hexmask.long 0x00 0.--31. 1. "SETPEND,SETPEND"
group.long 0x180++0x03
line.long 0x00 "ICPR,Interrupt Clear-Pending Register"
hexmask.long 0x00 0.--31. 1. "CLRPEND,CLRPEND"
group.long 0x200++0x03
line.long 0x00 "IABR,Interrupt Active bit Register"
hexmask.long 0x00 0.--31. 1. "IABR,IABR"
group.byte 0x300++0x00
line.byte 0x00 "IPR0,Interrupt Priority Register 0"
hexmask.byte 0x00 0.--7. 1. "PRI_00,PRI_00"
group.byte 0x301++0x00
line.byte 0x00 "IPR1,Interrupt Priority Register 1"
hexmask.byte 0x00 0.--7. 1. "PRI_01,PRI_01"
group.byte 0x302++0x00
line.byte 0x00 "IPR2,Interrupt Priority Register 2"
hexmask.byte 0x00 0.--7. 1. "PRI_02,PRI_02"
group.byte 0x303++0x00
line.byte 0x00 "IPR3,Interrupt Priority Register 3"
hexmask.byte 0x00 0.--7. 1. "PRI_03,PRI_03"
group.byte 0x304++0x00
line.byte 0x00 "IPR4,Interrupt Priority Register 4"
hexmask.byte 0x00 0.--7. 1. "PRI_04,PRI_04"
group.byte 0x305++0x00
line.byte 0x00 "IPR5,Interrupt Priority Register 5"
hexmask.byte 0x00 0.--7. 1. "PRI_05,PRI_05"
group.byte 0x306++0x00
line.byte 0x00 "IPR6,Interrupt Priority Register 6"
hexmask.byte 0x00 0.--7. 1. "PRI_06,PRI_06"
group.byte 0x307++0x00
line.byte 0x00 "IPR7,Interrupt Priority Register 7"
hexmask.byte 0x00 0.--7. 1. "PRI_07,PRI_07"
group.byte 0x308++0x00
line.byte 0x00 "IPR8,Interrupt Priority Register 8"
hexmask.byte 0x00 0.--7. 1. "PRI_08,PRI_08"
group.byte 0x309++0x00
line.byte 0x00 "IPR9,Interrupt Priority Register 9"
hexmask.byte 0x00 0.--7. 1. "PRI_09,PRI_09"
group.byte 0x30A++0x00
line.byte 0x00 "IPR10,Interrupt Priority Register 10"
hexmask.byte 0x00 0.--7. 1. "PRI_10,PRI_10"
group.byte 0x30B++0x00
line.byte 0x00 "IPR11,Interrupt Priority Register 11"
hexmask.byte 0x00 0.--7. 1. "PRI_11,PRI_11"
group.byte 0x30C++0x00
line.byte 0x00 "IPR12,Interrupt Priority Register 12"
hexmask.byte 0x00 0.--7. 1. "PRI_12,PRI_12"
group.byte 0x30D++0x00
line.byte 0x00 "IPR13,Interrupt Priority Register 13"
hexmask.byte 0x00 0.--7. 1. "PRI_13,PRI_13"
group.byte 0x30E++0x00
line.byte 0x00 "IPR14,Interrupt Priority Register 14"
hexmask.byte 0x00 0.--7. 1. "PRI_14,PRI_14"
group.byte 0x30F++0x00
line.byte 0x00 "IPR15,Interrupt Priority Register 15"
hexmask.byte 0x00 0.--7. 1. "PRI_15,PRI_15"
group.byte 0x310++0x00
line.byte 0x00 "IPR16,Interrupt Priority Register 16"
hexmask.byte 0x00 0.--7. 1. "PRI_16,PRI_16"
group.byte 0x311++0x00
line.byte 0x00 "IPR17,Interrupt Priority Register 17"
hexmask.byte 0x00 0.--7. 1. "PRI_17,PRI_17"
group.byte 0x312++0x00
line.byte 0x00 "IPR18,Interrupt Priority Register 18"
hexmask.byte 0x00 0.--7. 1. "PRI_18,PRI_18"
group.byte 0x313++0x00
line.byte 0x00 "IPR19,Interrupt Priority Register 19"
hexmask.byte 0x00 0.--7. 1. "PRI_19,PRI_19"
group.byte 0x314++0x00
line.byte 0x00 "IPR20,Interrupt Priority Register 20"
hexmask.byte 0x00 0.--7. 1. "PRI_20,PRI_20"
group.byte 0x315++0x00
line.byte 0x00 "IPR21,Interrupt Priority Register 21"
hexmask.byte 0x00 0.--7. 1. "PRI_21,PRI_21"
group.byte 0x316++0x00
line.byte 0x00 "IPR22,Interrupt Priority Register 22"
hexmask.byte 0x00 0.--7. 1. "PRI_22,PRI_22"
group.byte 0x317++0x00
line.byte 0x00 "IPR23,Interrupt Priority Register 23"
hexmask.byte 0x00 0.--7. 1. "PRI_23,PRI_23"
group.byte 0x318++0x00
line.byte 0x00 "IPR24,Interrupt Priority Register 24"
hexmask.byte 0x00 0.--7. 1. "PRI_24,PRI_24"
group.byte 0x319++0x00
line.byte 0x00 "IPR25,Interrupt Priority Register 25"
hexmask.byte 0x00 0.--7. 1. "PRI_25,PRI_25"
group.byte 0x31A++0x00
line.byte 0x00 "IPR26,Interrupt Priority Register 26"
hexmask.byte 0x00 0.--7. 1. "PRI_26,PRI_26"
group.byte 0x31B++0x00
line.byte 0x00 "IPR27,Interrupt Priority Register 27"
hexmask.byte 0x00 0.--7. 1. "PRI_27,PRI_27"
group.byte 0x31C++0x00
line.byte 0x00 "IPR28,Interrupt Priority Register 28"
hexmask.byte 0x00 0.--7. 1. "PRI_28,PRI_28"
group.byte 0x31D++0x00
line.byte 0x00 "IPR29,Interrupt Priority Register 29"
hexmask.byte 0x00 0.--7. 1. "PRI_29,PRI_29"
group.byte 0x31E++0x00
line.byte 0x00 "IPR30,Interrupt Priority Register 30"
hexmask.byte 0x00 0.--7. 1. "PRI_30,PRI_30"
group.byte 0x31F++0x00
line.byte 0x00 "IPR31,Interrupt Priority Register 31"
hexmask.byte 0x00 0.--7. 1. "PRI_31,PRI_31"
group.byte 0x320++0x00
line.byte 0x00 "IPR32,Interrupt Priority Register 32"
hexmask.byte 0x00 0.--7. 1. "PRI_32,PRI_32"
group.byte 0x321++0x00
line.byte 0x00 "IPR33,Interrupt Priority Register 33"
hexmask.byte 0x00 0.--7. 1. "PRI_33,PRI_33"
group.byte 0x322++0x00
line.byte 0x00 "IPR34,Interrupt Priority Register 34"
hexmask.byte 0x00 0.--7. 1. "PRI_34,PRI_34"
group.byte 0x323++0x00
line.byte 0x00 "IPR35,Interrupt Priority Register 35"
hexmask.byte 0x00 0.--7. 1. "PRI_35,PRI_35"
group.byte 0x324++0x00
line.byte 0x00 "IPR36,Interrupt Priority Register 36"
hexmask.byte 0x00 0.--7. 1. "PRI_36,PRI_36"
group.byte 0x325++0x00
line.byte 0x00 "IPR37,Interrupt Priority Register 37"
hexmask.byte 0x00 0.--7. 1. "PRI_37,PRI_37"
group.byte 0x326++0x00
line.byte 0x00 "IPR38,Interrupt Priority Register 38"
hexmask.byte 0x00 0.--7. 1. "PRI_38,PRI_38"
group.byte 0x327++0x00
line.byte 0x00 "IPR39,Interrupt Priority Register 39"
hexmask.byte 0x00 0.--7. 1. "PRI_39,PRI_39"
group.byte 0x328++0x00
line.byte 0x00 "IPR40,Interrupt Priority Register 40"
hexmask.byte 0x00 0.--7. 1. "PRI_40,PRI_40"
group.byte 0x329++0x00
line.byte 0x00 "IPR41,Interrupt Priority Register 41"
hexmask.byte 0x00 0.--7. 1. "PRI_41,PRI_41"
group.byte 0x32A++0x00
line.byte 0x00 "IPR42,Interrupt Priority Register 42"
hexmask.byte 0x00 0.--7. 1. "PRI_42,PRI_42"
group.byte 0x32B++0x00
line.byte 0x00 "IPR43,Interrupt Priority Register 43"
hexmask.byte 0x00 0.--7. 1. "PRI_43,PRI_43"
group.byte 0x32C++0x00
line.byte 0x00 "IPR44,Interrupt Priority Register 44"
hexmask.byte 0x00 0.--7. 1. "PRI_44,PRI_44"
group.byte 0x32D++0x00
line.byte 0x00 "IPR45,Interrupt Priority Register 45"
hexmask.byte 0x00 0.--7. 1. "PRI_45,PRI_45"
group.byte 0x32E++0x00
line.byte 0x00 "IPR46,Interrupt Priority Register 46"
hexmask.byte 0x00 0.--7. 1. "PRI_46,PRI_46"
group.byte 0x32F++0x00
line.byte 0x00 "IPR47,Interrupt Priority Register 47"
hexmask.byte 0x00 0.--7. 1. "PRI_47,PRI_47"
group.byte 0x330++0x00
line.byte 0x00 "IPR48,Interrupt Priority Register 48"
hexmask.byte 0x00 0.--7. 1. "PRI_48,PRI_48"
group.byte 0x331++0x00
line.byte 0x00 "IPR49,Interrupt Priority Register 49"
hexmask.byte 0x00 0.--7. 1. "PRI_49,PRI_49"
group.byte 0x332++0x00
line.byte 0x00 "IPR50,Interrupt Priority Register 50"
hexmask.byte 0x00 0.--7. 1. "PRI_50,PRI_50"
group.byte 0x333++0x00
line.byte 0x00 "IPR51,Interrupt Priority Register 51"
hexmask.byte 0x00 0.--7. 1. "PRI_51,PRI_51"
group.byte 0x334++0x00
line.byte 0x00 "IPR52,Interrupt Priority Register 52"
hexmask.byte 0x00 0.--7. 1. "PRI_52,PRI_52"
group.byte 0x335++0x00
line.byte 0x00 "IPR53,Interrupt Priority Register 53"
hexmask.byte 0x00 0.--7. 1. "PRI_53,PRI_53"
group.byte 0x336++0x00
line.byte 0x00 "IPR54,Interrupt Priority Register 54"
hexmask.byte 0x00 0.--7. 1. "PRI_54,PRI_54"
group.byte 0x337++0x00
line.byte 0x00 "IPR55,Interrupt Priority Register 55"
hexmask.byte 0x00 0.--7. 1. "PRI_55,PRI_55"
group.byte 0x338++0x00
line.byte 0x00 "IPR56,Interrupt Priority Register 56"
hexmask.byte 0x00 0.--7. 1. "PRI_56,PRI_56"
group.byte 0x339++0x00
line.byte 0x00 "IPR57,Interrupt Priority Register 57"
hexmask.byte 0x00 0.--7. 1. "PRI_57,PRI_57"
group.byte 0x33A++0x00
line.byte 0x00 "IPR58,Interrupt Priority Register 58"
hexmask.byte 0x00 0.--7. 1. "PRI_58,PRI_58"
group.byte 0x33B++0x00
line.byte 0x00 "IPR59,Interrupt Priority Register 59"
hexmask.byte 0x00 0.--7. 1. "PRI_59,PRI_59"
group.byte 0x33C++0x00
line.byte 0x00 "IPR60,Interrupt Priority Register 60"
hexmask.byte 0x00 0.--7. 1. "PRI_60,PRI_60"
group.byte 0x33D++0x00
line.byte 0x00 "IPR61,Interrupt Priority Register 61"
hexmask.byte 0x00 0.--7. 1. "PRI_61,PRI_61"
group.byte 0x33E++0x00
line.byte 0x00 "IPR62,Interrupt Priority Register 62"
hexmask.byte 0x00 0.--7. 1. "PRI_62,PRI_62"
group.byte 0x33F++0x00
line.byte 0x00 "IPR63,Interrupt Priority Register 63"
hexmask.byte 0x00 0.--7. 1. "PRI_63,PRI_63"
group.byte 0x340++0x00
line.byte 0x00 "IPR64,Interrupt Priority Register 64"
hexmask.byte 0x00 0.--7. 1. "PRI_64,PRI_64"
group.byte 0x341++0x00
line.byte 0x00 "IPR65,Interrupt Priority Register 65"
hexmask.byte 0x00 0.--7. 1. "PRI_65,PRI_65"
group.byte 0x342++0x00
line.byte 0x00 "IPR66,Interrupt Priority Register 66"
hexmask.byte 0x00 0.--7. 1. "PRI_66,PRI_66"
group.byte 0x343++0x00
line.byte 0x00 "IPR67,Interrupt Priority Register 67"
hexmask.byte 0x00 0.--7. 1. "PRI_67,PRI_67"
wgroup.long 0xE00++0x03
line.long 0x00 "STIR,Software Trigger Interrupt Register"
hexmask.long 0x00 0.--31. 1. "STIR,STIR"
tree.end
tree "PMU (Program Memory Unit)"
base ad:0x40007000
group.long 0x00++0x03
line.long 0x00 "CTL0,power control register 0"
bitfld.long 0x00 18.--19. "LDEN,Low-driver mode enable in Deep-sleep mode" "0,1,2,3"
bitfld.long 0x00 17. "HDS,High-driver mode switch" "0,1"
bitfld.long 0x00 16. "HDEN,High-driver mode enable" "0,1"
bitfld.long 0x00 11. "LDNP,Low-driver mode when use normal power LDO" "0,1"
newline
bitfld.long 0x00 10. "LDLP,Low-driver mode when use low power LDO" "0,1"
bitfld.long 0x00 8. "BKPWEN,Backup Domain Write Enable" "0,1"
bitfld.long 0x00 5.--7. "LVDT,Low Voltage Detector Threshold" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "LVDEN,Low Voltage Detector Enable" "0,1"
newline
bitfld.long 0x00 3. "STBRST,Standby Flag Reset" "0,1"
bitfld.long 0x00 2. "WURST,Wakeup Flag Reset" "0,1"
bitfld.long 0x00 1. "STBMOD,Standby Mode" "0,1"
bitfld.long 0x00 0. "LDOLP,LDO Low Power Mode" "0,1"
group.long 0x04++0x03
line.long 0x00 "CS0,power control/status register 0"
bitfld.long 0x00 18.--19. "LDRF,Low-driver mode ready flag" "0,1,2,3"
rbitfld.long 0x00 17. "HDSRF,High-driver switch ready flag" "0,1"
rbitfld.long 0x00 16. "HDRF,High-driver ready flag" "0,1"
bitfld.long 0x00 15. "WUPEN7,Enable WKUP Pin7(PF8)" "0,1"
newline
bitfld.long 0x00 13. "WUPEN5,Enable WKUP pin5" "0,1"
bitfld.long 0x00 12. "WUPEN4,Enable WKUP pin4" "0,1"
bitfld.long 0x00 11. "WUPEN3,Enable WKUP pin3" "0,1"
bitfld.long 0x00 10. "WUPEN2,Enable WKUP pin2" "0,1"
newline
bitfld.long 0x00 9. "WUPEN1,Enable WKUP pin1" "0,1"
bitfld.long 0x00 8. "WUPEN0,Enable WKUP pin0" "0,1"
bitfld.long 0x00 7. "WUPEN6,Enable WKUP pin6" "0,1"
rbitfld.long 0x00 2. "LVDF,Low Voltage Detector Status Flag" "0,1"
newline
rbitfld.long 0x00 1. "STBF,Standby flag" "0,1"
rbitfld.long 0x00 0. "WUF,Wakeup flag" "0,1"
group.long 0x08++0x03
line.long 0x00 "CTL1,power control register 1"
bitfld.long 0x00 1. "DPMOD2,Enable deep-sleep 2 mode" "0,1"
bitfld.long 0x00 0. "DPMOD1,Enable deep-sleep 1 mode" "0,1"
group.long 0x0C++0x03
line.long 0x00 "CS1,power control and status register 1"
bitfld.long 0x00 1. "DPF2,Deep-sleep 2 mode status flag" "0,1"
bitfld.long 0x00 0. "DPF1,Deep-sleep1 mode status flag" "0,1"
tree.end
tree "RCU (Reset and clock unit)"
base ad:0x40021000
group.long 0x00++0x03
line.long 0x00 "CTL,Control register"
rbitfld.long 0x00 29. "PLL2STB,PLL2 Clock Stabilization Flag" "0,1"
bitfld.long 0x00 28. "PLL2EN,PLL2 enable" "0,1"
rbitfld.long 0x00 27. "PLL1STB,PLL1 Clock Stabilization Flag" "0,1"
bitfld.long 0x00 26. "PLL1EN,PLL1 enable" "0,1"
newline
rbitfld.long 0x00 25. "PLLSTB,PLL Clock Stabilization Flag" "0,1"
bitfld.long 0x00 24. "PLLEN,PLL enable" "0,1"
bitfld.long 0x00 19. "CKMEN,HXTAL Clock Monitor Enable" "0,1"
bitfld.long 0x00 18. "HXTALBPS,External crystal oscillator (HXTAL) clock bypass mode enable" "0,1"
newline
rbitfld.long 0x00 17. "HXTALSTB,External crystal oscillator (HXTAL) clock stabilization flag" "0,1"
bitfld.long 0x00 16. "HXTALEN,External High Speed oscillator Enable" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "IRC8MCALIB,Internal 8MHz RC Oscillator calibration value register"
bitfld.long 0x00 3.--7. "IRC8MADJ,Internal 8MHz RC Oscillator clock trim adjust value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 1. "IRC8MSTB,IRC8M Internal 8MHz RC Oscillator stabilization Flag" "0,1"
bitfld.long 0x00 0. "IRC8MEN,Internal 8MHz RC oscillator Enable" "0,1"
group.long 0x00++0x03
line.long 0x00 "CTL,Control register"
rbitfld.long 0x00 25. "PLLSTB,PLL Clock Stabilization Flag" "0,1"
bitfld.long 0x00 24. "PLLEN,PLL enable" "0,1"
bitfld.long 0x00 19. "CKMEN,HXTAL Clock Monitor Enable" "0,1"
bitfld.long 0x00 18. "HXTALBPS,External crystal oscillator (HXTAL) clock bypass mode enable" "0,1"
newline
rbitfld.long 0x00 17. "HXTALSTB,External crystal oscillator (HXTAL) clock stabilization flag" "0,1"
bitfld.long 0x00 16. "HXTALEN,External High Speed oscillator Enable" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "IRC8MCALIB,Internal 8MHz RC Oscillator calibration value register"
bitfld.long 0x00 3.--7. "IRC8MADJ,Internal 8MHz RC Oscillator clock trim adjust value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 1. "IRC8MSTB,IRC8M Internal 8MHz RC Oscillator stabilization Flag" "0,1"
bitfld.long 0x00 0. "IRC8MEN,Internal 8MHz RC oscillator Enable" "0,1"
group.long 0x04++0x03
line.long 0x00 "CFG0,Clock configuration register 0 (RCU_CFG0)"
bitfld.long 0x00 31. "USBHSPSC,Bit 2 of USBHSPSC" "0,1"
bitfld.long 0x00 29.--30. "PLLMF_5_4,Bit 5 and Bit 4 of PLLMF" "0,1,2,3"
bitfld.long 0x00 28. "ADCPSC_2,Bit 2 of ADCPSC" "0,1"
bitfld.long 0x00 24.--27. "CKOUT0SEL,CKOUT0 Clock Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 22.--23. "USBHSPSC_1_0,USBHS clock prescaler selection" "0,1,2,3"
bitfld.long 0x00 18.--21. "PLLMF_3_0,The PLL clock multiplication factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 17. "PREDV0_LSB,The LSB of PREDV0 division factor" "0,1"
bitfld.long 0x00 16. "PLLSEL,PLL Clock Source Selection" "0,1"
newline
bitfld.long 0x00 14.--15. "ADCPSC_1_0,ADC clock prescaler selection" "0,1,2,3"
bitfld.long 0x00 11.--13. "APB2PSC,APB2 prescaler selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--10. "APB1PSC,APB1 prescaler selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--7. "AHBPSC,AHB prescaler selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 2.--3. "SCSS,System clock switch status" "0,1,2,3"
bitfld.long 0x00 0.--1. "SCS,System clock switch" "0,1,2,3"
group.long 0x04++0x03
line.long 0x00 "CFG0,Clock configuration register 0 (RCU_CFG0)"
bitfld.long 0x00 31. "USBDPSC_2,Bit 2 of USBHSPSC" "0,1"
bitfld.long 0x00 29. "PLLMF_5,Bit 5 of PLLMF" "0,1"
bitfld.long 0x00 28. "ADCPSC_2,Bit 2 of ADCPSC" "0,1"
bitfld.long 0x00 27. "PLLMF_4,Bit 4 of PLLMF" "0,1"
newline
bitfld.long 0x00 24.--26. "CKOUT0SEL,CKOUT0 Clock Source Selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 22.--23. "USBDPSC,USBD clock prescaler selection" "0,1,2,3"
bitfld.long 0x00 18.--21. "PLLMF_3_0,The PLL clock multiplication factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 17. "PREDV0,PREDV0 division factor" "0,1"
newline
bitfld.long 0x00 16. "PLLSEL,PLL Clock Source Selection" "0,1"
bitfld.long 0x00 14.--15. "ADCPSC_1_0,ADC clock prescaler selection" "0,1,2,3"
bitfld.long 0x00 11.--13. "APB2PSC,APB2 prescaler selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--10. "APB1PSC,APB1 prescaler selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--7. "AHBPSC,AHB prescaler selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 2.--3. "SCSS,System clock switch status" "0,1,2,3"
bitfld.long 0x00 0.--1. "SCS,System clock switch" "0,1,2,3"
group.long 0x08++0x03
line.long 0x00 "INT,Clock interrupt register (RCU_INT)"
bitfld.long 0x00 23. "CKMIC,HXTAL Clock Stuck Interrupt Clear" "0,1"
bitfld.long 0x00 20. "PLLSTBIC,PLL stabilization Interrupt Clear" "0,1"
bitfld.long 0x00 19. "HXTALSTBIC,HXTAL Stabilization Interrupt Clear" "0,1"
bitfld.long 0x00 18. "IRC8MSTBIC,IRC8M Stabilization Interrupt Clear" "0,1"
newline
bitfld.long 0x00 17. "LXTALSTBIC,LXTAL Stabilization Interrupt Clear" "0,1"
bitfld.long 0x00 16. "IRC40KSTBIC,IRC40K Stabilization Interrupt Clear" "0,1"
bitfld.long 0x00 12. "PLLSTBIE,PLL Stabilization Interrupt Enable" "0,1"
bitfld.long 0x00 11. "HXTALSTBIE,HXTAL Stabilization Interrupt Enable" "0,1"
newline
bitfld.long 0x00 10. "IRC8MSTBIE,IRC8M Stabilization Interrupt Enable" "0,1"
bitfld.long 0x00 9. "LXTALSTBIE,LXTAL Stabilization Interrupt Enable" "0,1"
bitfld.long 0x00 8. "IRC40KSTBIE,IRC40K Stabilization interrupt enable" "0,1"
rbitfld.long 0x00 7. "CKMIF,HXTAL Clock Stuck Interrupt Flag" "0,1"
newline
rbitfld.long 0x00 4. "PLLSTBIF,PLL stabilization interrupt flag" "0,1"
rbitfld.long 0x00 3. "HXTALSTBIF,HXTAL stabilization interrupt flag" "0,1"
rbitfld.long 0x00 2. "IRC8MSTBIF,IRC8M stabilization interrupt flag" "0,1"
rbitfld.long 0x00 1. "LXTALSTBIF,LXTAL stabilization interrupt flag" "0,1"
newline
rbitfld.long 0x00 0. "IRC40KSTBIF,IRC40K stabilization interrupt flag" "0,1"
group.long 0x08++0x03
line.long 0x00 "INT,Clock interrupt register (RCU_INT)"
bitfld.long 0x00 23. "CKMIC,HXTAL Clock Stuck Interrupt Clear" "0,1"
bitfld.long 0x00 22. "PLL2STBIC,PLL2 stabilization Interrupt Clear" "0,1"
bitfld.long 0x00 21. "PLL1STBIC,PLL1 stabilization Interrupt Clear" "0,1"
bitfld.long 0x00 20. "PLLSTBIC,PLL stabilization Interrupt Clear" "0,1"
newline
bitfld.long 0x00 19. "HXTALSTBIC,HXTAL Stabilization Interrupt Clear" "0,1"
bitfld.long 0x00 18. "IRC8MSTBIC,IRC8M Stabilization Interrupt Clear" "0,1"
bitfld.long 0x00 17. "LXTALSTBIC,LXTAL Stabilization Interrupt Clear" "0,1"
bitfld.long 0x00 16. "IRC40KSTBIC,IRC40K Stabilization Interrupt Clear" "0,1"
newline
bitfld.long 0x00 14. "PLL2STBIE,PLL2 Stabilization Interrupt Enable" "0,1"
bitfld.long 0x00 13. "PLL1STBIE,PLL1 Stabilization Interrupt Enable" "0,1"
bitfld.long 0x00 12. "PLLSTBIE,PLL Stabilization Interrupt Enable" "0,1"
bitfld.long 0x00 11. "HXTALSTBIE,HXTAL Stabilization Interrupt Enable" "0,1"
newline
bitfld.long 0x00 10. "IRC8MSTBIE,IRC8M Stabilization Interrupt Enable" "0,1"
bitfld.long 0x00 9. "LXTALSTBIE,LXTAL Stabilization Interrupt Enable" "0,1"
bitfld.long 0x00 8. "IRC40KSTBIE,IRC40K Stabilization interrupt enable" "0,1"
rbitfld.long 0x00 7. "CKMIF,HXTAL Clock Stuck Interrupt Flag" "0,1"
newline
rbitfld.long 0x00 6. "PLL2STBIF,PLL2 stabilization interrupt flag" "0,1"
rbitfld.long 0x00 5. "PLL1STBIF,PLL1 stabilization interrupt flag" "0,1"
rbitfld.long 0x00 4. "PLLSTBIF,PLL stabilization interrupt flag" "0,1"
rbitfld.long 0x00 3. "HXTALSTBIF,HXTAL stabilization interrupt flag" "0,1"
newline
rbitfld.long 0x00 2. "IRC8MSTBIF,IRC8M stabilization interrupt flag" "0,1"
rbitfld.long 0x00 1. "LXTALSTBIF,LXTAL stabilization interrupt flag" "0,1"
rbitfld.long 0x00 0. "IRC40KSTBIF,IRC40K stabilization interrupt flag" "0,1"
group.long 0x0C++0x03
line.long 0x00 "APB2RST,APB2 reset register (RCU_APB2RST)"
bitfld.long 0x00 31. "CMPRST,CMP reset" "0,1"
bitfld.long 0x00 29. "SHRTIMERRST,SHRTIMER reset" "0,1"
bitfld.long 0x00 28. "USART5RST,USART5 reset" "0,1"
bitfld.long 0x00 21. "TIMER10RST,Timer 10 reset" "0,1"
newline
bitfld.long 0x00 20. "TIMER9RST,Timer 9 reset" "0,1"
bitfld.long 0x00 19. "TIMER8RST,Timer 8 reset" "0,1"
bitfld.long 0x00 15. "ADC2RST,ADC2 reset" "0,1"
bitfld.long 0x00 14. "USART0RST,USART0 Reset" "0,1"
newline
bitfld.long 0x00 13. "TIMER7RST,Timer 7 reset" "0,1"
bitfld.long 0x00 12. "SPI0RST,SPI0 reset" "0,1"
bitfld.long 0x00 11. "TIMER0RST,Timer 0 reset" "0,1"
bitfld.long 0x00 10. "ADC1RST,ADC1 reset" "0,1"
newline
bitfld.long 0x00 9. "ADC0RST,ADC0 reset" "0,1"
bitfld.long 0x00 8. "PGRST,GPIO port G reset" "0,1"
bitfld.long 0x00 7. "PFRST,GPIO portF reset" "0,1"
bitfld.long 0x00 6. "PERST,GPIO port E reset" "0,1"
newline
bitfld.long 0x00 5. "PDRST,GPIO port D reset" "0,1"
bitfld.long 0x00 4. "PCRST,GPIO port C reset" "0,1"
bitfld.long 0x00 3. "PBRST,GPIO port B reset" "0,1"
bitfld.long 0x00 2. "PARST,GPIO port A reset" "0,1"
newline
bitfld.long 0x00 0. "AFRST,Alternate function I/O reset" "0,1"
group.long 0x0C++0x03
line.long 0x00 "APB2RST,APB2 reset register (RCU_APB2RST)"
bitfld.long 0x00 29. "SHRTIMERRST,SHRTIMER reset" "0,1"
bitfld.long 0x00 28. "USART5RST,USART5 reset" "0,1"
bitfld.long 0x00 21. "TIMER10RST,Timer 10 reset" "0,1"
bitfld.long 0x00 20. "TIMER9RST,Timer 9 reset" "0,1"
newline
bitfld.long 0x00 19. "TIMER8RST,Timer 8 reset" "0,1"
bitfld.long 0x00 15. "ADC2RST,ADC2 reset" "0,1"
bitfld.long 0x00 14. "USART0RST,USART0 Reset" "0,1"
bitfld.long 0x00 13. "TIMER7RST,Timer 7 reset" "0,1"
newline
bitfld.long 0x00 12. "SPI0RST,SPI0 reset" "0,1"
bitfld.long 0x00 11. "TIMER0RST,Timer 0 reset" "0,1"
bitfld.long 0x00 10. "ADC1RST,ADC1 reset" "0,1"
bitfld.long 0x00 9. "ADC0RST,ADC0 reset" "0,1"
newline
bitfld.long 0x00 8. "PGRST,GPIO port G reset" "0,1"
bitfld.long 0x00 7. "PFRST,GPIO portF reset" "0,1"
bitfld.long 0x00 6. "PERST,GPIO port E reset" "0,1"
bitfld.long 0x00 5. "PDRST,GPIO port D reset" "0,1"
newline
bitfld.long 0x00 4. "PCRST,GPIO port C reset" "0,1"
bitfld.long 0x00 3. "PBRST,GPIO port B reset" "0,1"
bitfld.long 0x00 2. "PARST,GPIO port A reset" "0,1"
bitfld.long 0x00 0. "AFRST,Alternate function I/O reset" "0,1"
group.long 0x10++0x03
line.long 0x00 "APB1RST,APB1 reset register (RCU_APB1RST)"
bitfld.long 0x00 29. "DACRST,DAC reset" "0,1"
bitfld.long 0x00 28. "PMURST,Power control reset" "0,1"
bitfld.long 0x00 27. "BKPIRST,Backup interface reset" "0,1"
bitfld.long 0x00 24. "I2C2RST,I2C2 reset" "0,1"
newline
bitfld.long 0x00 23. "USBDRST,USBD reset" "0,1"
bitfld.long 0x00 22. "I2C1RST,I2C1 reset" "0,1"
bitfld.long 0x00 21. "I2C0RST,I2C0 reset" "0,1"
bitfld.long 0x00 20. "UART4RST,UART4 reset" "0,1"
newline
bitfld.long 0x00 19. "UART3RST,UART3 reset" "0,1"
bitfld.long 0x00 18. "USART2RST,USART2 reset" "0,1"
bitfld.long 0x00 17. "USART1RST,USART1 reset" "0,1"
bitfld.long 0x00 15. "SPI2RST,SPI2 reset" "0,1"
newline
bitfld.long 0x00 14. "SPI1RST,SPI1 reset" "0,1"
bitfld.long 0x00 11. "WWDGTRST,Window watchdog timer reset" "0,1"
bitfld.long 0x00 8. "TIMER13RST,TIMER13 timer reset" "0,1"
bitfld.long 0x00 7. "TIMER12RST,TIMER12 timer reset" "0,1"
newline
bitfld.long 0x00 6. "TIMER11RST,TIMER11 timer reset" "0,1"
bitfld.long 0x00 5. "TIMER6RST,TIMER6 timer reset" "0,1"
bitfld.long 0x00 4. "TIMER5RST,TIMER5 timer reset" "0,1"
bitfld.long 0x00 3. "TIMER4RST,TIMER4 timer reset" "0,1"
newline
bitfld.long 0x00 2. "TIMER3RST,TIMER3 timer reset" "0,1"
bitfld.long 0x00 1. "TIMER2RST,TIMER2 timer reset" "0,1"
bitfld.long 0x00 0. "TIMER1RST,TIMER1 timer reset" "0,1"
group.long 0x10++0x03
line.long 0x00 "APB1RST,APB1 reset register (RCU_APB1RST)"
bitfld.long 0x00 29. "DACRST,DAC reset" "0,1"
bitfld.long 0x00 28. "PMURST,Power control reset" "0,1"
bitfld.long 0x00 27. "BKPIRST,Backup interface reset" "0,1"
bitfld.long 0x00 24. "I2C2RST,I2C2 reset" "0,1"
newline
bitfld.long 0x00 22. "I2C1RST,I2C1 reset" "0,1"
bitfld.long 0x00 21. "I2C0RST,I2C0 reset" "0,1"
bitfld.long 0x00 20. "UART4RST,UART4 reset" "0,1"
bitfld.long 0x00 19. "UART3RST,UART3 reset" "0,1"
newline
bitfld.long 0x00 18. "USART2RST,USART2 reset" "0,1"
bitfld.long 0x00 17. "USART1RST,USART1 reset" "0,1"
bitfld.long 0x00 15. "SPI2RST,SPI2 reset" "0,1"
bitfld.long 0x00 14. "SPI1RST,SPI1 reset" "0,1"
newline
bitfld.long 0x00 11. "WWDGTRST,Window watchdog timer reset" "0,1"
bitfld.long 0x00 8. "TIMER13RST,TIMER13 timer reset" "0,1"
bitfld.long 0x00 7. "TIMER12RST,TIMER12 timer reset" "0,1"
bitfld.long 0x00 6. "TIMER11RST,TIMER11 timer reset" "0,1"
newline
bitfld.long 0x00 5. "TIMER6RST,TIMER6 timer reset" "0,1"
bitfld.long 0x00 4. "TIMER5RST,TIMER5 timer reset" "0,1"
bitfld.long 0x00 3. "TIMER4RST,TIMER4 timer reset" "0,1"
bitfld.long 0x00 2. "TIMER3RST,TIMER3 timer reset" "0,1"
newline
bitfld.long 0x00 1. "TIMER2RST,TIMER2 timer reset" "0,1"
bitfld.long 0x00 0. "TIMER1RST,TIMER1 timer reset" "0,1"
group.long 0x14++0x03
line.long 0x00 "AHBEN,AHB enable register"
bitfld.long 0x00 31. "SQPIEN,SQPI clock enable" "0,1"
bitfld.long 0x00 10. "SDIOEN,SDIO clock enable" "0,1"
bitfld.long 0x00 8. "EXMCEN,EXMC clock enable" "0,1"
bitfld.long 0x00 6. "CRCEN,CRC clock enable" "0,1"
newline
bitfld.long 0x00 4. "FMCSPEN,FMC clock enable when sleep mode" "0,1"
bitfld.long 0x00 2. "SRAMSPEN,SRAM interface clock enable when sleep mode" "0,1"
bitfld.long 0x00 1. "DMA1EN,DMA1 clock enable" "0,1"
bitfld.long 0x00 0. "DMA0EN,DMA0 clock enable" "0,1"
group.long 0x14++0x03
line.long 0x00 "AHBEN,AHB enable register"
bitfld.long 0x00 31. "SQPIEN,SQPI clock enable" "0,1"
bitfld.long 0x00 30. "TMUEN,TMU clock enable" "0,1"
bitfld.long 0x00 16. "ENETRXEN,Ethernet RX clock enable" "0,1"
bitfld.long 0x00 15. "ENETTXEN,Ethernet TX clock enable" "0,1"
newline
bitfld.long 0x00 14. "ENETEN,Ethernet clock enable" "0,1"
bitfld.long 0x00 13. "ULPIEN,ULPI clock enable" "0,1"
bitfld.long 0x00 12. "USBHSEN,USBFS clock enable" "0,1"
bitfld.long 0x00 8. "EXMCEN,EXMC clock enable" "0,1"
newline
bitfld.long 0x00 6. "CRCEN,CRC clock enable" "0,1"
bitfld.long 0x00 4. "FMCSPEN,FMC clock enable when sleep mode" "0,1"
bitfld.long 0x00 2. "SRAMSPEN,SRAM interface clock enable when sleep mode" "0,1"
bitfld.long 0x00 1. "DMA1EN,DMA1 clock enable" "0,1"
newline
bitfld.long 0x00 0. "DMA0EN,DMA0 clock enable" "0,1"
group.long 0x18++0x03
line.long 0x00 "APB2EN,APB2 clock enable register (RCU_APB2EN)"
bitfld.long 0x00 31. "CMPEN,CMP clock enable" "0,1"
bitfld.long 0x00 29. "SHRTIMEREN,SHRTIMER clock enable" "0,1"
bitfld.long 0x00 28. "USART5EN,USART5 clock enable" "0,1"
bitfld.long 0x00 21. "TIMER10EN,TIMER10 clock enable" "0,1"
newline
bitfld.long 0x00 20. "TIMER9EN,TIMER9 clock enable" "0,1"
bitfld.long 0x00 19. "TIMER8EN,TIMER8 clock enable" "0,1"
bitfld.long 0x00 15. "ADC2EN,ADC2 clock enable" "0,1"
bitfld.long 0x00 14. "USART0EN,USART0 clock enable" "0,1"
newline
bitfld.long 0x00 13. "TIMER7EN,TIMER7 clock enable" "0,1"
bitfld.long 0x00 12. "SPI0EN,SPI0 clock enable" "0,1"
bitfld.long 0x00 11. "TIMER0EN,TIMER0 clock enable" "0,1"
bitfld.long 0x00 10. "ADC1EN,ADC1 clock enable" "0,1"
newline
bitfld.long 0x00 9. "ADC0EN,ADC0 clock enable" "0,1"
bitfld.long 0x00 8. "PGEN,GPIO port G clock enable" "0,1"
bitfld.long 0x00 7. "PFEN,GPIO port F clock enable" "0,1"
bitfld.long 0x00 6. "PEEN,GPIO port E clock enable" "0,1"
newline
bitfld.long 0x00 5. "PDEN,GPIO port D clock enable" "0,1"
bitfld.long 0x00 4. "PCEN,GPIO port C clock enable" "0,1"
bitfld.long 0x00 3. "PBEN,GPIO port B clock enable" "0,1"
bitfld.long 0x00 2. "PAEN,GPIO port A clock enable" "0,1"
newline
bitfld.long 0x00 0. "AFEN,Alternate function IO clock enable" "0,1"
group.long 0x18++0x03
line.long 0x00 "APB2EN,APB2 clock enable register (RCU_APB2EN)"
bitfld.long 0x00 29. "SHRTIMEREN,SHRTIMER clock enable" "0,1"
bitfld.long 0x00 28. "USART5EN,USART5 clock enable" "0,1"
bitfld.long 0x00 21. "TIMER10EN,TIMER10 clock enable" "0,1"
bitfld.long 0x00 20. "TIMER9EN,TIMER9 clock enable" "0,1"
newline
bitfld.long 0x00 19. "TIMER8EN,TIMER8 clock enable" "0,1"
bitfld.long 0x00 15. "ADC2EN,ADC2 clock enable" "0,1"
bitfld.long 0x00 14. "USART0EN,USART0 clock enable" "0,1"
bitfld.long 0x00 13. "TIMER7EN,TIMER7 clock enable" "0,1"
newline
bitfld.long 0x00 12. "SPI0EN,SPI0 clock enable" "0,1"
bitfld.long 0x00 11. "TIMER0EN,TIMER0 clock enable" "0,1"
bitfld.long 0x00 10. "ADC1EN,ADC1 clock enable" "0,1"
bitfld.long 0x00 9. "ADC0EN,ADC0 clock enable" "0,1"
newline
bitfld.long 0x00 8. "PGEN,GPIO port G clock enable" "0,1"
bitfld.long 0x00 7. "PFEN,GPIO port F clock enable" "0,1"
bitfld.long 0x00 6. "PEEN,GPIO port E clock enable" "0,1"
bitfld.long 0x00 5. "PDEN,GPIO port D clock enable" "0,1"
newline
bitfld.long 0x00 4. "PCEN,GPIO port C clock enable" "0,1"
bitfld.long 0x00 3. "PBEN,GPIO port B clock enable" "0,1"
bitfld.long 0x00 2. "PAEN,GPIO port A clock enable" "0,1"
bitfld.long 0x00 0. "AFEN,Alternate function IO clock enable" "0,1"
group.long 0x1C++0x03
line.long 0x00 "APB1EN,APB1 clock enable register (RCU_APB1EN)"
bitfld.long 0x00 29. "DACEN,DAC clock enable" "0,1"
bitfld.long 0x00 28. "PMUEN,Power control clock enable" "0,1"
bitfld.long 0x00 27. "BKPIEN,Backup interface clock enable" "0,1"
bitfld.long 0x00 24. "I2C2EN,I2C2 clock enable" "0,1"
newline
bitfld.long 0x00 22. "I2C1EN,I2C1 clock enable" "0,1"
bitfld.long 0x00 21. "I2C0EN,I2C0 clock enable" "0,1"
bitfld.long 0x00 20. "UART4EN,UART4 clock enable" "0,1"
bitfld.long 0x00 19. "UART3EN,UART3 clock enable" "0,1"
newline
bitfld.long 0x00 18. "USART2EN,USART2 clock enable" "0,1"
bitfld.long 0x00 17. "USART1EN,USART1 clock enable" "0,1"
bitfld.long 0x00 15. "SPI2EN,SPI2 clock enable" "0,1"
bitfld.long 0x00 14. "SPI1EN,SPI1 clock enable" "0,1"
newline
bitfld.long 0x00 11. "WWDGTEN,Window watchdog timer clock enable" "0,1"
bitfld.long 0x00 8. "TIMER13EN,TIMER13 timer clock enable" "0,1"
bitfld.long 0x00 7. "TIMER12EN,TIMER12 timer clock enable" "0,1"
bitfld.long 0x00 6. "TIMER11EN,TIMER11 timer clock enable" "0,1"
newline
bitfld.long 0x00 5. "TIMER6EN,TIMER6 timer clock enable" "0,1"
bitfld.long 0x00 4. "TIMER5EN,TIMER5 timer clock enable" "0,1"
bitfld.long 0x00 3. "TIMER4EN,TIMER4 timer clock enable" "0,1"
bitfld.long 0x00 2. "TIMER3EN,TIMER3 timer clock enable" "0,1"
newline
bitfld.long 0x00 1. "TIMER2EN,TIMER2 timer clock enable" "0,1"
bitfld.long 0x00 0. "TIMER1EN,TIMER1 timer clock enable" "0,1"
group.long 0x1C++0x03
line.long 0x00 "APB1EN,APB1 clock enable register (RCU_APB1EN)"
bitfld.long 0x00 29. "DACEN,DAC clock enable" "0,1"
bitfld.long 0x00 28. "PMUEN,Power control clock enable" "0,1"
bitfld.long 0x00 27. "BKPIEN,Backup interface clock enable" "0,1"
bitfld.long 0x00 24. "I2C2EN,I2C2 clock enable" "0,1"
newline
bitfld.long 0x00 23. "USBDEN,USBD clock enable" "0,1"
bitfld.long 0x00 22. "I2C1EN,I2C1 clock enable" "0,1"
bitfld.long 0x00 21. "I2C0EN,I2C0 clock enable" "0,1"
bitfld.long 0x00 20. "UART4EN,UART4 clock enable" "0,1"
newline
bitfld.long 0x00 19. "UART3EN,UART3 clock enable" "0,1"
bitfld.long 0x00 18. "USART2EN,USART2 clock enable" "0,1"
bitfld.long 0x00 17. "USART1EN,USART1 clock enable" "0,1"
bitfld.long 0x00 15. "SPI2EN,SPI2 clock enable" "0,1"
newline
bitfld.long 0x00 14. "SPI1EN,SPI1 clock enable" "0,1"
bitfld.long 0x00 11. "WWDGTEN,Window watchdog timer clock enable" "0,1"
bitfld.long 0x00 8. "TIMER13EN,TIMER13 timer clock enable" "0,1"
bitfld.long 0x00 7. "TIMER12EN,TIMER12 timer clock enable" "0,1"
newline
bitfld.long 0x00 6. "TIMER11EN,TIMER11 timer clock enable" "0,1"
bitfld.long 0x00 5. "TIMER6EN,TIMER6 timer clock enable" "0,1"
bitfld.long 0x00 4. "TIMER5EN,TIMER5 timer clock enable" "0,1"
bitfld.long 0x00 3. "TIMER4EN,TIMER4 timer clock enable" "0,1"
newline
bitfld.long 0x00 2. "TIMER3EN,TIMER3 timer clock enable" "0,1"
bitfld.long 0x00 1. "TIMER2EN,TIMER2 timer clock enable" "0,1"
bitfld.long 0x00 0. "TIMER1EN,TIMER1 timer clock enable" "0,1"
group.long 0x20++0x03
line.long 0x00 "BDCTL,Backup domain control register (RCU_BDCTL)"
bitfld.long 0x00 16. "BKPRST,Backup domain reset" "0,1"
bitfld.long 0x00 15. "RTCEN,RTC clock enable" "0,1"
bitfld.long 0x00 8.--9. "RTCSRC,RTC clock entry selection" "0,1,2,3"
bitfld.long 0x00 3.--4. "LXTALDRI,LXTAL drive capability" "0,1,2,3"
newline
bitfld.long 0x00 2. "LXTALBPS,LXTAL bypass mode enable" "0,1"
rbitfld.long 0x00 1. "LXTALSTB,External low-speed oscillator stabilization" "0,1"
bitfld.long 0x00 0. "LXTALEN,LXTAL enable" "0,1"
group.long 0x24++0x03
line.long 0x00 "RSTSCK,Reset source /clock register (RCU_RSTSCK)"
rbitfld.long 0x00 31. "LPRSTF,Low-power reset flag" "0,1"
rbitfld.long 0x00 30. "WWDGTRSTF,Window watchdog timer reset flag" "0,1"
rbitfld.long 0x00 29. "FWDGTRSTF,Free Watchdog timer reset flag" "0,1"
rbitfld.long 0x00 28. "SWRSTF,Software reset flag" "0,1"
newline
rbitfld.long 0x00 27. "PORRSTF,Power reset flag" "0,1"
rbitfld.long 0x00 26. "EPRSTF,External PIN reset flag" "0,1"
bitfld.long 0x00 25. "BORRSTF,BORt flag clear" "0,1"
bitfld.long 0x00 24. "RSTFC,Reset flag clear" "0,1"
newline
rbitfld.long 0x00 1. "IRC40KSTB,IRC40K stabilization" "0,1"
bitfld.long 0x00 0. "IRC40KEN,IRC40K enable" "0,1"
group.long 0x28++0x03
line.long 0x00 "AHBRST,AHB reset register"
bitfld.long 0x00 31. "SQPIRST,SQPI reset" "0,1"
bitfld.long 0x00 30. "TMURST,TMU reset" "0,1"
bitfld.long 0x00 14. "ENETRST,ENET reset" "0,1"
bitfld.long 0x00 12. "USBHSRST,USBHS reset" "0,1"
group.long 0x28++0x03
line.long 0x00 "AHBRST,AHB reset register"
bitfld.long 0x00 31. "SQPIRST,SQPI reset" "0,1"
group.long 0x2C++0x03
line.long 0x00 "CFG1,Clock Configuration register 1"
bitfld.long 0x00 31. "PLL2MF_4,Bit 4 of PLL2MF" "0,1"
bitfld.long 0x00 30. "PLLPRESEL,PLL Clock Source Selection" "0,1"
bitfld.long 0x00 29. "ADCPSC_3,Bit 3 of ADCPSC" "0,1"
bitfld.long 0x00 28. "PLL2MF_5,Bit 5 of PLL2MF" "0,1"
newline
bitfld.long 0x00 19. "SHRTIMERSEL,SHRTIMER Clock Source Selection" "0,1"
bitfld.long 0x00 18. "I2S2SEL,I2S2 Clock Source Selection" "0,1"
bitfld.long 0x00 17. "I2S1SEL,I2S1 Clock Source Selection" "0,1"
bitfld.long 0x00 16. "PREDV0SEL,PREDV0 input Clock Source Selection" "0,1"
newline
bitfld.long 0x00 12.--15. "PLL2MF,The PLL2 clock multiplication factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "PLL1MF,The PLL1 clock multiplication factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "PREDV1,PREDV1 division factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "PREDV0,PREDV0 division factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2C++0x03
line.long 0x00 "CFG1,Clock Configuration register 1"
bitfld.long 0x00 30. "PLLPRESEL,PLL Clock Source Selection" "0,1"
bitfld.long 0x00 29. "ADCPSC_3,Bit 3 of ADCPSC" "0,1"
group.long 0x34++0x03
line.long 0x00 "DSV,Deep sleep mode Voltage register"
bitfld.long 0x00 0.--2. "DSLPVS,Deep-sleep mode voltage select" "0,1,2,3,4,5,6,7"
group.long 0xC0++0x03
line.long 0x00 "ADDCTL,Additional clock control register"
hexmask.long.byte 0x00 24.--31. 1. "IRC48MCALIB,Internal 48MHz RC oscillator calibration value register"
rbitfld.long 0x00 17. "IRC48MSTB,Internal 48MHz RC oscillator clock stabilization Flag" "0,1"
bitfld.long 0x00 16. "IRC48MEN,Internal 48MHz RC oscillator enable" "0,1"
bitfld.long 0x00 0.--1. "CK48MSEL,48MHz clock selection" "0,1,2,3"
group.long 0xC0++0x03
line.long 0x00 "ADDCTL,Additional clock control register"
hexmask.long.byte 0x00 24.--31. 1. "IRC48MCALIB,Internal 48MHz RC oscillator calibration value register"
rbitfld.long 0x00 17. "IRC48MSTB,Internal 48MHz RC oscillator clock stabilization Flag" "0,1"
bitfld.long 0x00 16. "IRC48MEN,Internal 48MHz RC oscillator enable" "0,1"
bitfld.long 0x00 15. "PLLUSBSTB,PLLUSB clock stabilization flag" "0,1"
newline
bitfld.long 0x00 14. "PLLUSBEN,PLLUSB enable" "0,1"
bitfld.long 0x00 6. "USBSWEN,USB clock source selection enable" "0,1"
bitfld.long 0x00 3.--5. "USBHSDV,USBHS clock selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. "USBHSSEL,USBHS clock divider factor" "0,1"
newline
bitfld.long 0x00 0.--1. "CK48MSEL,48MHz clock selection" "0,1,2,3"
group.long 0xC4++0x03
line.long 0x00 "ADDCFG,Additional clock configuration register"
hexmask.long.byte 0x00 18.--24. 1. "PLLUSBMF,The PLLUSB clock multiplication factor"
bitfld.long 0x00 17. "PLLUSBPREDVSEL,PLLUSBPREDV input Clock Source Selection" "0,1"
bitfld.long 0x00 16. "PLLUSBPRESEL,PLLUSB clock source preselection" "0,1"
bitfld.long 0x00 0.--3. "PLLUSBPREDV,PLLUSBPREDV division factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xCC++0x03
line.long 0x00 "ADDINT,Additional clock interrupt register"
bitfld.long 0x00 23. "PLLUSBSTBIC,PLLUSB stabilization interrupt clear" "0,1"
bitfld.long 0x00 22. "IRC48MSTBIC,Internal 48 MHz RC oscillator Stabilization Interrupt Clear" "0,1"
bitfld.long 0x00 15. "PLLUSBSTBIE,PLLUSB stabilization interrupt enable" "0,1"
bitfld.long 0x00 14. "IRC48MSTBIE,Internal 48 MHz RC oscillator Stabilization Interrupt Enable" "0,1"
newline
rbitfld.long 0x00 7. "PLLUSBSTBIF,PLLUSB stabilization interrupt flag" "0,1"
rbitfld.long 0x00 6. "IRC48MSTBIF,IRC48M stabilization interrupt flag" "0,1"
group.long 0xCC++0x03
line.long 0x00 "ADDINT,Additional clock interrupt register"
bitfld.long 0x00 22. "IRC48MSTBIC,Internal 48 MHz RC oscillator Stabilization Interrupt Clear" "0,1"
bitfld.long 0x00 14. "IRC48MSTBIE,Internal 48 MHz RC oscillator Stabilization Interrupt Enable" "0,1"
rbitfld.long 0x00 7. "PLLUSBSTBIF,PLLUSB stabilization interrupt flag" "0,1"
rbitfld.long 0x00 6. "IRC48MSTBIF,IRC48M stabilization interrupt flag" "0,1"
group.long 0xD0++0x03
line.long 0x00 "PLLSSCTL,PLL clock spread spectrum control register"
bitfld.long 0x00 31. "SSCGON,PLL spread spectrum modulation enable" "0,1"
bitfld.long 0x00 30. "SS_TYPE,PLL spread spectrum modulation type select" "0,1"
hexmask.long.word 0x00 13.--27. 1. "MODSTEP,Configure PLL spread spectrum modulation profile amplitude and frequency"
hexmask.long.word 0x00 0.--12. 1. "MODCNT,Configure PLL spread spectrum modulation profile amplitude and frequency"
group.long 0xD4++0x03
line.long 0x00 "CFG2,Clock configuration register 2"
bitfld.long 0x00 4.--5. "I2C2SEL,I2C2 Clock Source Selection" "0,1,2,3"
bitfld.long 0x00 0.--1. "USART5SEL,USART5 Clock Source Selection" "0,1,2,3"
group.long 0xE0++0x03
line.long 0x00 "ADDAPB1RST,APB1 additional reset register"
bitfld.long 0x00 27. "CTCRST,CTC reset" "0,1"
group.long 0xE4++0x03
line.long 0x00 "ADDAPB1EN,APB1 additional enable register"
bitfld.long 0x00 27. "CTCEN,CTC clock enable" "0,1"
tree.end
tree "RTC (Real-time Counter)"
base ad:0x40002800
group.long 0x00++0x03
line.long 0x00 "INTEN,RTC interrupt enable register"
bitfld.long 0x00 2. "OVIE,Overflow interrupt enable" "0,1"
bitfld.long 0x00 1. "ALRMIE,Alarm interrupt enable" "0,1"
bitfld.long 0x00 0. "SCIE,Second interrupt" "0,1"
group.long 0x04++0x03
line.long 0x00 "CTL,control register"
rbitfld.long 0x00 5. "LWOFF,Last write operation finished flag" "0,1"
bitfld.long 0x00 4. "CMF,Configuration mode flag" "0,1"
bitfld.long 0x00 3. "RSYNF,Registers synchronized flag" "0,1"
bitfld.long 0x00 2. "OVIF,Overflow interrupt flag" "0,1"
newline
bitfld.long 0x00 1. "ALRMIF,Alarm interrupt flag" "0,1"
bitfld.long 0x00 0. "SCIF,Sencond interrupt flag" "0,1"
group.long 0x08++0x03
line.long 0x00 "PSCH,RTC prescaler high register"
bitfld.long 0x00 0.--3. "PSC,RTC prescaler value high" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x0C++0x03
line.long 0x00 "PSCL,RTC prescaler low register"
hexmask.long.word 0x00 0.--15. 1. "PSC,RTC prescaler value low"
group.long 0x10++0x03
line.long 0x00 "DIVH,RTC divider high register"
bitfld.long 0x00 0.--3. "DIV,RTC divider value high" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x14++0x03
line.long 0x00 "DIVL,RTC divider low register"
hexmask.long.word 0x00 0.--15. 1. "DIV,RTC divider value low"
group.long 0x18++0x03
line.long 0x00 "CNTH,RTC counter high register"
hexmask.long.word 0x00 0.--15. 1. "CNT,RTC counter value high"
group.long 0x1C++0x03
line.long 0x00 "CNTL,RTC counter low register"
hexmask.long.word 0x00 0.--15. 1. "CNT,RTC conuter value low"
group.long 0x20++0x03
line.long 0x00 "ALRMH,Alarm high register"
hexmask.long.word 0x00 0.--15. 1. "ALRM,Alarm value high"
group.long 0x24++0x03
line.long 0x00 "ALRML,RTC alarm low register"
hexmask.long.word 0x00 0.--15. 1. "ALRM,alarm value low"
tree.end
sif cpuis("GD32E50*HD")
tree "SDIO (Secure digital input/output interface)"
base ad:0x40018000
group.long 0x00++0x03
line.long 0x00 "PWRCTL,Power control register"
bitfld.long 0x00 0.--1. "PWRCTL,SDIO power control bits" "0,1,2,3"
group.long 0x04++0x03
line.long 0x00 "CLKCTL,Clock control register"
bitfld.long 0x00 31. "DIV_8,MSB of Clock division" "0,1"
bitfld.long 0x00 14. "HWCLKEN,Hardware Clock Control enable bit" "0,1"
bitfld.long 0x00 13. "CLKEDGE,SDIO_CLK clock edge selection bit" "0,1"
bitfld.long 0x00 11.--12. "BUSMODE,SDIO card bus mode control bit" "0,1,2,3"
newline
bitfld.long 0x00 10. "CLKBYP,Clock bypass enable bit" "0,1"
bitfld.long 0x00 9. "CLKPWRSAV,SDIO_CLK clock dynamic switch on/off for power saving" "0,1"
bitfld.long 0x00 8. "CLKEN,SDIO_CLK clock output enable bit" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "DIV_0_7,Clock division"
group.long 0x08++0x03
line.long 0x00 "CMDAGMT,Command argument register"
hexmask.long 0x00 0.--31. 1. "CMDAGMT,SDIO card command argument"
group.long 0x0C++0x03
line.long 0x00 "CMDCTL,Command control register"
bitfld.long 0x00 14. "ATAEN,CE-ATA command enable(CE-ATA only)" "0,1"
bitfld.long 0x00 13. "NINTEN,No CE-ATA Interrupt (CE-ATA only)" "0,1"
bitfld.long 0x00 12. "ENCMDC,CMD completion signal enabled (CE-ATA only)" "0,1"
bitfld.long 0x00 11. "SUSPEND,SD I/O suspend command(SD I/O only)" "0,1"
newline
bitfld.long 0x00 10. "CSMEN,Command state machine (CSM) enable bit" "0,1"
bitfld.long 0x00 9. "WAITDEND,Waits for ends of data transfer" "0,1"
bitfld.long 0x00 8. "INTWAIT,Interrupt wait instead of timeout" "0,1"
bitfld.long 0x00 6.--7. "CMDRESP,Command response type bits" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "CMDIDX,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x10++0x03
line.long 0x00 "RSPCMDIDX,Command index response register"
bitfld.long 0x00 0.--5. "RSPCMDIDX,Last response command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x14++0x03
line.long 0x00 "RESP0,Response register 0"
hexmask.long 0x00 0.--31. 1. "RESP0,Card state"
rgroup.long 0x18++0x03
line.long 0x00 "RESP1,Response register 1"
hexmask.long 0x00 0.--31. 1. "RESP1,Card state"
rgroup.long 0x1C++0x03
line.long 0x00 "RESP2,Response register 2"
hexmask.long 0x00 0.--31. 1. "RESP2,Card state"
rgroup.long 0x20++0x03
line.long 0x00 "RESP3,Response register 3"
hexmask.long 0x00 0.--31. 1. "RESP3,Response register 3"
group.long 0x24++0x03
line.long 0x00 "DATATO,Data timeout register"
hexmask.long 0x00 0.--31. 1. "DATATO,Data timeout period"
group.long 0x28++0x03
line.long 0x00 "DATALEN,Data length register"
hexmask.long 0x00 0.--24. 1. "DATALEN,Data transfer length"
group.long 0x2C++0x03
line.long 0x00 "DATACTL,Data control register"
bitfld.long 0x00 11. "IOEN,SD I/O specific function enable" "0,1"
bitfld.long 0x00 10. "RWTYPE,Read wait type" "0,1"
bitfld.long 0x00 9. "RWSTOP,Read wait stop" "0,1"
bitfld.long 0x00 8. "RWEN,Read wait mode enabled" "0,1"
newline
bitfld.long 0x00 4.--7. "BLKSZ,Data block size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "DMAEN,DMA enable bit" "0,1"
bitfld.long 0x00 2. "TRANSMOD,Data transfer mode" "0,1"
bitfld.long 0x00 1. "DATADIR,Data transfer direction" "0,1"
newline
bitfld.long 0x00 0. "DATAEN,Data transfer enabled bit" "0,1"
rgroup.long 0x30++0x03
line.long 0x00 "DATACNT,Data counter register"
hexmask.long 0x00 0.--24. 1. "DATACNT,Data count value"
rgroup.long 0x34++0x03
line.long 0x00 "STAT,Status register"
bitfld.long 0x00 23. "ATAEND,CE-ATA command completion signal received" "0,1"
bitfld.long 0x00 22. "SDIOINT,SD I/O interrupt received" "0,1"
bitfld.long 0x00 21. "RXDTVAL,Data is valid in receive FIFO" "0,1"
bitfld.long 0x00 20. "TXDTVAL,Data is valid in transmit FIFO" "0,1"
newline
bitfld.long 0x00 19. "RFE,Receive FIFO is empty" "0,1"
bitfld.long 0x00 18. "TFE,Transmit FIFO is empty" "0,1"
bitfld.long 0x00 17. "RFF,Receive FIFO is full" "0,1"
bitfld.long 0x00 16. "TFF,Transmit FIFO is full" "0,1"
newline
bitfld.long 0x00 15. "RFH,Receive FIFO is half full" "0,1"
bitfld.long 0x00 14. "TFH,Transmit FIFO is half empty" "0,1"
bitfld.long 0x00 13. "RXRUN,Data reception in progress" "0,1"
bitfld.long 0x00 12. "TXRUN,Data transmission in progress" "0,1"
newline
bitfld.long 0x00 11. "CMDRUN,Command transmission in progress" "0,1"
bitfld.long 0x00 10. "DTBLKEND,Data block sent/received" "0,1"
bitfld.long 0x00 9. "STBITE,Start bit error in the bus" "0,1"
bitfld.long 0x00 8. "DTEND,Data end" "0,1"
newline
bitfld.long 0x00 7. "CMDSEND,Command sent" "0,1"
bitfld.long 0x00 6. "CMDRECV,Command response received" "0,1"
bitfld.long 0x00 5. "RXORE,Received FIFO overrun error occurs" "0,1"
bitfld.long 0x00 4. "TXURE,Transmit FIFO underrun error occurs" "0,1"
newline
bitfld.long 0x00 3. "DTTMOUT,Data timeout" "0,1"
bitfld.long 0x00 2. "CMDTMOUT,Command response timeout" "0,1"
bitfld.long 0x00 1. "DTCRCERR,Data block sent/received" "0,1"
bitfld.long 0x00 0. "CCRCERR,Command response received" "0,1"
wgroup.long 0x38++0x03
line.long 0x00 "INTC,Interrupt clear register"
bitfld.long 0x00 23. "ATAENDC,ATAEND flag clear bit" "0,1"
bitfld.long 0x00 22. "SDIOINTC,SDIOINT flag clear bit" "0,1"
bitfld.long 0x00 10. "DTBLKENDC,DTBLKEND flag clear bit" "0,1"
bitfld.long 0x00 9. "STBITEC,STBITE flag clear bit" "0,1"
newline
bitfld.long 0x00 8. "DTENDC,DTEND flag clear bit" "0,1"
bitfld.long 0x00 7. "CMDSENDC,CMDSEND flag clear bit" "0,1"
bitfld.long 0x00 6. "CMDRECVC,CMDRECV flag clear bit" "0,1"
bitfld.long 0x00 5. "RXOREC,RXORE flag clear bit" "0,1"
newline
bitfld.long 0x00 4. "TXUREC,TXURE flag clear bit" "0,1"
bitfld.long 0x00 3. "DTTMOUTC,DTTMOUT flag clear bit" "0,1"
bitfld.long 0x00 2. "CMDTMOUTC,CMDTMOUT flag clear bit" "0,1"
bitfld.long 0x00 1. "DTCRCERRC,DTCRCERR flag clear bit" "0,1"
newline
bitfld.long 0x00 0. "CCRCERRC,CCRCERR flag clear bit" "0,1"
group.long 0x3C++0x03
line.long 0x00 "INTEN,Interrupt enable register"
bitfld.long 0x00 23. "ATAENDIE,CE-ATA command completion signal received interrupt enable" "0,1"
bitfld.long 0x00 22. "SDIOINTIE,SD I/O interrupt received interrupt enable" "0,1"
bitfld.long 0x00 21. "RXDTVALIE,Data valid in receive FIFO interrupt enable" "0,1"
bitfld.long 0x00 20. "TXDTVALIE,Data valid in transmit FIFO interrupt enable" "0,1"
newline
bitfld.long 0x00 19. "RFEIE,Receive FIFO empty interrupt enable" "0,1"
bitfld.long 0x00 18. "TFEIE,Transmit FIFO empty interrupt enable" "0,1"
bitfld.long 0x00 17. "RFFIE,Receive FIFO full interrupt enable" "0,1"
bitfld.long 0x00 16. "TFFIE,Transmit FIFO full interrupt enable" "0,1"
newline
bitfld.long 0x00 15. "RFHIE,Receive FIFO half full interrupt enable" "0,1"
bitfld.long 0x00 14. "TFHIE,Transmit FIFO half empty interrupt enable" "0,1"
bitfld.long 0x00 13. "RXRUNIE,Data reception interrupt enable" "0,1"
bitfld.long 0x00 12. "TXRUNIE,Data transmission interrupt enable" "0,1"
newline
bitfld.long 0x00 11. "CMDRUNIE,Command transmission interrupt enable" "0,1"
bitfld.long 0x00 10. "DTBLKENDIE,Data block end interrupt enable" "0,1"
bitfld.long 0x00 9. "STBITEIE,Start bit error interrupt enable" "0,1"
bitfld.long 0x00 8. "DTENDIE,Data end interrupt enable" "0,1"
newline
bitfld.long 0x00 7. "CMDSENDIE,Command sent interrupt enable" "0,1"
bitfld.long 0x00 6. "CMDRECVIE,Command response received interrupt enable" "0,1"
bitfld.long 0x00 5. "RXOREIE,Received FIFO overrun error interrupt enable" "0,1"
bitfld.long 0x00 4. "TXUREIE,Transmit FIFO underrun error interrupt enable" "0,1"
newline
bitfld.long 0x00 3. "DTTMOUTIE,Data timeout interrupt enable" "0,1"
bitfld.long 0x00 2. "CMDTMOUTIE,Command response timeout interrupt enable" "0,1"
bitfld.long 0x00 1. "DTCRCERRIE,Data CRC fail interrupt enable" "0,1"
bitfld.long 0x00 0. "CCRCERRIE,Command response CRC fail interrupt enable" "0,1"
rgroup.long 0x48++0x03
line.long 0x00 "FIFOCNT,FIFO counter register"
hexmask.long.tbyte 0x00 0.--23. 1. "FIFOCNT,FIFO counter"
group.long 0x80++0x03
line.long 0x00 "FIFO,FIFO data register"
hexmask.long 0x00 0.--31. 1. "FIFODT,Receive FIFO data or transmit FIFO data"
tree.end
endif
tree "SHRTIMER (SHRTIMER Master TIMER)"
tree "MASTER_TIMER"
base ad:0x40017400
group.long 0x00++0x03
line.long 0x00 "MTCTL0,SHRTIMER Master_TIMER control register 0"
bitfld.long 0x00 30.--31. "UPSEL,Update event selection" "0,1,2,3"
bitfld.long 0x00 29. "UPREP,Update event generated by repetition event" "0,1"
bitfld.long 0x00 27. "SHWEN,Shadow registers enable" "0,1"
bitfld.long 0x00 25.--26. "DACTRGS,Trigger source to DAC" "0,1,2,3"
newline
bitfld.long 0x00 21. "ST4CEN,The counter of Slave_TIMER4 enable" "0,1"
bitfld.long 0x00 20. "ST3CEN,The counter of Slave_TIMER3 enable" "0,1"
bitfld.long 0x00 19. "ST2CEN,The counter of Slave_TIMER2 enable" "0,1"
bitfld.long 0x00 18. "ST1CEN,The counter of Slave_TIMER1 enable" "0,1"
newline
bitfld.long 0x00 17. "ST0CEN,The counter of Slave_TIMER0 enable" "0,1"
bitfld.long 0x00 16. "MTCEN,The counter of Master_TIMER enable" "0,1"
bitfld.long 0x00 14.--15. "SYNOSRC,Synchronization output source" "0,1,2,3"
bitfld.long 0x00 12.--13. "SYNOPLS,Synchronization output pulse" "0,1,2,3"
newline
bitfld.long 0x00 11. "SYNISTRT,Synchronization input start counter" "0,1"
bitfld.long 0x00 10. "SYNIRST,Synchronization input reset counter" "0,1"
bitfld.long 0x00 8.--9. "SYNISRC,Synchronization input source" "0,1,2,3"
bitfld.long 0x00 5. "HALFM,Half mode" "0,1"
newline
bitfld.long 0x00 4. "CNTRSTM,Counter reset mode" "0,1"
bitfld.long 0x00 3. "CTNM,Continuous mode" "0,1"
bitfld.long 0x00 0.--1. "CNTCKDIV,Counter clock division" "0,1,2,3"
rgroup.long 0x04++0x03
line.long 0x00 "MTINTF,SHRTIMER Master_TIMER interrupt flag register"
bitfld.long 0x00 6. "UPIF,Update interrupt flag" "0,1"
bitfld.long 0x00 5. "SYNIIF,Synchronization input interrupt flag" "0,1"
bitfld.long 0x00 4. "REPIF,Repetition interrupt flag" "0,1"
bitfld.long 0x00 3. "CMP3IF,Compare 3 interrupt flag" "0,1"
newline
bitfld.long 0x00 2. "CMP2IF,Compare 2 interrupt flag" "0,1"
bitfld.long 0x00 1. "CMP1IF,Compare 1 interrupt flag" "0,1"
bitfld.long 0x00 0. "CMP0IF,Compare 0 interrupt flag" "0,1"
wgroup.long 0x08++0x03
line.long 0x00 "MTINTC,SHRTIMER Master_TIMER interrupt flag clear register"
bitfld.long 0x00 6. "UPIFC,Clear update interrupt flag" "0,1"
bitfld.long 0x00 5. "SYNIIFC,Clear synchronization input interrupt flag" "0,1"
bitfld.long 0x00 4. "REPIFC,Clear repetition interrupt flag" "0,1"
bitfld.long 0x00 3. "CMP3IFC,Clear compare 3 interrupt flag" "0,1"
newline
bitfld.long 0x00 2. "CMP2IFC,Clear compare 2 interrupt flag" "0,1"
bitfld.long 0x00 1. "CMP1IFC,Clear compare 1 interrupt flag" "0,1"
bitfld.long 0x00 0. "CMP0IFC,Clear compare 0 interrupt flag" "0,1"
group.long 0x0C++0x03
line.long 0x00 "MTDMAINTEN,SHRTIMER Master_TIMER DMA and interrupt enable register"
bitfld.long 0x00 22. "UPDEN,Update DMA request enable" "0,1"
bitfld.long 0x00 21. "SYNIDEN,Synchronization input DMA request enable" "0,1"
bitfld.long 0x00 20. "REPDEN,Repetition DMA request enable" "0,1"
bitfld.long 0x00 19. "CMP3DEN,Compare 3 DMA request enable" "0,1"
newline
bitfld.long 0x00 18. "CMP2DEN,Compare 2 DMA request enable" "0,1"
bitfld.long 0x00 17. "CMP1DEN,Compare 1 DMA request enable" "0,1"
bitfld.long 0x00 16. "CMP0DEN,Compare 0 DMA request enable" "0,1"
bitfld.long 0x00 6. "UPIE,Update interrupt enable" "0,1"
newline
bitfld.long 0x00 5. "SYNIIE,Synchronization input interrupt enable" "0,1"
bitfld.long 0x00 4. "REPIE,Repetition interrupt enable" "0,1"
bitfld.long 0x00 3. "CMP3IE,Compare 3 interrupt enable" "0,1"
bitfld.long 0x00 2. "CMP2IE,Compare 2 interrupt enable" "0,1"
newline
bitfld.long 0x00 1. "CMP1IE,Compare 1 interrupt enable" "0,1"
bitfld.long 0x00 0. "CMP0IE,Compare 0 interrupt enable" "0,1"
group.long 0x10++0x03
line.long 0x00 "MTCNT,SHRTIMER Master_TIMER counter register"
hexmask.long.word 0x00 0.--15. 1. "CNT,The current counter value"
group.long 0x14++0x03
line.long 0x00 "MTCAR,SHRTIMER Master_TIMER counter auto reload register"
hexmask.long.word 0x00 0.--15. 1. "CARL,Counter auto reload value"
group.long 0x18++0x03
line.long 0x00 "MTCREP,SHRTIMER Master_TIMER counter repetition register"
hexmask.long.byte 0x00 0.--7. 1. "CREP,Counter repetition value"
group.long 0x1C++0x03
line.long 0x00 "MTCMP0V,SHRTIMER Master_TIMER compare 0 value register"
hexmask.long.word 0x00 0.--15. 1. "CMP0VAL,Compare 0 value"
group.long 0x24++0x03
line.long 0x00 "MTCMP1V,SHRTIMER Master_TIMER compare 1 value register"
hexmask.long.word 0x00 0.--15. 1. "CMP1VAL,Compare 1 value"
group.long 0x28++0x03
line.long 0x00 "MTCMP2V,SHRTIMER Master_TIMER compare 2 value register"
hexmask.long.word 0x00 0.--15. 1. "CMP2VAL,Compare 2 value"
group.long 0x2C++0x03
line.long 0x00 "MTCMP3V,SHRTIMER Master_TIMER compare 3 value register"
hexmask.long.word 0x00 0.--15. 1. "CMP3VAL,Compare 3 value"
group.long 0x7C++0x03
line.long 0x00 "MTACTL,SHRTIMER Master_TIMER additional control register"
bitfld.long 0x00 3. "CNTCKDIV_3,Counter clock division" "0,1"
tree.end
tree "SHRTIMER_COMMON"
base ad:0x40017780
group.long 0x00++0x03
line.long 0x00 "CTL0,SHRTIMER control register 0"
bitfld.long 0x00 25.--27. "ADTG3USRC,SHRTIMER_ADCTRIG3 update source" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 22.--24. "ADTG2USRC,SHRTIMER_ADCTRIG2 update source" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 19.--21. "ADTG1USRC,SHRTIMER_ADCTRIG1 update source" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "ADTG0USRC,SHRTIMER_ADCTRIG0 update source" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 5. "ST4UPDIS,Slave_TIMER4 update disable" "0,1"
bitfld.long 0x00 4. "ST3UPDIS,Slave_TIMER3 update disable" "0,1"
bitfld.long 0x00 3. "ST2UPDIS,Slave_TIMER2 update disable" "0,1"
bitfld.long 0x00 1. "ST0UPDIS,Slave_TIMER0 update disable" "0,1"
newline
bitfld.long 0x00 0. "MTUPDIS,Master_TIMER update disable" "0,1"
group.long 0x04++0x03
line.long 0x00 "CTL1,SHRTIMER control register 1"
bitfld.long 0x00 13. "ST4SRST,Slave_TIMER4 software reset" "0,1"
bitfld.long 0x00 12. "ST3SRST,Slave_TIMER3 software reset" "0,1"
bitfld.long 0x00 11. "ST2SRST,Slave_TIMER2 software reset" "0,1"
bitfld.long 0x00 10. "ST1SRST,Slave_TIMER1 software reset" "0,1"
newline
bitfld.long 0x00 9. "ST0SRST,Slave_TIMER0 software reset" "0,1"
bitfld.long 0x00 8. "MTSRST,Master_TIMER software reset" "0,1"
bitfld.long 0x00 5. "ST4SUP,Slave_TIMER4 software update" "0,1"
bitfld.long 0x00 4. "ST3SUP,Slave_TIMER3 software update" "0,1"
newline
bitfld.long 0x00 3. "ST2SUP,Slave_TIMER2 software update" "0,1"
bitfld.long 0x00 2. "ST1SUP,Slave_TIMER1 software update" "0,1"
bitfld.long 0x00 1. "ST0SUP,Slave_TIMER0 software update" "0,1"
bitfld.long 0x00 0. "MTSUP,Master_TIMER software update" "0,1"
rgroup.long 0x08++0x03
line.long 0x00 "INTF,SHRTIMER interrupt flag register"
bitfld.long 0x00 17. "BMPERIF,Bunch mode period interrupt flag" "0,1"
bitfld.long 0x00 16. "DLLCALIF,DLL calibration completed interrupt flag" "0,1"
bitfld.long 0x00 5. "SYSFLTIF,System fault interrupt flag" "0,1"
bitfld.long 0x00 4. "FLT4IF,Fault 4 interrupt flag" "0,1"
newline
bitfld.long 0x00 3. "FLT3IF,Fault 3 interrupt flag" "0,1"
bitfld.long 0x00 2. "FLT2IF,Fault 2 interrupt flag" "0,1"
bitfld.long 0x00 1. "FLT1IF,Fault 1 interrupt flag" "0,1"
bitfld.long 0x00 0. "FLT0IF,Fault 0 interrupt flag" "0,1"
wgroup.long 0x0C++0x03
line.long 0x00 "INTC,SHRTIMER interrupt flag clear register"
bitfld.long 0x00 17. "BMPERIFC,Clear bunch mode period interrupt flag" "0,1"
bitfld.long 0x00 16. "DLLCALIF,Clear DLL calibration completed interrupt flag" "0,1"
bitfld.long 0x00 5. "SYSFLTIFC,Clear system fault interrupt flag" "0,1"
bitfld.long 0x00 4. "FLT4IFC,Clear fault 4 interrupt flag" "0,1"
newline
bitfld.long 0x00 3. "FLT3IFC,Clear fault 3 interrupt flag" "0,1"
bitfld.long 0x00 2. "FLT2IFC,Clear fault 2 interrupt flag" "0,1"
bitfld.long 0x00 1. "FLT1IF,Fault 1 interrupt flag" "0,1"
bitfld.long 0x00 0. "FLT0IFC,Fault 0 interrupt flag" "0,1"
group.long 0x10++0x03
line.long 0x00 "INTEN,SHRTIMER interrupt enable register"
bitfld.long 0x00 17. "BMPERIE,Bunch mode period interrupt enable" "0,1"
bitfld.long 0x00 16. "DLLCALIE,DLL calibration completed interrupt enable" "0,1"
bitfld.long 0x00 5. "SYSFLTIE,System fault interrupt enable" "0,1"
group.long 0x14++0x03
line.long 0x00 "CHOUTEN,SHRTIMER channel output enable register"
bitfld.long 0x00 9. "ST4CH1EN,Slave_TIMER4 channel 1 output (ST4CH1_O) enable" "0,1"
bitfld.long 0x00 8. "ST4CH0EN,Slave_TIMER4 channel 0 output (ST4CH0_O) enable" "0,1"
bitfld.long 0x00 7. "ST3CH1EN,Slave_TIMER3 channel 1 output (ST3CH1_O) enable" "0,1"
bitfld.long 0x00 6. "ST3CH0EN,Slave_TIMER3 channel 0 output (ST3CH0_O) enable" "0,1"
newline
bitfld.long 0x00 5. "ST2CH1EN,Slave_TIMER2 channel 1 output (ST2CH1_O) enable" "0,1"
bitfld.long 0x00 4. "ST2CH0EN,Slave_TIMER2 channel 0 output (ST2CH0_O) enable" "0,1"
bitfld.long 0x00 3. "ST1CH1EN,Slave_TIMER1 channel 1 output (ST1CH1_O) enable" "0,1"
bitfld.long 0x00 2. "ST1CH0EN,Slave_TIMER1 channel 0 output (ST1CH0_O) enable" "0,1"
newline
bitfld.long 0x00 1. "ST0CH1EN,Slave_TIMER0 channel 1 output (ST0CH1_O) enable" "0,1"
bitfld.long 0x00 0. "ST0CH0EN,Slave_TIMER0 channel 0 output (ST0CH0_O) enable" "0,1"
wgroup.long 0x18++0x03
line.long 0x00 "CHOUTDIS,SHRTIMER channel output disable register"
bitfld.long 0x00 9. "ST4CH1DIS,Slave_TIMER4 channel 1 output (ST4CH1_O) disable" "0,1"
bitfld.long 0x00 8. "ST4CH0DIS,Slave_TIMER4 channel 0 output (ST4CH0_O) disable" "0,1"
bitfld.long 0x00 7. "ST3CH1DIS,Slave_TIMER3 channel 1 output (ST3CH1_O) disable" "0,1"
bitfld.long 0x00 6. "ST3CH0DIS,Slave_TIMER3 channel 0 output (ST3CH0_O) disable" "0,1"
newline
bitfld.long 0x00 5. "ST2CH1DIS,Slave_TIMER2 channel 1 output (ST2CH1_O) disable" "0,1"
bitfld.long 0x00 4. "ST2CH0DIS,Slave_TIMER2 channel 0 output (ST2CH0_O) disable" "0,1"
bitfld.long 0x00 3. "ST1CH1DIS,Slave_TIMER1 channel 1 output (ST1CH1_O) disable" "0,1"
bitfld.long 0x00 2. "ST1CH0DIS,Slave_TIMER1 channel 0 output (ST1CH0_O) disable" "0,1"
newline
bitfld.long 0x00 1. "ST0CH1DIS,Slave_TIMER0 channel 1 output (ST4CH0_O) disable" "0,1"
bitfld.long 0x00 0. "ST0CH0DIS,Slave_TIMER0 channel 0 output (ST0CH0_O) disable" "0,1"
rgroup.long 0x1C++0x03
line.long 0x00 "CHOUTDISF,SHRTIMER channel output disable flag register"
bitfld.long 0x00 9. "ST4CH1DISF,Slave_TIMER4 channel 1 output (ST4CH1_O) disable flag" "0,1"
bitfld.long 0x00 8. "ST4CH0DISF,Slave_TIMER4 channel 0 output (ST4CH0_O) disable flag" "0,1"
bitfld.long 0x00 7. "ST3CH1DISF,Slave_TIMER3 channel 1 output (ST3CH1_O) disable flag" "0,1"
bitfld.long 0x00 6. "ST3CH0DISF,Slave_TIMER3 channel 0 output (ST3CH0_O) disable flag" "0,1"
newline
bitfld.long 0x00 5. "ST2CH1DISF,Slave_TIMER2 channel 1 output (ST2CH1_O) disable flag" "0,1"
bitfld.long 0x00 4. "ST2CH0DISF,Slave_TIMER2 channel 0 output (ST2CH0_O) disable flag" "0,1"
bitfld.long 0x00 3. "ST1CH1DISF,Slave_TIMER1 channel 1 output (ST1CH1_O) disable flag" "0,1"
bitfld.long 0x00 2. "ST1CH0DISF,Slave_TIMER1 channel 0 output (ST1CH0_O) disable flag" "0,1"
newline
bitfld.long 0x00 1. "ST0CH1DISF,Slave_TIMER0 channel 1 output (ST0CH1_O) disable flag" "0,1"
bitfld.long 0x00 0. "ST0CH0DISF,Slave_TIMER0 channel 0 output (ST0CH0_O) disable flag" "0,1"
group.long 0x20++0x03
line.long 0x00 "BMCTL,SHRTIMER bunch mode control register"
bitfld.long 0x00 31. "BMOPTF,Bunch mode operating flag" "0,1"
bitfld.long 0x00 21. "BMST4,Slave_TIMER4 bunch mode" "0,1"
bitfld.long 0x00 20. "BMST3,Slave_TIMER3 bunch mode" "0,1"
bitfld.long 0x00 19. "BMST2,Slave_TIMER2 bunch mode" "0,1"
newline
bitfld.long 0x00 18. "BMST1,Slave_TIMER1 bunch mode" "0,1"
bitfld.long 0x00 17. "BMST0,Slave_TIMER0 bunch mode" "0,1"
bitfld.long 0x00 16. "BMMT,Master_TIMER bunch mode" "0,1"
bitfld.long 0x00 10. "BMSE,Bunch mode shadow enable" "0,1"
newline
bitfld.long 0x00 6.--9. "BMPSC,Bunch mode clock division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 2.--5. "BMCLKS,Bunch mode clock source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. "BMCTN,Continuous mode in bunch mode" "0,1"
bitfld.long 0x00 0. "BMEN,Bunch mode enable" "0,1"
group.long 0x24++0x03
line.long 0x00 "BMSTRG,SHRTIMER bunch mode start trigger register"
bitfld.long 0x00 31. "CISGN,Chip internal signal triggers bunch mode operation" "0,1"
bitfld.long 0x00 30. "EXEV7,External event 7 triggers bunch mode operation" "0,1"
bitfld.long 0x00 29. "EXEV6,External event 6 triggers bunch mode operation" "0,1"
bitfld.long 0x00 28. "ST3EXEV7,Slave_TIMER3 period event following external event 7 triggers bunch mode operation" "0,1"
newline
bitfld.long 0x00 27. "ST0EXEV6,Slave_TIMER0 period event following external event 6 triggers bunch mode operation" "0,1"
bitfld.long 0x00 26. "ST4CMP1,Slave_TIMER4 compare 1 event triggers bunch mode operation" "0,1"
bitfld.long 0x00 25. "ST4CMP0,Slave_TIMER4 compare 0 event triggers bunch mode operation" "0,1"
bitfld.long 0x00 24. "ST4REP,Slave_TIMER4 repetition event triggers bunch mode operation" "0,1"
newline
bitfld.long 0x00 23. "ST4RST,Slave_TIMER4 reset event triggers bunch mode operation" "0,1"
bitfld.long 0x00 22. "ST3CMP1,Slave_TIMER3 compare 1 event triggers bunch mode operation" "0,1"
bitfld.long 0x00 21. "ST3CMP0,Slave_TIMER3 compare 0 event triggers bunch mode operation" "0,1"
bitfld.long 0x00 20. "ST3REP,Slave_TIMER3 repetition event triggers bunch mode operation" "0,1"
newline
bitfld.long 0x00 19. "ST3RST,Slave_TIMER3 reset event triggers bunch mode operation" "0,1"
bitfld.long 0x00 18. "ST2CMP1,Slave_TIMER2 compare 1 event triggers bunch mode operation" "0,1"
bitfld.long 0x00 17. "ST2CMP0,Slave_TIMER2 compare 0 event triggers bunch mode operation" "0,1"
bitfld.long 0x00 16. "ST2REP,Slave_TIMER1 repetition event triggers bunch mode operation" "0,1"
newline
bitfld.long 0x00 15. "ST2RST,Slave_TIMER2 reset event triggers bunch mode operation" "0,1"
bitfld.long 0x00 14. "ST1CMP1,Slave_TIMER1 compare 1 event triggers bunch mode operation" "0,1"
bitfld.long 0x00 13. "ST1CMP0,Slave_TIMER1 compare 0 event triggers bunch mode operation" "0,1"
bitfld.long 0x00 12. "ST1REP,Slave_TIMER1 repetition event triggers bunch mode operation" "0,1"
newline
bitfld.long 0x00 11. "ST1RST,Slave_TIMER1 reset event triggers bunch mode operation" "0,1"
bitfld.long 0x00 10. "ST0CMP1,Slave_TIMER0 compare 1 event triggers bunch mode operation" "0,1"
bitfld.long 0x00 9. "ST0CMP0,Slave_TIMER0 compare 0 event triggers bunch mode operation" "0,1"
bitfld.long 0x00 8. "ST0REP,Slave_TIMER0 repetition event triggers bunch mode operation" "0,1"
newline
bitfld.long 0x00 7. "ST0RST,Slave_TIMER0 reset event triggers bunch mode operation" "0,1"
bitfld.long 0x00 6. "MTCMP3,Master_TIMER compare 3 event triggers bunch mode operation" "0,1"
bitfld.long 0x00 5. "MTCMP2,Master_TIMER compare 2 event triggers bunch mode operation" "0,1"
bitfld.long 0x00 4. "MTCMP1,Master_TIMER compare 1 event triggers bunch mode operation" "0,1"
newline
bitfld.long 0x00 3. "MTCMP0,Master_TIMER compare 0 event triggers bunch mode operation" "0,1"
bitfld.long 0x00 2. "MTREP,Master_TIMER repetition event triggers bunch mode operation" "0,1"
bitfld.long 0x00 1. "MTRST,Master_TIMER reset event triggers bunch mode operation" "0,1"
bitfld.long 0x00 0. "SWTRG,Software triggers bunch mode operation" "0,1"
group.long 0x28++0x03
line.long 0x00 "BMCMPV,SHRTIMER bunch mode compare value register"
hexmask.long.word 0x00 0.--15. 1. "BMCMPVAL,Bunch mode compare value"
group.long 0x2C++0x03
line.long 0x00 "BMCAR,SHRTIMER bunch mode counter auto reload register"
hexmask.long.word 0x00 0.--15. 1. "BMCARL,Bunch mode counter auto reload value"
group.long 0x30++0x03
line.long 0x00 "EXEVCFG0,SHRTIMER external event configuration register 0"
bitfld.long 0x00 27.--28. "EXEV4EG,External event 4 edge sensitivity" "0,1,2,3"
bitfld.long 0x00 26. "EXEV4P,External event 4 polarity" "0,1"
bitfld.long 0x00 24.--25. "EXEV4SRC,External event 4 source" "0,1,2,3"
bitfld.long 0x00 21.--22. "EXEV3EG,External event 3 edge sensitivity" "0,1,2,3"
newline
bitfld.long 0x00 20. "EXEV3P,External event 3 polarity" "0,1"
bitfld.long 0x00 18.--19. "EXEV3SRC,External event 3 source" "0,1,2,3"
bitfld.long 0x00 15.--16. "EXEV2EG,External event 2 edge sensitivity" "0,1,2,3"
bitfld.long 0x00 14. "EXEV2P,External event 2 polarity" "0,1"
newline
bitfld.long 0x00 12.--13. "EXEV2SRC,External event 2 source" "0,1,2,3"
bitfld.long 0x00 9.--10. "EXEV1EG,External event 1 edge sensitivity" "0,1,2,3"
bitfld.long 0x00 8. "EXEV1P,External event 1 polarity" "0,1"
bitfld.long 0x00 6.--7. "EXEV1SRC,External event 1 source" "0,1,2,3"
newline
bitfld.long 0x00 3.--4. "EXEV0EG,External event 0 edge sensitivity" "0,1,2,3"
bitfld.long 0x00 2. "EXEV0P,External event 0 polarity" "0,1"
bitfld.long 0x00 0.--1. "EXEV0SRC,External event 0 source" "0,1,2,3"
group.long 0x34++0x03
line.long 0x00 "EXEVCFG1,SHRTIMER external event configuration register 1"
bitfld.long 0x00 27.--28. "EXEV9EG,External event 9 edge sensitivity" "0,1,2,3"
bitfld.long 0x00 26. "EXEV9P,External event 9 polarity" "0,1"
bitfld.long 0x00 24.--25. "EXEV9SRC,External event 9 source" "0,1,2,3"
bitfld.long 0x00 21.--22. "EXEV8EG,External event 8 edge sensitivity" "0,1,2,3"
newline
bitfld.long 0x00 20. "EXEV8P,External event 8 polarity" "0,1"
bitfld.long 0x00 18.--19. "EXEV8SRC,External event 8 source" "0,1,2,3"
bitfld.long 0x00 15.--16. "EXEV7EG,External event 7 edge sensitivity" "0,1,2,3"
bitfld.long 0x00 14. "EXEV7P,External event 7polarity" "0,1"
newline
bitfld.long 0x00 12.--13. "EXEV7SRC,External event 7 source" "0,1,2,3"
bitfld.long 0x00 9.--10. "EXEV6EG,External event 6 edge sensitivity" "0,1,2,3"
bitfld.long 0x00 8. "EXEV6P,External event 1 polarity" "0,1"
bitfld.long 0x00 6.--7. "EXEV6SRC,External event 1 source" "0,1,2,3"
newline
bitfld.long 0x00 3.--4. "EXEV5EG,External event 0 edge sensitivity" "0,1,2,3"
bitfld.long 0x00 2. "EXEV5P,External event 0 polarity" "0,1"
bitfld.long 0x00 0.--1. "EXEV5SRC,External event 0 source" "0,1,2,3"
group.long 0x38++0x03
line.long 0x00 "EXEVDFCTL,SHRTIMER external event digital filter control register"
bitfld.long 0x00 30.--31. "EXEVFDIV,External event digital filter clock division" "0,1,2,3"
bitfld.long 0x00 24.--27. "EXEV9FC,External event 9 filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 18.--21. "EXEV8FC,External event 8 filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "EXEV7FC,External event 7 filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 6.--9. "EXEV6FC,External event 6 filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "EXEV5FC,External event 5 filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x3C++0x03
line.long 0x00 "ADCTRIGS0,SHRTIMER trigger source 0 to ADC register"
bitfld.long 0x00 31. "TRG0ST4PER,SHRTIMER_ADCTRIG0 on Slave_TIMER4 period event" "0,1"
bitfld.long 0x00 30. "TRG0ST4C3,SHRTIMER_ADCTRIG0 on Slave_TIMER4 compare 3 event" "0,1"
bitfld.long 0x00 29. "TRG0ST4C2,SHRTIMER_ADCTRIG0 on Slave_TIMER4 compare 2 event" "0,1"
bitfld.long 0x00 28. "TRG0ST4C1,SHRTIMER_ADCTRIG0 on Slave_TIMER4 compare 1 event" "0,1"
newline
bitfld.long 0x00 27. "TRG0ST3PER,SHRTIMER_ADCTRIG0 on Slave_TIMER3 period event" "0,1"
bitfld.long 0x00 26. "TRG0ST3C3,SHRTIMER_ADCTRIG0 on Slave_TIMER3 compare 3 event" "0,1"
bitfld.long 0x00 25. "TRG0ST3C2,SHRTIMER_ADCTRIG0 on Slave_TIMER3 compare 2 event" "0,1"
bitfld.long 0x00 24. "TRG0ST3C1,SHRTIMER_ADCTRIG0 on Slave_TIMER3 compare 1 event" "0,1"
newline
bitfld.long 0x00 23. "TRG0ST2PER,SHRTIMER_ADCTRIG0 on Slave_TIMER2 period event" "0,1"
bitfld.long 0x00 22. "TRG0ST2C3,SHRTIMER_ADCTRIG0 on Slave_TIMER2 compare 3 event" "0,1"
bitfld.long 0x00 21. "TRG0ST2C2,SHRTIMER_ADCTRIG0 on Slave_TIMER2 compare 2 event" "0,1"
bitfld.long 0x00 20. "TRG0ST2C1,SHRTIMER_ADCTRIG0 on Slave_TIMER2 compare 1 event" "0,1"
newline
bitfld.long 0x00 19. "TRG0ST1RST,SHRTIMER_ADCTRIG0 on Slave_TIMER1 reset" "0,1"
bitfld.long 0x00 18. "TRG0ST1PER,SHRTIMER_ADCTRIG0 on Slave_TIMER1 period event" "0,1"
bitfld.long 0x00 17. "TRG0ST1C3,SHRTIMER_ADCTRIG0 on Slave_TIMER1 compare 3 event" "0,1"
bitfld.long 0x00 16. "TRG0ST1C2,SHRTIMER_ADCTRIG0 on Slave_TIMER1 compare 2 event" "0,1"
newline
bitfld.long 0x00 15. "TRG0ST1C1,SHRTIMER_ADCTRIG0 on Slave_TIMER1 compare 1 event" "0,1"
bitfld.long 0x00 14. "TRG0ST0RST,SHRTIMER_ADCTRIG0 on Slave_TIMER0 reset" "0,1"
bitfld.long 0x00 13. "TRG0ST0PER,SHRTIMER_ADCTRIG0 on Slave_TIMER0 period event" "0,1"
bitfld.long 0x00 12. "TRG0ST0C3,SHRTIMER_ADCTRIG0 on Slave_TIMER0 compare 3 event" "0,1"
newline
bitfld.long 0x00 11. "TRG0ST0C2,SHRTIMER_ADCTRIG0 on Slave_TIMER0 compare 2 event" "0,1"
bitfld.long 0x00 10. "TRG0ST0C1,SHRTIMER_ADCTRIG0 on Slave_TIMER0 compare 1 event" "0,1"
bitfld.long 0x00 9. "TRG0EXEV4,SHRTIMER_ADCTRIG0 on external event 4" "0,1"
bitfld.long 0x00 8. "TRG0EXEV3,SHRTIMER_ADCTRIG0 on external event 3" "0,1"
newline
bitfld.long 0x00 7. "TRG0EXEV2,SHRTIMER_ADCTRIG0 on external event 2" "0,1"
bitfld.long 0x00 6. "TRG0EXEV1,SHRTIMER_ADCTRIG0 on external event 1" "0,1"
bitfld.long 0x00 5. "TRG0EXEV0,SHRTIMER_ADCTRIG0 on external event 0" "0,1"
bitfld.long 0x00 4. "TRG0MTPER,SHRTIMER_ADCTRIG0 on Master_TIMER period event" "0,1"
newline
bitfld.long 0x00 3. "TRG0MTC3,SHRTIMER_ADCTRIG0 on Master_TIMER compare 3 event" "0,1"
bitfld.long 0x00 2. "TRG0MTC2,SHRTIMER_ADCTRIG0 on Master_TIMER compare 2 event" "0,1"
bitfld.long 0x00 1. "TRG0MTC1,SHRTIMER_ADCTRIG0 on Master_TIMER compare 1 event" "0,1"
bitfld.long 0x00 0. "TRG0MTC0,SHRTIMER_ADCTRIG0 on Master_TIMER compare 0 event" "0,1"
group.long 0x40++0x03
line.long 0x00 "ADCTRIGS1,SHRTIMER trigger source 1 to ADC register"
bitfld.long 0x00 31. "TRG1ST4RST,SHRTIMER_ADCTRIG1 on Slave_TIMER4 reset" "0,1"
bitfld.long 0x00 30. "TRG1ST4C3,SHRTIMER_ADCTRIG1 on Slave_TIMER4 compare 3 event" "0,1"
bitfld.long 0x00 29. "TRG1ST4C2,SHRTIMER_ADCTRIG1 on Slave_TIMER4 compare 2 event" "0,1"
bitfld.long 0x00 28. "TRG1ST4C1,SHRTIMER_ADCTRIG1 on Slave_TIMER4 compare 1 event" "0,1"
newline
bitfld.long 0x00 27. "TRG1ST3RST,SHRTIMER_ADCTRIG1 on Slave_TIMER3 reset" "0,1"
bitfld.long 0x00 26. "TRG1ST3PER,SHRTIMER_ADCTRIG1 on Slave_TIMER3 period event" "0,1"
bitfld.long 0x00 25. "TRG1ST3C3,SHRTIMER_ADCTRIG1 on Slave_TIMER3 compare 3 event" "0,1"
bitfld.long 0x00 24. "TRG1ST3C2,SHRTIMER_ADCTRIG1 on Slave_TIMER3 compare 2 event" "0,1"
newline
bitfld.long 0x00 23. "TRG1ST3C1,SHRTIMER_ADCTRIG1 on Slave_TIMER3 compare 1 event" "0,1"
bitfld.long 0x00 22. "TRG1ST2RST,SHRTIMER_ADCTRIG1 on Slave_TIMER2 reset" "0,1"
bitfld.long 0x00 21. "TRG1ST2PER,SHRTIMER_ADCTRIG1 on Slave_TIMER2 period event" "0,1"
bitfld.long 0x00 20. "TRG1ST2C3,SHRTIMER_ADCTRIG1 on Slave_TIMER2 compare 3 event" "0,1"
newline
bitfld.long 0x00 19. "TRG1ST2C2,SHRTIMER_ADCTRIG1 on Slave_TIMER2 compare 2 event" "0,1"
bitfld.long 0x00 18. "TRG1ST2C1,SHRTIMER_ADCTRIG1 on Slave_TIMER2 compare 1 event" "0,1"
bitfld.long 0x00 17. "TRG1ST1PER,SHRTIMER_ADCTRIG1 on Slave_TIMER1 period event" "0,1"
bitfld.long 0x00 16. "TRG1ST1C3,SHRTIMER_ADCTRIG1 on Slave_TIMER1 compare 3 event" "0,1"
newline
bitfld.long 0x00 15. "TRG1ST1C2,SHRTIMER_ADCTRIG1 on Slave_TIMER1 compare 2 event" "0,1"
bitfld.long 0x00 14. "TRG1ST1C1,SHRTIMER_ADCTRIG1 on Slave_TIMER1 compare 1 event" "0,1"
bitfld.long 0x00 13. "TRG1ST0PER,SHRTIMER_ADCTRIG1 on Slave_TIMER0 period event" "0,1"
bitfld.long 0x00 12. "TRG1ST0C3,SHRTIMER_ADCTRIG1 on Slave_TIMER0 compare 3 event" "0,1"
newline
bitfld.long 0x00 11. "TRG1ST0C2,SHRTIMER_ADCTRIG1 on Slave_TIMER0 compare 2 event" "0,1"
bitfld.long 0x00 10. "TRG1ST0C1,SHRTIMER_ADCTRIG1 on Slave_TIMER0 compare 1 event" "0,1"
bitfld.long 0x00 9. "TRG1EXEV9,SHRTIMER_ADCTRIG1 on external event 9" "0,1"
bitfld.long 0x00 8. "TRG1EXEV8,SHRTIMER_ADCTRIG1 on external event 8" "0,1"
newline
bitfld.long 0x00 7. "TRG1EXEV7,SHRTIMER_ADCTRIG1 on external event 7" "0,1"
bitfld.long 0x00 6. "TRG1EXEV6,SHRTIMER_ADCTRIG1 on external event 6" "0,1"
bitfld.long 0x00 5. "TRG1EXEV5,SHRTIMER_ADCTRIG1 on external event 5" "0,1"
bitfld.long 0x00 4. "TRG1MTPER,SHRTIMER_ADCTRIG1 on Master_TIMER period event" "0,1"
newline
bitfld.long 0x00 3. "TRG1MTC3,SHRTIMER_ADCTRIG1 on Master_TIMER compare 3 event" "0,1"
bitfld.long 0x00 2. "TRG1MTC2,SHRTIMER_ADCTRIG1 on Master_TIMER compare 2 event" "0,1"
bitfld.long 0x00 1. "TRG1MTC1,SHRTIMER_ADCTRIG1 on Master_TIMER compare 1 event" "0,1"
bitfld.long 0x00 0. "TRG1MTC0,SHRTIMER_ADCTRIG1 on Master_TIMER compare 0 event" "0,1"
group.long 0x44++0x03
line.long 0x00 "ADCTRIGS2,SHRTIMER trigger source 2 to ADC register"
bitfld.long 0x00 31. "TRG2ST4PER,SHRTIMER_ADCTRIG2 on Slave_TIMER4 period event" "0,1"
bitfld.long 0x00 30. "TRG2ST4C3,SHRTIMER_ADCTRIG2 on Slave_TIMER4 compare 3 event" "0,1"
bitfld.long 0x00 29. "TRG2ST4C2,SHRTIMER_ADCTRIG2 on Slave_TIMER4 compare 2 event" "0,1"
bitfld.long 0x00 28. "TRG2ST4C1,SHRTIMER_ADCTRIG2 on Slave_TIMER4 compare 1 event" "0,1"
newline
bitfld.long 0x00 27. "TRG2ST3PER,SHRTIMER_ADCTRIG2 on Slave_TIMER3 period event" "0,1"
bitfld.long 0x00 26. "TRG2ST3C3,SHRTIMER_ADCTRIG2 on Slave_TIMER3 compare 3 event" "0,1"
bitfld.long 0x00 25. "TRG2ST3C2,SHRTIMER_ADCTRIG2 on Slave_TIMER3 compare 2 event" "0,1"
bitfld.long 0x00 24. "TRG2ST3C1,SHRTIMER_ADCTRIG2 on Slave_TIMER3 compare 1 event" "0,1"
newline
bitfld.long 0x00 23. "TRG2ST2PER,SHRTIMER_ADCTRIG2 on Slave_TIMER2 period event" "0,1"
bitfld.long 0x00 22. "TRG2ST2C3,SHRTIMER_ADCTRIG2 on Slave_TIMER2 compare 3 event" "0,1"
bitfld.long 0x00 21. "TRG2ST2C2,SHRTIMER_ADCTRIG2 on Slave_TIMER2 compare 2 event" "0,1"
bitfld.long 0x00 20. "TRG2ST2C1,SHRTIMER_ADCTRIG2 on Slave_TIMER2 compare 1 event" "0,1"
newline
bitfld.long 0x00 19. "TRG2ST1RST,SHRTIMER_ADCTRIG2 on Slave_TIMER1 reset" "0,1"
bitfld.long 0x00 18. "TRG2ST1PER,SHRTIMER_ADCTRIG2 on Slave_TIMER1 period event" "0,1"
bitfld.long 0x00 17. "TRG2ST1C3,SHRTIMER_ADCTRIG2 on Slave_TIMER1 compare 3 event" "0,1"
bitfld.long 0x00 16. "TRG2ST1C2,SHRTIMER_ADCTRIG2 on Slave_TIMER1 compare 2 event" "0,1"
newline
bitfld.long 0x00 15. "TRG2ST1C1,SHRTIMER_ADCTRIG2 on Slave_TIMER1 compare 1 event" "0,1"
bitfld.long 0x00 14. "TRG2ST0RST,SHRTIMER_ADCTRIG2 on Slave_TIMER0 reset" "0,1"
bitfld.long 0x00 13. "TRG2ST0PER,SHRTIMER_ADCTRIG2 on Slave_TIMER0 period event" "0,1"
bitfld.long 0x00 12. "TRG2ST0C3,SHRTIMER_ADCTRIG2 on Slave_TIMER0 compare 3 event" "0,1"
newline
bitfld.long 0x00 11. "TRG2ST0C2,SHRTIMER_ADCTRIG2 on Slave_TIMER0 compare 2 event" "0,1"
bitfld.long 0x00 10. "TRG2ST0C1,SHRTIMER_ADCTRIG2 on Slave_TIMER0 compare 1 event" "0,1"
bitfld.long 0x00 9. "TRG2EXEV4,SHRTIMER_ADCTRIG2 on external event 4" "0,1"
bitfld.long 0x00 8. "TRG2EXEV3,SHRTIMER_ADCTRIG2 on external event 3" "0,1"
newline
bitfld.long 0x00 7. "TRG2EXEV2,SHRTIMER_ADCTRIG2 on external event 2" "0,1"
bitfld.long 0x00 6. "TRG2EXEV1,SHRTIMER_ADCTRIG2 on external event 1" "0,1"
bitfld.long 0x00 5. "TRG2EXEV0,SHRTIMER_ADCTRIG2 on external event 0" "0,1"
bitfld.long 0x00 4. "TRG2MTPER,SHRTIMER_ADCTRIG2 on Master_TIMER period event" "0,1"
newline
bitfld.long 0x00 3. "TRG2MTC3,SHRTIMER_ADCTRIG2 on Master_TIMER compare 3 event" "0,1"
bitfld.long 0x00 2. "TRG2MTC2,SHRTIMER_ADCTRIG2 on Master_TIMER compare 2 event" "0,1"
bitfld.long 0x00 1. "TRG2MTC1,SHRTIMER_ADCTRIG2 on Master_TIMER compare 1 event" "0,1"
bitfld.long 0x00 0. "TRG2MTC0,SHRTIMER_ADCTRIG2 on Master_TIMER compare 0 event" "0,1"
group.long 0x48++0x03
line.long 0x00 "ADCTRIGS3,SHRTIMER trigger source 3 to ADC register"
bitfld.long 0x00 31. "TRG3ST4RST,SHRTIMER_ADCTRIG3 on Slave_TIMER4 reset" "0,1"
bitfld.long 0x00 30. "TRG3ST4C3,SHRTIMER_ADCTRIG3 on Slave_TIMER4 compare 3 event" "0,1"
bitfld.long 0x00 29. "TRG3ST4C2,SHRTIMER_ADCTRIG3 on Slave_TIMER4 compare 2 event" "0,1"
bitfld.long 0x00 28. "TRG3ST4C1,SHRTIMER_ADCTRIG3 on Slave_TIMER4 compare 1 event" "0,1"
newline
bitfld.long 0x00 27. "TRG3ST3RST,SHRTIMER_ADCTRIG3 on Slave_TIMER3 reset" "0,1"
bitfld.long 0x00 26. "TRG3ST3PER,SHRTIMER_ADCTRIG3 on Slave_TIMER3 period event" "0,1"
bitfld.long 0x00 25. "TRG3ST3C3,SHRTIMER_ADCTRIG3 on Slave_TIMER3 compare 3 event" "0,1"
bitfld.long 0x00 24. "TRG3ST3C2,SHRTIMER_ADCTRIG3 on Slave_TIMER3 compare 2 event" "0,1"
newline
bitfld.long 0x00 23. "TRG3ST3C1,SHRTIMER_ADCTRIG3 on Slave_TIMER3 compare 1 event" "0,1"
bitfld.long 0x00 22. "TRG3ST2RST,SHRTIMER_ADCTRIG3 on Slave_TIMER2 reset" "0,1"
bitfld.long 0x00 21. "TRG3ST2PER,SHRTIMER_ADCTRIG3 on Slave_TIMER2 period event" "0,1"
bitfld.long 0x00 20. "TRG3ST2C3,SHRTIMER_ADCTRIG3 on Slave_TIMER2 compare 3 event" "0,1"
newline
bitfld.long 0x00 19. "TRG3ST2C2,SHRTIMER_ADCTRIG3 on Slave_TIMER2 compare 2 event" "0,1"
bitfld.long 0x00 18. "TRG3ST2C1,SHRTIMER_ADCTRIG3 on Slave_TIMER2 compare 1 event" "0,1"
bitfld.long 0x00 17. "TRG1ST3PER,SHRTIMER_ADCTRIG3 on Slave_TIMER1 period event" "0,1"
bitfld.long 0x00 16. "TRG3ST1C3,SHRTIMER_ADCTRIG3 on Slave_TIMER1 compare 3 event" "0,1"
newline
bitfld.long 0x00 15. "TRG3ST1C2,SHRTIMER_ADCTRIG3 on Slave_TIMER1 compare 2 event" "0,1"
bitfld.long 0x00 14. "TRG3ST1C1,SHRTIMER_ADCTRIG3 on Slave_TIMER1 compare 1 event" "0,1"
bitfld.long 0x00 13. "TRG3ST0PER,SHRTIMER_ADCTRIG3 on Slave_TIMER0 period event" "0,1"
bitfld.long 0x00 12. "TRG3ST0C3,SHRTIMER_ADCTRIG3 on Slave_TIMER0 compare 3 event" "0,1"
newline
bitfld.long 0x00 11. "TRG3ST0C2,SHRTIMER_ADCTRIG3 on Slave_TIMER0 compare 2 event" "0,1"
bitfld.long 0x00 10. "TRG3ST0C1,SHRTIMER_ADCTRIG3 on Slave_TIMER0 compare 1 event" "0,1"
bitfld.long 0x00 9. "TRG3EXEV9,SHRTIMER_ADCTRIG3 on external event 9" "0,1"
bitfld.long 0x00 8. "TRG3EXEV8,SHRTIMER_ADCTRIG3 on external event 8" "0,1"
newline
bitfld.long 0x00 7. "TRG3EXEV7,SHRTIMER_ADCTRIG3 on external event 7" "0,1"
bitfld.long 0x00 6. "TRG3EXEV6,SHRTIMER_ADCTRIG3 on external event 6" "0,1"
bitfld.long 0x00 5. "TRG3EXEV5,SHRTIMER_ADCTRIG3 on external event 5" "0,1"
bitfld.long 0x00 4. "TRG3MTPER,SHRTIMER_ADCTRIG3 on Master_TIMER period event" "0,1"
newline
bitfld.long 0x00 3. "TRG3MTC3,SHRTIMER_ADCTRIG3 on Master_TIMER compare 3 event" "0,1"
bitfld.long 0x00 2. "TRG3MTC2,SHRTIMER_ADCTRIG3 on Master_TIMER compare 2 event" "0,1"
bitfld.long 0x00 1. "TRG1MTC3,SHRTIMER_ADCTRIG3 on Master_TIMER compare 1 event" "0,1"
bitfld.long 0x00 0. "TRG3MTC0,SHRTIMER_ADCTRIG3 on Master_TIMER compare 0 event" "0,1"
group.long 0x4C++0x03
line.long 0x00 "DLLCCTL,SHRTIMER DLL calibration control register"
bitfld.long 0x00 2.--3. "CLBPER,DLL calibration period" "0,1,2,3"
bitfld.long 0x00 1. "CLBPEREN,DLL periodic calibration enable" "0,1"
bitfld.long 0x00 0. "CLBSTRT,DLL calibration start once" "0,1"
group.long 0x50++0x03
line.long 0x00 "FLTINCFG0,SHRTIMER fault input configuration register 0"
bitfld.long 0x00 31. "FLT3INPROT,Protect fault 3 input configuration" "0,1"
bitfld.long 0x00 27.--30. "FLT3INFC,Fault 3 input filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 26. "FLT3INSRC,Fault 3 input source" "0,1"
bitfld.long 0x00 25. "FLT3INP,Fault 3 input polarity" "0,1"
newline
bitfld.long 0x00 24. "FLT3INEN,Fault 3 input enable" "0,1"
bitfld.long 0x00 23. "FLT2INPROT,Protect fault 2 input configuration" "0,1"
bitfld.long 0x00 19.--22. "FLT2INFC,Fault 2 input filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 18. "FLT2INSRC,Fault 2 input source" "0,1"
newline
bitfld.long 0x00 17. "FLT2INP,Fault 2 input polarity" "0,1"
bitfld.long 0x00 16. "FLT2INEN,Fault 2 input enable" "0,1"
bitfld.long 0x00 15. "FLT1INPROT,Protect fault 1 input configuration" "0,1"
bitfld.long 0x00 11.--14. "FLT1INFC,Fault 1 input filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10. "FLT1INSRC,Fault 2 input source" "0,1"
bitfld.long 0x00 9. "FLT1INP,Fault 1 input polarity" "0,1"
bitfld.long 0x00 8. "FLT1INEN,Fault 1 input enable" "0,1"
bitfld.long 0x00 7. "FLT0INPROT,Protect fault 0 input configuration" "0,1"
newline
bitfld.long 0x00 3.--6. "FLT0INFC,Fault 0 input filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 2. "FLT0INSRC,Fault 0 input source" "0,1"
bitfld.long 0x00 1. "FLT0INP,Fault 0 input polarity" "0,1"
bitfld.long 0x00 0. "FLT0INEN,Fault 0 input enable" "0,1"
group.long 0x54++0x03
line.long 0x00 "FLTINCFG1,SHRTIMER fault input configuration register 1"
bitfld.long 0x00 24.--25. "FLTFDIV,Fault input digital filter clock division" "0,1,2,3"
bitfld.long 0x00 7. "FLT4INPROT,Protect fault 4 input configuration" "0,1"
bitfld.long 0x00 3.--6. "FLT4INFC,Fault 4 input filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 2. "FLT4INSRC,Fault 4 input source" "0,1"
newline
bitfld.long 0x00 1. "FLT4INP,Fault 4 input polarity" "0,1"
bitfld.long 0x00 0. "FLT4INEN,Fault 4 input enable" "0,1"
group.long 0x58++0x03
line.long 0x00 "DMAUPMTR,SHRTIMER DMA update Master_TIMER register"
bitfld.long 0x00 31. "MTACTL,SHRTIMER_MTACTL update by DMA mode" "0,1"
bitfld.long 0x00 9. "MTCMP3V,SHRTIMER_MTCMP3V update by DMA mode" "0,1"
bitfld.long 0x00 8. "MTCMP2V,SHRTIMER_MTCMP2V update by DMA mode" "0,1"
bitfld.long 0x00 7. "MTCMP1V,SHRTIMER_MTCMP1V update by DMA mode" "0,1"
newline
bitfld.long 0x00 6. "MTCMP0V,SHRTIMER_MTCMP0V update by DMA mode" "0,1"
bitfld.long 0x00 5. "MTCREP,SHRTIMER_MTCAR update by DMA mode" "0,1"
bitfld.long 0x00 4. "MTCAR,SHRTIMER_MTCAR update by DMA mode" "0,1"
bitfld.long 0x00 3. "MTCNT,SHRTIMER_MTCNT update by DMA mode" "0,1"
newline
bitfld.long 0x00 2. "MTDMAINTEN,SHRTIMER_MTDMAINTEN update by DMA mode" "0,1"
bitfld.long 0x00 1. "MTINTC,SHRTIMER_MTINTC update by DMA mode" "0,1"
bitfld.long 0x00 0. "MTCTL0,SHRTIMER_MTCTL0 update by DMA mode" "0,1"
group.long 0x5C++0x03
line.long 0x00 "DMAUPST0R,SHRTIMER DMA update Slave_TIMER0 register"
bitfld.long 0x00 31. "ST0ACTL,SHRTIMER_ST0ACTL update by DMA mode" "0,1"
bitfld.long 0x00 20. "ST0FLTCTL,SHRTIMER_ST0FLTCTL update by DMA mode" "0,1"
bitfld.long 0x00 19. "ST0CHOCTL,SHRTIMER_ST0CHOCTL update by DMA mode" "0,1"
bitfld.long 0x00 18. "ST0CSCTL,SHRTIMER_ST0CSCTL update by DMA mode" "0,1"
newline
bitfld.long 0x00 17. "ST0CNTRST,SHRTIMER_ST0CNTRST update by DMA mode" "0,1"
bitfld.long 0x00 16. "ST0EXEVFCFG1,SHRTIMER_ST0EXEVFCFG1update by DMA mode" "0,1"
bitfld.long 0x00 15. "ST0EXEVFCFG0,SHRTIMER_ST0EXEVFCFG0update by DMA mode" "0,1"
bitfld.long 0x00 14. "ST0CH1RST,SHRTIMER_ST0CH1RST update by DMA mode" "0,1"
newline
bitfld.long 0x00 13. "ST0CH1SET,SHRTIMER_ST0CH1SET update by DMA mode" "0,1"
bitfld.long 0x00 12. "ST0CH0RST,SHRTIMER_ST0CH0RST update by DMA mode" "0,1"
bitfld.long 0x00 11. "ST0CH0SET,SHRTIMER_ST0CH0SET update by DMA mode" "0,1"
bitfld.long 0x00 10. "ST0DTCTL,SHRTIMER_ST0DTCTL update by DMA mode" "0,1"
newline
bitfld.long 0x00 9. "ST0CMP3V,SHRTIMER_ST0CMP3V update by DMA mode" "0,1"
bitfld.long 0x00 8. "ST0CMP2V,SHRTIMER_ST0CMP2V update by DMA mode" "0,1"
bitfld.long 0x00 7. "ST0CMP1V,SHRTIMER_ST0CMP1V update by DMA mode" "0,1"
bitfld.long 0x00 6. "ST0CMP0V,SHRTIMER_ST0CMP0V update by DMA mode" "0,1"
newline
bitfld.long 0x00 5. "ST0CREP,SHRTIMER_ST0CREP update by DMA mode" "0,1"
bitfld.long 0x00 4. "ST0CAR,SHRTIMER_ST0CAR update by DMA mode" "0,1"
bitfld.long 0x00 3. "ST0CNT,SHRTIMER_ST0CNT update by DMA mode" "0,1"
bitfld.long 0x00 2. "ST0DMAINTEN,SHRTIMER_ST0DMAINTEN update by DMA mode" "0,1"
newline
bitfld.long 0x00 1. "ST0INTC,SHRTIMER_ST0INTC update by DMA mode" "0,1"
bitfld.long 0x00 0. "ST0CTL0,SHRTIMER_ST0CTL0 update by DMA mode" "0,1"
group.long 0x60++0x03
line.long 0x00 "DMAUPST1R,SHRTIMER DMA update Slave_TIMER1 register"
bitfld.long 0x00 31. "ST1ACTL,SHRTIMER_ST1ACTL update by DMA mode" "0,1"
bitfld.long 0x00 20. "ST1FLTCTL,SHRTIMER_ST1FLTCTL update by DMA mode" "0,1"
bitfld.long 0x00 19. "ST1CHOCTL,SHRTIMER_ST1CHOCTL update by DMA mode" "0,1"
bitfld.long 0x00 18. "ST1CSCTL,SHRTIMER_ST1CSCTL update by DMA mode" "0,1"
newline
bitfld.long 0x00 17. "ST1CNTRST,SHRTIMER_ST1CNTRST update by DMA mode" "0,1"
bitfld.long 0x00 16. "ST1EXEVFCFG1,SHRTIMER_ST1EXEVFCFG1update by DMA mode" "0,1"
bitfld.long 0x00 15. "ST1EXEVFCFG0,SHRTIMER_ST1EXEVFCFG0update by DMA mode" "0,1"
bitfld.long 0x00 14. "ST1CH1RST,SHRTIMER_ST1CH1RST update by DMA mode" "0,1"
newline
bitfld.long 0x00 13. "ST1CH1SET,SHRTIMER_ST1CH1SET update by DMA mode" "0,1"
bitfld.long 0x00 12. "ST1CH0RST,SHRTIMER_ST1CH0RST update by DMA mode" "0,1"
bitfld.long 0x00 11. "ST1CH0SET,SHRTIMER_ST1CH0SET update by DMA mode" "0,1"
bitfld.long 0x00 10. "ST1DTCTL,SHRTIMER_ST1DTCTL update by DMA mode" "0,1"
newline
bitfld.long 0x00 9. "ST1CMP3V,SHRTIMER_ST1CMP3V update by DMA mode" "0,1"
bitfld.long 0x00 8. "ST1CMP2V,SHRTIMER_ST1CMP2V update by DMA mode" "0,1"
bitfld.long 0x00 7. "ST1CMP1V,SHRTIMER_ST1CMP1V update by DMA mode" "0,1"
bitfld.long 0x00 6. "ST1CMP0V,SHRTIMER_ST1CMP0V update by DMA mode" "0,1"
newline
bitfld.long 0x00 5. "ST1CREP,SHRTIMER_ST1CREP update by DMA mode" "0,1"
bitfld.long 0x00 4. "ST1CAR,SHRTIMER_ST1CAR update by DMA mode" "0,1"
bitfld.long 0x00 3. "ST1CNT,SHRTIMER_ST1CNT update by DMA mode" "0,1"
bitfld.long 0x00 2. "ST1DMAINTEN,SHRTIMER_ST1DMAINTEN update by DMA mode" "0,1"
newline
bitfld.long 0x00 1. "ST1INTC,SHRTIMER_ST1INTC update by DMA mode" "0,1"
bitfld.long 0x00 0. "ST1CTL0,SHRTIMER_ST1CTL0 update by DMA mode" "0,1"
group.long 0x64++0x03
line.long 0x00 "DMAUPST2R,SHRTIMER DMA update Slave_TIMER2 register"
bitfld.long 0x00 31. "ST2ACTL,SHRTIMER_ST2ACTL update by DMA mode" "0,1"
bitfld.long 0x00 20. "ST2FLTCTL,SHRTIMER_ST2FLTCTL update by DMA mode" "0,1"
bitfld.long 0x00 19. "ST2CHOCTL,SHRTIMER_ST2CHOCTL update by DMA mode" "0,1"
bitfld.long 0x00 18. "ST2CSCTL,SHRTIMER_ST2CSCTL update by DMA mode" "0,1"
newline
bitfld.long 0x00 17. "ST2CNTRST,SHRTIMER_ST2CNTRST update by DMA mode" "0,1"
bitfld.long 0x00 16. "ST2EXEVFCFG1,SHRTIMER_ST2EXEVFCFG1update by DMA mode" "0,1"
bitfld.long 0x00 15. "ST2EXEVFCFG0,SHRTIMER_ST2EXEVFCFG0update by DMA mode" "0,1"
bitfld.long 0x00 14. "ST2CH1RST,SHRTIMER_ST2CH1RST update by DMA mode" "0,1"
newline
bitfld.long 0x00 13. "ST2CH1SET,SHRTIMER_ST2CH1SET update by DMA mode" "0,1"
bitfld.long 0x00 12. "ST2CH0RST,SHRTIMER_ST2CH0RST update by DMA mode" "0,1"
bitfld.long 0x00 11. "ST2CH0SET,SHRTIMER_ST2CH0SET update by DMA mode" "0,1"
bitfld.long 0x00 10. "ST2DTCTL,SHRTIMER_ST2DTCTL update by DMA mode" "0,1"
newline
bitfld.long 0x00 9. "ST2CMP3V,SHRTIMER_ST2CMP3V update by DMA mode" "0,1"
bitfld.long 0x00 8. "ST2CMP2V,SHRTIMER_ST2CMP2V update by DMA mode" "0,1"
bitfld.long 0x00 7. "ST2CMP1V,SHRTIMER_ST2CMP1V update by DMA mode" "0,1"
bitfld.long 0x00 6. "ST2CMP0V,SHRTIMER_ST2CMP0V update by DMA mode" "0,1"
newline
bitfld.long 0x00 5. "ST2CREP,SHRTIMER_ST2CREP update by DMA mode" "0,1"
bitfld.long 0x00 4. "ST2CAR,SHRTIMER_ST2CAR update by DMA mode" "0,1"
bitfld.long 0x00 3. "ST2CNT,SHRTIMER_ST2CNT update by DMA mode" "0,1"
bitfld.long 0x00 2. "ST2DMAINTEN,SHRTIMER_ST2DMAINTEN update by DMA mode" "0,1"
newline
bitfld.long 0x00 1. "ST2INTC,SHRTIMER_ST2INTC update by DMA mode" "0,1"
bitfld.long 0x00 0. "ST2CTL0,SHRTIMER_ST2CTL0 update by DMA mode" "0,1"
group.long 0x68++0x03
line.long 0x00 "DMAUPST3R,SHRTIMER DMA update Slave_TIMER3 register"
bitfld.long 0x00 31. "ST3ACTL,SHRTIMER_ST3ACTL update by DMA mode" "0,1"
bitfld.long 0x00 20. "ST3FLTCTL,SHRTIMER_ST3FLTCTL update by DMA mode" "0,1"
bitfld.long 0x00 19. "ST3CHOCTL,SHRTIMER_ST3CHOCTL update by DMA mode" "0,1"
bitfld.long 0x00 18. "ST3CSCTL,SHRTIMER_ST3CSCTL update by DMA mode" "0,1"
newline
bitfld.long 0x00 17. "ST3CNTRST,SHRTIMER_ST3CNTRST update by DMA mode" "0,1"
bitfld.long 0x00 16. "ST3EXEVFCFG1,SHRTIMER_ST3EXEVFCFG1update by DMA mode" "0,1"
bitfld.long 0x00 15. "ST3EXEVFCFG0,SHRTIMER_ST3EXEVFCFG0update by DMA mode" "0,1"
bitfld.long 0x00 14. "ST3CH1RST,SHRTIMER_ST3CH1RST update by DMA mode" "0,1"
newline
bitfld.long 0x00 13. "ST3CH1SET,SHRTIMER_ST3CH1SET update by DMA mode" "0,1"
bitfld.long 0x00 12. "ST3CH0RST,SHRTIMER_ST3CH0RST update by DMA mode" "0,1"
bitfld.long 0x00 11. "ST3CH0SET,SHRTIMER_ST3CH0SET update by DMA mode" "0,1"
bitfld.long 0x00 10. "ST3DTCTL,SHRTIMER_ST3DTCTL update by DMA mode" "0,1"
newline
bitfld.long 0x00 9. "ST3CMP3V,SHRTIMER_ST3CMP3V update by DMA mode" "0,1"
bitfld.long 0x00 8. "ST3CMP2V,SHRTIMER_ST3CMP2V update by DMA mode" "0,1"
bitfld.long 0x00 7. "ST3CMP1V,SHRTIMER_ST3CMP1V update by DMA mode" "0,1"
bitfld.long 0x00 6. "ST3CMP0V,SHRTIMER_ST3CMP0V update by DMA mode" "0,1"
newline
bitfld.long 0x00 5. "ST3CREP,SHRTIMER_ST3CREP update by DMA mode" "0,1"
bitfld.long 0x00 4. "ST3CAR,SHRTIMER_ST3CAR update by DMA mode" "0,1"
bitfld.long 0x00 3. "ST3CNT,SHRTIMER_ST3CNT update by DMA mode" "0,1"
bitfld.long 0x00 2. "ST3DMAINTEN,SHRTIMER_ST3DMAINTEN update by DMA mode" "0,1"
newline
bitfld.long 0x00 1. "ST3INTC,SHRTIMER_ST3INTC update by DMA mode" "0,1"
bitfld.long 0x00 0. "ST3CTL0,SHRTIMER_ST3CTL0 update by DMA mode" "0,1"
group.long 0x6C++0x03
line.long 0x00 "DMAUPST4R,SHRTIMER DMA update Slave_TIMER4 register"
bitfld.long 0x00 31. "ST4ACTL,SHRTIMER_ST4ACTL update by DMA mode" "0,1"
bitfld.long 0x00 20. "ST4FLTCTL,SHRTIMER_ST4FLTCTL update by DMA mode" "0,1"
bitfld.long 0x00 19. "ST4CHOCTL,SHRTIMER_ST4CHOCTL update by DMA mode" "0,1"
bitfld.long 0x00 18. "ST4CSCTL,SHRTIMER_ST4CSCTL update by DMA mode" "0,1"
newline
bitfld.long 0x00 17. "ST4CNTRST,SHRTIMER_ST4CNTRST update by DMA mode" "0,1"
bitfld.long 0x00 16. "ST4EXEVFCFG1,SHRTIMER_ST4EXEVFCFG1update by DMA mode" "0,1"
bitfld.long 0x00 15. "ST4EXEVFCFG0,SHRTIMER_ST4EXEVFCFG0update by DMA mode" "0,1"
bitfld.long 0x00 14. "ST4CH1RST,SHRTIMER_ST4CH1RST update by DMA mode" "0,1"
newline
bitfld.long 0x00 13. "ST4CH1SET,SHRTIMER_ST4CH1SET update by DMA mode" "0,1"
bitfld.long 0x00 12. "ST4CH0RST,SHRTIMER_ST4CH0RST update by DMA mode" "0,1"
bitfld.long 0x00 11. "ST4CH0SET,SHRTIMER_ST4CH0SET update by DMA mode" "0,1"
bitfld.long 0x00 10. "ST4DTCTL,SHRTIMER_ST4DTCTL update by DMA mode" "0,1"
newline
bitfld.long 0x00 9. "ST4CMP3V,SHRTIMER_ST4CMP3V update by DMA mode" "0,1"
bitfld.long 0x00 8. "ST4CMP2V,SHRTIMER_ST4CMP2V update by DMA mode" "0,1"
bitfld.long 0x00 7. "ST4CMP1V,SHRTIMER_ST4CMP1V update by DMA mode" "0,1"
bitfld.long 0x00 6. "ST4CMP0V,SHRTIMER_ST4CMP0V update by DMA mode" "0,1"
newline
bitfld.long 0x00 5. "ST4CREP,SHRTIMER_ST4CREP update by DMA mode" "0,1"
bitfld.long 0x00 4. "ST4CAR,SHRTIMER_ST4CAR update by DMA mode" "0,1"
bitfld.long 0x00 3. "ST4CNT,SHRTIMER_ST4CNT update by DMA mode" "0,1"
bitfld.long 0x00 2. "ST4DMAINTEN,SHRTIMER_ST4DMAINTEN update by DMA mode" "0,1"
newline
bitfld.long 0x00 1. "ST4INTC,SHRTIMER_ST4INTC update by DMA mode" "0,1"
bitfld.long 0x00 0. "ST4CTL0,SHRTIMER_ST4CTL0 update by DMA mode" "0,1"
wgroup.long 0x70++0x03
line.long 0x00 "DMATB,SHRTIMER DMA transfer buffer register"
hexmask.long 0x00 0.--31. 1. "DMATB,DMA transfer buffer"
tree.end
tree "SLAVE_TIMER0"
base ad:0x40017480
group.long 0x00++0x03
line.long 0x00 "ST0CTL0,SHRTIMER Slave_TIMER0 control register 0"
bitfld.long 0x00 28.--31. "UPSEL,Update event selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 27. "SHWEN,Shadow registers enable" "0,1"
bitfld.long 0x00 25.--26. "DACTRGS,Trigger source to DAC" "0,1,2,3"
bitfld.long 0x00 24. "UPBMT,Update by Master_TIMER update event" "0,1"
newline
bitfld.long 0x00 23. "UPBST4,Update by Slave_TIMER4 update event" "0,1"
bitfld.long 0x00 22. "UPBST3,Update by Slave_TIMER3 update event" "0,1"
bitfld.long 0x00 21. "UPBST2,Update by Slave_TIMER2 update event" "0,1"
bitfld.long 0x00 20. "UPBST1,Update by Slave_TIMER1 update event" "0,1"
newline
bitfld.long 0x00 18. "UPRST,Update event generated by reset event" "0,1"
bitfld.long 0x00 17. "UPREP,Update event generated by repetition event" "0,1"
bitfld.long 0x00 14.--15. "DELCMP3M,Compare 3 delayed mode" "0,1,2,3"
bitfld.long 0x00 12.--13. "DELCMP1M,Compare 1 delayed mode" "0,1,2,3"
newline
bitfld.long 0x00 11. "SYNISTRT,Synchronization input start counter" "0,1"
bitfld.long 0x00 10. "SYNIRST,Synchronization input reset counter" "0,1"
bitfld.long 0x00 6. "BLNMEN,Balanced mode enable" "0,1"
bitfld.long 0x00 5. "HALFM,Half mode" "0,1"
newline
bitfld.long 0x00 4. "CNTRSTM,Counter reset mode" "0,1"
bitfld.long 0x00 3. "CTNM,Continuous mode" "0,1"
bitfld.long 0x00 0.--2. "CNTCKDIV,Counter clock division" "0,1,2,3,4,5,6,7"
rgroup.long 0x04++0x03
line.long 0x00 "ST0INTF,SHRTIMER Slave_TIMER0 interrupt flag register"
bitfld.long 0x00 21. "CH1F,Channel 1 output flag" "0,1"
bitfld.long 0x00 20. "CH0F,Channel 0 output flag" "0,1"
bitfld.long 0x00 17. "BLNIF,Balanced IDLE flag" "0,1"
bitfld.long 0x00 16. "CBLNF,Current balanced flag" "0,1"
newline
bitfld.long 0x00 14. "DLYIIF,Delayed IDLE mode entry interrupt flag" "0,1"
bitfld.long 0x00 13. "RSTIF,Counter reset interrupt flag" "0,1"
bitfld.long 0x00 12. "CH1ONAIF,Channel 1 output inactive interrupt flag" "0,1"
bitfld.long 0x00 11. "CH1OAIF,Channel 1 output active interrupt flag" "0,1"
newline
bitfld.long 0x00 10. "CH0ONAIF,Channel 0 output inactive interrupt flag" "0,1"
bitfld.long 0x00 9. "CH0OAIF,Channel 0 output active interrupt flag" "0,1"
bitfld.long 0x00 8. "CAP1IF,Capture 1 interrupt flag" "0,1"
bitfld.long 0x00 7. "CAP0IF,Capture 0 interrupt flag" "0,1"
newline
bitfld.long 0x00 6. "UPIF,Update interrupt flag" "0,1"
bitfld.long 0x00 4. "REPIF,Repetition interrupt flag" "0,1"
bitfld.long 0x00 3. "CMP3IF,Compare 3 interrupt flag" "0,1"
bitfld.long 0x00 2. "CMP2IF,Compare 2 interrupt flag" "0,1"
newline
bitfld.long 0x00 1. "CMP1IF,Compare 1 interrupt flag" "0,1"
bitfld.long 0x00 0. "CMP0IF,Compare 0 interrupt flag" "0,1"
wgroup.long 0x08++0x03
line.long 0x00 "ST0INTC,SHRTIMER Slave_TIMER0 interrupt flag clear register"
bitfld.long 0x00 14. "DLYIIFC,Clear delayed IDLE mode entry interrupt flag" "0,1"
bitfld.long 0x00 13. "RSTIFC,Clear counter reset interrupt flag" "0,1"
bitfld.long 0x00 12. "CH1ONAIFC,Clear channel 1 output inactive interrupt flag" "0,1"
bitfld.long 0x00 11. "CH1OAIFC,Clear channel 1 output active interrupt flag" "0,1"
newline
bitfld.long 0x00 10. "CH0ONAIFC,Clear channel 0 output inactive interrupt flag" "0,1"
bitfld.long 0x00 9. "CH0OAIFC,Clear channel 0 output active interrupt flag" "0,1"
bitfld.long 0x00 8. "CAP1IFC,Clear capture 1 interrupt flag" "0,1"
bitfld.long 0x00 7. "CAP0IFC,Clear capture 0 interrupt flag" "0,1"
newline
bitfld.long 0x00 6. "UPIFC,Clear update interrupt flag" "0,1"
bitfld.long 0x00 4. "REPIFC,Clear repetition interrupt flag" "0,1"
bitfld.long 0x00 3. "CMP3IFC,Clear compare 3 interrupt flag" "0,1"
bitfld.long 0x00 2. "CMP2IFC,Clear compare 2 interrupt flag" "0,1"
newline
bitfld.long 0x00 1. "CMP1IFC,Clear compare 1 interrupt flag" "0,1"
bitfld.long 0x00 0. "CMP0IFC,Clear compare 0 interrupt flag" "0,1"
group.long 0x0C++0x03
line.long 0x00 "ST0DMAINTEN,SHRTIMER Slave_TIMER0 DMA and interrupt enable register"
bitfld.long 0x00 30. "DLYIDEN,Delayed IDLE mode entry DMA request enable" "0,1"
bitfld.long 0x00 29. "RSTDEN,Counter reset DMA request enable" "0,1"
bitfld.long 0x00 28. "CH1ONADEN,Channel 1 output inactive DMA request enable" "0,1"
bitfld.long 0x00 27. "CH1OADEN,Channel 1 output active DMA request enable" "0,1"
newline
bitfld.long 0x00 26. "CH0ONADEN,Channel 0 output inactive DMA request enable" "0,1"
bitfld.long 0x00 25. "CH0ADEN,Channel 0 output active DMA request enable" "0,1"
bitfld.long 0x00 24. "CAP1DEN,Capture 1 DMA request enable" "0,1"
bitfld.long 0x00 23. "CAP0DEN,Capture 0 DMA request enable" "0,1"
newline
bitfld.long 0x00 22. "UPDEN,Update DMA request enable" "0,1"
bitfld.long 0x00 20. "REPDEN,Repetition DMA request enable" "0,1"
bitfld.long 0x00 19. "CMP3DEN,Compare 3 DMA request enable" "0,1"
bitfld.long 0x00 18. "CMP2DEN,Compare 2 DMA request enable" "0,1"
newline
bitfld.long 0x00 17. "CMP1DEN,Compare 1 DMA request enable" "0,1"
bitfld.long 0x00 16. "CMP0DEN,Compare 0 DMA request enable" "0,1"
bitfld.long 0x00 14. "DLYIIE,Delayed IDLE mode entry interrupt enable" "0,1"
bitfld.long 0x00 13. "RSTIE,Counter reset interrupt enable" "0,1"
newline
bitfld.long 0x00 12. "CH1ONAIE,Channel 1 output inactive interrupt enable" "0,1"
bitfld.long 0x00 11. "CH1OAIE,Channel 1 output active interrupt enable" "0,1"
bitfld.long 0x00 10. "CH0ONAIE,Channel 0 output inactive interrupt enable" "0,1"
bitfld.long 0x00 9. "CH0OAIE,Channel 0 output active interrupt enable" "0,1"
newline
bitfld.long 0x00 8. "CAP1IE,Capture 1 interrupt enable" "0,1"
bitfld.long 0x00 7. "CAP0IE,Capture 0 interrupt enable" "0,1"
bitfld.long 0x00 6. "UPIE,Update interrupt enable" "0,1"
bitfld.long 0x00 4. "REPIE,Repetition interrupt enable" "0,1"
newline
bitfld.long 0x00 3. "CMP3IE,Compare 3 interrupt enable" "0,1"
bitfld.long 0x00 2. "CMP2IE,Compare 2 interrupt enable" "0,1"
bitfld.long 0x00 1. "CMP1IE,Compare 1 interrupt enable" "0,1"
bitfld.long 0x00 0. "CMP0IE,Compare 0 interrupt enable" "0,1"
group.long 0x10++0x03
line.long 0x00 "ST0CNT,SHRTIMER Slave_TIMER0 counter register"
hexmask.long.word 0x00 0.--15. 1. "CNT,The current counter value"
group.long 0x14++0x03
line.long 0x00 "ST0CAR,SHRTIMER Slave_TIMER0 counter auto reload register"
hexmask.long.word 0x00 0.--15. 1. "CARL,Counter auto reload value"
group.long 0x18++0x03
line.long 0x00 "ST0CREP,SHRTIMER Slave_TIMER0 counter repetition register"
hexmask.long.byte 0x00 0.--7. 1. "CREP,Counter repetition value"
group.long 0x1C++0x03
line.long 0x00 "ST0CMP0V,SHRTIMER Slave_TIMER0 compare 0 value register"
hexmask.long.word 0x00 0.--15. 1. "CMP0VAL,Compare 0 value"
group.long 0x20++0x03
line.long 0x00 "ST0CMP0CP,SHRTIMER Slave_TIMER0 compare 0 composite register"
hexmask.long.byte 0x00 16.--23. 1. "CREP,Counter repetition value"
hexmask.long.word 0x00 0.--15. 1. "CMP0VAL,Compare 0 value"
group.long 0x24++0x03
line.long 0x00 "ST0CMP1V,SHRTIMER Slave_TIMER0 compare 1 value register"
hexmask.long.word 0x00 0.--15. 1. "CMP1VAL,Compare 1 value"
group.long 0x28++0x03
line.long 0x00 "ST0CMP2V,SHRTIMER Slave_TIMER0 compare 2 value register"
hexmask.long.word 0x00 0.--15. 1. "CMP2VAL,Compare 2 value"
group.long 0x2C++0x03
line.long 0x00 "ST0CMP3V,SHRTIMER Slave_TIMER0 compare 3 value register"
hexmask.long.word 0x00 0.--15. 1. "CMP3VAL,Compare 3 value"
group.long 0x30++0x03
line.long 0x00 "ST0CAP0V,SHRTIMER Slave_TIMER0 capture 0 value register"
hexmask.long.word 0x00 0.--15. 1. "CAP0VAL,Capture 0 value"
group.long 0x34++0x03
line.long 0x00 "ST0CAP1V,SHRTIMER Slave_TIMER0 capture 1 value register"
hexmask.long.word 0x00 0.--15. 1. "CAP1VAL,Capture 1 value"
group.long 0x38++0x03
line.long 0x00 "ST0DTCTL,SHRTIMER Slave_TIMER0 dead-time control register"
bitfld.long 0x00 31. "DTFSVPROT,Dead-time falling edge protection for value and sign" "0,1"
bitfld.long 0x00 30. "DTFSPROT,Dead-time falling edge protection for sign" "0,1"
bitfld.long 0x00 25. "DTFS,The sign of falling edge dead-time value" "0,1"
hexmask.long.word 0x00 16.--24. 1. "DTFCFG,Falling edge dead-time value"
newline
bitfld.long 0x00 15. "DTRSVPROT,Dead-time rising edge protection for value and sign" "0,1"
bitfld.long 0x00 14. "DTRSPROT,Dead-time rising edge protection for sign" "0,1"
bitfld.long 0x00 10.--13. "DTGCKDIV,Dead time generator clock division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 9. "DTRS,The sign of falling edge dead-time value" "0,1"
newline
hexmask.long.word 0x00 0.--8. 1. "DTRCFG,Falling edge dead-time value"
group.long 0x3C++0x03
line.long 0x00 "ST0CH0SET,SHRTIMER Slave_TIMERx channel 0 set request register"
bitfld.long 0x00 31. "CH0SUP,Update event generates channel 0" "0,1"
bitfld.long 0x00 30. "CH0SEXEV9,External event 9 generates channel 0" "0,1"
bitfld.long 0x00 29. "CH0SEXEV8,External event 8 generates channel 0" "0,1"
bitfld.long 0x00 28. "CH0SEXEV7,External event 7 generates channel 0" "0,1"
newline
bitfld.long 0x00 27. "CH0SEXEV6,External event 6 generates channel 0" "0,1"
bitfld.long 0x00 26. "CH0SEXEV5,External event 5 generates channel 0" "0,1"
bitfld.long 0x00 25. "CH0SEXEV4,External event 4 generates channel 0" "0,1"
bitfld.long 0x00 24. "CH0SEXEV3,External event 3 generates channel 0" "0,1"
newline
bitfld.long 0x00 23. "CH0SEXEV2,External event 2 generates channel 0" "0,1"
bitfld.long 0x00 22. "CH0SEXEV1,External event 1 generates channel 0" "0,1"
bitfld.long 0x00 21. "CH0SEXEV0,External event 0 generates channel 0" "0,1"
bitfld.long 0x00 20. "CH0SSTEV8,Slave_TIMER0 interconnection event 8 generates channel 0" "0,1"
newline
bitfld.long 0x00 19. "CH0SSTEV7,Slave_TIMER0 interconnection event 7 generates channel 0" "0,1"
bitfld.long 0x00 18. "CH0SSTEV6,Slave_TIMER0 interconnection event 6 generates channel 0" "0,1"
bitfld.long 0x00 17. "CH0SSTEV5,Slave_TIMER0 interconnection event 5 generates channel 0" "0,1"
bitfld.long 0x00 16. "CH0SSTEV4,Slave_TIMER0 interconnection event 4 generates channel 0" "0,1"
newline
bitfld.long 0x00 15. "CH0SSTEV3,Slave_TIMER0 interconnection event 3 generates channel 0" "0,1"
bitfld.long 0x00 14. "CH0SSTEV2,Slave_TIMER0 interconnection event 2 generates channel 0" "0,1"
bitfld.long 0x00 13. "CH0SSTEV1,Slave_TIMER0 interconnection event 1 generates channel 0" "0,1"
bitfld.long 0x00 12. "CH0SSTEV0,Slave_TIMER0 interconnection event 0 generates channel 0" "0,1"
newline
bitfld.long 0x00 11. "CH0SMTCMP3,Master_TIMER compare 3 event generates channel 0" "0,1"
bitfld.long 0x00 10. "CH0SMTCMP2,Master_TIMER compare 2 event generates channel 0" "0,1"
bitfld.long 0x00 9. "CH0SMTCMP1,Master_TIMER compare 1 event generates channel 0" "0,1"
bitfld.long 0x00 8. "CH0SMTCMP0,Master_TIMER compare 0 event generates channel 0" "0,1"
newline
bitfld.long 0x00 7. "CH0SMTPER,Master_TIMER period event generates channel 0" "0,1"
bitfld.long 0x00 6. "CH0SCMP3,Slave_TIMER0 compare 3 event generates channel 0" "0,1"
bitfld.long 0x00 5. "CH0SCMP2,Slave_TIMER0 compare 2 event generates channel 0" "0,1"
bitfld.long 0x00 4. "CH0SCMP1,Slave_TIMER0 compare 1 event generates channel 0" "0,1"
newline
bitfld.long 0x00 3. "CH0SCMP0,Slave_TIMER0 compare 0 event generates channel 0" "0,1"
bitfld.long 0x00 2. "CH0SPER,Slave_TIMER0 period event generates channel 0" "0,1"
bitfld.long 0x00 1. "CH0SRST,Slave_TIMER0 reset event generates channel 0" "0,1"
bitfld.long 0x00 0. "CH0SSEV,Software event generates channel 0" "0,1"
group.long 0x40++0x03
line.long 0x00 "ST0CH0RST,SHRTIMER Slave_TIMER0 channel 0 reset request register"
bitfld.long 0x00 31. "CH0RSUP,Update event generates channel 0" "0,1"
bitfld.long 0x00 30. "CH0RSEXEV9,External event 9 generates channel 0" "0,1"
bitfld.long 0x00 29. "CH0RSEXEV8,External event 8 generates channel 0" "0,1"
bitfld.long 0x00 28. "CH0RSEXEV7,External event 7 generates channel 0" "0,1"
newline
bitfld.long 0x00 27. "CH0RSEXEV6,External event 6 generates channel 0" "0,1"
bitfld.long 0x00 26. "CH0RSEXEV5,External event 5 generates channel 0" "0,1"
bitfld.long 0x00 25. "CH0RSEXEV4,External event 4 generates channel 0" "0,1"
bitfld.long 0x00 24. "CH0RSEXEV3,External event 3 generates channel 0" "0,1"
newline
bitfld.long 0x00 23. "CH0RSEXEV2,External event 2 generates channel 0" "0,1"
bitfld.long 0x00 22. "CH0RSEXEV1,External event 1 generates channel 0" "0,1"
bitfld.long 0x00 21. "CH0RSEXEV0,External event 0 generates channel 0" "0,1"
bitfld.long 0x00 20. "CH0RSSTEV8,Slave_TIMER0 interconnection event 8 generates channel 0" "0,1"
newline
bitfld.long 0x00 19. "CH0RSSTEV7,Slave_TIMER0 interconnection event 7 generates channel 0" "0,1"
bitfld.long 0x00 18. "CH0RSSTEV6,Slave_TIMER0 interconnection event 6 generates channel 0" "0,1"
bitfld.long 0x00 17. "CH0RSSTEV5,Slave_TIMER0 interconnection event 5 generates channel 0" "0,1"
bitfld.long 0x00 16. "CH0RSSTEV4,Slave_TIMER0 interconnection event 4 generates channel 0" "0,1"
newline
bitfld.long 0x00 15. "CH0RSSTEV3,Slave_TIMER0 interconnection event 3 generates channel 0" "0,1"
bitfld.long 0x00 14. "CH0RSSTEV2,Slave_TIMER0 interconnection event 2 generates channel 0" "0,1"
bitfld.long 0x00 13. "CH0RSSTEV1,Slave_TIMER0 interconnection event 1 generates channel 0" "0,1"
bitfld.long 0x00 12. "CH0RSSTEV0,Slave_TIMER0 interconnection event 0 generates channel 0" "0,1"
newline
bitfld.long 0x00 11. "CH0RSMTCMP3,Master_TIMER compare 3 event generates channel 0" "0,1"
bitfld.long 0x00 10. "CH0RSMTCMP2,Master_TIMER compare 2 event generates channel 0" "0,1"
bitfld.long 0x00 9. "CH0RSMTCMP1,Master_TIMER compare 1 event generates channel 0" "0,1"
bitfld.long 0x00 8. "CH0RSMTCMP0,Master_TIMER compare 0 event generates channel 0" "0,1"
newline
bitfld.long 0x00 7. "CH0RSMTPER,Master_TIMER period event generates channel 0" "0,1"
bitfld.long 0x00 6. "CH0RSCMP3,Slave_TIMER0 compare 3 event generates channel 0" "0,1"
bitfld.long 0x00 5. "CH0RSCMP2,Slave_TIMER0 compare 2 event generates channel 0" "0,1"
bitfld.long 0x00 4. "CH0RSCMP1,Slave_TIMER0 compare 1 event generates channel 0" "0,1"
newline
bitfld.long 0x00 3. "CH0RSCMP0,Slave_TIMER0 compare 0 event generates channel 0" "0,1"
bitfld.long 0x00 2. "CH0RSPER,Slave_TIMER0 period event generates channel 0" "0,1"
bitfld.long 0x00 1. "CH0RSRST,Slave_TIMER0 reset event generates channel 0" "0,1"
bitfld.long 0x00 0. "CH0RSSEV,Software event generates channel 0" "0,1"
group.long 0x44++0x03
line.long 0x00 "ST0CH1SET,SHRTIMER Slave_TIMER0 channel 1 set request register"
bitfld.long 0x00 31. "CH1SUP,Update event generates channel 1" "0,1"
bitfld.long 0x00 30. "CH1SEXEV9,External event 9 generates channel 1" "0,1"
bitfld.long 0x00 29. "CH1SEXEV8,External event 8 generates channel 1" "0,1"
bitfld.long 0x00 28. "CH1SEXEV7,External event 7 generates channel 1" "0,1"
newline
bitfld.long 0x00 27. "CH1SEXEV6,External event 6 generates channel 1" "0,1"
bitfld.long 0x00 26. "CH1SEXEV5,External event 5 generates channel 1" "0,1"
bitfld.long 0x00 25. "CH1SEXEV4,External event 4 generates channel 1" "0,1"
bitfld.long 0x00 24. "CH1SEXEV3,External event 3 generates channel 1" "0,1"
newline
bitfld.long 0x00 23. "CH1SEXEV2,External event 2 generates channel 1" "0,1"
bitfld.long 0x00 22. "CH1SEXEV1,External event 1 generates channel 1" "0,1"
bitfld.long 0x00 21. "CH1SEXEV0,External event 0 generates channel 1" "0,1"
bitfld.long 0x00 20. "CH1SSTEV8,Slave_TIMER0 interconnection event 8 generates channel 1" "0,1"
newline
bitfld.long 0x00 19. "CH1SSTEV7,Slave_TIMER0 interconnection event 7 generates channel 1" "0,1"
bitfld.long 0x00 18. "CH1SSTEV6,Slave_TIMER0 interconnection event 6 generates channel 1" "0,1"
bitfld.long 0x00 17. "CH1SSTEV5,Slave_TIMER0 interconnection event 5 generates channel 1" "0,1"
bitfld.long 0x00 16. "CH1SSTEV4,Slave_TIMER0 interconnection event 4 generates channel 1" "0,1"
newline
bitfld.long 0x00 15. "CH1SSTEV3,Slave_TIMER0 interconnection event 3 generates channel 1" "0,1"
bitfld.long 0x00 14. "CH1SSTEV2,Slave_TIMER0 interconnection event 2 generates channel 1" "0,1"
bitfld.long 0x00 13. "CH1SSTEV1,Slave_TIMER0 interconnection event 1 generates channel 1" "0,1"
bitfld.long 0x00 12. "CH1SSTEV0,Slave_TIMER0 interconnection event 0 generates channel 1" "0,1"
newline
bitfld.long 0x00 11. "CH1SMTCMP3,Master_TIMER compare 3 event generates channel 1" "0,1"
bitfld.long 0x00 10. "CH1SMTCMP2,Master_TIMER compare 2 event generates channel 1" "0,1"
bitfld.long 0x00 9. "CH1SMTCMP1,Master_TIMER compare 1 event generates channel 1" "0,1"
bitfld.long 0x00 8. "CH1SMTCMP0,Master_TIMER compare 0 event generates channel 1" "0,1"
newline
bitfld.long 0x00 7. "CH1SMTPER,Master_TIMER period event generates channel 1" "0,1"
bitfld.long 0x00 6. "CH1SCMP3,Slave_TIMER0 compare 3 event generates channel 1" "0,1"
bitfld.long 0x00 5. "CH1SCMP2,Slave_TIMER0 compare 2 event generates channel 1" "0,1"
bitfld.long 0x00 4. "CH1SCMP1,Slave_TIMER0 compare 1 event generates channel 1" "0,1"
newline
bitfld.long 0x00 3. "CH1SCMP0,Slave_TIMER0 compare 0 event generates channel 1" "0,1"
bitfld.long 0x00 2. "CH1SPER,Slave_TIMER0 period event generates channel 1" "0,1"
bitfld.long 0x00 1. "CH1SRST,Slave_TIMER0 reset event generates channel 1" "0,1"
bitfld.long 0x00 0. "CH1SSEV,Software event generates channel 1" "0,1"
group.long 0x48++0x03
line.long 0x00 "ST0CH1RST,SHRTIMER Slave_TIMER0 channel 1 reset request register"
bitfld.long 0x00 31. "CH1RSUP,Update event generates channel 1" "0,1"
bitfld.long 0x00 30. "CH1RSEXEV9,External event 9 generates channel 1" "0,1"
bitfld.long 0x00 29. "CH1RSEXEV8,External event 8 generates channel 1" "0,1"
bitfld.long 0x00 28. "CH1RSEXEV7,External event 7 generates channel 1" "0,1"
newline
bitfld.long 0x00 27. "CH1RSEXEV6,External event 6 generates channel 1" "0,1"
bitfld.long 0x00 26. "CH1RSEXEV5,External event 5 generates channel 1" "0,1"
bitfld.long 0x00 25. "CH1RSEXEV4,External event 4 generates channel 1" "0,1"
bitfld.long 0x00 24. "CH1RSEXEV3,External event 3 generates channel 1" "0,1"
newline
bitfld.long 0x00 23. "CH1RSEXEV2,External event 2 generates channel 1" "0,1"
bitfld.long 0x00 22. "CH1RSEXEV1,External event 1 generates channel 1" "0,1"
bitfld.long 0x00 21. "CH1RSEXEV0,External event 0 generates channel 1" "0,1"
bitfld.long 0x00 20. "CH1RSSTEV8,Slave_TIMER0 interconnection event 8 generates channel 1" "0,1"
newline
bitfld.long 0x00 19. "CH1RSSTEV7,Slave_TIMER0 interconnection event 7 generates channel 1" "0,1"
bitfld.long 0x00 18. "CH1RSSTEV6,Slave_TIMER0 interconnection event 6 generates channel 1" "0,1"
bitfld.long 0x00 17. "CH1RSSTEV5,Slave_TIMER0 interconnection event 5 generates channel 1" "0,1"
bitfld.long 0x00 16. "CH1RSSTEV4,Slave_TIMER0 interconnection event 4 generates channel 1" "0,1"
newline
bitfld.long 0x00 15. "CH1RSSTEV3,Slave_TIMER0 interconnection event 3 generates channel 1" "0,1"
bitfld.long 0x00 14. "CH1RSSTEV2,Slave_TIMER0 interconnection event 2 generates channel 1" "0,1"
bitfld.long 0x00 13. "CH1RSSTEV1,Slave_TIMER0 interconnection event 1 generates channel 1" "0,1"
bitfld.long 0x00 12. "CH1RSSTEV0,Slave_TIMER0 interconnection event 0 generates channel 1" "0,1"
newline
bitfld.long 0x00 11. "CH1RSMTCMP3,Master_TIMER compare 3 event generates channel 1" "0,1"
bitfld.long 0x00 10. "CH1RSMTCMP2,Master_TIMER compare 2 event generates channel 1" "0,1"
bitfld.long 0x00 9. "CH1RSMTCMP1,Master_TIMER compare 1 event generates channel 1" "0,1"
bitfld.long 0x00 8. "CH1RSMTCMP0,Master_TIMER compare 0 event generates channel 1" "0,1"
newline
bitfld.long 0x00 7. "CH1RSMTPER,Master_TIMER period event generates channel 1" "0,1"
bitfld.long 0x00 6. "CH1RSCMP3,Slave_TIMER0 compare 3 event generates channel 1" "0,1"
bitfld.long 0x00 5. "CH1RSCMP2,Slave_TIMER0 compare 2 event generates channel 1" "0,1"
bitfld.long 0x00 4. "CH1RSCMP1,Slave_TIMER0 compare 1 event generates channel 1" "0,1"
newline
bitfld.long 0x00 3. "CH1RSCMP0,Slave_TIMER0 compare 0 event generates channel 1" "0,1"
bitfld.long 0x00 2. "CH1RSPER,Slave_TIMER0 period event generates channel 1" "0,1"
bitfld.long 0x00 1. "CH1RSRST,Slave_TIMER0 reset event generates channel 1" "0,1"
bitfld.long 0x00 0. "CH1RSSEV,Software event generates channel 1" "0,1"
group.long 0x4C++0x03
line.long 0x00 "ST0EXEVFCFG0,SHRTIMER Slave_TIMERx external event filter configuration register 0"
bitfld.long 0x00 25.--28. "EXEV4FM,External event 4 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24. "EXEV4MEEN,External event 4 memorized enable" "0,1"
bitfld.long 0x00 19.--22. "EXEV3FM,External event 3 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 18. "EXEV3MEEN,External event 3 memorized enable" "0,1"
newline
bitfld.long 0x00 13.--16. "EXEV2FM,External event 2 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12. "EXEV2MEEN,External event 2 memorized enable" "0,1"
bitfld.long 0x00 7.--10. "EXEV1FM,External event 1 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "EXEV1MEEN,External event 1 memorized enable" "0,1"
newline
bitfld.long 0x00 1.--4. "EXEV0FM,External event 0 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "EXEV0MEEN,External event 0 memorized enable" "0,1"
group.long 0x50++0x03
line.long 0x00 "ST0EXEVFCFG1,SHRTIMER Slave_TIMERx external event filter configuration register 1"
bitfld.long 0x00 25.--28. "EXEV9FM,External event 9 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24. "EXEV9MEEN,External event 9 memorized enable" "0,1"
bitfld.long 0x00 19.--22. "EXEV8FM,External event 8 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 18. "EXEV8MEEN,External event 8 memorized enable" "0,1"
newline
bitfld.long 0x00 13.--16. "EXEV7FM,External event 7 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12. "EXEV7MEEN,External event 7 memorized enable" "0,1"
bitfld.long 0x00 7.--10. "EXEV6FM,External event 6 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "EXEV6MEEN,External event 6 memorized enable" "0,1"
newline
bitfld.long 0x00 1.--4. "EXEV5FM,External event 5 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "EXEV5MEEN,External event 5 memorized enable" "0,1"
group.long 0x54++0x03
line.long 0x00 "ST0CNTRST,SHRTIMER Slave_TIMER0 counter reset register"
bitfld.long 0x00 30. "ST4CMP3RST,Slave_TIMER4 compare 3 event resets counter" "0,1"
bitfld.long 0x00 29. "ST4CMP1RST,Slave_TIMER4 compare 1 event resets counter" "0,1"
bitfld.long 0x00 28. "ST4CMP0RST,Slave_TIMER4 compare 0 event resets counter" "0,1"
bitfld.long 0x00 27. "ST3CMP3RST,Slave_TIMER3 compare 3 event resets counter" "0,1"
newline
bitfld.long 0x00 26. "ST3CMP1RST,Slave_TIMER3 compare 1 event resets counter" "0,1"
bitfld.long 0x00 25. "ST3CMP0RST,Slave_TIMER3 compare 0 event resets counter" "0,1"
bitfld.long 0x00 24. "ST2CMP3RST,Slave_TIMER2 compare 3 event resets counter" "0,1"
bitfld.long 0x00 23. "ST2CMP1RST,Slave_TIMER2 compare 1 event resets counter" "0,1"
newline
bitfld.long 0x00 22. "ST2CMP0RST,Slave_TIMER2 compare 0 event resets counter" "0,1"
bitfld.long 0x00 21. "ST1CMP3RST,Slave_TIMER1 compare 3 event resets counter" "0,1"
bitfld.long 0x00 20. "ST1CMP1RST,Slave_TIMER1 compare 1 event resets counter" "0,1"
bitfld.long 0x00 19. "ST1CMP0RST,Slave_TIMER1 compare 0 event resets counter" "0,1"
newline
bitfld.long 0x00 18. "EXEV9RST,External event 9 resets counter" "0,1"
bitfld.long 0x00 17. "EXEV8RST,External event 8 resets counter" "0,1"
bitfld.long 0x00 16. "EXEV7RST,External event 7 resets counter" "0,1"
bitfld.long 0x00 15. "EXEV6RST,External event 6 resets counter" "0,1"
newline
bitfld.long 0x00 14. "EXEV5RST,External event 5 resets counter" "0,1"
bitfld.long 0x00 13. "EXEV4RST,External event 4 resets counter" "0,1"
bitfld.long 0x00 12. "EXEV3RST,External event 3 resets counter" "0,1"
bitfld.long 0x00 11. "EXEV2RST,External event 2 resets counter" "0,1"
newline
bitfld.long 0x00 10. "EXEV1RST,External event 1 resets counter" "0,1"
bitfld.long 0x00 9. "EXEV0RST,External event 0 resets counter" "0,1"
bitfld.long 0x00 8. "MTCMP3RST,Master_TIMER compare 3 event resets counter" "0,1"
bitfld.long 0x00 7. "MTCMP2RST,Master_TIMER compare 2 event resets counter" "0,1"
newline
bitfld.long 0x00 6. "MTCMP1RST,Master_TIMER compare 1 event resets counter" "0,1"
bitfld.long 0x00 5. "MTCMP0RST,Master_TIMER compare 0 event resets counter" "0,1"
bitfld.long 0x00 4. "MTPERRST,Master_TIMER period event resets counter" "0,1"
bitfld.long 0x00 3. "CMP3RST,Slave_TIMER0 compare 3 event resets counter" "0,1"
newline
bitfld.long 0x00 2. "CMP1RST,Slave_TIMER0 compare 1 event resets counter" "0,1"
bitfld.long 0x00 1. "UPRST,Slave_TIMER0 update event resets counter" "0,1"
group.long 0x58++0x03
line.long 0x00 "ST0CSCTL,SHRTIMER Slave_TIMERx carrier-signal control register"
bitfld.long 0x00 7.--10. "CSFSTPW,First carrier-signal pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--6. "CSDTY,Carrier signal duty cycle" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--3. "CSPRD,Carrier signal period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x5C++0x03
line.long 0x00 "ST0CAP0TRG,SHRTIMER Slave_TIMER0 capture 0 trigger register"
bitfld.long 0x00 31. "CP0BST4CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER4" "0,1"
bitfld.long 0x00 30. "CP0BST4CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER4" "0,1"
bitfld.long 0x00 29. "CP0BST4NA,Capture 0 triggered by ST4CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 28. "CP0BST4A,Capture 0 triggered by ST4CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 27. "CP0BST3CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER3" "0,1"
bitfld.long 0x00 26. "CP0BST3CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER3" "0,1"
bitfld.long 0x00 25. "CP0BST3NA,Capture 0 triggered by ST3CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 24. "CP0BST3A,Capture 0 triggered by ST3CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 23. "CP0BST2CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER2" "0,1"
bitfld.long 0x00 22. "CP0BST2CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER2" "0,1"
bitfld.long 0x00 21. "CP0BST2NA,Capture 0 triggered by ST2CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 20. "CP0BST2A,Capture 0 triggered by ST2CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 19. "CP0BST1CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER1" "0,1"
bitfld.long 0x00 18. "CP0BST1CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER1" "0,1"
bitfld.long 0x00 17. "CP0BST1NA,Capture 0 triggered by ST1CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 16. "CP0BST1A,Capture 0 triggered by ST1CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 11. "CP0BEXEV9,Capture 0 triggered by external event 9" "0,1"
bitfld.long 0x00 10. "CP0BEXEV8,Capture 0 triggered by external event 8" "0,1"
bitfld.long 0x00 9. "CP0BEXEV7,Capture 0 triggered by external event 7" "0,1"
bitfld.long 0x00 8. "CP0BEXEV6,Capture 0 triggered by external event 6" "0,1"
newline
bitfld.long 0x00 7. "CP0BEXEV5,Capture 0 triggered by external event 5" "0,1"
bitfld.long 0x00 6. "CP0BEXEV4,Capture 0 triggered by external event 4" "0,1"
bitfld.long 0x00 5. "CP0BEXEV3,Capture 0 triggered by external event 3" "0,1"
bitfld.long 0x00 4. "CP0BEXEV2,Capture 0 triggered by external event 2" "0,1"
newline
bitfld.long 0x00 3. "CP0BEXEV1,Capture 0 triggered by external event 1" "0,1"
bitfld.long 0x00 2. "CP0BEXEV0,Capture 0 triggered by external event 0" "0,1"
bitfld.long 0x00 1. "CP0BUP,Capture 0 triggered by update event" "0,1"
bitfld.long 0x00 0. "CP0BSW,Capture 0 triggered by software" "0,1"
group.long 0x5C++0x03
line.long 0x00 "ST0CAP0TRG,SHRTIMER Slave_TIMER0 capture 0 trigger register"
bitfld.long 0x00 15. "CP0BST0CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER0" "0,1"
bitfld.long 0x00 14. "CP0BST0CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER0" "0,1"
bitfld.long 0x00 13. "CP0BST0NA,Capture 0 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 12. "CP0BST0A,Capture 0 triggered by ST0CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 11. "CP0BEXEV9,Capture 0 triggered by external event 9" "0,1"
bitfld.long 0x00 10. "CP0BEXEV8,Capture 0 triggered by external event 8" "0,1"
bitfld.long 0x00 9. "CP0BEXEV7,Capture 0 triggered by external event 7" "0,1"
bitfld.long 0x00 8. "CP0BEXEV6,Capture 0 triggered by external event 6" "0,1"
newline
bitfld.long 0x00 7. "CP0BEXEV5,Capture 0 triggered by external event 5" "0,1"
bitfld.long 0x00 6. "CP0BEXEV4,Capture 0 triggered by external event 4" "0,1"
bitfld.long 0x00 5. "CP0BEXEV3,Capture 0 triggered by external event 3" "0,1"
bitfld.long 0x00 4. "CP0BEXEV2,Capture 0 triggered by external event 2" "0,1"
newline
bitfld.long 0x00 3. "CP0BEXEV1,Capture 0 triggered by external event 1" "0,1"
bitfld.long 0x00 2. "CP0BEXEV0,Capture 0 triggered by external event 0" "0,1"
bitfld.long 0x00 1. "CP0BUP,Capture 0 triggered by update event" "0,1"
bitfld.long 0x00 0. "CP0BSW,Capture 0 triggered by software" "0,1"
group.long 0x60++0x03
line.long 0x00 "ST0CAP1TRG,SHRTIMER Slave_TIMER0 capture 1 trigger register"
bitfld.long 0x00 31. "CP1BST4CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER4" "0,1"
bitfld.long 0x00 30. "CP1BST4CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER4" "0,1"
bitfld.long 0x00 29. "CP1BST4NA,Capture 1 triggered by ST4CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 28. "CP1BST4A,Capture 1 triggered by ST4CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 27. "CP1BST3CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER3" "0,1"
bitfld.long 0x00 26. "CP1BST3CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER3" "0,1"
bitfld.long 0x00 25. "CP1BST3NA,Capture 1 triggered by ST3CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 24. "CP1BST3A,Capture 1 triggered by ST3CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 23. "CP1BST2CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER2" "0,1"
bitfld.long 0x00 22. "CP1BST2CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER2" "0,1"
bitfld.long 0x00 21. "CP1BST2NA,Capture 1 triggered by ST2CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 20. "CP1BST2A,Capture 1 triggered by ST2CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 19. "CP1BST1CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER1" "0,1"
bitfld.long 0x00 18. "CP1BST1CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER1" "0,1"
bitfld.long 0x00 17. "CP1BST1NA,Capture 1 triggered by ST1CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 16. "CP1BST1A,Capture 1 triggered by ST1CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 11. "CP1BEXEV9,Capture 1 triggered by external event 9" "0,1"
bitfld.long 0x00 10. "CP1BEXEV8,Capture 1 triggered by external event 8" "0,1"
bitfld.long 0x00 9. "CP1BEXEV7,Capture 1 triggered by external event 7" "0,1"
bitfld.long 0x00 8. "CP1BEXEV6,Capture 1 triggered by external event 6" "0,1"
newline
bitfld.long 0x00 7. "CP1BEXEV5,Capture 1 triggered by external event 5" "0,1"
bitfld.long 0x00 6. "CP1BEXEV4,Capture 1 triggered by external event 4" "0,1"
bitfld.long 0x00 5. "CP1BEXEV3,Capture 1 triggered by external event 3" "0,1"
bitfld.long 0x00 4. "CP1BEXEV2,Capture 1 triggered by external event 2" "0,1"
newline
bitfld.long 0x00 3. "CP1BEXEV1,Capture 1 triggered by external event 1" "0,1"
bitfld.long 0x00 2. "CP1BEXEV0,Capture 1 triggered by external event 0" "0,1"
bitfld.long 0x00 1. "CP1BUP,Capture 1 triggered by update event" "0,1"
bitfld.long 0x00 0. "CP1BSW,Capture 1 triggered by software" "0,1"
group.long 0x60++0x03
line.long 0x00 "ST0CAP1TRG,SHRTIMER Slave_TIMER0 capture 1 trigger register"
bitfld.long 0x00 15. "CP1BST0CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER0" "0,1"
bitfld.long 0x00 14. "CP1BST0CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER0" "0,1"
bitfld.long 0x00 13. "CP1BST0NA,Capture 1 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 12. "CP1BST0A,Capture 1 triggered by ST0CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 11. "CP1BEXEV9,Capture 1 triggered by external event 9" "0,1"
bitfld.long 0x00 10. "CP1BEXEV8,Capture 1 triggered by external event 8" "0,1"
bitfld.long 0x00 9. "CP1BEXEV7,Capture 1 triggered by external event 7" "0,1"
bitfld.long 0x00 8. "CP1BEXEV6,Capture 1 triggered by external event 6" "0,1"
newline
bitfld.long 0x00 7. "CP1BEXEV5,Capture 1 triggered by external event 5" "0,1"
bitfld.long 0x00 6. "CP1BEXEV4,Capture 1 triggered by external event 4" "0,1"
bitfld.long 0x00 5. "CP1BEXEV3,Capture 1 triggered by external event 3" "0,1"
bitfld.long 0x00 4. "CP1BEXEV2,Capture 1 triggered by external event 2" "0,1"
newline
bitfld.long 0x00 3. "CP1BEXEV1,Capture 1 triggered by external event 1" "0,1"
bitfld.long 0x00 2. "CP1BEXEV0,Capture 1 triggered by external event 0" "0,1"
bitfld.long 0x00 1. "CP1BUP,Capture 1 triggered by update event" "0,1"
bitfld.long 0x00 0. "CP1BSW,Capture 1 triggered by software" "0,1"
group.long 0x64++0x03
line.long 0x00 "ST0CHOCTL,SHRTIMER Slave_TIMERx channel output control register"
bitfld.long 0x00 23. "BMCH1DTI,Channel 1 dead-time insert in bunch mode" "0,1"
bitfld.long 0x00 22. "CH1CSEN,Channel 1 carrier-signal mode enable" "0,1"
bitfld.long 0x00 20.--21. "CH1FLTOS,Channel 1 Fault output state" "0,1,2,3"
bitfld.long 0x00 19. "ISO1,channel 1 output idle state" "0,1"
newline
bitfld.long 0x00 18. "BMCH1IEN,Channel 1 IDLE state enable in bunch mode" "0,1"
bitfld.long 0x00 17. "CH1P,Channel 1 output polarity" "0,1"
bitfld.long 0x00 10.--12. "DLYISCH,Delayed IDLE source and channel" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "DLYISMEN,Delayed IDLE state mode enable" "0,1"
newline
bitfld.long 0x00 8. "DTEN,Dead time enable" "0,1"
bitfld.long 0x00 7. "BMCH0DTI,Channel 0 dead-time insert in bunch mode" "0,1"
bitfld.long 0x00 6. "CH0CSEN,Channel 0 carrier-signal mode enable" "0,1"
bitfld.long 0x00 4.--5. "CH0FLTOS,Channel 0 Fault output state" "0,1,2,3"
newline
bitfld.long 0x00 3. "ISO0,Channel 0 output idle state" "0,1"
bitfld.long 0x00 2. "BMCH0IEN,Channel 0 IDLE state enable in bunch mode" "0,1"
bitfld.long 0x00 1. "CH0P,Channel 0 output polarity" "0,1"
group.long 0x68++0x03
line.long 0x00 "ST0FLTCTL,SHRTIMER Slave_TIMERx fault control register"
bitfld.long 0x00 31. "FLTENPROT,Protect fault enable" "0,1"
bitfld.long 0x00 4. "FLT4EN,Fault 4 enable" "0,1"
bitfld.long 0x00 3. "FLT3EN,Fault 3 enable" "0,1"
bitfld.long 0x00 2. "FLT2EN,Fault 2 enable" "0,1"
newline
bitfld.long 0x00 1. "FLT1EN,Fault 1 enable" "0,1"
bitfld.long 0x00 0. "FLT0EN,Fault 0 enable" "0,1"
group.long 0x7C++0x03
line.long 0x00 "ST0ACTL,SHRTIMER Slave_TIMERx additional control register"
hexmask.long.byte 0x00 25.--31. 1. "DTFCFG_15_9,Falling edge dead-time value configure"
hexmask.long.byte 0x00 9.--15. 1. "DTRCFG_15_9,Rising edge dead-time value configure"
bitfld.long 0x00 3. "CNTCKDIV_3,Counter clock division" "0,1"
tree.end
tree "SLAVE_TIMER1"
base ad:0x40017500
group.long 0x00++0x03
line.long 0x00 "ST1CTL0,SHRTIMER Slave_TIMER1 control register 0"
bitfld.long 0x00 28.--31. "UPSEL,Update event selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 27. "SHWEN,Shadow registers enable" "0,1"
bitfld.long 0x00 25.--26. "DACTRGS,Trigger source to DAC" "0,1,2,3"
bitfld.long 0x00 24. "UPBMT,Update by Master_TIMER update event" "0,1"
newline
bitfld.long 0x00 23. "UPBST4,Update by Slave_TIMER4 update event" "0,1"
bitfld.long 0x00 22. "UPBST3,Update by Slave_TIMER3 update event" "0,1"
bitfld.long 0x00 21. "UPBST2,Update by Slave_TIMER2 update event" "0,1"
bitfld.long 0x00 19. "UPBST0,Update by Slave_TIMER0 update event" "0,1"
newline
bitfld.long 0x00 18. "UPRST,Update event generated by reset event" "0,1"
bitfld.long 0x00 17. "UPREP,Update event generated by repetition event" "0,1"
bitfld.long 0x00 14.--15. "DELCMP3M,Compare 3 delayed mode" "0,1,2,3"
bitfld.long 0x00 12.--13. "DELCMP1M,Compare 1 delayed mode" "0,1,2,3"
newline
bitfld.long 0x00 11. "SYNISTRT,Synchronization input start counter" "0,1"
bitfld.long 0x00 10. "SYNIRST,Synchronization input reset counter" "0,1"
bitfld.long 0x00 6. "BLNMEN,Balanced mode enable" "0,1"
bitfld.long 0x00 5. "HALFM,Half mode" "0,1"
newline
bitfld.long 0x00 4. "CNTRSTM,Counter reset mode" "0,1"
bitfld.long 0x00 3. "CTNM,Continuous mode" "0,1"
bitfld.long 0x00 0.--2. "CNTCKDIV,Counter clock division" "0,1,2,3,4,5,6,7"
rgroup.long 0x04++0x03
line.long 0x00 "ST1INTF,SHRTIMER Slave_TIMER1 interrupt flag register"
bitfld.long 0x00 21. "CH1F,Channel 1 output flag" "0,1"
bitfld.long 0x00 20. "CH0F,Channel 0 output flag" "0,1"
bitfld.long 0x00 17. "BLNIF,Balanced IDLE flag" "0,1"
bitfld.long 0x00 16. "CBLNF,Current balanced flag" "0,1"
newline
bitfld.long 0x00 14. "DLYIIF,Delayed IDLE mode entry interrupt flag" "0,1"
bitfld.long 0x00 13. "RSTIF,Counter reset interrupt flag" "0,1"
bitfld.long 0x00 12. "CH1ONAIF,Channel 1 output inactive interrupt flag" "0,1"
bitfld.long 0x00 11. "CH1OAIF,Channel 1 output active interrupt flag" "0,1"
newline
bitfld.long 0x00 10. "CH0ONAIF,Channel 0 output inactive interrupt flag" "0,1"
bitfld.long 0x00 9. "CH0OAIF,Channel 0 output active interrupt flag" "0,1"
bitfld.long 0x00 8. "CAP1IF,Capture 1 interrupt flag" "0,1"
bitfld.long 0x00 7. "CAP0IF,Capture 0 interrupt flag" "0,1"
newline
bitfld.long 0x00 6. "UPIF,Update interrupt flag" "0,1"
bitfld.long 0x00 4. "REPIF,Repetition interrupt flag" "0,1"
bitfld.long 0x00 3. "CMP3IF,Compare 3 interrupt flag" "0,1"
bitfld.long 0x00 2. "CMP2IF,Compare 2 interrupt flag" "0,1"
newline
bitfld.long 0x00 1. "CMP1IF,Compare 1 interrupt flag" "0,1"
bitfld.long 0x00 0. "CMP0IF,Compare 0 interrupt flag" "0,1"
wgroup.long 0x08++0x03
line.long 0x00 "ST1INTC,SHRTIMER Slave_TIMER1 interrupt flag clear register"
bitfld.long 0x00 14. "DLYIIFC,Clear delayed IDLE mode entry interrupt flag" "0,1"
bitfld.long 0x00 13. "RSTIFC,Clear counter reset interrupt flag" "0,1"
bitfld.long 0x00 12. "CH1ONAIFC,Clear channel 1 output inactive interrupt flag" "0,1"
bitfld.long 0x00 11. "CH1OAIFC,Clear channel 1 output active interrupt flag" "0,1"
newline
bitfld.long 0x00 10. "CH0ONAIFC,Clear channel 0 output inactive interrupt flag" "0,1"
bitfld.long 0x00 9. "CH0OAIFC,Clear channel 0 output active interrupt flag" "0,1"
bitfld.long 0x00 8. "CAP1IFC,Clear capture 1 interrupt flag" "0,1"
bitfld.long 0x00 7. "CAP0IFC,Clear capture 0 interrupt flag" "0,1"
newline
bitfld.long 0x00 6. "UPIFC,Clear update interrupt flag" "0,1"
bitfld.long 0x00 4. "REPIFC,Clear repetition interrupt flag" "0,1"
bitfld.long 0x00 3. "CMP3IFC,Clear compare 3 interrupt flag" "0,1"
bitfld.long 0x00 2. "CMP2IFC,Clear compare 2 interrupt flag" "0,1"
newline
bitfld.long 0x00 1. "CMP1IFC,Clear compare 1 interrupt flag" "0,1"
bitfld.long 0x00 0. "CMP0IFC,Clear compare 0 interrupt flag" "0,1"
group.long 0x0C++0x03
line.long 0x00 "ST1DMAINTEN,SHRTIMER Slave_TIMER1 DMA and interrupt enable register"
bitfld.long 0x00 30. "DLYIDEN,Delayed IDLE mode entry DMA request enable" "0,1"
bitfld.long 0x00 29. "RSTDEN,Counter reset DMA request enable" "0,1"
bitfld.long 0x00 28. "CH1ONADEN,Channel 1 output inactive DMA request enable" "0,1"
bitfld.long 0x00 27. "CH1OADEN,Channel 1 output active DMA request enable" "0,1"
newline
bitfld.long 0x00 26. "CH0ONADEN,Channel 0 output inactive DMA request enable" "0,1"
bitfld.long 0x00 25. "CH0ADEN,Channel 0 output active DMA request enable" "0,1"
bitfld.long 0x00 24. "CAP1DEN,Capture 1 DMA request enable" "0,1"
bitfld.long 0x00 23. "CAP0DEN,Capture 0 DMA request enable" "0,1"
newline
bitfld.long 0x00 22. "UPDEN,Update DMA request enable" "0,1"
bitfld.long 0x00 20. "REPDEN,Repetition DMA request enable" "0,1"
bitfld.long 0x00 19. "CMP3DEN,Compare 3 DMA request enable" "0,1"
bitfld.long 0x00 18. "CMP2DEN,Compare 2 DMA request enable" "0,1"
newline
bitfld.long 0x00 17. "CMP1DEN,Compare 1 DMA request enable" "0,1"
bitfld.long 0x00 16. "CMP0DEN,Compare 0 DMA request enable" "0,1"
bitfld.long 0x00 14. "DLYIIE,Delayed IDLE mode entry interrupt enable" "0,1"
bitfld.long 0x00 13. "RSTIE,Counter reset interrupt enable" "0,1"
newline
bitfld.long 0x00 12. "CH1ONAIE,Channel 1 output inactive interrupt enable" "0,1"
bitfld.long 0x00 11. "CH1OAIE,Channel 1 output active interrupt enable" "0,1"
bitfld.long 0x00 10. "CH0ONAIE,Channel 0 output inactive interrupt enable" "0,1"
bitfld.long 0x00 9. "CH0OAIE,Channel 0 output active interrupt enable" "0,1"
newline
bitfld.long 0x00 8. "CAP1IE,Capture 1 interrupt enable" "0,1"
bitfld.long 0x00 7. "CAP0IE,Capture 0 interrupt enable" "0,1"
bitfld.long 0x00 6. "UPIE,Update interrupt enable" "0,1"
bitfld.long 0x00 4. "REPIE,Repetition interrupt enable" "0,1"
newline
bitfld.long 0x00 3. "CMP3IE,Compare 3 interrupt enable" "0,1"
bitfld.long 0x00 2. "CMP2IE,Compare 2 interrupt enable" "0,1"
bitfld.long 0x00 1. "CMP1IE,Compare 1 interrupt enable" "0,1"
bitfld.long 0x00 0. "CMP0IE,Compare 0 interrupt enable" "0,1"
group.long 0x10++0x03
line.long 0x00 "ST1CNT,SHRTIMER Slave_TIMER1 counter register"
hexmask.long.word 0x00 0.--15. 1. "CNT,The current counter value"
group.long 0x14++0x03
line.long 0x00 "ST1CAR,SHRTIMER Slave_TIMER1 counter auto reload register"
hexmask.long.word 0x00 0.--15. 1. "CARL,Counter auto reload value"
group.long 0x18++0x03
line.long 0x00 "ST1CREP,SHRTIMER Slave_TIMER1 counter repetition register"
hexmask.long.byte 0x00 0.--7. 1. "CREP,Counter repetition value"
group.long 0x1C++0x03
line.long 0x00 "ST1CMP0V,SHRTIMER Slave_TIMER1 compare 0 value register"
hexmask.long.word 0x00 0.--15. 1. "CMP0VAL,Compare 0 value"
group.long 0x20++0x03
line.long 0x00 "ST1CMP0CP,SHRTIMER Slave_TIMER1 compare 0 composite register"
hexmask.long.byte 0x00 16.--23. 1. "CREP,Counter repetition value"
hexmask.long.word 0x00 0.--15. 1. "CMP0VAL,Compare 0 value"
group.long 0x24++0x03
line.long 0x00 "ST1CMP1V,SHRTIMER Slave_TIMER1 compare 1 value register"
hexmask.long.word 0x00 0.--15. 1. "CMP1VAL,Compare 1 value"
group.long 0x28++0x03
line.long 0x00 "ST1CMP2V,SHRTIMER Slave_TIMER1 compare 2 value register"
hexmask.long.word 0x00 0.--15. 1. "CMP2VAL,Compare 2 value"
group.long 0x2C++0x03
line.long 0x00 "ST1CMP3V,SHRTIMER Slave_TIMER1 compare 3 value register"
hexmask.long.word 0x00 0.--15. 1. "CMP3VAL,Compare 3 value"
group.long 0x30++0x03
line.long 0x00 "ST1CAP0V,SHRTIMER Slave_TIMER1 capture 0 value register"
hexmask.long.word 0x00 0.--15. 1. "CAP0VAL,Capture 0 value"
group.long 0x34++0x03
line.long 0x00 "ST1CAP1V,SHRTIMER Slave_TIMER1 capture 1 value register"
hexmask.long.word 0x00 0.--15. 1. "CAP1VAL,Capture 1 value"
group.long 0x38++0x03
line.long 0x00 "ST1DTCTL,SHRTIMER Slave_TIMER1 dead-time control register"
bitfld.long 0x00 31. "DTFSVPROT,Dead-time falling edge protection for value and sign" "0,1"
bitfld.long 0x00 30. "DTFSPROT,Dead-time falling edge protection for sign" "0,1"
bitfld.long 0x00 25. "DTFS,The sign of falling edge dead-time value" "0,1"
hexmask.long.word 0x00 16.--24. 1. "DTFCFG,Falling edge dead-time value"
newline
bitfld.long 0x00 15. "DTRSVPROT,Dead-time rising edge protection for value and sign" "0,1"
bitfld.long 0x00 14. "DTRSPROT,Dead-time rising edge protection for sign" "0,1"
bitfld.long 0x00 10.--13. "DTGCKDIV,Dead time generator clock division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 9. "DTRS,The sign of falling edge dead-time value" "0,1"
newline
hexmask.long.word 0x00 0.--8. 1. "DTRCFG,Falling edge dead-time value"
group.long 0x3C++0x03
line.long 0x00 "ST1CH0SET,SHRTIMER Slave_TIMER1 channel 0 set request register"
bitfld.long 0x00 31. "CH0SUP,Update event generates channel 0" "0,1"
bitfld.long 0x00 30. "CH0SEXEV9,External event 9 generates channel 0" "0,1"
bitfld.long 0x00 29. "CH0SEXEV8,External event 8 generates channel 0" "0,1"
bitfld.long 0x00 28. "CH0SEXEV7,External event 7 generates channel 0" "0,1"
newline
bitfld.long 0x00 27. "CH0SEXEV6,External event 6 generates channel 0" "0,1"
bitfld.long 0x00 26. "CH0SEXEV5,External event 5 generates channel 0" "0,1"
bitfld.long 0x00 25. "CH0SEXEV4,External event 4 generates channel 0" "0,1"
bitfld.long 0x00 24. "CH0SEXEV3,External event 3 generates channel 0" "0,1"
newline
bitfld.long 0x00 23. "CH0SEXEV2,External event 2 generates channel 0" "0,1"
bitfld.long 0x00 22. "CH0SEXEV1,External event 1 generates channel 0" "0,1"
bitfld.long 0x00 21. "CH0SEXEV0,External event 0 generates channel 0" "0,1"
bitfld.long 0x00 20. "CH0SSTEV8,Slave_TIMER1 interconnection event 8 generates channel 0" "0,1"
newline
bitfld.long 0x00 19. "CH0SSTEV7,Slave_TIMER1 interconnection event 7 generates channel 0" "0,1"
bitfld.long 0x00 18. "CH0SSTEV6,Slave_TIMER1 interconnection event 6 generates channel 0" "0,1"
bitfld.long 0x00 17. "CH0SSTEV5,Slave_TIMER1 interconnection event 5 generates channel 0" "0,1"
bitfld.long 0x00 16. "CH0SSTEV4,Slave_TIMER1 interconnection event 4 generates channel 0" "0,1"
newline
bitfld.long 0x00 15. "CH0SSTEV3,Slave_TIMER1 interconnection event 3 generates channel 0" "0,1"
bitfld.long 0x00 14. "CH0SSTEV2,Slave_TIMER1 interconnection event 2 generates channel 0" "0,1"
bitfld.long 0x00 13. "CH0SSTEV1,Slave_TIMER1 interconnection event 1 generates channel 0" "0,1"
bitfld.long 0x00 12. "CH0SSTEV0,Slave_TIMER1 interconnection event 0 generates channel 0" "0,1"
newline
bitfld.long 0x00 11. "CH0SMTCMP3,Master_TIMER compare 3 event generates channel 0" "0,1"
bitfld.long 0x00 10. "CH0SMTCMP2,Master_TIMER compare 2 event generates channel 0" "0,1"
bitfld.long 0x00 9. "CH0SMTCMP1,Master_TIMER compare 1 event generates channel 0" "0,1"
bitfld.long 0x00 8. "CH0SMTCMP0,Master_TIMER compare 0 event generates channel 0" "0,1"
newline
bitfld.long 0x00 7. "CH0SMTPER,Master_TIMER period event generates channel 0" "0,1"
bitfld.long 0x00 6. "CH0SCMP3,Slave_TIMER1 compare 3 event generates channel 0" "0,1"
bitfld.long 0x00 5. "CH0SCMP2,Slave_TIMER1 compare 2 event generates channel 0" "0,1"
bitfld.long 0x00 4. "CH0SCMP1,Slave_TIMER1 compare 1 event generates channel 0" "0,1"
newline
bitfld.long 0x00 3. "CH0SCMP0,Slave_TIMER1 compare 0 event generates channel 0" "0,1"
bitfld.long 0x00 2. "CH0SPER,Slave_TIMER1 period event generates channel 0" "0,1"
bitfld.long 0x00 1. "CH0SRST,Slave_TIMER1 reset event generates channel 0" "0,1"
bitfld.long 0x00 0. "CH0SSEV,Software event generates channel 0" "0,1"
group.long 0x40++0x03
line.long 0x00 "ST1CH0RST,SHRTIMER Slave_TIMER1 channel 0 reset request register"
bitfld.long 0x00 31. "CH0RSUP,Update event generates channel 0" "0,1"
bitfld.long 0x00 30. "CH0RSEXEV9,External event 9 generates channel 0" "0,1"
bitfld.long 0x00 29. "CH0RSEXEV8,External event 8 generates channel 0" "0,1"
bitfld.long 0x00 28. "CH0RSEXEV7,External event 7 generates channel 0" "0,1"
newline
bitfld.long 0x00 27. "CH0RSEXEV6,External event 6 generates channel 0" "0,1"
bitfld.long 0x00 26. "CH0RSEXEV5,External event 5 generates channel 0" "0,1"
bitfld.long 0x00 25. "CH0RSEXEV4,External event 4 generates channel 0" "0,1"
bitfld.long 0x00 24. "CH0RSEXEV3,External event 3 generates channel 0" "0,1"
newline
bitfld.long 0x00 23. "CH0RSEXEV2,External event 2 generates channel 0" "0,1"
bitfld.long 0x00 22. "CH0RSEXEV1,External event 1 generates channel 0" "0,1"
bitfld.long 0x00 21. "CH0RSEXEV0,External event 0 generates channel 0" "0,1"
bitfld.long 0x00 20. "CH0RSSTEV8,Slave_TIMER1 interconnection event 8 generates channel 0" "0,1"
newline
bitfld.long 0x00 19. "CH0RSSTEV7,Slave_TIMER1 interconnection event 7 generates channel 0" "0,1"
bitfld.long 0x00 18. "CH0RSSTEV6,Slave_TIMER1 interconnection event 6 generates channel 0" "0,1"
bitfld.long 0x00 17. "CH0RSSTEV5,Slave_TIMER1 interconnection event 5 generates channel 0" "0,1"
bitfld.long 0x00 16. "CH0RSSTEV4,Slave_TIMER1 interconnection event 4 generates channel 0" "0,1"
newline
bitfld.long 0x00 15. "CH0RSSTEV3,Slave_TIMER1 interconnection event 3 generates channel 0" "0,1"
bitfld.long 0x00 14. "CH0RSSTEV2,Slave_TIMER1 interconnection event 2 generates channel 0" "0,1"
bitfld.long 0x00 13. "CH0RSSTEV1,Slave_TIMER1 interconnection event 1 generates channel 0" "0,1"
bitfld.long 0x00 12. "CH0RSSTEV0,Slave_TIMER1 interconnection event 0 generates channel 0" "0,1"
newline
bitfld.long 0x00 11. "CH0RSMTCMP3,Master_TIMER compare 3 event generates channel 0" "0,1"
bitfld.long 0x00 10. "CH0RSMTCMP2,Master_TIMER compare 2 event generates channel 0" "0,1"
bitfld.long 0x00 9. "CH0RSMTCMP1,Master_TIMER compare 1 event generates channel 0" "0,1"
bitfld.long 0x00 8. "CH0RSMTCMP0,Master_TIMER compare 0 event generates channel 0" "0,1"
newline
bitfld.long 0x00 7. "CH0RSMTPER,Master_TIMER period event generates channel 0" "0,1"
bitfld.long 0x00 6. "CH0RSCMP3,Slave_TIMER1 compare 3 event generates channel 0" "0,1"
bitfld.long 0x00 5. "CH0RSCMP2,Slave_TIMER1 compare 2 event generates channel 0" "0,1"
bitfld.long 0x00 4. "CH0RSCMP1,Slave_TIMER1 compare 1 event generates channel 0" "0,1"
newline
bitfld.long 0x00 3. "CH0RSCMP0,Slave_TIMER1 compare 0 event generates channel 0" "0,1"
bitfld.long 0x00 2. "CH0RSPER,Slave_TIMER1 period event generates channel 0" "0,1"
bitfld.long 0x00 1. "CH0RSRST,Slave_TIMER1 reset event generates channel 0" "0,1"
bitfld.long 0x00 0. "CH0RSSEV,Software event generates channel 0" "0,1"
group.long 0x44++0x03
line.long 0x00 "ST1CH1SET,SHRTIMER Slave_TIMER1 channel 1 set request register"
bitfld.long 0x00 31. "CH1SUP,Update event generates channel 1" "0,1"
bitfld.long 0x00 30. "CH1SEXEV9,External event 9 generates channel 1" "0,1"
bitfld.long 0x00 29. "CH1SEXEV8,External event 8 generates channel 1" "0,1"
bitfld.long 0x00 28. "CH1SEXEV7,External event 7 generates channel 1" "0,1"
newline
bitfld.long 0x00 27. "CH1SEXEV6,External event 6 generates channel 1" "0,1"
bitfld.long 0x00 26. "CH1SEXEV5,External event 5 generates channel 1" "0,1"
bitfld.long 0x00 25. "CH1SEXEV4,External event 4 generates channel 1" "0,1"
bitfld.long 0x00 24. "CH1SEXEV3,External event 3 generates channel 1" "0,1"
newline
bitfld.long 0x00 23. "CH1SEXEV2,External event 2 generates channel 1" "0,1"
bitfld.long 0x00 22. "CH1SEXEV1,External event 1 generates channel 1" "0,1"
bitfld.long 0x00 21. "CH1SEXEV0,External event 0 generates channel 1" "0,1"
bitfld.long 0x00 20. "CH1SSTEV8,Slave_TIMERx interconnection event 8 generates channel 1" "0,1"
newline
bitfld.long 0x00 19. "CH1SSTEV7,Slave_TIMERx interconnection event 7 generates channel 1" "0,1"
bitfld.long 0x00 18. "CH1SSTEV6,Slave_TIMERx interconnection event 6 generates channel 1" "0,1"
bitfld.long 0x00 17. "CH1SSTEV5,Slave_TIMERx interconnection event 5 generates channel 1" "0,1"
bitfld.long 0x00 16. "CH1SSTEV4,Slave_TIMERx interconnection event 4 generates channel 1" "0,1"
newline
bitfld.long 0x00 15. "CH1SSTEV3,Slave_TIMERx interconnection event 3 generates channel 1" "0,1"
bitfld.long 0x00 14. "CH1SSTEV2,Slave_TIMERx interconnection event 2 generates channel 1" "0,1"
bitfld.long 0x00 13. "CH1SSTEV1,Slave_TIMERx interconnection event 1 generates channel 1" "0,1"
bitfld.long 0x00 12. "CH1SSTEV0,Slave_TIMERx interconnection event 0 generates channel 1" "0,1"
newline
bitfld.long 0x00 11. "CH1SMTCMP3,Master_TIMER compare 3 event generates channel 1" "0,1"
bitfld.long 0x00 10. "CH1SMTCMP2,Master_TIMER compare 2 event generates channel 1" "0,1"
bitfld.long 0x00 9. "CH1SMTCMP1,Master_TIMER compare 1 event generates channel 1" "0,1"
bitfld.long 0x00 8. "CH1SMTCMP0,Master_TIMER compare 0 event generates channel 1" "0,1"
newline
bitfld.long 0x00 7. "CH1SMTPER,Master_TIMER period event generates channel 1" "0,1"
bitfld.long 0x00 6. "CH1SCMP3,Slave_TIMERx compare 3 event generates channel 1" "0,1"
bitfld.long 0x00 5. "CH1SCMP2,Slave_TIMERx compare 2 event generates channel 1" "0,1"
bitfld.long 0x00 4. "CH1SCMP1,Slave_TIMERx compare 1 event generates channel 1" "0,1"
newline
bitfld.long 0x00 3. "CH1SCMP0,Slave_TIMERx compare 0 event generates channel 1" "0,1"
bitfld.long 0x00 2. "CH1SPER,Slave_TIMERx period event generates channel 1" "0,1"
bitfld.long 0x00 1. "CH1SRST,Slave_TIMERx reset event generates channel 1" "0,1"
bitfld.long 0x00 0. "CH1SSEV,Software event generates channel 1" "0,1"
group.long 0x48++0x03
line.long 0x00 "ST1CH1RST,SHRTIMER Slave_TIMER1 channel 1 reset request register"
bitfld.long 0x00 31. "CH1RSUP,Update event generates channel 1" "0,1"
bitfld.long 0x00 30. "CH1RSEXEV9,External event 9 generates channel 1" "0,1"
bitfld.long 0x00 29. "CH1RSEXEV8,External event 8 generates channel 1" "0,1"
bitfld.long 0x00 28. "CH1RSEXEV7,External event 7 generates channel 1" "0,1"
newline
bitfld.long 0x00 27. "CH1RSEXEV6,External event 6 generates channel 1" "0,1"
bitfld.long 0x00 26. "CH1RSEXEV5,External event 5 generates channel 1" "0,1"
bitfld.long 0x00 25. "CH1RSEXEV4,External event 4 generates channel 1" "0,1"
bitfld.long 0x00 24. "CH1RSEXEV3,External event 3 generates channel 1" "0,1"
newline
bitfld.long 0x00 23. "CH1RSEXEV2,External event 2 generates channel 1" "0,1"
bitfld.long 0x00 22. "CH1RSEXEV1,External event 1 generates channel 1" "0,1"
bitfld.long 0x00 21. "CH1RSEXEV0,External event 0 generates channel 1" "0,1"
bitfld.long 0x00 20. "CH1RSSTEV8,Slave_TIMERx interconnection event 8 generates channel 1" "0,1"
newline
bitfld.long 0x00 19. "CH1RSSTEV7,Slave_TIMERx interconnection event 7 generates channel 1" "0,1"
bitfld.long 0x00 18. "CH1RSSTEV6,Slave_TIMERx interconnection event 6 generates channel 1" "0,1"
bitfld.long 0x00 17. "CH1RSSTEV5,Slave_TIMERx interconnection event 5 generates channel 1" "0,1"
bitfld.long 0x00 16. "CH1RSSTEV4,Slave_TIMERx interconnection event 4 generates channel 1" "0,1"
newline
bitfld.long 0x00 15. "CH1RSSTEV3,Slave_TIMERx interconnection event 3 generates channel 1" "0,1"
bitfld.long 0x00 14. "CH1RSSTEV2,Slave_TIMERx interconnection event 2 generates channel 1" "0,1"
bitfld.long 0x00 13. "CH1RSSTEV1,Slave_TIMERx interconnection event 1 generates channel 1" "0,1"
bitfld.long 0x00 12. "CH1RSSTEV0,Slave_TIMERx interconnection event 0 generates channel 1" "0,1"
newline
bitfld.long 0x00 11. "CH1RSMTCMP3,Master_TIMER compare 3 event generates channel 1" "0,1"
bitfld.long 0x00 10. "CH1RSMTCMP2,Master_TIMER compare 2 event generates channel 1" "0,1"
bitfld.long 0x00 9. "CH1RSMTCMP1,Master_TIMER compare 1 event generates channel 1" "0,1"
bitfld.long 0x00 8. "CH1RSMTCMP0,Master_TIMER compare 0 event generates channel 1" "0,1"
newline
bitfld.long 0x00 7. "CH1RSMTPER,Master_TIMER period event generates channel 1" "0,1"
bitfld.long 0x00 6. "CH1RSCMP3,Slave_TIMERx compare 3 event generates channel 1" "0,1"
bitfld.long 0x00 5. "CH1RSCMP2,Slave_TIMERx compare 2 event generates channel 1" "0,1"
bitfld.long 0x00 4. "CH1RSCMP1,Slave_TIMERx compare 1 event generates channel 1" "0,1"
newline
bitfld.long 0x00 3. "CH1RSCMP0,Slave_TIMERx compare 0 event generates channel 1" "0,1"
bitfld.long 0x00 2. "CH1RSPER,Slave_TIMERx period event generates channel 1" "0,1"
bitfld.long 0x00 1. "CH1RSRST,Slave_TIMERx reset event generates channel 1" "0,1"
bitfld.long 0x00 0. "CH1RSSEV,Software event generates channel 1" "0,1"
group.long 0x4C++0x03
line.long 0x00 "ST1EXEVFCFG0,SHRTIMER Slave_TIMERx external event filter configuration register 0"
bitfld.long 0x00 25.--28. "EXEV4FM,External event 4 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24. "EXEV4MEEN,External event 4 memorized enable" "0,1"
bitfld.long 0x00 19.--22. "EXEV3FM,External event 3 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 18. "EXEV3MEEN,External event 3 memorized enable" "0,1"
newline
bitfld.long 0x00 13.--16. "EXEV2FM,External event 2 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12. "EXEV2MEEN,External event 2 memorized enable" "0,1"
bitfld.long 0x00 7.--10. "EXEV1FM,External event 1 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "EXEV1MEEN,External event 1 memorized enable" "0,1"
newline
bitfld.long 0x00 1.--4. "EXEV0FM,External event 0 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "EXEV0MEEN,External event 0 memorized enable" "0,1"
group.long 0x50++0x03
line.long 0x00 "ST1EXEVFCFG1,SHRTIMER Slave_TIMERx external event filter configuration register 1"
bitfld.long 0x00 25.--28. "EXEV9FM,External event 9 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24. "EXEV9MEEN,External event 9 memorized enable" "0,1"
bitfld.long 0x00 19.--22. "EXEV8FM,External event 8 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 18. "EXEV8MEEN,External event 8 memorized enable" "0,1"
newline
bitfld.long 0x00 13.--16. "EXEV7FM,External event 7 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12. "EXEV7MEEN,External event 7 memorized enable" "0,1"
bitfld.long 0x00 7.--10. "EXEV6FM,External event 6 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "EXEV6MEEN,External event 6 memorized enable" "0,1"
newline
bitfld.long 0x00 1.--4. "EXEV5FM,External event 5 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "EXEV5MEEN,External event 5 memorized enable" "0,1"
group.long 0x54++0x03
line.long 0x00 "ST1CNTRST,SHRTIMER Slave_TIMERx counter reset register"
bitfld.long 0x00 30. "ST4CMP3RST,Slave_TIMER4 compare 3 event resets counter" "0,1"
bitfld.long 0x00 29. "ST4CMP1RST,Slave_TIMER4 compare 1 event resets counter" "0,1"
bitfld.long 0x00 28. "ST4CMP0RST,Slave_TIMER4 compare 0 event resets counter" "0,1"
bitfld.long 0x00 27. "ST3CMP3RST,Slave_TIMER3 compare 3 event resets counter" "0,1"
newline
bitfld.long 0x00 26. "ST3CMP1RST,Slave_TIMER3 compare 1 event resets counter" "0,1"
bitfld.long 0x00 25. "ST3CMP0RST,Slave_TIMER3 compare 0 event resets counter" "0,1"
bitfld.long 0x00 24. "ST2CMP3RST,Slave_TIMER2 compare 3 event resets counter" "0,1"
bitfld.long 0x00 23. "ST2CMP1RST,Slave_TIMER2 compare 1 event resets counter" "0,1"
newline
bitfld.long 0x00 22. "ST2CMP0RST,Slave_TIMER2 compare 0 event resets counter" "0,1"
bitfld.long 0x00 21. "ST0CMP3RST,Slave_TIMER0 compare 3 event resets counter" "0,1"
bitfld.long 0x00 20. "ST0CMP1RST,Slave_TIMER0 compare 1 event resets counter" "0,1"
bitfld.long 0x00 19. "ST0CMP0RST,Slave_TIMER0 compare 0 event resets counter" "0,1"
newline
bitfld.long 0x00 18. "EXEV9RST,External event 9 resets counter" "0,1"
bitfld.long 0x00 17. "EXEV8RST,External event 8 resets counter" "0,1"
bitfld.long 0x00 16. "EXEV7RST,External event 7 resets counter" "0,1"
bitfld.long 0x00 15. "EXEV6RST,External event 6 resets counter" "0,1"
newline
bitfld.long 0x00 14. "EXEV5RST,External event 5 resets counter" "0,1"
bitfld.long 0x00 13. "EXEV4RST,External event 4 resets counter" "0,1"
bitfld.long 0x00 12. "EXEV3RST,External event 3 resets counter" "0,1"
bitfld.long 0x00 11. "EXEV2RST,External event 2 resets counter" "0,1"
newline
bitfld.long 0x00 10. "EXEV1RST,External event 1 resets counter" "0,1"
bitfld.long 0x00 9. "EXEV0RST,External event 0 resets counter" "0,1"
bitfld.long 0x00 8. "MTCMP3RST,Master_TIMER compare 3 event resets counter" "0,1"
bitfld.long 0x00 7. "MTCMP2RST,Master_TIMER compare 2 event resets counter" "0,1"
newline
bitfld.long 0x00 6. "MTCMP1RST,Master_TIMER compare 1 event resets counter" "0,1"
bitfld.long 0x00 5. "MTCMP0RST,Master_TIMER compare 0 event resets counter" "0,1"
bitfld.long 0x00 4. "MTPERRST,Master_TIMER period event resets counter" "0,1"
bitfld.long 0x00 3. "CMP3RST,Slave_TIMER1 compare 3 event resets counter" "0,1"
newline
bitfld.long 0x00 2. "CMP1RST,Slave_TIMER1 compare 1 event resets counter" "0,1"
bitfld.long 0x00 1. "UPRST,Slave_TIMER1 update event resets counter" "0,1"
group.long 0x58++0x03
line.long 0x00 "ST1CSCTL,SHRTIMER Slave_TIMERx carrier-signal control register"
bitfld.long 0x00 7.--10. "CSFSTPW,First carrier-signal pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--6. "CSDTY,Carrier signal duty cycle" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--3. "CSPRD,Carrier signal period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x5C++0x03
line.long 0x00 "ST1CAP0TRG,SHRTIMER Slave_TIMERx capture 0 trigger register"
bitfld.long 0x00 31. "CP0BST4CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER4" "0,1"
bitfld.long 0x00 30. "CP0BST4CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER4" "0,1"
bitfld.long 0x00 29. "CP0BST4NA,Capture 0 triggered by ST4CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 28. "CP0BST4A,Capture 0 triggered by ST4CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 27. "CP0BST3CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER3" "0,1"
bitfld.long 0x00 26. "CP0BST3CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER3" "0,1"
bitfld.long 0x00 25. "CP0BST3NA,Capture 0 triggered by ST3CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 24. "CP0BST3A,Capture 0 triggered by ST3CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 23. "CP0BST2CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER2" "0,1"
bitfld.long 0x00 22. "CP0BST2CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER2" "0,1"
bitfld.long 0x00 21. "CP0BST2NA,Capture 0 triggered by ST2CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 20. "CP0BST2A,Capture 0 triggered by ST2CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 15. "CP0BST0CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER0" "0,1"
bitfld.long 0x00 14. "CP0BST0CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER0" "0,1"
bitfld.long 0x00 13. "CP0BST0NA,Capture 0 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 12. "CP0BST0A,Capture 0 triggered by ST0CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 11. "CP0BEXEV9,Capture 0 triggered by external event 9" "0,1"
bitfld.long 0x00 10. "CP0BEXEV8,Capture 0 triggered by external event 8" "0,1"
bitfld.long 0x00 9. "CP0BEXEV7,Capture 0 triggered by external event 7" "0,1"
bitfld.long 0x00 8. "CP0BEXEV6,Capture 0 triggered by external event 6" "0,1"
newline
bitfld.long 0x00 7. "CP0BEXEV5,Capture 0 triggered by external event 5" "0,1"
bitfld.long 0x00 6. "CP0BEXEV4,Capture 0 triggered by external event 4" "0,1"
bitfld.long 0x00 5. "CP0BEXEV3,Capture 0 triggered by external event 3" "0,1"
bitfld.long 0x00 4. "CP0BEXEV2,Capture 0 triggered by external event 2" "0,1"
newline
bitfld.long 0x00 3. "CP0BEXEV1,Capture 0 triggered by external event 1" "0,1"
bitfld.long 0x00 2. "CP0BEXEV0,Capture 0 triggered by external event 0" "0,1"
bitfld.long 0x00 1. "CP0BUP,Capture 0 triggered by update event" "0,1"
bitfld.long 0x00 0. "CP0BSW,Capture 0 triggered by software" "0,1"
group.long 0x5C++0x03
line.long 0x00 "ST1CAP0TRG,SHRTIMER Slave_TIMERx capture 0 trigger register"
bitfld.long 0x00 19. "CP0BST1CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER1" "0,1"
bitfld.long 0x00 18. "CP0BST1CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER1" "0,1"
bitfld.long 0x00 17. "CP0BST1NA,Capture 0 triggered by ST1CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 16. "CP0BST1A,Capture 0 triggered by ST1CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 11. "CP0BEXEV9,Capture 0 triggered by external event 9" "0,1"
bitfld.long 0x00 10. "CP0BEXEV8,Capture 0 triggered by external event 8" "0,1"
bitfld.long 0x00 9. "CP0BEXEV7,Capture 0 triggered by external event 7" "0,1"
bitfld.long 0x00 8. "CP0BEXEV6,Capture 0 triggered by external event 6" "0,1"
newline
bitfld.long 0x00 7. "CP0BEXEV5,Capture 0 triggered by external event 5" "0,1"
bitfld.long 0x00 6. "CP0BEXEV4,Capture 0 triggered by external event 4" "0,1"
bitfld.long 0x00 5. "CP0BEXEV3,Capture 0 triggered by external event 3" "0,1"
bitfld.long 0x00 4. "CP0BEXEV2,Capture 0 triggered by external event 2" "0,1"
newline
bitfld.long 0x00 3. "CP0BEXEV1,Capture 0 triggered by external event 1" "0,1"
bitfld.long 0x00 2. "CP0BEXEV0,Capture 0 triggered by external event 0" "0,1"
bitfld.long 0x00 1. "CP0BUP,Capture 0 triggered by update event" "0,1"
bitfld.long 0x00 0. "CP0BSW,Capture 0 triggered by software" "0,1"
group.long 0x60++0x03
line.long 0x00 "ST1CAP1TRG,SHRTIMER Slave_TIMERx capture 1 trigger register"
bitfld.long 0x00 31. "CP1BST4CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER4" "0,1"
bitfld.long 0x00 30. "CP1BST4CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER4" "0,1"
bitfld.long 0x00 29. "CP1BST4NA,Capture 1 triggered by ST4CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 28. "CP1BST4A,Capture 1 triggered by ST4CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 27. "CP1BST3CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER3" "0,1"
bitfld.long 0x00 26. "CP1BST3CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER3" "0,1"
bitfld.long 0x00 25. "CP1BST3NA,Capture 1 triggered by ST3CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 24. "CP1BST3A,Capture 1 triggered by ST3CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 23. "CP1BST2CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER2" "0,1"
bitfld.long 0x00 22. "CP1BST2CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER2" "0,1"
bitfld.long 0x00 21. "CP1BST2NA,Capture 1 triggered by ST2CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 20. "CP1BST2A,Capture 1 triggered by ST2CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 15. "CP1BST0CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER0" "0,1"
bitfld.long 0x00 14. "CP1BST0CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER0" "0,1"
bitfld.long 0x00 13. "CP1BST0NA,Capture 1 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 12. "CP1BST0A,Capture 1 triggered by ST0CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 11. "CP1BEXEV9,Capture 1 triggered by external event 9" "0,1"
bitfld.long 0x00 10. "CP1BEXEV8,Capture 1 triggered by external event 8" "0,1"
bitfld.long 0x00 9. "CP1BEXEV7,Capture 1 triggered by external event 7" "0,1"
bitfld.long 0x00 8. "CP1BEXEV6,Capture 1 triggered by external event 6" "0,1"
newline
bitfld.long 0x00 7. "CP1BEXEV5,Capture 1 triggered by external event 5" "0,1"
bitfld.long 0x00 6. "CP1BEXEV4,Capture 1 triggered by external event 4" "0,1"
bitfld.long 0x00 5. "CP1BEXEV3,Capture 1 triggered by external event 3" "0,1"
bitfld.long 0x00 4. "CP1BEXEV2,Capture 1 triggered by external event 2" "0,1"
newline
bitfld.long 0x00 3. "CP1BEXEV1,Capture 1 triggered by external event 1" "0,1"
bitfld.long 0x00 2. "CP1BEXEV0,Capture 1 triggered by external event 0" "0,1"
bitfld.long 0x00 1. "CP1BUP,Capture 1 triggered by update event" "0,1"
bitfld.long 0x00 0. "CP1BSW,Capture 1 triggered by software" "0,1"
group.long 0x60++0x03
line.long 0x00 "ST1CAP1TRG,SHRTIMER Slave_TIMERx capture 1 trigger register"
bitfld.long 0x00 19. "CP1BST1CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER1" "0,1"
bitfld.long 0x00 18. "CP1BST1CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER1" "0,1"
bitfld.long 0x00 17. "CP1BST1NA,Capture 1 triggered by ST1CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 16. "CP1BST1A,Capture 1 triggered by ST1CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 11. "CP1BEXEV9,Capture 1 triggered by external event 9" "0,1"
bitfld.long 0x00 10. "CP1BEXEV8,Capture 1 triggered by external event 8" "0,1"
bitfld.long 0x00 9. "CP1BEXEV7,Capture 1 triggered by external event 7" "0,1"
bitfld.long 0x00 8. "CP1BEXEV6,Capture 1 triggered by external event 6" "0,1"
newline
bitfld.long 0x00 7. "CP1BEXEV5,Capture 1 triggered by external event 5" "0,1"
bitfld.long 0x00 6. "CP1BEXEV4,Capture 1 triggered by external event 4" "0,1"
bitfld.long 0x00 5. "CP1BEXEV3,Capture 1 triggered by external event 3" "0,1"
bitfld.long 0x00 4. "CP1BEXEV2,Capture 1 triggered by external event 2" "0,1"
newline
bitfld.long 0x00 3. "CP1BEXEV1,Capture 1 triggered by external event 1" "0,1"
bitfld.long 0x00 2. "CP1BEXEV0,Capture 1 triggered by external event 0" "0,1"
bitfld.long 0x00 1. "CP1BUP,Capture 1 triggered by update event" "0,1"
bitfld.long 0x00 0. "CP1BSW,Capture 1 triggered by software" "0,1"
group.long 0x64++0x03
line.long 0x00 "ST1CHOCTL,SHRTIMER Slave_TIMERx channel output control register"
bitfld.long 0x00 23. "BMCH1DTI,Channel 1 dead-time insert in bunch mode" "0,1"
bitfld.long 0x00 22. "CH1CSEN,Channel 1 carrier-signal mode enable" "0,1"
bitfld.long 0x00 20.--21. "CH1FLTOS,Channel 1 Fault output state" "0,1,2,3"
bitfld.long 0x00 19. "ISO1,channel 1 output idle state" "0,1"
newline
bitfld.long 0x00 18. "BMCH1IEN,Channel 1 IDLE state enable in bunch mode" "0,1"
bitfld.long 0x00 17. "CH1P,Channel 1 output polarity" "0,1"
bitfld.long 0x00 10.--12. "DLYISCH,Delayed IDLE source and channel" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "DLYISMEN,Delayed IDLE state mode enable" "0,1"
newline
bitfld.long 0x00 8. "DTEN,Dead time enable" "0,1"
bitfld.long 0x00 7. "BMCH0DTI,Channel 0 dead-time insert in bunch mode" "0,1"
bitfld.long 0x00 6. "CH0CSEN,Channel 0 carrier-signal mode enable" "0,1"
bitfld.long 0x00 4.--5. "CH0FLTOS,Channel 0 Fault output state" "0,1,2,3"
newline
bitfld.long 0x00 3. "ISO0,Channel 0 output idle state" "0,1"
bitfld.long 0x00 2. "BMCH0IEN,Channel 0 IDLE state enable in bunch mode" "0,1"
bitfld.long 0x00 1. "CH0P,Channel 0 output polarity" "0,1"
group.long 0x68++0x03
line.long 0x00 "ST1FLTCTL,SHRTIMER Slave_TIMERx fault control register"
bitfld.long 0x00 31. "FLTENPROT,Protect fault enable" "0,1"
bitfld.long 0x00 4. "FLT4EN,Fault 4 enable" "0,1"
bitfld.long 0x00 3. "FLT3EN,Fault 3 enable" "0,1"
bitfld.long 0x00 2. "FLT2EN,Fault 2 enable" "0,1"
newline
bitfld.long 0x00 1. "FLT1EN,Fault 1 enable" "0,1"
bitfld.long 0x00 0. "FLT0EN,Fault 0 enable" "0,1"
group.long 0x7C++0x03
line.long 0x00 "ST1ACTL,SHRTIMER Slave_TIMERx additional control register"
hexmask.long.byte 0x00 25.--31. 1. "DTFCFG_15_9,Falling edge dead-time value configure"
hexmask.long.byte 0x00 9.--15. 1. "DTRCFG_15_9,Rising edge dead-time value configure"
bitfld.long 0x00 3. "CNTCKDIV_3,Counter clock division" "0,1"
tree.end
tree "SLAVE_TIMER2"
base ad:0x40017580
group.long 0x00++0x03
line.long 0x00 "ST2CTL0,SHRTIMER Slave_TIMERx control register 0"
bitfld.long 0x00 28.--31. "UPSEL,Update event selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 27. "SHWEN,Shadow registers enable" "0,1"
bitfld.long 0x00 25.--26. "DACTRGS,Trigger source to DAC" "0,1,2,3"
bitfld.long 0x00 24. "UPBMT,Update by Master_TIMER update event" "0,1"
newline
bitfld.long 0x00 23. "UPBST4,Update by Slave_TIMER4 update event" "0,1"
bitfld.long 0x00 22. "UPBST3,Update by Slave_TIMER3 update event" "0,1"
bitfld.long 0x00 20. "UPBST1,Update by Slave_TIMER1 update event" "0,1"
bitfld.long 0x00 19. "UPBST0,Update by Slave_TIMER0 update event" "0,1"
newline
bitfld.long 0x00 18. "UPRST,Update event generated by reset event" "0,1"
bitfld.long 0x00 17. "UPREP,Update event generated by repetition event" "0,1"
bitfld.long 0x00 14.--15. "DELCMP3M,Compare 3 delayed mode" "0,1,2,3"
bitfld.long 0x00 12.--13. "DELCMP1M,Compare 1 delayed mode" "0,1,2,3"
newline
bitfld.long 0x00 11. "SYNISTRT,Synchronization input start counter" "0,1"
bitfld.long 0x00 10. "SYNIRST,Synchronization input reset counter" "0,1"
bitfld.long 0x00 6. "BLNMEN,Balanced mode enable" "0,1"
bitfld.long 0x00 5. "HALFM,Half mode" "0,1"
newline
bitfld.long 0x00 4. "CNTRSTM,Counter reset mode" "0,1"
bitfld.long 0x00 3. "CTNM,Continuous mode" "0,1"
bitfld.long 0x00 0.--2. "CNTCKDIV,Counter clock division" "0,1,2,3,4,5,6,7"
rgroup.long 0x04++0x03
line.long 0x00 "ST2INTF,SHRTIMER Slave_TIMERx interrupt flag register"
bitfld.long 0x00 21. "CH1F,Channel 1 output flag" "0,1"
bitfld.long 0x00 20. "CH0F,Channel 0 output flag" "0,1"
bitfld.long 0x00 17. "BLNIF,Balanced IDLE flag" "0,1"
bitfld.long 0x00 16. "CBLNF,Current balanced flag" "0,1"
newline
bitfld.long 0x00 14. "DLYIIF,Delayed IDLE mode entry interrupt flag" "0,1"
bitfld.long 0x00 13. "RSTIF,Counter reset interrupt flag" "0,1"
bitfld.long 0x00 12. "CH1ONAIF,Channel 1 output inactive interrupt flag" "0,1"
bitfld.long 0x00 11. "CH1OAIF,Channel 1 output active interrupt flag" "0,1"
newline
bitfld.long 0x00 10. "CH0ONAIF,Channel 0 output inactive interrupt flag" "0,1"
bitfld.long 0x00 9. "CH0OAIF,Channel 0 output active interrupt flag" "0,1"
bitfld.long 0x00 8. "CAP1IF,Capture 1 interrupt flag" "0,1"
bitfld.long 0x00 7. "CAP0IF,Capture 0 interrupt flag" "0,1"
newline
bitfld.long 0x00 6. "UPIF,Update interrupt flag" "0,1"
bitfld.long 0x00 4. "REPIF,Repetition interrupt flag" "0,1"
bitfld.long 0x00 3. "CMP3IF,Compare 3 interrupt flag" "0,1"
bitfld.long 0x00 2. "CMP2IF,Compare 2 interrupt flag" "0,1"
newline
bitfld.long 0x00 1. "CMP1IF,Compare 1 interrupt flag" "0,1"
bitfld.long 0x00 0. "CMP0IF,Compare 0 interrupt flag" "0,1"
wgroup.long 0x08++0x03
line.long 0x00 "ST2INTC,SHRTIMER Slave_TIMERx interrupt flag clear register"
bitfld.long 0x00 14. "DLYIIFC,Clear delayed IDLE mode entry interrupt flag" "0,1"
bitfld.long 0x00 13. "RSTIFC,Clear counter reset interrupt flag" "0,1"
bitfld.long 0x00 12. "CH1ONAIFC,Clear channel 1 output inactive interrupt flag" "0,1"
bitfld.long 0x00 11. "CH1OAIFC,Clear channel 1 output active interrupt flag" "0,1"
newline
bitfld.long 0x00 10. "CH0ONAIFC,Clear channel 0 output inactive interrupt flag" "0,1"
bitfld.long 0x00 9. "CH0OAIFC,Clear channel 0 output active interrupt flag" "0,1"
bitfld.long 0x00 8. "CAP1IFC,Clear capture 1 interrupt flag" "0,1"
bitfld.long 0x00 7. "CAP0IFC,Clear capture 0 interrupt flag" "0,1"
newline
bitfld.long 0x00 6. "UPIFC,Clear update interrupt flag" "0,1"
bitfld.long 0x00 4. "REPIFC,Clear repetition interrupt flag" "0,1"
bitfld.long 0x00 3. "CMP3IFC,Clear compare 3 interrupt flag" "0,1"
bitfld.long 0x00 2. "CMP2IFC,Clear compare 2 interrupt flag" "0,1"
newline
bitfld.long 0x00 1. "CMP1IFC,Clear compare 1 interrupt flag" "0,1"
bitfld.long 0x00 0. "CMP0IFC,Clear compare 0 interrupt flag" "0,1"
group.long 0x0C++0x03
line.long 0x00 "ST2DMAINTEN,SHRTIMER Slave_TIMERx DMA and interrupt enable register"
bitfld.long 0x00 30. "DLYIDEN,Delayed IDLE mode entry DMA request enable" "0,1"
bitfld.long 0x00 29. "RSTDEN,Counter reset DMA request enable" "0,1"
bitfld.long 0x00 28. "CH1ONADEN,Channel 1 output inactive DMA request enable" "0,1"
bitfld.long 0x00 27. "CH1OADEN,Channel 1 output active DMA request enable" "0,1"
newline
bitfld.long 0x00 26. "CH0ONADEN,Channel 0 output inactive DMA request enable" "0,1"
bitfld.long 0x00 25. "CH0ADEN,Channel 0 output active DMA request enable" "0,1"
bitfld.long 0x00 24. "CAP1DEN,Capture 1 DMA request enable" "0,1"
bitfld.long 0x00 23. "CAP0DEN,Capture 0 DMA request enable" "0,1"
newline
bitfld.long 0x00 22. "UPDEN,Update DMA request enable" "0,1"
bitfld.long 0x00 20. "REPDEN,Repetition DMA request enable" "0,1"
bitfld.long 0x00 19. "CMP3DEN,Compare 3 DMA request enable" "0,1"
bitfld.long 0x00 18. "CMP2DEN,Compare 2 DMA request enable" "0,1"
newline
bitfld.long 0x00 17. "CMP1DEN,Compare 1 DMA request enable" "0,1"
bitfld.long 0x00 16. "CMP0DEN,Compare 0 DMA request enable" "0,1"
bitfld.long 0x00 14. "DLYIIE,Delayed IDLE mode entry interrupt enable" "0,1"
bitfld.long 0x00 13. "RSTIE,Counter reset interrupt enable" "0,1"
newline
bitfld.long 0x00 12. "CH1ONAIE,Channel 1 output inactive interrupt enable" "0,1"
bitfld.long 0x00 11. "CH1OAIE,Channel 1 output active interrupt enable" "0,1"
bitfld.long 0x00 10. "CH0ONAIE,Channel 0 output inactive interrupt enable" "0,1"
bitfld.long 0x00 9. "CH0OAIE,Channel 0 output active interrupt enable" "0,1"
newline
bitfld.long 0x00 8. "CAP1IE,Capture 1 interrupt enable" "0,1"
bitfld.long 0x00 7. "CAP0IE,Capture 0 interrupt enable" "0,1"
bitfld.long 0x00 6. "UPIE,Update interrupt enable" "0,1"
bitfld.long 0x00 4. "REPIE,Repetition interrupt enable" "0,1"
newline
bitfld.long 0x00 3. "CMP3IE,Compare 3 interrupt enable" "0,1"
bitfld.long 0x00 2. "CMP2IE,Compare 2 interrupt enable" "0,1"
bitfld.long 0x00 1. "CMP1IE,Compare 1 interrupt enable" "0,1"
bitfld.long 0x00 0. "CMP0IE,Compare 0 interrupt enable" "0,1"
group.long 0x10++0x03
line.long 0x00 "ST2CNT,SHRTIMER Slave_TIMERx counter register"
hexmask.long.word 0x00 0.--15. 1. "CNT,The current counter value"
group.long 0x14++0x03
line.long 0x00 "ST2CAR,SHRTIMER Slave_TIMER2 counter auto reload register"
hexmask.long.word 0x00 0.--15. 1. "CARL,Counter auto reload value"
group.long 0x18++0x03
line.long 0x00 "ST2CREP,SHRTIMER Slave_TIMER2 counter repetition register"
hexmask.long.byte 0x00 0.--7. 1. "CREP,Counter repetition value"
group.long 0x1C++0x03
line.long 0x00 "ST2CMP0V,SHRTIMER Slave_TIMER2 compare 0 value register"
hexmask.long.word 0x00 0.--15. 1. "CMP0VAL,Compare 0 value"
group.long 0x20++0x03
line.long 0x00 "ST2CMP0CP,SHRTIMER Slave_TIMERx compare 0 composite register"
hexmask.long.byte 0x00 16.--23. 1. "CREP,Counter repetition value"
hexmask.long.word 0x00 0.--15. 1. "CMP0VAL,Compare 0 value"
group.long 0x24++0x03
line.long 0x00 "ST2CMP1V,SHRTIMER Slave_TIMERx compare 1 value register"
hexmask.long.word 0x00 0.--15. 1. "CMP1VAL,Compare 1 value"
group.long 0x28++0x03
line.long 0x00 "ST2CMP2V,SHRTIMER Slave_TIMERx compare 2 value register"
hexmask.long.word 0x00 0.--15. 1. "CMP2VAL,Compare 2 value"
group.long 0x2C++0x03
line.long 0x00 "ST2CMP3V,SHRTIMER Slave_TIMERx compare 3 value register"
hexmask.long.word 0x00 0.--15. 1. "CMP3VAL,Compare 3 value"
group.long 0x30++0x03
line.long 0x00 "ST2CAP0V,SHRTIMER Slave_TIMERx capture 0 value register"
hexmask.long.word 0x00 0.--15. 1. "CAP0VAL,Capture 0 value"
group.long 0x34++0x03
line.long 0x00 "ST2CAP1V,SHRTIMER Slave_TIMERx capture 1 value register"
hexmask.long.word 0x00 0.--15. 1. "CAP1VAL,Capture 1 value"
group.long 0x38++0x03
line.long 0x00 "ST2DTCTL,SHRTIMER Slave_TIMERx dead-time control register"
bitfld.long 0x00 31. "DTFSVPROT,Dead-time falling edge protection for value and sign" "0,1"
bitfld.long 0x00 30. "DTFSPROT,Dead-time falling edge protection for sign" "0,1"
bitfld.long 0x00 25. "DTFS,The sign of falling edge dead-time value" "0,1"
hexmask.long.word 0x00 16.--24. 1. "DTFCFG,Falling edge dead-time value"
newline
bitfld.long 0x00 15. "DTRSVPROT,Dead-time rising edge protection for value and sign" "0,1"
bitfld.long 0x00 14. "DTRSPROT,Dead-time rising edge protection for sign" "0,1"
bitfld.long 0x00 10.--13. "DTGCKDIV,Dead time generator clock division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 9. "DTRS,The sign of falling edge dead-time value" "0,1"
newline
hexmask.long.word 0x00 0.--8. 1. "DTRCFG,Falling edge dead-time value"
group.long 0x3C++0x03
line.long 0x00 "ST2CH0SET,SHRTIMER Slave_TIMERx channel 0 set request register"
bitfld.long 0x00 31. "CH0SUP,Update event generates channel 0" "0,1"
bitfld.long 0x00 30. "CH0SEXEV9,External event 9 generates channel 0" "0,1"
bitfld.long 0x00 29. "CH0SEXEV8,External event 8 generates channel 0" "0,1"
bitfld.long 0x00 28. "CH0SEXEV7,External event 7 generates channel 0" "0,1"
newline
bitfld.long 0x00 27. "CH0SEXEV6,External event 6 generates channel 0" "0,1"
bitfld.long 0x00 26. "CH0SEXEV5,External event 5 generates channel 0" "0,1"
bitfld.long 0x00 25. "CH0SEXEV4,External event 4 generates channel 0" "0,1"
bitfld.long 0x00 24. "CH0SEXEV3,External event 3 generates channel 0" "0,1"
newline
bitfld.long 0x00 23. "CH0SEXEV2,External event 2 generates channel 0" "0,1"
bitfld.long 0x00 22. "CH0SEXEV1,External event 1 generates channel 0" "0,1"
bitfld.long 0x00 21. "CH0SEXEV0,External event 0 generates channel 0" "0,1"
bitfld.long 0x00 20. "CH0SSTEV8,Slave_TIMERx interconnection event 8 generates channel 0" "0,1"
newline
bitfld.long 0x00 19. "CH0SSTEV7,Slave_TIMER1 interconnection event 7 generates channel 0" "0,1"
bitfld.long 0x00 18. "CH0SSTEV6,Slave_TIMERx interconnection event 6 generates channel 0" "0,1"
bitfld.long 0x00 17. "CH0SSTEV5,Slave_TIMERx interconnection event 5 generates channel 0" "0,1"
bitfld.long 0x00 16. "CH0SSTEV4,Slave_TIMERx interconnection event 4 generates channel 0" "0,1"
newline
bitfld.long 0x00 15. "CH0SSTEV3,Slave_TIMERx interconnection event 3 generates channel 0" "0,1"
bitfld.long 0x00 14. "CH0SSTEV2,Slave_TIMERx interconnection event 2 generates channel 0" "0,1"
bitfld.long 0x00 13. "CH0SSTEV1,Slave_TIMERx interconnection event 1 generates channel 0" "0,1"
bitfld.long 0x00 12. "CH0SSTEV0,Slave_TIMERx interconnection event 0 generates channel 0" "0,1"
newline
bitfld.long 0x00 11. "CH0SMTCMP3,Master_TIMER compare 3 event generates channel 0" "0,1"
bitfld.long 0x00 10. "CH0SMTCMP2,Master_TIMER compare 2 event generates channel 0" "0,1"
bitfld.long 0x00 9. "CH0SMTCMP1,Master_TIMER compare 1 event generates channel 0" "0,1"
bitfld.long 0x00 8. "CH0SMTCMP0,Master_TIMER compare 0 event generates channel 0" "0,1"
newline
bitfld.long 0x00 7. "CH0SMTPER,Master_TIMER period event generates channel 0" "0,1"
bitfld.long 0x00 6. "CH0SCMP3,Slave_TIMERx compare 3 event generates channel 0" "0,1"
bitfld.long 0x00 5. "CH0SCMP2,Slave_TIMERx compare 2 event generates channel 0" "0,1"
bitfld.long 0x00 4. "CH0SCMP1,Slave_TIMERx compare 1 event generates channel 0" "0,1"
newline
bitfld.long 0x00 3. "CH0SCMP0,Slave_TIMERx compare 0 event generates channel 0" "0,1"
bitfld.long 0x00 2. "CH0SPER,Slave_TIMERx period event generates channel 0" "0,1"
bitfld.long 0x00 1. "CH0SRST,Slave_TIMERx reset event generates channel 0" "0,1"
bitfld.long 0x00 0. "CH0SSEV,Software event generates channel 0" "0,1"
group.long 0x40++0x03
line.long 0x00 "ST2CH0RST,SHRTIMER Slave_TIMERx channel 0 reset request register"
bitfld.long 0x00 31. "CH0RSUP,Update event generates channel 0" "0,1"
bitfld.long 0x00 30. "CH0RSEXEV9,External event 9 generates channel 0" "0,1"
bitfld.long 0x00 29. "CH0RSEXEV8,External event 8 generates channel 0" "0,1"
bitfld.long 0x00 28. "CH0RSEXEV7,External event 7 generates channel 0" "0,1"
newline
bitfld.long 0x00 27. "CH0RSEXEV6,External event 6 generates channel 0" "0,1"
bitfld.long 0x00 26. "CH0RSEXEV5,External event 5 generates channel 0" "0,1"
bitfld.long 0x00 25. "CH0RSEXEV4,External event 4 generates channel 0" "0,1"
bitfld.long 0x00 24. "CH0RSEXEV3,External event 3 generates channel 0" "0,1"
newline
bitfld.long 0x00 23. "CH0RSEXEV2,External event 2 generates channel 0" "0,1"
bitfld.long 0x00 22. "CH0RSEXEV1,External event 1 generates channel 0" "0,1"
bitfld.long 0x00 21. "CH0RSEXEV0,External event 0 generates channel 0" "0,1"
bitfld.long 0x00 20. "CH0RSSTEV8,Slave_TIMERx interconnection event 8 generates channel 0" "0,1"
newline
bitfld.long 0x00 19. "CH0RSSTEV7,Slave_TIMERx interconnection event 7 generates channel 0" "0,1"
bitfld.long 0x00 18. "CH0RSSTEV6,Slave_TIMERx interconnection event 6 generates channel 0" "0,1"
bitfld.long 0x00 17. "CH0RSSTEV5,Slave_TIMERx interconnection event 5 generates channel 0" "0,1"
bitfld.long 0x00 16. "CH0RSSTEV4,Slave_TIMER1 interconnection event 4 generates channel 0" "0,1"
newline
bitfld.long 0x00 15. "CH0RSSTEV3,Slave_TIMERx interconnection event 3 generates channel 0" "0,1"
bitfld.long 0x00 14. "CH0RSSTEV2,Slave_TIMERx interconnection event 2 generates channel 0" "0,1"
bitfld.long 0x00 13. "CH0RSSTEV1,Slave_TIMERx interconnection event 1 generates channel 0" "0,1"
bitfld.long 0x00 12. "CH0RSSTEV0,Slave_TIMER1 interconnection event 0 generates channel 0" "0,1"
newline
bitfld.long 0x00 11. "CH0RSMTCMP3,Master_TIMER compare 3 event generates channel 0" "0,1"
bitfld.long 0x00 10. "CH0RSMTCMP2,Master_TIMER compare 2 event generates channel 0" "0,1"
bitfld.long 0x00 9. "CH0RSMTCMP1,Master_TIMER compare 1 event generates channel 0" "0,1"
bitfld.long 0x00 8. "CH0RSMTCMP0,Master_TIMER compare 0 event generates channel 0" "0,1"
newline
bitfld.long 0x00 7. "CH0RSMTPER,Master_TIMER period event generates channel 0" "0,1"
bitfld.long 0x00 6. "CH0RSCMP3,Slave_TIMERx compare 3 event generates channel 0" "0,1"
bitfld.long 0x00 5. "CH0RSCMP2,Slave_TIMER1 compare 2 event generates channel 0" "0,1"
bitfld.long 0x00 4. "CH0RSCMP1,Slave_TIMERx compare 1 event generates channel 0" "0,1"
newline
bitfld.long 0x00 3. "CH0RSCMP0,Slave_TIMERx compare 0 event generates channel 0" "0,1"
bitfld.long 0x00 2. "CH0RSPER,Slave_TIMERx period event generates channel 0" "0,1"
bitfld.long 0x00 1. "CH0RSRST,Slave_TIMERx reset event generates channel 0" "0,1"
bitfld.long 0x00 0. "CH0RSSEV,Software event generates channel 0" "0,1"
group.long 0x44++0x03
line.long 0x00 "ST2CH1SET,SHRTIMER Slave_TIMERx channel 1 set request register"
bitfld.long 0x00 31. "CH1SUP,Update event generates channel 1" "0,1"
bitfld.long 0x00 30. "CH1SEXEV9,External event 9 generates channel 1" "0,1"
bitfld.long 0x00 29. "CH1SEXEV8,External event 8 generates channel 1" "0,1"
bitfld.long 0x00 28. "CH1SEXEV7,External event 7 generates channel 1" "0,1"
newline
bitfld.long 0x00 27. "CH1SEXEV6,External event 6 generates channel 1" "0,1"
bitfld.long 0x00 26. "CH1SEXEV5,External event 5 generates channel 1" "0,1"
bitfld.long 0x00 25. "CH1SEXEV4,External event 4 generates channel 1" "0,1"
bitfld.long 0x00 24. "CH1SEXEV3,External event 3 generates channel 1" "0,1"
newline
bitfld.long 0x00 23. "CH1SEXEV2,External event 2 generates channel 1" "0,1"
bitfld.long 0x00 22. "CH1SEXEV1,External event 1 generates channel 1" "0,1"
bitfld.long 0x00 21. "CH1SEXEV0,External event 0 generates channel 1" "0,1"
bitfld.long 0x00 20. "CH1SSTEV8,Slave_TIMERx interconnection event 8 generates channel 1" "0,1"
newline
bitfld.long 0x00 19. "CH1SSTEV7,Slave_TIMERx interconnection event 7 generates channel 1" "0,1"
bitfld.long 0x00 18. "CH1SSTEV6,Slave_TIMERx interconnection event 6 generates channel 1" "0,1"
bitfld.long 0x00 17. "CH1SSTEV5,Slave_TIMERx interconnection event 5 generates channel 1" "0,1"
bitfld.long 0x00 16. "CH1SSTEV4,Slave_TIMERx interconnection event 4 generates channel 1" "0,1"
newline
bitfld.long 0x00 15. "CH1SSTEV3,Slave_TIMERx interconnection event 3 generates channel 1" "0,1"
bitfld.long 0x00 14. "CH1SSTEV2,Slave_TIMERx interconnection event 2 generates channel 1" "0,1"
bitfld.long 0x00 13. "CH1SSTEV1,Slave_TIMERx interconnection event 1 generates channel 1" "0,1"
bitfld.long 0x00 12. "CH1SSTEV0,Slave_TIMERx interconnection event 0 generates channel 1" "0,1"
newline
bitfld.long 0x00 11. "CH1SMTCMP3,Master_TIMER compare 3 event generates channel 1" "0,1"
bitfld.long 0x00 10. "CH1SMTCMP2,Master_TIMER compare 2 event generates channel 1" "0,1"
bitfld.long 0x00 9. "CH1SMTCMP1,Master_TIMER compare 1 event generates channel 1" "0,1"
bitfld.long 0x00 8. "CH1SMTCMP0,Master_TIMER compare 0 event generates channel 1" "0,1"
newline
bitfld.long 0x00 7. "CH1SMTPER,Master_TIMER period event generates channel 1" "0,1"
bitfld.long 0x00 6. "CH1SCMP3,Slave_TIMERx compare 3 event generates channel 1" "0,1"
bitfld.long 0x00 5. "CH1SCMP2,Slave_TIMERx compare 2 event generates channel 1" "0,1"
bitfld.long 0x00 4. "CH1SCMP1,Slave_TIMERx compare 1 event generates channel 1" "0,1"
newline
bitfld.long 0x00 3. "CH1SCMP0,Slave_TIMERx compare 0 event generates channel 1" "0,1"
bitfld.long 0x00 2. "CH1SPER,Slave_TIMERx period event generates channel 1" "0,1"
bitfld.long 0x00 1. "CH1SRST,Slave_TIMERx reset event generates channel 1" "0,1"
bitfld.long 0x00 0. "CH1SSEV,Software event generates channel 1" "0,1"
group.long 0x48++0x03
line.long 0x00 "ST2CH1RST,SHRTIMER Slave_TIMERx channel 1 reset request register"
bitfld.long 0x00 31. "CH1RSUP,Update event generates channel 1" "0,1"
bitfld.long 0x00 30. "CH1RSEXEV9,External event 9 generates channel 1" "0,1"
bitfld.long 0x00 29. "CH1RSEXEV8,External event 8 generates channel 1" "0,1"
bitfld.long 0x00 28. "CH1RSEXEV7,External event 7 generates channel 1" "0,1"
newline
bitfld.long 0x00 27. "CH1RSEXEV6,External event 6 generates channel 1" "0,1"
bitfld.long 0x00 26. "CH1RSEXEV5,External event 5 generates channel 1" "0,1"
bitfld.long 0x00 25. "CH1RSEXEV4,External event 4 generates channel 1" "0,1"
bitfld.long 0x00 24. "CH1RSEXEV3,External event 3 generates channel 1" "0,1"
newline
bitfld.long 0x00 23. "CH1RSEXEV2,External event 2 generates channel 1" "0,1"
bitfld.long 0x00 22. "CH1RSEXEV1,External event 1 generates channel 1" "0,1"
bitfld.long 0x00 21. "CH1RSEXEV0,External event 0 generates channel 1" "0,1"
bitfld.long 0x00 20. "CH1RSSTEV8,Slave_TIMERx interconnection event 8 generates channel 1" "0,1"
newline
bitfld.long 0x00 19. "CH1RSSTEV7,Slave_TIMERx interconnection event 7 generates channel 1" "0,1"
bitfld.long 0x00 18. "CH1RSSTEV6,Slave_TIMERx interconnection event 6 generates channel 1" "0,1"
bitfld.long 0x00 17. "CH1RSSTEV5,Slave_TIMERx interconnection event 5 generates channel 1" "0,1"
bitfld.long 0x00 16. "CH1RSSTEV4,Slave_TIMERx interconnection event 4 generates channel 1" "0,1"
newline
bitfld.long 0x00 15. "CH1RSSTEV3,Slave_TIMERx interconnection event 3 generates channel 1" "0,1"
bitfld.long 0x00 14. "CH1RSSTEV2,Slave_TIMERx interconnection event 2 generates channel 1" "0,1"
bitfld.long 0x00 13. "CH1RSSTEV1,Slave_TIMERx interconnection event 1 generates channel 1" "0,1"
bitfld.long 0x00 12. "CH1RSSTEV0,Slave_TIMERx interconnection event 0 generates channel 1" "0,1"
newline
bitfld.long 0x00 11. "CH1RSMTCMP3,Master_TIMER compare 3 event generates channel 1" "0,1"
bitfld.long 0x00 10. "CH1RSMTCMP2,Master_TIMER compare 2 event generates channel 1" "0,1"
bitfld.long 0x00 9. "CH1RSMTCMP1,Master_TIMER compare 1 event generates channel 1" "0,1"
bitfld.long 0x00 8. "CH1RSMTCMP0,Master_TIMER compare 0 event generates channel 1" "0,1"
newline
bitfld.long 0x00 7. "CH1RSMTPER,Master_TIMER period event generates channel 1" "0,1"
bitfld.long 0x00 6. "CH1RSCMP3,Slave_TIMERx compare 3 event generates channel 1" "0,1"
bitfld.long 0x00 5. "CH1RSCMP2,Slave_TIMERx compare 2 event generates channel 1" "0,1"
bitfld.long 0x00 4. "CH1RSCMP1,Slave_TIMERx compare 1 event generates channel 1" "0,1"
newline
bitfld.long 0x00 3. "CH1RSCMP0,Slave_TIMERx compare 0 event generates channel 1" "0,1"
bitfld.long 0x00 2. "CH1RSPER,Slave_TIMERx period event generates channel 1" "0,1"
bitfld.long 0x00 1. "CH1RSRST,Slave_TIMERx reset event generates channel 1" "0,1"
bitfld.long 0x00 0. "CH1RSSEV,Software event generates channel 1" "0,1"
group.long 0x4C++0x03
line.long 0x00 "ST2EXEVFCFG0,SHRTIMER Slave_TIMERx external event filter configuration register 0"
bitfld.long 0x00 25.--28. "EXEV4FM,External event 4 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24. "EXEV4MEEN,External event 4 memorized enable" "0,1"
bitfld.long 0x00 19.--22. "EXEV3FM,External event 3 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 18. "EXEV3MEEN,External event 3 memorized enable" "0,1"
newline
bitfld.long 0x00 13.--16. "EXEV2FM,External event 2 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12. "EXEV2MEEN,External event 2 memorized enable" "0,1"
bitfld.long 0x00 7.--10. "EXEV1FM,External event 1 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "EXEV1MEEN,External event 1 memorized enable" "0,1"
newline
bitfld.long 0x00 1.--4. "EXEV0FM,External event 0 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "EXEV0MEEN,External event 0 memorized enable" "0,1"
group.long 0x50++0x03
line.long 0x00 "ST2EXEVFCFG1,SHRTIMER Slave_TIMERx external event filter configuration register 1"
bitfld.long 0x00 25.--28. "EXEV9FM,External event 9 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24. "EXEV9MEEN,External event 9 memorized enable" "0,1"
bitfld.long 0x00 19.--22. "EXEV8FM,External event 8 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 18. "EXEV8MEEN,External event 8 memorized enable" "0,1"
newline
bitfld.long 0x00 13.--16. "EXEV7FM,External event 7 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12. "EXEV7MEEN,External event 7 memorized enable" "0,1"
bitfld.long 0x00 7.--10. "EXEV6FM,External event 6 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "EXEV6MEEN,External event 6 memorized enable" "0,1"
newline
bitfld.long 0x00 1.--4. "EXEV5FM,External event 5 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "EXEV5MEEN,External event 5 memorized enable" "0,1"
group.long 0x54++0x03
line.long 0x00 "ST2CNTRST,SHRTIMER Slave_TIMERx counter reset register"
bitfld.long 0x00 30. "ST4CMP3RST,Slave_TIMER4 compare 3 event resets counter" "0,1"
bitfld.long 0x00 29. "ST4CMP1RST,Slave_TIMER4 compare 1 event resets counter" "0,1"
bitfld.long 0x00 28. "ST4CMP0RST,Slave_TIMER4 compare 0 event resets counter" "0,1"
bitfld.long 0x00 27. "ST3CMP3RST,Slave_TIMER3 compare 3 event resets counter" "0,1"
newline
bitfld.long 0x00 26. "ST3CMP1RST,Slave_TIMER3 compare 1 event resets counter" "0,1"
bitfld.long 0x00 25. "ST3CMP0RST,Slave_TIMER3 compare 0 event resets counter" "0,1"
bitfld.long 0x00 24. "ST1CMP3RST,Slave_TIMER1 compare 3 event resets counter" "0,1"
bitfld.long 0x00 23. "ST1CMP1RST,Slave_TIMER1 compare 1 event resets counter" "0,1"
newline
bitfld.long 0x00 22. "ST1CMP0RST,Slave_TIMER1 compare 0 event resets counter" "0,1"
bitfld.long 0x00 21. "ST0CMP3RST,Slave_TIMER0 compare 3 event resets counter" "0,1"
bitfld.long 0x00 20. "ST0CMP1RST,Slave_TIMER0 compare 1 event resets counter" "0,1"
bitfld.long 0x00 19. "ST0CMP0RST,Slave_TIMER0 compare 0 event resets counter" "0,1"
newline
bitfld.long 0x00 18. "EXEV9RST,External event 9 resets counter" "0,1"
bitfld.long 0x00 17. "EXEV8RST,External event 8 resets counter" "0,1"
bitfld.long 0x00 16. "EXEV7RST,External event 7 resets counter" "0,1"
bitfld.long 0x00 15. "EXEV6RST,External event 6 resets counter" "0,1"
newline
bitfld.long 0x00 14. "EXEV5RST,External event 5 resets counter" "0,1"
bitfld.long 0x00 13. "EXEV4RST,External event 4 resets counter" "0,1"
bitfld.long 0x00 12. "EXEV3RST,External event 3 resets counter" "0,1"
bitfld.long 0x00 11. "EXEV2RST,External event 2 resets counter" "0,1"
newline
bitfld.long 0x00 10. "EXEV1RST,External event 1 resets counter" "0,1"
bitfld.long 0x00 9. "EXEV0RST,External event 0 resets counter" "0,1"
bitfld.long 0x00 8. "MTCMP3RST,Master_TIMER compare 3 event resets counter" "0,1"
bitfld.long 0x00 7. "MTCMP2RST,Master_TIMER compare 2 event resets counter" "0,1"
newline
bitfld.long 0x00 6. "MTCMP1RST,Master_TIMER compare 1 event resets counter" "0,1"
bitfld.long 0x00 5. "MTCMP0RST,Master_TIMER compare 0 event resets counter" "0,1"
bitfld.long 0x00 4. "MTPERRST,Master_TIMER period event resets counter" "0,1"
bitfld.long 0x00 3. "CMP3RST,Slave_TIMER2 compare 3 event resets counter" "0,1"
newline
bitfld.long 0x00 2. "CMP1RST,Slave_TIMER2 compare 1 event resets counter" "0,1"
bitfld.long 0x00 1. "UPRST,Slave_TIMER2 update event resets counter" "0,1"
group.long 0x58++0x03
line.long 0x00 "ST2CSCTL,SHRTIMER Slave_TIMERx carrier-signal control register"
bitfld.long 0x00 7.--10. "CSFSTPW,First carrier-signal pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--6. "CSDTY,Carrier signal duty cycle" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--3. "CSPRD,Carrier signal period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x5C++0x03
line.long 0x00 "ST2CAP0TRG,SHRTIMER Slave_TIMERx capture 0 trigger register"
bitfld.long 0x00 31. "CP0BST4CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER4" "0,1"
bitfld.long 0x00 30. "CP0BST4CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER4" "0,1"
bitfld.long 0x00 29. "CP0BST4NA,Capture 0 triggered by ST4CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 28. "CP0BST4A,Capture 0 triggered by ST4CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 27. "CP0BST3CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER3" "0,1"
bitfld.long 0x00 26. "CP0BST3CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER3" "0,1"
bitfld.long 0x00 25. "CP0BST3NA,Capture 0 triggered by ST3CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 24. "CP0BST3A,Capture 0 triggered by ST3CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 19. "CP0BST1CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER1" "0,1"
bitfld.long 0x00 18. "CP0BST1CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER1" "0,1"
bitfld.long 0x00 17. "CP0BST1NA,Capture 0 triggered by ST2CH1_O output active to inactive transition" "0,1"
bitfld.long 0x00 16. "CP0BST1A,Capture 0 triggered by ST2CH1_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 15. "CP0BST0CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER0" "0,1"
bitfld.long 0x00 14. "CP0BST0CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER0" "0,1"
bitfld.long 0x00 13. "CP0BST0NA,Capture 0 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 12. "CP0BST0A,Capture 0 triggered by ST0CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 11. "CP0BEXEV9,Capture 0 triggered by external event 9" "0,1"
bitfld.long 0x00 10. "CP0BEXEV8,Capture 0 triggered by external event 8" "0,1"
bitfld.long 0x00 9. "CP0BEXEV7,Capture 0 triggered by external event 7" "0,1"
bitfld.long 0x00 8. "CP0BEXEV6,Capture 0 triggered by external event 6" "0,1"
newline
bitfld.long 0x00 7. "CP0BEXEV5,Capture 0 triggered by external event 5" "0,1"
bitfld.long 0x00 6. "CP0BEXEV4,Capture 0 triggered by external event 4" "0,1"
bitfld.long 0x00 5. "CP0BEXEV3,Capture 0 triggered by external event 3" "0,1"
bitfld.long 0x00 4. "CP0BEXEV2,Capture 0 triggered by external event 2" "0,1"
newline
bitfld.long 0x00 3. "CP0BEXEV1,Capture 0 triggered by external event 1" "0,1"
bitfld.long 0x00 2. "CP0BEXEV0,Capture 0 triggered by external event 0" "0,1"
bitfld.long 0x00 1. "CP0BUP,Capture 0 triggered by update event" "0,1"
bitfld.long 0x00 0. "CP0BSW,Capture 0 triggered by software" "0,1"
group.long 0x5C++0x03
line.long 0x00 "ST2CAP0TRG,SHRTIMER Slave_TIMERx capture 0 trigger register"
bitfld.long 0x00 23. "CP0BST2CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER2" "0,1"
bitfld.long 0x00 22. "CP0BST2CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER2" "0,1"
bitfld.long 0x00 21. "CP0BST2NA,Capture 0 triggered by ST2CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 20. "CP0BST2A,Capture 0 triggered by ST2CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 11. "CP0BEXEV9,Capture 0 triggered by external event 9" "0,1"
bitfld.long 0x00 10. "CP0BEXEV8,Capture 0 triggered by external event 8" "0,1"
bitfld.long 0x00 9. "CP0BEXEV7,Capture 0 triggered by external event 7" "0,1"
bitfld.long 0x00 8. "CP0BEXEV6,Capture 0 triggered by external event 6" "0,1"
newline
bitfld.long 0x00 7. "CP0BEXEV5,Capture 0 triggered by external event 5" "0,1"
bitfld.long 0x00 6. "CP0BEXEV4,Capture 0 triggered by external event 4" "0,1"
bitfld.long 0x00 5. "CP0BEXEV3,Capture 0 triggered by external event 3" "0,1"
bitfld.long 0x00 4. "CP0BEXEV2,Capture 0 triggered by external event 2" "0,1"
newline
bitfld.long 0x00 3. "CP0BEXEV1,Capture 0 triggered by external event 1" "0,1"
bitfld.long 0x00 2. "CP0BEXEV0,Capture 0 triggered by external event 0" "0,1"
bitfld.long 0x00 1. "CP0BUP,Capture 0 triggered by update event" "0,1"
bitfld.long 0x00 0. "CP0BSW,Capture 0 triggered by software" "0,1"
group.long 0x60++0x03
line.long 0x00 "ST2CAP1TRG,SHRTIMER Slave_TIMERx capture 1 trigger register"
bitfld.long 0x00 31. "CP1BST4CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER4" "0,1"
bitfld.long 0x00 30. "CP1BST4CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER4" "0,1"
bitfld.long 0x00 29. "CP1BST4NA,Capture 1 triggered by ST4CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 28. "CP1BST4A,Capture 1 triggered by ST4CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 27. "CP1BST3CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER3" "0,1"
bitfld.long 0x00 26. "CP1BST3CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER3" "0,1"
bitfld.long 0x00 25. "CP1BST3NA,Capture 1 triggered by ST3CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 24. "CP1BST3A,Capture 1 triggered by ST3CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 19. "CP1BST1CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER1" "0,1"
bitfld.long 0x00 18. "CP1BST1CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER1" "0,1"
bitfld.long 0x00 17. "CP1BST1NA,Capture 1 triggered by ST2CH1_O output active to inactive transition" "0,1"
bitfld.long 0x00 16. "CP1BST1A,Capture 1 triggered by ST2CH1_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 15. "CP1BST0CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER0" "0,1"
bitfld.long 0x00 14. "CP1BST0CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER0" "0,1"
bitfld.long 0x00 13. "CP1BST0NA,Capture 1 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 12. "CP1BST0A,Capture 1 triggered by ST0CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 11. "CP1BEXEV9,Capture 1 triggered by external event 9" "0,1"
bitfld.long 0x00 10. "CP1BEXEV8,Capture 1 triggered by external event 8" "0,1"
bitfld.long 0x00 9. "CP1BEXEV7,Capture 1 triggered by external event 7" "0,1"
bitfld.long 0x00 8. "CP1BEXEV6,Capture 1 triggered by external event 6" "0,1"
newline
bitfld.long 0x00 7. "CP1BEXEV5,Capture 1 triggered by external event 5" "0,1"
bitfld.long 0x00 6. "CP1BEXEV4,Capture 1 triggered by external event 4" "0,1"
bitfld.long 0x00 5. "CP1BEXEV3,Capture 1 triggered by external event 3" "0,1"
bitfld.long 0x00 4. "CP1BEXEV2,Capture 1 triggered by external event 2" "0,1"
newline
bitfld.long 0x00 3. "CP1BEXEV1,Capture 1 triggered by external event 1" "0,1"
bitfld.long 0x00 2. "CP1BEXEV0,Capture 1 triggered by external event 0" "0,1"
bitfld.long 0x00 1. "CP1BUP,Capture 1 triggered by update event" "0,1"
bitfld.long 0x00 0. "CP1BSW,Capture 1 triggered by software" "0,1"
group.long 0x60++0x03
line.long 0x00 "ST2CAP1TRG,SHRTIMER Slave_TIMERx capture 1 trigger register"
bitfld.long 0x00 23. "CP1BST2CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER2" "0,1"
bitfld.long 0x00 22. "CP1BST2CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER2" "0,1"
bitfld.long 0x00 21. "CP1BST2NA,Capture 1 triggered by ST2CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 20. "CP1BST2A,Capture 1 triggered by ST2CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 11. "CP1BEXEV9,Capture 1 triggered by external event 9" "0,1"
bitfld.long 0x00 10. "CP1BEXEV8,Capture 1 triggered by external event 8" "0,1"
bitfld.long 0x00 9. "CP1BEXEV7,Capture 1 triggered by external event 7" "0,1"
bitfld.long 0x00 8. "CP1BEXEV6,Capture 1 triggered by external event 6" "0,1"
newline
bitfld.long 0x00 7. "CP1BEXEV5,Capture 1 triggered by external event 5" "0,1"
bitfld.long 0x00 6. "CP1BEXEV4,Capture 1 triggered by external event 4" "0,1"
bitfld.long 0x00 5. "CP1BEXEV3,Capture 1 triggered by external event 3" "0,1"
bitfld.long 0x00 4. "CP1BEXEV2,Capture 1 triggered by external event 2" "0,1"
newline
bitfld.long 0x00 3. "CP1BEXEV1,Capture 1 triggered by external event 1" "0,1"
bitfld.long 0x00 2. "CP1BEXEV0,Capture 1 triggered by external event 0" "0,1"
bitfld.long 0x00 1. "CP1BUP,Capture 1 triggered by update event" "0,1"
bitfld.long 0x00 0. "CP1BSW,Capture 1 triggered by software" "0,1"
group.long 0x64++0x03
line.long 0x00 "ST2CHOCTL,SHRTIMER Slave_TIMERx channel output control register"
bitfld.long 0x00 23. "BMCH1DTI,Channel 1 dead-time insert in bunch mode" "0,1"
bitfld.long 0x00 22. "CH1CSEN,Channel 1 carrier-signal mode enable" "0,1"
bitfld.long 0x00 20.--21. "CH1FLTOS,Channel 1 Fault output state" "0,1,2,3"
bitfld.long 0x00 19. "ISO1,channel 1 output idle state" "0,1"
newline
bitfld.long 0x00 18. "BMCH1IEN,Channel 1 IDLE state enable in bunch mode" "0,1"
bitfld.long 0x00 17. "CH1P,Channel 1 output polarity" "0,1"
bitfld.long 0x00 10.--12. "DLYISCH,Delayed IDLE source and channel" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "DLYISMEN,Delayed IDLE state mode enable" "0,1"
newline
bitfld.long 0x00 8. "DTEN,Dead time enable" "0,1"
bitfld.long 0x00 7. "BMCH0DTI,Channel 0 dead-time insert in bunch mode" "0,1"
bitfld.long 0x00 6. "CH0CSEN,Channel 0 carrier-signal mode enable" "0,1"
bitfld.long 0x00 4.--5. "CH0FLTOS,Channel 0 Fault output state" "0,1,2,3"
newline
bitfld.long 0x00 3. "ISO0,Channel 0 output idle state" "0,1"
bitfld.long 0x00 2. "BMCH0IEN,Channel 0 IDLE state enable in bunch mode" "0,1"
bitfld.long 0x00 1. "CH0P,Channel 0 output polarity" "0,1"
group.long 0x68++0x03
line.long 0x00 "ST2FLTCTL,SHRTIMER Slave_TIMERx fault control register"
bitfld.long 0x00 31. "FLTENPROT,Protect fault enable" "0,1"
bitfld.long 0x00 4. "FLT4EN,Fault 4 enable" "0,1"
bitfld.long 0x00 3. "FLT3EN,Fault 3 enable" "0,1"
bitfld.long 0x00 2. "FLT2EN,Fault 2 enable" "0,1"
newline
bitfld.long 0x00 1. "FLT1EN,Fault 1 enable" "0,1"
bitfld.long 0x00 0. "FLT0EN,Fault 0 enable" "0,1"
group.long 0x7C++0x03
line.long 0x00 "ST2ACTL,SHRTIMER Slave_TIMERx additional control register"
hexmask.long.byte 0x00 25.--31. 1. "DTFCFG_15_9,Falling edge dead-time value configure"
hexmask.long.byte 0x00 9.--15. 1. "DTRCFG_15_9,Rising edge dead-time value configure"
bitfld.long 0x00 3. "CNTCKDIV_3,Counter clock division" "0,1"
tree.end
tree "SLAVE_TIMER3"
base ad:0x40017600
group.long 0x00++0x03
line.long 0x00 "ST3CTL0,SHRTIMER Slave_TIMERx control register 0"
bitfld.long 0x00 28.--31. "UPSEL,Update event selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 27. "SHWEN,Shadow registers enable" "0,1"
bitfld.long 0x00 25.--26. "DACTRGS,Trigger source to DAC" "0,1,2,3"
bitfld.long 0x00 24. "UPBMT,Update by Master_TIMER update event" "0,1"
newline
bitfld.long 0x00 23. "UPBST4,Update by Slave_TIMER4 update event" "0,1"
bitfld.long 0x00 21. "UPBST2,Update by Slave_TIMER2 update event" "0,1"
bitfld.long 0x00 20. "UPBST1,Update by Slave_TIMER1 update event" "0,1"
bitfld.long 0x00 19. "UPBST0,Update by Slave_TIMER0 update event" "0,1"
newline
bitfld.long 0x00 18. "UPRST,Update event generated by reset event" "0,1"
bitfld.long 0x00 17. "UPREP,Update event generated by repetition event" "0,1"
bitfld.long 0x00 14.--15. "DELCMP3M,Compare 3 delayed mode" "0,1,2,3"
bitfld.long 0x00 12.--13. "DELCMP1M,Compare 1 delayed mode" "0,1,2,3"
newline
bitfld.long 0x00 11. "SYNISTRT,Synchronization input start counter" "0,1"
bitfld.long 0x00 10. "SYNIRST,Synchronization input reset counter" "0,1"
bitfld.long 0x00 6. "BLNMEN,Balanced mode enable" "0,1"
bitfld.long 0x00 5. "HALFM,Half mode" "0,1"
newline
bitfld.long 0x00 4. "CNTRSTM,Counter reset mode" "0,1"
bitfld.long 0x00 3. "CTNM,Continuous mode" "0,1"
bitfld.long 0x00 0.--2. "CNTCKDIV,Counter clock division" "0,1,2,3,4,5,6,7"
rgroup.long 0x04++0x03
line.long 0x00 "ST3INTF,SHRTIMER Slave_TIMERx interrupt flag register"
bitfld.long 0x00 21. "CH1F,Channel 1 output flag" "0,1"
bitfld.long 0x00 20. "CH0F,Channel 0 output flag" "0,1"
bitfld.long 0x00 17. "BLNIF,Balanced IDLE flag" "0,1"
bitfld.long 0x00 16. "CBLNF,Current balanced flag" "0,1"
newline
bitfld.long 0x00 14. "DLYIIF,Delayed IDLE mode entry interrupt flag" "0,1"
bitfld.long 0x00 13. "RSTIF,Counter reset interrupt flag" "0,1"
bitfld.long 0x00 12. "CH1ONAIF,Channel 1 output inactive interrupt flag" "0,1"
bitfld.long 0x00 11. "CH1OAIF,Channel 1 output active interrupt flag" "0,1"
newline
bitfld.long 0x00 10. "CH0ONAIF,Channel 0 output inactive interrupt flag" "0,1"
bitfld.long 0x00 9. "CH0OAIF,Channel 0 output active interrupt flag" "0,1"
bitfld.long 0x00 8. "CAP1IF,Capture 1 interrupt flag" "0,1"
bitfld.long 0x00 7. "CAP0IF,Capture 0 interrupt flag" "0,1"
newline
bitfld.long 0x00 6. "UPIF,Update interrupt flag" "0,1"
bitfld.long 0x00 4. "REPIF,Repetition interrupt flag" "0,1"
bitfld.long 0x00 3. "CMP3IF,Compare 3 interrupt flag" "0,1"
bitfld.long 0x00 2. "CMP2IF,Compare 2 interrupt flag" "0,1"
newline
bitfld.long 0x00 1. "CMP1IF,Compare 1 interrupt flag" "0,1"
bitfld.long 0x00 0. "CMP0IF,Compare 0 interrupt flag" "0,1"
wgroup.long 0x08++0x03
line.long 0x00 "ST3INTC,SHRTIMER Slave_TIMERx interrupt flag clear register"
bitfld.long 0x00 14. "DLYIIFC,Clear delayed IDLE mode entry interrupt flag" "0,1"
bitfld.long 0x00 13. "RSTIFC,Clear counter reset interrupt flag" "0,1"
bitfld.long 0x00 12. "CH1ONAIFC,Clear channel 1 output inactive interrupt flag" "0,1"
bitfld.long 0x00 11. "CH1OAIFC,Clear channel 1 output active interrupt flag" "0,1"
newline
bitfld.long 0x00 10. "CH0ONAIFC,Clear channel 0 output inactive interrupt flag" "0,1"
bitfld.long 0x00 9. "CH0OAIFC,Clear channel 0 output active interrupt flag" "0,1"
bitfld.long 0x00 8. "CAP1IFC,Clear capture 1 interrupt flag" "0,1"
bitfld.long 0x00 7. "CAP0IFC,Clear capture 0 interrupt flag" "0,1"
newline
bitfld.long 0x00 6. "UPIFC,Clear update interrupt flag" "0,1"
bitfld.long 0x00 4. "REPIFC,Clear repetition interrupt flag" "0,1"
bitfld.long 0x00 3. "CMP3IFC,Clear compare 3 interrupt flag" "0,1"
bitfld.long 0x00 2. "CMP2IFC,Clear compare 2 interrupt flag" "0,1"
newline
bitfld.long 0x00 1. "CMP1IFC,Clear compare 1 interrupt flag" "0,1"
bitfld.long 0x00 0. "CMP0IFC,Clear compare 0 interrupt flag" "0,1"
group.long 0x0C++0x03
line.long 0x00 "ST3DMAINTEN,SHRTIMER Slave_TIMERx DMA and interrupt enable register"
bitfld.long 0x00 30. "DLYIDEN,Delayed IDLE mode entry DMA request enable" "0,1"
bitfld.long 0x00 29. "RSTDEN,Counter reset DMA request enable" "0,1"
bitfld.long 0x00 28. "CH1ONADEN,Channel 1 output inactive DMA request enable" "0,1"
bitfld.long 0x00 27. "CH1OADEN,Channel 1 output active DMA request enable" "0,1"
newline
bitfld.long 0x00 26. "CH0ONADEN,Channel 0 output inactive DMA request enable" "0,1"
bitfld.long 0x00 25. "CH0ADEN,Channel 0 output active DMA request enable" "0,1"
bitfld.long 0x00 24. "CAP1DEN,Capture 1 DMA request enable" "0,1"
bitfld.long 0x00 23. "CAP0DEN,Capture 0 DMA request enable" "0,1"
newline
bitfld.long 0x00 22. "UPDEN,Update DMA request enable" "0,1"
bitfld.long 0x00 20. "REPDEN,Repetition DMA request enable" "0,1"
bitfld.long 0x00 19. "CMP3DEN,Compare 3 DMA request enable" "0,1"
bitfld.long 0x00 18. "CMP2DEN,Compare 2 DMA request enable" "0,1"
newline
bitfld.long 0x00 17. "CMP1DEN,Compare 1 DMA request enable" "0,1"
bitfld.long 0x00 16. "CMP0DEN,Compare 0 DMA request enable" "0,1"
bitfld.long 0x00 14. "DLYIIE,Delayed IDLE mode entry interrupt enable" "0,1"
bitfld.long 0x00 13. "RSTIE,Counter reset interrupt enable" "0,1"
newline
bitfld.long 0x00 12. "CH1ONAIE,Channel 1 output inactive interrupt enable" "0,1"
bitfld.long 0x00 11. "CH1OAIE,Channel 1 output active interrupt enable" "0,1"
bitfld.long 0x00 10. "CH0ONAIE,Channel 0 output inactive interrupt enable" "0,1"
bitfld.long 0x00 9. "CH0OAIE,Channel 0 output active interrupt enable" "0,1"
newline
bitfld.long 0x00 8. "CAP1IE,Capture 1 interrupt enable" "0,1"
bitfld.long 0x00 7. "CAP0IE,Capture 0 interrupt enable" "0,1"
bitfld.long 0x00 6. "UPIE,Update interrupt enable" "0,1"
bitfld.long 0x00 4. "REPIE,Repetition interrupt enable" "0,1"
newline
bitfld.long 0x00 3. "CMP3IE,Compare 3 interrupt enable" "0,1"
bitfld.long 0x00 2. "CMP2IE,Compare 2 interrupt enable" "0,1"
bitfld.long 0x00 1. "CMP1IE,Compare 1 interrupt enable" "0,1"
bitfld.long 0x00 0. "CMP0IE,Compare 0 interrupt enable" "0,1"
group.long 0x10++0x03
line.long 0x00 "ST3CNT,SHRTIMER Slave_TIMERx counter register"
hexmask.long.word 0x00 0.--15. 1. "CNT,The current counter value"
group.long 0x14++0x03
line.long 0x00 "ST3CAR,SHRTIMER Slave_TIMER3 counter auto reload register"
hexmask.long.word 0x00 0.--15. 1. "CARL,Counter auto reload value"
group.long 0x18++0x03
line.long 0x00 "ST3CREP,SHRTIMER Slave_TIMER3 counter repetition register"
hexmask.long.byte 0x00 0.--7. 1. "CREP,Counter repetition value"
group.long 0x1C++0x03
line.long 0x00 "ST3CMP0V,SHRTIMER Slave_TIMER3 compare 0 value register"
hexmask.long.word 0x00 0.--15. 1. "CMP0VAL,Compare 0 value"
group.long 0x20++0x03
line.long 0x00 "ST3CMP0CP,SHRTIMER Slave_TIMERx compare 0 composite register"
hexmask.long.byte 0x00 16.--23. 1. "CREP,Counter repetition value"
hexmask.long.word 0x00 0.--15. 1. "CMP0VAL,Compare 0 value"
group.long 0x24++0x03
line.long 0x00 "ST3CMP1V,SHRTIMER Slave_TIMERx compare 1 value register"
hexmask.long.word 0x00 0.--15. 1. "CMP1VAL,Compare 1 value"
group.long 0x28++0x03
line.long 0x00 "ST3CMP2V,SHRTIMER Slave_TIMERx compare 2 value register"
hexmask.long.word 0x00 0.--15. 1. "CMP2VAL,Compare 2 value"
group.long 0x2C++0x03
line.long 0x00 "ST3CMP3V,SHRTIMER Slave_TIMERx compare 3 value register"
hexmask.long.word 0x00 0.--15. 1. "CMP3VAL,Compare 3 value"
group.long 0x30++0x03
line.long 0x00 "ST3CAP0V,SHRTIMER Slave_TIMERx capture 0 value register"
hexmask.long.word 0x00 0.--15. 1. "CAP0VAL,Capture 0 value"
group.long 0x34++0x03
line.long 0x00 "ST3CAP1V,SHRTIMER Slave_TIMERx capture 1 value register"
hexmask.long.word 0x00 0.--15. 1. "CAP1VAL,Capture 1 value"
group.long 0x38++0x03
line.long 0x00 "ST3DTCTL,SHRTIMER Slave_TIMERx dead-time control register"
bitfld.long 0x00 31. "DTFSVPROT,Dead-time falling edge protection for value and sign" "0,1"
bitfld.long 0x00 30. "DTFSPROT,Dead-time falling edge protection for sign" "0,1"
bitfld.long 0x00 25. "DTFS,The sign of falling edge dead-time value" "0,1"
hexmask.long.word 0x00 16.--24. 1. "DTFCFG,Falling edge dead-time value"
newline
bitfld.long 0x00 15. "DTRSVPROT,Dead-time rising edge protection for value and sign" "0,1"
bitfld.long 0x00 14. "DTRSPROT,Dead-time rising edge protection for sign" "0,1"
bitfld.long 0x00 10.--13. "DTGCKDIV,Dead time generator clock division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 9. "DTRS,The sign of falling edge dead-time value" "0,1"
newline
hexmask.long.word 0x00 0.--8. 1. "DTRCFG,Falling edge dead-time value"
group.long 0x3C++0x03
line.long 0x00 "ST3CH0SET,SHRTIMER Slave_TIMERx channel 0 set request register"
bitfld.long 0x00 31. "CH0SUP,Update event generates channel 0" "0,1"
bitfld.long 0x00 30. "CH0SEXEV9,External event 9 generates channel 0" "0,1"
bitfld.long 0x00 29. "CH0SEXEV8,External event 8 generates channel 0" "0,1"
bitfld.long 0x00 28. "CH0SEXEV7,External event 7 generates channel 0" "0,1"
newline
bitfld.long 0x00 27. "CH0SEXEV6,External event 6 generates channel 0" "0,1"
bitfld.long 0x00 26. "CH0SEXEV5,External event 5 generates channel 0" "0,1"
bitfld.long 0x00 25. "CH0SEXEV4,External event 4 generates channel 0" "0,1"
bitfld.long 0x00 24. "CH0SEXEV3,External event 3 generates channel 0" "0,1"
newline
bitfld.long 0x00 23. "CH0SEXEV2,External event 2 generates channel 0" "0,1"
bitfld.long 0x00 22. "CH0SEXEV1,External event 1 generates channel 0" "0,1"
bitfld.long 0x00 21. "CH0SEXEV0,External event 0 generates channel 0" "0,1"
bitfld.long 0x00 20. "CH0SSTEV8,Slave_TIMERx interconnection event 8 generates channel 0" "0,1"
newline
bitfld.long 0x00 19. "CH0SSTEV7,Slave_TIMER1 interconnection event 7 generates channel 0" "0,1"
bitfld.long 0x00 18. "CH0SSTEV6,Slave_TIMERx interconnection event 6 generates channel 0" "0,1"
bitfld.long 0x00 17. "CH0SSTEV5,Slave_TIMERx interconnection event 5 generates channel 0" "0,1"
bitfld.long 0x00 16. "CH0SSTEV4,Slave_TIMERx interconnection event 4 generates channel 0" "0,1"
newline
bitfld.long 0x00 15. "CH0SSTEV3,Slave_TIMERx interconnection event 3 generates channel 0" "0,1"
bitfld.long 0x00 14. "CH0SSTEV2,Slave_TIMERx interconnection event 2 generates channel 0" "0,1"
bitfld.long 0x00 13. "CH0SSTEV1,Slave_TIMERx interconnection event 1 generates channel 0" "0,1"
bitfld.long 0x00 12. "CH0SSTEV0,Slave_TIMERx interconnection event 0 generates channel 0" "0,1"
newline
bitfld.long 0x00 11. "CH0SMTCMP3,Master_TIMER compare 3 event generates channel 0" "0,1"
bitfld.long 0x00 10. "CH0SMTCMP2,Master_TIMER compare 2 event generates channel 0" "0,1"
bitfld.long 0x00 9. "CH0SMTCMP1,Master_TIMER compare 1 event generates channel 0" "0,1"
bitfld.long 0x00 8. "CH0SMTCMP0,Master_TIMER compare 0 event generates channel 0" "0,1"
newline
bitfld.long 0x00 7. "CH0SMTPER,Master_TIMER period event generates channel 0" "0,1"
bitfld.long 0x00 6. "CH0SCMP3,Slave_TIMERx compare 3 event generates channel 0" "0,1"
bitfld.long 0x00 5. "CH0SCMP2,Slave_TIMERx compare 2 event generates channel 0" "0,1"
bitfld.long 0x00 4. "CH0SCMP1,Slave_TIMERx compare 1 event generates channel 0" "0,1"
newline
bitfld.long 0x00 3. "CH0SCMP0,Slave_TIMERx compare 0 event generates channel 0" "0,1"
bitfld.long 0x00 2. "CH0SPER,Slave_TIMERx period event generates channel 0" "0,1"
bitfld.long 0x00 1. "CH0SRST,Slave_TIMERx reset event generates channel 0" "0,1"
bitfld.long 0x00 0. "CH0SSEV,Software event generates channel 0" "0,1"
group.long 0x40++0x03
line.long 0x00 "ST3CH0RST,SHRTIMER Slave_TIMERx channel 0 reset request register"
bitfld.long 0x00 31. "CH0RSUP,Update event generates channel 0" "0,1"
bitfld.long 0x00 30. "CH0RSEXEV9,External event 9 generates channel 0" "0,1"
bitfld.long 0x00 29. "CH0RSEXEV8,External event 8 generates channel 0" "0,1"
bitfld.long 0x00 28. "CH0RSEXEV7,External event 7 generates channel 0" "0,1"
newline
bitfld.long 0x00 27. "CH0RSEXEV6,External event 6 generates channel 0" "0,1"
bitfld.long 0x00 26. "CH0RSEXEV5,External event 5 generates channel 0" "0,1"
bitfld.long 0x00 25. "CH0RSEXEV4,External event 4 generates channel 0" "0,1"
bitfld.long 0x00 24. "CH0RSEXEV3,External event 3 generates channel 0" "0,1"
newline
bitfld.long 0x00 23. "CH0RSEXEV2,External event 2 generates channel 0" "0,1"
bitfld.long 0x00 22. "CH0RSEXEV1,External event 1 generates channel 0" "0,1"
bitfld.long 0x00 21. "CH0RSEXEV0,External event 0 generates channel 0" "0,1"
bitfld.long 0x00 20. "CH0RSSTEV8,Slave_TIMERx interconnection event 8 generates channel 0" "0,1"
newline
bitfld.long 0x00 19. "CH0RSSTEV7,Slave_TIMERx interconnection event 7 generates channel 0" "0,1"
bitfld.long 0x00 18. "CH0RSSTEV6,Slave_TIMERx interconnection event 6 generates channel 0" "0,1"
bitfld.long 0x00 17. "CH0RSSTEV5,Slave_TIMERx interconnection event 5 generates channel 0" "0,1"
bitfld.long 0x00 16. "CH0RSSTEV4,Slave_TIMER1 interconnection event 4 generates channel 0" "0,1"
newline
bitfld.long 0x00 15. "CH0RSSTEV3,Slave_TIMERx interconnection event 3 generates channel 0" "0,1"
bitfld.long 0x00 14. "CH0RSSTEV2,Slave_TIMERx interconnection event 2 generates channel 0" "0,1"
bitfld.long 0x00 13. "CH0RSSTEV1,Slave_TIMERx interconnection event 1 generates channel 0" "0,1"
bitfld.long 0x00 12. "CH0RSSTEV0,Slave_TIMER1 interconnection event 0 generates channel 0" "0,1"
newline
bitfld.long 0x00 11. "CH0RSMTCMP3,Master_TIMER compare 3 event generates channel 0" "0,1"
bitfld.long 0x00 10. "CH0RSMTCMP2,Master_TIMER compare 2 event generates channel 0" "0,1"
bitfld.long 0x00 9. "CH0RSMTCMP1,Master_TIMER compare 1 event generates channel 0" "0,1"
bitfld.long 0x00 8. "CH0RSMTCMP0,Master_TIMER compare 0 event generates channel 0" "0,1"
newline
bitfld.long 0x00 7. "CH0RSMTPER,Master_TIMER period event generates channel 0" "0,1"
bitfld.long 0x00 6. "CH0RSCMP3,Slave_TIMERx compare 3 event generates channel 0" "0,1"
bitfld.long 0x00 5. "CH0RSCMP2,Slave_TIMER1 compare 2 event generates channel 0" "0,1"
bitfld.long 0x00 4. "CH0RSCMP1,Slave_TIMERx compare 1 event generates channel 0" "0,1"
newline
bitfld.long 0x00 3. "CH0RSCMP0,Slave_TIMERx compare 0 event generates channel 0" "0,1"
bitfld.long 0x00 2. "CH0RSPER,Slave_TIMERx period event generates channel 0" "0,1"
bitfld.long 0x00 1. "CH0RSRST,Slave_TIMERx reset event generates channel 0" "0,1"
bitfld.long 0x00 0. "CH0RSSEV,Software event generates channel 0" "0,1"
group.long 0x44++0x03
line.long 0x00 "ST3CH1SET,SHRTIMER Slave_TIMERx channel 1 set request register"
bitfld.long 0x00 31. "CH1SUP,Update event generates channel 1" "0,1"
bitfld.long 0x00 30. "CH1SEXEV9,External event 9 generates channel 1" "0,1"
bitfld.long 0x00 29. "CH1SEXEV8,External event 8 generates channel 1" "0,1"
bitfld.long 0x00 28. "CH1SEXEV7,External event 7 generates channel 1" "0,1"
newline
bitfld.long 0x00 27. "CH1SEXEV6,External event 6 generates channel 1" "0,1"
bitfld.long 0x00 26. "CH1SEXEV5,External event 5 generates channel 1" "0,1"
bitfld.long 0x00 25. "CH1SEXEV4,External event 4 generates channel 1" "0,1"
bitfld.long 0x00 24. "CH1SEXEV3,External event 3 generates channel 1" "0,1"
newline
bitfld.long 0x00 23. "CH1SEXEV2,External event 2 generates channel 1" "0,1"
bitfld.long 0x00 22. "CH1SEXEV1,External event 1 generates channel 1" "0,1"
bitfld.long 0x00 21. "CH1SEXEV0,External event 0 generates channel 1" "0,1"
bitfld.long 0x00 20. "CH1SSTEV8,Slave_TIMERx interconnection event 8 generates channel 1" "0,1"
newline
bitfld.long 0x00 19. "CH1SSTEV7,Slave_TIMERx interconnection event 7 generates channel 1" "0,1"
bitfld.long 0x00 18. "CH1SSTEV6,Slave_TIMERx interconnection event 6 generates channel 1" "0,1"
bitfld.long 0x00 17. "CH1SSTEV5,Slave_TIMERx interconnection event 5 generates channel 1" "0,1"
bitfld.long 0x00 16. "CH1SSTEV4,Slave_TIMERx interconnection event 4 generates channel 1" "0,1"
newline
bitfld.long 0x00 15. "CH1SSTEV3,Slave_TIMERx interconnection event 3 generates channel 1" "0,1"
bitfld.long 0x00 14. "CH1SSTEV2,Slave_TIMERx interconnection event 2 generates channel 1" "0,1"
bitfld.long 0x00 13. "CH1SSTEV1,Slave_TIMERx interconnection event 1 generates channel 1" "0,1"
bitfld.long 0x00 12. "CH1SSTEV0,Slave_TIMERx interconnection event 0 generates channel 1" "0,1"
newline
bitfld.long 0x00 11. "CH1SMTCMP3,Master_TIMER compare 3 event generates channel 1" "0,1"
bitfld.long 0x00 10. "CH1SMTCMP2,Master_TIMER compare 2 event generates channel 1" "0,1"
bitfld.long 0x00 9. "CH1SMTCMP1,Master_TIMER compare 1 event generates channel 1" "0,1"
bitfld.long 0x00 8. "CH1SMTCMP0,Master_TIMER compare 0 event generates channel 1" "0,1"
newline
bitfld.long 0x00 7. "CH1SMTPER,Master_TIMER period event generates channel 1" "0,1"
bitfld.long 0x00 6. "CH1SCMP3,Slave_TIMERx compare 3 event generates channel 1" "0,1"
bitfld.long 0x00 5. "CH1SCMP2,Slave_TIMERx compare 2 event generates channel 1" "0,1"
bitfld.long 0x00 4. "CH1SCMP1,Slave_TIMERx compare 1 event generates channel 1" "0,1"
newline
bitfld.long 0x00 3. "CH1SCMP0,Slave_TIMERx compare 0 event generates channel 1" "0,1"
bitfld.long 0x00 2. "CH1SPER,Slave_TIMERx period event generates channel 1" "0,1"
bitfld.long 0x00 1. "CH1SRST,Slave_TIMERx reset event generates channel 1" "0,1"
bitfld.long 0x00 0. "CH1SSEV,Software event generates channel 1" "0,1"
group.long 0x48++0x03
line.long 0x00 "ST3CH1RST,SHRTIMER Slave_TIMERx channel 1 reset request register"
bitfld.long 0x00 31. "CH1RSUP,Update event generates channel 1" "0,1"
bitfld.long 0x00 30. "CH1RSEXEV9,External event 9 generates channel 1" "0,1"
bitfld.long 0x00 29. "CH1RSEXEV8,External event 8 generates channel 1" "0,1"
bitfld.long 0x00 28. "CH1RSEXEV7,External event 7 generates channel 1" "0,1"
newline
bitfld.long 0x00 27. "CH1RSEXEV6,External event 6 generates channel 1" "0,1"
bitfld.long 0x00 26. "CH1RSEXEV5,External event 5 generates channel 1" "0,1"
bitfld.long 0x00 25. "CH1RSEXEV4,External event 4 generates channel 1" "0,1"
bitfld.long 0x00 24. "CH1RSEXEV3,External event 3 generates channel 1" "0,1"
newline
bitfld.long 0x00 23. "CH1RSEXEV2,External event 2 generates channel 1" "0,1"
bitfld.long 0x00 22. "CH1RSEXEV1,External event 1 generates channel 1" "0,1"
bitfld.long 0x00 21. "CH1RSEXEV0,External event 0 generates channel 1" "0,1"
bitfld.long 0x00 20. "CH1RSSTEV8,Slave_TIMERx interconnection event 8 generates channel 1" "0,1"
newline
bitfld.long 0x00 19. "CH1RSSTEV7,Slave_TIMERx interconnection event 7 generates channel 1" "0,1"
bitfld.long 0x00 18. "CH1RSSTEV6,Slave_TIMERx interconnection event 6 generates channel 1" "0,1"
bitfld.long 0x00 17. "CH1RSSTEV5,Slave_TIMERx interconnection event 5 generates channel 1" "0,1"
bitfld.long 0x00 16. "CH1RSSTEV4,Slave_TIMERx interconnection event 4 generates channel 1" "0,1"
newline
bitfld.long 0x00 15. "CH1RSSTEV3,Slave_TIMERx interconnection event 3 generates channel 1" "0,1"
bitfld.long 0x00 14. "CH1RSSTEV2,Slave_TIMERx interconnection event 2 generates channel 1" "0,1"
bitfld.long 0x00 13. "CH1RSSTEV1,Slave_TIMERx interconnection event 1 generates channel 1" "0,1"
bitfld.long 0x00 12. "CH1RSSTEV0,Slave_TIMERx interconnection event 0 generates channel 1" "0,1"
newline
bitfld.long 0x00 11. "CH1RSMTCMP3,Master_TIMER compare 3 event generates channel 1" "0,1"
bitfld.long 0x00 10. "CH1RSMTCMP2,Master_TIMER compare 2 event generates channel 1" "0,1"
bitfld.long 0x00 9. "CH1RSMTCMP1,Master_TIMER compare 1 event generates channel 1" "0,1"
bitfld.long 0x00 8. "CH1RSMTCMP0,Master_TIMER compare 0 event generates channel 1" "0,1"
newline
bitfld.long 0x00 7. "CH1RSMTPER,Master_TIMER period event generates channel 1" "0,1"
bitfld.long 0x00 6. "CH1RSCMP3,Slave_TIMERx compare 3 event generates channel 1" "0,1"
bitfld.long 0x00 5. "CH1RSCMP2,Slave_TIMERx compare 2 event generates channel 1" "0,1"
bitfld.long 0x00 4. "CH1RSCMP1,Slave_TIMERx compare 1 event generates channel 1" "0,1"
newline
bitfld.long 0x00 3. "CH1RSCMP0,Slave_TIMERx compare 0 event generates channel 1" "0,1"
bitfld.long 0x00 2. "CH1RSPER,Slave_TIMERx period event generates channel 1" "0,1"
bitfld.long 0x00 1. "CH1RSRST,Slave_TIMERx reset event generates channel 1" "0,1"
bitfld.long 0x00 0. "CH1RSSEV,Software event generates channel 1" "0,1"
group.long 0x4C++0x03
line.long 0x00 "ST3EXEVFCFG0,SHRTIMER Slave_TIMERx external event filter configuration register 0"
bitfld.long 0x00 25.--28. "EXEV4FM,External event 4 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24. "EXEV4MEEN,External event 4 memorized enable" "0,1"
bitfld.long 0x00 19.--22. "EXEV3FM,External event 3 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 18. "EXEV3MEEN,External event 3 memorized enable" "0,1"
newline
bitfld.long 0x00 13.--16. "EXEV2FM,External event 2 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12. "EXEV2MEEN,External event 2 memorized enable" "0,1"
bitfld.long 0x00 7.--10. "EXEV1FM,External event 1 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "EXEV1MEEN,External event 1 memorized enable" "0,1"
newline
bitfld.long 0x00 1.--4. "EXEV0FM,External event 0 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "EXEV0MEEN,External event 0 memorized enable" "0,1"
group.long 0x50++0x03
line.long 0x00 "ST3EXEVFCFG1,SHRTIMER Slave_TIMERx external event filter configuration register 1"
bitfld.long 0x00 25.--28. "EXEV9FM,External event 9 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24. "EXEV9MEEN,External event 9 memorized enable" "0,1"
bitfld.long 0x00 19.--22. "EXEV8FM,External event 8 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 18. "EXEV8MEEN,External event 8 memorized enable" "0,1"
newline
bitfld.long 0x00 13.--16. "EXEV7FM,External event 7 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12. "EXEV7MEEN,External event 7 memorized enable" "0,1"
bitfld.long 0x00 7.--10. "EXEV6FM,External event 6 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "EXEV6MEEN,External event 6 memorized enable" "0,1"
newline
bitfld.long 0x00 1.--4. "EXEV5FM,External event 5 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "EXEV5MEEN,External event 5 memorized enable" "0,1"
group.long 0x54++0x03
line.long 0x00 "ST3CNTRST,SHRTIMER Slave_TIMERx counter reset register"
bitfld.long 0x00 30. "ST4CMP3RST,Slave_TIMER4 compare 3 event resets counter" "0,1"
bitfld.long 0x00 29. "ST4CMP1RST,Slave_TIMER4 compare 1 event resets counter" "0,1"
bitfld.long 0x00 28. "ST4CMP0RST,Slave_TIMER4 compare 0 event resets counter" "0,1"
bitfld.long 0x00 27. "ST2CMP3RST,Slave_TIMER2 compare 3 event resets counter" "0,1"
newline
bitfld.long 0x00 26. "ST2CMP1RST,Slave_TIMER2 compare 1 event resets counter" "0,1"
bitfld.long 0x00 25. "ST2CMP0RST,Slave_TIMER2 compare 0 event resets counter" "0,1"
bitfld.long 0x00 24. "ST1CMP3RST,Slave_TIMER1 compare 3 event resets counter" "0,1"
bitfld.long 0x00 23. "ST1CMP1RST,Slave_TIMER1 compare 1 event resets counter" "0,1"
newline
bitfld.long 0x00 22. "ST1CMP0RST,Slave_TIMER1 compare 0 event resets counter" "0,1"
bitfld.long 0x00 21. "ST0CMP3RST,Slave_TIMER0 compare 3 event resets counter" "0,1"
bitfld.long 0x00 20. "ST0CMP1RST,Slave_TIMER0 compare 1 event resets counter" "0,1"
bitfld.long 0x00 19. "ST0CMP0RST,Slave_TIMER0 compare 0 event resets counter" "0,1"
newline
bitfld.long 0x00 18. "EXEV9RST,External event 9 resets counter" "0,1"
bitfld.long 0x00 17. "EXEV8RST,External event 8 resets counter" "0,1"
bitfld.long 0x00 16. "EXEV7RST,External event 7 resets counter" "0,1"
bitfld.long 0x00 15. "EXEV6RST,External event 6 resets counter" "0,1"
newline
bitfld.long 0x00 14. "EXEV5RST,External event 5 resets counter" "0,1"
bitfld.long 0x00 13. "EXEV4RST,External event 4 resets counter" "0,1"
bitfld.long 0x00 12. "EXEV3RST,External event 3 resets counter" "0,1"
bitfld.long 0x00 11. "EXEV2RST,External event 2 resets counter" "0,1"
newline
bitfld.long 0x00 10. "EXEV1RST,External event 1 resets counter" "0,1"
bitfld.long 0x00 9. "EXEV0RST,External event 0 resets counter" "0,1"
bitfld.long 0x00 8. "MTCMP3RST,Master_TIMER compare 3 event resets counter" "0,1"
bitfld.long 0x00 7. "MTCMP2RST,Master_TIMER compare 2 event resets counter" "0,1"
newline
bitfld.long 0x00 6. "MTCMP1RST,Master_TIMER compare 1 event resets counter" "0,1"
bitfld.long 0x00 5. "MTCMP0RST,Master_TIMER compare 0 event resets counter" "0,1"
bitfld.long 0x00 4. "MTPERRST,Master_TIMER period event resets counter" "0,1"
bitfld.long 0x00 3. "CMP3RST,Slave_TIMERx compare 3 event resets counter" "0,1"
newline
bitfld.long 0x00 2. "CMP1RST,Slave_TIMERx compare 1 event resets counter" "0,1"
bitfld.long 0x00 1. "UPRST,Slave_TIMERx update event resets counter" "0,1"
group.long 0x58++0x03
line.long 0x00 "ST3CSCTL,SHRTIMER Slave_TIMERx carrier-signal control register"
bitfld.long 0x00 7.--10. "CSFSTPW,First carrier-signal pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--6. "CSDTY,Carrier signal duty cycle" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--3. "CSPRD,Carrier signal period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x5C++0x03
line.long 0x00 "ST3CAP0TRG,SHRTIMER Slave_TIMERx capture 0 trigger register"
bitfld.long 0x00 31. "CP0BST4CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER4" "0,1"
bitfld.long 0x00 30. "CP0BST4CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER4" "0,1"
bitfld.long 0x00 29. "CP0BST4NA,Capture 0 triggered by ST4CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 28. "CP0BST4A,Capture 0 triggered by ST4CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 23. "CP0BST2CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER2" "0,1"
bitfld.long 0x00 22. "CP0BST2CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER2" "0,1"
bitfld.long 0x00 21. "CP0BST2NA,Capture 0 triggered by ST2CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 20. "CP0BST2A,Capture 0 triggered by ST2CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 19. "CP0BST1CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER1" "0,1"
bitfld.long 0x00 18. "CP0BST1CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER1" "0,1"
bitfld.long 0x00 17. "CP0BST1NA,Capture 0 triggered by ST2CH1_O output active to inactive transition" "0,1"
bitfld.long 0x00 16. "CP0BST1A,Capture 0 triggered by ST2CH1_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 15. "CP0BST0CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER0" "0,1"
bitfld.long 0x00 14. "CP0BST0CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER0" "0,1"
bitfld.long 0x00 13. "CP0BST0NA,Capture 0 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 12. "CP0BST0A,Capture 0 triggered by ST0CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 11. "CP0BEXEV9,Capture 0 triggered by external event 9" "0,1"
bitfld.long 0x00 10. "CP0BEXEV8,Capture 0 triggered by external event 8" "0,1"
bitfld.long 0x00 9. "CP0BEXEV7,Capture 0 triggered by external event 7" "0,1"
bitfld.long 0x00 8. "CP0BEXEV6,Capture 0 triggered by external event 6" "0,1"
newline
bitfld.long 0x00 7. "CP0BEXEV5,Capture 0 triggered by external event 5" "0,1"
bitfld.long 0x00 6. "CP0BEXEV4,Capture 0 triggered by external event 4" "0,1"
bitfld.long 0x00 5. "CP0BEXEV3,Capture 0 triggered by external event 3" "0,1"
bitfld.long 0x00 4. "CP0BEXEV2,Capture 0 triggered by external event 2" "0,1"
newline
bitfld.long 0x00 3. "CP0BEXEV1,Capture 0 triggered by external event 1" "0,1"
bitfld.long 0x00 2. "CP0BEXEV0,Capture 0 triggered by external event 0" "0,1"
bitfld.long 0x00 1. "CP0BUP,Capture 0 triggered by update event" "0,1"
bitfld.long 0x00 0. "CP0BSW,Capture 0 triggered by software" "0,1"
group.long 0x5C++0x03
line.long 0x00 "ST3CAP0TRG,SHRTIMER Slave_TIMERx capture 0 trigger register"
bitfld.long 0x00 27. "CP0BST3CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER3" "0,1"
bitfld.long 0x00 26. "CP0BST3CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER3" "0,1"
bitfld.long 0x00 25. "CP0BST3NA,Capture 0 triggered by ST3CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 24. "CP0BST3A,Capture 0 triggered by ST3CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 11. "CP0BEXEV9,Capture 0 triggered by external event 9" "0,1"
bitfld.long 0x00 10. "CP0BEXEV8,Capture 0 triggered by external event 8" "0,1"
bitfld.long 0x00 9. "CP0BEXEV7,Capture 0 triggered by external event 7" "0,1"
bitfld.long 0x00 8. "CP0BEXEV6,Capture 0 triggered by external event 6" "0,1"
newline
bitfld.long 0x00 7. "CP0BEXEV5,Capture 0 triggered by external event 5" "0,1"
bitfld.long 0x00 6. "CP0BEXEV4,Capture 0 triggered by external event 4" "0,1"
bitfld.long 0x00 5. "CP0BEXEV3,Capture 0 triggered by external event 3" "0,1"
bitfld.long 0x00 4. "CP0BEXEV2,Capture 0 triggered by external event 2" "0,1"
newline
bitfld.long 0x00 3. "CP0BEXEV1,Capture 0 triggered by external event 1" "0,1"
bitfld.long 0x00 2. "CP0BEXEV0,Capture 0 triggered by external event 0" "0,1"
bitfld.long 0x00 1. "CP0BUP,Capture 0 triggered by update event" "0,1"
bitfld.long 0x00 0. "CP0BSW,Capture 0 triggered by software" "0,1"
group.long 0x60++0x03
line.long 0x00 "ST3CAP1TRG,SHRTIMER Slave_TIMERx capture 1 trigger register"
bitfld.long 0x00 31. "CP1BST4CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER4" "0,1"
bitfld.long 0x00 30. "CP1BST4CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER4" "0,1"
bitfld.long 0x00 29. "CP1BST4NA,Capture 1 triggered by ST4CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 28. "CP1BST4A,Capture 1 triggered by ST4CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 23. "CP1BST2CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER2" "0,1"
bitfld.long 0x00 22. "CP1BST2CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER2" "0,1"
bitfld.long 0x00 21. "CP1BST2NA,Capture 1 triggered by ST2CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 20. "CP1BST2A,Capture 1 triggered by ST2CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 19. "CP1BST1CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER1" "0,1"
bitfld.long 0x00 18. "CP1BST1CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER1" "0,1"
bitfld.long 0x00 17. "CP1BST1NA,Capture 1 triggered by ST2CH1_O output active to inactive transition" "0,1"
bitfld.long 0x00 16. "CP1BST1A,Capture 1 triggered by ST2CH1_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 15. "CP1BST0CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER0" "0,1"
bitfld.long 0x00 14. "CP1BST0CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER0" "0,1"
bitfld.long 0x00 13. "CP1BST0NA,Capture 1 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 12. "CP1BST0A,Capture 1 triggered by ST0CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 11. "CP1BEXEV9,Capture 1 triggered by external event 9" "0,1"
bitfld.long 0x00 10. "CP1BEXEV8,Capture 1 triggered by external event 8" "0,1"
bitfld.long 0x00 9. "CP1BEXEV7,Capture 1 triggered by external event 7" "0,1"
bitfld.long 0x00 8. "CP1BEXEV6,Capture 1 triggered by external event 6" "0,1"
newline
bitfld.long 0x00 7. "CP1BEXEV5,Capture 1 triggered by external event 5" "0,1"
bitfld.long 0x00 6. "CP1BEXEV4,Capture 1 triggered by external event 4" "0,1"
bitfld.long 0x00 5. "CP1BEXEV3,Capture 1 triggered by external event 3" "0,1"
bitfld.long 0x00 4. "CP1BEXEV2,Capture 1 triggered by external event 2" "0,1"
newline
bitfld.long 0x00 3. "CP1BEXEV1,Capture 1 triggered by external event 1" "0,1"
bitfld.long 0x00 2. "CP1BEXEV0,Capture 1 triggered by external event 0" "0,1"
bitfld.long 0x00 1. "CP1BUP,Capture 1 triggered by update event" "0,1"
bitfld.long 0x00 0. "CP1BSW,Capture 1 triggered by software" "0,1"
group.long 0x60++0x03
line.long 0x00 "ST3CAP1TRG,SHRTIMER Slave_TIMERx capture 1 trigger register"
bitfld.long 0x00 27. "CP1BST3CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER3" "0,1"
bitfld.long 0x00 26. "CP1BST3CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER3" "0,1"
bitfld.long 0x00 25. "CP1BST3NA,Capture 1 triggered by ST3CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 24. "CP1BST3A,Capture 1 triggered by ST3CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 11. "CP1BEXEV9,Capture 1 triggered by external event 9" "0,1"
bitfld.long 0x00 10. "CP1BEXEV8,Capture 1 triggered by external event 8" "0,1"
bitfld.long 0x00 9. "CP1BEXEV7,Capture 1 triggered by external event 7" "0,1"
bitfld.long 0x00 8. "CP1BEXEV6,Capture 1 triggered by external event 6" "0,1"
newline
bitfld.long 0x00 7. "CP1BEXEV5,Capture 1 triggered by external event 5" "0,1"
bitfld.long 0x00 6. "CP1BEXEV4,Capture 1 triggered by external event 4" "0,1"
bitfld.long 0x00 5. "CP1BEXEV3,Capture 1 triggered by external event 3" "0,1"
bitfld.long 0x00 4. "CP1BEXEV2,Capture 1 triggered by external event 2" "0,1"
newline
bitfld.long 0x00 3. "CP1BEXEV1,Capture 1 triggered by external event 1" "0,1"
bitfld.long 0x00 2. "CP1BEXEV0,Capture 1 triggered by external event 0" "0,1"
bitfld.long 0x00 1. "CP1BUP,Capture 1 triggered by update event" "0,1"
bitfld.long 0x00 0. "CP1BSW,Capture 1 triggered by software" "0,1"
group.long 0x64++0x03
line.long 0x00 "ST3CHOCTL,SHRTIMER Slave_TIMERx channel output control register"
bitfld.long 0x00 23. "BMCH1DTI,Channel 1 dead-time insert in bunch mode" "0,1"
bitfld.long 0x00 22. "CH1CSEN,Channel 1 carrier-signal mode enable" "0,1"
bitfld.long 0x00 20.--21. "CH1FLTOS,Channel 1 Fault output state" "0,1,2,3"
bitfld.long 0x00 19. "ISO1,channel 1 output idle state" "0,1"
newline
bitfld.long 0x00 18. "BMCH1IEN,Channel 1 IDLE state enable in bunch mode" "0,1"
bitfld.long 0x00 17. "CH1P,Channel 1 output polarity" "0,1"
bitfld.long 0x00 10.--12. "DLYISCH,Delayed IDLE source and channel" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "DLYISMEN,Delayed IDLE state mode enable" "0,1"
newline
bitfld.long 0x00 8. "DTEN,Dead time enable" "0,1"
bitfld.long 0x00 7. "BMCH0DTI,Channel 0 dead-time insert in bunch mode" "0,1"
bitfld.long 0x00 6. "CH0CSEN,Channel 0 carrier-signal mode enable" "0,1"
bitfld.long 0x00 4.--5. "CH0FLTOS,Channel 0 Fault output state" "0,1,2,3"
newline
bitfld.long 0x00 3. "ISO0,Channel 0 output idle state" "0,1"
bitfld.long 0x00 2. "BMCH0IEN,Channel 0 IDLE state enable in bunch mode" "0,1"
bitfld.long 0x00 1. "CH0P,Channel 0 output polarity" "0,1"
group.long 0x68++0x03
line.long 0x00 "ST3FLTCTL,SHRTIMER Slave_TIMERx fault control register"
bitfld.long 0x00 31. "FLTENPROT,Protect fault enable" "0,1"
bitfld.long 0x00 4. "FLT4EN,Fault 4 enable" "0,1"
bitfld.long 0x00 3. "FLT3EN,Fault 3 enable" "0,1"
bitfld.long 0x00 2. "FLT2EN,Fault 2 enable" "0,1"
newline
bitfld.long 0x00 1. "FLT1EN,Fault 1 enable" "0,1"
bitfld.long 0x00 0. "FLT0EN,Fault 0 enable" "0,1"
group.long 0x7C++0x03
line.long 0x00 "ST3ACTL,SHRTIMER Slave_TIMERx additional control register"
hexmask.long.byte 0x00 25.--31. 1. "DTFCFG_15_9,Falling edge dead-time value configure"
hexmask.long.byte 0x00 9.--15. 1. "DTRCFG_15_9,Rising edge dead-time value configure"
bitfld.long 0x00 3. "CNTCKDIV_3,Counter clock division" "0,1"
tree.end
tree "SLAVE_TIMER4"
base ad:0x40017680
group.long 0x00++0x03
line.long 0x00 "ST3CTL0,SHRTIMER Slave_TIMERx control register 0"
bitfld.long 0x00 28.--31. "UPSEL,Update event selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 27. "SHWEN,Shadow registers enable" "0,1"
bitfld.long 0x00 25.--26. "DACTRGS,Trigger source to DAC" "0,1,2,3"
bitfld.long 0x00 24. "UPBMT,Update by Master_TIMER update event" "0,1"
newline
bitfld.long 0x00 22. "UPBST3,Update by Slave_TIMER3 update event" "0,1"
bitfld.long 0x00 21. "UPBST2,Update by Slave_TIMER2 update event" "0,1"
bitfld.long 0x00 20. "UPBST1,Update by Slave_TIMER1 update event" "0,1"
bitfld.long 0x00 19. "UPBST0,Update by Slave_TIMER0 update event" "0,1"
newline
bitfld.long 0x00 18. "UPRST,Update event generated by reset event" "0,1"
bitfld.long 0x00 17. "UPREP,Update event generated by repetition event" "0,1"
bitfld.long 0x00 14.--15. "DELCMP3M,Compare 3 delayed mode" "0,1,2,3"
bitfld.long 0x00 12.--13. "DELCMP1M,Compare 1 delayed mode" "0,1,2,3"
newline
bitfld.long 0x00 11. "SYNISTRT,Synchronization input start counter" "0,1"
bitfld.long 0x00 10. "SYNIRST,Synchronization input reset counter" "0,1"
bitfld.long 0x00 6. "BLNMEN,Balanced mode enable" "0,1"
bitfld.long 0x00 5. "HALFM,Half mode" "0,1"
newline
bitfld.long 0x00 4. "CNTRSTM,Counter reset mode" "0,1"
bitfld.long 0x00 3. "CTNM,Continuous mode" "0,1"
bitfld.long 0x00 0.--2. "CNTCKDIV,Counter clock division" "0,1,2,3,4,5,6,7"
rgroup.long 0x04++0x03
line.long 0x00 "ST4INTF,SHRTIMER Slave_TIMERx interrupt flag register"
bitfld.long 0x00 21. "CH1F,Channel 1 output flag" "0,1"
bitfld.long 0x00 20. "CH0F,Channel 0 output flag" "0,1"
bitfld.long 0x00 17. "BLNIF,Balanced IDLE flag" "0,1"
bitfld.long 0x00 16. "CBLNF,Current balanced flag" "0,1"
newline
bitfld.long 0x00 14. "DLYIIF,Delayed IDLE mode entry interrupt flag" "0,1"
bitfld.long 0x00 13. "RSTIF,Counter reset interrupt flag" "0,1"
bitfld.long 0x00 12. "CH1ONAIF,Channel 1 output inactive interrupt flag" "0,1"
bitfld.long 0x00 11. "CH1OAIF,Channel 1 output active interrupt flag" "0,1"
newline
bitfld.long 0x00 10. "CH0ONAIF,Channel 0 output inactive interrupt flag" "0,1"
bitfld.long 0x00 9. "CH0OAIF,Channel 0 output active interrupt flag" "0,1"
bitfld.long 0x00 8. "CAP1IF,Capture 1 interrupt flag" "0,1"
bitfld.long 0x00 7. "CAP0IF,Capture 0 interrupt flag" "0,1"
newline
bitfld.long 0x00 6. "UPIF,Update interrupt flag" "0,1"
bitfld.long 0x00 4. "REPIF,Repetition interrupt flag" "0,1"
bitfld.long 0x00 3. "CMP3IF,Compare 3 interrupt flag" "0,1"
bitfld.long 0x00 2. "CMP2IF,Compare 2 interrupt flag" "0,1"
newline
bitfld.long 0x00 1. "CMP1IF,Compare 1 interrupt flag" "0,1"
bitfld.long 0x00 0. "CMP0IF,Compare 0 interrupt flag" "0,1"
wgroup.long 0x08++0x03
line.long 0x00 "ST4INTC,SHRTIMER Slave_TIMERx interrupt flag clear register"
bitfld.long 0x00 14. "DLYIIFC,Clear delayed IDLE mode entry interrupt flag" "0,1"
bitfld.long 0x00 13. "RSTIFC,Clear counter reset interrupt flag" "0,1"
bitfld.long 0x00 12. "CH1ONAIFC,Clear channel 1 output inactive interrupt flag" "0,1"
bitfld.long 0x00 11. "CH1OAIFC,Clear channel 1 output active interrupt flag" "0,1"
newline
bitfld.long 0x00 10. "CH0ONAIFC,Clear channel 0 output inactive interrupt flag" "0,1"
bitfld.long 0x00 9. "CH0OAIFC,Clear channel 0 output active interrupt flag" "0,1"
bitfld.long 0x00 8. "CAP1IFC,Clear capture 1 interrupt flag" "0,1"
bitfld.long 0x00 7. "CAP0IFC,Clear capture 0 interrupt flag" "0,1"
newline
bitfld.long 0x00 6. "UPIFC,Clear update interrupt flag" "0,1"
bitfld.long 0x00 4. "REPIFC,Clear repetition interrupt flag" "0,1"
bitfld.long 0x00 3. "CMP3IFC,Clear compare 3 interrupt flag" "0,1"
bitfld.long 0x00 2. "CMP2IFC,Clear compare 2 interrupt flag" "0,1"
newline
bitfld.long 0x00 1. "CMP1IFC,Clear compare 1 interrupt flag" "0,1"
bitfld.long 0x00 0. "CMP0IFC,Clear compare 0 interrupt flag" "0,1"
group.long 0x0C++0x03
line.long 0x00 "ST4DMAINTEN,SHRTIMER Slave_TIMERx DMA and interrupt enable register"
bitfld.long 0x00 30. "DLYIDEN,Delayed IDLE mode entry DMA request enable" "0,1"
bitfld.long 0x00 29. "RSTDEN,Counter reset DMA request enable" "0,1"
bitfld.long 0x00 28. "CH1ONADEN,Channel 1 output inactive DMA request enable" "0,1"
bitfld.long 0x00 27. "CH1OADEN,Channel 1 output active DMA request enable" "0,1"
newline
bitfld.long 0x00 26. "CH0ONADEN,Channel 0 output inactive DMA request enable" "0,1"
bitfld.long 0x00 25. "CH0ADEN,Channel 0 output active DMA request enable" "0,1"
bitfld.long 0x00 24. "CAP1DEN,Capture 1 DMA request enable" "0,1"
bitfld.long 0x00 23. "CAP0DEN,Capture 0 DMA request enable" "0,1"
newline
bitfld.long 0x00 22. "UPDEN,Update DMA request enable" "0,1"
bitfld.long 0x00 20. "REPDEN,Repetition DMA request enable" "0,1"
bitfld.long 0x00 19. "CMP3DEN,Compare 3 DMA request enable" "0,1"
bitfld.long 0x00 18. "CMP2DEN,Compare 2 DMA request enable" "0,1"
newline
bitfld.long 0x00 17. "CMP1DEN,Compare 1 DMA request enable" "0,1"
bitfld.long 0x00 16. "CMP0DEN,Compare 0 DMA request enable" "0,1"
bitfld.long 0x00 14. "DLYIIE,Delayed IDLE mode entry interrupt enable" "0,1"
bitfld.long 0x00 13. "RSTIE,Counter reset interrupt enable" "0,1"
newline
bitfld.long 0x00 12. "CH1ONAIE,Channel 1 output inactive interrupt enable" "0,1"
bitfld.long 0x00 11. "CH1OAIE,Channel 1 output active interrupt enable" "0,1"
bitfld.long 0x00 10. "CH0ONAIE,Channel 0 output inactive interrupt enable" "0,1"
bitfld.long 0x00 9. "CH0OAIE,Channel 0 output active interrupt enable" "0,1"
newline
bitfld.long 0x00 8. "CAP1IE,Capture 1 interrupt enable" "0,1"
bitfld.long 0x00 7. "CAP0IE,Capture 0 interrupt enable" "0,1"
bitfld.long 0x00 6. "UPIE,Update interrupt enable" "0,1"
bitfld.long 0x00 4. "REPIE,Repetition interrupt enable" "0,1"
newline
bitfld.long 0x00 3. "CMP3IE,Compare 3 interrupt enable" "0,1"
bitfld.long 0x00 2. "CMP2IE,Compare 2 interrupt enable" "0,1"
bitfld.long 0x00 1. "CMP1IE,Compare 1 interrupt enable" "0,1"
bitfld.long 0x00 0. "CMP0IE,Compare 0 interrupt enable" "0,1"
group.long 0x10++0x03
line.long 0x00 "ST4CNT,SHRTIMER Slave_TIMERx counter register"
hexmask.long.word 0x00 0.--15. 1. "CNT,The current counter value"
group.long 0x14++0x03
line.long 0x00 "ST4CAR,SHRTIMER Slave_TIMER4 counter auto reload register"
hexmask.long.word 0x00 0.--15. 1. "CARL,Counter auto reload value"
group.long 0x18++0x03
line.long 0x00 "ST4CREP,SHRTIMER Slave_TIMER4 counter repetition register"
hexmask.long.byte 0x00 0.--7. 1. "CREP,Counter repetition value"
group.long 0x1C++0x03
line.long 0x00 "ST4CMP0V,SHRTIMER Slave_TIMER4 compare 0 value register"
hexmask.long.word 0x00 0.--15. 1. "CMP0VAL,Compare 0 value"
group.long 0x20++0x03
line.long 0x00 "ST4CMP0CP,SHRTIMER Slave_TIMERx compare 0 composite register"
hexmask.long.byte 0x00 16.--23. 1. "CREP,Counter repetition value"
hexmask.long.word 0x00 0.--15. 1. "CMP0VAL,Compare 0 value"
group.long 0x24++0x03
line.long 0x00 "ST4CMP1V,SHRTIMER Slave_TIMERx compare 1 value register"
hexmask.long.word 0x00 0.--15. 1. "CMP1VAL,Compare 1 value"
group.long 0x28++0x03
line.long 0x00 "ST4CMP2V,SHRTIMER Slave_TIMERx compare 2 value register"
hexmask.long.word 0x00 0.--15. 1. "CMP2VAL,Compare 2 value"
group.long 0x2C++0x03
line.long 0x00 "ST4CMP3V,SHRTIMER Slave_TIMERx compare 3 value register"
hexmask.long.word 0x00 0.--15. 1. "CMP3VAL,Compare 3 value"
group.long 0x30++0x03
line.long 0x00 "ST4CAP0V,SHRTIMER Slave_TIMERx capture 0 value register"
hexmask.long.word 0x00 0.--15. 1. "CAP0VAL,Capture 0 value"
group.long 0x34++0x03
line.long 0x00 "ST4CAP1V,SHRTIMER Slave_TIMERx capture 1 value register"
hexmask.long.word 0x00 0.--15. 1. "CAP1VAL,Capture 1 value"
group.long 0x38++0x03
line.long 0x00 "ST4DTCTL,SHRTIMER Slave_TIMERx dead-time control register"
bitfld.long 0x00 31. "DTFSVPROT,Dead-time falling edge protection for value and sign" "0,1"
bitfld.long 0x00 30. "DTFSPROT,Dead-time falling edge protection for sign" "0,1"
bitfld.long 0x00 25. "DTFS,The sign of falling edge dead-time value" "0,1"
hexmask.long.word 0x00 16.--24. 1. "DTFCFG,Falling edge dead-time value"
newline
bitfld.long 0x00 15. "DTRSVPROT,Dead-time rising edge protection for value and sign" "0,1"
bitfld.long 0x00 14. "DTRSPROT,Dead-time rising edge protection for sign" "0,1"
bitfld.long 0x00 10.--13. "DTGCKDIV,Dead time generator clock division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 9. "DTRS,The sign of falling edge dead-time value" "0,1"
newline
hexmask.long.word 0x00 0.--8. 1. "DTRCFG,Falling edge dead-time value"
group.long 0x3C++0x03
line.long 0x00 "ST4CH0SET,SHRTIMER Slave_TIMERx channel 0 set request register"
bitfld.long 0x00 31. "CH0SUP,Update event generates channel 0" "0,1"
bitfld.long 0x00 30. "CH0SEXEV9,External event 9 generates channel 0" "0,1"
bitfld.long 0x00 29. "CH0SEXEV8,External event 8 generates channel 0" "0,1"
bitfld.long 0x00 28. "CH0SEXEV7,External event 7 generates channel 0" "0,1"
newline
bitfld.long 0x00 27. "CH0SEXEV6,External event 6 generates channel 0" "0,1"
bitfld.long 0x00 26. "CH0SEXEV5,External event 5 generates channel 0" "0,1"
bitfld.long 0x00 25. "CH0SEXEV4,External event 4 generates channel 0" "0,1"
bitfld.long 0x00 24. "CH0SEXEV3,External event 3 generates channel 0" "0,1"
newline
bitfld.long 0x00 23. "CH0SEXEV2,External event 2 generates channel 0" "0,1"
bitfld.long 0x00 22. "CH0SEXEV1,External event 1 generates channel 0" "0,1"
bitfld.long 0x00 21. "CH0SEXEV0,External event 0 generates channel 0" "0,1"
bitfld.long 0x00 20. "CH0SSTEV8,Slave_TIMERx interconnection event 8 generates channel 0" "0,1"
newline
bitfld.long 0x00 19. "CH0SSTEV7,Slave_TIMER1 interconnection event 7 generates channel 0" "0,1"
bitfld.long 0x00 18. "CH0SSTEV6,Slave_TIMERx interconnection event 6 generates channel 0" "0,1"
bitfld.long 0x00 17. "CH0SSTEV5,Slave_TIMERx interconnection event 5 generates channel 0" "0,1"
bitfld.long 0x00 16. "CH0SSTEV4,Slave_TIMERx interconnection event 4 generates channel 0" "0,1"
newline
bitfld.long 0x00 15. "CH0SSTEV3,Slave_TIMERx interconnection event 3 generates channel 0" "0,1"
bitfld.long 0x00 14. "CH0SSTEV2,Slave_TIMERx interconnection event 2 generates channel 0" "0,1"
bitfld.long 0x00 13. "CH0SSTEV1,Slave_TIMERx interconnection event 1 generates channel 0" "0,1"
bitfld.long 0x00 12. "CH0SSTEV0,Slave_TIMERx interconnection event 0 generates channel 0" "0,1"
newline
bitfld.long 0x00 11. "CH0SMTCMP3,Master_TIMER compare 3 event generates channel 0" "0,1"
bitfld.long 0x00 10. "CH0SMTCMP2,Master_TIMER compare 2 event generates channel 0" "0,1"
bitfld.long 0x00 9. "CH0SMTCMP1,Master_TIMER compare 1 event generates channel 0" "0,1"
bitfld.long 0x00 8. "CH0SMTCMP0,Master_TIMER compare 0 event generates channel 0" "0,1"
newline
bitfld.long 0x00 7. "CH0SMTPER,Master_TIMER period event generates channel 0" "0,1"
bitfld.long 0x00 6. "CH0SCMP3,Slave_TIMERx compare 3 event generates channel 0" "0,1"
bitfld.long 0x00 5. "CH0SCMP2,Slave_TIMERx compare 2 event generates channel 0" "0,1"
bitfld.long 0x00 4. "CH0SCMP1,Slave_TIMERx compare 1 event generates channel 0" "0,1"
newline
bitfld.long 0x00 3. "CH0SCMP0,Slave_TIMERx compare 0 event generates channel 0" "0,1"
bitfld.long 0x00 2. "CH0SPER,Slave_TIMERx period event generates channel 0" "0,1"
bitfld.long 0x00 1. "CH0SRST,Slave_TIMERx reset event generates channel 0" "0,1"
bitfld.long 0x00 0. "CH0SSEV,Software event generates channel 0" "0,1"
group.long 0x40++0x03
line.long 0x00 "ST4CH0RST,SHRTIMER Slave_TIMERx channel 0 reset request register"
bitfld.long 0x00 31. "CH0RSUP,Update event generates channel 0" "0,1"
bitfld.long 0x00 30. "CH0RSEXEV9,External event 9 generates channel 0" "0,1"
bitfld.long 0x00 29. "CH0RSEXEV8,External event 8 generates channel 0" "0,1"
bitfld.long 0x00 28. "CH0RSEXEV7,External event 7 generates channel 0" "0,1"
newline
bitfld.long 0x00 27. "CH0RSEXEV6,External event 6 generates channel 0" "0,1"
bitfld.long 0x00 26. "CH0RSEXEV5,External event 5 generates channel 0" "0,1"
bitfld.long 0x00 25. "CH0RSEXEV4,External event 4 generates channel 0" "0,1"
bitfld.long 0x00 24. "CH0RSEXEV3,External event 3 generates channel 0" "0,1"
newline
bitfld.long 0x00 23. "CH0RSEXEV2,External event 2 generates channel 0" "0,1"
bitfld.long 0x00 22. "CH0RSEXEV1,External event 1 generates channel 0" "0,1"
bitfld.long 0x00 21. "CH0RSEXEV0,External event 0 generates channel 0" "0,1"
bitfld.long 0x00 20. "CH0RSSTEV8,Slave_TIMERx interconnection event 8 generates channel 0" "0,1"
newline
bitfld.long 0x00 19. "CH0RSSTEV7,Slave_TIMERx interconnection event 7 generates channel 0" "0,1"
bitfld.long 0x00 18. "CH0RSSTEV6,Slave_TIMERx interconnection event 6 generates channel 0" "0,1"
bitfld.long 0x00 17. "CH0RSSTEV5,Slave_TIMERx interconnection event 5 generates channel 0" "0,1"
bitfld.long 0x00 16. "CH0RSSTEV4,Slave_TIMER1 interconnection event 4 generates channel 0" "0,1"
newline
bitfld.long 0x00 15. "CH0RSSTEV3,Slave_TIMERx interconnection event 3 generates channel 0" "0,1"
bitfld.long 0x00 14. "CH0RSSTEV2,Slave_TIMERx interconnection event 2 generates channel 0" "0,1"
bitfld.long 0x00 13. "CH0RSSTEV1,Slave_TIMERx interconnection event 1 generates channel 0" "0,1"
bitfld.long 0x00 12. "CH0RSSTEV0,Slave_TIMER1 interconnection event 0 generates channel 0" "0,1"
newline
bitfld.long 0x00 11. "CH0RSMTCMP3,Master_TIMER compare 3 event generates channel 0" "0,1"
bitfld.long 0x00 10. "CH0RSMTCMP2,Master_TIMER compare 2 event generates channel 0" "0,1"
bitfld.long 0x00 9. "CH0RSMTCMP1,Master_TIMER compare 1 event generates channel 0" "0,1"
bitfld.long 0x00 8. "CH0RSMTCMP0,Master_TIMER compare 0 event generates channel 0" "0,1"
newline
bitfld.long 0x00 7. "CH0RSMTPER,Master_TIMER period event generates channel 0" "0,1"
bitfld.long 0x00 6. "CH0RSCMP3,Slave_TIMERx compare 3 event generates channel 0" "0,1"
bitfld.long 0x00 5. "CH0RSCMP2,Slave_TIMER1 compare 2 event generates channel 0" "0,1"
bitfld.long 0x00 4. "CH0RSCMP1,Slave_TIMERx compare 1 event generates channel 0" "0,1"
newline
bitfld.long 0x00 3. "CH0RSCMP0,Slave_TIMERx compare 0 event generates channel 0" "0,1"
bitfld.long 0x00 2. "CH0RSPER,Slave_TIMERx period event generates channel 0" "0,1"
bitfld.long 0x00 1. "CH0RSRST,Slave_TIMERx reset event generates channel 0" "0,1"
bitfld.long 0x00 0. "CH0RSSEV,Software event generates channel 0" "0,1"
group.long 0x44++0x03
line.long 0x00 "ST4CH1SET,SHRTIMER Slave_TIMERx channel 1 set request register"
bitfld.long 0x00 31. "CH1SUP,Update event generates channel 1" "0,1"
bitfld.long 0x00 30. "CH1SEXEV9,External event 9 generates channel 1" "0,1"
bitfld.long 0x00 29. "CH1SEXEV8,External event 8 generates channel 1" "0,1"
bitfld.long 0x00 28. "CH1SEXEV7,External event 7 generates channel 1" "0,1"
newline
bitfld.long 0x00 27. "CH1SEXEV6,External event 6 generates channel 1" "0,1"
bitfld.long 0x00 26. "CH1SEXEV5,External event 5 generates channel 1" "0,1"
bitfld.long 0x00 25. "CH1SEXEV4,External event 4 generates channel 1" "0,1"
bitfld.long 0x00 24. "CH1SEXEV3,External event 3 generates channel 1" "0,1"
newline
bitfld.long 0x00 23. "CH1SEXEV2,External event 2 generates channel 1" "0,1"
bitfld.long 0x00 22. "CH1SEXEV1,External event 1 generates channel 1" "0,1"
bitfld.long 0x00 21. "CH1SEXEV0,External event 0 generates channel 1" "0,1"
bitfld.long 0x00 20. "CH1SSTEV8,Slave_TIMERx interconnection event 8 generates channel 1" "0,1"
newline
bitfld.long 0x00 19. "CH1SSTEV7,Slave_TIMERx interconnection event 7 generates channel 1" "0,1"
bitfld.long 0x00 18. "CH1SSTEV6,Slave_TIMERx interconnection event 6 generates channel 1" "0,1"
bitfld.long 0x00 17. "CH1SSTEV5,Slave_TIMERx interconnection event 5 generates channel 1" "0,1"
bitfld.long 0x00 16. "CH1SSTEV4,Slave_TIMERx interconnection event 4 generates channel 1" "0,1"
newline
bitfld.long 0x00 15. "CH1SSTEV3,Slave_TIMERx interconnection event 3 generates channel 1" "0,1"
bitfld.long 0x00 14. "CH1SSTEV2,Slave_TIMERx interconnection event 2 generates channel 1" "0,1"
bitfld.long 0x00 13. "CH1SSTEV1,Slave_TIMERx interconnection event 1 generates channel 1" "0,1"
bitfld.long 0x00 12. "CH1SSTEV0,Slave_TIMERx interconnection event 0 generates channel 1" "0,1"
newline
bitfld.long 0x00 11. "CH1SMTCMP3,Master_TIMER compare 3 event generates channel 1" "0,1"
bitfld.long 0x00 10. "CH1SMTCMP2,Master_TIMER compare 2 event generates channel 1" "0,1"
bitfld.long 0x00 9. "CH1SMTCMP1,Master_TIMER compare 1 event generates channel 1" "0,1"
bitfld.long 0x00 8. "CH1SMTCMP0,Master_TIMER compare 0 event generates channel 1" "0,1"
newline
bitfld.long 0x00 7. "CH1SMTPER,Master_TIMER period event generates channel 1" "0,1"
bitfld.long 0x00 6. "CH1SCMP3,Slave_TIMERx compare 3 event generates channel 1" "0,1"
bitfld.long 0x00 5. "CH1SCMP2,Slave_TIMERx compare 2 event generates channel 1" "0,1"
bitfld.long 0x00 4. "CH1SCMP1,Slave_TIMERx compare 1 event generates channel 1" "0,1"
newline
bitfld.long 0x00 3. "CH1SCMP0,Slave_TIMERx compare 0 event generates channel 1" "0,1"
bitfld.long 0x00 2. "CH1SPER,Slave_TIMERx period event generates channel 1" "0,1"
bitfld.long 0x00 1. "CH1SRST,Slave_TIMERx reset event generates channel 1" "0,1"
bitfld.long 0x00 0. "CH1SSEV,Software event generates channel 1" "0,1"
group.long 0x48++0x03
line.long 0x00 "ST4CH1RST,SHRTIMER Slave_TIMERx channel 1 reset request register"
bitfld.long 0x00 31. "CH1RSUP,Update event generates channel 1" "0,1"
bitfld.long 0x00 30. "CH1RSEXEV9,External event 9 generates channel 1" "0,1"
bitfld.long 0x00 29. "CH1RSEXEV8,External event 8 generates channel 1" "0,1"
bitfld.long 0x00 28. "CH1RSEXEV7,External event 7 generates channel 1" "0,1"
newline
bitfld.long 0x00 27. "CH1RSEXEV6,External event 6 generates channel 1" "0,1"
bitfld.long 0x00 26. "CH1RSEXEV5,External event 5 generates channel 1" "0,1"
bitfld.long 0x00 25. "CH1RSEXEV4,External event 4 generates channel 1" "0,1"
bitfld.long 0x00 24. "CH1RSEXEV3,External event 3 generates channel 1" "0,1"
newline
bitfld.long 0x00 23. "CH1RSEXEV2,External event 2 generates channel 1" "0,1"
bitfld.long 0x00 22. "CH1RSEXEV1,External event 1 generates channel 1" "0,1"
bitfld.long 0x00 21. "CH1RSEXEV0,External event 0 generates channel 1" "0,1"
bitfld.long 0x00 20. "CH1RSSTEV8,Slave_TIMERx interconnection event 8 generates channel 1" "0,1"
newline
bitfld.long 0x00 19. "CH1RSSTEV7,Slave_TIMERx interconnection event 7 generates channel 1" "0,1"
bitfld.long 0x00 18. "CH1RSSTEV6,Slave_TIMERx interconnection event 6 generates channel 1" "0,1"
bitfld.long 0x00 17. "CH1RSSTEV5,Slave_TIMERx interconnection event 5 generates channel 1" "0,1"
bitfld.long 0x00 16. "CH1RSSTEV4,Slave_TIMERx interconnection event 4 generates channel 1" "0,1"
newline
bitfld.long 0x00 15. "CH1RSSTEV3,Slave_TIMERx interconnection event 3 generates channel 1" "0,1"
bitfld.long 0x00 14. "CH1RSSTEV2,Slave_TIMERx interconnection event 2 generates channel 1" "0,1"
bitfld.long 0x00 13. "CH1RSSTEV1,Slave_TIMERx interconnection event 1 generates channel 1" "0,1"
bitfld.long 0x00 12. "CH1RSSTEV0,Slave_TIMERx interconnection event 0 generates channel 1" "0,1"
newline
bitfld.long 0x00 11. "CH1RSMTCMP3,Master_TIMER compare 3 event generates channel 1" "0,1"
bitfld.long 0x00 10. "CH1RSMTCMP2,Master_TIMER compare 2 event generates channel 1" "0,1"
bitfld.long 0x00 9. "CH1RSMTCMP1,Master_TIMER compare 1 event generates channel 1" "0,1"
bitfld.long 0x00 8. "CH1RSMTCMP0,Master_TIMER compare 0 event generates channel 1" "0,1"
newline
bitfld.long 0x00 7. "CH1RSMTPER,Master_TIMER period event generates channel 1" "0,1"
bitfld.long 0x00 6. "CH1RSCMP3,Slave_TIMERx compare 3 event generates channel 1" "0,1"
bitfld.long 0x00 5. "CH1RSCMP2,Slave_TIMERx compare 2 event generates channel 1" "0,1"
bitfld.long 0x00 4. "CH1RSCMP1,Slave_TIMERx compare 1 event generates channel 1" "0,1"
newline
bitfld.long 0x00 3. "CH1RSCMP0,Slave_TIMERx compare 0 event generates channel 1" "0,1"
bitfld.long 0x00 2. "CH1RSPER,Slave_TIMERx period event generates channel 1" "0,1"
bitfld.long 0x00 1. "CH1RSRST,Slave_TIMERx reset event generates channel 1" "0,1"
bitfld.long 0x00 0. "CH1RSSEV,Software event generates channel 1" "0,1"
group.long 0x4C++0x03
line.long 0x00 "ST4EXEVFCFG0,SHRTIMER Slave_TIMERx external event filter configuration register 0"
bitfld.long 0x00 25.--28. "EXEV4FM,External event 4 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24. "EXEV4MEEN,External event 4 memorized enable" "0,1"
bitfld.long 0x00 19.--22. "EXEV3FM,External event 3 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 18. "EXEV3MEEN,External event 3 memorized enable" "0,1"
newline
bitfld.long 0x00 13.--16. "EXEV2FM,External event 2 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12. "EXEV2MEEN,External event 2 memorized enable" "0,1"
bitfld.long 0x00 7.--10. "EXEV1FM,External event 1 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "EXEV1MEEN,External event 1 memorized enable" "0,1"
newline
bitfld.long 0x00 1.--4. "EXEV0FM,External event 0 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "EXEV0MEEN,External event 0 memorized enable" "0,1"
group.long 0x50++0x03
line.long 0x00 "ST4EXEVFCFG1,SHRTIMER Slave_TIMERx external event filter configuration register 1"
bitfld.long 0x00 25.--28. "EXEV9FM,External event 9 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24. "EXEV9MEEN,External event 9 memorized enable" "0,1"
bitfld.long 0x00 19.--22. "EXEV8FM,External event 8 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 18. "EXEV8MEEN,External event 8 memorized enable" "0,1"
newline
bitfld.long 0x00 13.--16. "EXEV7FM,External event 7 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12. "EXEV7MEEN,External event 7 memorized enable" "0,1"
bitfld.long 0x00 7.--10. "EXEV6FM,External event 6 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "EXEV6MEEN,External event 6 memorized enable" "0,1"
newline
bitfld.long 0x00 1.--4. "EXEV5FM,External event 5 filter mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "EXEV5MEEN,External event 5 memorized enable" "0,1"
group.long 0x54++0x03
line.long 0x00 "ST4CNTRST,SHRTIMER Slave_TIMERx counter reset register"
bitfld.long 0x00 30. "ST3CMP3RST,Slave_TIMER3 compare 3 event resets counter" "0,1"
bitfld.long 0x00 29. "ST3CMP1RST,Slave_TIMER3 compare 1 event resets counter" "0,1"
bitfld.long 0x00 28. "ST3CMP0RST,Slave_TIMER3 compare 0 event resets counter" "0,1"
bitfld.long 0x00 27. "ST2CMP3RST,Slave_TIMER2 compare 3 event resets counter" "0,1"
newline
bitfld.long 0x00 26. "ST2CMP1RST,Slave_TIMER2 compare 1 event resets counter" "0,1"
bitfld.long 0x00 25. "ST2CMP0RST,Slave_TIMER2 compare 0 event resets counter" "0,1"
bitfld.long 0x00 24. "ST1CMP3RST,Slave_TIMER1 compare 3 event resets counter" "0,1"
bitfld.long 0x00 23. "ST1CMP1RST,Slave_TIMER1 compare 1 event resets counter" "0,1"
newline
bitfld.long 0x00 22. "ST1CMP0RST,Slave_TIMER1 compare 0 event resets counter" "0,1"
bitfld.long 0x00 21. "ST0CMP3RST,Slave_TIMER0 compare 3 event resets counter" "0,1"
bitfld.long 0x00 20. "ST0CMP1RST,Slave_TIMER0 compare 1 event resets counter" "0,1"
bitfld.long 0x00 19. "ST0CMP0RST,Slave_TIMER0 compare 0 event resets counter" "0,1"
newline
bitfld.long 0x00 18. "EXEV9RST,External event 9 resets counter" "0,1"
bitfld.long 0x00 17. "EXEV8RST,External event 8 resets counter" "0,1"
bitfld.long 0x00 16. "EXEV7RST,External event 7 resets counter" "0,1"
bitfld.long 0x00 15. "EXEV6RST,External event 6 resets counter" "0,1"
newline
bitfld.long 0x00 14. "EXEV5RST,External event 5 resets counter" "0,1"
bitfld.long 0x00 13. "EXEV4RST,External event 4 resets counter" "0,1"
bitfld.long 0x00 12. "EXEV3RST,External event 3 resets counter" "0,1"
bitfld.long 0x00 11. "EXEV2RST,External event 2 resets counter" "0,1"
newline
bitfld.long 0x00 10. "EXEV1RST,External event 1 resets counter" "0,1"
bitfld.long 0x00 9. "EXEV0RST,External event 0 resets counter" "0,1"
bitfld.long 0x00 8. "MTCMP3RST,Master_TIMER compare 3 event resets counter" "0,1"
bitfld.long 0x00 7. "MTCMP2RST,Master_TIMER compare 2 event resets counter" "0,1"
newline
bitfld.long 0x00 6. "MTCMP1RST,Master_TIMER compare 1 event resets counter" "0,1"
bitfld.long 0x00 5. "MTCMP0RST,Master_TIMER compare 0 event resets counter" "0,1"
bitfld.long 0x00 4. "MTPERRST,Master_TIMER period event resets counter" "0,1"
bitfld.long 0x00 3. "CMP3RST,Slave_TIMERx compare 3 event resets counter" "0,1"
newline
bitfld.long 0x00 2. "CMP1RST,Slave_TIMERx compare 1 event resets counter" "0,1"
bitfld.long 0x00 1. "UPRST,Slave_TIMERx update event resets counter" "0,1"
group.long 0x58++0x03
line.long 0x00 "ST4CSCTL,SHRTIMER Slave_TIMERx carrier-signal control register"
bitfld.long 0x00 7.--10. "CSFSTPW,First carrier-signal pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--6. "CSDTY,Carrier signal duty cycle" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--3. "CSPRD,Carrier signal period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x5C++0x03
line.long 0x00 "ST4CAP0TRG,SHRTIMER Slave_TIMERx capture 0 trigger register"
bitfld.long 0x00 27. "CP0BST3CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER3" "0,1"
bitfld.long 0x00 26. "CP0BST3CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER3" "0,1"
bitfld.long 0x00 25. "CP0BST3NA,Capture 0 triggered by ST3CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 24. "CP0BST3A,Capture 0 triggered by ST3CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 23. "CP0BST2CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER2" "0,1"
bitfld.long 0x00 22. "CP0BST2CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER2" "0,1"
bitfld.long 0x00 21. "CP0BST2NA,Capture 0 triggered by ST2CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 20. "CP0BST2A,Capture 0 triggered by ST2CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 19. "CP0BST1CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER1" "0,1"
bitfld.long 0x00 18. "CP0BST1CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER1" "0,1"
bitfld.long 0x00 17. "CP0BST1NA,Capture 0 triggered by ST2CH1_O output active to inactive transition" "0,1"
bitfld.long 0x00 16. "CP0BST1A,Capture 0 triggered by ST2CH1_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 15. "CP0BST0CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER0" "0,1"
bitfld.long 0x00 14. "CP0BST0CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER0" "0,1"
bitfld.long 0x00 13. "CP0BST0NA,Capture 0 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 12. "CP0BST0A,Capture 0 triggered by ST0CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 11. "CP0BEXEV9,Capture 0 triggered by external event 9" "0,1"
bitfld.long 0x00 10. "CP0BEXEV8,Capture 0 triggered by external event 8" "0,1"
bitfld.long 0x00 9. "CP0BEXEV7,Capture 0 triggered by external event 7" "0,1"
bitfld.long 0x00 8. "CP0BEXEV6,Capture 0 triggered by external event 6" "0,1"
newline
bitfld.long 0x00 7. "CP0BEXEV5,Capture 0 triggered by external event 5" "0,1"
bitfld.long 0x00 6. "CP0BEXEV4,Capture 0 triggered by external event 4" "0,1"
bitfld.long 0x00 5. "CP0BEXEV3,Capture 0 triggered by external event 3" "0,1"
bitfld.long 0x00 4. "CP0BEXEV2,Capture 0 triggered by external event 2" "0,1"
newline
bitfld.long 0x00 3. "CP0BEXEV1,Capture 0 triggered by external event 1" "0,1"
bitfld.long 0x00 2. "CP0BEXEV0,Capture 0 triggered by external event 0" "0,1"
bitfld.long 0x00 1. "CP0BUP,Capture 0 triggered by update event" "0,1"
bitfld.long 0x00 0. "CP0BSW,Capture 0 triggered by software" "0,1"
group.long 0x5C++0x03
line.long 0x00 "ST4CAP0TRG,SHRTIMER Slave_TIMERx capture 0 trigger register"
bitfld.long 0x00 31. "CP0BST4CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER4" "0,1"
bitfld.long 0x00 30. "CP0BST4CMP0,Capture 0 triggered by compare 0 event of Slave_TIMER4" "0,1"
bitfld.long 0x00 29. "CP0BST4NA,Capture 0 triggered by ST4CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 28. "CP0BST4A,Capture 0 triggered by ST4CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 11. "CP0BEXEV9,Capture 0 triggered by external event 9" "0,1"
bitfld.long 0x00 10. "CP0BEXEV8,Capture 0 triggered by external event 8" "0,1"
bitfld.long 0x00 9. "CP0BEXEV7,Capture 0 triggered by external event 7" "0,1"
bitfld.long 0x00 8. "CP0BEXEV6,Capture 0 triggered by external event 6" "0,1"
newline
bitfld.long 0x00 7. "CP0BEXEV5,Capture 0 triggered by external event 5" "0,1"
bitfld.long 0x00 6. "CP0BEXEV4,Capture 0 triggered by external event 4" "0,1"
bitfld.long 0x00 5. "CP0BEXEV3,Capture 0 triggered by external event 3" "0,1"
bitfld.long 0x00 4. "CP0BEXEV2,Capture 0 triggered by external event 2" "0,1"
newline
bitfld.long 0x00 3. "CP0BEXEV1,Capture 0 triggered by external event 1" "0,1"
bitfld.long 0x00 2. "CP0BEXEV0,Capture 0 triggered by external event 0" "0,1"
bitfld.long 0x00 1. "CP0BUP,Capture 0 triggered by update event" "0,1"
bitfld.long 0x00 0. "CP0BSW,Capture 0 triggered by software" "0,1"
group.long 0x60++0x03
line.long 0x00 "ST4CAP1TRG,SHRTIMER Slave_TIMERx capture 1 trigger register"
bitfld.long 0x00 27. "CP0BST3CMP1,Capture 0 triggered by compare 1 event of Slave_TIMER3" "0,1"
bitfld.long 0x00 26. "CP1BST3CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER3" "0,1"
bitfld.long 0x00 25. "CP1BST3NA,Capture 1 triggered by ST3CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 24. "CP1BST3A,Capture 1 triggered by ST3CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 23. "CP1BST2CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER2" "0,1"
bitfld.long 0x00 22. "CP1BST2CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER2" "0,1"
bitfld.long 0x00 21. "CP1BST2NA,Capture 1 triggered by ST2CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 20. "CP1BST2A,Capture 1 triggered by ST2CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 19. "CP1BST1CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER1" "0,1"
bitfld.long 0x00 18. "CP1BST1CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER1" "0,1"
bitfld.long 0x00 17. "CP1BST1NA,Capture 1 triggered by ST2CH1_O output active to inactive transition" "0,1"
bitfld.long 0x00 16. "CP1BST1A,Capture 1 triggered by ST2CH1_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 15. "CP1BST0CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER0" "0,1"
bitfld.long 0x00 14. "CP1BST0CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER0" "0,1"
bitfld.long 0x00 13. "CP1BST0NA,Capture 1 triggered by ST0CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 12. "CP1BST0A,Capture 1 triggered by ST0CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 11. "CP1BEXEV9,Capture 1 triggered by external event 9" "0,1"
bitfld.long 0x00 10. "CP1BEXEV8,Capture 1 triggered by external event 8" "0,1"
bitfld.long 0x00 9. "CP1BEXEV7,Capture 1 triggered by external event 7" "0,1"
bitfld.long 0x00 8. "CP1BEXEV6,Capture 1 triggered by external event 6" "0,1"
newline
bitfld.long 0x00 7. "CP1BEXEV5,Capture 1 triggered by external event 5" "0,1"
bitfld.long 0x00 6. "CP1BEXEV4,Capture 1 triggered by external event 4" "0,1"
bitfld.long 0x00 5. "CP1BEXEV3,Capture 1 triggered by external event 3" "0,1"
bitfld.long 0x00 4. "CP1BEXEV2,Capture 1 triggered by external event 2" "0,1"
newline
bitfld.long 0x00 3. "CP1BEXEV1,Capture 1 triggered by external event 1" "0,1"
bitfld.long 0x00 2. "CP1BEXEV0,Capture 1 triggered by external event 0" "0,1"
bitfld.long 0x00 1. "CP1BUP,Capture 1 triggered by update event" "0,1"
bitfld.long 0x00 0. "CP1BSW,Capture 1 triggered by software" "0,1"
group.long 0x60++0x03
line.long 0x00 "ST4CAP1TRG,SHRTIMER Slave_TIMERx capture 1 trigger register"
bitfld.long 0x00 31. "CP1BST4CMP1,Capture 1 triggered by compare 1 event of Slave_TIMER4" "0,1"
bitfld.long 0x00 30. "CP1BST4CMP0,Capture 1 triggered by compare 0 event of Slave_TIMER4" "0,1"
bitfld.long 0x00 29. "CP1BST4NA,Capture 1 triggered by ST4CH0_O output active to inactive transition" "0,1"
bitfld.long 0x00 28. "CP1BST4A,Capture 1 triggered by ST4CH0_O output inactive to active transition" "0,1"
newline
bitfld.long 0x00 11. "CP1BEXEV9,Capture 1 triggered by external event 9" "0,1"
bitfld.long 0x00 10. "CP1BEXEV8,Capture 1 triggered by external event 8" "0,1"
bitfld.long 0x00 9. "CP1BEXEV7,Capture 1 triggered by external event 7" "0,1"
bitfld.long 0x00 8. "CP1BEXEV6,Capture 1 triggered by external event 6" "0,1"
newline
bitfld.long 0x00 7. "CP1BEXEV5,Capture 1 triggered by external event 5" "0,1"
bitfld.long 0x00 6. "CP1BEXEV4,Capture 1 triggered by external event 4" "0,1"
bitfld.long 0x00 5. "CP1BEXEV3,Capture 1 triggered by external event 3" "0,1"
bitfld.long 0x00 4. "CP1BEXEV2,Capture 1 triggered by external event 2" "0,1"
newline
bitfld.long 0x00 3. "CP1BEXEV1,Capture 1 triggered by external event 1" "0,1"
bitfld.long 0x00 2. "CP1BEXEV0,Capture 1 triggered by external event 0" "0,1"
bitfld.long 0x00 1. "CP1BUP,Capture 1 triggered by update event" "0,1"
bitfld.long 0x00 0. "CP1BSW,Capture 1 triggered by software" "0,1"
group.long 0x64++0x03
line.long 0x00 "ST4CHOCTL,SHRTIMER Slave_TIMERx channel output control register"
bitfld.long 0x00 23. "BMCH1DTI,Channel 1 dead-time insert in bunch mode" "0,1"
bitfld.long 0x00 22. "CH1CSEN,Channel 1 carrier-signal mode enable" "0,1"
bitfld.long 0x00 20.--21. "CH1FLTOS,Channel 1 Fault output state" "0,1,2,3"
bitfld.long 0x00 19. "ISO1,channel 1 output idle state" "0,1"
newline
bitfld.long 0x00 18. "BMCH1IEN,Channel 1 IDLE state enable in bunch mode" "0,1"
bitfld.long 0x00 17. "CH1P,Channel 1 output polarity" "0,1"
bitfld.long 0x00 10.--12. "DLYISCH,Delayed IDLE source and channel" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "DLYISMEN,Delayed IDLE state mode enable" "0,1"
newline
bitfld.long 0x00 8. "DTEN,Dead time enable" "0,1"
bitfld.long 0x00 7. "BMCH0DTI,Channel 0 dead-time insert in bunch mode" "0,1"
bitfld.long 0x00 6. "CH0CSEN,Channel 0 carrier-signal mode enable" "0,1"
bitfld.long 0x00 4.--5. "CH0FLTOS,Channel 0 Fault output state" "0,1,2,3"
newline
bitfld.long 0x00 3. "ISO0,Channel 0 output idle state" "0,1"
bitfld.long 0x00 2. "BMCH0IEN,Channel 0 IDLE state enable in bunch mode" "0,1"
bitfld.long 0x00 1. "CH0P,Channel 0 output polarity" "0,1"
group.long 0x68++0x03
line.long 0x00 "ST4FLTCTL,SHRTIMER Slave_TIMERx fault control register"
bitfld.long 0x00 31. "FLTENPROT,Protect fault enable" "0,1"
bitfld.long 0x00 4. "FLT4EN,Fault 4 enable" "0,1"
bitfld.long 0x00 3. "FLT3EN,Fault 3 enable" "0,1"
bitfld.long 0x00 2. "FLT2EN,Fault 2 enable" "0,1"
newline
bitfld.long 0x00 1. "FLT1EN,Fault 1 enable" "0,1"
bitfld.long 0x00 0. "FLT0EN,Fault 0 enable" "0,1"
group.long 0x7C++0x03
line.long 0x00 "ST4ACTL,SHRTIMER Slave_TIMERx additional control register"
hexmask.long.byte 0x00 25.--31. 1. "DTFCFG_15_9,Falling edge dead-time value configure"
hexmask.long.byte 0x00 9.--15. 1. "DTRCFG_15_9,Rising edge dead-time value configure"
bitfld.long 0x00 3. "CNTCKDIV_3,Counter clock division" "0,1"
tree.end
tree.end
tree "SPI (Serial peripheral interface)"
repeat 2. (list 0. 1.) (list ad:0x40013000 ad:0x40003800)
tree "SPI$1"
base $2
group.long 0x00++0x03
line.long 0x00 "CTL0,control register 0"
bitfld.long 0x00 15. "BDEN,Bidirectional enable" "0,1"
bitfld.long 0x00 14. "BDOEN,Bidirectional Transmit output enable" "0,1"
bitfld.long 0x00 13. "CRCEN,CRC Calculation Enable" "0,1"
bitfld.long 0x00 12. "CRCNT,CRC Next Transfer" "0,1"
newline
bitfld.long 0x00 11. "FF16,Data frame format" "0,1"
bitfld.long 0x00 10. "RO,Receive only" "0,1"
bitfld.long 0x00 9. "SWNSSEN,NSS Software Mode Selection" "0,1"
bitfld.long 0x00 8. "SWNSS,NSS Pin Selection In NSS Software Mode" "0,1"
newline
bitfld.long 0x00 7. "LF,LSB First Mode" "0,1"
bitfld.long 0x00 6. "SPIEN,SPI enable" "0,1"
bitfld.long 0x00 3.--5. "PSC,Master Clock Prescaler Selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. "MSTMOD,Master Mode Enable" "0,1"
newline
bitfld.long 0x00 1. "CKPL,Clock polarity Selection" "0,1"
bitfld.long 0x00 0. "CKPH,Clock Phase Selection" "0,1"
group.long 0x04++0x03
line.long 0x00 "CTL1,control register 1"
bitfld.long 0x00 7. "TBEIE,Tx buffer empty interrupt enable" "0,1"
bitfld.long 0x00 6. "RBNEIE,RX buffer not empty interrupt enable" "0,1"
bitfld.long 0x00 5. "ERRIE,Error interrupt enable" "0,1"
bitfld.long 0x00 4. "TMOD,SPI TI Mode Enable" "0,1"
newline
bitfld.long 0x00 3. "NSSP,SPI NSS pulse mode Enable" "0,1"
bitfld.long 0x00 2. "NSSDRV,Drive NSS Output" "0,1"
bitfld.long 0x00 1. "DMATEN,Transmit Buffer DMA Enable" "0,1"
bitfld.long 0x00 0. "DMAREN,Rx buffer DMA enable" "0,1"
group.long 0x08++0x03
line.long 0x00 "STAT,status register"
bitfld.long 0x00 8. "FERR,Format Error" "0,1"
rbitfld.long 0x00 7. "TRANS,Transmitting On-going Bit" "0,1"
rbitfld.long 0x00 6. "RXORERR,Reception Overrun Error Bit" "0,1"
rbitfld.long 0x00 5. "CONFERR,SPI Configuration error" "0,1"
newline
bitfld.long 0x00 4. "CRCERR,SPI CRC Error Bit" "0,1"
rbitfld.long 0x00 3. "TXURERR,Transmission underrun error bit" "0,1"
rbitfld.long 0x00 2. "I2SCH,I2S channel side" "0,1"
rbitfld.long 0x00 1. "TBE,Transmit Buffer Empty" "0,1"
newline
rbitfld.long 0x00 0. "RBNE,Receive Buffer Not Empty" "0,1"
group.long 0x0C++0x03
line.long 0x00 "DATA,data register"
hexmask.long.word 0x00 0.--15. 1. "SPI_DATA,Data transfer register"
group.long 0x10++0x03
line.long 0x00 "CRCPOLY,CRC polynomial register"
hexmask.long.word 0x00 0.--15. 1. "CPR,CRC polynomial register"
rgroup.long 0x14++0x03
line.long 0x00 "RCRC,RX CRC register"
hexmask.long.word 0x00 0.--15. 1. "RCR,RX CRC register"
rgroup.long 0x18++0x03
line.long 0x00 "TCRC,TX CRC register"
hexmask.long.word 0x00 0.--15. 1. "TCR,Tx CRC register"
group.long 0x1C++0x03
line.long 0x00 "I2SCTL,I2S control register"
bitfld.long 0x00 11. "I2SSEL,I2S mode selection" "0,1"
bitfld.long 0x00 10. "I2SEN,I2S Enable" "0,1"
bitfld.long 0x00 8.--9. "I2SOPMOD,I2S operation mode" "0,1,2,3"
bitfld.long 0x00 7. "PCMSMOD,PCM frame synchronization mode" "0,1"
newline
bitfld.long 0x00 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3"
bitfld.long 0x00 3. "CKPL,Idle state clock polarity" "0,1"
bitfld.long 0x00 1.--2. "DTLEN,Data length" "0,1,2,3"
bitfld.long 0x00 0. "CHLEN,Channel length (number of bits per audio channel)" "0,1"
group.long 0x20++0x03
line.long 0x00 "I2SPSC,I2S prescaler register"
bitfld.long 0x00 9. "MCKOEN,I2S_MCK output enable" "0,1"
bitfld.long 0x00 8. "OF,Odd factor for the prescaler" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Dividing factor for the prescaler"
tree.end
repeat.end
tree "SPI2"
base ad:0x40003C00
group.long 0x00++0x03
line.long 0x00 "CTL0,control register 0"
bitfld.long 0x00 15. "BDEN,Bidirectional enable" "0,1"
bitfld.long 0x00 14. "BDOEN,Bidirectional Transmit output enable" "0,1"
bitfld.long 0x00 13. "CRCEN,CRC Calculation Enable" "0,1"
bitfld.long 0x00 12. "CRCNT,CRC Next Transfer" "0,1"
newline
bitfld.long 0x00 11. "FF16,Data frame format" "0,1"
bitfld.long 0x00 10. "RO,Receive only" "0,1"
bitfld.long 0x00 9. "SWNSSEN,NSS Software Mode Selection" "0,1"
bitfld.long 0x00 8. "SWNSS,NSS Pin Selection In NSS Software Mode" "0,1"
newline
bitfld.long 0x00 7. "LF,LSB First Mode" "0,1"
bitfld.long 0x00 6. "SPIEN,SPI enable" "0,1"
bitfld.long 0x00 3.--5. "PSC,Master Clock Prescaler Selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. "MSTMOD,Master Mode Enable" "0,1"
newline
bitfld.long 0x00 1. "CKPL,Clock polarity Selection" "0,1"
bitfld.long 0x00 0. "CKPH,Clock Phase Selection" "0,1"
group.long 0x04++0x03
line.long 0x00 "CTL1,control register 1"
bitfld.long 0x00 7. "TBEIE,Tx buffer empty interrupt enable" "0,1"
bitfld.long 0x00 6. "RBNEIE,RX buffer not empty interrupt enable" "0,1"
bitfld.long 0x00 5. "ERRIE,Error interrupt enable" "0,1"
bitfld.long 0x00 4. "TMOD,SPI TI Mode Enable" "0,1"
newline
bitfld.long 0x00 3. "NSSP,SPI NSS pulse mode Enable" "0,1"
bitfld.long 0x00 2. "NSSDRV,Drive NSS Output" "0,1"
bitfld.long 0x00 1. "DMATEN,Transmit Buffer DMA Enable" "0,1"
bitfld.long 0x00 0. "DMAREN,Rx buffer DMA enable" "0,1"
group.long 0x08++0x03
line.long 0x00 "STAT,status register"
bitfld.long 0x00 8. "FERR,Format Error" "0,1"
rbitfld.long 0x00 7. "TRANS,Transmitting On-going Bit" "0,1"
rbitfld.long 0x00 6. "RXORERR,Reception Overrun Error Bit" "0,1"
rbitfld.long 0x00 5. "CONFERR,SPI Configuration error" "0,1"
newline
bitfld.long 0x00 4. "CRCERR,SPI CRC Error Bit" "0,1"
rbitfld.long 0x00 3. "TXURERR,Transmission underrun error bit" "0,1"
rbitfld.long 0x00 2. "I2SCH,I2S channel side" "0,1"
rbitfld.long 0x00 1. "TBE,Transmit Buffer Empty" "0,1"
newline
rbitfld.long 0x00 0. "RBNE,Receive Buffer Not Empty" "0,1"
group.long 0x0C++0x03
line.long 0x00 "DATA,data register"
hexmask.long.word 0x00 0.--15. 1. "SPI_DATA,Data transfer register"
group.long 0x10++0x03
line.long 0x00 "CRCPOLY,CRC polynomial register"
hexmask.long.word 0x00 0.--15. 1. "CPR,CRC polynomial register"
rgroup.long 0x14++0x03
line.long 0x00 "RCRC,RX CRC register"
hexmask.long.word 0x00 0.--15. 1. "RCR,RX CRC register"
rgroup.long 0x18++0x03
line.long 0x00 "TCRC,TX CRC register"
hexmask.long.word 0x00 0.--15. 1. "TCR,Tx CRC register"
group.long 0x1C++0x03
line.long 0x00 "I2SCTL,I2S control register"
bitfld.long 0x00 11. "I2SSEL,I2S mode selection" "0,1"
bitfld.long 0x00 10. "I2SEN,I2S Enable" "0,1"
bitfld.long 0x00 8.--9. "I2SOPMOD,I2S operation mode" "0,1,2,3"
bitfld.long 0x00 7. "PCMSMOD,PCM frame synchronization mode" "0,1"
newline
bitfld.long 0x00 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3"
bitfld.long 0x00 3. "CKPL,Idle state clock polarity" "0,1"
bitfld.long 0x00 1.--2. "DTLEN,Data length" "0,1,2,3"
bitfld.long 0x00 0. "CHLEN,Channel length (number of bits per audio channel)" "0,1"
group.long 0x20++0x03
line.long 0x00 "I2SPSC,I2S prescaler register"
bitfld.long 0x00 9. "MCKOEN,I2S_MCK output enable" "0,1"
bitfld.long 0x00 8. "OF,Odd factor for the prescaler" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "DIV,Dividing factor for the prescaler"
group.long 0x80++0x03
line.long 0x00 "QCTL,Quad-SPI mode control register"
bitfld.long 0x00 2. "IO23_DRV,Drive IO2 and IO3 enable" "0,1"
bitfld.long 0x00 1. "QRD,Quad-SPI mode read select" "0,1"
bitfld.long 0x00 0. "QMOD,Quad-SPI mode enable" "0,1"
tree.end
tree.end
tree "SQPI (Serial/Quad Parallel Interface)"
base ad:0xA0001000
group.long 0x00++0x03
line.long 0x00 "INIT,SQPI Initial Register"
bitfld.long 0x00 31. "SQPI_PL,Read data sample polarity" "0,1"
bitfld.long 0x00 29.--30. "SQPI_IDLEN,SQPI controller external memory ID length" "0,1,2,3"
bitfld.long 0x00 24.--28. "SQPI_ADDRBIT,Bit number of SPI PSRAM address phase" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 18.--23. "SQPI_CLKDIV,Clock divider for SQPI output clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 16.--17. "SQPI_CMDBIT,Bit number of SQPI controller command phase" "0,1,2,3"
group.long 0x04++0x03
line.long 0x00 "RCMD,SQPI Read Command Register"
bitfld.long 0x00 31. "SQPI_RID,Send read ID command" "0,1"
bitfld.long 0x00 20.--22. "SQPI_RMODE,SQPI controller read command mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--19. "SQPI_RWAITCYCLE,SQPI read command waitcycle number after address phase" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "SQPI_RCMD,SQPI read command for AHB read transfer"
group.long 0x08++0x03
line.long 0x00 "WCMD,Write Command Register"
bitfld.long 0x00 31. "SQPI_SC,Send special command" "0,1"
bitfld.long 0x00 20.--22. "SQPI_WMODE,SQPI controller write command mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--19. "SQPI_WWAITCYCLE,SQPI write command waitcycle number after address phase" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "SPI_WCMD,SQPI write command for AHB write transfer"
rgroup.long 0x0C++0x03
line.long 0x00 "IDL,ID Low Register"
hexmask.long 0x00 0.--31. 1. "SQPI_IDL,ID Low Data saved for SQPI Read ID Command"
rgroup.long 0x10++0x03
line.long 0x00 "IDH,ID High Register"
hexmask.long 0x00 0.--31. 1. "SQPI_IDH,ID High Data saved for SQPI read ID command"
tree.end
tree "TIMER (Timer/Counter)"
tree "TIMER0"
base ad:0x40012C00
group.long 0x00++0x03
line.long 0x00 "CTL0,control register 0"
bitfld.long 0x00 8.--9. "CKDIV,Clock division" "0,1,2,3"
bitfld.long 0x00 7. "ARSE,Auto-reload shadow enable" "0,1"
bitfld.long 0x00 5.--6. "CAM,Counter aligns mode selection" "0,1,2,3"
bitfld.long 0x00 4. "DIR,Direction" "0,1"
newline
bitfld.long 0x00 3. "SPM,Single pulse mode" "0,1"
bitfld.long 0x00 2. "UPS,Update source" "0,1"
bitfld.long 0x00 1. "UPDIS,Update disable" "0,1"
bitfld.long 0x00 0. "CEN,Counter enable" "0,1"
group.long 0x04++0x03
line.long 0x00 "CTL1,control register 1"
bitfld.long 0x00 14. "ISO3,Idle state of channel 3 output" "0,1"
bitfld.long 0x00 13. "ISO2N,Idle state of channel 2 complementary output" "0,1"
bitfld.long 0x00 12. "ISO2,Idle state of channel 2 output" "0,1"
bitfld.long 0x00 11. "ISO1N,Idle state of channel 1 complementary output" "0,1"
newline
bitfld.long 0x00 10. "ISO1,Idle state of channel 1 output" "0,1"
bitfld.long 0x00 9. "ISO0N,Idle state of channel 0 complementary output" "0,1"
bitfld.long 0x00 8. "ISO0,Idle state of channel 0 output" "0,1"
bitfld.long 0x00 7. "TI0S,Channel 0 trigger input selection" "0,1"
newline
bitfld.long 0x00 4.--6. "MMC,Master mode control" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "DMAS,DMA request source selection" "0,1"
bitfld.long 0x00 2. "CCUC,Commutation control shadow register update control" "0,1"
bitfld.long 0x00 0. "CCSE,Commutation control shadow enable" "0,1"
group.long 0x08++0x03
line.long 0x00 "SMCFG,slave mode configuration register"
bitfld.long 0x00 15. "ETP,External trigger polarity" "0,1"
bitfld.long 0x00 14. "SMC1,Part of SMC for enable External clock mode1" "0,1"
bitfld.long 0x00 12.--13. "ETPSC,External trigger prescaler" "0,1,2,3"
bitfld.long 0x00 8.--11. "ETFC,External trigger filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 7. "MSM,Master/Slave mode" "0,1"
bitfld.long 0x00 4.--6. "TRGS,Trigger selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "SMC,Slave mode selection" "0,1,2,3,4,5,6,7"
group.long 0x0C++0x03
line.long 0x00 "DMAINTEN,DMA/Interrupt enable register"
bitfld.long 0x00 14. "TRGDEN,Trigger DMA request enable" "0,1"
bitfld.long 0x00 13. "CMTDEN,Commutation DMA request enable" "0,1"
bitfld.long 0x00 12. "CH3DEN,Channel 3 capture/compare DMA request enable" "0,1"
bitfld.long 0x00 11. "CH2DEN,Channel 2 capture/compare DMA request enable" "0,1"
newline
bitfld.long 0x00 10. "CH1DEN,Channel 1 capture/compare DMA request enable" "0,1"
bitfld.long 0x00 9. "CH0DEN,Channel 0 capture/compare DMA request enable" "0,1"
bitfld.long 0x00 8. "UPDEN,Update DMA request enable" "0,1"
bitfld.long 0x00 7. "BRKIE,Break interrupt enable" "0,1"
newline
bitfld.long 0x00 6. "TRGIE,Trigger interrupt enable" "0,1"
bitfld.long 0x00 5. "CMTIE,commutation interrupt enable" "0,1"
bitfld.long 0x00 4. "CH3IE,Channel 3 capture/compare interrupt enable" "0,1"
bitfld.long 0x00 3. "CH2IE,Channel 2 capture/compare interrupt enable" "0,1"
newline
bitfld.long 0x00 2. "CH1IE,Channel 1 capture/compare interrupt enable" "0,1"
bitfld.long 0x00 1. "CH0IE,Channel 0 capture/compare interrupt enable" "0,1"
bitfld.long 0x00 0. "UPIE,Update interrupt enable" "0,1"
group.long 0x10++0x03
line.long 0x00 "INTF,Interrupt flag register"
bitfld.long 0x00 12. "CH3OF,Channel 3 over capture flag" "0,1"
bitfld.long 0x00 11. "CH2OF,Channel 2 over capture flag" "0,1"
bitfld.long 0x00 10. "CH1OF,Channel 1 over capture flag" "0,1"
bitfld.long 0x00 9. "CH0OF,Channel 0 over capture flag" "0,1"
newline
bitfld.long 0x00 7. "BRKIF,Break interrupt flag" "0,1"
bitfld.long 0x00 6. "TRGIF,Trigger interrupt flag" "0,1"
bitfld.long 0x00 5. "CMTIF,Channel commutation interrupt flag" "0,1"
bitfld.long 0x00 4. "CH3IF,Channel 3 capture/compare interrupt flag" "0,1"
newline
bitfld.long 0x00 3. "CH2IF,Channel 2 capture/compare interrupt flag" "0,1"
bitfld.long 0x00 2. "CH1IF,Channel 1 capture/compare interrupt flag" "0,1"
bitfld.long 0x00 1. "CH0IF,Channel 0 capture/compare interrupt flag" "0,1"
bitfld.long 0x00 0. "UPIF,Update interrupt flag" "0,1"
wgroup.long 0x14++0x03
line.long 0x00 "SWEVG,Software event generation register"
bitfld.long 0x00 7. "BRKG,Break event generation" "0,1"
bitfld.long 0x00 6. "TRGG,Trigger event generation" "0,1"
bitfld.long 0x00 5. "CMTG,Channel commutation event generation" "0,1"
bitfld.long 0x00 4. "CH3G,Channel 3 capture or compare event generation" "0,1"
newline
bitfld.long 0x00 3. "CH2G,Channel 2 capture or compare event generation" "0,1"
bitfld.long 0x00 2. "CH1G,Channel 1 capture or compare event generation" "0,1"
bitfld.long 0x00 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
bitfld.long 0x00 0. "UPG,Update event generation" "0,1"
group.long 0x18++0x03
line.long 0x00 "CHCTL0_Output,Channel control register 0 (output mode)"
bitfld.long 0x00 15. "CH1COMCEN,Channel 1 output compare clear enable" "0,1"
bitfld.long 0x00 12.--14. "CH1COMCTL,Channel 1 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 11. "CH1COMSEN,Channel 1 output compare shadow enable" "0,1"
bitfld.long 0x00 10. "CH1COMFEN,Channel 1 output compare fast enable" "0,1"
newline
bitfld.long 0x00 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
bitfld.long 0x00 7. "CH0COMCEN,Channel 0 output compare clear enable" "0,1"
bitfld.long 0x00 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
newline
bitfld.long 0x00 2. "CH0COMFEN,Channel 0 output compare fast enable" "0,1"
bitfld.long 0x00 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
group.long 0x18++0x03
line.long 0x00 "CHCTL0_Input,Channel control register 0 (input mode)"
bitfld.long 0x00 12.--15. "CH1CAPFLT,Channel 1 input capture filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "CH1CAPPSC,Channel 1 input capture prescaler" "0,1,2,3"
bitfld.long 0x00 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
bitfld.long 0x00 4.--7. "CH0CAPFLT,Channel 0 input capture filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
bitfld.long 0x00 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
group.long 0x1C++0x03
line.long 0x00 "CHCTL1_Output,Channel control register 1 (output mode)"
bitfld.long 0x00 15. "CH3COMCEN,Channel 3 output compare clear enable" "0,1"
bitfld.long 0x00 12.--14. "CH3COMCTL,Channel 3 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 11. "CH3COMSEN,Channel 3 output compare shadow enable" "0,1"
bitfld.long 0x00 10. "CH3COMFEN,Channel 3 output compare fast enable" "0,1"
newline
bitfld.long 0x00 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
bitfld.long 0x00 7. "CH2COMCEN,Channel 2 output compare clear enable" "0,1"
bitfld.long 0x00 4.--6. "CH2COMCTL,Channel 2 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "CH2COMSEN,Channel 2 compare output shadow enable" "0,1"
newline
bitfld.long 0x00 2. "CH2COMFEN,Channel 2 output compare fast enable" "0,1"
bitfld.long 0x00 0.--1. "CH2MS,Channel 2 I/O mode selection" "0,1,2,3"
group.long 0x1C++0x03
line.long 0x00 "CHCTL1_Input,Channel control register 1 (input mode)"
bitfld.long 0x00 12.--15. "CH3CAPFLT,Channel 3 input capture filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "CH3CAPPSC,Channel 3 input capture prescaler" "0,1,2,3"
bitfld.long 0x00 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
bitfld.long 0x00 4.--7. "CH2CAPFLT,Channel 2 input capture filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 2.--3. "CH2CAPPSC,Channel 2 input capture prescaler" "0,1,2,3"
bitfld.long 0x00 0.--1. "CH2MS,Channel 2 mode selection" "0,1,2,3"
group.long 0x20++0x03
line.long 0x00 "CHCTL2,Channel control register 2"
bitfld.long 0x00 13. "CH3P,Channel 3 capture/compare function polarity" "0,1"
bitfld.long 0x00 12. "CH3EN,Channel 3 capture/compare function enable" "0,1"
bitfld.long 0x00 11. "CH2NP,Channel 2 complementary output polarity" "0,1"
bitfld.long 0x00 10. "CH2NEN,Channel 2 complementary output enable" "0,1"
newline
bitfld.long 0x00 9. "CH2P,Channel 2 capture/compare function polarity" "0,1"
bitfld.long 0x00 8. "CH2EN,Channel 2 capture/compare function enable" "0,1"
bitfld.long 0x00 7. "CH1NP,Channel 1 complementary output polarity" "0,1"
bitfld.long 0x00 6. "CH1NEN,Channel 1 complementary output enable" "0,1"
newline
bitfld.long 0x00 5. "CH1P,Channel 1 capture/compare function polarity" "0,1"
bitfld.long 0x00 4. "CH1EN,Channel 1 capture/compare function enable" "0,1"
bitfld.long 0x00 3. "CH0NP,Channel 0 complementary output polarity" "0,1"
bitfld.long 0x00 2. "CH0NEN,Channel 0 complementary output enable" "0,1"
newline
bitfld.long 0x00 1. "CH0P,Channel 0 capture/compare function polarity" "0,1"
bitfld.long 0x00 0. "CH0EN,Channel 0 capture/compare function enable" "0,1"
group.long 0x24++0x03
line.long 0x00 "CNT,counter"
hexmask.long.word 0x00 0.--15. 1. "CNT,current counter value"
group.long 0x28++0x03
line.long 0x00 "PSC,prescaler"
hexmask.long.word 0x00 0.--15. 1. "PSC,Prescaler value of the counter clock"
group.long 0x2C++0x03
line.long 0x00 "CAR,Counter auto reload register"
hexmask.long.word 0x00 0.--15. 1. "CARL,Counter auto reload value"
group.long 0x30++0x03
line.long 0x00 "CREP,Counter repetition register"
hexmask.long.byte 0x00 0.--7. 1. "CREP,Counter repetition value"
group.long 0x34++0x03
line.long 0x00 "CH0CV,Channel 0 capture/compare value register"
hexmask.long.word 0x00 0.--15. 1. "CH0VAL,Capture or compare value of channel0"
group.long 0x38++0x03
line.long 0x00 "CH1CV,Channel 1 capture/compare value register"
hexmask.long.word 0x00 0.--15. 1. "CH1VAL,Capture or compare value of channel1"
group.long 0x3C++0x03
line.long 0x00 "CH2CV,Channel 2 capture/compare value register"
hexmask.long.word 0x00 0.--15. 1. "CH2VAL,Capture or compare value of channel 2"
group.long 0x40++0x03
line.long 0x00 "CH3CV,Channel 3 capture/compare value register"
hexmask.long.word 0x00 0.--15. 1. "CH3VAL,Capture or compare value of channel 3"
group.long 0x44++0x03
line.long 0x00 "CCHP,channel complementary protection register"
bitfld.long 0x00 15. "POEN,Primary output enable" "0,1"
bitfld.long 0x00 14. "OAEN,Output automatic enable" "0,1"
bitfld.long 0x00 13. "BRKP,Break polarity" "0,1"
bitfld.long 0x00 12. "BRKEN,Break enable" "0,1"
newline
bitfld.long 0x00 11. "ROS,Run mode off-state configure" "0,1"
bitfld.long 0x00 10. "IOS,Idle mode off-state configure" "0,1"
bitfld.long 0x00 8.--9. "PROT,Complementary register protect control" "0,1,2,3"
hexmask.long.byte 0x00 0.--7. 1. "DTCFG,Dead time configure"
group.long 0x48++0x03
line.long 0x00 "DMACFG,DMA configuration register"
bitfld.long 0x00 8.--12. "DMATC,DMA transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "DMATA,DMA transfer access start address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x4C++0x03
line.long 0x00 "DMATB,DMA transfer buffer register"
hexmask.long.word 0x00 0.--15. 1. "DMATB,DMA transfer buffer"
group.long 0xFC++0x03
line.long 0x00 "CFG,Configuration register"
bitfld.long 0x00 1. "CHVSEL,Write CHxVAL register selection" "0,1"
bitfld.long 0x00 0. "OUTSEL,The output value selection" "0,1"
tree.end
tree "TIMER1"
base ad:0x40000000
group.long 0x00++0x03
line.long 0x00 "CTL0,control register 0"
bitfld.long 0x00 8.--9. "CKDIV,Clock division" "0,1,2,3"
bitfld.long 0x00 7. "ARSE,Auto-reload shadow enable" "0,1"
bitfld.long 0x00 5.--6. "CAM,Counter aligns mode selection" "0,1,2,3"
bitfld.long 0x00 4. "DIR,Direction" "0,1"
newline
bitfld.long 0x00 3. "SPM,Single pulse mode" "0,1"
bitfld.long 0x00 2. "UPS,Update source" "0,1"
bitfld.long 0x00 1. "UPDIS,Update disable" "0,1"
bitfld.long 0x00 0. "CEN,Counter enable" "0,1"
group.long 0x04++0x03
line.long 0x00 "CTL1,control register 1"
bitfld.long 0x00 7. "TI0S,Channel 0 trigger input selection" "0,1"
bitfld.long 0x00 4.--6. "MMC,Master mode control" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "DMAS,DMA request source selection" "0,1"
group.long 0x08++0x03
line.long 0x00 "SMCFG,slave mode control register"
bitfld.long 0x00 15. "ETP,External trigger polarity" "0,1"
bitfld.long 0x00 14. "SMC1,Part of SMC for enable External clock mode1" "0,1"
bitfld.long 0x00 12.--13. "ETPSC,External trigger prescaler" "0,1,2,3"
bitfld.long 0x00 8.--11. "ETFC,External trigger filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 7. "MSM,Master-slave mode" "0,1"
bitfld.long 0x00 4.--6. "TRGS,Trigger selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "SMC,Slave mode control" "0,1,2,3,4,5,6,7"
group.long 0x0C++0x03
line.long 0x00 "DMAINTEN,DMA/Interrupt enable register"
bitfld.long 0x00 14. "TRGDEN,Trigger DMA request enable" "0,1"
bitfld.long 0x00 12. "CH3DEN,Channel 3 capture/compare DMA request enable" "0,1"
bitfld.long 0x00 11. "CH2DEN,Channel 2 capture/compare DMA request enable" "0,1"
bitfld.long 0x00 10. "CH1DEN,Channel 1 capture/compare DMA request enable" "0,1"
newline
bitfld.long 0x00 9. "CH0DEN,Channel 0 capture/compare DMA request enable" "0,1"
bitfld.long 0x00 8. "UPDEN,Update DMA request enable" "0,1"
bitfld.long 0x00 6. "TRGIE,Trigger interrupt enable" "0,1"
bitfld.long 0x00 4. "CH3IE,Channel 3 capture/compare interrupt enable" "0,1"
newline
bitfld.long 0x00 3. "CH2IE,Channel 2 capture/compare interrupt enable" "0,1"
bitfld.long 0x00 2. "CH1IE,Channel 1 capture/compare interrupt enable" "0,1"
bitfld.long 0x00 1. "CH0IE,Channel 0 capture/compare interrupt enable" "0,1"
bitfld.long 0x00 0. "UPIE,Update interrupt enable" "0,1"
group.long 0x10++0x03
line.long 0x00 "INTF,interrupt flag register"
bitfld.long 0x00 12. "CH3OF,Channel 3 over capture flag" "0,1"
bitfld.long 0x00 11. "CH2OF,Channel 2 over capture flag" "0,1"
bitfld.long 0x00 10. "CH1OF,Channel 1 over capture flag" "0,1"
bitfld.long 0x00 9. "CH0OF,Channel 0 over capture flag" "0,1"
newline
bitfld.long 0x00 6. "TRGIF,Trigger interrupt flag" "0,1"
bitfld.long 0x00 4. "CH3IF,Channel 3 capture/compare interrupt enable" "0,1"
bitfld.long 0x00 3. "CH2IF,Channel 2 capture/compare interrupt enable" "0,1"
bitfld.long 0x00 2. "CH1IF,Channel 1 capture/compare interrupt flag" "0,1"
newline
bitfld.long 0x00 1. "CH0IF,Channel 0 capture/compare interrupt flag" "0,1"
bitfld.long 0x00 0. "UPIF,Update interrupt flag" "0,1"
wgroup.long 0x14++0x03
line.long 0x00 "SWEVG,event generation register"
bitfld.long 0x00 6. "TRGG,Trigger event generation" "0,1"
bitfld.long 0x00 4. "CH3G,Channel 3 capture or compare event generation" "0,1"
bitfld.long 0x00 3. "CH2G,Channel 2 capture or compare event generation" "0,1"
bitfld.long 0x00 2. "CH1G,Channel 1 capture or compare event generation" "0,1"
newline
bitfld.long 0x00 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
bitfld.long 0x00 0. "UPG,Update generation" "0,1"
group.long 0x18++0x03
line.long 0x00 "CHCTL0_Output,Channel control register 0 (output mode)"
bitfld.long 0x00 15. "CH1COMCEN,Channel 1 output compare clear enable" "0,1"
bitfld.long 0x00 12.--14. "CH1COMCTL,Channel 1 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 11. "CH1COMSEN,Channel 1 output compare shadow enable" "0,1"
bitfld.long 0x00 10. "CH1COMFEN,Channel 1 output compare fast enable" "0,1"
newline
bitfld.long 0x00 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
bitfld.long 0x00 7. "CH0COMCEN,Channel 0 output compare clear enable" "0,1"
bitfld.long 0x00 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
newline
bitfld.long 0x00 2. "CH0COMFEN,Channel 0 output compare fast enable" "0,1"
bitfld.long 0x00 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
group.long 0x18++0x03
line.long 0x00 "CHCTL0_Input,Channel control register 0 (input mode)"
bitfld.long 0x00 12.--15. "CH1CAPFLT,Channel 1 input capture filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "CH1CAPPSC,Channel 1 input capture prescaler" "0,1,2,3"
bitfld.long 0x00 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
bitfld.long 0x00 4.--7. "CH0CAPFLT,Channel 0 input capture filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
bitfld.long 0x00 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
group.long 0x1C++0x03
line.long 0x00 "CHCTL1_Output,Channel control register 1 (output mode)"
bitfld.long 0x00 15. "CH3COMCEN,Channel 3 output compare clear enable" "0,1"
bitfld.long 0x00 12.--14. "CH3COMCTL,Channel 3 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 11. "CH3COMSEN,Channel 3 output compare shadow enable" "0,1"
bitfld.long 0x00 10. "CH3COMFEN,Channel 3 output compare fast enable" "0,1"
newline
bitfld.long 0x00 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
bitfld.long 0x00 7. "CH2COMCEN,Channel 2 output compare clear enable" "0,1"
bitfld.long 0x00 4.--6. "CH2COMCTL,Channel 2 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "CH2COMSEN,Channel 2 compare output shadow enable" "0,1"
newline
bitfld.long 0x00 2. "CH2COMFEN,Channel 2 output compare fast enable" "0,1"
bitfld.long 0x00 0.--1. "CH2MS,Channel 2 I/O mode selection" "0,1,2,3"
group.long 0x1C++0x03
line.long 0x00 "CHCTL1_Input,Channel control register 1 (input mode)"
bitfld.long 0x00 12.--15. "CH3CAPFLT,Channel 3 input capture filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "CH3CAPPSC,Channel 3 input capture prescaler" "0,1,2,3"
bitfld.long 0x00 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
bitfld.long 0x00 4.--7. "CH2CAPFLT,Channel 2 input capture filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 2.--3. "CH2CAPPSC,Channel 2 input capture prescaler" "0,1,2,3"
bitfld.long 0x00 0.--1. "CH2MS,Channel 2 mode selection" "0,1,2,3"
group.long 0x20++0x03
line.long 0x00 "CHCTL2,Channel control register 2"
bitfld.long 0x00 15. "CH3NP,Channel 3 complementary output polarity" "0,1"
bitfld.long 0x00 13. "CH3P,Channel 3 capture/compare function polarity" "0,1"
bitfld.long 0x00 12. "CH3EN,Channel 3 capture/compare function enable" "0,1"
bitfld.long 0x00 11. "CH2NP,Channel 2 complementary output polarity" "0,1"
newline
bitfld.long 0x00 9. "CH2P,Channel 2 capture/compare function polarity" "0,1"
bitfld.long 0x00 8. "CH2EN,Channel 2 capture/compare function enable" "0,1"
bitfld.long 0x00 7. "CH1NP,Channel 1 complementary output polarity" "0,1"
bitfld.long 0x00 5. "CH1P,Channel 1 capture/compare function polarity" "0,1"
newline
bitfld.long 0x00 4. "CH1EN,Channel 1 capture/compare function enable" "0,1"
bitfld.long 0x00 3. "CH0NP,Channel 0 complementary output polarity" "0,1"
bitfld.long 0x00 1. "CH0P,Channel 0 capture/compare function polarity" "0,1"
bitfld.long 0x00 0. "CH0EN,Channel 0 capture/compare function enable" "0,1"
group.long 0x24++0x03
line.long 0x00 "CNT,Counter register"
hexmask.long 0x00 0.--31. 1. "CNT,counter value"
group.long 0x28++0x03
line.long 0x00 "PSC,Prescaler register"
hexmask.long.word 0x00 0.--15. 1. "PSC,Prescaler value of the counter clock"
group.long 0x2C++0x03
line.long 0x00 "CAR,Counter auto reload register"
hexmask.long 0x00 0.--31. 1. "CARL,Counter auto reload value"
group.long 0x34++0x03
line.long 0x00 "CH0CV,Channel 0 capture/compare value register"
hexmask.long 0x00 0.--31. 1. "CH0VAL,Capture or compare value of channel 0"
group.long 0x38++0x03
line.long 0x00 "CH1CV,Channel 1 capture/compare value register"
hexmask.long 0x00 0.--31. 1. "CH1VAL,Capture or compare value of channel1"
group.long 0x3C++0x03
line.long 0x00 "CH2CV,Channel 2 capture/compare value register"
hexmask.long 0x00 0.--31. 1. "CH2VAL,Capture or compare value of channel 2"
group.long 0x40++0x03
line.long 0x00 "CH3CV,Channel 3 capture/compare value register"
hexmask.long 0x00 0.--31. 1. "CH3VAL,Capture or compare value of channel 3"
group.long 0x48++0x03
line.long 0x00 "DMACFG,DMA configuration register"
bitfld.long 0x00 8.--12. "DMATC,DMA transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "DMATA,DMA transfer access start address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x4C++0x03
line.long 0x00 "DMATB,DMA transfer buffer register"
hexmask.long.word 0x00 0.--15. 1. "DMATB,DMA transfer buffer"
group.long 0xFC++0x03
line.long 0x00 "CFG,Configuration"
bitfld.long 0x00 1. "CHVSEL,Write CHxVAL register selection" "0,1"
tree.end
repeat 3. (list 2. 3. 4.) (list ad:0x40000400 ad:0x40000800 ad:0x40000C00)
tree "TIMER$1"
base $2
group.long 0x00++0x03
line.long 0x00 "CTL0,control register 0"
bitfld.long 0x00 8.--9. "CKDIV,Clock division" "0,1,2,3"
bitfld.long 0x00 7. "ARSE,Auto-reload shadow enable" "0,1"
bitfld.long 0x00 5.--6. "CAM,Counter aligns mode selection" "0,1,2,3"
bitfld.long 0x00 4. "DIR,Direction" "0,1"
newline
bitfld.long 0x00 3. "SPM,Single pulse mode" "0,1"
bitfld.long 0x00 2. "UPS,Update source" "0,1"
bitfld.long 0x00 1. "UPDIS,Update disable" "0,1"
bitfld.long 0x00 0. "CEN,Counter enable" "0,1"
group.long 0x04++0x03
line.long 0x00 "CTL1,control register 1"
bitfld.long 0x00 7. "TI0S,Channel 0 trigger input selection" "0,1"
bitfld.long 0x00 4.--6. "MMC,Master mode control" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "DMAS,DMA request source selection" "0,1"
group.long 0x08++0x03
line.long 0x00 "SMCFG,slave mode control register"
bitfld.long 0x00 15. "ETP,External trigger polarity" "0,1"
bitfld.long 0x00 14. "SMC1,Part of SMC for enable External clock mode1" "0,1"
bitfld.long 0x00 12.--13. "ETPSC,External trigger prescaler" "0,1,2,3"
bitfld.long 0x00 8.--11. "ETFC,External trigger filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 7. "MSM,Master-slave mode" "0,1"
bitfld.long 0x00 4.--6. "TRGS,Trigger selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "SMC,Slave mode control" "0,1,2,3,4,5,6,7"
group.long 0x0C++0x03
line.long 0x00 "DMAINTEN,DMA/Interrupt enable register"
bitfld.long 0x00 14. "TRGDEN,Trigger DMA request enable" "0,1"
bitfld.long 0x00 12. "CH3DEN,Channel 3 capture/compare DMA request enable" "0,1"
bitfld.long 0x00 11. "CH2DEN,Channel 2 capture/compare DMA request enable" "0,1"
bitfld.long 0x00 10. "CH1DEN,Channel 1 capture/compare DMA request enable" "0,1"
newline
bitfld.long 0x00 9. "CH0DEN,Channel 0 capture/compare DMA request enable" "0,1"
bitfld.long 0x00 8. "UPDEN,Update DMA request enable" "0,1"
bitfld.long 0x00 6. "TRGIE,Trigger interrupt enable" "0,1"
bitfld.long 0x00 4. "CH3IE,Channel 3 capture/compare interrupt enable" "0,1"
newline
bitfld.long 0x00 3. "CH2IE,Channel 2 capture/compare interrupt enable" "0,1"
bitfld.long 0x00 2. "CH1IE,Channel 1 capture/compare interrupt enable" "0,1"
bitfld.long 0x00 1. "CH0IE,Channel 0 capture/compare interrupt enable" "0,1"
bitfld.long 0x00 0. "UPIE,Update interrupt enable" "0,1"
group.long 0x10++0x03
line.long 0x00 "INTF,interrupt flag register"
bitfld.long 0x00 12. "CH3OF,Channel 3 over capture flag" "0,1"
bitfld.long 0x00 11. "CH2OF,Channel 2 over capture flag" "0,1"
bitfld.long 0x00 10. "CH1OF,Channel 1 over capture flag" "0,1"
bitfld.long 0x00 9. "CH0OF,Channel 0 over capture flag" "0,1"
newline
bitfld.long 0x00 6. "TRGIF,Trigger interrupt flag" "0,1"
bitfld.long 0x00 4. "CH3IF,Channel 3 capture/compare interrupt enable" "0,1"
bitfld.long 0x00 3. "CH2IF,Channel 2 capture/compare interrupt enable" "0,1"
bitfld.long 0x00 2. "CH1IF,Channel 1 capture/compare interrupt flag" "0,1"
newline
bitfld.long 0x00 1. "CH0IF,Channel 0 capture/compare interrupt flag" "0,1"
bitfld.long 0x00 0. "UPIF,Update interrupt flag" "0,1"
wgroup.long 0x14++0x03
line.long 0x00 "SWEVG,event generation register"
bitfld.long 0x00 6. "TRGG,Trigger event generation" "0,1"
bitfld.long 0x00 4. "CH3G,Channel 3 capture or compare event generation" "0,1"
bitfld.long 0x00 3. "CH2G,Channel 2 capture or compare event generation" "0,1"
bitfld.long 0x00 2. "CH1G,Channel 1 capture or compare event generation" "0,1"
newline
bitfld.long 0x00 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
bitfld.long 0x00 0. "UPG,Update generation" "0,1"
group.long 0x18++0x03
line.long 0x00 "CHCTL0_Output,Channel control register 0 (output mode)"
bitfld.long 0x00 15. "CH1COMCEN,Channel 1 output compare clear enable" "0,1"
bitfld.long 0x00 12.--14. "CH1COMCTL,Channel 1 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 11. "CH1COMSEN,Channel 1 output compare shadow enable" "0,1"
bitfld.long 0x00 10. "CH1COMFEN,Channel 1 output compare fast enable" "0,1"
newline
bitfld.long 0x00 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
bitfld.long 0x00 7. "CH0COMCEN,Channel 0 output compare clear enable" "0,1"
bitfld.long 0x00 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
newline
bitfld.long 0x00 2. "CH0COMFEN,Channel 0 output compare fast enable" "0,1"
bitfld.long 0x00 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
group.long 0x18++0x03
line.long 0x00 "CHCTL0_Input,Channel control register 0 (input mode)"
bitfld.long 0x00 12.--15. "CH1CAPFLT,Channel 1 input capture filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "CH1CAPPSC,Channel 1 input capture prescaler" "0,1,2,3"
bitfld.long 0x00 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
bitfld.long 0x00 4.--7. "CH0CAPFLT,Channel 0 input capture filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
bitfld.long 0x00 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
group.long 0x1C++0x03
line.long 0x00 "CHCTL1_Output,Channel control register 1 (output mode)"
bitfld.long 0x00 15. "CH3COMCEN,Channel 3 output compare clear enable" "0,1"
bitfld.long 0x00 12.--14. "CH3COMCTL,Channel 3 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 11. "CH3COMSEN,Channel 3 output compare shadow enable" "0,1"
bitfld.long 0x00 10. "CH3COMFEN,Channel 3 output compare fast enable" "0,1"
newline
bitfld.long 0x00 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
bitfld.long 0x00 7. "CH2COMCEN,Channel 2 output compare clear enable" "0,1"
bitfld.long 0x00 4.--6. "CH2COMCTL,Channel 2 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "CH2COMSEN,Channel 2 compare output shadow enable" "0,1"
newline
bitfld.long 0x00 2. "CH2COMFEN,Channel 2 output compare fast enable" "0,1"
bitfld.long 0x00 0.--1. "CH2MS,Channel 2 I/O mode selection" "0,1,2,3"
group.long 0x1C++0x03
line.long 0x00 "CHCTL1_Input,Channel control register 1 (input mode)"
bitfld.long 0x00 12.--15. "CH3CAPFLT,Channel 3 input capture filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "CH3CAPPSC,Channel 3 input capture prescaler" "0,1,2,3"
bitfld.long 0x00 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
bitfld.long 0x00 4.--7. "CH2CAPFLT,Channel 2 input capture filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 2.--3. "CH2CAPPSC,Channel 2 input capture prescaler" "0,1,2,3"
bitfld.long 0x00 0.--1. "CH2MS,Channel 2 mode selection" "0,1,2,3"
group.long 0x20++0x03
line.long 0x00 "CHCTL2,Channel control register 2"
bitfld.long 0x00 15. "CH3NP,Channel 3 complementary output polarity" "0,1"
bitfld.long 0x00 13. "CH3P,Channel 3 capture/compare function polarity" "0,1"
bitfld.long 0x00 12. "CH3EN,Channel 3 capture/compare function enable" "0,1"
bitfld.long 0x00 11. "CH2NP,Channel 2 complementary output polarity" "0,1"
newline
bitfld.long 0x00 9. "CH2P,Channel 2 capture/compare function polarity" "0,1"
bitfld.long 0x00 8. "CH2EN,Channel 2 capture/compare function enable" "0,1"
bitfld.long 0x00 7. "CH1NP,Channel 1 complementary output polarity" "0,1"
bitfld.long 0x00 5. "CH1P,Channel 1 capture/compare function polarity" "0,1"
newline
bitfld.long 0x00 4. "CH1EN,Channel 1 capture/compare function enable" "0,1"
bitfld.long 0x00 3. "CH0NP,Channel 0 complementary output polarity" "0,1"
bitfld.long 0x00 1. "CH0P,Channel 0 capture/compare function polarity" "0,1"
bitfld.long 0x00 0. "CH0EN,Channel 0 capture/compare function enable" "0,1"
group.long 0x24++0x03
line.long 0x00 "CNT,Counter register"
hexmask.long.word 0x00 0.--15. 1. "CNT,counter value"
group.long 0x28++0x03
line.long 0x00 "PSC,Prescaler register"
hexmask.long.word 0x00 0.--15. 1. "PSC,Prescaler value of the counter clock"
group.long 0x2C++0x03
line.long 0x00 "CAR,Counter auto reload register"
hexmask.long.word 0x00 0.--15. 1. "CARL,Counter auto reload value"
group.long 0x34++0x03
line.long 0x00 "CH0CV,Channel 0 capture/compare value register"
hexmask.long.word 0x00 0.--15. 1. "CH0VAL,Capture or compare value of channel 0"
group.long 0x38++0x03
line.long 0x00 "CH1CV,Channel 1 capture/compare value register"
hexmask.long.word 0x00 0.--15. 1. "CH1VAL,Capture or compare value of channel1"
group.long 0x3C++0x03
line.long 0x00 "CH2CV,Channel 2 capture/compare value register"
hexmask.long.word 0x00 0.--15. 1. "CH2VAL,Capture or compare value of channel 2"
group.long 0x40++0x03
line.long 0x00 "CH3CV,Channel 3 capture/compare value register"
hexmask.long.word 0x00 0.--15. 1. "CH3VAL,Capture or compare value of channel 3"
group.long 0x48++0x03
line.long 0x00 "DMACFG,DMA configuration register"
bitfld.long 0x00 8.--12. "DMATC,DMA transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "DMATA,DMA transfer access start address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x4C++0x03
line.long 0x00 "DMATB,DMA transfer buffer register"
hexmask.long.word 0x00 0.--15. 1. "DMATB,DMA transfer buffer"
group.long 0xFC++0x03
line.long 0x00 "CFG,Configuration"
bitfld.long 0x00 1. "CHVSEL,Write CHxVAL register selection" "0,1"
tree.end
repeat.end
repeat 2. (list 5. 6.) (list ad:0x40001000 ad:0x40001400)
tree "TIMER$1"
base $2
group.long 0x00++0x03
line.long 0x00 "CTL0,control register 0"
bitfld.long 0x00 7. "ARSE,Auto-reload shadow enable" "0,1"
bitfld.long 0x00 3. "SPM,Single pulse mode" "0,1"
bitfld.long 0x00 2. "UPS,Update source" "0,1"
bitfld.long 0x00 1. "UPDIS,Update disable" "0,1"
newline
bitfld.long 0x00 0. "CEN,Counter enable" "0,1"
group.long 0x04++0x03
line.long 0x00 "CTL1,control register 1"
bitfld.long 0x00 4.--6. "MMC,Master mode control" "0,1,2,3,4,5,6,7"
group.long 0x0C++0x03
line.long 0x00 "DMAINTEN,DMA/Interrupt enable register"
bitfld.long 0x00 8. "UPDEN,Update DMA request enable" "0,1"
bitfld.long 0x00 0. "UPIE,Update interrupt enable" "0,1"
group.long 0x10++0x03
line.long 0x00 "INTF,Interrupt flag register"
bitfld.long 0x00 0. "UPIF,Update interrupt flag" "0,1"
wgroup.long 0x14++0x03
line.long 0x00 "SWEVG,event generation register"
bitfld.long 0x00 0. "UPG,Update generation" "0,1"
group.long 0x24++0x03
line.long 0x00 "CNT,Counter register"
hexmask.long.word 0x00 0.--15. 1. "CNT,Low counter value"
group.long 0x28++0x03
line.long 0x00 "PSC,Prescaler register"
hexmask.long.word 0x00 0.--15. 1. "PSC,Prescaler value of the counter clock"
group.long 0x2C++0x03
line.long 0x00 "CAR,Counter auto reload register"
hexmask.long.word 0x00 0.--15. 1. "CARL,Counter auto reload value"
tree.end
repeat.end
tree "TIMER7"
base ad:0x40013400
group.long 0x00++0x03
line.long 0x00 "CTL0,control register 0"
bitfld.long 0x00 8.--9. "CKDIV,Clock division" "0,1,2,3"
bitfld.long 0x00 7. "ARSE,Auto-reload shadow enable" "0,1"
bitfld.long 0x00 5.--6. "CAM,Counter aligns mode selection" "0,1,2,3"
bitfld.long 0x00 4. "DIR,Direction" "0,1"
newline
bitfld.long 0x00 3. "SPM,Single pulse mode" "0,1"
bitfld.long 0x00 2. "UPS,Update source" "0,1"
bitfld.long 0x00 1. "UPDIS,Update disable" "0,1"
bitfld.long 0x00 0. "CEN,Counter enable" "0,1"
group.long 0x04++0x03
line.long 0x00 "CTL1,control register 1"
bitfld.long 0x00 14. "ISO3,Idle state of channel 3 output" "0,1"
bitfld.long 0x00 13. "ISO2N,Idle state of channel 2 complementary output" "0,1"
bitfld.long 0x00 12. "ISO2,Idle state of channel 2 output" "0,1"
bitfld.long 0x00 11. "ISO1N,Idle state of channel 1 complementary output" "0,1"
newline
bitfld.long 0x00 10. "ISO1,Idle state of channel 1 output" "0,1"
bitfld.long 0x00 9. "ISO0N,Idle state of channel 0 complementary output" "0,1"
bitfld.long 0x00 8. "ISO0,Idle state of channel 0 output" "0,1"
bitfld.long 0x00 7. "TI0S,Channel 0 trigger input selection" "0,1"
newline
bitfld.long 0x00 4.--6. "MMC,Master mode control" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "DMAS,DMA request source selection" "0,1"
bitfld.long 0x00 2. "CCUC,Commutation control shadow register update control" "0,1"
bitfld.long 0x00 0. "CCSE,Commutation control shadow enable" "0,1"
group.long 0x08++0x03
line.long 0x00 "SMCFG,slave mode configuration register"
bitfld.long 0x00 15. "ETP,External trigger polarity" "0,1"
bitfld.long 0x00 14. "SMC1,Part of SMC for enable External clock mode1" "0,1"
bitfld.long 0x00 12.--13. "ETPSC,External trigger prescaler" "0,1,2,3"
bitfld.long 0x00 8.--11. "ETFC,External trigger filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 7. "MSM,Master/Slave mode" "0,1"
bitfld.long 0x00 4.--6. "TRGS,Trigger selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "SMC,Slave mode selection" "0,1,2,3,4,5,6,7"
group.long 0x0C++0x03
line.long 0x00 "DMAINTEN,DMA/Interrupt enable register"
bitfld.long 0x00 14. "TRGDEN,Trigger DMA request enable" "0,1"
bitfld.long 0x00 13. "CMTDEN,Commutation DMA request enable" "0,1"
bitfld.long 0x00 12. "CH3DEN,Channel 3 capture/compare DMA request enable" "0,1"
bitfld.long 0x00 11. "CH2DEN,Channel 2 capture/compare DMA request enable" "0,1"
newline
bitfld.long 0x00 10. "CH1DEN,Channel 1 capture/compare DMA request enable" "0,1"
bitfld.long 0x00 9. "CH0DEN,Channel 0 capture/compare DMA request enable" "0,1"
bitfld.long 0x00 8. "UPDEN,Update DMA request enable" "0,1"
bitfld.long 0x00 7. "BRKIE,Break interrupt enable" "0,1"
newline
bitfld.long 0x00 6. "TRGIE,Trigger interrupt enable" "0,1"
bitfld.long 0x00 5. "CMTIE,commutation interrupt enable" "0,1"
bitfld.long 0x00 4. "CH3IE,Channel 3 capture/compare interrupt enable" "0,1"
bitfld.long 0x00 3. "CH2IE,Channel 2 capture/compare interrupt enable" "0,1"
newline
bitfld.long 0x00 2. "CH1IE,Channel 1 capture/compare interrupt enable" "0,1"
bitfld.long 0x00 1. "CH0IE,Channel 0 capture/compare interrupt enable" "0,1"
bitfld.long 0x00 0. "UPIE,Update interrupt enable" "0,1"
group.long 0x10++0x03
line.long 0x00 "INTF,Interrupt flag register"
bitfld.long 0x00 12. "CH3OF,Channel 3 over capture flag" "0,1"
bitfld.long 0x00 11. "CH2OF,Channel 2 over capture flag" "0,1"
bitfld.long 0x00 10. "CH1OF,Channel 1 over capture flag" "0,1"
bitfld.long 0x00 9. "CH0OF,Channel 0 over capture flag" "0,1"
newline
bitfld.long 0x00 7. "BRKIF,Break interrupt flag" "0,1"
bitfld.long 0x00 6. "TRGIF,Trigger interrupt flag" "0,1"
bitfld.long 0x00 5. "CMTIF,Channel commutation interrupt flag" "0,1"
bitfld.long 0x00 4. "CH3IF,Channel 3 capture/compare interrupt flag" "0,1"
newline
bitfld.long 0x00 3. "CH2IF,Channel 2 capture/compare interrupt flag" "0,1"
bitfld.long 0x00 2. "CH1IF,Channel 1 capture/compare interrupt flag" "0,1"
bitfld.long 0x00 1. "CH0IF,Channel 0 capture/compare interrupt flag" "0,1"
bitfld.long 0x00 0. "UPIF,Update interrupt flag" "0,1"
wgroup.long 0x14++0x03
line.long 0x00 "SWEVG,Software event generation register"
bitfld.long 0x00 7. "BRKG,Break event generation" "0,1"
bitfld.long 0x00 6. "TRGG,Trigger event generation" "0,1"
bitfld.long 0x00 5. "CMTG,Channel commutation event generation" "0,1"
bitfld.long 0x00 4. "CH3G,Channel 3 capture or compare event generation" "0,1"
newline
bitfld.long 0x00 3. "CH2G,Channel 2 capture or compare event generation" "0,1"
bitfld.long 0x00 2. "CH1G,Channel 1 capture or compare event generation" "0,1"
bitfld.long 0x00 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
bitfld.long 0x00 0. "UPG,Update event generation" "0,1"
group.long 0x18++0x03
line.long 0x00 "CHCTL0_Output,Channel control register 0 (output mode)"
bitfld.long 0x00 15. "CH1COMCEN,Channel 1 output compare clear enable" "0,1"
bitfld.long 0x00 12.--14. "CH1COMCTL,Channel 1 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 11. "CH1COMSEN,Channel 1 output compare shadow enable" "0,1"
bitfld.long 0x00 10. "CH1COMFEN,Channel 1 output compare fast enable" "0,1"
newline
bitfld.long 0x00 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
bitfld.long 0x00 7. "CH0COMCEN,Channel 0 output compare clear enable" "0,1"
bitfld.long 0x00 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
newline
bitfld.long 0x00 2. "CH0COMFEN,Channel 0 output compare fast enable" "0,1"
bitfld.long 0x00 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
group.long 0x18++0x03
line.long 0x00 "CHCTL0_Input,Channel control register 0 (input mode)"
bitfld.long 0x00 12.--15. "CH1CAPFLT,Channel 1 input capture filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "CH1CAPPSC,Channel 1 input capture prescaler" "0,1,2,3"
bitfld.long 0x00 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
bitfld.long 0x00 4.--7. "CH0CAPFLT,Channel 0 input capture filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
bitfld.long 0x00 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
group.long 0x1C++0x03
line.long 0x00 "CHCTL1_Output,Channel control register 1 (output mode)"
bitfld.long 0x00 15. "CH3COMCEN,Channel 3 output compare clear enable" "0,1"
bitfld.long 0x00 12.--14. "CH3COMCTL,Channel 3 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 11. "CH3COMSEN,Channel 3 output compare shadow enable" "0,1"
bitfld.long 0x00 10. "CH3COMFEN,Channel 3 output compare fast enable" "0,1"
newline
bitfld.long 0x00 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
bitfld.long 0x00 7. "CH2COMCEN,Channel 2 output compare clear enable" "0,1"
bitfld.long 0x00 4.--6. "CH2COMCTL,Channel 2 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "CH2COMSEN,Channel 2 compare output shadow enable" "0,1"
newline
bitfld.long 0x00 2. "CH2COMFEN,Channel 2 output compare fast enable" "0,1"
bitfld.long 0x00 0.--1. "CH2MS,Channel 2 I/O mode selection" "0,1,2,3"
group.long 0x1C++0x03
line.long 0x00 "CHCTL1_Input,Channel control register 1 (input mode)"
bitfld.long 0x00 12.--15. "CH3CAPFLT,Channel 3 input capture filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "CH3CAPPSC,Channel 3 input capture prescaler" "0,1,2,3"
bitfld.long 0x00 8.--9. "CH3MS,Channel 3 mode selection" "0,1,2,3"
bitfld.long 0x00 4.--7. "CH2CAPFLT,Channel 2 input capture filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 2.--3. "CH2CAPPSC,Channel 2 input capture prescaler" "0,1,2,3"
bitfld.long 0x00 0.--1. "CH2MS,Channel 2 mode selection" "0,1,2,3"
group.long 0x20++0x03
line.long 0x00 "CHCTL2,Channel control register 2"
bitfld.long 0x00 13. "CH3P,Channel 3 capture/compare function polarity" "0,1"
bitfld.long 0x00 12. "CH3EN,Channel 3 capture/compare function enable" "0,1"
bitfld.long 0x00 11. "CH2NP,Channel 2 complementary output polarity" "0,1"
bitfld.long 0x00 10. "CH2NEN,Channel 2 complementary output enable" "0,1"
newline
bitfld.long 0x00 9. "CH2P,Channel 2 capture/compare function polarity" "0,1"
bitfld.long 0x00 8. "CH2EN,Channel 2 capture/compare function enable" "0,1"
bitfld.long 0x00 7. "CH1NP,Channel 1 complementary output polarity" "0,1"
bitfld.long 0x00 6. "CH1NEN,Channel 1 complementary output enable" "0,1"
newline
bitfld.long 0x00 5. "CH1P,Channel 1 capture/compare function polarity" "0,1"
bitfld.long 0x00 4. "CH1EN,Channel 1 capture/compare function enable" "0,1"
bitfld.long 0x00 3. "CH0NP,Channel 0 complementary output polarity" "0,1"
bitfld.long 0x00 2. "CH0NEN,Channel 0 complementary output enable" "0,1"
newline
bitfld.long 0x00 1. "CH0P,Channel 0 capture/compare function polarity" "0,1"
bitfld.long 0x00 0. "CH0EN,Channel 0 capture/compare function enable" "0,1"
group.long 0x24++0x03
line.long 0x00 "CNT,counter"
hexmask.long.word 0x00 0.--15. 1. "CNT,current counter value"
group.long 0x28++0x03
line.long 0x00 "PSC,prescaler"
hexmask.long.word 0x00 0.--15. 1. "PSC,Prescaler value of the counter clock"
group.long 0x2C++0x03
line.long 0x00 "CAR,Counter auto reload register"
hexmask.long.word 0x00 0.--15. 1. "CARL,Counter auto reload value"
group.long 0x30++0x03
line.long 0x00 "CREP,Counter repetition register"
hexmask.long.byte 0x00 0.--7. 1. "CREP,Counter repetition value"
group.long 0x34++0x03
line.long 0x00 "CH0CV,Channel 0 capture/compare value register"
hexmask.long.word 0x00 0.--15. 1. "CH0VAL,Capture or compare value of channel0"
group.long 0x38++0x03
line.long 0x00 "CH1CV,Channel 1 capture/compare value register"
hexmask.long.word 0x00 0.--15. 1. "CH1VAL,Capture or compare value of channel1"
group.long 0x3C++0x03
line.long 0x00 "CH2CV,Channel 2 capture/compare value register"
hexmask.long.word 0x00 0.--15. 1. "CH2VAL,Capture or compare value of channel 2"
group.long 0x40++0x03
line.long 0x00 "CH3CV,Channel 3 capture/compare value register"
hexmask.long.word 0x00 0.--15. 1. "CH3VAL,Capture or compare value of channel 3"
group.long 0x44++0x03
line.long 0x00 "CCHP,channel complementary protection register"
bitfld.long 0x00 15. "POEN,Primary output enable" "0,1"
bitfld.long 0x00 14. "OAEN,Output automatic enable" "0,1"
bitfld.long 0x00 13. "BRKP,Break polarity" "0,1"
bitfld.long 0x00 12. "BRKEN,Break enable" "0,1"
newline
bitfld.long 0x00 11. "ROS,Run mode off-state configure" "0,1"
bitfld.long 0x00 10. "IOS,Idle mode off-state configure" "0,1"
bitfld.long 0x00 8.--9. "PROT,Complementary register protect control" "0,1,2,3"
hexmask.long.byte 0x00 0.--7. 1. "DTCFG,Dead time configure"
group.long 0x48++0x03
line.long 0x00 "DMACFG,DMA configuration register"
bitfld.long 0x00 8.--12. "DMATC,DMA transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "DMATA,DMA transfer access start address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x4C++0x03
line.long 0x00 "DMATB,DMA transfer buffer register"
hexmask.long.word 0x00 0.--15. 1. "DMATB,DMA transfer buffer"
group.long 0xFC++0x03
line.long 0x00 "CFG,Configuration register"
bitfld.long 0x00 1. "CHVSEL,Write CHxVAL register selection" "0,1"
bitfld.long 0x00 0. "OUTSEL,The output value selection" "0,1"
tree.end
tree "TIMER8"
base ad:0x40014C00
group.long 0x00++0x03
line.long 0x00 "CTL0,control register 0"
bitfld.long 0x00 8.--9. "CKDIV,Clock division" "0,1,2,3"
bitfld.long 0x00 7. "ARSE,Auto-reload shadow enable" "0,1"
bitfld.long 0x00 3. "SPM,Single pulse mode" "0,1"
bitfld.long 0x00 2. "UPS,Update source" "0,1"
newline
bitfld.long 0x00 1. "UPDIS,Update disable" "0,1"
bitfld.long 0x00 0. "CEN,Counter enable" "0,1"
group.long 0x08++0x03
line.long 0x00 "SMCFG,slave mode configuration register"
bitfld.long 0x00 7. "MSM,Master-slave mode" "0,1"
bitfld.long 0x00 4.--6. "TRGS,Trigger selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "SMC,Slave mode control" "0,1,2,3,4,5,6,7"
group.long 0x0C++0x03
line.long 0x00 "DMAINTEN,DMA and interrupt enable register"
bitfld.long 0x00 6. "TRGIE,Trigger interrupt enable" "0,1"
bitfld.long 0x00 2. "CH1IE,Channel 1 capture/compare interrupt enable" "0,1"
bitfld.long 0x00 1. "CH0IE,Channel 0 capture/compare interrupt enable" "0,1"
bitfld.long 0x00 0. "UPIE,Update interrupt enable" "0,1"
group.long 0x10++0x03
line.long 0x00 "INTF,interrupt flag register"
bitfld.long 0x00 10. "CH1OF,Channel 1 over capture flag" "0,1"
bitfld.long 0x00 9. "CH0OF,Channel 0 over capture flag" "0,1"
bitfld.long 0x00 6. "TRGIF,Trigger interrupt flag" "0,1"
bitfld.long 0x00 2. "CH1IF,Channel 1 capture/compare interrupt flag" "0,1"
newline
bitfld.long 0x00 1. "CH0IF,Channel 0 capture/compare interrupt flag" "0,1"
bitfld.long 0x00 0. "UPIF,Update interrupt flag" "0,1"
wgroup.long 0x14++0x03
line.long 0x00 "SWEVG,event generation register"
bitfld.long 0x00 6. "TRGG,Trigger event generation" "0,1"
bitfld.long 0x00 2. "CH1G,Channel 1 capture or compare event generation" "0,1"
bitfld.long 0x00 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
bitfld.long 0x00 0. "UPG,Update generation" "0,1"
group.long 0x18++0x03
line.long 0x00 "CHCTL0_Output,Channel control register 0 (output mode)"
bitfld.long 0x00 12.--14. "CH1COMCTL,Channel 1 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 11. "CH1COMSEN,Channel 1 output compare shadow enable" "0,1"
bitfld.long 0x00 10. "CH1COMFEN,Channel 1 output compare fast enable" "0,1"
bitfld.long 0x00 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
newline
bitfld.long 0x00 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
bitfld.long 0x00 2. "CH0COMFEN,Channel 0 output compare fast enable" "0,1"
bitfld.long 0x00 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
group.long 0x18++0x03
line.long 0x00 "CHCTL0_Input,Channel control register 0 (input mode)"
bitfld.long 0x00 12.--15. "CH1CAPFLT,Channel 1 input capture filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "CH1CAPPSC,Channel 1 input capture prescaler" "0,1,2,3"
bitfld.long 0x00 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
bitfld.long 0x00 4.--7. "CH0CAPFLT,Channel 0 input capture filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
bitfld.long 0x00 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
group.long 0x20++0x03
line.long 0x00 "CHCTL2,Channel control register 2"
bitfld.long 0x00 7. "CH1NP,Channel 1 complementary output polarity" "0,1"
bitfld.long 0x00 5. "CH1P,Channel 1 capture/compare function polarity" "0,1"
bitfld.long 0x00 4. "CH1EN,Channel 1 capture/compare function enable" "0,1"
bitfld.long 0x00 3. "CH0NP,Channel 0 complementary output polarity" "0,1"
newline
bitfld.long 0x00 1. "CH0P,Channel 0 capture/compare function polarity" "0,1"
bitfld.long 0x00 0. "CH0EN,Channel 0 capture/compare function enable" "0,1"
group.long 0x24++0x03
line.long 0x00 "CNT,Counter register"
hexmask.long.word 0x00 0.--15. 1. "CNT,current counter value"
group.long 0x28++0x03
line.long 0x00 "PSC,Prescaler register"
hexmask.long.word 0x00 0.--15. 1. "PSC,Prescaler value of the counter clock"
group.long 0x2C++0x03
line.long 0x00 "CAR,Counter auto reload register"
hexmask.long.word 0x00 0.--15. 1. "CARL,Counter auto reload value"
group.long 0x34++0x03
line.long 0x00 "CH0CV,Channel 0 capture/compare value register"
hexmask.long.word 0x00 0.--15. 1. "CH0VAL,Capture or compare value of channel0"
group.long 0x38++0x03
line.long 0x00 "CH1CV,Channel 1 capture/compare value register"
hexmask.long.word 0x00 0.--15. 1. "CH1VAL,Capture or compare value of channel1"
group.long 0xFC++0x03
line.long 0x00 "CFG,configuration register"
bitfld.long 0x00 1. "CHVSEL,Write CHxVAL register selection" "0,1"
tree.end
repeat 2. (list 9. 10.) (list ad:0x40015000 ad:0x40015400)
tree "TIMER$1"
base $2
group.long 0x00++0x03
line.long 0x00 "CTL0,control register 0"
bitfld.long 0x00 8.--9. "CKDIV,Clock division" "0,1,2,3"
bitfld.long 0x00 7. "ARSE,Auto-reload shadow enable" "0,1"
bitfld.long 0x00 2. "UPS,Update source" "0,1"
bitfld.long 0x00 1. "UPDIS,Update disable" "0,1"
newline
bitfld.long 0x00 0. "CEN,Counter enable" "0,1"
group.long 0x04++0x03
line.long 0x00 "CTL1,control register 1"
bitfld.long 0x00 4.--6. "MMC,Master mode control" "0,1,2,3,4,5,6,7"
group.long 0x0C++0x03
line.long 0x00 "DMAINTEN,DMA/Interrupt enable register"
bitfld.long 0x00 1. "CH0IE,Channel 0 capture/compare interrupt enable" "0,1"
bitfld.long 0x00 0. "UPIE,Update interrupt enable" "0,1"
group.long 0x10++0x03
line.long 0x00 "INTF,interrupt flag register"
bitfld.long 0x00 9. "CH0OF,Channel 0 over capture flag" "0,1"
bitfld.long 0x00 1. "CH0IF,Channel 0 capture/compare interrupt flag" "0,1"
bitfld.long 0x00 0. "UPIF,Update interrupt flag" "0,1"
wgroup.long 0x14++0x03
line.long 0x00 "SWEVG,event generation register"
bitfld.long 0x00 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
bitfld.long 0x00 0. "UPG,Update generation" "0,1"
group.long 0x18++0x03
line.long 0x00 "CHCTL0_Output,Channel control register 0 (output mode)"
bitfld.long 0x00 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
bitfld.long 0x00 2. "CH0COMFEN,Channel 0 output compare fast enable" "0,1"
bitfld.long 0x00 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
group.long 0x18++0x03
line.long 0x00 "CHCTL0_Input,Channel control register 0 ( (input mode)"
bitfld.long 0x00 4.--7. "CH0CAPFLT,Channel 0 input capture filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
bitfld.long 0x00 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
group.long 0x20++0x03
line.long 0x00 "CHCTL2,Channel control register 2"
bitfld.long 0x00 3. "CH0NP,Channel 0 complementary output polarity" "0,1"
bitfld.long 0x00 1. "CH0P,Channel 0 capture/compare polarity" "0,1"
bitfld.long 0x00 0. "CH0EN,Channel 0 capture/compare function enable" "0,1"
group.long 0x24++0x03
line.long 0x00 "CNT,Counter register"
hexmask.long.word 0x00 0.--15. 1. "CNT,current counter value"
group.long 0x28++0x03
line.long 0x00 "PSC,Prescaler register"
hexmask.long.word 0x00 0.--15. 1. "PSC,Prescaler value of the counter clock"
group.long 0x2C++0x03
line.long 0x00 "CAR,Counter auto reload register"
hexmask.long.word 0x00 0.--15. 1. "CARL,Counter auto reload value"
group.long 0x34++0x03
line.long 0x00 "CH0CV,Channel 0 capture/compare value register"
hexmask.long.word 0x00 0.--15. 1. "CH0VAL,Capture or compare value of channel 0"
group.long 0xFC++0x03
line.long 0x00 "CFG,configuration register"
bitfld.long 0x00 1. "CHVSEL,Write CHxVAL register selection" "0,1"
tree.end
repeat.end
tree "TIMER11"
base ad:0x40001800
group.long 0x00++0x03
line.long 0x00 "CTL0,control register 0"
bitfld.long 0x00 8.--9. "CKDIV,Clock division" "0,1,2,3"
bitfld.long 0x00 7. "ARSE,Auto-reload shadow enable" "0,1"
bitfld.long 0x00 3. "SPM,Single pulse mode" "0,1"
bitfld.long 0x00 2. "UPS,Update source" "0,1"
newline
bitfld.long 0x00 1. "UPDIS,Update disable" "0,1"
bitfld.long 0x00 0. "CEN,Counter enable" "0,1"
group.long 0x08++0x03
line.long 0x00 "SMCFG,slave mode configuration register"
bitfld.long 0x00 7. "MSM,Master-slave mode" "0,1"
bitfld.long 0x00 4.--6. "TRGS,Trigger selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "SMC,Slave mode control" "0,1,2,3,4,5,6,7"
group.long 0x0C++0x03
line.long 0x00 "DMAINTEN,DMA and interrupt enable register"
bitfld.long 0x00 6. "TRGIE,Trigger interrupt enable" "0,1"
bitfld.long 0x00 2. "CH1IE,Channel 1 capture/compare interrupt enable" "0,1"
bitfld.long 0x00 1. "CH0IE,Channel 0 capture/compare interrupt enable" "0,1"
bitfld.long 0x00 0. "UPIE,Update interrupt enable" "0,1"
group.long 0x10++0x03
line.long 0x00 "INTF,interrupt flag register"
bitfld.long 0x00 10. "CH1OF,Channel 1 over capture flag" "0,1"
bitfld.long 0x00 9. "CH0OF,Channel 0 over capture flag" "0,1"
bitfld.long 0x00 6. "TRGIF,Trigger interrupt flag" "0,1"
bitfld.long 0x00 2. "CH1IF,Channel 1 capture/compare interrupt flag" "0,1"
newline
bitfld.long 0x00 1. "CH0IF,Channel 0 capture/compare interrupt flag" "0,1"
bitfld.long 0x00 0. "UPIF,Update interrupt flag" "0,1"
wgroup.long 0x14++0x03
line.long 0x00 "SWEVG,event generation register"
bitfld.long 0x00 6. "TRGG,Trigger event generation" "0,1"
bitfld.long 0x00 2. "CH1G,Channel 1 capture or compare event generation" "0,1"
bitfld.long 0x00 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
bitfld.long 0x00 0. "UPG,Update generation" "0,1"
group.long 0x18++0x03
line.long 0x00 "CHCTL0_Output,Channel control register 0 (output mode)"
bitfld.long 0x00 12.--14. "CH1COMCTL,Channel 1 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 11. "CH1COMSEN,Channel 1 output compare shadow enable" "0,1"
bitfld.long 0x00 10. "CH1COMFEN,Channel 1 output compare fast enable" "0,1"
bitfld.long 0x00 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
newline
bitfld.long 0x00 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
bitfld.long 0x00 2. "CH0COMFEN,Channel 0 output compare fast enable" "0,1"
bitfld.long 0x00 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
group.long 0x18++0x03
line.long 0x00 "CHCTL0_Input,Channel control register 0 (input mode)"
bitfld.long 0x00 12.--15. "CH1CAPFLT,Channel 1 input capture filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "CH1CAPPSC,Channel 1 input capture prescaler" "0,1,2,3"
bitfld.long 0x00 8.--9. "CH1MS,Channel 1 mode selection" "0,1,2,3"
bitfld.long 0x00 4.--7. "CH0CAPFLT,Channel 0 input capture filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
bitfld.long 0x00 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
group.long 0x20++0x03
line.long 0x00 "CHCTL2,Channel control register 2"
bitfld.long 0x00 7. "CH1NP,Channel 1 complementary output polarity" "0,1"
bitfld.long 0x00 5. "CH1P,Channel 1 capture/compare function polarity" "0,1"
bitfld.long 0x00 4. "CH1EN,Channel 1 capture/compare function enable" "0,1"
bitfld.long 0x00 3. "CH0NP,Channel 0 complementary output polarity" "0,1"
newline
bitfld.long 0x00 1. "CH0P,Channel 0 capture/compare function polarity" "0,1"
bitfld.long 0x00 0. "CH0EN,Channel 0 capture/compare function enable" "0,1"
group.long 0x24++0x03
line.long 0x00 "CNT,Counter register"
hexmask.long.word 0x00 0.--15. 1. "CNT,current counter value"
group.long 0x28++0x03
line.long 0x00 "PSC,Prescaler register"
hexmask.long.word 0x00 0.--15. 1. "PSC,Prescaler value of the counter clock"
group.long 0x2C++0x03
line.long 0x00 "CAR,Counter auto reload register"
hexmask.long.word 0x00 0.--15. 1. "CARL,Counter auto reload value"
group.long 0x34++0x03
line.long 0x00 "CH0CV,Channel 0 capture/compare value register"
hexmask.long.word 0x00 0.--15. 1. "CH0VAL,Capture or compare value of channel0"
group.long 0x38++0x03
line.long 0x00 "CH1CV,Channel 1 capture/compare value register"
hexmask.long.word 0x00 0.--15. 1. "CH1VAL,Capture or compare value of channel1"
group.long 0xFC++0x03
line.long 0x00 "CFG,configuration register"
bitfld.long 0x00 1. "CHVSEL,Write CHxVAL register selection" "0,1"
tree.end
repeat 2. (list 12. 13.) (list ad:0x40001C00 ad:0x40002000)
tree "TIMER$1"
base $2
group.long 0x00++0x03
line.long 0x00 "CTL0,control register 0"
bitfld.long 0x00 8.--9. "CKDIV,Clock division" "0,1,2,3"
bitfld.long 0x00 7. "ARSE,Auto-reload shadow enable" "0,1"
bitfld.long 0x00 2. "UPS,Update source" "0,1"
bitfld.long 0x00 1. "UPDIS,Update disable" "0,1"
newline
bitfld.long 0x00 0. "CEN,Counter enable" "0,1"
group.long 0x04++0x03
line.long 0x00 "CTL1,control register 1"
bitfld.long 0x00 4.--6. "MMC,Master mode control" "0,1,2,3,4,5,6,7"
group.long 0x0C++0x03
line.long 0x00 "DMAINTEN,DMA/Interrupt enable register"
bitfld.long 0x00 1. "CH0IE,Channel 0 capture/compare interrupt enable" "0,1"
bitfld.long 0x00 0. "UPIE,Update interrupt enable" "0,1"
group.long 0x10++0x03
line.long 0x00 "INTF,interrupt flag register"
bitfld.long 0x00 9. "CH0OF,Channel 0 over capture flag" "0,1"
bitfld.long 0x00 1. "CH0IF,Channel 0 capture/compare interrupt flag" "0,1"
bitfld.long 0x00 0. "UPIF,Update interrupt flag" "0,1"
wgroup.long 0x14++0x03
line.long 0x00 "SWEVG,event generation register"
bitfld.long 0x00 1. "CH0G,Channel 0 capture or compare event generation" "0,1"
bitfld.long 0x00 0. "UPG,Update generation" "0,1"
group.long 0x18++0x03
line.long 0x00 "CHCTL0_Output,Channel control register 0 (output mode)"
bitfld.long 0x00 4.--6. "CH0COMCTL,Channel 0 compare output control" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "CH0COMSEN,Channel 0 compare output shadow enable" "0,1"
bitfld.long 0x00 2. "CH0COMFEN,Channel 0 output compare fast enable" "0,1"
bitfld.long 0x00 0.--1. "CH0MS,Channel 0 I/O mode selection" "0,1,2,3"
group.long 0x18++0x03
line.long 0x00 "CHCTL0_Input,Channel control register 0 ( (input mode)"
bitfld.long 0x00 4.--7. "CH0CAPFLT,Channel 0 input capture filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 2.--3. "CH0CAPPSC,Channel 0 input capture prescaler" "0,1,2,3"
bitfld.long 0x00 0.--1. "CH0MS,Channel 0 mode selection" "0,1,2,3"
group.long 0x20++0x03
line.long 0x00 "CHCTL2,Channel control register 2"
bitfld.long 0x00 3. "CH0NP,Channel 0 complementary output polarity" "0,1"
bitfld.long 0x00 1. "CH0P,Channel 0 capture/compare polarity" "0,1"
bitfld.long 0x00 0. "CH0EN,Channel 0 capture/compare function enable" "0,1"
group.long 0x24++0x03
line.long 0x00 "CNT,Counter register"
hexmask.long.word 0x00 0.--15. 1. "CNT,current counter value"
group.long 0x28++0x03
line.long 0x00 "PSC,Prescaler register"
hexmask.long.word 0x00 0.--15. 1. "PSC,Prescaler value of the counter clock"
group.long 0x2C++0x03
line.long 0x00 "CAR,Counter auto reload register"
hexmask.long.word 0x00 0.--15. 1. "CARL,Counter auto reload value"
group.long 0x34++0x03
line.long 0x00 "CH0CV,Channel 0 capture/compare value register"
hexmask.long.word 0x00 0.--15. 1. "CH0VAL,Capture or compare value of channel 0"
group.long 0xFC++0x03
line.long 0x00 "CFG,configuration register"
bitfld.long 0x00 1. "CHVSEL,Write CHxVAL register selection" "0,1"
tree.end
repeat.end
tree.end
sif cpuis("GD32E50*CL")
tree "TMU (Thermal Monitoring Unit)"
base ad:0x40080000
group.long 0x00++0x03
line.long 0x00 "IDATA0,Input data0 register"
hexmask.long 0x00 0.--31. 1. "IDATA0,IDATA0"
group.long 0x04++0x03
line.long 0x00 "IDATA1,Input data1 register"
hexmask.long 0x00 0.--31. 1. "IDATA1,IDATA1"
group.long 0x08++0x03
line.long 0x00 "CTL,Control register"
rbitfld.long 0x00 6. "CFIF,CFIF" "0,1"
bitfld.long 0x00 5. "CFIE,CFIE" "0,1"
bitfld.long 0x00 1.--4. "MODE,Set the mode of TMU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "TMUEN,start TMU module calculation" "0,1"
group.long 0x0C++0x03
line.long 0x00 "DATA0,data0 register"
hexmask.long 0x00 0.--31. 1. "DATA0,DATA0"
group.long 0x10++0x03
line.long 0x00 "DATA1,data1 register"
hexmask.long 0x00 0.--31. 1. "DATA1,DATA1"
rgroup.long 0x14++0x03
line.long 0x00 "STAT,Status register"
bitfld.long 0x00 1. "UDRF,The flag of underflow" "0,1"
bitfld.long 0x00 0. "OVRF,The flag of overflow" "0,1"
tree.end
endif
tree "UART (Universal Asynchronous Receiver/Transmitter)"
repeat 2. (list 3. 4.) (list ad:0x40004C00 ad:0x40005000)
tree "UART$1"
base $2
rgroup.long 0x00++0x03
line.long 0x00 "STAT0,Status register 0"
bitfld.long 0x00 8. "LBDF,LIN break detection flag" "0,1"
bitfld.long 0x00 7. "TBE,Transmit data buffer empty" "0,1"
bitfld.long 0x00 6. "TC,Transmission complete" "0,1"
bitfld.long 0x00 5. "RBNE,Read data buffer not empty" "0,1"
newline
bitfld.long 0x00 4. "IDLEF,IDLE frame detected flag" "0,1"
bitfld.long 0x00 3. "ORERR,Overrun error" "0,1"
bitfld.long 0x00 2. "NERR,Noise error flag" "0,1"
bitfld.long 0x00 1. "FERR,Frame error flag" "0,1"
newline
bitfld.long 0x00 0. "PERR,Parity error flag" "0,1"
group.long 0x04++0x03
line.long 0x00 "DATA,Data register"
hexmask.long.word 0x00 0.--8. 1. "DATA,Transmit or read data value"
group.long 0x08++0x03
line.long 0x00 "BAUD,Baud rate register"
hexmask.long.word 0x00 4.--15. 1. "INTDIV,Integer part of baud-rate divider"
bitfld.long 0x00 0.--3. "FRADIV,Fraction part of baud-rate divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x0C++0x03
line.long 0x00 "CTL0,Control register 0"
bitfld.long 0x00 15. "OVSMOD,Oversampe mode" "0,1"
bitfld.long 0x00 13. "UEN,USART enable" "0,1"
bitfld.long 0x00 12. "WL,Word length" "0,1"
bitfld.long 0x00 11. "WM,Wakeup method in mute mode" "0,1"
newline
bitfld.long 0x00 10. "PCEN,Parity check function enable" "0,1"
bitfld.long 0x00 9. "PM,Parity mode" "0,1"
bitfld.long 0x00 8. "PERRIE,Parity error interrupt enable" "0,1"
bitfld.long 0x00 7. "TBEIE,Transmitter buffer empty interrupt enable" "0,1"
newline
bitfld.long 0x00 6. "TCIE,Transmission complete interrupt enable" "0,1"
bitfld.long 0x00 5. "RBNEIE,Read data buffer not empty interrupt and overrun error interrupt enable" "0,1"
bitfld.long 0x00 4. "IDLEIE,IDLE line detected interrupt enable" "0,1"
bitfld.long 0x00 3. "TEN,Transmitter enable" "0,1"
newline
bitfld.long 0x00 2. "REN,Receiver enable" "0,1"
bitfld.long 0x00 1. "RWU,Receiver wakeup from mute mode" "0,1"
bitfld.long 0x00 0. "SBKCMD,Send break command" "0,1"
group.long 0x10++0x03
line.long 0x00 "CTL1,Control register 1"
bitfld.long 0x00 14. "LMEN,LIN mode enable" "0,1"
bitfld.long 0x00 12.--13. "STB,STOP bits length" "0,1,2,3"
bitfld.long 0x00 6. "LBDIE,LIN break detection interrupt enable" "0,1"
bitfld.long 0x00 5. "LBLEN,LIN break frame length" "0,1"
newline
bitfld.long 0x00 0.--3. "ADDR,Address of the USART" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x14++0x03
line.long 0x00 "CTL2,Control register 2"
bitfld.long 0x00 11. "OSB,One sample bit method enable" "0,1"
bitfld.long 0x00 7. "DENT,DMA request enable for transmission" "0,1"
bitfld.long 0x00 6. "DENR,DMA request enable for reception" "0,1"
bitfld.long 0x00 3. "HDEN,Half-duplex selection" "0,1"
newline
bitfld.long 0x00 2. "IRLP,IrDA low-power" "0,1"
bitfld.long 0x00 1. "IREN,IrDA mode enable" "0,1"
bitfld.long 0x00 0. "ERRIE,Error interrupt enable" "0,1"
group.long 0x18++0x03
line.long 0x00 "GP,Guard time and prescaler register"
hexmask.long.byte 0x00 8.--15. 1. "GUAT,Guard time value in Smartcard mode"
hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescaler value"
group.long 0xD0++0x03
line.long 0x00 "GDCTL,GD control register"
bitfld.long 0x00 16. "CDIE,Collision detected interrupt enable" "0,1"
bitfld.long 0x00 8. "CD,Collision detected status" "0,1"
bitfld.long 0x00 1. "CDEN,Collision detection enable" "0,1"
tree.end
repeat.end
tree.end
tree "USART (Universal synchronous asynchronous receiver transmitter)"
repeat 3. (list 0. 1. 2.) (list ad:0x40013800 ad:0x40004400 ad:0x40004800)
tree "USART$1"
base $2
rgroup.long 0x00++0x03
line.long 0x00 "STAT0,Status register 0"
bitfld.long 0x00 9. "CTSF,CTS change flag" "0,1"
bitfld.long 0x00 8. "LBDF,LIN break detection flag" "0,1"
bitfld.long 0x00 7. "TBE,Transmit data buffer empty" "0,1"
bitfld.long 0x00 6. "TC,Transmission complete" "0,1"
newline
bitfld.long 0x00 5. "RBNE,Read data buffer not empty" "0,1"
bitfld.long 0x00 4. "IDLEF,IDLE frame detected flag" "0,1"
bitfld.long 0x00 3. "ORERR,Overrun error" "0,1"
bitfld.long 0x00 2. "NERR,Noise error flag" "0,1"
newline
bitfld.long 0x00 1. "FERR,Frame error flag" "0,1"
bitfld.long 0x00 0. "PERR,Parity error flag" "0,1"
group.long 0x04++0x03
line.long 0x00 "DATA,Data register"
hexmask.long.word 0x00 0.--8. 1. "DATA,Transmit or read data value"
group.long 0x08++0x03
line.long 0x00 "BAUD,Baud rate register"
hexmask.long.word 0x00 4.--15. 1. "INTDIV,Integer part of baud-rate divider"
bitfld.long 0x00 0.--3. "FRADIV,Fraction part of baud-rate divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x0C++0x03
line.long 0x00 "CTL0,Control register 0"
bitfld.long 0x00 15. "OVSMOD,Oversampe mode" "0,1"
bitfld.long 0x00 13. "UEN,USART enable" "0,1"
bitfld.long 0x00 12. "WL,Word length" "0,1"
bitfld.long 0x00 11. "WM,Wakeup method in mute mode" "0,1"
newline
bitfld.long 0x00 10. "PCEN,Parity check function enable" "0,1"
bitfld.long 0x00 9. "PM,Parity mode" "0,1"
bitfld.long 0x00 8. "PERRIE,Parity error interrupt enable" "0,1"
bitfld.long 0x00 7. "TBEIE,Transmitter buffer empty interrupt enable" "0,1"
newline
bitfld.long 0x00 6. "TCIE,Transmission complete interrupt enable" "0,1"
bitfld.long 0x00 5. "RBNEIE,Read data buffer not empty interrupt and overrun error interrupt enable" "0,1"
bitfld.long 0x00 4. "IDLEIE,IDLE line detected interrupt enable" "0,1"
bitfld.long 0x00 3. "TEN,Transmitter enable" "0,1"
newline
bitfld.long 0x00 2. "REN,Receiver enable" "0,1"
bitfld.long 0x00 1. "RWU,Receiver wakeup from mute mode" "0,1"
bitfld.long 0x00 0. "SBKCMD,Send break command" "0,1"
group.long 0x10++0x03
line.long 0x00 "CTL1,Control register 1"
bitfld.long 0x00 14. "LMEN,LIN mode enable" "0,1"
bitfld.long 0x00 12.--13. "STB,STOP bits length" "0,1,2,3"
bitfld.long 0x00 11. "CKEN,CK pin enable" "0,1"
bitfld.long 0x00 10. "CPL,Clock polarity" "0,1"
newline
bitfld.long 0x00 9. "CPH,Clock phase" "0,1"
bitfld.long 0x00 8. "CLEN,CK Length" "0,1"
bitfld.long 0x00 6. "LBDIE,LIN break detection interrupt enable" "0,1"
bitfld.long 0x00 5. "LBLEN,LIN break frame length" "0,1"
newline
bitfld.long 0x00 0.--3. "ADDR,Address of the USART" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x14++0x03
line.long 0x00 "CTL2,Control register 2"
bitfld.long 0x00 11. "OSB,One sample bit method" "0,1"
bitfld.long 0x00 10. "CTSIE,CTS interrupt enable" "0,1"
bitfld.long 0x00 9. "CTSEN,CTS enable" "0,1"
bitfld.long 0x00 8. "RTSEN,RTS enable" "0,1"
newline
bitfld.long 0x00 7. "DENT,DMA request enable for transmission" "0,1"
bitfld.long 0x00 6. "DENR,DMA request enable for reception" "0,1"
bitfld.long 0x00 5. "SCEN,Smartcard mode enable" "0,1"
bitfld.long 0x00 4. "NKEN,Smartcard NACK enable" "0,1"
newline
bitfld.long 0x00 3. "HDEN,Half-duplex selection" "0,1"
bitfld.long 0x00 2. "IRLP,IrDA low-power" "0,1"
bitfld.long 0x00 1. "IREN,IrDA mode enable" "0,1"
bitfld.long 0x00 0. "ERRIE,Error interrupt enable" "0,1"
group.long 0x18++0x03
line.long 0x00 "GP,Guard time and prescaler register"
hexmask.long.byte 0x00 8.--15. 1. "GUAT,Guard time value in Smartcard mode"
hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescaler value"
group.long 0x80++0x03
line.long 0x00 "CTL3,Control register 3"
bitfld.long 0x00 11. "MSBF,Most significant bit first" "0,1"
bitfld.long 0x00 10. "DINV,Data bit level inversion" "0,1"
bitfld.long 0x00 9. "TINV,TX pin level inversion" "0,1"
bitfld.long 0x00 8. "RINV,RX pin level inversion" "0,1"
newline
bitfld.long 0x00 5. "EBIE,Interrupt enable bit of end of block event" "0,1"
bitfld.long 0x00 4. "RTIE,Interrupt enable bit of receive timeout event" "0,1"
bitfld.long 0x00 1.--3. "SCRTNUM,Smartcard auto-retry number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "RTEN,Receiver timeout enable" "0,1"
group.long 0x84++0x03
line.long 0x00 "RT,Receiver timeout register"
hexmask.long.byte 0x00 24.--31. 1. "BL,Block Length"
hexmask.long.tbyte 0x00 0.--23. 1. "RT,Receiver timeout threshold"
group.long 0x88++0x03
line.long 0x00 "STAT1,Status register 1"
rbitfld.long 0x00 16. "BSY,Busy flag" "0,1"
bitfld.long 0x00 12. "EBF,End of block flag" "0,1"
bitfld.long 0x00 11. "RTF,Receiver timeout flag" "0,1"
group.long 0xD0++0x03
line.long 0x00 "GDCTL,GD control register"
bitfld.long 0x00 16. "CDIE,Collision detected interrupt enable" "0,1"
bitfld.long 0x00 8. "CD,Collision detected status" "0,1"
bitfld.long 0x00 1. "CDEN,Collision detection enable" "0,1"
tree.end
repeat.end
tree "USART5"
base ad:0x40017000
group.long 0x00++0x03
line.long 0x00 "CTL0,Control register 0"
bitfld.long 0x00 27. "EBIE,End of Block interrupt enable" "0,1"
bitfld.long 0x00 26. "RTIE,Receiver timeout interrupt enable" "0,1"
bitfld.long 0x00 21.--25. "DEA,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "DED,Driver Enable de-assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15. "OVSMOD,Oversample mode" "0,1"
bitfld.long 0x00 14. "AMIE,ADDR match interrupt enable" "0,1"
bitfld.long 0x00 13. "MEN,Mute mode enable" "0,1"
bitfld.long 0x00 12. "WL,Word length" "0,1"
newline
bitfld.long 0x00 11. "WM,Wakeup method in mute mode" "0,1"
bitfld.long 0x00 10. "PCEN,Parity control enable" "0,1"
bitfld.long 0x00 9. "PM,Parity mode" "0,1"
bitfld.long 0x00 8. "PERRIE,Parity error interrupt enable" "0,1"
newline
bitfld.long 0x00 7. "TBEIE,Transmitter register empty interrupt enable" "0,1"
bitfld.long 0x00 6. "TCIE,Transmission complete interrupt enable" "0,1"
bitfld.long 0x00 5. "RBNEIE,Read data buffer not empty interrupt and overrun error interrupt enable" "0,1"
bitfld.long 0x00 4. "IDLEIE,IDLE line detected interrupt enable" "0,1"
newline
bitfld.long 0x00 3. "TEN,Transmitter enable" "0,1"
bitfld.long 0x00 2. "REN,Receiver enable" "0,1"
bitfld.long 0x00 1. "UESM,USART enable in Deep-sleep mode" "0,1"
bitfld.long 0x00 0. "UEN,USART enable" "0,1"
group.long 0x04++0x03
line.long 0x00 "CTL1,Control register 1"
hexmask.long.byte 0x00 24.--31. 1. "ADDR,Address of the USART terminal"
bitfld.long 0x00 23. "RTEN,Receiver timeout enable" "0,1"
bitfld.long 0x00 21.--22. "ABDM,Auto baud rate mode" "0,1,2,3"
bitfld.long 0x00 20. "ABDEN,Auto baud rate enable" "0,1"
newline
bitfld.long 0x00 19. "MSBF,Most significant bit first" "0,1"
bitfld.long 0x00 18. "DINV,Data bit level inversion" "0,1"
bitfld.long 0x00 17. "TINV,TX pin level inversion" "0,1"
bitfld.long 0x00 16. "RINV,RX pin level inversion" "0,1"
newline
bitfld.long 0x00 15. "STRP,Swap TX/RX pins" "0,1"
bitfld.long 0x00 14. "LMEN,LIN mode enable" "0,1"
bitfld.long 0x00 12.--13. "STB,STOP bits length" "0,1,2,3"
bitfld.long 0x00 11. "CKEN,CK pin enable" "0,1"
newline
bitfld.long 0x00 10. "CPL,Clock polarity" "0,1"
bitfld.long 0x00 9. "CPH,Clock phase" "0,1"
bitfld.long 0x00 8. "CLEN,CK length" "0,1"
bitfld.long 0x00 6. "LBDIE,LIN break detection interrupt enable" "0,1"
newline
bitfld.long 0x00 5. "LBLEN,LIN break frame length" "0,1"
bitfld.long 0x00 4. "ADDM,Address detection mode" "0,1"
group.long 0x08++0x03
line.long 0x00 "CTL2,Control register 2"
bitfld.long 0x00 22. "WUIE,Wakeup from Deep-sleep mode interrupt enable" "0,1"
bitfld.long 0x00 20.--21. "WUM,Wakeup mode from Deep-sleep mode" "0,1,2,3"
bitfld.long 0x00 17.--19. "SCRTNUM,Smartcard auto-retry number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 15. "DEP,Driver enable polarity mode" "0,1"
newline
bitfld.long 0x00 14. "DEM,Driver enable mode" "0,1"
bitfld.long 0x00 13. "DDRE,Disable DMA on reception error" "0,1"
bitfld.long 0x00 12. "OVRD,Overrun disable" "0,1"
bitfld.long 0x00 11. "OSB,One sample bit method" "0,1"
newline
bitfld.long 0x00 10. "CTSIE,CTS interrupt enable" "0,1"
bitfld.long 0x00 9. "CTSEN,CTS enable" "0,1"
bitfld.long 0x00 8. "RTSEN,RTS enable" "0,1"
bitfld.long 0x00 7. "DENT,DMA enable for transmission" "0,1"
newline
bitfld.long 0x00 6. "DENR,DMA enable for reception" "0,1"
bitfld.long 0x00 5. "SCEN,Smartcard mode enable" "0,1"
bitfld.long 0x00 4. "NKEN,NACK enable in Smartcard mode" "0,1"
bitfld.long 0x00 3. "HDEN,Half-duplex enable" "0,1"
newline
bitfld.long 0x00 2. "IRLP,IrDA low-power" "0,1"
bitfld.long 0x00 1. "IREN,IrDA mode enable" "0,1"
bitfld.long 0x00 0. "ERRIE,Error interrupt enable" "0,1"
group.long 0x0C++0x03
line.long 0x00 "BAUD,Baud rate generator register"
hexmask.long.word 0x00 4.--15. 1. "BRR_4_15,Integer of baud-rate divider"
bitfld.long 0x00 0.--3. "BRR_0_3,Fraction of baud-rate divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x03
line.long 0x00 "GP,Prescaler and guard time configuration register"
hexmask.long.byte 0x00 8.--15. 1. "GUAT,Guard time value in smartcard mode"
hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescaler value for dividing the system clock"
group.long 0x14++0x03
line.long 0x00 "RT,Receiver timeout register"
hexmask.long.byte 0x00 24.--31. 1. "BL,Block Length"
hexmask.long.tbyte 0x00 0.--23. 1. "RT,Receiver timeout threshold"
wgroup.long 0x18++0x03
line.long 0x00 "CMD,Command register (USART_CMD)"
bitfld.long 0x00 4. "TXFCMD,Transmit data flush request" "0,1"
bitfld.long 0x00 3. "RXFCMD,Receive data flush command" "0,1"
bitfld.long 0x00 2. "MMCMD,Mute mode command" "0,1"
bitfld.long 0x00 1. "SBKCMD,Send break command" "0,1"
newline
bitfld.long 0x00 0. "ABDCMD,Auto baudrate detection command" "0,1"
rgroup.long 0x1C++0x03
line.long 0x00 "STAT,Status register"
bitfld.long 0x00 22. "REA,Receive enable acknowledge flag" "0,1"
bitfld.long 0x00 21. "TEA,Transmit enable acknowledge flag" "0,1"
bitfld.long 0x00 20. "WUF,Wakeup from Deep-sleep mode flag" "0,1"
bitfld.long 0x00 19. "RWU,Receiver wakeup from mute mode" "0,1"
newline
bitfld.long 0x00 18. "SBF,Send break flag" "0,1"
bitfld.long 0x00 17. "AMF,ADDR match flag" "0,1"
bitfld.long 0x00 16. "BSY,Busy flag" "0,1"
bitfld.long 0x00 15. "ABDF,Auto baudrate detection flag" "0,1"
newline
bitfld.long 0x00 14. "ABDE,Auto baudrate detection error" "0,1"
bitfld.long 0x00 12. "EBF,End of block flag" "0,1"
bitfld.long 0x00 11. "RTF,Receiver timeout flag" "0,1"
bitfld.long 0x00 10. "CTS,CTS level" "0,1"
newline
bitfld.long 0x00 9. "CTSF,CTS change flag" "0,1"
bitfld.long 0x00 8. "LBDF,LIN break detected flag" "0,1"
bitfld.long 0x00 7. "TBE,Transmit data register empty" "0,1"
bitfld.long 0x00 6. "TC,Transmission completed" "0,1"
newline
bitfld.long 0x00 5. "RBNE,Read data buffer not empty" "0,1"
bitfld.long 0x00 4. "IDLEF,IDLE line detected flag" "0,1"
bitfld.long 0x00 3. "ORERR,Overrun error" "0,1"
bitfld.long 0x00 2. "NERR,Noise error flag" "0,1"
newline
bitfld.long 0x00 1. "FERR,Frame error flag" "0,1"
bitfld.long 0x00 0. "PERR,Parity error flag" "0,1"
wgroup.long 0x20++0x03
line.long 0x00 "INTC,Interrupt status clear register"
bitfld.long 0x00 20. "WUC,Wakeup from Deep-sleep mode clear" "0,1"
bitfld.long 0x00 17. "AMC,ADDR match clear" "0,1"
bitfld.long 0x00 12. "EBC,End of block clear" "0,1"
bitfld.long 0x00 11. "RTC,Receiver timeout clear" "0,1"
newline
bitfld.long 0x00 9. "CTSC,CTS change clear" "0,1"
bitfld.long 0x00 8. "LBDC,LIN break detected clear" "0,1"
bitfld.long 0x00 6. "TCC,Transmission complete clear" "0,1"
bitfld.long 0x00 4. "IDLEC,Idle line detected clear" "0,1"
newline
bitfld.long 0x00 3. "OREC,Overrun error clear" "0,1"
bitfld.long 0x00 2. "NEC,Noise detected clear" "0,1"
bitfld.long 0x00 1. "FEC,Frame error flag clear" "0,1"
bitfld.long 0x00 0. "PEC,Parity error clear" "0,1"
rgroup.long 0x24++0x03
line.long 0x00 "RDATA,Receive data register ("
hexmask.long.word 0x00 0.--8. 1. "RDATA,Receive Data value"
group.long 0x28++0x03
line.long 0x00 "TDATA,Transmit data register"
hexmask.long.word 0x00 0.--8. 1. "TDATA,Transmit Data value"
group.long 0xC0++0x03
line.long 0x00 "CHC,USART coherence control register"
bitfld.long 0x00 8. "EPERR,Early parity error flag" "0,1"
bitfld.long 0x00 0. "HCM,Hardware flow control coherence mode" "0,1"
group.long 0xD0++0x03
line.long 0x00 "RFCS,receive FIFO control and status register"
bitfld.long 0x00 15. "RFFINT,Receive FIFO full interrupt flag" "0,1"
rbitfld.long 0x00 12.--14. "RFCNT,Receive FIFO counter number" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 11. "RFF,Receive FIFO full flag" "0,1"
rbitfld.long 0x00 10. "RFE,Receive FIFO empty flag" "0,1"
newline
bitfld.long 0x00 9. "RFFIE,Receive FIFO full interrupt enable" "0,1"
bitfld.long 0x00 8. "RFEN,Receive FIFO enable" "0,1"
bitfld.long 0x00 0. "ELNACK,Early NACK when smartcard mode is selected" "0,1"
tree.end
tree.end
sif cpuis("GD32E50*HD")
tree "USBD (Universal Serial Bus Device)"
base ad:0x40005C00
group.word 0x00++0x01
line.word 0x00 "EP0CS,endpoint 0 register"
bitfld.word 0x00 15. "RX_ST,Correct transfer for reception" "0,1"
bitfld.word 0x00 14. "RX_DTG,Data Toggle for reception transfers" "0,1"
bitfld.word 0x00 12.--13. "RX_STA,Status bits for reception transfers" "0,1,2,3"
bitfld.word 0x00 11. "SETUP,Setup transaction completed" "0,1"
newline
bitfld.word 0x00 9.--10. "EP_CTL,Endpoint type" "0,1,2,3"
bitfld.word 0x00 8. "EP_KCTL,Endpoint kind" "0,1"
bitfld.word 0x00 7. "TX_ST,Correct Transfer for transmission" "0,1"
bitfld.word 0x00 6. "TX_DTG,Data PID Toggle for transmission transfers" "0,1"
newline
bitfld.word 0x00 4.--5. "TX_STA,Status bits for transmission transfers" "0,1,2,3"
bitfld.word 0x00 0.--3. "EP_AR,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x04++0x01
line.word 0x00 "EP1CS,endpoint 1 register"
bitfld.word 0x00 15. "RX_ST,Correct transfer for reception" "0,1"
bitfld.word 0x00 14. "RX_DTG,Data Toggle for reception transfers" "0,1"
bitfld.word 0x00 12.--13. "RX_STA,Status bits for reception transfers" "0,1,2,3"
bitfld.word 0x00 11. "SETUP,Setup transaction completed" "0,1"
newline
bitfld.word 0x00 9.--10. "EP_CTL,Endpoint type" "0,1,2,3"
bitfld.word 0x00 8. "EP_KCTL,Endpoint kind" "0,1"
bitfld.word 0x00 7. "TX_ST,Correct Transfer for transmission" "0,1"
bitfld.word 0x00 6. "TX_DTG,Data Toggle for transmission transfers" "0,1"
newline
bitfld.word 0x00 4.--5. "TX_STA,Status bits for transmission transfers" "0,1,2,3"
bitfld.word 0x00 0.--3. "EP_AR,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x08++0x01
line.word 0x00 "EP2CS,endpoint 2 register"
bitfld.word 0x00 15. "RX_ST,Correct transfer for reception" "0,1"
bitfld.word 0x00 14. "RX_DTG,Data Toggle for reception transfers" "0,1"
bitfld.word 0x00 12.--13. "RX_STA,Status bits for reception transfers" "0,1,2,3"
bitfld.word 0x00 11. "SETUP,Setup transaction completed" "0,1"
newline
bitfld.word 0x00 9.--10. "EP_CTL,Endpoint type" "0,1,2,3"
bitfld.word 0x00 8. "EP_KCTL,Endpoint kind" "0,1"
bitfld.word 0x00 7. "TX_ST,Correct Transfer for transmission" "0,1"
bitfld.word 0x00 6. "TX_DTG,Data Toggle for transmission transfers" "0,1"
newline
bitfld.word 0x00 4.--5. "TX_STA,Status bits for transmission transfers" "0,1,2,3"
bitfld.word 0x00 0.--3. "EP_AR,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x0C++0x01
line.word 0x00 "EP3CS,endpoint 3 register"
bitfld.word 0x00 15. "RX_ST,Correct transfer for reception" "0,1"
bitfld.word 0x00 14. "RX_DTG,Data Toggle for reception transfers" "0,1"
bitfld.word 0x00 12.--13. "RX_STA,Status bits for reception transfers" "0,1,2,3"
bitfld.word 0x00 11. "SETUP,Setup transaction completed" "0,1"
newline
bitfld.word 0x00 9.--10. "EP_CTL,Endpoint type" "0,1,2,3"
bitfld.word 0x00 8. "EP_KCTL,Endpoint kind" "0,1"
bitfld.word 0x00 7. "TX_ST,Correct Transfer for transmission" "0,1"
bitfld.word 0x00 6. "TX_DTG,Data Toggle for transmission transfers" "0,1"
newline
bitfld.word 0x00 4.--5. "TX_STA,Status bits for transmission transfers" "0,1,2,3"
bitfld.word 0x00 0.--3. "EP_AR,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x10++0x01
line.word 0x00 "EP4CS,endpoint 4 register"
bitfld.word 0x00 15. "RX_ST,Correct transfer for reception" "0,1"
bitfld.word 0x00 14. "RX_DTG,Data Toggle for reception transfers" "0,1"
bitfld.word 0x00 12.--13. "RX_STA,Status bits for reception transfers" "0,1,2,3"
bitfld.word 0x00 11. "SETUP,Setup transaction completed" "0,1"
newline
bitfld.word 0x00 9.--10. "EP_CTL,Endpoint type" "0,1,2,3"
bitfld.word 0x00 8. "EP_KCTL,Endpoint kind" "0,1"
bitfld.word 0x00 7. "TX_ST,Correct Transfer for transmission" "0,1"
bitfld.word 0x00 6. "TX_DTG,Data Toggle for transmission transfers" "0,1"
newline
bitfld.word 0x00 4.--5. "TX_STA,Status bits for transmission transfers" "0,1,2,3"
bitfld.word 0x00 0.--3. "EP_AR,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x14++0x01
line.word 0x00 "EP5CS,endpoint 5 register"
bitfld.word 0x00 15. "RX_ST,Correct transfer for reception" "0,1"
bitfld.word 0x00 14. "RX_DTG,Data Toggle for reception transfers" "0,1"
bitfld.word 0x00 12.--13. "RX_STA,Status bits for reception transfers" "0,1,2,3"
bitfld.word 0x00 11. "SETUP,Setup transaction completed" "0,1"
newline
bitfld.word 0x00 9.--10. "EP_CTL,Endpoint type" "0,1,2,3"
bitfld.word 0x00 8. "EP_KCTL,Endpoint kind" "0,1"
bitfld.word 0x00 7. "TX_ST,Correct Transfer for transmission" "0,1"
bitfld.word 0x00 6. "TX_DTG,Data Toggle for transmission transfers" "0,1"
newline
bitfld.word 0x00 4.--5. "TX_STA,Status bits for transmission transfers" "0,1,2,3"
bitfld.word 0x00 0.--3. "EP_AR,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x18++0x01
line.word 0x00 "EP6CS,endpoint 6 register"
bitfld.word 0x00 15. "RX_ST,Correct transfer for reception" "0,1"
bitfld.word 0x00 14. "RX_DTG,Data Toggle for reception transfers" "0,1"
bitfld.word 0x00 12.--13. "RX_STA,Status bits for reception transfers" "0,1,2,3"
bitfld.word 0x00 11. "SETUP,Setup transaction completed" "0,1"
newline
bitfld.word 0x00 9.--10. "EP_CTL,Endpoint type" "0,1,2,3"
bitfld.word 0x00 8. "EP_KCTL,Endpoint kind" "0,1"
bitfld.word 0x00 7. "TX_ST,Correct Transfer for transmission" "0,1"
bitfld.word 0x00 6. "TX_DTG,Data Toggle for transmission transfers" "0,1"
newline
bitfld.word 0x00 4.--5. "TX_STA,Status bits for transmission transfers" "0,1,2,3"
bitfld.word 0x00 0.--3. "EP_AR,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x1C++0x01
line.word 0x00 "EP7CS,endpoint 7 register"
bitfld.word 0x00 15. "RX_ST,Correct transfer for reception" "0,1"
bitfld.word 0x00 14. "RX_DTG,Data Toggle for reception transfers" "0,1"
bitfld.word 0x00 12.--13. "RX_STA,Status bits for reception transfers" "0,1,2,3"
bitfld.word 0x00 11. "SETUP,Setup transaction completed" "0,1"
newline
bitfld.word 0x00 9.--10. "EP_CTL,Endpoint type" "0,1,2,3"
bitfld.word 0x00 8. "EP_KCTL,Endpoint kind" "0,1"
bitfld.word 0x00 7. "TX_ST,Correct Transfer for transmission" "0,1"
bitfld.word 0x00 6. "TX_DTG,Data Toggle for transmission transfers" "0,1"
newline
bitfld.word 0x00 4.--5. "TX_STA,Status bits for transmission transfers" "0,1,2,3"
bitfld.word 0x00 0.--3. "EP_AR,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x40++0x01
line.word 0x00 "CTL,control register"
bitfld.word 0x00 15. "STIE,Successful transfer interrupt enable" "0,1"
bitfld.word 0x00 14. "PMOUIE,Packet memory area over / underrun interrupt enable" "0,1"
bitfld.word 0x00 13. "ERRIE,Error interrupt mask" "0,1"
bitfld.word 0x00 12. "WKUPIE,Wakeup interrupt enable" "0,1"
newline
bitfld.word 0x00 11. "SPSIE,Suspend mode interrupt mask" "0,1"
bitfld.word 0x00 10. "RSTIE,USB reset interrupt mask" "0,1"
bitfld.word 0x00 9. "SOFIE,Start of frame interrupt mask" "0,1"
bitfld.word 0x00 8. "ESOFIE,Expected start of frame interrupt enable" "0,1"
newline
bitfld.word 0x00 7. "L1REQIE,LPM L1 state request interrupt enable" "0,1"
bitfld.word 0x00 5. "L1RSREQ,LPM L1 resume request" "0,1"
bitfld.word 0x00 4. "RSREQ,Resume request" "0,1"
bitfld.word 0x00 3. "SETSPS,Set suspend" "0,1"
newline
bitfld.word 0x00 2. "LOWM,Low-power mode" "0,1"
bitfld.word 0x00 1. "CLOSE,Close state" "0,1"
bitfld.word 0x00 0. "SETRST,Set reset" "0,1"
group.word 0x44++0x01
line.word 0x00 "INTF,interrupt flag register"
bitfld.word 0x00 15. "STIF,Successful transfer interrupt flag" "0,1"
bitfld.word 0x00 14. "PMOUIF,Packet memory area over / underrun interrupt flag" "0,1"
bitfld.word 0x00 13. "ERRIF,Error interrupt flag" "0,1"
bitfld.word 0x00 12. "WKUPIF,Wakeup interrupt flag" "0,1"
newline
bitfld.word 0x00 11. "SPSIF,Suspend mode interrupt flag" "0,1"
bitfld.word 0x00 10. "RSTIF,reset interrupt flag" "0,1"
bitfld.word 0x00 9. "SOFIF,start of frame interrupt flag" "0,1"
bitfld.word 0x00 8. "ESOFIF,Expected start of frame interrupt flag" "0,1"
newline
bitfld.word 0x00 7. "L1REQ,LPM L1 transaction is successful" "0,1"
bitfld.word 0x00 4. "DIR,Direction of transaction" "0,1"
bitfld.word 0x00 0.--3. "EPNUM,Endpoint Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.word 0x48++0x01
line.word 0x00 "STAT,Status register"
bitfld.word 0x00 15. "RX_DP,Receive data + line status" "0,1"
bitfld.word 0x00 14. "RX_DM,Receive data - line status" "0,1"
bitfld.word 0x00 13. "LOCK,Locked the USB" "0,1"
bitfld.word 0x00 11.--12. "SOFLN,Lost SOF number" "0,1,2,3"
newline
hexmask.word 0x00 0.--10. 1. "FCNT,Frame number counter"
group.word 0x4C++0x01
line.word 0x00 "ADDR,device address register"
bitfld.word 0x00 7. "USBEN,USB device enable" "0,1"
hexmask.word.byte 0x00 0.--6. 1. "USBDAR,Device address"
group.word 0x50++0x01
line.word 0x00 "BADDR,Buffer address register"
hexmask.word 0x00 3.--15. 1. "BAR,Buffer address"
group.word 0x54++0x01
line.word 0x00 "LPMCS,USB LPM control and status register"
bitfld.word 0x00 4.--7. "BLSTAT,bLinkState value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 3. "REMWK,bRemoteWake value" "0,1"
bitfld.word 0x00 1. "LPMACK,LPM token acknowledge enable" "0,1"
bitfld.word 0x00 0. "LPMEN,LPM support enable" "0,1"
tree.end
endif
sif cpuis("GD32E50*CL")
tree "USBHS (USB on the go high speed host)"
tree "USBGS_HOST"
base ad:0x50000400
group.long 0x00++0x03
line.long 0x00 "HCTL,host configuration register (HCTL)"
bitfld.long 0x00 2. "SPDFSLS,Speed limited to FS and LS" "0,1"
group.long 0x04++0x03
line.long 0x00 "HFT,Host frame interval register"
hexmask.long.word 0x00 0.--15. 1. "FRI,Frame interval"
rgroup.long 0x08++0x03
line.long 0x00 "HFINFR,OTG_FS host frame number/frame time remaining register (HFINFR)"
hexmask.long.word 0x00 16.--31. 1. "FRT,Frame remaining time"
hexmask.long.word 0x00 0.--15. 1. "FRNUM,Frame number"
group.long 0x10++0x03
line.long 0x00 "HPTFQSTAT,Host periodic transmit FIFO/queue status register (HPTFQSTAT)"
hexmask.long.byte 0x00 24.--31. 1. "PTXREQT,Top of the periodic transmit request queue"
hexmask.long.byte 0x00 16.--23. 1. "PTXREQS,Periodic transmit request queue space available"
hexmask.long.word 0x00 0.--15. 1. "PTXFS,Periodic transmit data FIFO space available"
rgroup.long 0x14++0x03
line.long 0x00 "HACHINT,Host all channels interrupt register"
hexmask.long.word 0x00 0.--11. 1. "HACHINT,Host all channel interrupts"
group.long 0x18++0x03
line.long 0x00 "HACHINTEN,host all channels interrupt mask register"
hexmask.long.word 0x00 0.--11. 1. "CINTEN,Channel interrupt enable"
group.long 0x40++0x03
line.long 0x00 "HPCS,Host port control and status register (USBFS_HPCS)"
rbitfld.long 0x00 17.--18. "PS,Port speed" "0,1,2,3"
bitfld.long 0x00 13.--16. "PTEST,Port Test control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12. "PP,Port power" "0,1"
rbitfld.long 0x00 10.--11. "PLST,Port line status" "0,1,2,3"
newline
bitfld.long 0x00 8. "PRST,Port reset" "0,1"
bitfld.long 0x00 7. "PSP,Port suspend" "0,1"
bitfld.long 0x00 6. "PREM,Port resume" "0,1"
bitfld.long 0x00 3. "PEDC,Port enable/disable change" "0,1"
newline
bitfld.long 0x00 2. "PE,Port enable" "0,1"
bitfld.long 0x00 1. "PCD,Port connect detected" "0,1"
rbitfld.long 0x00 0. "PCST,Port connect status" "0,1"
group.long 0x100++0x03
line.long 0x00 "HCH0CTL,host channel-0 characteristics register (HCH0CTL)"
bitfld.long 0x00 31. "CEN,Channel enable" "0,1"
bitfld.long 0x00 30. "CDIS,Channel disable" "0,1"
bitfld.long 0x00 29. "ODDFRM,Odd frame" "0,1"
hexmask.long.byte 0x00 22.--28. 1. "DAR,Device address"
newline
bitfld.long 0x00 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
bitfld.long 0x00 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
bitfld.long 0x00 17. "LSD,Low-speed device" "0,1"
bitfld.long 0x00 15. "EPDIR,Endpoint direction" "0,1"
newline
bitfld.long 0x00 11.--14. "EPNUM,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--10. 1. "MPL,Maximum packet size"
group.long 0x120++0x03
line.long 0x00 "HCH1CTL,host channel-1 characteristics register (HCH1CTL)"
bitfld.long 0x00 31. "CEN,Channel enable" "0,1"
bitfld.long 0x00 30. "CDIS,Channel disable" "0,1"
bitfld.long 0x00 29. "ODDFRM,Odd frame" "0,1"
hexmask.long.byte 0x00 22.--28. 1. "DAR,Device address"
newline
bitfld.long 0x00 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
bitfld.long 0x00 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
bitfld.long 0x00 17. "LSD,Low-speed device" "0,1"
bitfld.long 0x00 15. "EPDIR,Endpoint direction" "0,1"
newline
bitfld.long 0x00 11.--14. "EPNUM,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--10. 1. "MPL,Maximum packet size"
group.long 0x140++0x03
line.long 0x00 "HCH2CTL,host channel-2 characteristics register (HCH2CTL)"
bitfld.long 0x00 31. "CEN,Channel enable" "0,1"
bitfld.long 0x00 30. "CDIS,Channel disable" "0,1"
bitfld.long 0x00 29. "ODDFRM,Odd frame" "0,1"
hexmask.long.byte 0x00 22.--28. 1. "DAR,Device address"
newline
bitfld.long 0x00 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
bitfld.long 0x00 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
bitfld.long 0x00 17. "LSD,Low-speed device" "0,1"
bitfld.long 0x00 15. "EPDIR,Endpoint direction" "0,1"
newline
bitfld.long 0x00 11.--14. "EPNUM,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--10. 1. "MPL,Maximum packet size"
group.long 0x160++0x03
line.long 0x00 "HCH3CTL,host channel-3 characteristics register (HCH3CTL)"
bitfld.long 0x00 31. "CEN,Channel enable" "0,1"
bitfld.long 0x00 30. "CDIS,Channel disable" "0,1"
bitfld.long 0x00 29. "ODDFRM,Odd frame" "0,1"
hexmask.long.byte 0x00 22.--28. 1. "DAR,Device address"
newline
bitfld.long 0x00 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
bitfld.long 0x00 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
bitfld.long 0x00 17. "LSD,Low-speed device" "0,1"
bitfld.long 0x00 15. "EPDIR,Endpoint direction" "0,1"
newline
bitfld.long 0x00 11.--14. "EPNUM,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--10. 1. "MPL,Maximum packet size"
group.long 0x180++0x03
line.long 0x00 "HCH4CTL,host channel-4 characteristics register (HCH4CTL)"
bitfld.long 0x00 31. "CEN,Channel enable" "0,1"
bitfld.long 0x00 30. "CDIS,Channel disable" "0,1"
bitfld.long 0x00 29. "ODDFRM,Odd frame" "0,1"
hexmask.long.byte 0x00 22.--28. 1. "DAR,Device address"
newline
bitfld.long 0x00 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
bitfld.long 0x00 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
bitfld.long 0x00 17. "LSD,Low-speed device" "0,1"
bitfld.long 0x00 15. "EPDIR,Endpoint direction" "0,1"
newline
bitfld.long 0x00 11.--14. "EPNUM,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--10. 1. "MPL,Maximum packet size"
group.long 0x1A0++0x03
line.long 0x00 "HCH5CTL,host channel-5 characteristics register (HCH5CTL)"
bitfld.long 0x00 31. "CEN,Channel enable" "0,1"
bitfld.long 0x00 30. "CDIS,Channel disable" "0,1"
bitfld.long 0x00 29. "ODDFRM,Odd frame" "0,1"
hexmask.long.byte 0x00 22.--28. 1. "DAR,Device address"
newline
bitfld.long 0x00 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
bitfld.long 0x00 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
bitfld.long 0x00 17. "LSD,Low-speed device" "0,1"
bitfld.long 0x00 15. "EPDIR,Endpoint direction" "0,1"
newline
bitfld.long 0x00 11.--14. "EPNUM,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--10. 1. "MPL,Maximum packet size"
group.long 0x1C0++0x03
line.long 0x00 "HCH6CTL,host channel-6 characteristics register (HCH6CTL)"
bitfld.long 0x00 31. "CEN,Channel enable" "0,1"
bitfld.long 0x00 30. "CDIS,Channel disable" "0,1"
bitfld.long 0x00 29. "ODDFRM,Odd frame" "0,1"
hexmask.long.byte 0x00 22.--28. 1. "DAR,Device address"
newline
bitfld.long 0x00 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
bitfld.long 0x00 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
bitfld.long 0x00 17. "LSD,Low-speed device" "0,1"
bitfld.long 0x00 15. "EPDIR,Endpoint direction" "0,1"
newline
bitfld.long 0x00 11.--14. "EPNUM,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--10. 1. "MPL,Maximum packet size"
group.long 0x1E0++0x03
line.long 0x00 "HCH7CTL,host channel-7 characteristics register (HCH7CTL)"
bitfld.long 0x00 31. "CEN,Channel enable" "0,1"
bitfld.long 0x00 30. "CDIS,Channel disable" "0,1"
bitfld.long 0x00 29. "ODDFRM,Odd frame" "0,1"
hexmask.long.byte 0x00 22.--28. 1. "DAR,Device address"
newline
bitfld.long 0x00 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
bitfld.long 0x00 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
bitfld.long 0x00 17. "LSD,Low-speed device" "0,1"
bitfld.long 0x00 15. "EPDIR,Endpoint direction" "0,1"
newline
bitfld.long 0x00 11.--14. "EPNUM,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--10. 1. "MPL,Maximum packet size"
group.long 0x200++0x03
line.long 0x00 "HCH8CTL,host channel-8 characteristics register (HCH8CTL)"
bitfld.long 0x00 31. "CEN,Channel enable" "0,1"
bitfld.long 0x00 30. "CDIS,Channel disable" "0,1"
bitfld.long 0x00 29. "ODDFRM,Odd frame" "0,1"
hexmask.long.byte 0x00 22.--28. 1. "DAR,Device address"
newline
bitfld.long 0x00 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
bitfld.long 0x00 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
bitfld.long 0x00 17. "LSD,Low-speed device" "0,1"
bitfld.long 0x00 15. "EPDIR,Endpoint direction" "0,1"
newline
bitfld.long 0x00 11.--14. "EPNUM,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--10. 1. "MPL,Maximum packet size"
group.long 0x220++0x03
line.long 0x00 "HCH9CTL,host channel-9 characteristics register (HCH9CTL)"
bitfld.long 0x00 31. "CEN,Channel enable" "0,1"
bitfld.long 0x00 30. "CDIS,Channel disable" "0,1"
bitfld.long 0x00 29. "ODDFRM,Odd frame" "0,1"
hexmask.long.byte 0x00 22.--28. 1. "DAR,Device address"
newline
bitfld.long 0x00 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
bitfld.long 0x00 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
bitfld.long 0x00 17. "LSD,Low-speed device" "0,1"
bitfld.long 0x00 15. "EPDIR,Endpoint direction" "0,1"
newline
bitfld.long 0x00 11.--14. "EPNUM,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--10. 1. "MPL,Maximum packet size"
group.long 0x240++0x03
line.long 0x00 "HCH10CTL,host channel-10 characteristics register (HCH10CTL)"
bitfld.long 0x00 31. "CEN,Channel enable" "0,1"
bitfld.long 0x00 30. "CDIS,Channel disable" "0,1"
bitfld.long 0x00 29. "ODDFRM,Odd frame" "0,1"
hexmask.long.byte 0x00 22.--28. 1. "DAR,Device address"
newline
bitfld.long 0x00 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
bitfld.long 0x00 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
bitfld.long 0x00 17. "LSD,Low-speed device" "0,1"
bitfld.long 0x00 15. "EPDIR,Endpoint direction" "0,1"
newline
bitfld.long 0x00 11.--14. "EPNUM,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--10. 1. "MPL,Maximum packet size"
group.long 0x260++0x03
line.long 0x00 "HCH11CTL,host channel-11 characteristics register (HCH11CTL)"
bitfld.long 0x00 31. "CEN,Channel enable" "0,1"
bitfld.long 0x00 30. "CDIS,Channel disable" "0,1"
bitfld.long 0x00 29. "ODDFRM,Odd frame" "0,1"
hexmask.long.byte 0x00 22.--28. 1. "DAR,Device address"
newline
bitfld.long 0x00 20.--21. "MPC,Multiple Packet Count" "0,1,2,3"
bitfld.long 0x00 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
bitfld.long 0x00 17. "LSD,Low-speed device" "0,1"
bitfld.long 0x00 15. "EPDIR,Endpoint direction" "0,1"
newline
bitfld.long 0x00 11.--14. "EPNUM,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--10. 1. "MPL,Maximum packet size"
group.long 0x108++0x03
line.long 0x00 "HCH0INTF,host channel-0 interrupt register (USBHS_HCHxINTF)"
bitfld.long 0x00 10. "DTER,Data toggle error" "0,1"
bitfld.long 0x00 9. "REQOVR,Request queue overrun" "0,1"
bitfld.long 0x00 8. "BBER,Babble error" "0,1"
bitfld.long 0x00 7. "USBER,USB bus error" "0,1"
newline
bitfld.long 0x00 6. "NYET,NYET" "0,1"
bitfld.long 0x00 5. "ACK,ACK response received/transmitted interrupt" "0,1"
bitfld.long 0x00 4. "NAK,NAK response received interrupt" "0,1"
bitfld.long 0x00 3. "STALL,STALL response received interrupt" "0,1"
newline
bitfld.long 0x00 2. "DMAER,DMA Error" "0,1"
bitfld.long 0x00 1. "CH,Channel halted" "0,1"
bitfld.long 0x00 0. "TF,Transfer finished" "0,1"
group.long 0x128++0x03
line.long 0x00 "HCH1INTF,host channel-1 interrupt register (HCH1INTF)"
bitfld.long 0x00 10. "DTER,Data toggle error" "0,1"
bitfld.long 0x00 9. "REQOVR,Request queue overrun" "0,1"
bitfld.long 0x00 8. "BBER,Babble error" "0,1"
bitfld.long 0x00 7. "USBER,USB bus error" "0,1"
newline
bitfld.long 0x00 6. "NYET,NYET" "0,1"
bitfld.long 0x00 5. "ACK,ACK response received/transmitted interrupt" "0,1"
bitfld.long 0x00 4. "NAK,NAK response received interrupt" "0,1"
bitfld.long 0x00 3. "STALL,STALL response received interrupt" "0,1"
newline
bitfld.long 0x00 2. "DMAER,DMA Error" "0,1"
bitfld.long 0x00 1. "CH,Channel halted" "0,1"
bitfld.long 0x00 0. "TF,Transfer finished" "0,1"
group.long 0x148++0x03
line.long 0x00 "HCH2INTF,host channel-2 interrupt register (HCH2INTF)"
bitfld.long 0x00 10. "DTER,Data toggle error" "0,1"
bitfld.long 0x00 9. "REQOVR,Request queue overrun" "0,1"
bitfld.long 0x00 8. "BBER,Babble error" "0,1"
bitfld.long 0x00 7. "USBER,USB bus error" "0,1"
newline
bitfld.long 0x00 6. "NYET,NYET" "0,1"
bitfld.long 0x00 5. "ACK,ACK response received/transmitted interrupt" "0,1"
bitfld.long 0x00 4. "NAK,NAK response received interrupt" "0,1"
bitfld.long 0x00 3. "STALL,STALL response received interrupt" "0,1"
newline
bitfld.long 0x00 2. "DMAER,DMA Error" "0,1"
bitfld.long 0x00 1. "CH,Channel halted" "0,1"
bitfld.long 0x00 0. "TF,Transfer finished" "0,1"
group.long 0x168++0x03
line.long 0x00 "HCH3INTF,host channel-3 interrupt register (HCH3INTF)"
bitfld.long 0x00 10. "DTER,Data toggle error" "0,1"
bitfld.long 0x00 9. "REQOVR,Request queue overrun" "0,1"
bitfld.long 0x00 8. "BBER,Babble error" "0,1"
bitfld.long 0x00 7. "USBER,USB bus error" "0,1"
newline
bitfld.long 0x00 6. "NYET,NYET" "0,1"
bitfld.long 0x00 5. "ACK,ACK response received/transmitted interrupt" "0,1"
bitfld.long 0x00 4. "NAK,NAK response received interrupt" "0,1"
bitfld.long 0x00 3. "STALL,STALL response received interrupt" "0,1"
newline
bitfld.long 0x00 2. "DMAER,DMA Error" "0,1"
bitfld.long 0x00 1. "CH,Channel halted" "0,1"
bitfld.long 0x00 0. "TF,Transfer finished" "0,1"
group.long 0x188++0x03
line.long 0x00 "HCH4INTF,host channel-4 interrupt register (HCH4INTF)"
bitfld.long 0x00 10. "DTER,Data toggle error" "0,1"
bitfld.long 0x00 9. "REQOVR,Request queue overrun" "0,1"
bitfld.long 0x00 8. "BBER,Babble error" "0,1"
bitfld.long 0x00 7. "USBER,USB bus error" "0,1"
newline
bitfld.long 0x00 6. "NYET,NYET" "0,1"
bitfld.long 0x00 5. "ACK,ACK response received/transmitted interrupt" "0,1"
bitfld.long 0x00 4. "NAK,NAK response received interrupt" "0,1"
bitfld.long 0x00 3. "STALL,STALL response received interrupt" "0,1"
newline
bitfld.long 0x00 2. "DMAER,DMA Error" "0,1"
bitfld.long 0x00 1. "CH,Channel halted" "0,1"
bitfld.long 0x00 0. "TF,Transfer finished" "0,1"
group.long 0x1A8++0x03
line.long 0x00 "HCH5INTF,host channel-5 interrupt register (HCH5INTF)"
bitfld.long 0x00 10. "DTER,Data toggle error" "0,1"
bitfld.long 0x00 9. "REQOVR,Request queue overrun" "0,1"
bitfld.long 0x00 8. "BBER,Babble error" "0,1"
bitfld.long 0x00 7. "USBER,USB bus error" "0,1"
newline
bitfld.long 0x00 6. "NYET,NYET" "0,1"
bitfld.long 0x00 5. "ACK,ACK response received/transmitted interrupt" "0,1"
bitfld.long 0x00 4. "NAK,NAK response received interrupt" "0,1"
bitfld.long 0x00 3. "STALL,STALL response received interrupt" "0,1"
newline
bitfld.long 0x00 2. "DMAER,DMA Error" "0,1"
bitfld.long 0x00 1. "CH,Channel halted" "0,1"
bitfld.long 0x00 0. "TF,Transfer finished" "0,1"
group.long 0x1C8++0x03
line.long 0x00 "HCH6INTF,host channel-6 interrupt register (HCH6INTF)"
bitfld.long 0x00 10. "DTER,Data toggle error" "0,1"
bitfld.long 0x00 9. "REQOVR,Request queue overrun" "0,1"
bitfld.long 0x00 8. "BBER,Babble error" "0,1"
bitfld.long 0x00 7. "USBER,USB bus error" "0,1"
newline
bitfld.long 0x00 6. "NYET,NYET" "0,1"
bitfld.long 0x00 5. "ACK,ACK response received/transmitted interrupt" "0,1"
bitfld.long 0x00 4. "NAK,NAK response received interrupt" "0,1"
bitfld.long 0x00 3. "STALL,STALL response received interrupt" "0,1"
newline
bitfld.long 0x00 2. "DMAER,DMA Error" "0,1"
bitfld.long 0x00 1. "CH,Channel halted" "0,1"
bitfld.long 0x00 0. "TF,Transfer finished" "0,1"
group.long 0x1E8++0x03
line.long 0x00 "HCH7INTF,host channel-7 interrupt register (HCH7INTF)"
bitfld.long 0x00 10. "DTER,Data toggle error" "0,1"
bitfld.long 0x00 9. "REQOVR,Request queue overrun" "0,1"
bitfld.long 0x00 8. "BBER,Babble error" "0,1"
bitfld.long 0x00 7. "USBER,USB bus error" "0,1"
newline
bitfld.long 0x00 6. "NYET,NYET" "0,1"
bitfld.long 0x00 5. "ACK,ACK response received/transmitted interrupt" "0,1"
bitfld.long 0x00 4. "NAK,NAK response received interrupt" "0,1"
bitfld.long 0x00 3. "STALL,STALL response received interrupt" "0,1"
newline
bitfld.long 0x00 2. "DMAER,DMA Error" "0,1"
bitfld.long 0x00 1. "CH,Channel halted" "0,1"
bitfld.long 0x00 0. "TF,Transfer finished" "0,1"
group.long 0x208++0x03
line.long 0x00 "HCH8INTF,host channel-8 interrupt register (HCH8INTF)"
bitfld.long 0x00 10. "DTER,Data toggle error" "0,1"
bitfld.long 0x00 9. "REQOVR,Request queue overrun" "0,1"
bitfld.long 0x00 8. "BBER,Babble error" "0,1"
bitfld.long 0x00 7. "USBER,USB bus error" "0,1"
newline
bitfld.long 0x00 6. "NYET,NYET" "0,1"
bitfld.long 0x00 5. "ACK,ACK response received/transmitted interrupt" "0,1"
bitfld.long 0x00 4. "NAK,NAK response received interrupt" "0,1"
bitfld.long 0x00 3. "STALL,STALL response received interrupt" "0,1"
newline
bitfld.long 0x00 2. "DMAER,DMA Error" "0,1"
bitfld.long 0x00 1. "CH,Channel halted" "0,1"
bitfld.long 0x00 0. "TF,Transfer finished" "0,1"
group.long 0x228++0x03
line.long 0x00 "HCH9INTF,host channel-9 interrupt register (HCH9INTF)"
bitfld.long 0x00 10. "DTER,Data toggle error" "0,1"
bitfld.long 0x00 9. "REQOVR,Request queue overrun" "0,1"
bitfld.long 0x00 8. "BBER,Babble error" "0,1"
bitfld.long 0x00 7. "USBER,USB bus error" "0,1"
newline
bitfld.long 0x00 6. "NYET,NYET" "0,1"
bitfld.long 0x00 5. "ACK,ACK response received/transmitted interrupt" "0,1"
bitfld.long 0x00 4. "NAK,NAK response received interrupt" "0,1"
bitfld.long 0x00 3. "STALL,STALL response received interrupt" "0,1"
newline
bitfld.long 0x00 2. "DMAER,DMA Error" "0,1"
bitfld.long 0x00 1. "CH,Channel halted" "0,1"
bitfld.long 0x00 0. "TF,Transfer finished" "0,1"
group.long 0x248++0x03
line.long 0x00 "HCH10INTF,host channel-10 interrupt register (HCH10INTF)"
bitfld.long 0x00 10. "DTER,Data toggle error" "0,1"
bitfld.long 0x00 9. "REQOVR,Request queue overrun" "0,1"
bitfld.long 0x00 8. "BBER,Babble error" "0,1"
bitfld.long 0x00 7. "USBER,USB bus error" "0,1"
newline
bitfld.long 0x00 6. "NYET,NYET" "0,1"
bitfld.long 0x00 5. "ACK,ACK response received/transmitted interrupt" "0,1"
bitfld.long 0x00 4. "NAK,NAK response received interrupt" "0,1"
bitfld.long 0x00 3. "STALL,STALL response received interrupt" "0,1"
newline
bitfld.long 0x00 2. "DMAER,DMA Error" "0,1"
bitfld.long 0x00 1. "CH,Channel halted" "0,1"
bitfld.long 0x00 0. "TF,Transfer finished" "0,1"
group.long 0x268++0x03
line.long 0x00 "HCH11INTF,host channel-11 interrupt register (HCH11INTF)"
bitfld.long 0x00 10. "DTER,Data toggle error" "0,1"
bitfld.long 0x00 9. "REQOVR,Request queue overrun" "0,1"
bitfld.long 0x00 8. "BBER,Babble error" "0,1"
bitfld.long 0x00 7. "USBER,USB bus error" "0,1"
newline
bitfld.long 0x00 6. "NYET,NYET" "0,1"
bitfld.long 0x00 5. "ACK,ACK response received/transmitted interrupt" "0,1"
bitfld.long 0x00 4. "NAK,NAK response received interrupt" "0,1"
bitfld.long 0x00 3. "STALL,STALL response received interrupt" "0,1"
newline
bitfld.long 0x00 2. "DMAER,DMA Error" "0,1"
bitfld.long 0x00 1. "CH,Channel halted" "0,1"
bitfld.long 0x00 0. "TF,Transfer finished" "0,1"
group.long 0x10C++0x03
line.long 0x00 "HCH0INTEN,host channel-0 interrupt enable register (HCH0INTEN)"
bitfld.long 0x00 10. "DTERIE,Data toggle error interrupt enable" "0,1"
bitfld.long 0x00 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
bitfld.long 0x00 8. "BBERIE,Babble error interrupt enable" "0,1"
bitfld.long 0x00 7. "USBERIE,USB bus error interrupt enable" "0,1"
newline
bitfld.long 0x00 6. "NYETIE,NYET interrupt enable" "0,1"
bitfld.long 0x00 5. "ACKIE,ACK interrupt enable" "0,1"
bitfld.long 0x00 4. "NAKIE,NAK interrupt enable" "0,1"
bitfld.long 0x00 3. "STALLIE,STALL interrupt enable" "0,1"
newline
bitfld.long 0x00 2. "DMAERIE,DMA Error interrupt enable" "0,1"
bitfld.long 0x00 1. "CHIE,Channel halted interrupt enable" "0,1"
bitfld.long 0x00 0. "TFIE,Transfer completed interrupt enable" "0,1"
group.long 0x12C++0x03
line.long 0x00 "HCH1INTEN,host channel-1 interrupt enable register (HCH1INTEN)"
bitfld.long 0x00 10. "DTERIE,Data toggle error interrupt enable" "0,1"
bitfld.long 0x00 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
bitfld.long 0x00 8. "BBERIE,Babble error interrupt enable" "0,1"
bitfld.long 0x00 7. "USBERIE,USB bus error interrupt enable" "0,1"
newline
bitfld.long 0x00 5. "ACKIE,ACK interrupt enable" "0,1"
bitfld.long 0x00 4. "NAKIE,NAK interrupt enable" "0,1"
bitfld.long 0x00 3. "STALLIE,STALL interrupt enable" "0,1"
bitfld.long 0x00 1. "CHIE,Channel halted interrupt enable" "0,1"
newline
bitfld.long 0x00 0. "TFIE,Transfer completed interrupt enable" "0,1"
group.long 0x14C++0x03
line.long 0x00 "HCH2INTEN,host channel-2 interrupt enable register (HCH2INTEN)"
bitfld.long 0x00 10. "DTERIE,Data toggle error interrupt enable" "0,1"
bitfld.long 0x00 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
bitfld.long 0x00 8. "BBERIE,Babble error interrupt enable" "0,1"
bitfld.long 0x00 7. "USBERIE,USB bus error interrupt enable" "0,1"
newline
bitfld.long 0x00 5. "ACKIE,ACK interrupt enable" "0,1"
bitfld.long 0x00 4. "NAKIE,NAK interrupt enable" "0,1"
bitfld.long 0x00 3. "STALLIE,STALL interrupt enable" "0,1"
bitfld.long 0x00 1. "CHIE,Channel halted interrupt enable" "0,1"
newline
bitfld.long 0x00 0. "TFIE,Transfer completed interrupt enable" "0,1"
group.long 0x16C++0x03
line.long 0x00 "HCH3INTEN,host channel-3 interrupt enable register (HCH3INTEN)"
bitfld.long 0x00 10. "DTERIE,Data toggle error interrupt enable" "0,1"
bitfld.long 0x00 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
bitfld.long 0x00 8. "BBERIE,Babble error interrupt enable" "0,1"
bitfld.long 0x00 7. "USBERIE,USB bus error interrupt enable" "0,1"
newline
bitfld.long 0x00 5. "ACKIE,ACK interrupt enable" "0,1"
bitfld.long 0x00 4. "NAKIE,NAK interrupt enable" "0,1"
bitfld.long 0x00 3. "STALLIE,STALL interrupt enable" "0,1"
bitfld.long 0x00 1. "CHIE,Channel halted interrupt enable" "0,1"
newline
bitfld.long 0x00 0. "TFIE,Transfer completed interrupt enable" "0,1"
group.long 0x18C++0x03
line.long 0x00 "HCH4INTEN,host channel-4 interrupt enable register (HCH4INTEN)"
bitfld.long 0x00 10. "DTERIE,Data toggle error interrupt enable" "0,1"
bitfld.long 0x00 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
bitfld.long 0x00 8. "BBERIE,Babble error interrupt enable" "0,1"
bitfld.long 0x00 7. "USBERIE,USB bus error interrupt enable" "0,1"
newline
bitfld.long 0x00 5. "ACKIE,ACK interrupt enable" "0,1"
bitfld.long 0x00 4. "NAKIE,NAK interrupt enable" "0,1"
bitfld.long 0x00 3. "STALLIE,STALL interrupt enable" "0,1"
bitfld.long 0x00 1. "CHIE,Channel halted interrupt enable" "0,1"
newline
bitfld.long 0x00 0. "TFIE,Transfer completed interrupt enable" "0,1"
group.long 0x1AC++0x03
line.long 0x00 "HCH5INTEN,host channel-5 interrupt enable register (HCH5INTEN)"
bitfld.long 0x00 10. "DTERIE,Data toggle error interrupt enable" "0,1"
bitfld.long 0x00 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
bitfld.long 0x00 8. "BBERIE,Babble error interrupt enable" "0,1"
bitfld.long 0x00 7. "USBERIE,USB bus error interrupt enable" "0,1"
newline
bitfld.long 0x00 5. "ACKIE,ACK interrupt enable" "0,1"
bitfld.long 0x00 4. "NAKIE,NAK interrupt enable" "0,1"
bitfld.long 0x00 3. "STALLIE,STALL interrupt enable" "0,1"
bitfld.long 0x00 1. "CHIE,Channel halted interrupt enable" "0,1"
newline
bitfld.long 0x00 0. "TFIE,Transfer completed interrupt enable" "0,1"
group.long 0x1CC++0x03
line.long 0x00 "HCH6INTEN,host channel-6 interrupt enable register (HCH6INTEN)"
bitfld.long 0x00 10. "DTERIE,Data toggle error interrupt enable" "0,1"
bitfld.long 0x00 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
bitfld.long 0x00 8. "BBERIE,Babble error interrupt enable" "0,1"
bitfld.long 0x00 7. "USBERIE,USB bus error interrupt enable" "0,1"
newline
bitfld.long 0x00 5. "ACKIE,ACK interrupt enable" "0,1"
bitfld.long 0x00 4. "NAKIE,NAK interrupt enable" "0,1"
bitfld.long 0x00 3. "STALLIE,STALL interrupt enable" "0,1"
bitfld.long 0x00 1. "CHIE,Channel halted interrupt enable" "0,1"
newline
bitfld.long 0x00 0. "TFIE,Transfer completed interrupt enable" "0,1"
group.long 0x1EC++0x03
line.long 0x00 "HCH7INTEN,host channel-7 interrupt enable register (HCH7INTEN)"
bitfld.long 0x00 10. "DTERIE,Data toggle error interrupt enable" "0,1"
bitfld.long 0x00 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
bitfld.long 0x00 8. "BBERIE,Babble error interrupt enable" "0,1"
bitfld.long 0x00 7. "USBERIE,USB bus error interrupt enable" "0,1"
newline
bitfld.long 0x00 5. "ACKIE,ACK interrupt enable" "0,1"
bitfld.long 0x00 4. "NAKIE,NAK interrupt enable" "0,1"
bitfld.long 0x00 3. "STALLIE,STALL interrupt enable" "0,1"
bitfld.long 0x00 1. "CHIE,Channel halted interrupt enable" "0,1"
newline
bitfld.long 0x00 0. "TFIE,Transfer completed interrupt enable" "0,1"
group.long 0x20C++0x03
line.long 0x00 "HCH8INTEN,host channel-8 interrupt enable register (HCH7INTEN)"
bitfld.long 0x00 10. "DTERIE,Data toggle error interrupt enable" "0,1"
bitfld.long 0x00 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
bitfld.long 0x00 8. "BBERIE,Babble error interrupt enable" "0,1"
bitfld.long 0x00 7. "USBERIE,USB bus error interrupt enable" "0,1"
newline
bitfld.long 0x00 5. "ACKIE,ACK interrupt enable" "0,1"
bitfld.long 0x00 4. "NAKIE,NAK interrupt enable" "0,1"
bitfld.long 0x00 3. "STALLIE,STALL interrupt enable" "0,1"
bitfld.long 0x00 1. "CHIE,Channel halted interrupt enable" "0,1"
newline
bitfld.long 0x00 0. "TFIE,Transfer completed interrupt enable" "0,1"
group.long 0x22C++0x03
line.long 0x00 "HCH9INTEN,host channel-9 interrupt enable register (HCH9INTEN)"
bitfld.long 0x00 10. "DTERIE,Data toggle error interrupt enable" "0,1"
bitfld.long 0x00 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
bitfld.long 0x00 8. "BBERIE,Babble error interrupt enable" "0,1"
bitfld.long 0x00 7. "USBERIE,USB bus error interrupt enable" "0,1"
newline
bitfld.long 0x00 5. "ACKIE,ACK interrupt enable" "0,1"
bitfld.long 0x00 4. "NAKIE,NAK interrupt enable" "0,1"
bitfld.long 0x00 3. "STALLIE,STALL interrupt enable" "0,1"
bitfld.long 0x00 1. "CHIE,Channel halted interrupt enable" "0,1"
newline
bitfld.long 0x00 0. "TFIE,Transfer completed interrupt enable" "0,1"
group.long 0x24C++0x03
line.long 0x00 "HCH10INTEN,host channel-10 interrupt enable register (HCH10INTEN)"
bitfld.long 0x00 10. "DTERIE,Data toggle error interrupt enable" "0,1"
bitfld.long 0x00 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
bitfld.long 0x00 8. "BBERIE,Babble error interrupt enable" "0,1"
bitfld.long 0x00 7. "USBERIE,USB bus error interrupt enable" "0,1"
newline
bitfld.long 0x00 5. "ACKIE,ACK interrupt enable" "0,1"
bitfld.long 0x00 4. "NAKIE,NAK interrupt enable" "0,1"
bitfld.long 0x00 3. "STALLIE,STALL interrupt enable" "0,1"
bitfld.long 0x00 1. "CHIE,Channel halted interrupt enable" "0,1"
newline
bitfld.long 0x00 0. "TFIE,Transfer completed interrupt enable" "0,1"
group.long 0x26C++0x03
line.long 0x00 "HCH11INTEN,host channel-11 interrupt enable register (HCH11INTEN)"
bitfld.long 0x00 10. "DTERIE,Data toggle error interrupt enable" "0,1"
bitfld.long 0x00 9. "REQOVRIE,request queue overrun interrupt enable" "0,1"
bitfld.long 0x00 8. "BBERIE,Babble error interrupt enable" "0,1"
bitfld.long 0x00 7. "USBERIE,USB bus error interrupt enable" "0,1"
newline
bitfld.long 0x00 5. "ACKIE,ACK interrupt enable" "0,1"
bitfld.long 0x00 4. "NAKIE,NAK interrupt enable" "0,1"
bitfld.long 0x00 3. "STALLIE,STALL interrupt enable" "0,1"
bitfld.long 0x00 1. "CHIE,Channel halted interrupt enable" "0,1"
newline
bitfld.long 0x00 0. "TFIE,Transfer completed interrupt enable" "0,1"
group.long 0x110++0x03
line.long 0x00 "HCH0LEN,host channel-0 transfer length register"
bitfld.long 0x00 31. "PING,PING token request" "0,1"
bitfld.long 0x00 29.--30. "DPID,Data PID" "0,1,2,3"
hexmask.long.word 0x00 19.--28. 1. "PCNT,Packet count"
hexmask.long.tbyte 0x00 0.--18. 1. "TLEN,Transfer length"
group.long 0x130++0x03
line.long 0x00 "HCH1LEN,host channel-1 transfer length register"
bitfld.long 0x00 31. "PING,PING token request" "0,1"
bitfld.long 0x00 29.--30. "DPID,Data PID" "0,1,2,3"
hexmask.long.word 0x00 19.--28. 1. "PCNT,Packet count"
hexmask.long.tbyte 0x00 0.--18. 1. "TLEN,Transfer length"
group.long 0x150++0x03
line.long 0x00 "HCH2LEN,host channel-2 transfer length register"
bitfld.long 0x00 31. "PING,PING token request" "0,1"
bitfld.long 0x00 29.--30. "DPID,Data PID" "0,1,2,3"
hexmask.long.word 0x00 19.--28. 1. "PCNT,Packet count"
hexmask.long.tbyte 0x00 0.--18. 1. "TLEN,Transfer length"
group.long 0x170++0x03
line.long 0x00 "HCH3LEN,host channel-3 transfer length register"
bitfld.long 0x00 31. "PING,PING token request" "0,1"
bitfld.long 0x00 29.--30. "DPID,Data PID" "0,1,2,3"
hexmask.long.word 0x00 19.--28. 1. "PCNT,Packet count"
hexmask.long.tbyte 0x00 0.--18. 1. "TLEN,Transfer length"
group.long 0x190++0x03
line.long 0x00 "HCH4LEN,host channel-4 transfer length register"
bitfld.long 0x00 31. "PING,PING token request" "0,1"
bitfld.long 0x00 29.--30. "DPID,Data PID" "0,1,2,3"
hexmask.long.word 0x00 19.--28. 1. "PCNT,Packet count"
hexmask.long.tbyte 0x00 0.--18. 1. "TLEN,Transfer length"
group.long 0x1B0++0x03
line.long 0x00 "HCH5LEN,host channel-5 transfer length register"
bitfld.long 0x00 31. "PING,PING token request" "0,1"
bitfld.long 0x00 29.--30. "DPID,Data PID" "0,1,2,3"
hexmask.long.word 0x00 19.--28. 1. "PCNT,Packet count"
hexmask.long.tbyte 0x00 0.--18. 1. "TLEN,Transfer length"
group.long 0x1D0++0x03
line.long 0x00 "HCH6LEN,host channel-6 transfer length register"
bitfld.long 0x00 31. "PING,PING token request" "0,1"
bitfld.long 0x00 29.--30. "DPID,Data PID" "0,1,2,3"
hexmask.long.word 0x00 19.--28. 1. "PCNT,Packet count"
hexmask.long.tbyte 0x00 0.--18. 1. "TLEN,Transfer length"
group.long 0x1F0++0x03
line.long 0x00 "HCH7LEN,host channel-7 transfer length register"
bitfld.long 0x00 31. "PING,PING token request" "0,1"
bitfld.long 0x00 29.--30. "DPID,Data PID" "0,1,2,3"
hexmask.long.word 0x00 19.--28. 1. "PCNT,Packet count"
hexmask.long.tbyte 0x00 0.--18. 1. "TLEN,Transfer length"
group.long 0x210++0x03
line.long 0x00 "HCH8LEN,host channel-8 transfer length register"
bitfld.long 0x00 31. "PING,PING token request" "0,1"
bitfld.long 0x00 29.--30. "DPID,Data PID" "0,1,2,3"
hexmask.long.word 0x00 19.--28. 1. "PCNT,Packet count"
hexmask.long.tbyte 0x00 0.--18. 1. "TLEN,Transfer length"
group.long 0x230++0x03
line.long 0x00 "HCH9LEN,host channel-9 transfer length register"
bitfld.long 0x00 31. "PING,PING token request" "0,1"
bitfld.long 0x00 29.--30. "DPID,Data PID" "0,1,2,3"
hexmask.long.word 0x00 19.--28. 1. "PCNT,Packet count"
hexmask.long.tbyte 0x00 0.--18. 1. "TLEN,Transfer length"
group.long 0x250++0x03
line.long 0x00 "HCH10LEN,host channel-10 transfer length register"
bitfld.long 0x00 31. "PING,PING token request" "0,1"
bitfld.long 0x00 29.--30. "DPID,Data PID" "0,1,2,3"
hexmask.long.word 0x00 19.--28. 1. "PCNT,Packet count"
hexmask.long.tbyte 0x00 0.--18. 1. "TLEN,Transfer length"
group.long 0x270++0x03
line.long 0x00 "HCH11LEN,host channel-11 transfer length register"
bitfld.long 0x00 31. "PING,PING token request" "0,1"
bitfld.long 0x00 29.--30. "DPID,Data PID" "0,1,2,3"
hexmask.long.word 0x00 19.--28. 1. "PCNT,Packet count"
hexmask.long.tbyte 0x00 0.--18. 1. "TLEN,Transfer length"
group.long 0x114++0x03
line.long 0x00 "HCH0DMAADDR,Host channel 0 DMA address register"
hexmask.long 0x00 0.--31. 1. "DMAADDR,DMA address"
group.long 0x134++0x03
line.long 0x00 "HCH1DMAADDR,Host channel 1 DMA address register"
hexmask.long 0x00 0.--31. 1. "DMAADDR,DMA address"
group.long 0x154++0x03
line.long 0x00 "HCH2DMAADDR,Host channel 2 DMA address register"
hexmask.long 0x00 0.--31. 1. "DMAADDR,DMA address"
group.long 0x174++0x03
line.long 0x00 "HCH3DMAADDR,Host channel 3 DMA address register"
hexmask.long 0x00 0.--31. 1. "DMAADDR,DMA address"
group.long 0x194++0x03
line.long 0x00 "HCH4DMAADDR,Host channel 4 DMA address register"
hexmask.long 0x00 0.--31. 1. "DMAADDR,DMA address"
group.long 0x1B4++0x03
line.long 0x00 "HCH5DMAADDR,Host channel 5 DMA address register"
hexmask.long 0x00 0.--31. 1. "DMAADDR,DMA address"
group.long 0x1D4++0x03
line.long 0x00 "HCH6DMAADDR,Host channel 6 DMA address register"
hexmask.long 0x00 0.--31. 1. "DMAADDR,DMA address"
group.long 0x1F4++0x03
line.long 0x00 "HCH7DMAADDR,Host channel 7 DMA address register"
hexmask.long 0x00 0.--31. 1. "DMAADDR,DMA address"
group.long 0x214++0x03
line.long 0x00 "HCH8DMAADDR,Host channel 8 DMA address register"
hexmask.long 0x00 0.--31. 1. "DMAADDR,DMA address"
group.long 0x234++0x03
line.long 0x00 "HCH9DMAADDR,Host channel 9 DMA address register"
hexmask.long 0x00 0.--31. 1. "DMAADDR,DMA address"
group.long 0x254++0x03
line.long 0x00 "HCH10DMAADDR,Host channel 10 DMA address register"
hexmask.long 0x00 0.--31. 1. "DMAADDR,DMA address"
group.long 0x274++0x03
line.long 0x00 "HCH11DMAADDR,Host channel 11 DMA address register"
hexmask.long 0x00 0.--31. 1. "DMAADDR,DMA address"
tree.end
tree "USBHS_DEVICE"
base ad:0x50000800
group.long 0x00++0x03
line.long 0x00 "DCFG,device configuration register (DCFG)"
bitfld.long 0x00 11.--12. "EOPFT,end of periodic frame time" "0,1,2,3"
hexmask.long.byte 0x00 4.--10. 1. "DAR,Device address"
bitfld.long 0x00 2. "NZLSOH,Non-zero-length status OUT handshake" "0,1"
bitfld.long 0x00 0.--1. "DS,Device speed" "0,1,2,3"
group.long 0x04++0x03
line.long 0x00 "DCTL,device control register (DCTL)"
bitfld.long 0x00 18. "L1RJCT,Deep sleep reject" "0,1"
bitfld.long 0x00 11. "POIF,Power-on initialization flag" "0,1"
bitfld.long 0x00 10. "CGONAK,Clear global OUT NAK" "0,1"
bitfld.long 0x00 9. "SGONAK,Set global OUT NAK" "0,1"
newline
bitfld.long 0x00 8. "CGINAK,Clear global IN NAK" "0,1"
bitfld.long 0x00 7. "SGINAK,Set global IN NAK" "0,1"
bitfld.long 0x00 4.--6. "DTEST,Device Test control" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 3. "GONS,Global OUT NAK status" "0,1"
newline
rbitfld.long 0x00 2. "GINS,Global IN NAK status" "0,1"
bitfld.long 0x00 1. "SD,Soft disconnect" "0,1"
bitfld.long 0x00 0. "RWKUP,Remote wakeup" "0,1"
rgroup.long 0x08++0x03
line.long 0x00 "DSTAT,device status register (DSTAT)"
hexmask.long.word 0x00 8.--21. 1. "FNRSOF,Frame number of the received SOF"
bitfld.long 0x00 1.--2. "ES,Enumerated speed" "0,1,2,3"
bitfld.long 0x00 0. "SPST,Suspend status" "0,1"
group.long 0x10++0x03
line.long 0x00 "DIEPINTEN,device IN endpoint common interrupt mask register (DIEPINTEN)"
bitfld.long 0x00 13. "NAKEN,NAK handshake sent by USBHS interrupt enable bit" "0,1"
bitfld.long 0x00 6. "IEPNEEN,IN endpoint NAK effective interrupt enable" "0,1"
bitfld.long 0x00 4. "EPTXFUDEN,Endpoint Tx FIFO underrun interrupt enable bit" "0,1"
bitfld.long 0x00 3. "CITOEN,Control IN timeout condition interrupt enable (Non-isochronous endpoints)" "0,1"
newline
bitfld.long 0x00 1. "EPDISEN,Endpoint disabled interrupt enable" "0,1"
bitfld.long 0x00 0. "TFEN,Transfer finished interrupt enable" "0,1"
group.long 0x14++0x03
line.long 0x00 "DOEPINTEN,device OUT endpoint common interrupt enable register (DOEPINTEN)"
bitfld.long 0x00 14. "NYETEN,Send NYET handshake interrupt enable bit" "0,1"
bitfld.long 0x00 6. "BTBSTPEN,Back-to-back SETUP packets interrupt enable" "0,1"
bitfld.long 0x00 4. "EPRXFOVREN,Endpoint Rx FIFO overrun interrupt enable" "0,1"
bitfld.long 0x00 3. "STPFEN,SETUP phase finished interrupt enable" "0,1"
newline
bitfld.long 0x00 1. "EPDISEN,Endpoint disabled interrupt enable" "0,1"
bitfld.long 0x00 0. "TFEN,Transfer finished interrupt enable" "0,1"
rgroup.long 0x18++0x03
line.long 0x00 "DAEPINT,device all endpoints interrupt register (DAEPINT)"
bitfld.long 0x00 16.--21. "OEPITB,Device all OUT endpoint interrupt bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "IEPITB,Device all IN endpoint interrupt bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x1C++0x03
line.long 0x00 "DAEPINTEN,Device all endpoints interrupt enable register (DAEPINTEN)"
bitfld.long 0x00 16.--21. "OEPIE,OUT endpoint interrupt enable bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "IEPIE,IN EP interrupt interrupt enable bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x28++0x03
line.long 0x00 "DVBUSDT,device VBUS discharge time register"
hexmask.long.word 0x00 0.--15. 1. "DVBUSDT,Device VBUS discharge time"
group.long 0x2C++0x03
line.long 0x00 "DVBUSPT,device VBUS pulsing time register"
hexmask.long.word 0x00 0.--11. 1. "DVBUSPT,Device VBUS pulsing time"
group.long 0x34++0x03
line.long 0x00 "DIEPFEINTEN,device IN endpoint FIFO empty interrupt enable register"
bitfld.long 0x00 0.--5. "IEPTXFEIE,IN EP Tx FIFO empty interrupt enable bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x38++0x03
line.long 0x00 "DEP1INT,Device endpoint 1 interrupt register"
bitfld.long 0x00 17. "OEP1INT,OUT Endpoint 1 interrupt" "0,1"
bitfld.long 0x00 1. "IEP1INT,IN Endpoint 1 interrupt" "0,1"
rgroup.long 0x3C++0x03
line.long 0x00 "DEP1INTEN,Device endpoint 1 interrupt register"
bitfld.long 0x00 17. "OEP1INTEN,OUT Endpoint 1 interrupt enable" "0,1"
bitfld.long 0x00 1. "IEP1INTEN,IN Endpoint 1 interrupt enable" "0,1"
group.long 0x44++0x03
line.long 0x00 "DIEP1INTEN,Device IN endpoint 1 interrupt enable register"
bitfld.long 0x00 13. "NAKEN,Interrupt enable bit of NAK handshake sent by USBHS" "0,1"
bitfld.long 0x00 6. "IEPNEEN,IN endpoint NAK effective interrupt enable bit" "0,1"
bitfld.long 0x00 4. "EPTXFUDEN,Endpoint Tx FIFO underrun interrupt enable bit" "0,1"
bitfld.long 0x00 3. "CITOEN,Control In Timeout interrupt enable bit" "0,1"
newline
bitfld.long 0x00 1. "EPDISEN,Endpoint disabled interrupt enable bit" "0,1"
bitfld.long 0x00 0. "TFEN,Transfer finished interrupt enable bit" "0,1"
group.long 0x84++0x03
line.long 0x00 "DOEP1INTEN,Device OUT endpoint 1 interrupt enable register"
bitfld.long 0x00 13. "NYETEN,Send NYET handshake interrupt enable bit" "0,1"
bitfld.long 0x00 6. "BTBSTPEN,Back-to-back SETUP packets interrupt enable bit" "0,1"
bitfld.long 0x00 4. "EPRXFOVREN,Endpoint Rx FIFO over run interrupt enable bit" "0,1"
bitfld.long 0x00 3. "STPFEN,SETUP phase finished interrupt enable bit" "0,1"
newline
bitfld.long 0x00 1. "EPDISEN,Endpoint disabled interrupt enable bit" "0,1"
bitfld.long 0x00 0. "TFEN,Transfer finished interrupt enable bit" "0,1"
group.long 0x100++0x03
line.long 0x00 "DIEP0CTL,device IN endpoint 0 control register (DIEP0CTL)"
bitfld.long 0x00 31. "EPEN,Endpoint enable" "0,1"
bitfld.long 0x00 30. "EPD,Endpoint disable" "0,1"
bitfld.long 0x00 27. "SNAK,Set NAK" "0,1"
bitfld.long 0x00 26. "CNAK,Clear NAK" "0,1"
newline
bitfld.long 0x00 22.--25. "TXFNUM,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 21. "STALL,STALL handshake" "0,1"
rbitfld.long 0x00 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
rbitfld.long 0x00 17. "NAKS,NAK status" "0,1"
newline
rbitfld.long 0x00 15. "EPACT,endpoint active" "0,1"
bitfld.long 0x00 0.--1. "MPL,Maximum packet length" "0,1,2,3"
group.long 0x120++0x03
line.long 0x00 "DIEP1CTL,device in endpoint-1 control register"
bitfld.long 0x00 31. "EPEN,Endpoint enable" "0,1"
bitfld.long 0x00 30. "EPD,Endpoint disable" "0,1"
bitfld.long 0x00 29. "SD1PID_SODDFRM,Set DATA1 PID/Set odd frame" "0,1"
bitfld.long 0x00 28. "SD0PID_SEVENFRM,SD0PID/SEVNFRM" "0,1"
newline
bitfld.long 0x00 27. "SNAK,Set NAK" "0,1"
bitfld.long 0x00 26. "CNAK,Clear NAK" "0,1"
bitfld.long 0x00 22.--25. "TXFNUM,Tx FIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 21. "STALL,STALL handshake" "0,1"
newline
bitfld.long 0x00 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
rbitfld.long 0x00 17. "NAKS,NAK status" "0,1"
rbitfld.long 0x00 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
bitfld.long 0x00 15. "EPACT,Endpoint active" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "MPL,maximum packet length"
group.long 0x140++0x03
line.long 0x00 "DIEP2CTL,device endpoint-2 control register"
bitfld.long 0x00 31. "EPEN,Endpoint enable" "0,1"
bitfld.long 0x00 30. "EPD,Endpoint disable" "0,1"
bitfld.long 0x00 29. "SD1PID_SODDFRM,Set DATA1 PID/Set odd frame" "0,1"
bitfld.long 0x00 28. "SD0PID_SEVENFRM,SD0PID/SEVNFRM" "0,1"
newline
bitfld.long 0x00 27. "SNAK,Set NAK" "0,1"
bitfld.long 0x00 26. "CNAK,Clear NAK" "0,1"
bitfld.long 0x00 22.--25. "TXFNUM,Tx FIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 21. "STALL,STALL handshake" "0,1"
newline
bitfld.long 0x00 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
rbitfld.long 0x00 17. "NAKS,NAK status" "0,1"
rbitfld.long 0x00 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
bitfld.long 0x00 15. "EPACT,Endpoint active" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "MPL,maximum packet length"
group.long 0x160++0x03
line.long 0x00 "DIEP3CTL,device endpoint-3 control register"
bitfld.long 0x00 31. "EPEN,Endpoint enable" "0,1"
bitfld.long 0x00 30. "EPD,Endpoint disable" "0,1"
bitfld.long 0x00 29. "SD1PID_SODDFRM,Set DATA1 PID/Set odd frame" "0,1"
bitfld.long 0x00 28. "SD0PID_SEVENFRM,SD0PID/SEVNFRM" "0,1"
newline
bitfld.long 0x00 27. "SNAK,Set NAK" "0,1"
bitfld.long 0x00 26. "CNAK,Clear NAK" "0,1"
bitfld.long 0x00 22.--25. "TXFNUM,Tx FIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 21. "STALL,STALL handshake" "0,1"
newline
bitfld.long 0x00 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
rbitfld.long 0x00 17. "NAKS,NAK status" "0,1"
rbitfld.long 0x00 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
bitfld.long 0x00 15. "EPACT,Endpoint active" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "MPL,maximum packet length"
group.long 0x180++0x03
line.long 0x00 "DIEP4CTL,device endpoint-4 control register"
bitfld.long 0x00 31. "EPEN,Endpoint enable" "0,1"
bitfld.long 0x00 30. "EPD,Endpoint disable" "0,1"
bitfld.long 0x00 29. "SD1PID_SODDFRM,Set DATA1 PID/Set odd frame" "0,1"
bitfld.long 0x00 28. "SD0PID_SEVENFRM,SD0PID/SEVNFRM" "0,1"
newline
bitfld.long 0x00 27. "SNAK,Set NAK" "0,1"
bitfld.long 0x00 26. "CNAK,Clear NAK" "0,1"
bitfld.long 0x00 22.--25. "TXFNUM,Tx FIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 21. "STALL,STALL handshake" "0,1"
newline
bitfld.long 0x00 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
rbitfld.long 0x00 17. "NAKS,NAK status" "0,1"
rbitfld.long 0x00 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
bitfld.long 0x00 15. "EPACT,Endpoint active" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "MPL,maximum packet length"
group.long 0x1A0++0x03
line.long 0x00 "DIEP5CTL,device endpoint-5 control register"
bitfld.long 0x00 31. "EPEN,Endpoint enable" "0,1"
bitfld.long 0x00 30. "EPD,Endpoint disable" "0,1"
bitfld.long 0x00 29. "SD1PID_SODDFRM,Set DATA1 PID/Set odd frame" "0,1"
bitfld.long 0x00 28. "SD0PID_SEVENFRM,SD0PID/SEVNFRM" "0,1"
newline
bitfld.long 0x00 27. "SNAK,Set NAK" "0,1"
bitfld.long 0x00 26. "CNAK,Clear NAK" "0,1"
bitfld.long 0x00 22.--25. "TXFNUM,Tx FIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 21. "STALL,STALL handshake" "0,1"
newline
bitfld.long 0x00 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
rbitfld.long 0x00 17. "NAKS,NAK status" "0,1"
rbitfld.long 0x00 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
bitfld.long 0x00 15. "EPACT,Endpoint active" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "MPL,maximum packet length"
group.long 0x300++0x03
line.long 0x00 "DOEP0CTL,device endpoint-0 control register"
bitfld.long 0x00 31. "EPEN,Endpoint enable" "0,1"
rbitfld.long 0x00 30. "EPD,Endpoint disable" "0,1"
bitfld.long 0x00 27. "SNAK,Set NAK" "0,1"
bitfld.long 0x00 26. "CNAK,Clear NAK" "0,1"
newline
bitfld.long 0x00 21. "STALL,STALL handshake" "0,1"
bitfld.long 0x00 20. "SNOOP,Snoop mode" "0,1"
rbitfld.long 0x00 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
rbitfld.long 0x00 17. "NAKS,NAK status" "0,1"
newline
rbitfld.long 0x00 15. "EPACT,Endpoint active" "0,1"
rbitfld.long 0x00 0.--1. "MPL,Maximum packet length" "0,1,2,3"
group.long 0x320++0x03
line.long 0x00 "DOEP1CTL,device endpoint-1 control register"
bitfld.long 0x00 31. "EPEN,Endpoint enable" "0,1"
bitfld.long 0x00 30. "EPD,Endpoint disable" "0,1"
bitfld.long 0x00 29. "SD1PID_SODDFRM,SD1PID/SODDFRM" "0,1"
bitfld.long 0x00 28. "SD0PID_SEVENFRM,SD0PID/SEVENFRM" "0,1"
newline
bitfld.long 0x00 27. "SNAK,Set NAK" "0,1"
bitfld.long 0x00 26. "CNAK,Clear NAK" "0,1"
bitfld.long 0x00 21. "STALL,STALL handshake" "0,1"
bitfld.long 0x00 20. "SNOOP,Snoop mode" "0,1"
newline
bitfld.long 0x00 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
rbitfld.long 0x00 17. "NAKS,NAK status" "0,1"
rbitfld.long 0x00 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
bitfld.long 0x00 15. "EPACT,Endpoint active" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "MPL,maximum packet length"
group.long 0x340++0x03
line.long 0x00 "DOEP2CTL,device endpoint-2 control register"
bitfld.long 0x00 31. "EPEN,Endpoint enable" "0,1"
bitfld.long 0x00 30. "EPD,Endpoint disable" "0,1"
bitfld.long 0x00 29. "SD1PID_SODDFRM,SD1PID/SODDFRM" "0,1"
bitfld.long 0x00 28. "SD0PID_SEVENFRM,SD0PID/SEVENFRM" "0,1"
newline
bitfld.long 0x00 27. "SNAK,Set NAK" "0,1"
bitfld.long 0x00 26. "CNAK,Clear NAK" "0,1"
bitfld.long 0x00 21. "STALL,STALL handshake" "0,1"
bitfld.long 0x00 20. "SNOOP,Snoop mode" "0,1"
newline
bitfld.long 0x00 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
rbitfld.long 0x00 17. "NAKS,NAK status" "0,1"
rbitfld.long 0x00 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
bitfld.long 0x00 15. "EPACT,Endpoint active" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "MPL,maximum packet length"
group.long 0x360++0x03
line.long 0x00 "DOEP3CTL,device endpoint-3 control register"
bitfld.long 0x00 31. "EPEN,Endpoint enable" "0,1"
bitfld.long 0x00 30. "EPD,Endpoint disable" "0,1"
bitfld.long 0x00 29. "SD1PID_SODDFRM,SD1PID/SODDFRM" "0,1"
bitfld.long 0x00 28. "SD0PID_SEVENFRM,SD0PID/SEVENFRM" "0,1"
newline
bitfld.long 0x00 27. "SNAK,Set NAK" "0,1"
bitfld.long 0x00 26. "CNAK,Clear NAK" "0,1"
bitfld.long 0x00 21. "STALL,STALL handshake" "0,1"
bitfld.long 0x00 20. "SNOOP,Snoop mode" "0,1"
newline
bitfld.long 0x00 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
rbitfld.long 0x00 17. "NAKS,NAK status" "0,1"
rbitfld.long 0x00 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
bitfld.long 0x00 15. "EPACT,Endpoint active" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "MPL,maximum packet length"
group.long 0x380++0x03
line.long 0x00 "DOEP4CTL,device endpoint-4 control register"
bitfld.long 0x00 31. "EPEN,Endpoint enable" "0,1"
bitfld.long 0x00 30. "EPD,Endpoint disable" "0,1"
bitfld.long 0x00 29. "SD1PID_SODDFRM,SD1PID/SODDFRM" "0,1"
bitfld.long 0x00 28. "SD0PID_SEVENFRM,SD0PID/SEVENFRM" "0,1"
newline
bitfld.long 0x00 27. "SNAK,Set NAK" "0,1"
bitfld.long 0x00 26. "CNAK,Clear NAK" "0,1"
bitfld.long 0x00 21. "STALL,STALL handshake" "0,1"
bitfld.long 0x00 20. "SNOOP,Snoop mode" "0,1"
newline
bitfld.long 0x00 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
rbitfld.long 0x00 17. "NAKS,NAK status" "0,1"
rbitfld.long 0x00 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
bitfld.long 0x00 15. "EPACT,Endpoint active" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "MPL,maximum packet length"
group.long 0x3A0++0x03
line.long 0x00 "DOEP5CTL,device endpoint-5 control register"
bitfld.long 0x00 31. "EPEN,Endpoint enable" "0,1"
bitfld.long 0x00 30. "EPD,Endpoint disable" "0,1"
bitfld.long 0x00 29. "SD1PID_SODDFRM,SD1PID/SODDFRM" "0,1"
bitfld.long 0x00 28. "SD0PID_SEVENFRM,SD0PID/SEVENFRM" "0,1"
newline
bitfld.long 0x00 27. "SNAK,Set NAK" "0,1"
bitfld.long 0x00 26. "CNAK,Clear NAK" "0,1"
bitfld.long 0x00 21. "STALL,STALL handshake" "0,1"
bitfld.long 0x00 20. "SNOOP,Snoop mode" "0,1"
newline
bitfld.long 0x00 18.--19. "EPTYPE,Endpoint type" "0,1,2,3"
rbitfld.long 0x00 17. "NAKS,NAK status" "0,1"
rbitfld.long 0x00 16. "EOFRM_DPID,EOFRM/DPID" "0,1"
bitfld.long 0x00 15. "EPACT,Endpoint active" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "MPL,maximum packet length"
group.long 0x108++0x03
line.long 0x00 "DIEP0INTF,device endpoint-0 interrupt register"
bitfld.long 0x00 13. "NAK,NAK handshake sent by USBHS" "0,1"
rbitfld.long 0x00 7. "TXFE,Transmit FIFO empty" "0,1"
bitfld.long 0x00 6. "IEPNE,IN endpoint NAK effective" "0,1"
bitfld.long 0x00 4. "EPTXFUD,Endpoint Tx FIFO underrun" "0,1"
newline
bitfld.long 0x00 3. "CITO,Control in timeout interrupt" "0,1"
bitfld.long 0x00 1. "EPDIS,Endpoint finished" "0,1"
bitfld.long 0x00 0. "TF,Transfer finished" "0,1"
group.long 0x128++0x03
line.long 0x00 "DIEP1INTF,device endpoint-1 interrupt register"
bitfld.long 0x00 13. "NAK,NAK handshake sent by USBHS" "0,1"
rbitfld.long 0x00 7. "TXFE,Transmit FIFO empty" "0,1"
bitfld.long 0x00 6. "IEPNE,IN endpoint NAK effective" "0,1"
bitfld.long 0x00 4. "EPTXFUD,Endpoint Tx FIFO underrun" "0,1"
newline
bitfld.long 0x00 3. "CITO,Control in timeout interrupt" "0,1"
bitfld.long 0x00 1. "EPDIS,Endpoint finished" "0,1"
bitfld.long 0x00 0. "TF,Transfer finished" "0,1"
group.long 0x148++0x03
line.long 0x00 "DIEP2INTF,device endpoint-2 interrupt register"
bitfld.long 0x00 13. "NAK,NAK handshake sent by USBHS" "0,1"
rbitfld.long 0x00 7. "TXFE,Transmit FIFO empty" "0,1"
bitfld.long 0x00 6. "IEPNE,IN endpoint NAK effective" "0,1"
bitfld.long 0x00 4. "EPTXFUD,Endpoint Tx FIFO underrun" "0,1"
newline
bitfld.long 0x00 3. "CITO,Control in timeout interrupt" "0,1"
bitfld.long 0x00 1. "EPDIS,Endpoint finished" "0,1"
bitfld.long 0x00 0. "TF,Transfer finished" "0,1"
group.long 0x168++0x03
line.long 0x00 "DIEP3INTF,device endpoint-3 interrupt register"
bitfld.long 0x00 13. "NAK,NAK handshake sent by USBHS" "0,1"
rbitfld.long 0x00 7. "TXFE,Transmit FIFO empty" "0,1"
bitfld.long 0x00 6. "IEPNE,IN endpoint NAK effective" "0,1"
bitfld.long 0x00 4. "EPTXFUD,Endpoint Tx FIFO underrun" "0,1"
newline
bitfld.long 0x00 3. "CITO,Control in timeout interrupt" "0,1"
bitfld.long 0x00 1. "EPDIS,Endpoint finished" "0,1"
bitfld.long 0x00 0. "TF,Transfer finished" "0,1"
group.long 0x188++0x03
line.long 0x00 "DIEP4INTF,device endpoint-4 interrupt register"
bitfld.long 0x00 13. "NAK,NAK handshake sent by USBHS" "0,1"
rbitfld.long 0x00 7. "TXFE,Transmit FIFO empty" "0,1"
bitfld.long 0x00 6. "IEPNE,IN endpoint NAK effective" "0,1"
bitfld.long 0x00 4. "EPTXFUD,Endpoint Tx FIFO underrun" "0,1"
newline
bitfld.long 0x00 3. "CITO,Control in timeout interrupt" "0,1"
bitfld.long 0x00 1. "EPDIS,Endpoint finished" "0,1"
bitfld.long 0x00 0. "TF,Transfer finished" "0,1"
group.long 0x1A8++0x03
line.long 0x00 "DIEP5INTF,device endpoint-5 interrupt register"
bitfld.long 0x00 13. "NAK,NAK handshake sent by USBHS" "0,1"
rbitfld.long 0x00 7. "TXFE,Transmit FIFO empty" "0,1"
bitfld.long 0x00 6. "IEPNE,IN endpoint NAK effective" "0,1"
bitfld.long 0x00 4. "EPTXFUD,Endpoint Tx FIFO underrun" "0,1"
newline
bitfld.long 0x00 3. "CITO,Control in timeout interrupt" "0,1"
bitfld.long 0x00 1. "EPDIS,Endpoint finished" "0,1"
bitfld.long 0x00 0. "TF,Transfer finished" "0,1"
group.long 0x308++0x03
line.long 0x00 "DOEP0INTF,device out endpoint-0 interrupt flag register"
bitfld.long 0x00 14. "NYET,NYET handshake is sent" "0,1"
bitfld.long 0x00 6. "BTBSTP,Back-to-back SETUP packets" "0,1"
bitfld.long 0x00 4. "EPRXFOVR,Endpoint Rx FIFO overrun" "0,1"
bitfld.long 0x00 3. "STPF,Setup phase finished" "0,1"
newline
bitfld.long 0x00 1. "EPDIS,Endpoint disabled" "0,1"
bitfld.long 0x00 0. "TF,Transfer finished" "0,1"
group.long 0x328++0x03
line.long 0x00 "DOEP1INTF,device out endpoint-1 interrupt flag register"
bitfld.long 0x00 14. "NYET,NYET handshake is sent" "0,1"
bitfld.long 0x00 6. "BTBSTP,Back-to-back SETUP packets" "0,1"
bitfld.long 0x00 4. "EPRXFOVR,Endpoint Rx FIFO overrun" "0,1"
bitfld.long 0x00 3. "STPF,Setup phase finished" "0,1"
newline
bitfld.long 0x00 1. "EPDIS,Endpoint disabled" "0,1"
bitfld.long 0x00 0. "TF,Transfer finished" "0,1"
group.long 0x348++0x03
line.long 0x00 "DOEP2INTF,device out endpoint-2 interrupt flag register"
bitfld.long 0x00 14. "NYET,NYET handshake is sent" "0,1"
bitfld.long 0x00 6. "BTBSTP,Back-to-back SETUP packets" "0,1"
bitfld.long 0x00 4. "EPRXFOVR,Endpoint Rx FIFO overrun" "0,1"
bitfld.long 0x00 3. "STPF,Setup phase finished" "0,1"
newline
bitfld.long 0x00 1. "EPDIS,Endpoint disabled" "0,1"
bitfld.long 0x00 0. "TF,Transfer finished" "0,1"
group.long 0x368++0x03
line.long 0x00 "DOEP3INTF,device out endpoint-3 interrupt flag register"
bitfld.long 0x00 14. "NYET,NYET handshake is sent" "0,1"
bitfld.long 0x00 6. "BTBSTP,Back-to-back SETUP packets" "0,1"
bitfld.long 0x00 4. "EPRXFOVR,Endpoint Rx FIFO overrun" "0,1"
bitfld.long 0x00 3. "STPF,Setup phase finished" "0,1"
newline
bitfld.long 0x00 1. "EPDIS,Endpoint disabled" "0,1"
bitfld.long 0x00 0. "TF,Transfer finished" "0,1"
group.long 0x388++0x03
line.long 0x00 "DOEP4INTF,device out endpoint-4 interrupt flag register"
bitfld.long 0x00 14. "NYET,NYET handshake is sent" "0,1"
bitfld.long 0x00 6. "BTBSTP,Back-to-back SETUP packets" "0,1"
bitfld.long 0x00 4. "EPRXFOVR,Endpoint Rx FIFO overrun" "0,1"
bitfld.long 0x00 3. "STPF,Setup phase finished" "0,1"
newline
bitfld.long 0x00 1. "EPDIS,Endpoint disabled" "0,1"
bitfld.long 0x00 0. "TF,Transfer finished" "0,1"
group.long 0x3A8++0x03
line.long 0x00 "DOEP5INTF,device out endpoint-5 interrupt flag register"
bitfld.long 0x00 14. "NYET,NYET handshake is sent" "0,1"
bitfld.long 0x00 6. "BTBSTP,Back-to-back SETUP packets" "0,1"
bitfld.long 0x00 4. "EPRXFOVR,Endpoint Rx FIFO overrun" "0,1"
bitfld.long 0x00 3. "STPF,Setup phase finished" "0,1"
newline
bitfld.long 0x00 1. "EPDIS,Endpoint disabled" "0,1"
bitfld.long 0x00 0. "TF,Transfer finished" "0,1"
group.long 0x110++0x03
line.long 0x00 "DIEP0LEN,device IN endpoint-0 transfer length register"
bitfld.long 0x00 19.--20. "PCNT,Packet count" "0,1,2,3"
hexmask.long.byte 0x00 0.--6. 1. "TLEN,Transfer length"
group.long 0x310++0x03
line.long 0x00 "DOEP0LEN,device OUT endpoint-0 transfer length register"
bitfld.long 0x00 29.--30. "STPCNT,SETUP packet count" "0,1,2,3"
bitfld.long 0x00 19. "PCNT,Packet count" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "TLEN,Transfer length"
group.long 0x130++0x03
line.long 0x00 "DIEP1LEN,device IN endpoint-1 transfer length register"
bitfld.long 0x00 29.--30. "MCNT,Multi count" "0,1,2,3"
hexmask.long.word 0x00 19.--28. 1. "PCNT,Packet count"
hexmask.long.tbyte 0x00 0.--18. 1. "TLEN,Transfer length"
group.long 0x150++0x03
line.long 0x00 "DIEP2LEN,device IN endpoint-2 transfer length register"
bitfld.long 0x00 29.--30. "MCNT,Multi count" "0,1,2,3"
hexmask.long.word 0x00 19.--28. 1. "PCNT,Packet count"
hexmask.long.tbyte 0x00 0.--18. 1. "TLEN,Transfer length"
group.long 0x170++0x03
line.long 0x00 "DIEP3LEN,device IN endpoint-3 transfer length register"
bitfld.long 0x00 29.--30. "MCNT,Multi count" "0,1,2,3"
hexmask.long.word 0x00 19.--28. 1. "PCNT,Packet count"
hexmask.long.tbyte 0x00 0.--18. 1. "TLEN,Transfer length"
group.long 0x190++0x03
line.long 0x00 "DIEP4LEN,device IN endpoint-4 transfer length register"
bitfld.long 0x00 29.--30. "MCNT,Multi count" "0,1,2,3"
hexmask.long.word 0x00 19.--28. 1. "PCNT,Packet count"
hexmask.long.tbyte 0x00 0.--18. 1. "TLEN,Transfer length"
group.long 0x1B0++0x03
line.long 0x00 "DIEP5LEN,device IN endpoint-5 transfer length register"
bitfld.long 0x00 29.--30. "MCNT,Multi count" "0,1,2,3"
hexmask.long.word 0x00 19.--28. 1. "PCNT,Packet count"
hexmask.long.tbyte 0x00 0.--18. 1. "TLEN,Transfer length"
group.long 0x330++0x03
line.long 0x00 "DOEP1LEN,device OUT endpoint-1 transfer length register"
bitfld.long 0x00 29.--30. "STPCNT_RXDPID,SETUP packet count/Received data PID" "0,1,2,3"
hexmask.long.word 0x00 19.--28. 1. "PCNT,Packet count"
hexmask.long.tbyte 0x00 0.--18. 1. "TLEN,Transfer length"
group.long 0x350++0x03
line.long 0x00 "DOEP2LEN,device OUT endpoint-2 transfer length register"
bitfld.long 0x00 29.--30. "STPCNT_RXDPID,SETUP packet count/Received data PID" "0,1,2,3"
hexmask.long.word 0x00 19.--28. 1. "PCNT,Packet count"
hexmask.long.tbyte 0x00 0.--18. 1. "TLEN,Transfer length"
group.long 0x370++0x03
line.long 0x00 "DOEP3LEN,device OUT endpoint-3 transfer length register"
bitfld.long 0x00 29.--30. "STPCNT_RXDPID,SETUP packet count/Received data PID" "0,1,2,3"
hexmask.long.word 0x00 19.--28. 1. "PCNT,Packet count"
hexmask.long.tbyte 0x00 0.--18. 1. "TLEN,Transfer length"
group.long 0x390++0x03
line.long 0x00 "DOEP4LEN,device OUT endpoint-4 transfer length register"
bitfld.long 0x00 29.--30. "STPCNT_RXDPID,SETUP packet count/Received data PID" "0,1,2,3"
hexmask.long.word 0x00 19.--28. 1. "PCNT,Packet count"
hexmask.long.tbyte 0x00 0.--18. 1. "TLEN,Transfer length"
group.long 0x3B0++0x03
line.long 0x00 "DOEP5LEN,device OUT endpoint-5 transfer length register"
bitfld.long 0x00 29.--30. "STPCNT_RXDPID,SETUP packet count/Received data PID" "0,1,2,3"
hexmask.long.word 0x00 19.--28. 1. "PCNT,Packet count"
hexmask.long.tbyte 0x00 0.--18. 1. "TLEN,Transfer length"
group.long 0x114++0x03
line.long 0x00 "DIEP0DMAADDR,Device IN endpoint 0 DMA address register"
hexmask.long 0x00 0.--31. 1. "DMAADDR,DMA address"
group.long 0x134++0x03
line.long 0x00 "DIEP1DMAADDR,Device IN endpoint 1 DMA address register"
hexmask.long 0x00 0.--31. 1. "DMAADDR,DMA address"
group.long 0x154++0x03
line.long 0x00 "DIEP2DMAADDR,Device IN endpoint 2 DMA address register"
hexmask.long 0x00 0.--31. 1. "DMAADDR,DMA address"
group.long 0x174++0x03
line.long 0x00 "DIEP3DMAADDR,Device IN endpoint 3 DMA address register"
hexmask.long 0x00 0.--31. 1. "DMAADDR,DMA address"
group.long 0x194++0x03
line.long 0x00 "DIEP4DMAADDR,Device IN endpoint 4 DMA address register"
hexmask.long 0x00 0.--31. 1. "DMAADDR,DMA address"
group.long 0x1B4++0x03
line.long 0x00 "DIEP5DMAADDR,Device IN endpoint 5 DMA address register"
hexmask.long 0x00 0.--31. 1. "DMAADDR,DMA address"
group.long 0x314++0x03
line.long 0x00 "DOEP0DMAADDR,Device OUT endpoint 0 DMA address register"
hexmask.long 0x00 0.--31. 1. "DMAADDR,DMA address"
group.long 0x334++0x03
line.long 0x00 "DOEP1DMAADDR,Device OUT endpoint 1 DMA address register"
hexmask.long 0x00 0.--31. 1. "DMAADDR,DMA address"
group.long 0x354++0x03
line.long 0x00 "DOEP2DMAADDR,Device OUT endpoint 2 DMA address register"
hexmask.long 0x00 0.--31. 1. "DMAADDR,DMA address"
group.long 0x374++0x03
line.long 0x00 "DOEP3DMAADDR,Device OUT endpoint 3 DMA address register"
hexmask.long 0x00 0.--31. 1. "DMAADDR,DMA address"
group.long 0x394++0x03
line.long 0x00 "DOEP4DMAADDR,Device OUT endpoint 4 DMA address register"
hexmask.long 0x00 0.--31. 1. "DMAADDR,DMA address"
group.long 0x3B4++0x03
line.long 0x00 "DOEP5DMAADDR,Device OUT endpoint 5 DMA address register"
hexmask.long 0x00 0.--31. 1. "DMAADDR,DMA address"
rgroup.long 0x118++0x03
line.long 0x00 "DIEP0TFSTAT,device IN endpoint 0 transmit FIFO status register"
hexmask.long.word 0x00 0.--15. 1. "IEPTFS,IN endpoint TxFIFO space remaining"
rgroup.long 0x138++0x03
line.long 0x00 "DIEP1TFSTAT,device IN endpoint 1 transmit FIFO status register"
hexmask.long.word 0x00 0.--15. 1. "IEPTFS,IN endpoint TxFIFO space remaining"
rgroup.long 0x158++0x03
line.long 0x00 "DIEP2TFSTAT,device IN endpoint 2 transmit FIFO status register"
hexmask.long.word 0x00 0.--15. 1. "IEPTFS,IN endpoint TxFIFO space remaining"
rgroup.long 0x178++0x03
line.long 0x00 "DIEP3TFSTAT,device IN endpoint 3 transmit FIFO status register"
hexmask.long.word 0x00 0.--15. 1. "IEPTFS,IN endpoint TxFIFO space remaining"
rgroup.long 0x198++0x03
line.long 0x00 "DIEP4TFSTAT,device IN endpoint 4 transmit FIFO status register"
hexmask.long.word 0x00 0.--15. 1. "IEPTFS,IN endpoint TxFIFO space remaining"
rgroup.long 0x1B8++0x03
line.long 0x00 "DIEP5TFSTAT,device IN endpoint 5 transmit FIFO status register"
hexmask.long.word 0x00 0.--15. 1. "IEPTFS,IN endpoint TxFIFO space remaining"
tree.end
tree "USBHS_GLOBAL"
base ad:0x50000000
group.long 0x00++0x03
line.long 0x00 "GOTGCS,Global OTG control and status register (USBFS_GOTGCS)"
bitfld.long 0x00 20. "OV,Select OTG version" "0,1"
rbitfld.long 0x00 19. "BSV,B-session valid" "0,1"
rbitfld.long 0x00 18. "ASV,A-session valid" "0,1"
rbitfld.long 0x00 17. "DI,Debounce interval" "0,1"
newline
rbitfld.long 0x00 16. "IDPS,ID pin status" "0,1"
bitfld.long 0x00 12. "EHE,Embedded host enable" "0,1"
bitfld.long 0x00 11. "DHNPEN,Device HNP enabled" "0,1"
bitfld.long 0x00 10. "HHNPEN,Host HNP enable" "0,1"
newline
bitfld.long 0x00 9. "HNPREQ,HNP request" "0,1"
rbitfld.long 0x00 8. "HNPS,HNP success" "0,1"
bitfld.long 0x00 7. "BVOV,Override value of B-peripheral session valid" "0,1"
bitfld.long 0x00 6. "BVOE,Override enable of B-peripheral session valid" "0,1"
newline
bitfld.long 0x00 5. "AVOV,Override value of A-peripheral session valid" "0,1"
bitfld.long 0x00 4. "AVOE,Override enable of A-peripheral session valid" "0,1"
bitfld.long 0x00 3. "VOV,Override value of VBUS valid" "0,1"
bitfld.long 0x00 2. "VOE,Override enable of VBUS valid" "0,1"
newline
bitfld.long 0x00 1. "SRPREQ,SRP request" "0,1"
rbitfld.long 0x00 0. "SRPS,SRP success" "0,1"
group.long 0x04++0x03
line.long 0x00 "GOTGINTF,Global OTG interrupt flag register (USBHS_GOTGINTF)"
bitfld.long 0x00 20. "IDCHG,There is a change in the value of ID input" "0,1"
bitfld.long 0x00 19. "DF,Debounce finish" "0,1"
bitfld.long 0x00 18. "ADTO,A-device timeout" "0,1"
bitfld.long 0x00 17. "HNPDET,Host negotiation request detected" "0,1"
newline
bitfld.long 0x00 9. "HNPEND,HNP end" "0,1"
bitfld.long 0x00 8. "SRPEND,Session request success status change" "0,1"
bitfld.long 0x00 2. "SESEND,Session end" "0,1"
group.long 0x08++0x03
line.long 0x00 "GAHBCS,Global AHB control and status register (USBHS_GAHBCS)"
bitfld.long 0x00 8. "PTXFTH,Periodic Tx FIFO threshold" "0,1"
bitfld.long 0x00 7. "TXFTH,Tx FIFO threshold" "0,1"
bitfld.long 0x00 5. "DMAEN,DMA function Enable" "0,1"
bitfld.long 0x00 1.--4. "BURST,The AHB burst type used by DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "GINTEN,Global interrupt enable" "0,1"
group.long 0x0C++0x03
line.long 0x00 "GUSBCS,Global USB control and status register (USBHS_GUSBCSR)"
bitfld.long 0x00 30. "FDM,Force device mode" "0,1"
bitfld.long 0x00 29. "FHM,Force host mode" "0,1"
bitfld.long 0x00 21. "ULPIEOI,ULPI external over-current indicator" "0,1"
bitfld.long 0x00 20. "ULPIEVD,ULPI external VBUS driver" "0,1"
newline
bitfld.long 0x00 10.--13. "UTT,USB turnaround time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 9. "HNPCEN,HNP capability enable" "0,1"
bitfld.long 0x00 8. "SRPCEN,SRP capability enable" "0,1"
bitfld.long 0x00 6. "EMBPHY_FS,Embedded FS PHY selected" "0,1"
newline
bitfld.long 0x00 5. "EMBPHY_HS,Embedded HS PHY selected" "0,1"
bitfld.long 0x00 4. "HS_CUR_FE,HS current software enable" "0,1"
bitfld.long 0x00 0.--2. "TOC,Timeout calibration" "0,1,2,3,4,5,6,7"
group.long 0x10++0x03
line.long 0x00 "GRSTCTL,Global reset control register (USBHS_GRSTCTL)"
rbitfld.long 0x00 31. "DMAIDL,DMA Idle state" "0,1"
rbitfld.long 0x00 30. "DMABSY,DMA Busy" "0,1"
bitfld.long 0x00 6.--10. "TXFNUM,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5. "TXFF,TxFIFO flush" "0,1"
newline
bitfld.long 0x00 4. "RXFF,RxFIFO flush" "0,1"
bitfld.long 0x00 2. "HFCRST,Host frame counter reset" "0,1"
bitfld.long 0x00 1. "HCSRST,HCLK soft reset" "0,1"
bitfld.long 0x00 0. "CSRST,Core soft reset" "0,1"
group.long 0x14++0x03
line.long 0x00 "GINTF,Global interrupt flag register (USBFS_GINTF)"
bitfld.long 0x00 31. "WKUPIF,Wakeup interrupt flag" "0,1"
bitfld.long 0x00 30. "SESIF,Session interrupt flag" "0,1"
bitfld.long 0x00 29. "DISCIF,Disconnect interrupt flag" "0,1"
bitfld.long 0x00 28. "IDPSC,ID pin status change" "0,1"
newline
bitfld.long 0x00 27. "LPMIF,LPM interrupt flag" "0,1"
rbitfld.long 0x00 26. "PTXFEIF,Periodic TxFIFO empty interrupt flag" "0,1"
rbitfld.long 0x00 25. "HCIF,Host channels interrupt flag" "0,1"
rbitfld.long 0x00 24. "HPIF,Host port interrupt flag" "0,1"
newline
bitfld.long 0x00 21. "PXNCIF_ISOONCIF,periodic transfer not complete interrupt flag(Host mode)/isochronous OUT transfer not complete interrupt flag(Device mode)" "0,1"
bitfld.long 0x00 20. "ISOINCIF,Isochronous IN transfer Not Complete Interrupt Flag" "0,1"
rbitfld.long 0x00 19. "OEPIF,OUT endpoint interrupt flag" "0,1"
rbitfld.long 0x00 18. "IEPIF,IN endpoint interrupt flag" "0,1"
newline
bitfld.long 0x00 15. "EOPFIF,End of periodic frame interrupt flag" "0,1"
bitfld.long 0x00 14. "ISOOPDIF,Isochronous OUT packet dropped interrupt" "0,1"
bitfld.long 0x00 13. "ENUMF,Enumeration finished" "0,1"
bitfld.long 0x00 12. "RST,USB reset" "0,1"
newline
bitfld.long 0x00 11. "SP,USB suspend" "0,1"
bitfld.long 0x00 10. "ESP,Early suspend" "0,1"
rbitfld.long 0x00 7. "GONAK,Global OUT NAK effective" "0,1"
rbitfld.long 0x00 6. "GNPINAK,Global Non-Periodic IN NAK effective" "0,1"
newline
rbitfld.long 0x00 5. "NPTXFEIF,Non-periodic TxFIFO empty interrupt flag" "0,1"
rbitfld.long 0x00 4. "RXFNEIF,RxFIFO non-empty interrupt flag" "0,1"
bitfld.long 0x00 3. "SOF,Start of frame" "0,1"
rbitfld.long 0x00 2. "OTGIF,OTG interrupt flag" "0,1"
newline
bitfld.long 0x00 1. "MFIF,Mode fault interrupt flag" "0,1"
rbitfld.long 0x00 0. "COPM,Current operation mode" "0,1"
group.long 0x18++0x03
line.long 0x00 "GINTEN,Global interrupt enable register (USBHS_GINTEN)"
bitfld.long 0x00 31. "WKUPIE,Wakeup interrupt enable" "0,1"
bitfld.long 0x00 30. "SESIE,Session interrupt enable" "0,1"
bitfld.long 0x00 29. "DISCIE,Disconnect interrupt enable" "0,1"
bitfld.long 0x00 28. "IDPSCIE,ID pin status change interrupt enable" "0,1"
newline
bitfld.long 0x00 27. "LPMIE,LPM interrupt enable" "0,1"
bitfld.long 0x00 26. "PTXFEIE,Periodic TxFIFO empty interrupt enable" "0,1"
bitfld.long 0x00 25. "HCIE,Host channels interrupt enable" "0,1"
rbitfld.long 0x00 24. "HPIE,Host port interrupt enable" "0,1"
newline
bitfld.long 0x00 21. "PXNCIE_ISOONCIE,periodic transfer not compelete Interrupt enable(Host mode)/isochronous OUT transfer not complete interrupt enable(Device mode)" "0,1"
bitfld.long 0x00 20. "ISOINCIE,isochronous IN transfer not complete interrupt enable" "0,1"
bitfld.long 0x00 19. "OEPIE,OUT endpoints interrupt enable" "0,1"
bitfld.long 0x00 18. "IEPIE,IN endpoints interrupt enable" "0,1"
newline
bitfld.long 0x00 15. "EOPFIE,End of periodic frame interrupt enable" "0,1"
bitfld.long 0x00 14. "ISOOPDIE,Isochronous OUT packet dropped interrupt enable" "0,1"
bitfld.long 0x00 13. "ENUMFIE,Enumeration finish interrupt enable" "0,1"
bitfld.long 0x00 12. "RSTIE,USB reset interrupt enable" "0,1"
newline
bitfld.long 0x00 11. "SPIE,USB suspend interrupt enable" "0,1"
bitfld.long 0x00 10. "ESPIE,Early suspend interrupt enable" "0,1"
bitfld.long 0x00 7. "GONAKIE,Global OUT NAK effective interrupt enable" "0,1"
bitfld.long 0x00 6. "GNPINAKIE,Global non-periodic IN NAK effective interrupt enable" "0,1"
newline
bitfld.long 0x00 5. "NPTXFEIE,Non-periodic TxFIFO empty interrupt enable" "0,1"
bitfld.long 0x00 4. "RXFNEIE,Receive FIFO non-empty interrupt enable" "0,1"
bitfld.long 0x00 3. "SOFIE,Start of frame interrupt enable" "0,1"
bitfld.long 0x00 2. "OTGIE,OTG interrupt enable" "0,1"
newline
bitfld.long 0x00 1. "MFIE,Mode fault interrupt enable" "0,1"
rgroup.long 0x1C++0x03
line.long 0x00 "GRSTATR_Device,Global Receive status read(Device mode)"
bitfld.long 0x00 17.--20. "RPCKST,Recieve packet status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 15.--16. "DPID,Data PID" "0,1,2,3"
hexmask.long.word 0x00 4.--14. 1. "BCOUNT,Byte count"
bitfld.long 0x00 0.--3. "EPNUM,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x1C++0x03
line.long 0x00 "GRSTATR_Host,Global Receive status read(Host mode)"
bitfld.long 0x00 17.--20. "RPCKST,Reivece packet status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 15.--16. "DPID,Data PID" "0,1,2,3"
hexmask.long.word 0x00 4.--14. 1. "BCOUNT,Byte count"
bitfld.long 0x00 0.--3. "CNUM,Channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x20++0x03
line.long 0x00 "GRSTATP_Device,Global Receive status pop(Device mode)"
bitfld.long 0x00 17.--20. "RPCKST,Recieve packet status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 15.--16. "DPID,Data PID" "0,1,2,3"
hexmask.long.word 0x00 4.--14. 1. "BCOUNT,Byte count"
bitfld.long 0x00 0.--3. "EPNUM,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x20++0x03
line.long 0x00 "GRSTATP_Host,Global Receive status pop(Host mode)"
bitfld.long 0x00 17.--20. "RPCKST,Reivece packet status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 15.--16. "DPID,Data PID" "0,1,2,3"
hexmask.long.word 0x00 4.--14. 1. "BCOUNT,Byte count"
bitfld.long 0x00 0.--3. "CNUM,Channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x24++0x03
line.long 0x00 "GRFLEN,Global Receive FIFO size register (USBHS_GRFLEN)"
hexmask.long.word 0x00 0.--15. 1. "RXFD,Rx FIFO depth"
group.long 0x28++0x03
line.long 0x00 "HNPTFLEN,Host non-periodic transmit FIFO length register (Host mode)"
hexmask.long.word 0x00 16.--31. 1. "HNPTXFD,host non-periodic TxFIFO depth"
hexmask.long.word 0x00 0.--15. 1. "HNPTXRSAR,host non-periodic transmit Tx RAM start address"
group.long 0x28++0x03
line.long 0x00 "DIEP0TFLEN,Device IN endpoint 0 transmit FIFO length (Device mode)"
hexmask.long.word 0x00 16.--31. 1. "IEP0TXFD,in endpoint 0 Tx FIFO depth"
hexmask.long.word 0x00 0.--15. 1. "IEP0TXRSAR,in endpoint 0 Tx RAM start address"
rgroup.long 0x2C++0x03
line.long 0x00 "HNPTFQSTAT,Host non-periodic transmit FIFO/queue status register (HNPTFQSTAT)"
hexmask.long.byte 0x00 24.--30. 1. "NPTXRQTOP,Top of the non-periodic transmit request queue"
hexmask.long.byte 0x00 16.--23. 1. "NPTXRQS,Non-periodic transmit request queue space"
hexmask.long.word 0x00 0.--15. 1. "NPTXFS,Non-periodic TxFIFO space"
group.long 0x38++0x03
line.long 0x00 "GCCFG,Global core configuration register (USBFS_GCCFG)"
bitfld.long 0x00 21. "VDEN,Enable of VBUS sensing comparator to detect VBUS valid" "0,1"
bitfld.long 0x00 20. "SOFOEN,SOF output enable" "0,1"
bitfld.long 0x00 16. "PWRON,Power on" "0,1"
bitfld.long 0x00 15. "SDMEN,Secondary detection mode enable" "0,1"
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bitfld.long 0x00 14. "PDMEN,Primary detection mode enable" "0,1"
bitfld.long 0x00 13. "DCDMEN,Data connect detection mode enable" "0,1"
bitfld.long 0x00 12. "BCDEN,Battery charging detection enable" "0,1"
bitfld.long 0x00 3. "PS2F,PS2 detection status" "0,1"
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bitfld.long 0x00 2. "SDF,Secondary detection status" "0,1"
bitfld.long 0x00 1. "PDF,Primary detection status" "0,1"
bitfld.long 0x00 0. "DCDF,Data connect detection status" "0,1"
group.long 0x3C++0x03
line.long 0x00 "CID,core ID register"
hexmask.long 0x00 0.--31. 1. "CID,Core ID"
group.long 0x54++0x03
line.long 0x00 "GLPMCFG,Global core LPM configuration register"
bitfld.long 0x00 28. "BESLEN,LPM Errata selection enable" "0,1"
bitfld.long 0x00 25.--27. "LPMRCS,LPM retry count status" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24. "LPMSND,Send LPM transaction" "0,1"
bitfld.long 0x00 21.--23. "LPMRC,LPM retry count" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 17.--20. "LPMCHI,Channel number index when send LPM transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16. "RSOK,Resume can be sent after sleep state" "0,1"
bitfld.long 0x00 15. "LPMSLPS,Sleep status" "0,1"
bitfld.long 0x00 13.--14. "LPMRSP,Response of LPM" "0,1,2,3"
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bitfld.long 0x00 12. "DSEN,Deep sleep enable" "0,1"
bitfld.long 0x00 8.--11. "BESLTH,BESL threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "SSEN,Shallow sleep enable" "0,1"
bitfld.long 0x00 6. "REW,RemoteWake value" "0,1"
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bitfld.long 0x00 2.--5. "BESL,Best effort service latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. "ACKLPM,ACK in LPM transaction enable" "0,1"
bitfld.long 0x00 0. "LPMEN,LPM enable" "0,1"
group.long 0x58++0x03
line.long 0x00 "PWRD,Power down register (USBHS_PWRD)"
bitfld.long 0x00 23. "ADPF,ADP event interrupt flag" "0,1"
bitfld.long 0x00 0. "ADPMEN,ADP module enable" "0,1"
group.long 0x60++0x03
line.long 0x00 "ADPCTL,ADP control andstatus register"
bitfld.long 0x00 27.--28. "RWR,Read and write request" "0,1,2,3"
bitfld.long 0x00 26. "ADPTFM,The mask of ADP timeout interrupt flag" "0,1"
bitfld.long 0x00 25. "ADPSNFM,The mask of ADP sense interrupt flag" "0,1"
bitfld.long 0x00 24. "ADPPRFM,The mask of ADP probe interrupt flag" "0,1"
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bitfld.long 0x00 23. "ADPTF,ADP timeout interrupt flag" "0,1"
bitfld.long 0x00 22. "ADPSNF,ADP sense interrupt flag" "0,1"
bitfld.long 0x00 21. "ADPPRF,ADP probe interrupt flag" "0,1"
bitfld.long 0x00 20. "ADPEN,ADP enable" "0,1"
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bitfld.long 0x00 19. "ADPRST,ADP reset" "0,1"
bitfld.long 0x00 18. "SNEN,ADP sense enable" "0,1"
bitfld.long 0x00 17. "PREN,ADP probe enable" "0,1"
hexmask.long.word 0x00 6.--16. 1. "CHGT,The latest time that VBUS ramps from VADPSINK to VADPPRB"
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bitfld.long 0x00 4.--5. "PERPR,Period of probe" "0,1,2,3"
bitfld.long 0x00 2.--3. "RESOPR,The resolution of CHGT value" "0,1,2,3"
bitfld.long 0x00 0.--1. "DSCHGPR,Time of probe discharge" "0,1,2,3"
group.long 0x100++0x03
line.long 0x00 "HPTFLEN,Host periodic transmit FIFO length register (HPTFLEN)"
hexmask.long.word 0x00 16.--31. 1. "HPTXFD,Host periodic TxFIFO depth"
hexmask.long.word 0x00 0.--15. 1. "HPTXFSAR,Host periodic TxFIFO start address"
group.long 0x104++0x03
line.long 0x00 "DIEP1TFLEN,device IN endpoint transmit FIFO size register"
hexmask.long.word 0x00 16.--31. 1. "IEPTXFD,IN endpoint TxFIFO depth"
hexmask.long.word 0x00 0.--15. 1. "IEPTXRSAR,IN endpoint FIFO transmit RAM start address"
group.long 0x108++0x03
line.long 0x00 "DIEP2TFLEN,device IN endpoint transmit FIFO size register"
hexmask.long.word 0x00 16.--31. 1. "IEPTXFD,IN endpoint TxFIFO depth"
hexmask.long.word 0x00 0.--15. 1. "IEPTXRSAR,IN endpoint FIFO transmit RAM start address"
group.long 0x10C++0x03
line.long 0x00 "DIEP3TFLEN,device IN endpoint transmit FIFO size register"
hexmask.long.word 0x00 16.--31. 1. "IEPTXFD,IN endpoint TxFIFO depth"
hexmask.long.word 0x00 0.--15. 1. "IEPTXRSAR,IN endpoint FIFO4 transmit RAM start address"
group.long 0x110++0x03
line.long 0x00 "DIEP4TFLEN,device IN endpoint transmit FIFO size register"
hexmask.long.word 0x00 16.--31. 1. "IEPTXFD,IN endpoint TxFIFO depth"
hexmask.long.word 0x00 0.--15. 1. "IEPTXRSAR,IN endpoint FIFO4 transmit RAM start address"
group.long 0x114++0x03
line.long 0x00 "DIEP5TFLEN,device IN endpoint transmit FIFO size register (FS_DIEP5TXFLEN)"
hexmask.long.word 0x00 16.--31. 1. "IEPTXFD,IN endpoint TxFIFO depth"
hexmask.long.word 0x00 0.--15. 1. "IEPTXRSAR,IN endpoint FIFO4 transmit RAM start address"
tree.end
tree "USBHS_PWRCLK"
base ad:0x50000E00
group.long 0x00++0x03
line.long 0x00 "PWRCLKCTL,power and clock gating control register (PWRCLKCTL)"
rbitfld.long 0x00 7. "DSLEEP,PHY is in deep sleep status" "0,1"
rbitfld.long 0x00 6. "SSLEEP,PHY is in shallow sleep status" "0,1"
rbitfld.long 0x00 5. "SCGEN,internal clock gating enable" "0,1"
rbitfld.long 0x00 4. "SUSP,PHY is in suspend status" "0,1"
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bitfld.long 0x00 1. "SHCLK,Stop HCLK" "0,1"
bitfld.long 0x00 0. "SUCLK,Stop the USB clock" "0,1"
tree.end
tree.end
endif
tree "WWDGT (Window watchdog timer)"
base ad:0x40002C00
group.long 0x00++0x03
line.long 0x00 "CTL,Control register"
bitfld.long 0x00 7. "WDGTEN,Activation bit" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "CNT,7-bit counter"
group.long 0x04++0x03
line.long 0x00 "CFG,Configuration register"
bitfld.long 0x00 9. "EWIE,Early wakeup interrupt" "0,1"
bitfld.long 0x00 7.--8. "PSC,Prescaler" "0,1,2,3"
hexmask.long.byte 0x00 0.--6. 1. "WIN,7-bit window value"
group.long 0x08++0x03
line.long 0x00 "STAT,Status register"
bitfld.long 0x00 0. "EWIF,Early wakeup interrupt flag" "0,1"
tree.end
autoindent.off
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