15738 lines
1015 KiB
Plaintext
15738 lines
1015 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: FM0P On-Chip Peripherals
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; @Props: Released
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; @Author: GAJ, KMW, BUM
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; @Changelog: 2015-08-12 GAJ
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; @ 2018-08-06 KMW
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; @Manufacturer: CYPRESS - Cypress Semiconductor Corporation
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; @Doc: reference_manual_S6E1A1_MN710-00001.pdf
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; 002-04969_32_Bit_Microcontroller_FM0_Family_Peripheral_Manual.pdf (Rev. C, 03/18)
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; @Chip: S6E1A11B, S6E1A11C, S6E1A12B, S6E1A12C
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; S6E1C11B, S6E1C11D, S6E1C12B, S6E1C11C, S6E1C12C, S6E1C12D
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; S6E1C31B, S6E1C31C, S6E1C31D, S6E1C32B, S6E1C32C, S6E1C32D
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; @Core: Cortex-M0+
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; @Copyright: (C) 1989-2018 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perfm0p.per 9610 2018-08-31 08:29:03Z psurmacki $
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config 16. 8.
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tree.close "Core Registers (Cortex-M0+)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 0x8
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if (CORENAME()=="CORTEXM1")
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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else
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
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bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
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else
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
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endif
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
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hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
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textline " "
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hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
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hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
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group.long 0xd04++0x03
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
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bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
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bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
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bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
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hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
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textline " "
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hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
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if (CORENAME()=="CORTEXM0+")
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group.long 0xd08++0x03
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line.long 0x00 "VTOR,Vector Table Offset Register"
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hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
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else
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textline " "
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endif
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group.long 0xd0c++0x03
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line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
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bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
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textline " "
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bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
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bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
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group.long 0xd10++0x03
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line.long 0x00 "SCR,System Control Register"
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bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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rgroup.long 0xd14++0x03
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line.long 0x00 "CCR,Configuration and Control Register"
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bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
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bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
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group.long 0xd1c++0x0b
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
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bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
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if (CORENAME()=="CORTEXM0+")
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hgroup.long 0x08++0x03
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hide.long 0x00 "ACTLR,Auxiliary Control Register"
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else
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textline " "
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endif
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Memory Protection Unit (MPU)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 15.
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rgroup.long 0xD90++0x03
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line.long 0x00 "MPU_TYPE,MPU Type Register"
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bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
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group.long 0xD94++0x03
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line.long 0x00 "MPU_CTRL,MPU Control Register"
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bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
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bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
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bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
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group.long 0xD98++0x03
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line.long 0x00 "MPU_RNR,MPU Region Number Register"
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hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
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tree.close "MPU regions"
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
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group.long 0xD9C++0x03 "Region 0"
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
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textline " "
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textline " "
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endif
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
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group.long 0xD9C++0x03 "Region 1"
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saveout 0xD98 %l 0x1
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line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x1
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line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
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saveout 0xD98 %l 0x1
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hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x1
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hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
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textline " "
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textline " "
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endif
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
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group.long 0xD9C++0x03 "Region 2"
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saveout 0xD98 %l 0x2
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line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x2
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line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
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saveout 0xD98 %l 0x2
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hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x2
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hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
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textline " "
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textline " "
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endif
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
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group.long 0xD9C++0x03 "Region 3"
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saveout 0xD98 %l 0x3
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line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x3
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line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
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saveout 0xD98 %l 0x3
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hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
tree.end
|
|
width 6.
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x00 "INT0,Interrupt Priority Register"
|
|
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
|
|
line.long 0x04 "INT1,Interrupt Priority Register"
|
|
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
|
|
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
|
|
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
|
|
line.long 0x08 "INT2,Interrupt Priority Register"
|
|
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
|
|
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
|
|
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
|
|
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
|
|
line.long 0x0C "INT3,Interrupt Priority Register"
|
|
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
|
|
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
|
|
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
|
|
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
|
|
line.long 0x10 "INT4,Interrupt Priority Register"
|
|
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
|
|
line.long 0x14 "INT5,Interrupt Priority Register"
|
|
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
|
|
line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "Clock"
|
|
base ad:0x40010000
|
|
width 18.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SCM_CTL,System Clock Mode Control Register"
|
|
bitfld.byte 0x00 5.--7. " RCS ,Master clock switch control bits" "High-speed CR,Main clock,Main PLL,,Low-speed CR,Sub clock,?..."
|
|
bitfld.byte 0x00 4. " PLLE ,PLL oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SOSCE ,Sub clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " MOSCE ,Main clock oscillation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " HCRE ,High-speed CR clock oscillation enable bit" "Disabled,Enabled"
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "SCM_STR,System Clock Mode Status Register"
|
|
bitfld.byte 0x00 5.--7. " RCM ,Master clock selection bits" "High-speed CR,Main clock,Main PLL,,Low-speed CR,Sub clock,?..."
|
|
bitfld.byte 0x00 4. " PLRDY ,PLL oscillation stable bit" "Not stable,Stable"
|
|
bitfld.byte 0x00 3. " SORDY ,Sub clock oscillation stable bit" "Not stable,Stable"
|
|
bitfld.byte 0x00 1. " MORDY ,Main clock oscillation stable bit" "Not stable,Stable"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " HCRDY ,High-speed CR clock oscillation stable bit" "Not stable,Stable"
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "BSC_PSR,Base Clock Prescaler Register"
|
|
bitfld.byte 0x00 0.--2. " BSR ,Base clock frequency division ratio setting bits" "1,1/2,1/3,1/4,1/6,1/8,1/16,?..."
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "APBC0_PSR,APB0 Prescaler Register"
|
|
bitfld.byte 0x00 0.--1. " APBC0 ,APB0 bus clock frequency division setting bits" "1,1/2,1/4,1/8"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "APBC1_PSR,APB1 Prescaler Register"
|
|
bitfld.byte 0x00 7. " APBC1EN ,APB1 clock enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " APBC1RST ,APB1 bus reset control bit" "Inactive,Active"
|
|
bitfld.byte 0x00 0.--1. " APBC1 ,APB1 bus clock frequency division setting bits" "1,1/2,1/4,1/8"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "SWC_PSR,Software Watchdog Clock Prescaler Register"
|
|
bitfld.byte 0x00 7. " TESTB ,TEST bit" ",1"
|
|
bitfld.byte 0x00 0.--1. " SWDS ,Software watchdog clock frequency division ratio setting bits" "1,1/2,1/4,1/8"
|
|
group.byte 0x30++0x00
|
|
line.byte 0x00 "CSW_TMR,Clock Stabilization Wait Time Register"
|
|
bitfld.byte 0x00 4.--7. " SOWT ,Sub clock stabilization wait time setup bits (cycles)" "2^10,2^11,2^12,2^13,2^14,2^15,2^16,2^17,2^18,2^19,2^20,2^21,2^1,2^2,2^3,2^4"
|
|
bitfld.byte 0x00 0.--3. " MOWT ,Main clock stabilization wait time setup bits (cycles)" "2^1,2^5,2^6,2^7,2^8,2^9,2^10,2^11,2^12,2^13,2^14,2^15,2^17,2^19,2^21,2^23"
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "PSW_TMR,PLL Clock Stabilization Wait Time Setup Register"
|
|
bitfld.byte 0x00 4. " PINC ,PLL input clock select bit" "CLKMO,CLKHC"
|
|
bitfld.byte 0x00 0.--2. " POWT ,Main PLL clock stabilization wait time setup bits (cycles)" "2^9,2^10,2^11,2^12,2^13,2^14,2^15,2^16"
|
|
group.byte 0x38++0x00
|
|
line.byte 0x00 "PLL_CTL1,PLL Control Register 1"
|
|
bitfld.byte 0x00 4.--7. " PLLK ,PLL input clock frequency division ratio setting bits" "1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.byte 0x00 0.--3. " PLLM ,PLL VCO clock frequency division ratio setting bits" "1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
group.byte 0x3C++0x00
|
|
line.byte 0x00 "PLL_CTL2,PLL Control Register 2"
|
|
bitfld.byte 0x00 0.--5. " PLLN ,PLL feedback frequency division ratio setting bits" "1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,?..."
|
|
group.byte 0x54++0x00
|
|
line.byte 0x00 "DBWDT_CTL,Debug Break Watchdog Timer Control Register"
|
|
bitfld.byte 0x00 7. " DPHWBE ,HW-WDG debug mode break bit" "Stopped,Continued"
|
|
bitfld.byte 0x00 5. " DPSWBE ,SW-WDG debug mode break bit" "Stopped,Continued"
|
|
group.byte 0x60++0x04
|
|
line.byte 0x00 "INT_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.byte 0x04 5. 0x00 5. 0x08 5. " FCSE ,Anomalous frequency detection interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x04 2. 0x00 2. 0x08 2. " PCSE ,PLL oscillation stabilization wait completion interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x04 1. 0x00 1. 0x08 1. " SCSE ,Sub clock oscillation stabilization wait completion interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x04 0. 0x00 0. 0x08 0. " MCSE ,Main clock oscillation stabilization wait completion interrupt enable bit" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "Peripheral Clock Gating Function Registers"
|
|
base ad:0x4003C100
|
|
width 7.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CKEN0,Peripheral Function Clock Control Register 0"
|
|
bitfld.long 0x00 28. " GIOCK ,Software clock control of GPIO/Fast GPIO function" "Gated,Supplied"
|
|
bitfld.long 0x00 24. " DMACK ,Supplying and gating settings of DMAC operation clock" "Gated,Supplied"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ADCCK[3] ,Settings for operation clock supplying and gating to AD converter unit 3" "Gated,Supplied"
|
|
bitfld.long 0x00 18. " [2] ,Settings for operation clock supplying and gating to AD converter unit 2" "Gated,Supplied"
|
|
bitfld.long 0x00 17. " [1] ,Settings for operation clock supplying and gating to AD converter unit 1" "Gated,Supplied"
|
|
bitfld.long 0x00 16. " [0] ,Settings for operation clock supplying and gating to AD converter unit 0" "Gated,Supplied"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MFSCK[15] ,Multi-function serial interface channel 15" "Gated,Supplied"
|
|
bitfld.long 0x00 14. " [14] ,Multi-function serial interface channel 14" "Gated,Supplied"
|
|
textline " "
|
|
bitfld.long 0x00 13. " [13] ,Multi-function serial interface channel 13" "Gated,Supplied"
|
|
bitfld.long 0x00 12. " [12] ,Multi-function serial interface channel 12" "Gated,Supplied"
|
|
bitfld.long 0x00 11. " [11] ,Multi-function serial interface channel 11" "Gated,Supplied"
|
|
bitfld.long 0x00 10. " [10] ,Multi-function serial interface channel 10" "Gated,Supplied"
|
|
textline " "
|
|
bitfld.long 0x00 9. " [9] ,Multi-function serial interface channel 9" "Gated,Supplied"
|
|
bitfld.long 0x00 8. " [8] ,Multi-function serial interface channel 8" "Gated,Supplied"
|
|
bitfld.long 0x00 7. " [7] ,Multi-function serial interface channel 7" "Gated,Supplied"
|
|
bitfld.long 0x00 6. " [6] ,Multi-function serial interface channel 6" "Gated,Supplied"
|
|
textline " "
|
|
bitfld.long 0x00 5. " [5] ,Multi-function serial interface channel 5" "Gated,Supplied"
|
|
bitfld.long 0x00 4. " [4] ,Multi-function serial interface channel 4" "Gated,Supplied"
|
|
bitfld.long 0x00 3. " [3] ,Multi-function serial interface channel 3" "Gated,Supplied"
|
|
bitfld.long 0x00 2. " [2] ,Multi-function serial interface channel 2" "Gated,Supplied"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Multi-function serial interface channel 1" "Gated,Supplied"
|
|
bitfld.long 0x00 0. " [0] ,Multi-function serial interface channel 0" "Gated,Supplied"
|
|
line.long 0x04 "MRST0,Peripheral Reset Control Register 0"
|
|
bitfld.long 0x04 24. " DMARST ,Reset control of DMAC" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ADCRST[3] ,Reset control of AD converter unit 3" "No reset,Reset"
|
|
bitfld.long 0x04 18. " [2] ,Reset control of AD converter unit 2" "No reset,Reset"
|
|
bitfld.long 0x04 17. " [1] ,Reset control of AD converter unit 1" "No reset,Reset"
|
|
bitfld.long 0x04 16. " [0] ,Reset control of AD converter unit 0" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 15. " MFSRST[15] ,Multi-function serial interface channel 15" "No reset,Reset"
|
|
bitfld.long 0x04 14. " [14] ,Multi-function serial interface channel 14" "No reset,Reset"
|
|
bitfld.long 0x04 13. " [13] ,Multi-function serial interface channel 13" "No reset,Reset"
|
|
bitfld.long 0x04 12. " [12] ,Multi-function serial interface channel 12" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 11. " [11] ,Multi-function serial interface channel 11" "No reset,Reset"
|
|
bitfld.long 0x04 10. " [10] ,Multi-function serial interface channel 10" "No reset,Reset"
|
|
bitfld.long 0x04 9. " [9] ,Multi-function serial interface channel 9" "No reset,Reset"
|
|
bitfld.long 0x04 8. " [8] ,Multi-function serial interface channel 8" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 7. " [7] ,Multi-function serial interface channel 7" "No reset,Reset"
|
|
bitfld.long 0x04 6. " [6] ,Multi-function serial interface channel 6" "No reset,Reset"
|
|
bitfld.long 0x04 5. " [5] ,Multi-function serial interface channel 5" "No reset,Reset"
|
|
bitfld.long 0x04 4. " [4] ,Multi-function serial interface channel 4" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [3] ,Multi-function serial interface channel 3" "No reset,Reset"
|
|
bitfld.long 0x04 2. " [2] ,Multi-function serial interface channel 2" "No reset,Reset"
|
|
bitfld.long 0x04 1. " [1] ,Multi-function serial interface channel 1" "No reset,Reset"
|
|
bitfld.long 0x04 0. " [0] ,Multi-function serial interface channel 0" "No reset,Reset"
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "CKEN1,Peripheral Function Clock Control Register 1"
|
|
bitfld.long 0x00 19. " QDUCK[3] ,Settings for operation clock supply and gating of quad counter unit 3" "Gated,Supplied"
|
|
bitfld.long 0x00 18. " [2] ,Settings for operation clock supply and gating of quad counter unit 2" "Gated,Supplied"
|
|
bitfld.long 0x00 17. " [1] ,Settings for operation clock supply and gating of quad counter unit 1" "Gated,Supplied"
|
|
bitfld.long 0x00 16. " [0] ,Settings for operation clock supply and gating of quad counter unit 0" "Gated,Supplied"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MFTCK[3] ,Settings for operation clock supply and gating of multi-function timer 3 and PPG channels 24, 26, 28, 30" "Gated,Supplied"
|
|
bitfld.long 0x00 10. " [2] ,Settings for operation clock supply and gating of multi-function timer 2 and PPG channels 16, 18, 20, 22" "Gated,Supplied"
|
|
bitfld.long 0x00 9. " [1] ,Settings for operation clock supply and gating of multi-function timer 1 and PPG channels 8, 10, 12, 14" "Gated,Supplied"
|
|
bitfld.long 0x00 8. " [0] ,Settings for operation clock supply and gating of multi-function timer 0 and PPG channels 0, 2, 4, 6" "Gated,Supplied"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BTMCK[3] ,Settings operation clock supply and gating to base timer channel 12, 13, 14, 15" "Gated,Supplied"
|
|
bitfld.long 0x00 2. " [2] ,Settings operation clock supply and gating to base timer channel 8, 9, 10, 11" "Gated,Supplied"
|
|
bitfld.long 0x00 1. " [1] ,Settings operation clock supply and gating to base timer channel 4, 5, 6, 7" "Gated,Supplied"
|
|
bitfld.long 0x00 0. " [0] ,Settings operation clock supply and gating to base timer channel 0, 1, 2, 3" "Gated,Supplied"
|
|
line.long 0x04 "MRST1,Peripheral Function Reset Control Register 1"
|
|
bitfld.long 0x04 19. " QDURST[3] ,Reset control of quad counter unit 3" "No reset,Reset"
|
|
bitfld.long 0x04 18. " [2] ,Reset control of quad counter unit 2" "No reset,Reset"
|
|
bitfld.long 0x04 17. " [1] ,Reset control of quad counter unit 1" "No reset,Reset"
|
|
bitfld.long 0x04 16. " [0] ,Reset control of quad counter unit 0" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 11. " MFTRST[3] ,Control of multi-function timer unit 3 and PPG channel 24, 26, 28, 30 reset control" "No reset,Reset"
|
|
bitfld.long 0x04 10. " [2] ,Control of multi-function timer unit 2 and PPG channel 16, 18, 20, 22 reset control" "No reset,Reset"
|
|
bitfld.long 0x04 9. " [1] ,Control of multi-function timer unit 1 and PPG channel 8, 10, 12, 14 reset control" "No reset,Reset"
|
|
bitfld.long 0x04 8. " [0] ,Control of multi-function timer unit 0 and PPG channel 0, 2, 4, 6 reset control" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 3. " BTMRST[3] ,Reset control of base timer channels 12, 13, 14, 15" "No reset,Reset"
|
|
bitfld.long 0x04 2. " [2] ,Reset control of base timer channels 8, 9, 10, 11" "No reset,Reset"
|
|
bitfld.long 0x04 1. " [1] ,Reset control of base timer channels 4, 5, 6, 7" "No reset,Reset"
|
|
bitfld.long 0x04 0. " [0] ,Reset control of base timer channels 0, 1, 2, 3" "No reset,Reset"
|
|
sif (cpuis("S6E1C*"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "CKEN2,Peripheral Clock Control Register 2"
|
|
bitfld.long 0x00 20. " PCRCCK ,Settings for operation clock supply and gating to programmable-CRC" "Gated,Supplied"
|
|
bitfld.long 0x00 18. " CECCK ,Settings for operation clock supply and gating of HDMI-CEC/remote control reception" "Gated,Supplied"
|
|
bitfld.long 0x00 16. " LCDCCK ,Settings for operation clock supply and gating to LCD controller" "Gated,Supplied"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I2SCCK[1] ,MFS I2S interface channel 6" "Gated,Supplied"
|
|
bitfld.long 0x00 14. " [0] ,MFS I2S interface channel 4" "Gated,Supplied"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICCCK[1] ,Smart-Card interface channel 1" "Gated,Supplied"
|
|
bitfld.long 0x00 12. " [0] ,Smart-Card interface channel 0" "Gated,Supplied"
|
|
bitfld.long 0x00 1. " USBCK[1] ,Setting for operation clock supply and gating of USB channel 1" "Gated,Supplied"
|
|
bitfld.long 0x00 0. " [0] ,Setting for operation clock supply and gating of USB channel 1" "Gated,Supplied"
|
|
line.long 0x04 "MRST2,Peripheral Function Reset Control Register 2"
|
|
bitfld.long 0x04 20. " PCRCRST ,Reset control of programmable-CRC" "No reset,Reset"
|
|
bitfld.long 0x04 18. " CECRST ,Reset control of HDMI-CEC/remote control reception" "No reset,Reset"
|
|
bitfld.long 0x04 16. " LCDCRST ,Reset control of LCD controller" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 15. " I2SCRST[1] ,Reset control of MFSI2S interface channel 6" "No reset,Reset"
|
|
bitfld.long 0x04 14. " [0] ,Reset control of MFSI2S interface channel 4" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ICCRST[1] ,Reset control of smart-card interface channel 1" "No reset,Reset"
|
|
bitfld.long 0x04 12. " [0] ,Reset control of smart-card interface channel 0" "No reset,Reset"
|
|
bitfld.long 0x04 1. " USBRST[1] , Reset control of USB 1" "No reset,Reset"
|
|
bitfld.long 0x04 0. " [0] , Reset control of USB 0" "No reset,Reset"
|
|
else
|
|
rgroup.long 0x20++0x07
|
|
line.long 0x00 "CKEN2,Peripheral Function Clock Control Register 2"
|
|
bitfld.long 0x00 5. " CANCK1 ,Settings for clock supply and gating to CAN controller channel 1" "Gated,Supplied"
|
|
bitfld.long 0x00 4. " CANCK0 ,Settings for clock supply and gating to CAN controller channel 0" "Gated,Supplied"
|
|
line.long 0x04 "MRST2,Peripheral Function Reset Control Reset 2"
|
|
bitfld.long 0x04 5. " CANRST1 ,Reset control of CAN controller channel 1" "No reset,Reset"
|
|
bitfld.long 0x04 4. " CANRST0 ,Reset control of CAN controller channel 0" "No reset,Reset"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "High-Speed CR Trimming"
|
|
base ad:0x4002E000
|
|
width 10.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MCR_PSR,High-Speed CR Oscillation Frequency Division Setup Register"
|
|
bitfld.byte 0x00 0.--2. " CSR ,High-speed CR oscillation frequency division ratio setting bits" "/4,/8,/16,/32,/64,/128,/256,/512"
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "MCR_FTRM,High-Speed CR Oscillation Frequency Trimming Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " TRD ,Frequency trimming setup bits"
|
|
line.long 0x04 "MCR_TTRM,High-Speed CR Oscillation Temperature Trimming Setup Register"
|
|
sif cpuis("S6E1C*")
|
|
hexmask.long.byte 0x04 0.--6. 1. " TRT ,Temperature trimming setup bits"
|
|
else
|
|
bitfld.long 0x04 0.--4. " TRT ,Temperature trimming setup bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
line.long 0x08 "MCR_RLR,High-Speed CR Oscillation Register Write-Protect Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Low-speed CR Prescaler"
|
|
base ad:0x4003C000
|
|
width 12.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "LCR_PRSLD,Low-Speed CR Prescaler Control Register"
|
|
bitfld.byte 0x00 0.--5. " LCR_PRSLD ,Low-speed CR prescaler load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
width 0xB
|
|
tree.end
|
|
tree "Clock supervisor"
|
|
base ad:0x40010000
|
|
width 11.
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "CSV_CTL,CSV Control Register"
|
|
bitfld.word 0x00 12.--14. " FCD ,FCS count cycle setting bits" ",,,,,1/256,1/512,1/1024"
|
|
bitfld.word 0x00 9. " FCSRE ,FCS reset output enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " FCSDE ,FCS function enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " SCSVE ,Sub CSV function enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " MCSVE ,Main CSV function enable bit" "Disabled,Enabled"
|
|
sif cpuis("S6E1C*")
|
|
hgroup.byte 0x44++0x00
|
|
hide.byte 0x00 "CSV_STR,CSV Status Register"
|
|
in
|
|
else
|
|
rgroup.byte 0x44++0x00
|
|
line.byte 0x00 "CSV_STR,CSV Status Register"
|
|
bitfld.byte 0x00 1. " SCMF ,Sub clock failure detection flag" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " MCMF ,Main clock failure detection flag" "Not detected,Detected"
|
|
endif
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "FCSWH_CTL,Frequency Detection Window Setting Register (Upper)"
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "FCSWL_CTL,Frequency Detection Window Setting Register (Lower)"
|
|
rgroup.word 0x50++0x01
|
|
line.word 0x00 "FCSWD_CTL,Frequency Detection Counter register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Resets"
|
|
base ad:0x40010000
|
|
width 9.
|
|
hgroup.word 0x0C++0x01
|
|
hide.word 0x00 "RST_STR,Reset Factor Register"
|
|
in
|
|
width 0xB
|
|
tree.end
|
|
tree "Low-voltage Detection"
|
|
base ad:0x40035000
|
|
width 10.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "LVD_CTL,Low-Voltage Detection Voltage Control Register"
|
|
bitfld.word 0x00 15. " LVDRE ,Low-voltage detection reset operation enable bit" "Disabled,Enabled"
|
|
sif !cpuis("S6E1C*")
|
|
bitfld.word 0x00 10.--14. " SVHR ,Low-voltage detection reset voltage setting bits" "2.45 V,2.60 V,2.70 V,2.80 V,3.00 V,3.20 V,3.60 V,3.70 V,4.00 V,4.10 V,4.20 V,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 7. " LVDIE ,Low-voltage detection interrupt enable bit" "Disabled,Enabled"
|
|
sif cpuis("S6E1C*")
|
|
bitfld.word 0x00 2.--6. " SVHI ,Low-voltage detection interrupt voltage setting bits" "1.50 V,1.55 V,1.60 V,1.65 V,1.70 V,1.75 V,1.80 V,1.85 V,1.90 V,1.95 V,2.00 V,2.05 V,2.50 V,2.60 V,2.70 V,2.80 V,2.90 V,3.00 V,3.10 V,3.20 V,?..."
|
|
else
|
|
bitfld.word 0x00 2.--6. " SVHI ,Low-voltage detection interrupt voltage setting bits" "2.80 V,3.00 V,3.20 V,3.60 V,3.70 V,4.00 V,4.10 V,4.20 V,?..."
|
|
endif
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "LVD_STR,Low-Voltage Detection Interrupt Factor Register"
|
|
bitfld.byte 0x00 7. " LVDIR ,Low-voltage detection interrupt factor bit" "Not detected,Detected"
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "LVD_CLR,Low-Voltage Detection Interrupt Factor Clear Register"
|
|
bitfld.byte 0x00 7. " LVDCL ,Low-voltage detection interrupt factor clear bit" "Cleared,No effect"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "LVD_RLR,Low-Voltage Detection Voltage Protection Register"
|
|
textline " "
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "LVD_STR2,Low-Voltage Detection Circuit Status Register"
|
|
bitfld.byte 0x00 7. " LVDIRDY ,Low-voltage detection interrupt status flag" "Stabilization/Monitoring,Monitoring"
|
|
bitfld.byte 0x00 6. " LVDRRDY ,Low-voltage detection reset status flag" "Stabilization/Monitoring,Monitoring"
|
|
sif cpuis("S6E1C*")
|
|
group.word 0x200++0x01
|
|
line.word 0x00 "CAL_CTL,Vref Calibration Control Register"
|
|
bitfld.word 0x00 3. " CALDONE ,Vref calibration done flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CALSTART ,Vref calibration start bit" ",Started"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "CAL_KEY,Vref Calibration Security Key Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Low Power Consumption Mode"
|
|
base ad:0x40035100
|
|
width 14.
|
|
base ad:0x40010000
|
|
if ((per.l((ad:0x40010000+0x008))&0x004)==0x004)
|
|
if ((per.l((ad:0x40035100+0x700))&0x1)==0x1)
|
|
group.long 0x008++0x03
|
|
line.long 0x00 "STB_CTL,Standby Mode Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " KEY ,Standby mode control write control bits"
|
|
bitfld.long 0x00 4. " SPL ,Standby pin level setting bit" "Retained,High impedance"
|
|
bitfld.long 0x00 2. " DSTM ,Deep standby mode select bit" "Standby,Deep standby"
|
|
bitfld.long 0x00 0.--1. " STM ,Standby mode select bits" ",,Deep standby RTC,?..."
|
|
else
|
|
group.long 0x008++0x03
|
|
line.long 0x00 "STB_CTL,Standby Mode Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " KEY ,Standby mode control write control bits"
|
|
bitfld.long 0x00 4. " SPL ,Standby pin level setting bit" "Retained,High impedance"
|
|
bitfld.long 0x00 2. " DSTM ,Deep standby mode select bit" "Standby,Deep standby"
|
|
bitfld.long 0x00 0.--1. " STM ,Standby mode select bits" ",,Deep standby stop,?..."
|
|
endif
|
|
else
|
|
if ((per.l((ad:0x40035100+0x700))&0x1)==0x1)
|
|
group.long 0x008++0x03
|
|
line.long 0x00 "STB_CTL,Standby Mode Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " KEY ,Standby mode control write control bits"
|
|
bitfld.long 0x00 4. " SPL ,Standby pin level setting bit" "Retained,High impedance"
|
|
bitfld.long 0x00 2. " DSTM ,Deep standby mode select bit" "Standby,Deep standby"
|
|
bitfld.long 0x00 0.--1. " STM ,Standby mode select bits" ",,RTC mode,?..."
|
|
else
|
|
group.long 0x008++0x03
|
|
line.long 0x00 "STB_CTL,Standby Mode Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " KEY ,Standby mode control write control bits"
|
|
bitfld.long 0x00 4. " SPL ,Standby pin level setting bit" "Retained,High impedance"
|
|
bitfld.long 0x00 2. " DSTM ,Deep standby mode select bit" "Standby,Deep standby"
|
|
bitfld.long 0x00 0.--1. " STM ,Standby mode select bits" "TIMER mode,,STOP mode,?..."
|
|
endif
|
|
endif
|
|
base ad:0x40035100
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "REG_CTL,Sub Oscillation Circuit Power Supply Control Register"
|
|
bitfld.byte 0x00 1.--2. " ISUBSEL ,Sub oscillation circuit current setting bits" ",,360nA,"
|
|
group.byte 0x004++0x00
|
|
line.byte 0x00 "RCK_CTL,Sub Clock Control Register"
|
|
bitfld.byte 0x00 1. " CECCKE ,CEC clock control bit" "Not supplied,Supplied"
|
|
bitfld.byte 0x00 0. " RTCCKE ,RTC clock control bit" "Not supplied,Supplied"
|
|
group.byte 0x700++0x00
|
|
line.byte 0x00 "PMD_CTL,RTC Mode Control Register"
|
|
bitfld.byte 0x00 0. " RTCE ,RTC mode control bit" "STOP mode,RTC mode"
|
|
textline " "
|
|
hgroup.byte 0x704++0x00
|
|
hide.byte 0x00 "WRFSR,Deep Standby Return Factor Register 1"
|
|
in
|
|
hgroup.word 0x708++0x01
|
|
hide.word 0x00 "WIFSR,Deep Standby Return Factor Register 2"
|
|
in
|
|
textline " "
|
|
group.word 0x70C++0x01
|
|
line.word 0x00 "WIER,Deep Standby Return Enable Register"
|
|
sif cpuis("S6E1C*")
|
|
bitfld.word 0x00 15. " WUI11E ,WKUP11 pin input return enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " WUI10E ,WKUP10 pin input return enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " WUI9E ,WKUP9 pin input return enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " WUI8E ,WKUP8 pin input return enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " WUI7E ,WKUP7 pin input return enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " WUI6E ,WKUP6 pin input return enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.word 0x00 9. " WCEC1E ,HDMI-CEC/ remote control reception ch.1 interrupt return enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " WCEC0E ,HDMI-CEC/ remote control reception ch.0 interrupt return enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " WUI5E ,WKUP5 pin input return enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " WUI4E ,WKUP4 pin input return enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " WUI3E ,WKUP3 pin input return enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " WUI2E ,WKUP2 pin input return enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " WUI1E ,WKUP1 pin input return enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " WLVDE ,LVD interrupt return enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " WRTCE ,RTC interrupt return enable bit" "Disabled,Enabled"
|
|
sif cpuis("S6E1C*")
|
|
group.word 0x710++0x01
|
|
line.word 0x00 "WILVR,WKUP Pin Input Level Register"
|
|
bitfld.word 0x00 10. " WUI11LV ,WKUP11 pin input level select bit" "Low,High"
|
|
bitfld.word 0x00 9. " WUI10LV ,WKUP10 pin input level select bit" "Low,High"
|
|
bitfld.word 0x00 8. " WUI9LV ,WKUP9 pin input level select bit" "Low,High"
|
|
bitfld.word 0x00 7. " WUI8LV ,WKUP8 pin input level select bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 6. " WUI7LV ,WKUP7 pin input level select bit" "Low,High"
|
|
bitfld.word 0x00 5. " WUI6LV ,WKUP6 pin input level select bit" "Low,High"
|
|
bitfld.word 0x00 4. " WUI5LV ,WKUP5 pin input level select bit" "Low,High"
|
|
bitfld.word 0x00 3. " WUI4LV ,WKUP4 pin input level select bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 2. " WUI3LV ,WKUP3 pin input level select bit" "Low,High"
|
|
bitfld.word 0x00 1. " WUI2LV ,WKUP2 pin input level select bit" "Low,High"
|
|
bitfld.word 0x00 0. " WUI1LV ,WKUP1 pin input level select bit" "Low,High"
|
|
else
|
|
group.byte 0x710++0x00
|
|
line.byte 0x00 "WILVR,WKUP Pin Input Level Register"
|
|
bitfld.byte 0x00 7. " WUI5LV ,WKUP5 pin input level select bits" "Low,High"
|
|
bitfld.byte 0x00 6. " WUI4LV ,WKUP4 pin input level select bits" "Low,High"
|
|
bitfld.byte 0x00 5. " WUI3LV ,WKUP3 pin input level select bits" "Low,High"
|
|
bitfld.byte 0x00 4. " WUI2LV ,WKUP2 pin input level select bits" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " WUI1LV ,WKUP1 pin input level select bits" "Low,High"
|
|
endif
|
|
group.byte 0x714++0x00
|
|
line.byte 0x00 "DSRAMR,Deep Standby RAM Retention Register"
|
|
bitfld.byte 0x00 0.--1. " SRAMR ,On-chip SRAM retention control bits" "Not retained,,,Retained"
|
|
textline " "
|
|
group.byte 0x800++0x00
|
|
line.byte 0x00 "BUR_1,Backup Register 1"
|
|
group.byte 0x801++0x00
|
|
line.byte 0x00 "BUR_2,Backup Register 2"
|
|
group.byte 0x802++0x00
|
|
line.byte 0x00 "BUR_3,Backup Register 3"
|
|
group.byte 0x803++0x00
|
|
line.byte 0x00 "BUR_4,Backup Register 4"
|
|
group.byte 0x804++0x00
|
|
line.byte 0x00 "BUR_5,Backup Register 5"
|
|
group.byte 0x805++0x00
|
|
line.byte 0x00 "BUR_6,Backup Register 6"
|
|
group.byte 0x806++0x00
|
|
line.byte 0x00 "BUR_7,Backup Register 7"
|
|
group.byte 0x807++0x00
|
|
line.byte 0x00 "BUR_8,Backup Register 8"
|
|
group.byte 0x808++0x00
|
|
line.byte 0x00 "BUR_9,Backup Register 9"
|
|
group.byte 0x809++0x00
|
|
line.byte 0x00 "BUR_10,Backup Register 10"
|
|
group.byte 0x80A++0x00
|
|
line.byte 0x00 "BUR_11,Backup Register 11"
|
|
group.byte 0x80B++0x00
|
|
line.byte 0x00 "BUR_12,Backup Register 12"
|
|
group.byte 0x80C++0x00
|
|
line.byte 0x00 "BUR_13,Backup Register 13"
|
|
group.byte 0x80D++0x00
|
|
line.byte 0x00 "BUR_14,Backup Register 14"
|
|
group.byte 0x80E++0x00
|
|
line.byte 0x00 "BUR_15,Backup Register 15"
|
|
group.byte 0x80F++0x00
|
|
line.byte 0x00 "BUR_16,Backup Register 16"
|
|
sif cpuis("S6E1C*")
|
|
textline " "
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MOSC_CTL,Main Oscillation Crystal Type Selection Control Register"
|
|
bitfld.byte 0x00 1.--2. " IMAINSEL ,Main oscillation circuit current setting bits" ",8MHz,16MHz,48MHz"
|
|
group.long 0x900++0x03
|
|
line.long 0x00 "WIOLC_CTL,IO State Hold Control Register"
|
|
bitfld.long 0x00 16. " LHX_ST ,IO state bit" "Held,Released"
|
|
bitfld.long 0x00 8. " CONTX ,IO state hold function enable bit" "Yes,No"
|
|
bitfld.long 0x00 0. " LH_CL ,IO state hold release bit" "No effect,Released"
|
|
if ((per.l((ad:0x40010000+0x008))&0x004)==0x004)
|
|
group.byte 0x904++0x00
|
|
line.byte 0x00 "SUBOSC_CTL,Sub Oscillator IO Control Register"
|
|
bitfld.byte 0x00 0.--1. " SUBXC ,Sub clock (oscillation) pin setting register" "X0A & X1A as digital pins,X0A & A1A as sub,?..."
|
|
else
|
|
group.byte 0x904++0x00
|
|
line.byte 0x00 "SUBOSC_CTL,Sub Oscillator IO Control Register"
|
|
bitfld.byte 0x00 0.--1. " SUBXC ,Sub clock (oscillation) pin setting register" "X0A & X1A - digital pins,X0A & A1A - sub clock,,X0A - external clock input & X1A - digital pin"
|
|
endif
|
|
group.byte 0x908++0x00
|
|
line.byte 0x00 "CEC_CTL,CEC Input/Output Control Register"
|
|
bitfld.byte 0x00 2.--3. " WS_CECR1B ,CEC1 input/output selection bits" "Not used,Used,?..."
|
|
bitfld.byte 0x00 0.--1. " WS_CECR0B ,CEC0 input/output selection bits" "Not used,Used,?..."
|
|
group.byte 0x90C++0x00
|
|
line.byte 0x00 "DEBUG_SW_CTL,Serial Wire Debug Control Register"
|
|
bitfld.byte 0x00 0. " DBG_EN ,SWD enable bit" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("S6E1C*")
|
|
tree "Interrupts"
|
|
base ad:0x40031000
|
|
width 12.
|
|
rgroup.long 0x200++0x0F
|
|
line.long 0x00 "EXC02MON,EXC02 Batch Read Register"
|
|
bitfld.long 0x00 1. " HWINT ,The hardware watchdog timer interrupt request occurred" "Occurred,Not occurred"
|
|
bitfld.long 0x00 0. " NMI ,The interrupt request of the NMIX external pin occurred" "Occurred,Not occurred"
|
|
line.long 0x04 "IRQ00MON,IRQ00 Batch Read Register"
|
|
bitfld.long 0x04 2. " INT2 ,The interrupt assigned to low-voltage detection (LVD) occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x04 1. " INT1 ,The interrupt assigned to software watchdog timer occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x04 0. " INT0 ,The interrupt assigned to anomalous frequency detection occurred" "Not occurred,Occurred"
|
|
line.long 0x08 "IRQ01MON,IRQ01 Batch Read Register"
|
|
bitfld.long 0x08 2. " INT2 ,The interrupt assigned to MFS ch.0 status occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x08 1. " INT1 ,The interrupt assigned to FS ch.0 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x08 0. " INT0 ,The interrupt assigned to MFS ch.0 reception occurred" "Not occurred,Occurred"
|
|
line.long 0x0C "IRQ02MON,IRQ02 Batch Read Register"
|
|
bitfld.long 0x0C 2. " INT2 ,The interrupt assigned to MFS ch.1 status occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 1. " INT1 ,The interrupt assigned to MFS ch.1 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 0. " INT0 ,The interrupt assigned to MFS ch.1 reception occurred" "Not occurred,Occurred"
|
|
hgroup.long 0x210++0x03
|
|
hide.long 0x00 "IRQ03MON,IRQ02 Batch Read Register"
|
|
rgroup.long 0x214++0x07
|
|
line.long 0x00 "IRQ04MON,IRQ04 Batch Read Register"
|
|
bitfld.long 0x00 2. " INT2 ,The interrupt assigned to MFS ch.3 status occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " INT1 ,The interrupt assigned to MFS ch.3 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " INT0 ,The interrupt assigned to MFS ch.3 reception occurred" "Not occurred,Occurred"
|
|
line.long 0x04 "IRQ05MON,IRQ05 Batch Read Register"
|
|
bitfld.long 0x04 2. " INT2 ,The interrupt assigned to MFS ch.4 status occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x04 1. " INT1 ,The interrupt assigned to MFS ch.4 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x04 0. " INT0 ,The interrupt assigned to MFS ch.4 reception occurred" "Not occurred,Occurred"
|
|
hgroup.long 0x21C++0x03
|
|
hide.long 0x00 "IRQ06MON,IRQ06 Batch Read Register"
|
|
rgroup.long 0x220++0x37
|
|
line.long 0x00 "IRQ07MON,IRQ07 Batch Read Register"
|
|
bitfld.long 0x00 2. " INT2 ,The interrupt assigned to MFS ch.6/I2CSLAVE status occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " INT1 ,The interrupt assigned to MFS ch.6/I2CSLAVE transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " INT0 ,The interrupt assigned to MFS ch.6/I2CSLAVE reception occurred" "Not occurred,Occurred"
|
|
line.long 0x04 "IRQ08MON,IRQ08 Batch Read Register"
|
|
bitfld.long 0x04 2. " INT2 ,The interrupt assigned to MFS ch.7 status occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x04 1. " INT1 ,The interrupt assigned to MFS ch.7 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x04 0. " INT0 ,The interrupt assigned to MFS ch.7 reception occurred" "Not occurred,Occurred"
|
|
line.long 0x08 "IRQ09MON,IRQ09 Batch Read Register"
|
|
bitfld.long 0x08 2. " INT2 ,The interrupt assigned to A/D converter unit0 range comparison result/conversion result comparison/FIFO overrun occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x08 1. " INT1 ,The interrupt assigned to A/D converter unit0 scan conversion occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x08 0. " INT0 ,The interrupt assigned to A/D converter unit0 priority conversion occurred" "Not occurred,Occurred"
|
|
line.long 0x0C "IRQ10MON,IRQ10 Batch Read Register"
|
|
bitfld.long 0x0C 2. " INT2 ,The interrupt assigned to USB ch.0 device endpoint3 DRQ occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 1. " INT1 ,The interrupt assigned to USB ch.0 device endpoint2 DRQ occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 0. " INT0 ,The interrupt assigned to USB ch.0 device endpoint1 DRQ occurred" "Not occurred,Occurred"
|
|
line.long 0x10 "IRQ11MON,IRQ11 Batch Read Register"
|
|
bitfld.long 0x10 2. " INT2 ,The interrupt assigned to USB ch.0 device endpoint0 DRQI occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x10 1. " INT1 ,The interrupt assigned to USB ch.0 device endpoint5 DRQ occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x10 0. " INT0 ,The interrupt assigned to USB ch.0 device endpoint4 DRQ occurred" "Not occurred,Occurred"
|
|
line.long 0x14 "IRQ12MON,IRQ12 Batch Read Register"
|
|
bitfld.long 0x14 2. " INT2 ,The interrupt assigned to USB ch.0 device SPK occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x14 1. " INT1 ,The interrupt assigned to USB ch.0 device WKUP/CONF/BRST/SOF/SUSP occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x14 0. " INT0 ,The interrupt assigned to USB ch.0 device endpoint0 DRQO occurred" "Not occurred,Occurred"
|
|
line.long 0x18 "IRQ13MON,IRQ13 Batch Read Register"
|
|
bitfld.long 0x18 1. " INT1 ,The interrupt assigned to USB ch.0 host SOFIRQ/CMPIRQ occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x18 0. " INT0 ,The interrupt assigned to USB ch.0 host DIRQ/URIRQ/RWKIRQ/CNNIRQ occurred" "Not occurred,Occurred"
|
|
line.long 0x1C "IRQ14MON,IRQ14 Batch Read Register"
|
|
bitfld.long 0x1C 0. " INT0 ,The interrupt assigned to main PLL/main clock/sub clock stabilization wait completion occurred" "Not occurred,Occurred"
|
|
line.long 0x20 "IRQ15MON,IRQ15 Batch Read Register"
|
|
bitfld.long 0x20 1. " INT1 ,The interrupt assigned to RTC/dual timer ch.1/dual timer ch.2 occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x20 0. " INT0 ,The interrupt assigned to Watch counter interrupt occurred" "Not occurred,Occurred"
|
|
line.long 0x24 "IRQ16MON,IRQ16 Batch Read Register"
|
|
bitfld.long 0x24 1. " INT1 ,The interrupt assigned to external pin ch.1 occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x24 0. " INT0 ,The interrupt assigned to external pin ch.0 occurred" "Not occurred,Occurred"
|
|
line.long 0x28 "IRQ17MON,IRQ17 Batch Read Register"
|
|
bitfld.long 0x28 1. " INT1 ,The interrupt assigned to external pin ch.3 occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x28 0. " INT0 ,The interrupt assigned to external pin ch.2 occurred" "Not occurred,Occurred"
|
|
line.long 0x2C "IRQ18MON,IRQ18 Batch Read Register"
|
|
bitfld.long 0x2C 1. " INT1 ,The interrupt assigned to external pin ch.5 occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x2C 0. " INT0 ,The interrupt assigned to external pin ch.4 occurred" "Not occurred,Occurred"
|
|
line.long 0x30 "IRQ19MON,IRQ19 Batch Read Register"
|
|
bitfld.long 0x30 1. " INT1 ,The interrupt assigned to external pin ch.7 occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x30 0. " INT0 ,The interrupt assigned to external pin ch.6 occurred" "Not occurred,Occurred"
|
|
line.long 0x34 "IRQ20MON,IRQ20 Batch Read Register"
|
|
bitfld.long 0x34 0. " INT0 ,The interrupt assigned to external pin ch.8 occurred" "Not occurred,Occurred"
|
|
hgroup.long 0x258++0x03
|
|
hide.long 0x00 "IRQ21MON,IRQ21 Batch Read Register"
|
|
rgroup.long 0x25C++0x23
|
|
line.long 0x00 "IRQ22MON,IRQ22 Batch Read Register"
|
|
bitfld.long 0x00 1. " INT1 ,The interrupt assigned to external pin ch.13 occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " INT1 ,The interrupt assigned to external pin ch.12 occurred" "Not occurred,Occurred"
|
|
line.long 0x04 "IRQ23MON,IRQ23 Batch Read Register"
|
|
bitfld.long 0x04 1. " INT1 ,The interrupt assigned to external pin ch.15 occurred" "Not occurred,Occurred"
|
|
line.long 0x08 "IRQ24MON,IRQ24 Batch Read Register"
|
|
bitfld.long 0x08 1. " INT1 ,The interrupt assigned to case timer ch.4 source1/source0 occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x08 0. " INT0 ,The interrupt assigned to case timer ch.0 source1/source0 occurred" "Not occurred,Occurred"
|
|
line.long 0x0C "IRQ25MON,IRQ25 Batch Read Register"
|
|
bitfld.long 0x0C 1. " INT1 ,The interrupt assigned to case timer ch.5 source1/source0 occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 0. " INT0 ,The interrupt assigned to case timer ch.1 source1/source0 occurred" "Not occurred,Occurred"
|
|
line.long 0x10 "IRQ26MON,IRQ26 Batch Read Register"
|
|
bitfld.long 0x10 1. " INT1 ,The interrupt assigned to case timer ch.6 source1/source0 occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x10 0. " INT0 ,The interrupt assigned to case timer ch.2 source1/source0 occurred" "Not occurred,Occurred"
|
|
line.long 0x14 "IRQ27MON,IRQ27 Batch Read Register"
|
|
bitfld.long 0x14 1. " INT1 ,The interrupt assigned to case timer ch.7 source1/source0 occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x14 0. " INT0 ,The interrupt assigned to case timer ch.3 source1/source0 occurred" "Not occurred,Occurred"
|
|
line.long 0x18 "IRQ28MON,IRQ28 Batch Read Register"
|
|
bitfld.long 0x18 1. " INT1 ,The interrupt assigned to CEC transmission ch.1 occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x18 0. " INT0 ,The interrupt assigned to CEC transmission ch.0 occurred" "Not occurred,Occurred"
|
|
line.long 0x1C "IRQ29MON,IRQ29 Batch Read Register"
|
|
bitfld.long 0x1C 1. " INT1 ,The interrupt assigned to FLASH memory RDY/HANG occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x1C 0. " INT0 ,The interrupt assigned to Smart Card ch.1 occurred" "Not occurred,Occurred"
|
|
line.long 0x20 "IRQ30MON,IRQ30 Batch Read Register"
|
|
bitfld.long 0x20 1. " INT1 ,The interrupt assigned to DSTC error occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x20 0. " INT0 ,The interrupt assigned to DSTC SW transfer complete occurred" "Not occurred,Occurred"
|
|
hgroup.long 0x280++0x03
|
|
hide.long 0x00 "IRQ31MON,IRQ31 Batch Read Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "VIR_OFFSET,VIR Offset Register"
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "ODDPKS,USB ch.0 Odd Packet Size DMA Enable Register"
|
|
bitfld.byte 0x00 4. " ODDPKS[4] ,DMA USB.EP5DT transfer bit width converted" "Not converted,Converted"
|
|
bitfld.byte 0x00 3. " [3] ,DMA USB.EP4DT transfer bit width converted" "Not converted,Converted"
|
|
bitfld.byte 0x00 2. " [2] ,DMA USB.EP3DT transfer bit width converted" "Not converted,Converted"
|
|
bitfld.byte 0x00 1. " [1] ,DMA USB.EP2DT transfer bit width converted" "Not converted,Converted"
|
|
bitfld.byte 0x00 0. " [0] ,DMA USB.EP1DT transfer bit width converted" "Not converted,Converted"
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "Interrupts"
|
|
base ad:0x40031000
|
|
width 10.
|
|
if ((d.b(ad:0x40031000+0x0C)&0x1)==0x0)
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DRQSEL,DMA Request Selection Register"
|
|
bitfld.long 0x00 31. " DRQSEL[31] ,The interrupt signal of the external interrupt ch.3" "CPU,DMAC"
|
|
bitfld.long 0x00 30. " [30] ,The interrupt signal of the external interrupt ch.2" "CPU,DMAC"
|
|
bitfld.long 0x00 29. " [29] ,The interrupt signal of the external interrupt ch.1" "CPU,DMAC"
|
|
bitfld.long 0x00 28. " [28] ,The interrupt signal of the external interrupt ch.0" "CPU,DMAC"
|
|
bitfld.long 0x00 27. " [27] ,The transmission interrupt signal of the MFS ch.7" "CPU,DMAC"
|
|
bitfld.long 0x00 26. " [26] ,The reception interrupt signal of the MFS ch.7" "CPU,DMAC"
|
|
bitfld.long 0x00 25. " [25] ,The transmission interrupt signal of the MFS ch.6" "CPU,DMAC"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,The reception interrupt signal of the MFS ch.6" "CPU,DMAC"
|
|
bitfld.long 0x00 23. " [23] ,The transmission interrupt signal of the MFS ch.5" "CPU,DMAC"
|
|
bitfld.long 0x00 22. " [22] ,The reception interrupt signal of the MFS ch.5" "CPU,DMAC"
|
|
bitfld.long 0x00 21. " [21] ,The transmission interrupt signal of the MFS ch.4" "CPU,DMAC"
|
|
bitfld.long 0x00 20. " [20] ,The reception interrupt signal of the MFS ch.4" "CPU,DMAC"
|
|
bitfld.long 0x00 19. " [19] ,The transmission interrupt signal of the MFS ch.3" "CPU,DMAC"
|
|
bitfld.long 0x00 18. " [18] ,The reception interrupt signal of the MFS ch.3" "CPU,DMAC"
|
|
textline " "
|
|
bitfld.long 0x00 17. " [17] ,The transmission interrupt signal of the MFS ch.2" "CPU,DMAC"
|
|
bitfld.long 0x00 16. " [16] ,The reception interrupt signal of the MFS ch.2" "CPU,DMAC"
|
|
bitfld.long 0x00 15. " [15] ,The transmission interrupt signal of the MFS ch.1" "CPU,DMAC"
|
|
bitfld.long 0x00 14. " [14] ,The reception interrupt signal of the MFS ch.1" "CPU,DMAC"
|
|
bitfld.long 0x00 13. " [13] ,The transmission interrupt signal of the MFS ch.0" "CPU,DMAC"
|
|
bitfld.long 0x00 12. " [12] ,The reception interrupt signal of the MFS ch.0" "CPU,DMAC"
|
|
bitfld.long 0x00 11. " [11] ,The IRQ0 interrupt signal of the base timer ch.6" "CPU,DMAC"
|
|
textline " "
|
|
bitfld.long 0x00 10. " [10] ,The IRQ0 interrupt signal of the base timer ch.4" "CPU,DMAC"
|
|
bitfld.long 0x00 9. " [9] ,The IRQ0 interrupt signal of the base timer ch.2" "CPU,DMAC"
|
|
bitfld.long 0x00 8. " [8] ,The IRQ0 interrupt signal of the base timer ch.0" "CPU,DMAC"
|
|
bitfld.long 0x00 7. " [7] ,The scan conversion interrupt signal of the A/D converter unit 2" "CPU,DMAC"
|
|
bitfld.long 0x00 6. " [6] ,The scan conversion interrupt signal of the A/D converter unit 1" "CPU,DMAC"
|
|
bitfld.long 0x00 5. " [5] ,The scan conversion interrupt signal of the A/D converter unit 0" "CPU,DMAC"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "EXC02MON,EXC02 Batch Read Register"
|
|
bitfld.long 0x00 1. " HWINT ,Hardware watchdog timer interrupt request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NMI ,NMIX external pin interrupt request" "Not requested,Requested"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "IRQ00MON,IRQ00 Batch Read Register"
|
|
bitfld.long 0x00 0. " FCSINT ,Anomalous frequency detection by CSV interrupt request" "Not requested,Requested"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "IRQ01MON,IRQ01 Batch Read Register"
|
|
bitfld.long 0x00 0. " SWWDTINT ,Software watchdog timer interrupt request" "Not requested,Requested"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "IRQ02MON,IRQ02 Batch Read Register"
|
|
bitfld.long 0x00 0. " LVDINT ,Low voltage detection (LVD) interrupt request" "Not requested,Requested"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "IRQ03MON,IRQ03 Batch Read Register"
|
|
bitfld.long 0x00 11. " WAVE2INT[11] ,WFG timer 54 interrupt request in MFT unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 10. " [10] ,WFG timer 32 interrupt request in MFT unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 9. " [9] ,WFG timer 10 interrupt request in MFT unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " [8] ,DTIF (motor emergency stop) interrupt request in MFT unit 2" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WAVE1INT[7] ,WFG timer 54 interrupt request in MFT unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " [6] ,WFG timer 32 interrupt request in MFT unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 5. " [5] ,WFG timer 10 interrupt request in MFT unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " [4] ,DTIF (motor emergency stop) interrupt request in MFT unit 1" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 3. " WAVE0INT[3] ,WFG timer 54 interrupt request in MFT unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,WFG timer 32 interrupt request in MFT unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,WFG timer 10 interrupt request in MFT unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,DTIF (motor emergency stop) interrupt request in MFT 0" "Not requested,Requested"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "IRQ04MON,IRQ04 Batch Read Register"
|
|
bitfld.long 0x00 7. " EXTINT[7] ,Interrupt request of external interrupt ch.7" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " [6] ,Interrupt request of external interrupt ch.6" "Not requested,Requested"
|
|
bitfld.long 0x00 5. " [5] ,Interrupt request of external interrupt ch.5" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " [4] ,Interrupt request of external interrupt ch.4" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " [3] ,Interrupt request of external interrupt ch.3" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,Interrupt request of external interrupt ch.2" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Interrupt request of external interrupt ch.1" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Interrupt request of external interrupt ch.0" "Not requested,Requested"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "IRQ05MON,IRQ05 Batch Read Register"
|
|
bitfld.long 0x00 23. " EXTINT[23] ,Interrupt request of external interrupt ch.31" "Not requested,Requested"
|
|
bitfld.long 0x00 22. " [22] ,Interrupt request of external interrupt ch.30" "Not requested,Requested"
|
|
bitfld.long 0x00 21. " [21] ,Interrupt request of external interrupt ch.29" "Not requested,Requested"
|
|
bitfld.long 0x00 20. " [20] ,Interrupt request of external interrupt ch.28" "Not requested,Requested"
|
|
bitfld.long 0x00 19. " [19] ,Interrupt request of external interrupt ch.27" "Not requested,Requested"
|
|
bitfld.long 0x00 18. " [18] ,Interrupt request of external interrupt ch.26" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " [17] ,Interrupt request of external interrupt ch.25" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Interrupt request of external interrupt ch.24" "Not requested,Requested"
|
|
bitfld.long 0x00 15. " [15] ,Interrupt request of external interrupt ch.23" "Not requested,Requested"
|
|
bitfld.long 0x00 14. " [14] ,Interrupt request of external interrupt ch.22" "Not requested,Requested"
|
|
bitfld.long 0x00 13. " [13] ,Interrupt request of external interrupt ch.21" "Not requested,Requested"
|
|
bitfld.long 0x00 12. " [12] ,Interrupt request of external interrupt ch.20" "Not requested,Requested"
|
|
bitfld.long 0x00 11. " [11] ,Interrupt request of external interrupt ch.19" "Not requested,Requested"
|
|
bitfld.long 0x00 10. " [10] ,Interrupt request of external interrupt ch.18" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 9. " [9] ,Interrupt request of external interrupt ch.17" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " [8] ,Interrupt request of external interrupt ch.16" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " [7] ,Interrupt request of external interrupt ch.15" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " [6] ,Interrupt request of external interrupt ch.14" "Not requested,Requested"
|
|
bitfld.long 0x00 5. " [5] ,Interrupt request of external interrupt ch.13" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " [4] ,Interrupt request of external interrupt ch.12" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " [3] ,Interrupt request of external interrupt ch.11" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 2. " [2] ,Interrupt request of external interrupt ch.10" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Interrupt request of external interrupt ch.9" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Interrupt request of external interrupt ch.8" "Not requested,Requested"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "IRQ06MON,IRQ06 Batch Read Register"
|
|
bitfld.long 0x00 19. " QUD2INT[19] ,PC match & RC match interrupt request of QPRC ch.2" "Not requested,Requested"
|
|
bitfld.long 0x00 18. " [18] ,Interrupt request detected RC out of range on QPRC ch.2" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " [17] ,PC count invert interrupt request of QPRC ch.2" "Not requested,Requested"
|
|
bitfld.long 0x00 16. " [16] ,Overflow/underflow/zero index interrupt request of QPRC ch.2" "Not requested,Requested"
|
|
bitfld.long 0x00 15. " [15] ,PC&RC match interrupt request of QPRC ch.2" "Not requested,Requested"
|
|
bitfld.long 0x00 14. " [14] ,PC match interrupt request of QPRC ch.2" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 13. " QUD1INT[13] ,PC match & RC match interrupt request of QPRC ch.1" "Not requested,Requested"
|
|
bitfld.long 0x00 12. " [12] ,Interrupt request detected RC out of range on QPRC ch.1" "Not requested,Requested"
|
|
bitfld.long 0x00 11. " [11] ,PC count invert interrupt request of QPRC ch.1" "Not requested,Requested"
|
|
bitfld.long 0x00 10. " [10] ,Overflow/underflow/zero index interrupt request of QPRC ch.1" "Not requested,Requested"
|
|
bitfld.long 0x00 9. " [9] ,PC&RC match interrupt request of QPRC ch.1" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " [8] ,PC match interrupt request of QPRC ch.1" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 7. " QUD0INT[7] ,PC match & RC match interrupt request of QPRC ch.0" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " [6] ,Interrupt request detected RC out of range on QPRC ch.0" "Not requested,Requested"
|
|
bitfld.long 0x00 5. " [5] ,PC count invert interrupt request of QPRC ch.0" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " [4] ,Overflow/underflow/zero index interrupt request of QPRC ch.0" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " [3] ,PC&RC match interrupt request of QPRC ch.0" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,PC match interrupt request of QPRC ch.0" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TIMINT[1] , Dual timer TIMINT2 interrupt request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] , Dual timer TIMINT1 interrupt request" "Not requested,Requested"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "IRQ07MON,IRQ07 Batch Read Register"
|
|
bitfld.long 0x00 1. " MFSINT[1] ,Reception interrupt request of MFS channel 8" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Reception interrupt request of MFS channel 0" "Not requested,Requested"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "IRQ09MON,IRQ09 Batch Read Register"
|
|
bitfld.long 0x00 1. " MFSINT[1] ,Reception interrupt request of MFS channel 9" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Reception interrupt request of MFS channel 1" "Not requested,Requested"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "IRQ11MON,IRQ11 Batch Read Register"
|
|
bitfld.long 0x00 1. " MFSINT[1] ,Reception interrupt request of MFS channel 10" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Reception interrupt request of MFS channel 2" "Not requested,Requested"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "IRQ13MON,IRQ13 Batch Read Register"
|
|
bitfld.long 0x00 1. " MFSINT[1] ,Reception interrupt request of MFS channel 11" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Reception interrupt request of MFS channel 3" "Not requested,Requested"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "IRQ15MON,IRQ15 Batch Read Register"
|
|
bitfld.long 0x00 1. " MFSINT[1] ,Reception interrupt request of MFS channel 12" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Reception interrupt request of MFS channel 4" "Not requested,Requested"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "IRQ17MON,IRQ17 Batch Read Register"
|
|
bitfld.long 0x00 1. " MFSINT[1] ,Reception interrupt request of MFS channel 13" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Reception interrupt request of MFS channel 5" "Not requested,Requested"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "IRQ19MON,IRQ19 Batch Read Register"
|
|
bitfld.long 0x00 4. " DMAINT ,Interrupt request of DMAC ch.0" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MFSINT[1] ,Reception interrupt request of MFS channel 14" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Reception interrupt request of MFS channel 6" "Not requested,Requested"
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "IRQ21MON,IRQ21 Batch Read Register"
|
|
bitfld.long 0x00 4. " DMAINT ,Interrupt request of DMAC ch.2" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MFSINT[1] ,Reception interrupt request of MFS channel 15" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Reception interrupt request of MFS channel 7" "Not requested,Requested"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "IRQ08MON,IRQ08 Batch Read Register"
|
|
bitfld.long 0x00 3. " MFSINT[3] ,Status interrupt request of MFS channel 8" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,Transmission interrupt request of MFS channel 8" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Status interrupt request of MFS channel 0" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Transmission interrupt request of MFS channel 0" "Not requested,Requested"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "IRQ10MON,IRQ10 Batch Read Register"
|
|
bitfld.long 0x00 3. " MFSINT[3] ,Status interrupt request of MFS channel 9" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,Transmission interrupt request of MFS channel 9" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Status interrupt request of MFS channel 1" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Transmission interrupt request of MFS channel 1" "Not requested,Requested"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "IRQ12MON,IRQ12 Batch Read Register"
|
|
bitfld.long 0x00 3. " MFSINT[3] ,Status interrupt request of MFS channel 10" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,Transmission interrupt request of MFS channel 10" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Status interrupt request of MFS channel 2" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Transmission interrupt request of MFS channel 2" "Not requested,Requested"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "IRQ14MON,IRQ14 Batch Read Register"
|
|
bitfld.long 0x00 3. " MFSINT[3] ,Status interrupt request of MFS channel 11" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,Transmission interrupt request of MFS channel 11" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Status interrupt request of MFS channel 3" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Transmission interrupt request of MFS channel 3" "Not requested,Requested"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "IRQ16MON,IRQ16 Batch Read Register"
|
|
bitfld.long 0x00 3. " MFSINT[3] ,Status interrupt request of MFS channel 12" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,Transmission interrupt request of MFS channel 12" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Status interrupt request of MFS channel 4" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Transmission interrupt request of MFS channel 4" "Not requested,Requested"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "IRQ18MON,IRQ18 Batch Read Register"
|
|
bitfld.long 0x00 3. " MFSINT[3] ,Status interrupt request of MFS channel 13" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,Transmission interrupt request of MFS channel 13" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Status interrupt request of MFS channel 5" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Transmission interrupt request of MFS channel 5" "Not requested,Requested"
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "IRQ20MON,IRQ20 Batch Read Register"
|
|
bitfld.long 0x00 4. " DMAINT ,Interrupt request of DMAC ch.1" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MFSINT[3] ,Status interrupt request of MFS channel 14" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,Transmission interrupt request of MFS channel 14" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Status interrupt request of MFS channel 6" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Transmission interrupt request of MFS channel 6" "Not requested,Requested"
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "IRQ22MON,IRQ22 Batch Read Register"
|
|
bitfld.long 0x00 4. " DMAINT ,Interrupt request of DMAC ch.3" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MFSINT[3] ,Status interrupt request of MFS channel 15" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,Transmission interrupt request of MFS channel 15" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Status interrupt request of MFS channel 7" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Transmission interrupt request of MFS channel 7" "Not requested,Requested"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "IRQ23MON,IRQ23 Batch Read Register"
|
|
bitfld.long 0x00 8. " PPGINT[8] ,Interrupt request of PPG ch.20" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " [7] ,Interrupt request of PPG ch.18" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " [6] ,Interrupt request of PPG ch.16" "Not requested,Requested"
|
|
bitfld.long 0x00 5. " [5] ,Interrupt request of PPG ch.12" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " [4] ,Interrupt request of PPG ch.10" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " [3] ,Interrupt request of PPG ch.8" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,Interrupt request of PPG ch.4" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Interrupt request of PPG ch.2" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Interrupt request of PPG ch.0" "Not requested,Requested"
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "IRQ24MON,IRQ24 Batch Read Register"
|
|
bitfld.long 0x00 5. " RTCINT ,RTC interrupt request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WCINT ,Watch counter interrupt request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MPLLINT ,Stabilization wait completion interrupt request for main PLL oscillation" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOSCINT ,Stabilization wait completion interrupt request for sub-clock oscillation" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MOSCINT ,Stabilization wait completion interrupt request for main clock oscillation" "Not requested,Requested"
|
|
rgroup.long 0x78++0x03
|
|
line.long 0x00 "IRQ25MON,IRQ25 Batch Read Register"
|
|
bitfld.long 0x00 4. " ADCINT[4] ,Range comparison result interrupt request in A/D converter unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " [3] ,Conversion result comparison interrupt request in A/D converter unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,FIFO overrun interrupt request in A/D converter unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Scan conversion interrupt request in A/D converter unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Priority conversion interrupt request in A/D converter unit 0" "Not requested,Requested"
|
|
rgroup.long 0x7C++0x03
|
|
line.long 0x00 "IRQ26MON,IRQ26 Batch Read Register"
|
|
bitfld.long 0x00 4. " ADCINT[4] ,Range comparison result interrupt request in A/D converter unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " [3] ,Conversion result comparison interrupt request in A/D converter unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,FIFO overrun interrupt request in A/D converter unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Scan conversion interrupt request in A/D converter unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Priority conversion interrupt request in A/D converter unit 1" "Not requested,Requested"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "IRQ27MON,IRQ27 Batch Read Register"
|
|
bitfld.long 0x00 5. " LCDCINT ,Interrupt request for LCD controller" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ADCINT[4] ,Range comparison result interrupt request in A/D converter unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " [3] ,Conversion result comparison interrupt request in A/D converter unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,FIFO overrun interrupt request in A/D converter unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Scan conversion interrupt request in A/D converter unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Priority conversion interrupt request in A/D converter unit 2" "Not requested,Requested"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "IRQ28MON,IRQ28 Batch Read Register"
|
|
bitfld.long 0x00 17. " FRT2INT[17] ,Zero detection interrupt request of the free run timer ch.2 in the MFT unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 16. " [16] ,Zero detection interrupt request of the free run timer ch.1 in the MFT unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 15. " [15] ,Zero detection interrupt request of the free run timer ch.0 in the MFT unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 14. " [14] ,Peak value detection interrupt request of the free run timer ch.2 in the MFT unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 13. " [13] ,Peak value detection interrupt request of the free run timer ch.1 in the MFT unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 12. " [12] ,Peak value detection interrupt request of the free run timer ch.0 in the MFT unit 2" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FRT1INT[11] ,Zero detection interrupt request of the free run timer ch.2 in the MFT unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 10. " [10] ,Zero detection interrupt request of the free run timer ch.1 in the MFT unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 9. " [9] ,Zero detection interrupt request of the free run timer ch.0 in the MFT unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " [8] ,Peak value detection interrupt request of the free run timer ch.2 in the MFT unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " [7] ,Peak value detection interrupt request of the free run timer ch.1 in the MFT unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " [6] ,Peak value detection interrupt request of the free run timer ch.0 in the MFT unit 1" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FRT0INT[5] ,Zero detection interrupt request of the free run timer ch.2 in the MFT unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " [4] ,Zero detection interrupt request of the free run timer ch.1 in the MFT unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " [3] ,Zero detection interrupt request of the free run timer ch.0 in the MFT unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,Peak value detection interrupt request of the free run timer ch.2 in the MFT unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Peak value detection interrupt request of the free run timer ch.1 in the MFT unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Peak value detection interrupt request of the free run timer ch.0 in the MFT unit 0" "Not requested,Requested"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "IRQ29MON,IRQ29 Batch Read Register"
|
|
bitfld.long 0x00 11. " ICU2INT[11] ,Interrupt request of the input capture ch.3 in the MFT unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 10. " [10] ,Interrupt request of the input capture ch.2 in the MFT unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 9. " [9] ,Interrupt request of the input capture ch.1 in the MFT unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " [8] ,Interrupt request of the input capture ch.0 in the MFT unit 2" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICU1INT[7] ,Interrupt request of the input capture ch.3 in the MFT unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " [6] ,Interrupt request of the input capture ch.2 in the MFT unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 5. " [5] ,Interrupt request of the input capture ch.1 in the MFT unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " [4] ,Interrupt request of the input capture ch.0 in the MFT unit 1" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ICU0INT[3] ,Interrupt request of the input capture ch.3 in the MFT unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,Interrupt request of the input capture ch.2 in the MFT unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Interrupt request of the input capture ch.1 in the MFT unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Interrupt request of the input capture ch.0 in the MFT unit 0" "Not requested,Requested"
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "IRQ30MON,IRQ30 Batch Read Register"
|
|
bitfld.long 0x00 17. " OCU2INT[17] ,Interrupt request of the output compare ch.5 in the MFT unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 16. " [16] ,Interrupt request of the output compare ch.4 in the MFT unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 15. " [15] ,Interrupt request of the output compare ch.3 in the MFT unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 14. " [14] ,Interrupt request of the output compare ch.2 in the MFT unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 13. " [13] ,Interrupt request of the output compare ch.1 in the MFT unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 12. " [12] ,Interrupt request of the output compare ch.0 in the MFT unit 2" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OCU1INT[11] ,Interrupt request of the output compare ch.5 in the MFT unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 10. " [10] ,Interrupt request of the output compare ch.4 in the MFT unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 9. " [9] ,Interrupt request of the output compare ch.3 in the MFT unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " [8] ,Interrupt request of the output compare ch.2 in the MFT unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " [7] ,Interrupt request of the output compare ch.1 in the MFT unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " [6] ,Interrupt request of the output compare ch.0 in the MFT unit 1" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OCU0INT[5] ,Interrupt request of the output compare ch.5 in the MFT unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " [4] ,Interrupt request of the output compare ch.4 in the MFT unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " [3] ,Interrupt request of the output compare ch.3 in the MFT unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,Interrupt request of the output compare ch.2 in the MFT unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Interrupt request of the output compare ch.1 in the MFT unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Interrupt request of the output compare ch.0 in the MFT unit 0" "Not requested,Requested"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "IRQ31MON,IRQ31 Batch Read Register"
|
|
bitfld.long 0x00 27. " FLASHINT ,RDY,HANG interrupt request for flash memory" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BTINT[15] ,IRQ1 interrupt request on the base timer ch.7" "Not requested,Requested"
|
|
bitfld.long 0x00 14. " [14] ,IRQ0 interrupt request on the base timer ch.7" "Not requested,Requested"
|
|
bitfld.long 0x00 13. " [13] ,IRQ1 interrupt request on the base timer ch.6" "Not requested,Requested"
|
|
bitfld.long 0x00 12. " [12] ,IRQ0 interrupt request on the base timer ch.6" "Not requested,Requested"
|
|
bitfld.long 0x00 11. " [11] ,IRQ1 interrupt request on the base timer ch.5" "Not requested,Requested"
|
|
bitfld.long 0x00 10. " [10] ,IRQ0 interrupt request on the base timer ch.5" "Not requested,Requested"
|
|
bitfld.long 0x00 9. " [9] ,IRQ1 interrupt request on the base timer ch.4" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,IRQ0 interrupt request on the base timer ch.4" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " [7] ,IRQ1 interrupt request on the base timer ch.3" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " [6] ,IRQ0 interrupt request on the base timer ch.3" "Not requested,Requested"
|
|
bitfld.long 0x00 5. " [5] ,IRQ1 interrupt request on the base timer ch.2" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " [4] ,IRQ0 interrupt request on the base timer ch.2" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " [3] ,IRQ1 interrupt request on the base timer ch.1" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,IRQ0 interrupt request on the base timer ch.1" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,IRQ1 interrupt request on the base timer ch.0 " "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,IRQ0 interrupt request on the base timer ch.0 " "Not requested,Requested"
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "IRQCMODE,Interrupt Factor Vector Relocate Setting Register"
|
|
bitfld.byte 0x00 0. " IRQCMODE ,Interrupt factor vector select" "Interrupts (A),Interrupts (B)"
|
|
width 0xB
|
|
else
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DRQSEL,DMA Request Selection Register"
|
|
bitfld.long 0x00 31. " DRQSEL[31] ,The interrupt signal of the external interrupt ch.3" "CPU,DMAC"
|
|
bitfld.long 0x00 30. " [30] ,The interrupt signal of the external interrupt ch.2" "CPU,DMAC"
|
|
bitfld.long 0x00 29. " [29] ,The interrupt signal of the external interrupt ch.1" "CPU,DMAC"
|
|
bitfld.long 0x00 28. " [28] ,The interrupt signal of the external interrupt ch.0" "CPU,DMAC"
|
|
bitfld.long 0x00 27. " [27] ,The transmission interrupt signal of the MFS ch.7" "CPU,DMAC"
|
|
bitfld.long 0x00 26. " [26] ,The reception interrupt signal of the MFS ch.7" "CPU,DMAC"
|
|
bitfld.long 0x00 25. " [25] ,The transmission interrupt signal of the MFS ch.6" "CPU,DMAC"
|
|
textline " "
|
|
bitfld.long 0x00 24. " [24] ,The reception interrupt signal of the MFS ch.6" "CPU,DMAC"
|
|
bitfld.long 0x00 23. " [23] ,The transmission interrupt signal of the MFS ch.5" "CPU,DMAC"
|
|
bitfld.long 0x00 22. " [22] ,The reception interrupt signal of the MFS ch.5" "CPU,DMAC"
|
|
bitfld.long 0x00 21. " [21] ,The transmission interrupt signal of the MFS ch.4" "CPU,DMAC"
|
|
bitfld.long 0x00 20. " [20] ,The reception interrupt signal of the MFS ch.4" "CPU,DMAC"
|
|
bitfld.long 0x00 19. " [19] ,The transmission interrupt signal of the MFS ch.3" "CPU,DMAC"
|
|
bitfld.long 0x00 18. " [18] ,The reception interrupt signal of the MFS ch.3" "CPU,DMAC"
|
|
textline " "
|
|
bitfld.long 0x00 17. " [17] ,The transmission interrupt signal of the MFS ch.2" "CPU,DMAC"
|
|
bitfld.long 0x00 16. " [16] ,The reception interrupt signal of the MFS ch.2" "CPU,DMAC"
|
|
bitfld.long 0x00 15. " [15] ,The transmission interrupt signal of the MFS ch.1" "CPU,DMAC"
|
|
bitfld.long 0x00 14. " [14] ,The reception interrupt signal of the MFS ch.1" "CPU,DMAC"
|
|
bitfld.long 0x00 13. " [13] ,The transmission interrupt signal of the MFS ch.0" "CPU,DMAC"
|
|
bitfld.long 0x00 12. " [12] ,The reception interrupt signal of the MFS ch.0" "CPU,DMAC"
|
|
bitfld.long 0x00 11. " [11] ,The IRQ0 interrupt signal of the base timer ch.6" "CPU,DMAC"
|
|
textline " "
|
|
bitfld.long 0x00 10. " [10] ,The IRQ0 interrupt signal of the base timer ch.4" "CPU,DMAC"
|
|
bitfld.long 0x00 9. " [9] ,The IRQ0 interrupt signal of the base timer ch.2" "CPU,DMAC"
|
|
bitfld.long 0x00 8. " [8] ,The IRQ0 interrupt signal of the base timer ch.0" "CPU,DMAC"
|
|
bitfld.long 0x00 7. " [7] ,The scan conversion interrupt signal of the A/D converter unit 2" "CPU,DMAC"
|
|
bitfld.long 0x00 6. " [6] ,The scan conversion interrupt signal of the A/D converter unit 1" "CPU,DMAC"
|
|
bitfld.long 0x00 5. " [5] ,The scan conversion interrupt signal of the A/D converter unit 0" "CPU,DMAC"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "EXC02MON,EXC02 Batch Read Register"
|
|
bitfld.long 0x00 1. " HWINT ,Hardware watchdog timer interrupt request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " NMI ,NMIX external pin interrupt request" "Not requested,Requested"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "IRQ00MON,IRQ00 Batch Read Register"
|
|
bitfld.long 0x00 0. " FCSINT ,Anomalous frequency detection by CSV interrupt request" "Not requested,Requested"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "IRQ01MON,IRQ01 Batch Read Register"
|
|
bitfld.long 0x00 0. " SWWDTINT ,Software watchdog timer interrupt request" "Not requested,Requested"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "IRQ02MON,IRQ02 Batch Read Register"
|
|
bitfld.long 0x00 0. " LVDINT ,Low voltage detection (LVD) interrupt request" "Not requested,Requested"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "IRQ03MON,IRQ03 Batch Read Register"
|
|
bitfld.long 0x00 0. " RCINT ,Interrupt request selected in the INTSEL0 bits in the RCINTSEL0 Register" "Not requested,Requested"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "IRQ04MON,IRQ04 Batch Read Register"
|
|
bitfld.long 0x00 0. " RCINT ,Interrupt request selected in the INTSEL1 bits in the RCINTSEL0 Register" "Not requested,Requested"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "IRQ05MON,IRQ05 Batch Read Register"
|
|
bitfld.long 0x00 0. " RCINT ,Interrupt request selected in the INTSEL2 bits in the RCINTSEL0 Register" "Not requested,Requested"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "IRQ06MON,IRQ06 Batch Read Register"
|
|
bitfld.long 0x00 0. " RCINT ,Interrupt request selected in the INTSEL3 bits in the RCINTSEL0 Register" "Not requested,Requested"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "IRQ07MON,IRQ07 Batch Read Register"
|
|
bitfld.long 0x00 0. " RCINT ,Interrupt request selected in the INTSEL0 bits in the RCINTSEL1 Register" "Not requested,Requested"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "IRQ08MON,IRQ08 Batch Read Register"
|
|
bitfld.long 0x00 0. " RCINT ,Interrupt request selected in the INTSEL1 bits in the RCINTSEL1 Register" "Not requested,Requested"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "IRQ09MON,IRQ09 Batch Read Register"
|
|
bitfld.long 0x00 0. " RCINT ,Interrupt request selected in the INTSEL2 bits in the RCINTSEL1 Register" "Not requested,Requested"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "IRQ10MON,IRQ10 Batch Read Register"
|
|
bitfld.long 0x00 0. " RCINT ,Interrupt request selected in the INTSEL3 bits in the RCINTSEL1 Register" "Not requested,Requested"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "IRQ11MON,IRQ11 Batch Read Register"
|
|
bitfld.long 0x00 6. " MFSINT[6] ,Status interrupt request of MFS channel 8" "Not requested,Requested"
|
|
bitfld.long 0x00 5. " [5] ,Transmission interrupt request of MFS channel 8" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " [4] ,Reception interrupt request of MFS channel 8" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 3. " WAVEINT[3] ,Interrupt request of WFG timer 54 in the MFT unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,Interrupt request of WFG timer 32 in the MFT unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Interrupt request of WFG timer 10 in the MFT unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Interrupt request of DTIF (Motor emergency stop) in the MFT unit 0" "Not requested,Requested"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "IRQ12MON,IRQ12 Batch Read Register"
|
|
bitfld.long 0x00 7. " EXTINT[7] ,Interrupt request of external interrupt ch.7" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " [6] ,Interrupt request of external interrupt ch.6" "Not requested,Requested"
|
|
bitfld.long 0x00 5. " [5] ,Interrupt request of external interrupt ch.5" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " [4] ,Interrupt request of external interrupt ch.4" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " [3] ,Interrupt request of external interrupt ch.3" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,Interrupt request of external interrupt ch.2" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Interrupt request of external interrupt ch.1" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Interrupt request of external interrupt ch.0" "Not requested,Requested"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "IRQ13MON,IRQ13 Batch Read Register"
|
|
bitfld.long 0x00 23. " EXTINT[23] ,Interrupt request of external interrupt ch.31" "Not requested,Requested"
|
|
bitfld.long 0x00 22. " [22] ,Interrupt request of external interrupt ch.30" "Not requested,Requested"
|
|
bitfld.long 0x00 21. " [21] ,Interrupt request of external interrupt ch.29" "Not requested,Requested"
|
|
bitfld.long 0x00 20. " [20] ,Interrupt request of external interrupt ch.28" "Not requested,Requested"
|
|
bitfld.long 0x00 19. " [19] ,Interrupt request of external interrupt ch.27" "Not requested,Requested"
|
|
bitfld.long 0x00 18. " [18] ,Interrupt request of external interrupt ch.26" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " [17] ,Interrupt request of external interrupt ch.25" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Interrupt request of external interrupt ch.24" "Not requested,Requested"
|
|
bitfld.long 0x00 15. " [15] ,Interrupt request of external interrupt ch.23" "Not requested,Requested"
|
|
bitfld.long 0x00 14. " [14] ,Interrupt request of external interrupt ch.22" "Not requested,Requested"
|
|
bitfld.long 0x00 13. " [13] ,Interrupt request of external interrupt ch.21" "Not requested,Requested"
|
|
bitfld.long 0x00 12. " [12] ,Interrupt request of external interrupt ch.20" "Not requested,Requested"
|
|
bitfld.long 0x00 11. " [11] ,Interrupt request of external interrupt ch.19" "Not requested,Requested"
|
|
bitfld.long 0x00 10. " [10] ,Interrupt request of external interrupt ch.18" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 9. " [9] ,Interrupt request of external interrupt ch.17" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " [8] ,Interrupt request of external interrupt ch.16" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " [7] ,Interrupt request of external interrupt ch.15" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " [6] ,Interrupt request of external interrupt ch.14" "Not requested,Requested"
|
|
bitfld.long 0x00 5. " [5] ,Interrupt request of external interrupt ch.13" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " [4] ,Interrupt request of external interrupt ch.12" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " [3] ,Interrupt request of external interrupt ch.11" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 2. " [2] ,Interrupt request of external interrupt ch.10" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Interrupt request of external interrupt ch.9" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Interrupt request of external interrupt ch.8" "Not requested,Requested"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "IRQ14MON,IRQ14 Batch Read Register"
|
|
bitfld.long 0x00 7. " QUDINT[7] ,PC match & RC match interrupt request of QPRC ch.0" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " [6] ,Interrupt request detected RC out of range on QPRC ch.0" "Not requested,Requested"
|
|
bitfld.long 0x00 5. " [5] ,PC count invert interrupt request of QPRC ch.0" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " [4] ,Overflow/underflow/zero index interrupt request of QPRC ch.0" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " [3] ,PC&RC match interrupt request of QPRC ch.0" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,PC match interrupt request of QPRC ch.0" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TIMINT[1] ,Dual timer TIMINT2 interrupt request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Dual timer TIMINT1 interrupt request" "Not requested,Requested"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "IRQ15MON,IRQ15 Batch Read Register"
|
|
bitfld.long 0x00 2. " MFSINT[2] ,Status interrupt request of MFS channel 0" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Transmission interrupt request of MFS channel 0" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Reception interrupt request of MFS channel 0" "Not requested,Requested"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "IRQ16MON,IRQ16 Batch Read Register"
|
|
bitfld.long 0x00 2. " MFSINT[2] ,Status interrupt request of MFS channel 1" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Transmission interrupt request of MFS channel 1" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Reception interrupt request of MFS channel 1" "Not requested,Requested"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "IRQ17MON,IRQ17 Batch Read Register"
|
|
bitfld.long 0x00 2. " MFSINT[2] ,Status interrupt request of MFS channel 2" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Transmission interrupt request of MFS channel 2" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Reception interrupt request of MFS channel 2" "Not requested,Requested"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "IRQ18MON,IRQ18 Batch Read Register"
|
|
bitfld.long 0x00 2. " MFSINT[2] ,Status interrupt request of MFS channel 3" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Transmission interrupt request of MFS channel 3" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Reception interrupt request of MFS channel 3" "Not requested,Requested"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "IRQ19MON,IRQ19 Batch Read Register"
|
|
bitfld.long 0x00 0. " MFSINT ,Reception interrupt request of MFS channel 4" "Not requested,Requested"
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "IRQ21MON,IRQ21 Batch Read Register"
|
|
bitfld.long 0x00 0. " MFSINT ,Reception interrupt request of MFS channel 5" "Not requested,Requested"
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "IRQ20MON,IRQ20 Batch Read Register"
|
|
bitfld.long 0x00 1. " MFSINT[1] ,Status interrupt request of MFS channel 4" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Transmission interrupt request of MFS channel 4" "Not requested,Requested"
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "IRQ22MON,IRQ22 Batch Read Register"
|
|
bitfld.long 0x00 1. " MFSINT[1] ,Status interrupt request of MFS channel 5" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Transmission interrupt request of MFS channel 5" "Not requested,Requested"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "IRQ23MON,IRQ23 Batch Read Register"
|
|
bitfld.long 0x00 8. " PPGINT[8] ,Interrupt request of PPG ch.20" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " [7] ,Interrupt request of PPG ch.18" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " [6] ,Interrupt request of PPG ch.16" "Not requested,Requested"
|
|
bitfld.long 0x00 5. " [5] ,Interrupt request of PPG ch.12" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " [4] ,Interrupt request of PPG ch.10" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " [3] ,Interrupt request of PPG ch.8" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,Interrupt request of PPG ch.4" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Interrupt request of PPG ch.2" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Interrupt request of PPG ch.0" "Not requested,Requested"
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "IRQ24MON,IRQ24 Batch Read Register"
|
|
bitfld.long 0x00 5. " RTCINT ,RTC interrupt request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WCINT ,Watch counter interrupt request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MPLLINT ,Stabilization wait completion interrupt request for main PLL oscillation" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOSCINT ,Stabilization wait completion interrupt request for sub-clock oscillation" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MOSCINT ,Stabilization wait completion interrupt request for main clock oscillation" "Not requested,Requested"
|
|
rgroup.long 0x78++0x03
|
|
line.long 0x00 "IRQ25MON,IRQ25 Batch Read Register"
|
|
bitfld.long 0x00 7. " MFSINT[7] ,Status interrupt request of MFS channel 9" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " [6] ,Transmission interrupt request of MFS channel 9" "Not requested,Requested"
|
|
bitfld.long 0x00 5. " [5] ,Reception interrupt request of MFS channel 9" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ADCINT[4] ,Range comparison result interrupt request in A/D converter unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " [3] ,Conversion result comparison interrupt request in A/D converter unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,FIFO overrun interrupt request in A/D converter unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Scan conversion interrupt request in A/D converter unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Priority conversion interrupt request in A/D converter unit 0" "Not requested,Requested"
|
|
rgroup.long 0x7C++0x03
|
|
line.long 0x00 "IRQ26MON,IRQ26 Batch Read Register"
|
|
bitfld.long 0x00 7. " MFSINT[7] ,Status interrupt request of MFS channel 10" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " [6] ,Transmission interrupt request of MFS channel 10" "Not requested,Requested"
|
|
bitfld.long 0x00 5. " [5] ,Reception interrupt request of MFS channel 10" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ADCINT[4] ,Range comparison result interrupt request in A/D converter unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " [3] ,Conversion result comparison interrupt request in A/D converter unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,FIFO overrun interrupt request in A/D converter unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Scan conversion interrupt request in A/D converter unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Priority conversion interrupt request in A/D converter unit 1" "Not requested,Requested"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "IRQ27MON,IRQ27 Batch Read Register"
|
|
bitfld.long 0x00 8. " MFSINT[8] ,Status interrupt request of MFS channel 11" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " [7] ,Transmission interrupt request of MFS channel 11" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " [6] ,Reception interrupt request of MFS channel 11" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 5. " LCDCINT ,Interrupt request for LCD controller" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ADCINT[4] ,Range comparison result interrupt request in A/D converter unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " [3] ,Conversion result comparison interrupt request in A/D converter unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,FIFO overrun interrupt request in A/D converter unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Scan conversion interrupt request in A/D converter unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Priority conversion interrupt request in A/D converter unit 2" "Not requested,Requested"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "IRQ28MON,IRQ28 Batch Read Register"
|
|
bitfld.long 0x00 15. " OCUINT[15] ,Interrupt request of the output compare ch.5 in the MFT unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 14. " [14] ,Interrupt request of the output compare ch.4 in the MFT unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 13. " [13] ,Interrupt request of the output compare ch.3 in the MFT unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 12. " [12] ,Interrupt request of the output compare ch.2 in the MFT unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 11. " [11] ,Interrupt request of the output compare ch.1 in the MFT unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 10. " [10] ,Interrupt request of the output compare ch.0 in the MFT unit 0" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ICUINT[9] ,Interrupt request of the input capture ch.3 in the MFT unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " [8] ,Interrupt request of the input capture ch.2 in the MFT unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " [7] ,Interrupt request of the input capture ch.1 in the MFT unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " [6] ,Interrupt request of the input capture ch.0 in the MFT unit 0" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FRTINT[5] ,Zero detection interrupt request of the free run timer ch.2 in the MFT unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " [4] ,Zero detection interrupt request of the free run timer ch.1 in the MFT unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " [3] ,Zero detection interrupt request of the free run timer ch.0 in the MFT unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,Peak value detection interrupt request of the free run timer ch.2 in the MFT unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Peak value detection interrupt request of the free run timer ch.1 in the MFT unit 0" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Peak value detection interrupt request of the free run timer ch.0 in the MFT unit 0" "Not requested,Requested"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "IRQ29MON,IRQ29 Batch Read Register"
|
|
bitfld.long 0x00 15. " OCUINT[15] ,Interrupt request of the output compare ch.5 in the MFT unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 14. " [14] ,Interrupt request of the output compare ch.4 in the MFT unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 13. " [13] ,Interrupt request of the output compare ch.3 in the MFT unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 12. " [12] ,Interrupt request of the output compare ch.2 in the MFT unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 11. " [11] ,Interrupt request of the output compare ch.1 in the MFT unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 10. " [10] ,Interrupt request of the output compare ch.0 in the MFT unit 1" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ICUINT[9] ,Interrupt request of the input capture ch.3 in the MFT unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " [8] ,Interrupt request of the input capture ch.2 in the MFT unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " [7] ,Interrupt request of the input capture ch.1 in the MFT unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " [6] ,Interrupt request of the input capture ch.0 in the MFT unit 1" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FRTINT[5] ,Zero detection interrupt request of the free run timer ch.2 in the MFT unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " [4] ,Zero detection interrupt request of the free run timer ch.1 in the MFT unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " [3] ,Zero detection interrupt request of the free run timer ch.0 in the MFT unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,Peak value detection interrupt request of the free run timer ch.2 in the MFT unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Peak value detection interrupt request of the free run timer ch.1 in the MFT unit 1" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Peak value detection interrupt request of the free run timer ch.0 in the MFT unit 1" "Not requested,Requested"
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "IRQ30MON,IRQ30 Batch Read Register"
|
|
bitfld.long 0x00 23. " DMAINT[23] ,Interrupt request of DMA controller ch.7" "Not requested,Requested"
|
|
bitfld.long 0x00 22. " [22] ,Interrupt request of DMA controller ch.6" "Not requested,Requested"
|
|
bitfld.long 0x00 21. " [21] ,Interrupt request of DMA controller ch.5" "Not requested,Requested"
|
|
bitfld.long 0x00 20. " [20] ,Interrupt request of DMA controller ch.4" "Not requested,Requested"
|
|
bitfld.long 0x00 19. " [19] ,Interrupt request of DMA controller ch.3" "Not requested,Requested"
|
|
bitfld.long 0x00 18. " [18] ,Interrupt request of DMA controller ch.2" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " [17] ,Interrupt request of DMA controller ch.1" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Interrupt request of DMA controller ch.0" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 15. " OCUINT[15] ,Interrupt request of the output compare ch.5 in the unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 14. " [14] ,Interrupt request of the output compare ch.4 in the MFT unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 13. " [13] ,Interrupt request of the output compare ch.3 in the MFT unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 12. " [12] ,Interrupt request of the output compare ch.2 in the MFT unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 11. " [11] ,Interrupt request of the output compare ch.1 in the MFT unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 10. " [10] ,Interrupt request of the output compare ch.0 in the MFT unit 2" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ICUINT[9] ,Interrupt request of the input capture ch.3 in the MFT unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " [8] ,Interrupt request of the input capture ch.2 in the MFT unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " [7] ,Interrupt request of the input capture ch.1 in the MFT unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " [6] ,Interrupt request of the input capture ch.0 in the MFT unit 2" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FRTINT[5] ,Zero detection interrupt request of the free run timer ch.2 in the MFT unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " [4] ,Zero detection interrupt request of the free run timer ch.1 in the MFT unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " [3] ,Zero detection interrupt request of the free run timer ch.0 in the MFT unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,Peak value detection interrupt request of the free run timer ch.2 in the MFT unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Peak value detection interrupt request of the free run timer ch.1 in the MFT unit 2" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Peak value detection interrupt request of the free run timer ch.0. in the MFT unit 2" "Not requested,Requested"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "IRQ31MON,IRQ31 Batch Read Register"
|
|
bitfld.long 0x00 27. " FLASHINT ,RDY,HANG interrupt request for flash memory" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BTINT[15] ,IRQ1 interrupt request on the base timer ch.7" "Not requested,Requested"
|
|
bitfld.long 0x00 14. " [14] ,IRQ0 interrupt request on the base timer ch.7" "Not requested,Requested"
|
|
bitfld.long 0x00 13. " [13] ,IRQ1 interrupt request on the base timer ch.6" "Not requested,Requested"
|
|
bitfld.long 0x00 12. " [12] ,IRQ0 interrupt request on the base timer ch.6" "Not requested,Requested"
|
|
bitfld.long 0x00 11. " [11] ,IRQ1 interrupt request on the base timer ch.5" "Not requested,Requested"
|
|
bitfld.long 0x00 10. " [10] ,IRQ0 interrupt request on the base timer ch.5" "Not requested,Requested"
|
|
bitfld.long 0x00 9. " [9] ,IRQ1 interrupt request on the base timer ch.4" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 8. " [8] ,IRQ0 interrupt request on the base timer ch.4" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " [7] ,IRQ1 interrupt request on the base timer ch.3" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " [6] ,IRQ0 interrupt request on the base timer ch.3" "Not requested,Requested"
|
|
bitfld.long 0x00 5. " [5] ,IRQ1 interrupt request on the base timer ch.2" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " [4] ,IRQ0 interrupt request on the base timer ch.2" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " [3] ,IRQ1 interrupt request on the base timer ch.1" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,IRQ0 interrupt request on the base timer ch.1" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,IRQ1 interrupt request on the base timer ch.0 " "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,IRQ0 interrupt request on the base timer ch.0 " "Not requested,Requested"
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "IRQCMODE,Interrupt Factor Vector Relocate Setting Register"
|
|
bitfld.byte 0x00 0. " IRQCMODE ,Interrupt factor vector select" "Interrupts (A),Interrupts (B)"
|
|
width 0xB
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree "External Interrupts and NMI Control"
|
|
base ad:0x40030000
|
|
width 15.
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ENIR_SET/CLR,External Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. -0x04 31. 0x04 31. " EN[31] ,INT31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x04 30. 0x04 30. " [30] ,INT30 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x04 29. 0x04 29. " [29] ,INT29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x04 28. 0x04 28. " [28] ,INT28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x04 27. 0x04 27. " [27] ,INT27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x04 26. 0x04 26. " [26] ,INT26 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x04 25. 0x04 25. " [25] ,INT25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x04 24. 0x04 24. " [24] ,INT24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x04 23. 0x04 23. " [23] ,INT23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x04 22. 0x04 22. " [22] ,INT22 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x04 21. 0x04 21. " [21] ,INT21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x04 20. 0x04 20. " [20] ,INT20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x04 19. 0x04 19. " [19] ,INT19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x04 18. 0x04 18. " [18] ,INT18 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x04 17. 0x04 17. " [17] ,INT17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x04 16. 0x04 16. " [16] ,INT16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x04 15. 0x04 15. " [15] ,INT15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x04 14. 0x04 14. " [14] ,INT14 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x04 13. 0x04 13. " [13] ,INT13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x04 12. 0x04 12. " [12] ,INT12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. 0x04 11. " [11] ,INT11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x04 10. 0x04 10. " [10] ,INT10 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x04 9. 0x04 9. " [9] ,INT9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x04 8. 0x04 8. " [8] ,INT8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. 0x04 7. " [7] ,INT7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x04 6. 0x04 6. " [6] ,INT6 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x04 5. 0x04 5. " [5] ,INT5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x04 4. 0x04 4. " [4] ,INT4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. 0x04 3. " [3] ,INT3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x04 2. 0x04 2. " [2] ,INT2 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x04 1. 0x04 1. " [1] ,INT1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x04 0. 0x04 0. " [0] ,INT0 enable" "Disabled,Enabled"
|
|
group.long 0x0C++0x7
|
|
line.long 0x00 "ELVR,External Interrupt Factor Level Register"
|
|
bitfld.long 0x00 30.--31. " LB_LA[15] ,INT15 request detection level selection" "L level,H level,Rising,Falling"
|
|
bitfld.long 0x00 28.--29. " [14] ,INT14 request detection level selection" "L level,H level,Rising,Falling"
|
|
bitfld.long 0x00 26.--27. " [13] ,INT13 request detection level selection" "L level,H level,Rising,Falling"
|
|
bitfld.long 0x00 24.--25. " [12] ,INT12 request detection level selection" "L level,H level,Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " [11] ,INT11 request detection level selection" "L level,H level,Rising,Falling"
|
|
bitfld.long 0x00 20.--21. " [10] ,INT10 request detection level selection" "L level,H level,Rising,Falling"
|
|
bitfld.long 0x00 18.--19. " [9] ,INT9 request detection level selection" "L level,H level,Rising,Falling"
|
|
bitfld.long 0x00 16.--17. " [8] ,INT8 request detection level selection" "L level,H level,Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " [7] ,INT7 request detection level selection" "L level,H level,Rising,Falling"
|
|
bitfld.long 0x00 12.--13. " [6] ,INT6 request detection level selection" "L level,H level,Rising,Falling"
|
|
bitfld.long 0x00 10.--11. " [5] ,INT5 request detection level selection" "L level,H level,Rising,Falling"
|
|
bitfld.long 0x00 8.--9. " [4] ,INT4 request detection level selection" "L level,H level,Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " [3] ,INT3 request detection level selection" "L level,H level,Rising,Falling"
|
|
bitfld.long 0x00 4.--5. " [2] ,INT2 request detection level selection" "L level,H level,Rising,Falling"
|
|
bitfld.long 0x00 2.--3. " [1] ,INT1 request detection level selection" "L level,H level,Rising,Falling"
|
|
bitfld.long 0x00 0.--1. " [0] ,INT0 request detection level selection" "L level,H level,Rising,Falling"
|
|
line.long 0x04 "ELVR1,External Interrupt Factor Level Register 1"
|
|
bitfld.long 0x04 30.--31. " LB_LA[31] ,INT31 request detection level selection" "L level,H level,Rising,Falling"
|
|
bitfld.long 0x04 28.--29. " [30] ,INT30 request detection level selection" "L level,H level,Rising,Falling"
|
|
bitfld.long 0x04 26.--27. " [29] ,INT29 request detection level selection" "L level,H level,Rising,Falling"
|
|
bitfld.long 0x04 24.--25. " [28] ,INT28 request detection level selection" "L level,H level,Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x04 22.--23. " [27] ,INT27 request detection level selection" "L level,H level,Rising,Falling"
|
|
bitfld.long 0x04 20.--21. " [26] ,INT26 request detection level selection" "L level,H level,Rising,Falling"
|
|
bitfld.long 0x04 18.--19. " [25] ,INT25 request detection level selection" "L level,H level,Rising,Falling"
|
|
bitfld.long 0x04 16.--17. " [24] ,INT24 request detection level selection" "L level,H level,Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " [23] ,INT23 request detection level selection" "L level,H level,Rising,Falling"
|
|
bitfld.long 0x04 12.--13. " [22] ,INT22 request detection level selection" "L level,H level,Rising,Falling"
|
|
bitfld.long 0x04 10.--11. " [21] ,INT21 request detection level selection" "L level,H level,Rising,Falling"
|
|
bitfld.long 0x04 8.--9. " [20] ,INT20 request detection level selection" "L level,H level,Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " [19] ,INT19 request detection level selection" "L level,H level,Rising,Falling"
|
|
bitfld.long 0x04 4.--5. " [18] ,INT18 request detection level selection" "L level,H level,Rising,Falling"
|
|
bitfld.long 0x04 2.--3. " [17] ,INT17 request detection level selection" "L level,H level,Rising,Falling"
|
|
bitfld.long 0x04 0.--1. " [16] ,INT16 request detection level selection" "L level,H level,Rising,Falling"
|
|
sif cpuis("S6E1C*")
|
|
textline " "
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "NMIRR,Non Maskable Interrupt Factor Register"
|
|
bitfld.word 0x00 0. " NR ,NMI interrupt request detection bit" "Not detected,Detected"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "NMICL,Non Maskable Interrupt Factor Clear Register"
|
|
bitfld.word 0x00 0. " NCL ,NMI interrupt factor clear bit" "Cleared,No effect"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ELVR2,External Interrupt Factor Level Register 2"
|
|
bitfld.long 0x00 31. " LC[31] ,INT31 external interrupt request detection level selection" "Edge/Selected with ELVR & ELVR,Both rising & falling edge"
|
|
bitfld.long 0x00 30. " [30] ,INT30 external interrupt request detection level selection" "Edge/Selected with ELVR & ELVR,Both rising & falling edge"
|
|
bitfld.long 0x00 29. " [29] ,INT29 external interrupt request detection level selection" "Edge/Selected with ELVR & ELVR,Both rising & falling edge"
|
|
bitfld.long 0x00 28. " [28] ,INT28 external interrupt request detection level selection" "Edge/Selected with ELVR & ELVR,Both rising & falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,INT27 external interrupt request detection level selection" "Edge/Selected with ELVR & ELVR,Both rising & falling edge"
|
|
bitfld.long 0x00 26. " [26] ,INT26 external interrupt request detection level selection" "Edge/Selected with ELVR & ELVR,Both rising & falling edge"
|
|
bitfld.long 0x00 25. " [25] ,INT25 external interrupt request detection level selection" "Edge/Selected with ELVR & ELVR,Both rising & falling edge"
|
|
bitfld.long 0x00 24. " [24] ,INT24 external interrupt request detection level selection" "Edge/Selected with ELVR & ELVR,Both rising & falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,INT23 external interrupt request detection level selection" "Edge/Selected with ELVR & ELVR,Both rising & falling edge"
|
|
bitfld.long 0x00 22. " [22] ,INT22 external interrupt request detection level selection" "Edge/Selected with ELVR & ELVR,Both rising & falling edge"
|
|
bitfld.long 0x00 21. " [21] ,INT21 external interrupt request detection level selection" "Edge/Selected with ELVR & ELVR,Both rising & falling edge"
|
|
bitfld.long 0x00 20. " [20] ,INT20 external interrupt request detection level selection" "Edge/Selected with ELVR & ELVR,Both rising & falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,INT19 external interrupt request detection level selection" "Edge/Selected with ELVR & ELVR,Both rising & falling edge"
|
|
bitfld.long 0x00 18. " [18] ,INT18 external interrupt request detection level selection" "Edge/Selected with ELVR & ELVR,Both rising & falling edge"
|
|
bitfld.long 0x00 17. " [17] ,INT17 external interrupt request detection level selection" "Edge/Selected with ELVR & ELVR,Both rising & falling edge"
|
|
bitfld.long 0x00 16. " [16] ,INT16 external interrupt request detection level selection" "Edge/Selected with ELVR & ELVR,Both rising & falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,INT15 external interrupt request detection level selection" "Edge/Selected with ELVR & ELVR,Both rising & falling edge"
|
|
bitfld.long 0x00 14. " [14] ,INT14 external interrupt request detection level selection" "Edge/Selected with ELVR & ELVR,Both rising & falling edge"
|
|
bitfld.long 0x00 13. " [13] ,INT13 external interrupt request detection level selection" "Edge/Selected with ELVR & ELVR,Both rising & falling edge"
|
|
bitfld.long 0x00 12. " [12] ,INT12 external interrupt request detection level selection" "Edge/Selected with ELVR & ELVR,Both rising & falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,INT11 external interrupt request detection level selection" "Edge/Selected with ELVR & ELVR,Both rising & falling edge"
|
|
bitfld.long 0x00 10. " [10] ,INT10 external interrupt request detection level selection" "Edge/Selected with ELVR & ELVR,Both rising & falling edge"
|
|
bitfld.long 0x00 9. " [9] ,INT9 external interrupt request detection level selection" "Edge/Selected with ELVR & ELVR,Both rising & falling edge"
|
|
bitfld.long 0x00 8. " [8] ,INT8 external interrupt request detection level selection" "Edge/Selected with ELVR & ELVR,Both rising & falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,INT7 external interrupt request detection level selection" "Edge/Selected with ELVR & ELVR,Both rising & falling edge"
|
|
bitfld.long 0x00 6. " [6] ,INT6 external interrupt request detection level selection" "Edge/Selected with ELVR & ELVR,Both rising & falling edge"
|
|
bitfld.long 0x00 5. " [5] ,INT5 external interrupt request detection level selection" "Edge/Selected with ELVR & ELVR,Both rising & falling edge"
|
|
bitfld.long 0x00 4. " [4] ,INT4 external interrupt request detection level selection" "Edge/Selected with ELVR & ELVR,Both rising & falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,INT3 external interrupt request detection level selection" "Edge/Selected with ELVR & ELVR,Both rising & falling edge"
|
|
bitfld.long 0x00 2. " [2] ,INT2 external interrupt request detection level selection" "Edge/Selected with ELVR & ELVR,Both rising & falling edge"
|
|
bitfld.long 0x00 1. " [1] ,INT1 external interrupt request detection level selection" "Edge/Selected with ELVR & ELVR,Both rising & falling edge"
|
|
bitfld.long 0x00 0. " [0] ,INT0 external interrupt request detection level selection" "Edge/Selected with ELVR & ELVR,Both rising & falling edge"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "NMIENR,Non Maskable Interrupt Enable Register"
|
|
bitfld.byte 0x00 0. " NE0 ,NMI enable bit" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "NMIRR,Non Maskable Interrupt Factor Register"
|
|
rbitfld.long 0x00 0. " NMIINT ,NMI interrupt request detection bit" "Not detected,Detected"
|
|
line.long 0x04 "NMICL,Non Maskable Interrupt Factor Clear Register"
|
|
bitfld.long 0x04 0. " NCL ,NMI interrupt factor clear bit" "Cleared,No effect"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
sif !cpuis("S6E1C*")
|
|
tree.open "DMAC (Direct Memory Access Controller)"
|
|
tree "Common Register"
|
|
base ad:0x40060000
|
|
width 7.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DMACR,Entire DMAC configuration register"
|
|
bitfld.long 0x00 31. " DE ,DMA Enable (all-channel operation enable bit)" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DS ,DMA Stop" "Not stopped,Stopped"
|
|
bitfld.long 0x00 28. " PR ,Priority Rotation" "Fixed,Rotation"
|
|
bitfld.long 0x00 24.--27. " DH ,DMA Halt" "Not halted,Halted,Halted,Halted,Halted,Halted,Halted,Halted,Halted,Halted,Halted,Halted,Halted,Halted,Halted,Halted"
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 0"
|
|
base ad:0x40060000
|
|
width 10.
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "DMACA_0,Configuration A Register 0"
|
|
bitfld.long 0x00 31. " EB ,Enable bit (individual-channel operation enable bit)" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit (individual-channel pause bit)" "Not paused,Paused"
|
|
bitfld.long 0x00 29. " ST ,Software Trigger" "No trigger,Trigger"
|
|
bitfld.long 0x00 23.--28. " IS ,Input Select" ",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,IDREQ[0],IDREQ[1],IDREQ[2],IDREQ[3],IDREQ[4],IDREQ[5],IDREQ[6],IDREQ[7],IDREQ[8],IDREQ[9],IDREQ[10],IDREQ[11],IDREQ[12],IDREQ[13],IDREQ[14],IDREQ[15],IDREQ[16],IDREQ[17],IDREQ[18],IDREQ[19],IDREQ[20],IDREQ[21],IDREQ[22],IDREQ[23],IDREQ[24],IDREQ[25],IDREQ[26],IDREQ[27],IDREQ[28],IDREQ[29],IDREQ[30],IDREQ[31]"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " BC ,Block Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer Count"
|
|
line.long 0x04 "DMACB_0,Configuration B Register 0"
|
|
bitfld.long 0x04 28.--29. " MS ,Mode Select" "Block,Burst,Demand,"
|
|
bitfld.long 0x04 26.--27. " TW ,Transfer Width" "8 bits,16 bits,32 bits,"
|
|
bitfld.long 0x04 25. " FS ,Fixed Source" "Incremented,Fixed"
|
|
bitfld.long 0x04 24. " FD ,Fixed Destination" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x04 23. " RC ,Reload Count (BC/TC reload)" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " RS ,Reload Source" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " RD ,Reload Destination" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " EI ,Error Interrupt (unsuccessful transfer completion interrupt enable)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " CI ,Completion Interrupt (successful transfer completion interrupt enable)" "Disabled,Enabled"
|
|
bitfld.long 0x04 16.--18. " SS ,Stop Status (stop status notification)" "Initial value,Address overflow,Stop request,Source error,Destination error,Completed,,Pause"
|
|
bitfld.long 0x04 0. " EM , Enable bit Mask (EB bit clear mask)" "Cleared,Not cleared"
|
|
line.long 0x08 "DMACSA_0,Transfer Source Address Register 0"
|
|
line.long 0x0C "DMACDA_0,Transfer Destination Address Register"
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0x40060010
|
|
width 10.
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "DMACA_1,Configuration A Register 1"
|
|
bitfld.long 0x00 31. " EB ,Enable bit (individual-channel operation enable bit)" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit (individual-channel pause bit)" "Not paused,Paused"
|
|
bitfld.long 0x00 29. " ST ,Software Trigger" "No trigger,Trigger"
|
|
bitfld.long 0x00 23.--28. " IS ,Input Select" ",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,IDREQ[0],IDREQ[1],IDREQ[2],IDREQ[3],IDREQ[4],IDREQ[5],IDREQ[6],IDREQ[7],IDREQ[8],IDREQ[9],IDREQ[10],IDREQ[11],IDREQ[12],IDREQ[13],IDREQ[14],IDREQ[15],IDREQ[16],IDREQ[17],IDREQ[18],IDREQ[19],IDREQ[20],IDREQ[21],IDREQ[22],IDREQ[23],IDREQ[24],IDREQ[25],IDREQ[26],IDREQ[27],IDREQ[28],IDREQ[29],IDREQ[30],IDREQ[31]"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " BC ,Block Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer Count"
|
|
line.long 0x04 "DMACB_1,Configuration B Register 1"
|
|
bitfld.long 0x04 28.--29. " MS ,Mode Select" "Block,Burst,Demand,"
|
|
bitfld.long 0x04 26.--27. " TW ,Transfer Width" "8 bits,16 bits,32 bits,"
|
|
bitfld.long 0x04 25. " FS ,Fixed Source" "Incremented,Fixed"
|
|
bitfld.long 0x04 24. " FD ,Fixed Destination" "Incremented,Fixed"
|
|
textline " "
|
|
bitfld.long 0x04 23. " RC ,Reload Count (BC/TC reload)" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " RS ,Reload Source" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " RD ,Reload Destination" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " EI ,Error Interrupt (unsuccessful transfer completion interrupt enable)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " CI ,Completion Interrupt (successful transfer completion interrupt enable)" "Disabled,Enabled"
|
|
bitfld.long 0x04 16.--18. " SS ,Stop Status (stop status notification)" "Initial value,Address overflow,Stop request,Source error,Destination error,Completed,,Pause"
|
|
bitfld.long 0x04 0. " EM , Enable bit Mask (EB bit clear mask)" "Cleared,Not cleared"
|
|
line.long 0x08 "DMACSA_1,Transfer Source Address Register 0"
|
|
line.long 0x0C "DMACDA_1,Transfer Destination Address Register"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree "I/O Ports"
|
|
base ad:0x40033000
|
|
width 7.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PFR0,Port Function Setting Register 0"
|
|
bitfld.long 0x00 15. " P0_F ,Port function bit 15" "GPIO,I/O"
|
|
bitfld.long 0x00 14. " P0_E ,Port function bit 14" "GPIO,I/O"
|
|
bitfld.long 0x00 13. " P0_D ,Port function bit 13" "GPIO,I/O"
|
|
bitfld.long 0x00 12. " P0_C ,Port function bit 12" "GPIO,I/O"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P0_B ,Port function bit 11" "GPIO,I/O"
|
|
bitfld.long 0x00 10. " P0_A ,Port function bit 10" "GPIO,I/O"
|
|
bitfld.long 0x00 9. " P0_9 ,Port function bit 9" "GPIO,I/O"
|
|
bitfld.long 0x00 8. " P0_8 ,Port function bit 8" "GPIO,I/O"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P0_7 ,Port function bit 7" "GPIO,I/O"
|
|
bitfld.long 0x00 6. " P0_6 ,Port function bit 6" "GPIO,I/O"
|
|
bitfld.long 0x00 5. " P0_5 ,Port function bit 5" "GPIO,I/O"
|
|
bitfld.long 0x00 4. " P0_4 ,Port function bit 4" "GPIO,I/O"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P0_3 ,Port function bit 3" "GPIO,I/O"
|
|
bitfld.long 0x00 2. " P0_2 ,Port function bit 2" "GPIO,I/O"
|
|
bitfld.long 0x00 1. " P0_1 ,Port function bit 1" "GPIO,I/O"
|
|
bitfld.long 0x00 0. " P0_0 ,Port function bit 0" "GPIO,I/O"
|
|
sif cpuis("S6E1A11B")||cpuis("S6E1A12B")||cpuis("S6E1C11B")||cpuis("S6E1C12B")||cpuis("S6E1C31B")||cpuis("S6E1C32B")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PFR1,Port Function Setting Register 1"
|
|
sif cpuis("S6E1C11B")||cpuis("S6E1C12B")||cpuis("S6E1C31B")||cpuis("S6E1C32B")
|
|
bitfld.long 0x00 7. " P1_7 ,Port function bit 7" "GPIO,I/O"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " P1_6 ,Port function bit 6" "GPIO,I/O"
|
|
bitfld.long 0x00 5. " P1_5 ,Port function bit 5" "GPIO,I/O"
|
|
bitfld.long 0x00 4. " P1_4 ,Port function bit 4" "GPIO,I/O"
|
|
bitfld.long 0x00 3. " P1_3 ,Port function bit 3" "GPIO,I/O"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P1_2 ,Port function bit 2" "GPIO,I/O"
|
|
bitfld.long 0x00 1. " P1_1 ,Port function bit 1" "GPIO,I/O"
|
|
bitfld.long 0x00 0. " P1_0 ,Port function bit 0" "GPIO,I/O"
|
|
elif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C31C")||cpuis("S6E1C32C")
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "PFR1,Port Function Setting Register 1"
|
|
bitfld.long 0x00 15. " P1_F ,Port function bit 15" "GPIO,I/O"
|
|
bitfld.long 0x00 14. " P1_E ,Port function bit 14" "GPIO,I/O"
|
|
bitfld.long 0x00 13. " P1_D ,Port function bit 13" "GPIO,I/O"
|
|
bitfld.long 0x00 12. " P1_C ,Port function bit 12" "GPIO,I/O"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P1_B ,Port function bit 11" "GPIO,I/O"
|
|
bitfld.long 0x00 10. " P1_A ,Port function bit 10" "GPIO,I/O"
|
|
bitfld.long 0x00 9. " P1_9 ,Port function bit 9" "GPIO,I/O"
|
|
bitfld.long 0x00 8. " P1_8 ,Port function bit 8" "GPIO,I/O"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P1_7 ,Port function bit 7" "GPIO,I/O"
|
|
bitfld.long 0x00 6. " P1_6 ,Port function bit 6" "GPIO,I/O"
|
|
bitfld.long 0x00 5. " P1_5 ,Port function bit 5" "GPIO,I/O"
|
|
bitfld.long 0x00 4. " P1_4 ,Port function bit 4" "GPIO,I/O"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P1_3 ,Port function bit 3" "GPIO,I/O"
|
|
bitfld.long 0x00 2. " P1_2 ,Port function bit 2" "GPIO,I/O"
|
|
bitfld.long 0x00 1. " P1_1 ,Port function bit 1" "GPIO,I/O"
|
|
bitfld.long 0x00 0. " P1_0 ,Port function bit 0" "GPIO,I/O"
|
|
line.long 0x04 "PFR2,Port Function Setting Register 2"
|
|
sif cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C31C")||cpuis("S6E1C32C")
|
|
bitfld.long 0x04 5. " P2_5 ,Port function bit 5" "GPIO,I/O"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 4. " P2_4 ,Port function bit 4" "GPIO,I/O"
|
|
bitfld.long 0x04 3. " P2_3 ,Port function bit 3" "GPIO,I/O"
|
|
bitfld.long 0x04 2. " P2_2 ,Port function bit 2" "GPIO,I/O"
|
|
bitfld.long 0x04 1. " P2_1 ,Port function bit 1" "GPIO,I/O"
|
|
textline " "
|
|
bitfld.long 0x04 0. " P2_0 ,Port function bit 0" "GPIO,I/O"
|
|
elif cpuis("S6E1C11D")||cpuis("S6E1C12D")||cpuis("S6E1C31D")||cpuis("S6E1C32D")
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "PFR1,Port Function Setting Register 1"
|
|
bitfld.long 0x00 15. " P1_F ,Port function bit 15" "GPIO,I/O"
|
|
bitfld.long 0x00 14. " P1_E ,Port function bit 14" "GPIO,I/O"
|
|
bitfld.long 0x00 13. " P1_D ,Port function bit 13" "GPIO,I/O"
|
|
bitfld.long 0x00 12. " P1_C ,Port function bit 12" "GPIO,I/O"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P1_B ,Port function bit 11" "GPIO,I/O"
|
|
bitfld.long 0x00 10. " P1_A ,Port function bit 10" "GPIO,I/O"
|
|
bitfld.long 0x00 9. " P1_9 ,Port function bit 9" "GPIO,I/O"
|
|
bitfld.long 0x00 8. " P1_8 ,Port function bit 8" "GPIO,I/O"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P1_7 ,Port function bit 7" "GPIO,I/O"
|
|
bitfld.long 0x00 6. " P1_6 ,Port function bit 6" "GPIO,I/O"
|
|
bitfld.long 0x00 5. " P1_5 ,Port function bit 5" "GPIO,I/O"
|
|
bitfld.long 0x00 4. " P1_4 ,Port function bit 4" "GPIO,I/O"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P1_3 ,Port function bit 3" "GPIO,I/O"
|
|
bitfld.long 0x00 2. " P1_2 ,Port function bit 2" "GPIO,I/O"
|
|
bitfld.long 0x00 1. " P1_1 ,Port function bit 1" "GPIO,I/O"
|
|
bitfld.long 0x00 0. " P1_0 ,Port function bit 0" "GPIO,I/O"
|
|
line.long 0x04 "PFR2,Port Function Setting Register 2"
|
|
bitfld.long 0x04 15. " P2_F ,Port function bit 15" "GPIO,I/O"
|
|
bitfld.long 0x04 14. " P2_E ,Port function bit 14" "GPIO,I/O"
|
|
bitfld.long 0x04 13. " P2_D ,Port function bit 13" "GPIO,I/O"
|
|
bitfld.long 0x04 12. " P2_C ,Port function bit 12" "GPIO,I/O"
|
|
textline " "
|
|
bitfld.long 0x04 11. " P2_B ,Port function bit 11" "GPIO,I/O"
|
|
bitfld.long 0x04 10. " P2_A ,Port function bit 10" "GPIO,I/O"
|
|
bitfld.long 0x04 9. " P2_9 ,Port function bit 9" "GPIO,I/O"
|
|
bitfld.long 0x04 8. " P2_8 ,Port function bit 8" "GPIO,I/O"
|
|
textline " "
|
|
bitfld.long 0x04 7. " P2_7 ,Port function bit 7" "GPIO,I/O"
|
|
bitfld.long 0x04 6. " P2_6 ,Port function bit 6" "GPIO,I/O"
|
|
bitfld.long 0x04 5. " P2_5 ,Port function bit 5" "GPIO,I/O"
|
|
bitfld.long 0x04 4. " P2_4 ,Port function bit 4" "GPIO,I/O"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P2_3 ,Port function bit 3" "GPIO,I/O"
|
|
bitfld.long 0x04 2. " P2_2 ,Port function bit 2" "GPIO,I/O"
|
|
bitfld.long 0x04 1. " P2_1 ,Port function bit 1" "GPIO,I/O"
|
|
bitfld.long 0x04 0. " P2_0 ,Port function bit 0" "GPIO,I/O"
|
|
line.long 0x08 "PFR3,Port Function Setting Register 3"
|
|
bitfld.long 0x08 5. " P3_5 ,Port function bit 5" "GPIO,I/O"
|
|
bitfld.long 0x08 4. " P3_4 ,Port function bit 4" "GPIO,I/O"
|
|
textline " "
|
|
bitfld.long 0x08 3. " P3_3 ,Port function bit 3" "GPIO,I/O"
|
|
bitfld.long 0x08 2. " P3_2 ,Port function bit 2" "GPIO,I/O"
|
|
bitfld.long 0x08 1. " P3_1 ,Port function bit 1" "GPIO,I/O"
|
|
bitfld.long 0x08 0. " P3_0 ,Port function bit 0" "GPIO,I/O"
|
|
endif
|
|
textline " "
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PCR0,Pull-Up Setting Register 0"
|
|
bitfld.long 0x00 15. " P0_F ,Pull-up setting bit 15" "Disconnected,Connected"
|
|
bitfld.long 0x00 14. " P0_E ,Pull-up setting bit 14" "Disconnected,Connected"
|
|
bitfld.long 0x00 13. " P0_D ,Pull-up setting bit 13" "Disconnected,Connected"
|
|
bitfld.long 0x00 12. " P0_C ,Pull-up setting bit 12" "Disconnected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P0_B ,Pull-up setting bit 11" "Disconnected,Connected"
|
|
bitfld.long 0x00 10. " P0_A ,Pull-up setting bit 10" "Disconnected,Connected"
|
|
bitfld.long 0x00 9. " P0_9 ,Pull-up setting bit 9" "Disconnected,Connected"
|
|
bitfld.long 0x00 8. " P0_8 ,Pull-up setting bit 8" "Disconnected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P0_7 ,Pull-up setting bit 7" "Disconnected,Connected"
|
|
bitfld.long 0x00 6. " P0_6 ,Pull-up setting bit 6" "Disconnected,Connected"
|
|
bitfld.long 0x00 5. " P0_5 ,Pull-up setting bit 5" "Disconnected,Connected"
|
|
bitfld.long 0x00 4. " P0_4 ,Pull-up setting bit 4" "Disconnected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P0_3 ,Pull-up setting bit 3" "Disconnected,Connected"
|
|
bitfld.long 0x00 2. " P0_2 ,Pull-up setting bit 2" "Disconnected,Connected"
|
|
bitfld.long 0x00 1. " P0_1 ,Pull-up setting bit 1" "Disconnected,Connected"
|
|
bitfld.long 0x00 0. " P0_0 ,Pull-up setting bit 0" "Disconnected,Connected"
|
|
sif cpuis("S6E1A11B")||cpuis("S6E1A12B")||cpuis("S6E1C11B")||cpuis("S6E1C12B")||cpuis("S6E1C31B")||cpuis("S6E1C32B")
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "PCR1,Pull-Up Setting Register 1"
|
|
sif cpuis("S6E1C11B")||cpuis("S6E1C12B")||cpuis("S6E1C31B")||cpuis("S6E1C32B")
|
|
bitfld.long 0x00 7. " P1_7 ,Pull-up setting bit 7" "Disconnected,Connected"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " P1_6 ,Pull-up setting bit 6" "Disconnected,Connected"
|
|
bitfld.long 0x00 5. " P1_5 ,Pull-up setting bit 5" "Disconnected,Connected"
|
|
bitfld.long 0x00 4. " P1_4 ,Pull-up setting bit 4" "Disconnected,Connected"
|
|
bitfld.long 0x00 3. " P1_3 ,Pull-up setting bit 3" "Disconnected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P1_2 ,Pull-up setting bit 2" "Disconnected,Connected"
|
|
bitfld.long 0x00 1. " P1_1 ,Pull-up setting bit 1" "Disconnected,Connected"
|
|
bitfld.long 0x00 0. " P1_0 ,Pull-up setting bit 0" "Disconnected,Connected"
|
|
elif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C31C")||cpuis("S6E1C32C")
|
|
group.long 0x104++0x07
|
|
line.long 0x00 "PCR1,Pull-Up Setting Register 1"
|
|
bitfld.long 0x00 15. " P1_F ,Pull-up setting bit 15" "Disconnected,Connected"
|
|
bitfld.long 0x00 14. " P1_E ,Pull-up setting bit 14" "Disconnected,Connected"
|
|
bitfld.long 0x00 13. " P1_D ,Pull-up setting bit 13" "Disconnected,Connected"
|
|
bitfld.long 0x00 12. " P1_C ,Pull-up setting bit 12" "Disconnected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P1_B ,Pull-up setting bit 11" "Disconnected,Connected"
|
|
bitfld.long 0x00 10. " P1_A ,Pull-up setting bit 10" "Disconnected,Connected"
|
|
bitfld.long 0x00 9. " P1_9 ,Pull-up setting bit 9" "Disconnected,Connected"
|
|
bitfld.long 0x00 8. " P1_8 ,Pull-up setting bit 8" "Disconnected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P1_7 ,Pull-up setting bit 7" "Disconnected,Connected"
|
|
bitfld.long 0x00 6. " P1_6 ,Pull-up setting bit 6" "Disconnected,Connected"
|
|
bitfld.long 0x00 5. " P1_5 ,Pull-up setting bit 5" "Disconnected,Connected"
|
|
bitfld.long 0x00 4. " P1_4 ,Pull-up setting bit 4" "Disconnected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P1_3 ,Pull-up setting bit 3" "Disconnected,Connected"
|
|
bitfld.long 0x00 2. " P1_2 ,Pull-up setting bit 2" "Disconnected,Connected"
|
|
bitfld.long 0x00 1. " P1_1 ,Pull-up setting bit 1" "Disconnected,Connected"
|
|
bitfld.long 0x00 0. " P1_0 ,Pull-up setting bit 0" "Disconnected,Connected"
|
|
line.long 0x04 "PCR2,Pull-Up Setting Register 2"
|
|
sif cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C31C")||cpuis("S6E1C32C")
|
|
bitfld.long 0x04 5. " P2_5 ,Pull-up setting bit 5" "Disconnected,Connected"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 4. " P2_4 ,Pull-up setting bit 4" "Disconnected,Connected"
|
|
bitfld.long 0x04 3. " P2_3 ,Pull-up setting bit 3" "Disconnected,Connected"
|
|
bitfld.long 0x04 2. " P2_2 ,Pull-up setting bit 2" "Disconnected,Connected"
|
|
bitfld.long 0x04 1. " P2_1 ,Pull-up setting bit 1" "Disconnected,Connected"
|
|
textline " "
|
|
bitfld.long 0x04 0. " P2_0 ,Pull-up setting bit 0" "Disconnected,Connected"
|
|
elif cpuis("S6E1C11D")||cpuis("S6E1C12D")||cpuis("S6E1C31D")||cpuis("S6E1C32D")
|
|
group.long 0x104++0x0B
|
|
line.long 0x00 "PCR1,Pull-Up Setting Register 1"
|
|
bitfld.long 0x00 15. " P1_F ,Pull-up setting bit 15" "Disconnected,Connected"
|
|
bitfld.long 0x00 14. " P1_E ,Pull-up setting bit 14" "Disconnected,Connected"
|
|
bitfld.long 0x00 13. " P1_D ,Pull-up setting bit 13" "Disconnected,Connected"
|
|
bitfld.long 0x00 12. " P1_C ,Pull-up setting bit 12" "Disconnected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P1_B ,Pull-up setting bit 11" "Disconnected,Connected"
|
|
bitfld.long 0x00 10. " P1_A ,Pull-up setting bit 10" "Disconnected,Connected"
|
|
bitfld.long 0x00 9. " P1_9 ,Pull-up setting bit 9" "Disconnected,Connected"
|
|
bitfld.long 0x00 8. " P1_8 ,Pull-up setting bit 8" "Disconnected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P1_7 ,Pull-up setting bit 7" "Disconnected,Connected"
|
|
bitfld.long 0x00 6. " P1_6 ,Pull-up setting bit 6" "Disconnected,Connected"
|
|
bitfld.long 0x00 5. " P1_5 ,Pull-up setting bit 5" "Disconnected,Connected"
|
|
bitfld.long 0x00 4. " P1_4 ,Pull-up setting bit 4" "Disconnected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P1_3 ,Pull-up setting bit 3" "Disconnected,Connected"
|
|
bitfld.long 0x00 2. " P1_2 ,Pull-up setting bit 2" "Disconnected,Connected"
|
|
bitfld.long 0x00 1. " P1_1 ,Pull-up setting bit 1" "Disconnected,Connected"
|
|
bitfld.long 0x00 0. " P1_0 ,Pull-up setting bit 0" "Disconnected,Connected"
|
|
line.long 0x04 "PCR2,Pull-Up Setting Register 2"
|
|
bitfld.long 0x04 15. " P2_F ,Pull-up setting bit 15" "Disconnected,Connected"
|
|
bitfld.long 0x04 14. " P2_E ,Pull-up setting bit 14" "Disconnected,Connected"
|
|
bitfld.long 0x04 13. " P2_D ,Pull-up setting bit 13" "Disconnected,Connected"
|
|
bitfld.long 0x04 12. " P2_C ,Pull-up setting bit 12" "Disconnected,Connected"
|
|
textline " "
|
|
bitfld.long 0x04 11. " P2_B ,Pull-up setting bit 11" "Disconnected,Connected"
|
|
bitfld.long 0x04 10. " P2_A ,Pull-up setting bit 10" "Disconnected,Connected"
|
|
bitfld.long 0x04 9. " P2_9 ,Pull-up setting bit 9" "Disconnected,Connected"
|
|
bitfld.long 0x04 8. " P2_8 ,Pull-up setting bit 8" "Disconnected,Connected"
|
|
textline " "
|
|
bitfld.long 0x04 7. " P2_7 ,Pull-up setting bit 7" "Disconnected,Connected"
|
|
bitfld.long 0x04 6. " P2_6 ,Pull-up setting bit 6" "Disconnected,Connected"
|
|
bitfld.long 0x04 5. " P2_5 ,Pull-up setting bit 5" "Disconnected,Connected"
|
|
bitfld.long 0x04 4. " P2_4 ,Pull-up setting bit 4" "Disconnected,Connected"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P2_3 ,Pull-up setting bit 3" "Disconnected,Connected"
|
|
bitfld.long 0x04 2. " P2_2 ,Pull-up setting bit 2" "Disconnected,Connected"
|
|
bitfld.long 0x04 1. " P2_1 ,Pull-up setting bit 1" "Disconnected,Connected"
|
|
bitfld.long 0x04 0. " P2_0 ,Pull-up setting bit 0" "Disconnected,Connected"
|
|
line.long 0x08 "PCR3,Pull-Up Setting Register 3"
|
|
bitfld.long 0x08 5. " P3_5 ,Pull-up setting bit 5" "Disconnected,Connected"
|
|
bitfld.long 0x08 4. " P3_4 ,Pull-up setting bit 4" "Disconnected,Connected"
|
|
textline " "
|
|
bitfld.long 0x08 3. " P3_3 ,Pull-up setting bit 3" "Disconnected,Connected"
|
|
bitfld.long 0x08 2. " P3_2 ,Pull-up setting bit 2" "Disconnected,Connected"
|
|
bitfld.long 0x08 1. " P3_1 ,Pull-up setting bit 1" "Disconnected,Connected"
|
|
bitfld.long 0x08 0. " P3_0 ,Pull-up setting bit 0" "Disconnected,Connected"
|
|
endif
|
|
textline " "
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "DDR0,Port Input/Output Direction Setting Register 0"
|
|
bitfld.long 0x00 15. " P0_F ,Port input/output direction bit 15" "Input,Output"
|
|
bitfld.long 0x00 14. " P0_E ,Port input/output direction bit 14" "Input,Output"
|
|
bitfld.long 0x00 13. " P0_D ,Port input/output direction bit 13" "Input,Output"
|
|
bitfld.long 0x00 12. " P0_C ,Port input/output direction bit 12" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P0_B ,Port input/output direction bit 11" "Input,Output"
|
|
bitfld.long 0x00 10. " P0_A ,Port input/output direction bit 10" "Input,Output"
|
|
bitfld.long 0x00 9. " P0_9 ,Port input/output direction bit 9" "Input,Output"
|
|
bitfld.long 0x00 8. " P0_8 ,Port input/output direction bit 8" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P0_7 ,Port input/output direction bit 7" "Input,Output"
|
|
bitfld.long 0x00 6. " P0_6 ,Port input/output direction bit 6" "Input,Output"
|
|
bitfld.long 0x00 5. " P0_5 ,Port input/output direction bit 5" "Input,Output"
|
|
bitfld.long 0x00 4. " P0_4 ,Port input/output direction bit 4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P0_3 ,Port input/output direction bit 3" "Input,Output"
|
|
bitfld.long 0x00 2. " P0_2 ,Port input/output direction bit 2" "Input,Output"
|
|
bitfld.long 0x00 1. " P0_1 ,Port input/output direction bit 1" "Input,Output"
|
|
bitfld.long 0x00 0. " P0_0 ,Port input/output direction bit 0" "Input,Output"
|
|
sif cpuis("S6E1A11B")||cpuis("S6E1A12B")||cpuis("S6E1C11B")||cpuis("S6E1C12B")||cpuis("S6E1C31B")||cpuis("S6E1C32B")
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "DDR1,Port Input/Output Direction Setting Register 1"
|
|
sif cpuis("S6E1C11B")||cpuis("S6E1C12B")||cpuis("S6E1C31B")||cpuis("S6E1C32B")
|
|
bitfld.long 0x00 7. " P1_7 ,Port input/output direction bit 7" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " P1_6 ,Port input/output direction bit 6" "Input,Output"
|
|
bitfld.long 0x00 5. " P1_5 ,Port input/output direction bit 5" "Input,Output"
|
|
bitfld.long 0x00 4. " P1_4 ,Port input/output direction bit 4" "Input,Output"
|
|
bitfld.long 0x00 3. " P1_3 ,Port input/output direction bit 3" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P1_2 ,Port input/output direction bit 2" "Input,Output"
|
|
bitfld.long 0x00 1. " P1_1 ,Port input/output direction bit 1" "Input,Output"
|
|
bitfld.long 0x00 0. " P1_0 ,Port input/output direction bit 0" "Input,Output"
|
|
elif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C31C")||cpuis("S6E1C32C")
|
|
group.long 0x204++0x07
|
|
line.long 0x00 "DDR1,Port Input/Output Direction Setting Register 1"
|
|
bitfld.long 0x00 15. " P1_F ,Port input/output direction bit 15" "Input,Output"
|
|
bitfld.long 0x00 14. " P1_E ,Port input/output direction bit 14" "Input,Output"
|
|
bitfld.long 0x00 13. " P1_D ,Port input/output direction bit 13" "Input,Output"
|
|
bitfld.long 0x00 12. " P1_C ,Port input/output direction bit 12" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P1_B ,Port input/output direction bit 11" "Input,Output"
|
|
bitfld.long 0x00 10. " P1_A ,Port input/output direction bit 10" "Input,Output"
|
|
bitfld.long 0x00 9. " P1_9 ,Port input/output direction bit 9" "Input,Output"
|
|
bitfld.long 0x00 8. " P1_8 ,Port input/output direction bit 8" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P1_7 ,Port input/output direction bit 7" "Input,Output"
|
|
bitfld.long 0x00 6. " P1_6 ,Port input/output direction bit 6" "Input,Output"
|
|
bitfld.long 0x00 5. " P1_5 ,Port input/output direction bit 5" "Input,Output"
|
|
bitfld.long 0x00 4. " P1_4 ,Port input/output direction bit 4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P1_3 ,Port input/output direction bit 3" "Input,Output"
|
|
bitfld.long 0x00 2. " P1_2 ,Port input/output direction bit 2" "Input,Output"
|
|
bitfld.long 0x00 1. " P1_1 ,Port input/output direction bit 1" "Input,Output"
|
|
bitfld.long 0x00 0. " P1_0 ,Port input/output direction bit 0" "Input,Output"
|
|
line.long 0x04 "DDR2,Port Input/Output Direction Setting Register 2"
|
|
sif cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C31C")||cpuis("S6E1C32C")
|
|
bitfld.long 0x04 5. " P2_5 ,Port input/output direction bit 5" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 4. " P2_4 ,Port input/output direction bit 4" "Input,Output"
|
|
bitfld.long 0x04 3. " P2_3 ,Port input/output direction bit 3" "Input,Output"
|
|
bitfld.long 0x04 2. " P2_2 ,Port input/output direction bit 2" "Input,Output"
|
|
bitfld.long 0x04 1. " P2_1 ,Port input/output direction bit 1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 0. " P2_0 ,Port input/output direction bit 0" "Input,Output"
|
|
elif cpuis("S6E1C11D")||cpuis("S6E1C12D")||cpuis("S6E1C31D")||cpuis("S6E1C32D")
|
|
group.long 0x204++0x0B
|
|
line.long 0x00 "DDR1,Port Input/Output Direction Setting Register 1"
|
|
bitfld.long 0x00 15. " P1_F ,Port input/output direction bit 15" "Input,Output"
|
|
bitfld.long 0x00 14. " P1_E ,Port input/output direction bit 14" "Input,Output"
|
|
bitfld.long 0x00 13. " P1_D ,Port input/output direction bit 13" "Input,Output"
|
|
bitfld.long 0x00 12. " P1_C ,Port input/output direction bit 12" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P1_B ,Port input/output direction bit 11" "Input,Output"
|
|
bitfld.long 0x00 10. " P1_A ,Port input/output direction bit 10" "Input,Output"
|
|
bitfld.long 0x00 9. " P1_9 ,Port input/output direction bit 9" "Input,Output"
|
|
bitfld.long 0x00 8. " P1_8 ,Port input/output direction bit 8" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P1_7 ,Port input/output direction bit 7" "Input,Output"
|
|
bitfld.long 0x00 6. " P1_6 ,Port input/output direction bit 6" "Input,Output"
|
|
bitfld.long 0x00 5. " P1_5 ,Port input/output direction bit 5" "Input,Output"
|
|
bitfld.long 0x00 4. " P1_4 ,Port input/output direction bit 4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P1_3 ,Port input/output direction bit 3" "Input,Output"
|
|
bitfld.long 0x00 2. " P1_2 ,Port input/output direction bit 2" "Input,Output"
|
|
bitfld.long 0x00 1. " P1_1 ,Port input/output direction bit 1" "Input,Output"
|
|
bitfld.long 0x00 0. " P1_0 ,Port input/output direction bit 0" "Input,Output"
|
|
line.long 0x04 "DDR2,Port Input/Output Direction Setting Register 2"
|
|
bitfld.long 0x04 15. " P2_F ,Port input/output direction bit 15" "Input,Output"
|
|
bitfld.long 0x04 14. " P2_E ,Port input/output direction bit 14" "Input,Output"
|
|
bitfld.long 0x04 13. " P2_D ,Port input/output direction bit 13" "Input,Output"
|
|
bitfld.long 0x04 12. " P2_C ,Port input/output direction bit 12" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 11. " P2_B ,Port input/output direction bit 11" "Input,Output"
|
|
bitfld.long 0x04 10. " P2_A ,Port input/output direction bit 10" "Input,Output"
|
|
bitfld.long 0x04 9. " P2_9 ,Port input/output direction bit 9" "Input,Output"
|
|
bitfld.long 0x04 8. " P2_8 ,Port input/output direction bit 8" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 7. " P2_7 ,Port input/output direction bit 7" "Input,Output"
|
|
bitfld.long 0x04 6. " P2_6 ,Port input/output direction bit 6" "Input,Output"
|
|
bitfld.long 0x04 5. " P2_5 ,Port input/output direction bit 5" "Input,Output"
|
|
bitfld.long 0x04 4. " P2_4 ,Port input/output direction bit 4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P2_3 ,Port input/output direction bit 3" "Input,Output"
|
|
bitfld.long 0x04 2. " P2_2 ,Port input/output direction bit 2" "Input,Output"
|
|
bitfld.long 0x04 1. " P2_1 ,Port input/output direction bit 1" "Input,Output"
|
|
bitfld.long 0x04 0. " P2_0 ,Port input/output direction bit 0" "Input,Output"
|
|
line.long 0x08 "DDR3,Port Input/Output Direction Setting Register 3"
|
|
bitfld.long 0x08 5. " P3_5 ,Port input/output direction bit 5" "Input,Output"
|
|
bitfld.long 0x08 4. " P3_4 ,Port input/output direction bit 4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x08 3. " P3_3 ,Port input/output direction bit 3" "Input,Output"
|
|
bitfld.long 0x08 2. " P3_2 ,Port input/output direction bit 2" "Input,Output"
|
|
bitfld.long 0x08 1. " P3_1 ,Port input/output direction bit 1" "Input,Output"
|
|
bitfld.long 0x08 0. " P3_0 ,Port input/output direction bit 0" "Input,Output"
|
|
endif
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "PDIR0,Port Input Data Register 0"
|
|
bitfld.long 0x00 15. " P0_F ,Port input data bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " P0_E ,Port input data bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " P0_D ,Port input data bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " P0_C ,Port input data bit 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P0_B ,Port input data bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " P0_A ,Port input data bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " P0_9 ,Port input data bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " P0_8 ,Port input data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P0_7 ,Port input data bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " P0_6 ,Port input data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " P0_5 ,Port input data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " P0_4 ,Port input data bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P0_3 ,Port Input Data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " P0_2 ,Port input data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P0_1 ,Port input data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " P0_0 ,Port input data bit 0" "Low,High"
|
|
sif cpuis("S6E1A11B")||cpuis("S6E1A12B")||cpuis("S6E1C11B")||cpuis("S6E1C12B")||cpuis("S6E1C31B")||cpuis("S6E1C32B")
|
|
rgroup.long 0x304++0x03
|
|
line.long 0x00 "PDIR1,Port Input Data Register 1"
|
|
sif cpuis("S6E1C11B")||cpuis("S6E1C12B")||cpuis("S6E1C31B")||cpuis("S6E1C32B")
|
|
bitfld.long 0x00 7. " P1_7 ,Port input data bit 7" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " P1_6 ,Port 7Input Data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " P1_5 ,Port input data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " P1_4 ,Port input data bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " P1_3 ,Port input data bit 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P1_2 ,Port input data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P1_1 ,Port input data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " P1_0 ,Port input data bit 0" "Low,High"
|
|
elif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C31C")||cpuis("S6E1C32C")
|
|
rgroup.long 0x304++0x07
|
|
line.long 0x00 "PDIR1,Port Input Data Register 1"
|
|
bitfld.long 0x00 15. " P1_F ,Port input data bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " P1_E ,Port input data bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " P1_D ,Port input data bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " P1_C ,Port input data bit 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P1_B ,Port input data bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " P1_A ,Port input data bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " P1_9 ,Port input data bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " P1_8 ,Port input data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P1_7 ,Port input data bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " P1_6 ,Port input data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " P1_5 ,Port input data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " P1_4 ,Port input data bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P1_3 ,Port input data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " P1_2 ,Port input data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P1_1 ,Port input data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " P1_0 ,Port input data bit 0" "Low,High"
|
|
line.long 0x04 "PDIR2,Port Input Data Register 2"
|
|
sif cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C31C")||cpuis("S6E1C32C")
|
|
bitfld.long 0x04 5. " P2_5 ,Port input data bit 5" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 4. " P2_4 ,Port input data bit 4" "Low,High"
|
|
bitfld.long 0x04 3. " P2_3 ,Port input data bit 3" "Low,High"
|
|
bitfld.long 0x04 2. " P2_2 ,Port input data bit 2" "Low,High"
|
|
bitfld.long 0x04 1. " P2_1 ,Port input data bit 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 0. " P2_0 ,Port input data bit 0" "Low,High"
|
|
elif cpuis("S6E1C11D")||cpuis("S6E1C12D")||cpuis("S6E1C31D")||cpuis("S6E1C32D")
|
|
rgroup.long 0x304++0x0B
|
|
line.long 0x00 "PDIR1,Port Input Data Register 1"
|
|
bitfld.long 0x00 15. " P1_F ,Port Input Data bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " P1_E ,Port input data bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " P1_D ,Port input data bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " P1_C ,Port input data bit 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P1_B ,Port input data bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " P1_A ,Port input data bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " P1_9 ,Port input data bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " P1_8 ,Port input data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P1_7 ,Port input data bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " P1_6 ,Port input data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " P1_5 ,Port input data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " P1_4 ,Port input data bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P1_3 ,Port input data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " P1_2 ,Port input data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P1_1 ,Port input data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " P1_0 ,Port input data bit 0" "Low,High"
|
|
line.long 0x04 "PDIR2,Port Input Data Register 2"
|
|
bitfld.long 0x04 15. " P2_F ,Port input data bit 15" "Low,High"
|
|
bitfld.long 0x04 14. " P2_E ,Port input data bit 14" "Low,High"
|
|
bitfld.long 0x04 13. " P2_D ,Port input data bit 13" "Low,High"
|
|
bitfld.long 0x04 12. " P2_C ,Port input data bit 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 11. " P2_B ,Port input data bit 11" "Low,High"
|
|
bitfld.long 0x04 10. " P2_A ,Port input data bit 10" "Low,High"
|
|
bitfld.long 0x04 9. " P2_9 ,Port input data bit 9" "Low,High"
|
|
bitfld.long 0x04 8. " P2_8 ,Port input data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 7. " P2_7 ,Port input data bit 7" "Low,High"
|
|
bitfld.long 0x04 6. " P2_6 ,Port input data bit 6" "Low,High"
|
|
bitfld.long 0x04 5. " P2_5 ,Port input data bit 5" "Low,High"
|
|
bitfld.long 0x04 4. " P2_4 ,Port input data bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P2_3 ,Port input data bit 3" "Low,High"
|
|
bitfld.long 0x04 2. " P2_2 ,Port input data bit 2" "Low,High"
|
|
bitfld.long 0x04 1. " P2_1 ,Port input data bit 1" "Low,High"
|
|
bitfld.long 0x04 0. " P2_0 ,Port input data bit 0" "Low,High"
|
|
line.long 0x08 "PDIR3,Port Input Data Register 3"
|
|
bitfld.long 0x08 5. " P3_5 ,Port input data bit 5" "Low,High"
|
|
bitfld.long 0x08 4. " P3_4 ,Port input data bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 3. " P3_3 ,Port input data bit 3" "Low,High"
|
|
bitfld.long 0x08 2. " P3_2 ,Port input data bit 2" "Low,High"
|
|
bitfld.long 0x08 1. " P3_1 ,Port input data bit 1" "Low,High"
|
|
bitfld.long 0x08 0. " P3_0 ,Port input data bit 0" "Low,High"
|
|
endif
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "PDOR0,Port Output Data Register 0"
|
|
bitfld.long 0x00 15. " P0_F ,Port output data bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " P0_E ,Port output data bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " P0_D ,Port output data bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " P0_C ,Port output data bit 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P0_B ,Port output data bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " P0_A ,Port output data bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " P0_9 ,Port output data bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " P0_8 ,Port output data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P0_7 ,Port output data bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " P0_6 ,Port output data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " P0_5 ,Port output data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " P0_4 ,Port output data bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P0_3 ,Port output data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " P0_2 ,Port output data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P0_1 ,Port output data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " P0_0 ,Port output data bit 0" "Low,High"
|
|
sif cpuis("S6E1A11B")||cpuis("S6E1A12B")||cpuis("S6E1C11B")||cpuis("S6E1C12B")||cpuis("S6E1C31B")||cpuis("S6E1C32B")
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "PDOR1,Port Output Data Register 1"
|
|
sif cpuis("S6E1C11B")||cpuis("S6E1C12B")||cpuis("S6E1C31B")||cpuis("S6E1C32B")
|
|
bitfld.long 0x00 7. " P1_7 ,Port output data bit 7" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " P1_6 ,Port output data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " P1_5 ,Port output data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " P1_4 ,Port output data bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " P1_3 ,Port output data bit 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P1_2 ,Port output data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P1_1 ,Port output data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " P1_0 ,Port output data bit 0" "Low,High"
|
|
elif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C31C")||cpuis("S6E1C32C")
|
|
group.long 0x404++0x07
|
|
line.long 0x00 "PDOR1,Port Output Data Register 1"
|
|
bitfld.long 0x00 15. " P1_F ,Port output data bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " P1_E ,Port output data bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " P1_D ,Port output data bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " P1_C ,Port output data bit 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P1_B ,Port output data bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " P1_A ,Port output data bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " P1_9 ,Port output data bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " P1_8 ,Port output data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P1_7 ,Port output data bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " P1_6 ,Port output data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " P1_5 ,Port output data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " P1_4 ,Port output data bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P1_3 ,Port output data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " P1_2 ,Port output data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P1_1 ,Port output data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " P1_0 ,Port output data bit 0" "Low,High"
|
|
line.long 0x04 "PDOR2,Port Output Data Register 2"
|
|
sif cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C31C")||cpuis("S6E1C32C")
|
|
bitfld.long 0x04 5. " P2_5 ,Port output data bit 5" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 4. " P2_4 ,Port output data bit 4" "Low,High"
|
|
bitfld.long 0x04 3. " P2_3 ,Port output data bit 3" "Low,High"
|
|
bitfld.long 0x04 2. " P2_2 ,Port output data bit 2" "Low,High"
|
|
bitfld.long 0x04 1. " P2_1 ,Port output data bit 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 0. " P2_0 ,Port output data bit 0" "Low,High"
|
|
elif cpuis("S6E1C11D")||cpuis("S6E1C12D")||cpuis("S6E1C31D")||cpuis("S6E1C32D")
|
|
group.long 0x404++0x0B
|
|
line.long 0x00 "PDOR1,Port Output Data Register 1"
|
|
bitfld.long 0x00 15. " P1_F ,Port output data bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " P1_E ,Port output data bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " P1_D ,Port output data bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " P1_C ,Port output data bit 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P1_B ,Port output data bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " P1_A ,Port output data bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " P1_9 ,Port output data bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " P1_8 ,Port output data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P1_7 ,Port output data bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " P1_6 ,Port output data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " P1_5 ,Port output data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " P1_4 ,Port output data bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P1_3 ,Port output data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " P1_2 ,Port output data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P1_1 ,Port output data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " P1_0 ,Port output data bit 0" "Low,High"
|
|
line.long 0x04 "PDOR2,Port Output Data Register 2"
|
|
bitfld.long 0x04 15. " P2_F ,Port output data bit 15" "Low,High"
|
|
bitfld.long 0x04 14. " P2_E ,Port output data bit 14" "Low,High"
|
|
bitfld.long 0x04 13. " P2_D ,Port output data bit 13" "Low,High"
|
|
bitfld.long 0x04 12. " P2_C ,Port output data bit 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 11. " P2_B ,Port output data bit 11" "Low,High"
|
|
bitfld.long 0x04 10. " P2_A ,Port output data bit 10" "Low,High"
|
|
bitfld.long 0x04 9. " P2_9 ,Port output data bit 9" "Low,High"
|
|
bitfld.long 0x04 8. " P2_8 ,Port output data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 7. " P2_7 ,Port output data bit 7" "Low,High"
|
|
bitfld.long 0x04 6. " P2_6 ,Port output data bit 6" "Low,High"
|
|
bitfld.long 0x04 5. " P2_5 ,Port output data bit 5" "Low,High"
|
|
bitfld.long 0x04 4. " P2_4 ,Port output data bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P2_3 ,Port output data bit 3" "Low,High"
|
|
bitfld.long 0x04 2. " P2_2 ,Port output data bit 2" "Low,High"
|
|
bitfld.long 0x04 1. " P2_1 ,Port output data bit 1" "Low,High"
|
|
bitfld.long 0x04 0. " P2_0 ,Port output data bit 0" "Low,High"
|
|
line.long 0x08 "PDOR3,Port Output Data Register 3"
|
|
bitfld.long 0x08 5. " P3_5 ,Port output data bit 5" "Low,High"
|
|
bitfld.long 0x08 4. " P3_4 ,Port output data bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 3. " P3_3 ,Port output data bit 3" "Low,High"
|
|
bitfld.long 0x08 2. " P3_2 ,Port output data bit 2" "Low,High"
|
|
bitfld.long 0x08 1. " P3_1 ,Port output data bit 1" "Low,High"
|
|
bitfld.long 0x08 0. " P3_0 ,Port output data bit 0" "Low,High"
|
|
endif
|
|
width 0x0B
|
|
tree "Common Registers"
|
|
base ad:0x40033000
|
|
width 8.
|
|
group.long 0x500++0x003
|
|
line.long 0x00 "ADE,Analog Input Setting Register"
|
|
bitfld.long 0x00 31. " AN_31 ,Analog signal input pin 31 setting" "Digital I/O,Analog IN"
|
|
bitfld.long 0x00 30. " AN_30 ,Analog signal input pin 30 setting" "Digital I/O,Analog IN"
|
|
bitfld.long 0x00 29. " AN_29 ,Analog signal input pin 29 setting" "Digital I/O,Analog IN"
|
|
bitfld.long 0x00 28. " AN_28 ,Analog signal input pin 28 setting" "Digital I/O,Analog IN"
|
|
textline " "
|
|
bitfld.long 0x00 27. " AN_27 ,Analog signal input pin 27 setting" "Digital I/O,Analog IN"
|
|
bitfld.long 0x00 26. " AN_26 ,Analog signal input pin 26 setting" "Digital I/O,Analog IN"
|
|
bitfld.long 0x00 25. " AN_25 ,Analog signal input pin 25 setting" "Digital I/O,Analog IN"
|
|
bitfld.long 0x00 24. " AN_24 ,Analog signal input pin 24 setting" "Digital I/O,Analog IN"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AN_23 ,Analog signal input pin 23 setting" "Digital I/O,Analog IN"
|
|
bitfld.long 0x00 22. " AN_22 ,Analog signal input pin 22 setting" "Digital I/O,Analog IN"
|
|
bitfld.long 0x00 21. " AN_21 ,Analog signal input pin 21 setting" "Digital I/O,Analog IN"
|
|
bitfld.long 0x00 20. " AN_20 ,Analog signal input pin 20 setting" "Digital I/O,Analog IN"
|
|
textline " "
|
|
bitfld.long 0x00 19. " AN_19 ,Analog signal input pin 19 setting" "Digital I/O,Analog IN"
|
|
bitfld.long 0x00 18. " AN_18 ,Analog signal input pin 18 setting" "Digital I/O,Analog IN"
|
|
bitfld.long 0x00 17. " AN_17 ,Analog signal input pin 17 setting" "Digital I/O,Analog IN"
|
|
bitfld.long 0x00 16. " AN_16 ,Analog signal input pin 16 setting" "Digital I/O,Analog IN"
|
|
textline " "
|
|
bitfld.long 0x00 15. " AN_15 ,Analog signal input pin 15 setting" "Digital I/O,Analog IN"
|
|
bitfld.long 0x00 14. " AN_14 ,Analog signal input pin 14 setting" "Digital I/O,Analog IN"
|
|
bitfld.long 0x00 13. " AN_13 ,Analog signal input pin 13 setting" "Digital I/O,Analog IN"
|
|
bitfld.long 0x00 12. " AN_12 ,Analog signal input pin 12 setting" "Digital I/O,Analog IN"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AN_11 ,Analog signal input pin 11 setting" "Digital I/O,Analog IN"
|
|
bitfld.long 0x00 10. " AN_10 ,Analog signal input pin 10 setting" "Digital I/O,Analog IN"
|
|
bitfld.long 0x00 9. " AN_9 ,Analog signal input pin 9 setting" "Digital I/O,Analog IN"
|
|
bitfld.long 0x00 8. " AN_8 ,Analog signal input pin 8 setting" "Digital I/O,Analog IN"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AN_7 ,Analog signal input pin 7 setting" "Digital I/O,Analog IN"
|
|
bitfld.long 0x00 6. " AN_6 ,Analog signal input pin 6 setting" "Digital I/O,Analog IN"
|
|
bitfld.long 0x00 5. " AN_5 ,Analog signal input pin 5 setting" "Digital I/O,Analog IN"
|
|
bitfld.long 0x00 4. " AN_4 ,Analog signal input pin 4 setting" "Digital I/O,Analog IN"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AN_3 ,Analog signal input pin 3 setting" "Digital I/O,Analog IN"
|
|
bitfld.long 0x00 2. " AN_2 ,Analog signal input pin 2 setting" "Digital I/O,Analog IN"
|
|
bitfld.long 0x00 1. " AN_1 ,Analog signal input pin 1 setting" "Digital I/O,Analog IN"
|
|
bitfld.long 0x00 0. " AN_0 ,Analog signal input pin 0 setting" "Digital I/O,Analog IN"
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "EPFR00,Extended Pin Function Setting Register 0"
|
|
bitfld.long 0x00 16. " SWDEN ,Serial Wire Debug Function Select bit 0" "Not used,Used"
|
|
textline " "
|
|
sif cpuis("S6E1C*")
|
|
bitfld.long 0x00 9. " USBP0E ,USB ch.0 function select bit 1" "Output D+ not produced,Output D+ produced"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6.--7. " SUBOUTE ,Sub clock divide output function select bit" "None,SUBOUT_0,SUBOUT_1,SUBOUT_2"
|
|
bitfld.long 0x00 4.--5. " RTCCOE ,RTC clock output select bit" "None,RTCCOE_0,RTCCOE_1,RTCCOE_2"
|
|
bitfld.long 0x00 1.--2. " CROUTE ,Internal high-speed CR oscillation output function select bit" "None,CROUT_0,CROUT_1,CROUT_2"
|
|
bitfld.long 0x00 0. " NMIS ,NMIX function select bit" "Not used,Used"
|
|
sif !cpuis("S6E1C*")
|
|
group.long 0x604++0x0B
|
|
line.long 0x00 "EPFR01,Extended Pin Function Setting Register 01"
|
|
bitfld.long 0x00 29.--31. " IC03S ,IC03 Input Select bits" "IC03_0,IC03_0,IC03_1,IC03_2,MFS ch.3 LSYN,ch.7 LSYN,,CRTRIM"
|
|
bitfld.long 0x00 26.--28. " IC02S ,IC02 Input Select bits" "IC02_0,IC02_0,IC02_1,IC02_2,MFS ch.2 LSYN,MFS ch.6 LSYN,,"
|
|
bitfld.long 0x00 23.--25. " IC01S ,IC01 Input Select bits" "IC01_0,IC01_0,IC01_1,IC01_2,MFS ch.1 LSYN,MFS ch.5 LSYN,,"
|
|
bitfld.long 0x00 20.--22. " IC00S ,IC00 Input Select bits" "IC00_0,IC00_0,IC00_1,IC00_2,MFS ch.0 LSYN,MFS ch.4 LSYN,,"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " FRCK0S ,FRCK0 Input Select bits" "FRCK0_0,FRCK0_0,FRCK0_1,FRCK0_2"
|
|
bitfld.long 0x00 16.--17. " DTTI0S ,DTTIX0 Input Select bits" "DTTIX0_0,DTTIX0_0,DTTIX0_1,DTTIX0_2"
|
|
bitfld.long 0x00 12. " DTTI0C ,DTTIX0 Function Select bit" "GPIO,DTTIF0"
|
|
bitfld.long 0x00 10.--11. " RTO05E ,RTO05 Output Select bits" "None,RTO05_0,RTO05_1,"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RTO04E ,RTO04 Output Select bits" "None,RTO04_0,RTO04_1,"
|
|
bitfld.long 0x00 6.--7. " RTO03E ,RTO03 Output Select bits" "None,RTO03_0,RTO03_1,"
|
|
bitfld.long 0x00 4.--5. " RTO02E ,RTO02 Output Select bits" "None,RTO02_0,RTO02_1,"
|
|
bitfld.long 0x00 2.--3. " RTO01E ,RTO01 Output Select bits" "None,RTO01_0,RTO01_1,"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " RTO00E ,RTO00 Output Select bits" "None,RTO00_0,RTO00_1,"
|
|
line.long 0x04 "EPFR02,Extended Pin Function Setting Register 02"
|
|
bitfld.long 0x04 29.--31. " IC13S ,IC13 Input Select bits" "IC13_0,IC13_0,IC13_1,,MFS ch.3 LSYN,ch.7 LSYN,,"
|
|
bitfld.long 0x04 26.--28. " IC12S ,IC12 Input Select bits" "IC12_0,IC12_0,IC12_1,,MFS ch.2 LSYN,MFS ch.6 LSYN,,"
|
|
bitfld.long 0x04 23.--25. " IC11S ,IC11 Input Select bits" "IC11_0,IC11_0,IC11_1,,MFS ch.1 LSYN,MFS ch.5 LSYN,,"
|
|
bitfld.long 0x04 20.--22. " IC10S ,IC10 Input Select bits" "IC10_0,IC10_0,IC10_1,,MFS ch.0 LSYN,MFS ch.4 LSYN,,"
|
|
textline " "
|
|
bitfld.long 0x04 18.--19. " FRCK1S ,FRCK1 Input Select bits" "FRCK1_0,FRCK1_0,FRCK1_1,"
|
|
bitfld.long 0x04 16.--17. " DTTI1S ,DTTIX1 Input Select bits" "DTTIX1_0,DTTIX1_0,DTTIX1_1,"
|
|
bitfld.long 0x04 13. " IGTRG0 ,IGTRG0 Input Select bit" "IGTRG0_0,IGTRG0_1"
|
|
bitfld.long 0x04 12. " DTTI1C ,DTTIX1 Function Select bit" "GPIO,DTTIF1"
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " RTO15E ,RTO15 Output Select bits" "None,RTO15_0,RTO15_1,"
|
|
bitfld.long 0x04 8.--9. " RTO14E ,RTO14 Output Select bits" "None,RTO14_0,RTO14_1,"
|
|
bitfld.long 0x04 6.--7. " RTO13E ,RTO13 Output Select bits" "None,RTO13_0,RTO13_1,"
|
|
bitfld.long 0x04 4.--5. " RTO12E ,RTO12 Output Select bits" "None,RTO12_0,RTO12_1,"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " RTO11E ,RTO11 Output Select bits" "None,RTO11_0,RTO11_1,"
|
|
bitfld.long 0x04 0.--1. " RTO10E ,RTO10 Output Select bits" "None,RTO10_0,RTO10_1,"
|
|
line.long 0x08 "EPFR03,Extended Pin Function Setting Register 03"
|
|
bitfld.long 0x08 29.--31. " IC23S ,IC23 Input Select bits" "IC23_0,IC23_0,IC23_1,,MFS ch.3 LSYN,ch.7 LSYN,,"
|
|
bitfld.long 0x08 26.--28. " IC22S ,IC22 Input Select bits" "IC22_0,IC22_0,IC22_1,,MFS ch.2 LSYN,MFS ch.6 LSYN,,"
|
|
bitfld.long 0x08 23.--25. " IC21S ,IC21 Input Select bits" "IC21_0,IC21_0,IC21_1,,MFS ch.1 LSYN,MFS ch.5 LSYN,,"
|
|
bitfld.long 0x08 20.--22. " IC20S ,IC20 Input Select bits" "IC20_0,IC20_0,IC20_1,,MFS ch.0 LSYN,MFS ch.4 LSYN,,"
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " FRCK2S ,FRCK2 Input Select bits" "FRCK2_0,FRCK2_0,FRCK2_1,"
|
|
bitfld.long 0x08 16.--17. " DTTI2S ,DTTIX2 Input Select bits" "DTTIX2_0,DTTIX2_0,DTTIX2_1,"
|
|
bitfld.long 0x08 12. " DTTI2C ,DTTIX2 Function Select bit" "GPIO,DTTIF2"
|
|
bitfld.long 0x08 10.--11. " RTO25E ,RTO25 Output Select bits" "None,RTO25_0,RTO25_1,"
|
|
textline " "
|
|
bitfld.long 0x08 8.--9. " RTO24E ,RTO24 Output Select bits" "None,RTO24_0,RTO24_1,"
|
|
bitfld.long 0x08 6.--7. " RTO23E ,RTO23 Output Select bits" "None,RTO23_0,RTO23_1,"
|
|
bitfld.long 0x08 4.--5. " RTO22E ,RTO22 Output Select bits" "None,RTO22_0,RTO22_1,"
|
|
bitfld.long 0x08 2.--3. " RTO21E ,RTO21 Output Select bits" "None,RTO21_0,RTO21_1,"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " RTO20E ,RTO20 Output Select bits" "None,RTO20_0,RTO20_1,"
|
|
endif
|
|
group.long 0x610++0x13
|
|
line.long 0x00 "EPFR04,Extended Pin Function Setting Register 04"
|
|
bitfld.long 0x00 28.--29. " TIOB3S ,TIOB3 input select bits" "TIOB3_0,TIOB3_0,TIOB3_1,TIOB3_2"
|
|
bitfld.long 0x00 26.--27. " TIOA3E ,TIOA3 output select bits" "None,TIOA3_0,TIOA3_1,TIOA3_2"
|
|
bitfld.long 0x00 24.--25. " TIOA3S ,TIOA3 input select bits" "TIOA3_0,TIOA3_0,TIOA3_1,TIOA3_2"
|
|
bitfld.long 0x00 20.--21. " TIOB2S ,TIOB2 input select bits" "TIOB2_0,TIOB2_0,TIOB2_1,TIOB2_2"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " TIOA2E ,TIOA2 output select bits" "None,TIOA2_0,TIOA2_1,TIOA2_2"
|
|
bitfld.long 0x00 12.--13. " TIOB1S ,TIOB1 input select bits" "TIOB1_0,TIOB1_0,TIOB1_1,TIOB1_2"
|
|
bitfld.long 0x00 10.--11. " TIOA1E ,TIOA1 output select bits" "None,TIOA1_0,TIOA1_1,TIOA1_2"
|
|
bitfld.long 0x00 8.--9. " TIOA1S ,TIOA1 input select bits" "TIOA1_0,TIOA1_0,TIOA1_1,TIOA1_2"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " TIOB0S ,TIOB0 input select bits" "TIOB0_0,TIOB0_0,TIOB0_1,TIOB0_2,,,SUBOUT,CR"
|
|
bitfld.long 0x00 2.--3. " TIOA0E ,TIOA0 output select bits" "BT,TIOA0_0,TIOA0_1,TIOA0_2"
|
|
line.long 0x04 "EPFR05,Extended Pin Function Setting Register 05"
|
|
bitfld.long 0x04 28.--29. " TIOB7S ,TIOB7 Input select bits" "TIOB7_0,TIOB7_0,TIOB7_1,TIOB7_2"
|
|
bitfld.long 0x04 26.--27. " TIOA7E ,TIOA7 output select bits" "None,TIOA7_0,TIOA7_1,TIOA7_2"
|
|
bitfld.long 0x04 24.--25. " TIOA7S ,TIOA7 input select bits" "TIOA7_0,TIOA7_0,TIOA7_1,TIOA7_2"
|
|
bitfld.long 0x04 20.--21. " TIOB6S ,TIOB6 input select bits" "TIOB6_0,TIOB6_0,TIOB6_1,TIOB6_2"
|
|
textline " "
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|
bitfld.long 0x04 18.--19. " TIOA6E ,TIOA6 output select bits" "None,TIOA6_0,TIOA6_1,TIOA6_2"
|
|
bitfld.long 0x04 12.--13. " TIOB5S ,TIOB5 input select bits" "TIOB5_0,TIOB5_0,TIOB5_1,TIOB5_2"
|
|
bitfld.long 0x04 10.--11. " TIOA5E ,TIOA5 output select bits" "None,TIOA5_0,TIOA5_1,TIOA5_2"
|
|
bitfld.long 0x04 8.--9. " TIOA5S ,TIOA5 input select bits" "TIOA5_0,TIOA5_0,TIOA5_1,TIOA5_2"
|
|
textline " "
|
|
bitfld.long 0x04 4.--5. " TIOB4S ,TIOB4 input select bits" "TIOB4_0,TIOB4_0,TIOB4_1,TIOB4_2"
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|
bitfld.long 0x04 2.--3. " TIOA4E ,TIOA4 output select bits" "None,TIOA4_0,TIOA4_1,TIOA4_2"
|
|
line.long 0x08 "EPFR06,Extended Pin Function Setting Register 06"
|
|
bitfld.long 0x08 30.--31. " EINT15S ,External interrupt input select bit 15" "INT15_0,INT15_0,INT15_1,INT15_2"
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|
bitfld.long 0x08 28.--29. " EINT14S ,External interrupt input select bit 14" "INT14_0,INT14_0,INT14_1,INT14_2"
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bitfld.long 0x08 26.--27. " EINT13S ,External interrupt input select bit 13" "INT13_0,INT13_0,INT13_1,INT13_2"
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bitfld.long 0x08 24.--25. " EINT12S ,External interrupt input select bit 12" "INT12_0,INT12_0,INT12_1,INT12_2"
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|
textline " "
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bitfld.long 0x08 22.--23. " EINT11S ,External interrupt input select bit 11" "INT11_0,INT11_0,INT11_1,INT11_2"
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|
bitfld.long 0x08 20.--21. " EINT10S ,External interrupt input select bit 10" "INT10_0,INT10_0,INT10_1,INT10_2"
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bitfld.long 0x08 18.--19. " EINT09S ,External interrupt input select bit 9" "INT09_0,INT09_0,INT09_1,INT09_2"
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bitfld.long 0x08 16.--17. " EINT08S ,External interrupt input select bit 8" "INT08_0,INT08_0,INT08_1,INT08_2"
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|
textline " "
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bitfld.long 0x08 14.--15. " EINT07S ,External interrupt input select bit 7" "INT07_0,INT07_0,INT07_1,INT07_2"
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bitfld.long 0x08 12.--13. " EINT06S ,External interrupt input select bit 6" "INT06_0,INT06_0,INT06_1,INT06_2"
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bitfld.long 0x08 10.--11. " EINT05S ,External interrupt input select bit 5" "INT05_0,INT05_0,INT05_1,INT05_2"
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|
bitfld.long 0x08 8.--9. " EINT04S ,External interrupt input select bit 4" "INT04_0,INT04_0,INT04_1,INT04_2"
|
|
textline " "
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|
bitfld.long 0x08 6.--7. " EINT03S ,External interrupt input select bit 3" "INT03_0,INT03_0,INT03_1,INT03_2"
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bitfld.long 0x08 4.--5. " EINT02S ,External interrupt input select bit 2" "INT02_0,INT02_0,INT02_1,INT02_2"
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bitfld.long 0x08 2.--3. " EINT01S ,External interrupt input select bit 1" "INT01_0,INT01_0,INT01_1,INT01_2"
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bitfld.long 0x08 0.--1. " EINT00S ,External interrupt input select bit 0" "INT00_0,INT00_0,INT00_1,INT00_2"
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line.long 0x0C "EPFR07,Extended Pin Function Setting Register 07"
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bitfld.long 0x0C 26.--27. " SCK3B ,SCK3 input/output select bits" "SCK3_0/None,SCK3_0,SCK3_1,SCK3_2"
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bitfld.long 0x0C 24.--25. " SOT3B ,SOT3 input/output select bits" "SOT3_0/None,SOT3_0,SOT3_1,SOT3_2"
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|
bitfld.long 0x0C 22.--23. " SIN3S ,SIN3 input select bits" "SIN3_0,SIN3_0,SIN3_1,SIN3_2"
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bitfld.long 0x0C 20.--21. " SCK2B ,SCK2 input/output select bits" "SCK2_0/None,SCK2_0,SCK2_1,SCK2_2"
|
|
textline " "
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bitfld.long 0x0C 18.--19. " SOT2B ,SOT2 input/output select bits" "SOT2_0/None,SOT2_0,SOT2_1,SOT2_2"
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|
bitfld.long 0x0C 16.--17. " SIN2S ,SIN2 input select bits" "SIN2_0,SIN2_0,SIN2_1,SIN2_2"
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|
bitfld.long 0x0C 14.--15. " SCK1B ,SCK1 input/output select bits" "SCK1_0/None,SCK1_0,SCK1_1,SCK1_2"
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|
bitfld.long 0x0C 12.--13. " SOT1B ,SOT1 input/output select bits" "SOT1_0/None,SOT1_0,SOT1_1,SOT1_2"
|
|
textline " "
|
|
bitfld.long 0x0C 10.--11. " SIN1S ,SIN1 input select bits" "SIN1_0,SIN1_0,SIN1_1,SIN1_2"
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|
bitfld.long 0x0C 8.--9. " SCK0B ,SCK0 input/output select bits" "SCK0_0/None,SCK0_0,SCK0_1,SCK0_2"
|
|
bitfld.long 0x0C 6.--7. " SOT0B ,SOT0 input/output select bits" "SOT0_0/None,SOT0_0,SOT0_1,SOT0_2"
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|
bitfld.long 0x0C 4.--5. " SIN0S ,SIN0 input select bits" "SIN0_0,SIN0_0,SIN0_1,SIN0_2"
|
|
line.long 0x10 "EPFR08,Extended Pin Function Setting Register 08"
|
|
bitfld.long 0x10 26.--27. " SCK7B ,SCK7 input/output select bits" "SCK7_0/None,SCK7_0,SCK7_1,SCK7_2"
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|
bitfld.long 0x10 24.--25. " SOT7B ,SOT7 input/output select bits" "SOT7_0/None,SOT7_0,SOT7_1,SOT7_2"
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|
bitfld.long 0x10 22.--23. " SIN7S ,SIN7 input select bits" "SIN7_0,SIN7_0,SIN7_1,SIN7_2"
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|
bitfld.long 0x10 20.--21. " SCK6B ,SCK6 input/output select bits" "SCK6_0/None,SCK6_0,SCK6_1,SCK6_2"
|
|
textline " "
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bitfld.long 0x10 18.--19. " SOT6B ,SOT6 input/output select bits" "SOT6_0/None,SOT6_0,SOT6_1,SOT6_2"
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bitfld.long 0x10 16.--17. " SIN6S ,SIN6 input select bits" "SIN6_0,SIN6_0,SIN6_1,SIN6_2"
|
|
bitfld.long 0x10 14.--15. " SCK5B ,SCK5 input/output select bits" "SCK5_0/None,SCK5_0,SCK5_1,SCK5_2"
|
|
bitfld.long 0x10 12.--13. " SOT5B ,SOT5 input/output select bits" "SOT5_0/None,SOT5_0,SOT5_1,SOT5_2"
|
|
textline " "
|
|
bitfld.long 0x10 10.--11. " SIN5S ,SIN5 input select bits" "SIN5_0,SIN5_0,SIN5_1,SIN5_2"
|
|
bitfld.long 0x10 8.--9. " SCK4B ,SCK4 input/output select bits" "SCK4_0/None,SCK4_0,SCK4_1,SCK4_2"
|
|
bitfld.long 0x10 6.--7. " SOT4B ,SOT4 input/output select bits" "SOT4_0/None,SOT4_0,SOT4_1,SOT4_2"
|
|
bitfld.long 0x10 4.--5. " SIN4S ,SIN4 input select bits" "SIN4_0,SIN4_0,SIN4_1,SIN4_2"
|
|
textline " "
|
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bitfld.long 0x10 2.--3. " CTS4S ,CTS4 input select bits" "CTS4_0,CTS4_0,CTS4_1,CTS4_2"
|
|
bitfld.long 0x10 0.--1. " RTS4E ,RTS4 output select bits" "None,RTS4_0,RTS4_1,RTS4_2"
|
|
sif cpuis("S6E1C*")
|
|
group.long 0x624++0x03
|
|
line.long 0x00 "EPFR09,Extended Pin Function Setting Register 09"
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|
bitfld.long 0x00 20.--23. " ADTRG2S ,ADTRG2 Input Select bits (ADC unit 2)" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..."
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bitfld.long 0x00 16.--19. " ADTRG1S ,ADTRG1 Input Select bits (ADC unit 1)" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..."
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bitfld.long 0x00 12.--15. " ADTRG0S ,ADTRG0 Input Select bits (ADC unit 0)" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..."
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bitfld.long 0x00 10.--11. " QZIN1S ,QZIN1S Input Select bits" "ZIN1_0,ZIN1_0,ZIN1_1,ZIN1_2"
|
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textline " "
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bitfld.long 0x00 8.--9. " QBIN1S ,QBIN1S Input Select bits" "BIN1_0,BIN1_0,BIN1_1,BIN1_2"
|
|
bitfld.long 0x00 6.--7. " QAIN1S ,QAIN1S Input Select bits" "AIN1_0,AIN1_0,AIN1_1,AIN1_2"
|
|
bitfld.long 0x00 4.--5. " QZIN0S ,QZIN0S Input Select bits" "ZIN0_0,ZIN0_0,ZIN0_1,ZIN0_2"
|
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bitfld.long 0x00 2.--3. " QBIN0S ,QBIN0S Input Select bits" "BIN0_0,BIN0_0,BIN0_1,BIN0_2"
|
|
textline " "
|
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bitfld.long 0x00 0.--1. " QAIN0S ,QAIN0S Input Select bits" "AIN0_0,AIN0_0,AIN0_1,AIN0_2"
|
|
else
|
|
if ((per.l((ad:0x40033000+0x654))&0x07)==0x07)
|
|
group.long 0x624++0x03
|
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line.long 0x00 "EPFR09,Extended Pin Function Setting Register 09"
|
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bitfld.long 0x00 30.--31. " CTX1E ,CTX1E Output Select bits" "None,TX1_0,TX1_1,TX1_2"
|
|
bitfld.long 0x00 28.--29. " CRX1S ,CRX1S Input Select bits" "RX1_0,RX1_0,RX1_1,RX1_2"
|
|
bitfld.long 0x00 26.--27. " CTX0E ,CTX0E Output Select bits" "None,TX0_0,TX0_1,TX0_2"
|
|
bitfld.long 0x00 24.--25. " CRX0S ,CRX0S Input Select bits" "RX0_0,RX0_0,RX0_1,RX0_2"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ADTRG2S ,ADTRG2 Input Select bits (ADC unit 2)" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..."
|
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bitfld.long 0x00 16.--19. " ADTRG1S ,ADTRG1 Input Select bits (ADC unit 1)" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..."
|
|
bitfld.long 0x00 12.--15. " ADTRG0S ,ADTRG0 Input Select bits (ADC unit 0)" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..."
|
|
bitfld.long 0x00 10.--11. " QZIN1S ,QZIN1S Input Select bits" "ZIN1_0,ZIN1_0,ZIN1_1,ZIN1_2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " QBIN1S ,QBIN1S Input Select bits" "BIN1_0,BIN1_0,BIN1_1,BIN1_2"
|
|
bitfld.long 0x00 6.--7. " QAIN1S ,QAIN1S Input Select bits" "AIN1_0,AIN1_0,AIN1_1,AIN1_2"
|
|
bitfld.long 0x00 4.--5. " QZIN0S ,QZIN0S Input Select bits" "ZIN0_3,?..."
|
|
bitfld.long 0x00 2.--3. " QBIN0S ,QBIN0S Input Select bits" "BIN0_3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " QAIN0S ,QAIN0S Input Select bits" "AIN0_3,?..."
|
|
elif ((per.l((ad:0x40033000+0x654))&0x6)==0x6)
|
|
group.long 0x624++0x03
|
|
line.long 0x00 "EPFR09,Extended Pin Function Setting Register 09"
|
|
bitfld.long 0x00 30.--31. " CTX1E ,CTX1E Output Select bits" "None,TX1_0,TX1_1,TX1_2"
|
|
bitfld.long 0x00 28.--29. " CRX1S ,CRX1S Input Select bits" "RX1_0,RX1_0,RX1_1,RX1_2"
|
|
bitfld.long 0x00 26.--27. " CTX0E ,CTX0E Output Select bits" "None,TX0_0,TX0_1,TX0_2"
|
|
bitfld.long 0x00 24.--25. " CRX0S ,CRX0S Input Select bits" "RX0_0,RX0_0,RX0_1,RX0_2"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ADTRG2S ,ADTRG2 Input Select bits (ADC unit 2)" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..."
|
|
bitfld.long 0x00 16.--19. " ADTRG1S ,ADTRG1 Input Select bits (ADC unit 1)" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..."
|
|
bitfld.long 0x00 12.--15. " ADTRG0S ,ADTRG0 Input Select bits (ADC unit 0)" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..."
|
|
bitfld.long 0x00 10.--11. " QZIN1S ,QZIN1S Input Select bits" "ZIN1_0,ZIN1_0,ZIN1_1,ZIN1_2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " QBIN1S ,QBIN1S Input Select bits" "BIN1_0,BIN1_0,BIN1_1,BIN1_2"
|
|
bitfld.long 0x00 6.--7. " QAIN1S ,QAIN1S Input Select bits" "AIN1_0,AIN1_0,AIN1_1,AIN1_2"
|
|
bitfld.long 0x00 4.--5. " QZIN0S ,QZIN0S Input Select bits" "ZIN0_3,?..."
|
|
bitfld.long 0x00 2.--3. " QBIN0S ,QBIN0S Input Select bits" "BIN0_3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " QAIN0S ,QAIN0S Input Select bits" "AIN0_0,AIN0_0,AIN0_1,AIN0_2"
|
|
elif ((per.l((ad:0x40033000+0x654))&0x5)==0x5)
|
|
group.long 0x624++0x03
|
|
line.long 0x00 "EPFR09,Extended Pin Function Setting Register 09"
|
|
bitfld.long 0x00 30.--31. " CTX1E ,CTX1E Output Select bits" "None,TX1_0,TX1_1,TX1_2"
|
|
bitfld.long 0x00 28.--29. " CRX1S ,CRX1S Input Select bits" "RX1_0,RX1_0,RX1_1,RX1_2"
|
|
bitfld.long 0x00 26.--27. " CTX0E ,CTX0E Output Select bits" "None,TX0_0,TX0_1,TX0_2"
|
|
bitfld.long 0x00 24.--25. " CRX0S ,CRX0S Input Select bits" "RX0_0,RX0_0,RX0_1,RX0_2"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ADTRG2S ,ADTRG2 Input Select bits (ADC unit 2)" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..."
|
|
bitfld.long 0x00 16.--19. " ADTRG1S ,ADTRG1 Input Select bits (ADC unit 1)" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..."
|
|
bitfld.long 0x00 12.--15. " ADTRG0S ,ADTRG0 Input Select bits (ADC unit 0)" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..."
|
|
bitfld.long 0x00 10.--11. " QZIN1S ,QZIN1S Input Select bits" "ZIN1_0,ZIN1_0,ZIN1_1,ZIN1_2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " QBIN1S ,QBIN1S Input Select bits" "BIN1_0,BIN1_0,BIN1_1,BIN1_2"
|
|
bitfld.long 0x00 6.--7. " QAIN1S ,QAIN1S Input Select bits" "AIN1_0,AIN1_0,AIN1_1,AIN1_2"
|
|
bitfld.long 0x00 4.--5. " QZIN0S ,QZIN0S Input Select bits" "ZIN0_3,?..."
|
|
bitfld.long 0x00 2.--3. " QBIN0S ,QBIN0S Input Select bits" "BIN0_0,BIN0_0,BIN0_1,BIN0_2"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " QAIN0S ,QAIN0S Input Select bits" "AIN0_3,?..."
|
|
elif ((per.l((ad:0x40033000+0x654))&0x4)==0x4)
|
|
group.long 0x624++0x03
|
|
line.long 0x00 "EPFR09,Extended Pin Function Setting Register 09"
|
|
bitfld.long 0x00 30.--31. " CTX1E ,CTX1E Output Select bits" "None,TX1_0,TX1_1,TX1_2"
|
|
bitfld.long 0x00 28.--29. " CRX1S ,CRX1S Input Select bits" "RX1_0,RX1_0,RX1_1,RX1_2"
|
|
bitfld.long 0x00 26.--27. " CTX0E ,CTX0E Output Select bits" "None,TX0_0,TX0_1,TX0_2"
|
|
bitfld.long 0x00 24.--25. " CRX0S ,CRX0S Input Select bits" "RX0_0,RX0_0,RX0_1,RX0_2"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ADTRG2S ,ADTRG2 Input Select bits (ADC unit 2)" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..."
|
|
bitfld.long 0x00 16.--19. " ADTRG1S ,ADTRG1 Input Select bits (ADC unit 1)" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..."
|
|
bitfld.long 0x00 12.--15. " ADTRG0S ,ADTRG0 Input Select bits (ADC unit 0)" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..."
|
|
bitfld.long 0x00 10.--11. " QZIN1S ,QZIN1S Input Select bits" "ZIN1_0,ZIN1_0,ZIN1_1,ZIN1_2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " QBIN1S ,QBIN1S Input Select bits" "BIN1_0,BIN1_0,BIN1_1,BIN1_2"
|
|
bitfld.long 0x00 6.--7. " QAIN1S ,QAIN1S Input Select bits" "AIN1_0,AIN1_0,AIN1_1,AIN1_2"
|
|
bitfld.long 0x00 4.--5. " QZIN0S ,QZIN0S Input Select bits" "ZIN0_3,?..."
|
|
bitfld.long 0x00 2.--3. " QBIN0S ,QBIN0S Input Select bits" "BIN0_0,BIN0_0,BIN0_1,BIN0_2"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " QAIN0S ,QAIN0S Input Select bits" "AIN0_0,AIN0_0,AIN0_1,AIN0_2"
|
|
elif ((per.l((ad:0x40033000+0x654))&0x3)==0x3)
|
|
group.long 0x624++0x03
|
|
line.long 0x00 "EPFR09,Extended Pin Function Setting Register 09"
|
|
bitfld.long 0x00 30.--31. " CTX1E ,CTX1E Output Select bits" "None,TX1_0,TX1_1,TX1_2"
|
|
bitfld.long 0x00 28.--29. " CRX1S ,CRX1S Input Select bits" "RX1_0,RX1_0,RX1_1,RX1_2"
|
|
bitfld.long 0x00 26.--27. " CTX0E ,CTX0E Output Select bits" "None,TX0_0,TX0_1,TX0_2"
|
|
bitfld.long 0x00 24.--25. " CRX0S ,CRX0S Input Select bits" "RX0_0,RX0_0,RX0_1,RX0_2"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ADTRG2S ,ADTRG2 Input Select bits (ADC unit 2)" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..."
|
|
bitfld.long 0x00 16.--19. " ADTRG1S ,ADTRG1 Input Select bits (ADC unit 1)" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..."
|
|
bitfld.long 0x00 12.--15. " ADTRG0S ,ADTRG0 Input Select bits (ADC unit 0)" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..."
|
|
bitfld.long 0x00 10.--11. " QZIN1S ,QZIN1S Input Select bits" "ZIN1_0,ZIN1_0,ZIN1_1,ZIN1_2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " QBIN1S ,QBIN1S Input Select bits" "BIN1_0,BIN1_0,BIN1_1,BIN1_2"
|
|
bitfld.long 0x00 6.--7. " QAIN1S ,QAIN1S Input Select bits" "AIN1_0,AIN1_0,AIN1_1,AIN1_2"
|
|
bitfld.long 0x00 4.--5. " QZIN0S ,QZIN0S Input Select bits" "ZIN0_0,ZIN0_0,ZIN0_1,ZIN0_2"
|
|
bitfld.long 0x00 2.--3. " QBIN0S ,QBIN0S Input Select bits" "BIN0_3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " QAIN0S ,QAIN0S Input Select bits" "AIN0_3,?..."
|
|
elif ((per.l((ad:0x40033000+0x654))&0x2)==0x2)
|
|
group.long 0x624++0x03
|
|
line.long 0x00 "EPFR09,Extended Pin Function Setting Register 09"
|
|
bitfld.long 0x00 30.--31. " CTX1E ,CTX1E Output Select bits" "None,TX1_0,TX1_1,TX1_2"
|
|
bitfld.long 0x00 28.--29. " CRX1S ,CRX1S Input Select bits" "RX1_0,RX1_0,RX1_1,RX1_2"
|
|
bitfld.long 0x00 26.--27. " CTX0E ,CTX0E Output Select bits" "None,TX0_0,TX0_1,TX0_2"
|
|
bitfld.long 0x00 24.--25. " CRX0S ,CRX0S Input Select bits" "RX0_0,RX0_0,RX0_1,RX0_2"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ADTRG2S ,ADTRG2 Input Select bits (ADC unit 2)" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..."
|
|
bitfld.long 0x00 16.--19. " ADTRG1S ,ADTRG1 Input Select bits (ADC unit 1)" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..."
|
|
bitfld.long 0x00 12.--15. " ADTRG0S ,ADTRG0 Input Select bits (ADC unit 0)" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..."
|
|
bitfld.long 0x00 10.--11. " QZIN1S ,QZIN1S Input Select bits" "ZIN1_0,ZIN1_0,ZIN1_1,ZIN1_2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " QBIN1S ,QBIN1S Input Select bits" "BIN1_0,BIN1_0,BIN1_1,BIN1_2"
|
|
bitfld.long 0x00 6.--7. " QAIN1S ,QAIN1S Input Select bits" "AIN1_0,AIN1_0,AIN1_1,AIN1_2"
|
|
bitfld.long 0x00 4.--5. " QZIN0S ,QZIN0S Input Select bits" "ZIN0_0,ZIN0_0,ZIN0_1,ZIN0_2"
|
|
bitfld.long 0x00 2.--3. " QBIN0S ,QBIN0S Input Select bits" "BIN0_3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " QAIN0S ,QAIN0S Input Select bits" "AIN0_0,AIN0_0,AIN0_1,AIN0_2"
|
|
elif ((per.l((ad:0x40033000+0x654))&0x1)==0x1)
|
|
group.long 0x624++0x03
|
|
line.long 0x00 "EPFR09,Extended Pin Function Setting Register 09"
|
|
bitfld.long 0x00 30.--31. " CTX1E ,CTX1E Output Select bits" "None,TX1_0,TX1_1,TX1_2"
|
|
bitfld.long 0x00 28.--29. " CRX1S ,CRX1S Input Select bits" "RX1_0,RX1_0,RX1_1,RX1_2"
|
|
bitfld.long 0x00 26.--27. " CTX0E ,CTX0E Output Select bits" "None,TX0_0,TX0_1,TX0_2"
|
|
bitfld.long 0x00 24.--25. " CRX0S ,CRX0S Input Select bits" "RX0_0,RX0_0,RX0_1,RX0_2"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ADTRG2S ,ADTRG2 Input Select bits (ADC unit 2)" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..."
|
|
bitfld.long 0x00 16.--19. " ADTRG1S ,ADTRG1 Input Select bits (ADC unit 1)" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..."
|
|
bitfld.long 0x00 12.--15. " ADTRG0S ,ADTRG0 Input Select bits (ADC unit 0)" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..."
|
|
bitfld.long 0x00 10.--11. " QZIN1S ,QZIN1S Input Select bits" "ZIN1_0,ZIN1_0,ZIN1_1,ZIN1_2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " QBIN1S ,QBIN1S Input Select bits" "BIN1_0,BIN1_0,BIN1_1,BIN1_2"
|
|
bitfld.long 0x00 6.--7. " QAIN1S ,QAIN1S Input Select bits" "AIN1_0,AIN1_0,AIN1_1,AIN1_2"
|
|
bitfld.long 0x00 4.--5. " QZIN0S ,QZIN0S Input Select bits" "ZIN0_0,ZIN0_0,ZIN0_1,ZIN0_2"
|
|
bitfld.long 0x00 2.--3. " QBIN0S ,QBIN0S Input Select bits" "BIN0_0,BIN0_0,BIN0_1,BIN0_2"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " QAIN0S ,QAIN0S Input Select bits" "AIN0_3,?..."
|
|
else
|
|
group.long 0x624++0x03
|
|
line.long 0x00 "EPFR09,Extended Pin Function Setting Register 09"
|
|
bitfld.long 0x00 30.--31. " CTX1E ,CTX1E Output Select bits" "None,TX1_0,TX1_1,TX1_2"
|
|
bitfld.long 0x00 28.--29. " CRX1S ,CRX1S Input Select bits" "RX1_0,RX1_0,RX1_1,RX1_2"
|
|
bitfld.long 0x00 26.--27. " CTX0E ,CTX0E Output Select bits" "None,TX0_0,TX0_1,TX0_2"
|
|
bitfld.long 0x00 24.--25. " CRX0S ,CRX0S Input Select bits" "RX0_0,RX0_0,RX0_1,RX0_2"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ADTRG2S ,ADTRG2 Input Select bits (ADC unit 2)" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..."
|
|
bitfld.long 0x00 16.--19. " ADTRG1S ,ADTRG1 Input Select bits (ADC unit 1)" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..."
|
|
bitfld.long 0x00 12.--15. " ADTRG0S ,ADTRG0 Input Select bits (ADC unit 0)" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..."
|
|
bitfld.long 0x00 10.--11. " QZIN1S ,QZIN1S Input Select bits" "ZIN1_0,ZIN1_0,ZIN1_1,ZIN1_2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " QBIN1S ,QBIN1S Input Select bits" "BIN1_0,BIN1_0,BIN1_1,BIN1_2"
|
|
bitfld.long 0x00 6.--7. " QAIN1S ,QAIN1S Input Select bits" "AIN1_0,AIN1_0,AIN1_1,AIN1_2"
|
|
bitfld.long 0x00 4.--5. " QZIN0S ,QZIN0S Input Select bits" "ZIN0_0,ZIN0_0,ZIN0_1,ZIN0_2"
|
|
bitfld.long 0x00 2.--3. " QBIN0S ,QBIN0S Input Select bits" "BIN0_0,BIN0_0,BIN0_1,BIN0_2"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " QAIN0S ,QAIN0S Input Select bits" "AIN0_0,AIN0_0,AIN0_1,AIN0_2"
|
|
endif
|
|
endif
|
|
sif !cpuis("S6E1C*")
|
|
group.long 0x630++0x1B
|
|
line.long 0x00 "EPFR12,Extended Pin Function Setting Register 12"
|
|
bitfld.long 0x00 28.--29. " TIOB11S ,TIOB11 Input Select bits" "TIOB11_0,TIOB11_0,TIOB11_1,TIOB11_2"
|
|
bitfld.long 0x00 26.--27. " TIOA11E ,TIOA11 Output Select bits" "None,TIOA11_0,TIOA11_1,TIOA11_2"
|
|
bitfld.long 0x00 24.--25. " TIOA11S ,TIOA11 Input Select bits" "TIOA11_0,TIOA11_0,TIOA11_1,TIOA11_2"
|
|
bitfld.long 0x00 20.--21. " TIOB10S ,TIOB10 Input Select bits" "TIOB10_0,TIOB10_0,TIOB10_1,TIOB10_2"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " TIOA10E ,TIOA10 Output Select bits" "None,TIOA10_0,TIOA10_1,TIOA10_2"
|
|
bitfld.long 0x00 12.--13. " TIOB9S ,TIOB9 Input Select bits" "TIOB9_0,TIOB9_0,TIOB9_1,TIOB9_2"
|
|
bitfld.long 0x00 10.--11. " TIOA9E ,TIOA9 Output Select bits" "None,TIOA9_0,TIOA9_1,TIOA9_2"
|
|
bitfld.long 0x00 8.--9. " TIOA9S ,TIOA9 Input Select bits" "TIOA9_0,TIOA9_0,TIOA9_1,TIOA9_2"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " TIOB8S ,TIOB8 Input Select bits" "TIOB8_0,TIOB8_0,TIOB8_1,TIOB8_2"
|
|
bitfld.long 0x00 2.--3. " TIOA8E ,TIOA8 Output Select bits" "None,TIOA8_0,TIOA8_1,TIOA8_2"
|
|
line.long 0x04 "EPFR13,Extended Pin Function Setting Register 13"
|
|
bitfld.long 0x04 28.--29. " TIOB15S ,TIOB15 Input Select bits" "TIOB15_0,TIOB15_0,TIOB15_1,TIOB15_2"
|
|
bitfld.long 0x04 26.--27. " TIOA15E ,TIOA15 Output Select bits" "None,TIOA15_0,TIOA15_1,TIOA15_2"
|
|
bitfld.long 0x04 24.--25. " TIOA15S ,TIOA15 Input Select bits" "TIOA15_0,TIOA15_0,TIOA15_1,TIOA15_2"
|
|
bitfld.long 0x04 20.--21. " TIOB14S ,TIOB14 Input Select bits" "TIOB14_0,TIOB14_0,TIOB14_1,TIOB10_2"
|
|
textline " "
|
|
bitfld.long 0x04 18.--19. " TIOA14E ,TIOA14 Output Select bits" "None,TIOA14_0,TIOA14_1,TIOA14_2"
|
|
bitfld.long 0x04 12.--13. " TIOB13S ,TIOB13 Input Select bits" "TIOB13_0,TIOB13_0,TIOB13_1,TIOB13_2"
|
|
bitfld.long 0x04 10.--11. " TIOA13E ,TIOA13 Output Select bits" "None,TIOA13_0,TIOA13_1,TIOA13_2"
|
|
bitfld.long 0x04 8.--9. " TIOA13S ,TIOA13 Input Select bits" "TIOA13_0,TIOA13_0,TIOA13_1,TIOA13_2"
|
|
textline " "
|
|
bitfld.long 0x04 4.--5. " TIOB12S ,TIO12 Input Select bits" "TIOB12_0,TIOB12_0,TIOB12_1,TIOB12_2"
|
|
bitfld.long 0x04 2.--3. " TIOA12E ,TIOA12 Output Select bits" "None,TIOA12_0,TIOA12_1,TIOA12_2"
|
|
line.long 0x08 "EPFR14,Extended Pin Function Setting Register 14"
|
|
bitfld.long 0x08 4.--5. " QZIN2S ,QPRC-ch.2 ZIN Input Pin bits" "ZIN2_0,ZIN2_0,ZIN2_1,ZIN2_2"
|
|
bitfld.long 0x08 2.--3. " QBIN2S ,QPRC-ch.2 BIN Input Pin bits" "BIN2_0,BIN2_0,BIN2_1,BIN2_2"
|
|
bitfld.long 0x08 0.--1. " QAIN2S ,QPRC-ch.2 AIN Input Pin bits" "AIN2_0,AIN2_0,AIN2_1,AIN2_2"
|
|
line.long 0x0C "EPFR15,Extended Pin Function Setting Register 15"
|
|
bitfld.long 0x0C 30.--31. " EINT31S ,External Interrupt Input Select bits" "INT31_0,INT31_0,INT31_1,INT31_2"
|
|
bitfld.long 0x0C 28.--29. " EINT30S ,External Interrupt Input Select bits" "INT30_0,INT30_0,INT30_1,INT30_2"
|
|
bitfld.long 0x0C 26.--27. " EINT29S ,External Interrupt Input Select bits" "INT29_0,INT29_0,INT29_1,INT29_2"
|
|
bitfld.long 0x0C 24.--25. " EINT28S ,External Interrupt Input Select bits" "INT28_0,INT28_0,INT28_1,INT28_2"
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " EINT27S ,External Interrupt Input Select bits" "INT27_0,INT27_0,INT27_1,INT27_2"
|
|
bitfld.long 0x0C 20.--21. " EINT26S ,External Interrupt Input Select bits" "INT26_0,INT26_0,INT26_1,INT26_2"
|
|
bitfld.long 0x0C 18.--19. " EINT25S ,External Interrupt Input Select bits" "INT25_0,INT25_0,INT25_1,INT25_2"
|
|
bitfld.long 0x0C 16.--17. " EINT24S ,External Interrupt Input Select bits" "INT24_0,INT24_0,INT24_1,INT24_2"
|
|
textline " "
|
|
bitfld.long 0x0C 14.--15. " EINT23S ,External Interrupt Input Select bits" "INT23_0,INT23_0,INT23_1,INT23_2"
|
|
bitfld.long 0x0C 12.--13. " EINT22S ,External Interrupt Input Select bits" "INT22_0,INT22_0,INT22_1,INT22_2"
|
|
bitfld.long 0x0C 10.--11. " EINT21S ,External Interrupt Input Select bits" "INT21_0,INT21_0,INT21_1,INT21_2"
|
|
bitfld.long 0x0C 8.--9. " EINT20S ,External Interrupt Input Select bits" "INT20_0,INT20_0,INT20_1,INT20_2"
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " EINT19S ,External Interrupt Input Select bits" "INT19_0,INT19_0,INT19_1,INT19_2"
|
|
bitfld.long 0x0C 4.--5. " EINT18S ,External Interrupt Input Select bits" "INT18_0,INT18_0,INT18_1,INT18_2"
|
|
bitfld.long 0x0C 2.--3. " EINT17S ,External Interrupt Input Select bits" "INT17_0,INT17_0,INT17_1,INT17_2"
|
|
bitfld.long 0x0C 0.--1. " EINT16S ,External Interrupt Input Select bits" "INT16_0,INT16_0,INT16_1,INT16_2"
|
|
line.long 0x10 "EPFR16,Extended Pin Function Setting Register 16"
|
|
bitfld.long 0x10 26.--27. " SCK11B ,SCK11 Input/Output Select bits" "SCK11_0/None,SCK11_0,SCK11_1,SCK11_2"
|
|
bitfld.long 0x10 24.--25. " SOT11B ,SOT11 Input/Output Select bits" "SOT11_0/None,SOT11_0,SOT11_1,SOT11_2"
|
|
bitfld.long 0x10 22.--23. " SIN11S ,SIN11 Input Select bits" "SIN11_0,SIN11_0,SIN11_1,SIN11_2"
|
|
bitfld.long 0x10 20.--21. " SCK10B ,SCK10 Input/Output Select bits" "SCK10_0/None,SCK10_0,SCK10_1,SCK10_2"
|
|
textline " "
|
|
bitfld.long 0x10 18.--19. " SOT10B ,SOT10 Input/Output Select bits" "SOT10_0/None,SOT10_0,SOT10_1,SOT10_2"
|
|
bitfld.long 0x10 16.--17. " SIN10S ,SIN10 Input Select bits" "SIN10_0,SIN10_0,SIN10_1,SIN10_2"
|
|
bitfld.long 0x10 14.--15. " SCK9B ,SCK9 Input/Output Select bits" "SCK9_0/None,SCK9_0,SCK9_1,SCK9_2"
|
|
bitfld.long 0x10 12.--13. " SOT9B ,SOT9 Input/Output Select bits" "SOT9_0/None,SOT9_0,SOT9_1,SOT9_2"
|
|
textline " "
|
|
bitfld.long 0x10 10.--11. " SIN9S ,SIN9 Input Select bits" "SIN9_0,SIN9_0,SIN9_1,SIN9_2"
|
|
bitfld.long 0x10 8.--9. " SCK8B ,SCK8 Input/Output Select bits" "SCK8_0/None,SCK8_0,SCK8_1,SCK8_2"
|
|
bitfld.long 0x10 6.--7. " SOT8B ,SOT8 Input/Output Select bits" "SOT8_0/None,SOT8_0,SOT8_1,SOT8_2"
|
|
bitfld.long 0x10 4.--5. " SIN8S ,SIN8 Input Select bits" "SIN8_0,SIN8_0,SIN8_1,SIN8_2"
|
|
line.long 0x14 "EPFR17,Extended Pin Function Setting Register 17"
|
|
bitfld.long 0x14 26.--27. " SCK15B ,SCK15 Input/Output Select bits" "SCK15_0/None,SCK15_0,SCK15_1,SCK15_2"
|
|
bitfld.long 0x14 24.--25. " SOT15B ,SOT15 Input/Output Select bits" "SOT15_0/None,SOT15_0,SOT15_1,SOT15_2"
|
|
bitfld.long 0x14 22.--23. " SIN15S ,SIN15 Input Select bits" "SIN15_0,SIN15_0,SIN15_1,SIN15_2"
|
|
bitfld.long 0x14 20.--21. " SCK14B ,SCK14 Input/Output Select bits" "SCK14_0/None,SCK14_0,SCK14_1,SCK14_2"
|
|
textline " "
|
|
bitfld.long 0x14 18.--19. " SOT14B ,SOT14 Input/Output Select bits" "SOT14_0/None,SOT14_0,SOT14_1,SOT14_2"
|
|
bitfld.long 0x14 16.--17. " SIN14S ,SIN14 Input Select bits" "SIN14_0,SIN14_0,SIN14_1,SIN14_2"
|
|
bitfld.long 0x14 14.--15. " SCK13B ,SCK13 Input/Output Select bits" "SCK13_0/None,SCK13_0,SCK13_1,SCK13_2"
|
|
bitfld.long 0x14 12.--13. " SOT13B ,SOT13 Input/Output Select bits" "SOT13_0/None,SOT13_0,SOT13_1,SOT13_2"
|
|
textline " "
|
|
bitfld.long 0x14 10.--11. " SIN13S ,SIN13 Input Select bits" "SIN13_0,SIN13_0,SIN13_1,SIN13_2"
|
|
bitfld.long 0x14 8.--9. " SCK12B ,SCK12 Input/Output Select bits" "SCK12_0/None,SCK12_0,SCK12_1,SCK12_2"
|
|
bitfld.long 0x14 6.--7. " SOT12B ,SOT12 Input/Output Select bits" "SOT12_0/None,SOT12_0,SOT12_1,SOT12_2"
|
|
bitfld.long 0x14 4.--5. " SIN12S ,SIN12 Input Select bits" "SIN12_0,SIN12_0,SIN12_1,SIN12_2"
|
|
line.long 0x18 "EPFR18,Extended Pin Function Setting Register 18"
|
|
bitfld.long 0x18 2.--3. " CECR1B ,CEC1 input/output selection bits" "None,CEC1_0,CEC1_1,"
|
|
bitfld.long 0x18 0.--1. " CECR0B ,CEC0 input/output selection bits" "None,CEC0_0,CEC0_1,"
|
|
group.long 0x654++0x03
|
|
line.long 0x00 "EPFR21,Extended Pin Function Setting Register 21"
|
|
bitfld.long 0x00 2. " QZIN0S ,QPRC-ch.0 ZIN input pin bits" "Low,High"
|
|
bitfld.long 0x00 1. " QBIN0S ,QPRC-ch.0 BIN input pin bits" "Low,High"
|
|
bitfld.long 0x00 0. " QAIN0S ,QPRC-ch.0 AIN input pin bits" "Low,High"
|
|
endif
|
|
group.long 0x658++0x03
|
|
line.long 0x00 "EPFR22,Extended Pin Function Setting Register 22"
|
|
bitfld.long 0x00 14.--15. " SCS31E ,SCS31 output select bits" "None,SCS31_0,SCS31_1,SCS31_2"
|
|
bitfld.long 0x00 12.--13. " SCS30B ,SCS30 input/output select bits" "SCS30_0/None,SCS30_0,SCS30_1,SCS30_2"
|
|
bitfld.long 0x00 6.--7. " SCS11E ,SCS11 output select bits" "None,SCS11_0,SCS11_1,SCS11_2"
|
|
bitfld.long 0x00 4.--5. " SCS10B ,SCS10 input/output select bits" "SCS10_0/None,SCS10_0,SCS10_1,SCS10_2"
|
|
sif cpuis("S6E1C*")
|
|
group.long 0x65C++0x03
|
|
line.long 0x00 "EPFR23,Extended Pin Function Setting Register 23"
|
|
bitfld.long 0x00 14.--15. " SCS73E ,SCS73 output select bits" "None,SCS73_0,SCS73_1,SCS73_2"
|
|
bitfld.long 0x00 12.--13. " SCS72E ,SCS72 output select bits" "None,SCS72_0,SCS72_1,SCS72_2"
|
|
bitfld.long 0x00 10.--11. " SCS71E ,SCS71 output select bits" "None,SCS71_0,SCS71_1,SCS71_2"
|
|
bitfld.long 0x00 8.--9. " SCS70B ,SCS70 output select bits" "SCS70_0/None,SCS70_0,SCS70_1,SCS70_2"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " SCS63E ,SCS63 output select bits" "None,SCS63_0,SCS63_1,SCS63_2"
|
|
bitfld.long 0x00 4.--5. " SCS62E ,SCS62 output select bits" "None,SCS62_0,SCS62_1,SCS62_2"
|
|
bitfld.long 0x00 2.--3. " SCS61E ,SCS61 output select bits" "None,SCS61_0,SCS61_1,SCS61_2"
|
|
bitfld.long 0x00 0.--1. " SCS60B ,SCS60 output select bits" "SCS60_0/None,SCS60_0,SCS60_1,SCS60_2"
|
|
group.long 0x67C++0x03
|
|
line.long 0x00 "EPFR31,Extended Pin Function Setting Register 31"
|
|
bitfld.long 0x00 26.--27. " SI2CSDA6B ,I2C slave ch.6 SDA pin select bit" "SI2CSDA6_0/None,SI2CSDA6_0,SI2CSDA6_1,SI2CSDA6_2"
|
|
bitfld.long 0x00 24.--25. " SI2CSCL6B ,I2C slave ch.6 SCL pin select bits" "SI2CSCL6_0/None,SI2CSCL6_0,SI2CSCL6_1,SI2CSCL6_2"
|
|
group.long 0x684++0x03
|
|
line.long 0x00 "EPFR33,Extended Pin Function Setting Register 33"
|
|
bitfld.long 0x00 26.--27. " CLK1E ,CLK1 output select bits" "None,CLK1_0,CLK1_1,?..."
|
|
bitfld.long 0x00 24.--25. " VCC1E ,VCC1 output select bits" "None,VCC1_0,VCC1_1,?..."
|
|
bitfld.long 0x00 22.--23. " VPEN1E ,VCC1 output select bits" "None,VPEN1_0,VPEN1_1,?..."
|
|
bitfld.long 0x00 20.--21. " RST1E ,VCC1 output select bits" "None,RST1_0,RST1_1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " DATA1B ,VDATA1 bus select bits" "DATA1_0,DATA1_0,DATA1_1,?..."
|
|
bitfld.long 0x00 16.--17. " CIN1S ,CIN1 input select bits" "CIN1_0,CIN1_0,CIN1_1,None"
|
|
bitfld.long 0x00 10.--11. " CLK0E ,CLK0 output select bits" "None,CLK0_0,CLK0_1,?..."
|
|
bitfld.long 0x00 8.--9. " VCC0E ,VCC0 output select bits" "None,VCC0_0,VCC0_1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " VPEN0E ,VPEN0 output select bits" "None,VPEN0_0,VPEN0_1,?..."
|
|
bitfld.long 0x00 4.--5. " RST0E ,RST0 output select bits" "None,RST0_0,RST0_1,?..."
|
|
bitfld.long 0x00 2.--3. " DATA0B ,DATA0 bus select bits" "DATA0_0,DATA0_0,DATA0_1,?..."
|
|
bitfld.long 0x00 0.--1. " CIN0S ,CIN0 input select bits" "CIN0_0,CIN0_0,CIN0_1,None"
|
|
group.long 0x694++0x07
|
|
line.long 0x00 "EPFR37,Extended Pin Function Setting Register 37"
|
|
bitfld.long 0x00 26.--27. " SDO5E ,MFSI2S SDO5 output select bits" "None,I2SDO5_0,I2SDO5_1,I2SDO5_2"
|
|
bitfld.long 0x00 24.--25. " SDI5S ,MFSI2S I2SDI5 input select bits" "None,I2SDI5_0,I2SDI5_1,I2SDI5_2"
|
|
bitfld.long 0x00 22.--23. " WS5B ,I2SWS5 output select bits" "None,I2SWS5_0,I2SWS5_1,I2SWS5_2"
|
|
bitfld.long 0x00 20.--21. " SCK5B ,I2SCK5 output select bits" "None,I2SCK5_0,I2SCK5_1,I2SCK5_2"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MCLK5E ,I2SMCLK5 output select bits" "None,I2SMCLK5_0,I2SMCLK5_1,I2SMCLK5_2"
|
|
bitfld.long 0x00 16.--17. " MCLK5S ,I2SMCLK5 input select bits" "None,I2SMCLK5_0,I2SMCLK5_1,I2SMCLK5_2"
|
|
bitfld.long 0x00 10.--11. " SDO4E ,MFSI2S SDO4 output select bits" "None,I2SDO4_0,I2SDO4_1,I2SDO4_2"
|
|
bitfld.long 0x00 8.--9. " SDI4S ,MFSI2S I2SDI4 input select bits" "None,I2SDI4_0,I2SDI4_1,I2SDI4_1"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " WS4B ,I2SWS4 output select bits" "None,I2SWS4_0,I2SWS4_1,I2SWS4_2"
|
|
bitfld.long 0x00 4.--5. " SCK4B ,I2SCK4 output select bits" "None,I2SCK4_0,I2SCK4_1,I2SCK4_2"
|
|
bitfld.long 0x00 2.--3. " MCLK4E ,I2SMCLK4 output select bits" "None,I2SMCLK4_0,I2SMCLK4_1,I2SMCLK4_2"
|
|
bitfld.long 0x00 0.--1. " MCLK4S ,I2SMCLK4 input select bits" "None,I2SMCLK4_0,I2SMCLK4_1,I2SMCLK4_2"
|
|
line.long 0x04 "MCLK6E,Extended Pin Function Setting Register 38"
|
|
bitfld.long 0x04 10.--11. " SDO6E ,MFSI2S SDO6 output select bits" "None,I2SDO6_0,I2SDO6_1,I2SDO6_2"
|
|
bitfld.long 0x04 8.--9. " SDI6S ,MFSI2S I2SDI6 input select bits" "None,I2SDI6_0,I2SDI6_1,I2SDI6_2"
|
|
bitfld.long 0x04 6.--7. " WS6B ,I2SWS6 output select bits" "None,I2SWS6_0,I2SWS6_1,I2SWS6_2"
|
|
textline " "
|
|
bitfld.long 0x04 4.--5. " SCK6B ,I2SCK6 output select bits" "None,I2SCK6_0,I2SCK6_1,I2SCK6_2"
|
|
bitfld.long 0x04 2.--3. " SCK6B ,I2SMCLK6 output select bits" "None,I2SMCLK6_0,I2SMCLK6_1,I2SMCLK6_2"
|
|
bitfld.long 0x04 0.--1. " MCLK6S ,I2SMCLK6 input select bits" "None,I2SMCLK6_0,I2SMCLK6_1,I2SMCLK6_2"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("S6E1C*"))
|
|
group.long 0x704++0x03
|
|
line.long 0x00 "PZR1,Port 1 Pseudo Open Drain Setting Register"
|
|
bitfld.long 0x00 15. " PZR1[15] ,Port pseudo open drain setting bit 15" "High,Hi-Z"
|
|
bitfld.long 0x00 14. " [14] ,Port pseudo open drain setting bit 14" "High,Hi-Z"
|
|
bitfld.long 0x00 13. " [13] ,Port pseudo open drain setting bit 13" "High,Hi-Z"
|
|
bitfld.long 0x00 12. " [12] ,Port pseudo open drain setting bit 12" "High,Hi-Z"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port pseudo open drain setting bit 11" "High,Hi-Z"
|
|
bitfld.long 0x00 10. " [10] ,Port pseudo open drain setting bit 10" "High,Hi-Z"
|
|
bitfld.long 0x00 9. " [9] ,Port pseudo open drain setting bit 9" "High,Hi-Z"
|
|
bitfld.long 0x00 8. " [8] ,Port pseudo open drain setting bit 8" "High,Hi-Z"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port pseudo open drain setting bit 7" "High,Hi-Z"
|
|
bitfld.long 0x00 6. " [6] ,Port pseudo open drain setting bit 6" "High,Hi-Z"
|
|
bitfld.long 0x00 5. " [5] ,Port pseudo open drain setting bit 5" "High,Hi-Z"
|
|
bitfld.long 0x00 4. " [4] ,Port pseudo open drain setting bit 4" "High,Hi-Z"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port pseudo open drain setting bit 3" "High,Hi-Z"
|
|
bitfld.long 0x00 2. " [2] ,Port pseudo open drain setting bit 2" "High,Hi-Z"
|
|
bitfld.long 0x00 1. " [1] ,Port pseudo open drain setting bit 1" "High,Hi-Z"
|
|
bitfld.long 0x00 0. " [0] ,Port pseudo open drain setting bit 0" "High,Hi-Z"
|
|
group.long 0x70C++0x03
|
|
line.long 0x00 "PZR3,Port 3 Pseudo Open Drain Setting Register"
|
|
bitfld.long 0x00 15. " PZR3[15] ,Port pseudo open drain setting bit 15" "High,Hi-Z"
|
|
bitfld.long 0x00 14. " [14] ,Port pseudo open drain setting bit 14" "High,Hi-Z"
|
|
bitfld.long 0x00 13. " [13] ,Port pseudo open drain setting bit 13" "High,Hi-Z"
|
|
bitfld.long 0x00 12. " [12] ,Port pseudo open drain setting bit 12" "High,Hi-Z"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port pseudo open drain setting bit 11" "High,Hi-Z"
|
|
bitfld.long 0x00 10. " [10] ,Port pseudo open drain setting bit 10" "High,Hi-Z"
|
|
bitfld.long 0x00 9. " [9] ,Port pseudo open drain setting bit 9" "High,Hi-Z"
|
|
bitfld.long 0x00 8. " [8] ,Port pseudo open drain setting bit 8" "High,Hi-Z"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port pseudo open drain setting bit 7" "High,Hi-Z"
|
|
bitfld.long 0x00 6. " [6] ,Port pseudo open drain setting bit 6" "High,Hi-Z"
|
|
bitfld.long 0x00 5. " [5] ,Port pseudo open drain setting bit 5" "High,Hi-Z"
|
|
bitfld.long 0x00 4. " [4] ,Port pseudo open drain setting bit 4" "High,Hi-Z"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port pseudo open drain setting bit 3" "High,Hi-Z"
|
|
bitfld.long 0x00 2. " [2] ,Port pseudo open drain setting bit 2" "High,Hi-Z"
|
|
bitfld.long 0x00 1. " [1] ,Port pseudo open drain setting bit 1" "High,Hi-Z"
|
|
bitfld.long 0x00 0. " [0] ,Port pseudo open drain setting bit 0" "High,Hi-Z"
|
|
group.long 0x718++0x03
|
|
line.long 0x00 "PZR6,Port 6 Pseudo Open Drain Setting Register"
|
|
bitfld.long 0x00 15. " PZR6[15] ,Port pseudo open drain setting bit 15" "High,Hi-Z"
|
|
bitfld.long 0x00 14. " [14] ,Port pseudo open drain setting bit 14" "High,Hi-Z"
|
|
bitfld.long 0x00 13. " [13] ,Port pseudo open drain setting bit 13" "High,Hi-Z"
|
|
bitfld.long 0x00 12. " [12] ,Port pseudo open drain setting bit 12" "High,Hi-Z"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Port pseudo open drain setting bit 11" "High,Hi-Z"
|
|
bitfld.long 0x00 10. " [10] ,Port pseudo open drain setting bit 10" "High,Hi-Z"
|
|
bitfld.long 0x00 9. " [9] ,Port pseudo open drain setting bit 9" "High,Hi-Z"
|
|
bitfld.long 0x00 8. " [8] ,Port pseudo open drain setting bit 8" "High,Hi-Z"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Port pseudo open drain setting bit 7" "High,Hi-Z"
|
|
bitfld.long 0x00 6. " [6] ,Port pseudo open drain setting bit 6" "High,Hi-Z"
|
|
bitfld.long 0x00 5. " [5] ,Port pseudo open drain setting bit 5" "High,Hi-Z"
|
|
bitfld.long 0x00 4. " [4] ,Port pseudo open drain setting bit 4" "High,Hi-Z"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Port pseudo open drain setting bit 3" "High,Hi-Z"
|
|
bitfld.long 0x00 2. " [2] ,Port pseudo open drain setting bit 2" "High,Hi-Z"
|
|
bitfld.long 0x00 1. " [1] ,Port pseudo open drain setting bit 1" "High,Hi-Z"
|
|
bitfld.long 0x00 0. " [0] ,Port pseudo open drain setting bit 0" "High,Hi-Z"
|
|
endif
|
|
textline " "
|
|
group.long 0x580++0x03
|
|
line.long 0x00 "SPSR,Special Port Setting Register"
|
|
sif cpuis("S6E1C*")
|
|
bitfld.long 0x00 4. " USB0C ,USB ch.0 pin setting register" "Digital I/O pins,USB"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2.--3. " MAINXC ,Main Clock (Oscillation) Pin Setting Register (X0/X1)" "I/O,Main clock,,Ext. clk. input/I/O"
|
|
bitfld.long 0x00 0.--1. " SUBXC ,Sub Clock (Oscillation) Pin Setting Register (X0A/X1A)" "I/O,Sub clock,,Ext. clk. input/I/O"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "Fast GPIO"
|
|
base ad:0xF8000000
|
|
width 10.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "FPDIR0,Fast GPIO Input Data Register 0"
|
|
bitfld.long 0x00 15. " P0_F ,Fast GPIO input data bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " P0_E ,Fast GPIO input data bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " P0_D ,Fast GPIO input data bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " P0_C ,Fast GPIO input data bit 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P0_B ,Fast GPIO input data bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " P0_A ,Fast GPIO input data bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " P0_9 ,Fast GPIO input data bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " P0_8 ,Fast GPIO input data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P0_7 ,Fast GPIO input data bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " P0_6 ,Fast GPIO input data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " P0_5 ,Fast GPIO input data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " P0_4 ,Fast GPIO input data bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P0_3 ,Fast GPIO input data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " P0_2 ,Fast GPIO input data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P0_1 ,Fast GPIO input data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " P0_0 ,Fast GPIO input data bit 0" "Low,High"
|
|
sif cpuis("S6E1A11B")||cpuis("S6E1A12B")||cpuis("S6E1C11B")||cpuis("S6E1C12B")||cpuis("S6E1C31B")||cpuis("S6E1C32B")
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "FPDIR1,Fast GPIO Input Data Register 1"
|
|
sif cpuis("S6E1C11B")||cpuis("S6E1C12B")||cpuis("S6E1C31B")||cpuis("S6E1C32B")
|
|
bitfld.long 0x00 7. " P1_7 ,Fast GPIO input data bit 7" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " P1_6 ,Fast GPIO input data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " P1_5 ,Fast GPIO input data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " P1_4 ,Fast GPIO input data bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " P1_3 ,Fast GPIO input data bit 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P1_2 ,Fast GPIO input data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P1_1 ,Fast GPIO input data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " P1_0 ,Fast GPIO input data bit 0" "Low,High"
|
|
elif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C31C")||cpuis("S6E1C32C")||cpuis("S6E1C11D")||cpuis("S6E1C12D")||cpuis("S6E1C31D")||cpuis("S6E1C32D")
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "FPDIR1,Fast GPIO Input Data Register 1"
|
|
bitfld.long 0x00 15. " P1_F ,Fast GPIO input data bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " P1_E ,Fast GPIO input data bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " P1_D ,Fast GPIO input data bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " P1_C ,Fast GPIO input data bit 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P1_B ,Fast GPIO input data bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " P1_A ,Fast GPIO input data bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " P1_9 ,Fast GPIO input data bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " P1_8 ,Fast GPIO input data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P1_7 ,Fast GPIO input data bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " P1_6 ,Fast GPIO input data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " P1_5 ,Fast GPIO input data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " P1_4 ,Fast GPIO input data bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P1_3 ,Fast GPIO input data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " P1_2 ,Fast GPIO input data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P1_1 ,Fast GPIO input data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " P1_0 ,Fast GPIO input data bit 0" "Low,High"
|
|
sif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C31C")||cpuis("S6E1C32C")
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "FPDIR2,Fast GPIO Input Data Register 0"
|
|
sif cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C31C")||cpuis("S6E1C32C")
|
|
bitfld.long 0x00 5. " P2_5 ,Fast GPIO input data bit 5" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " P2_4 ,Fast GPIO input data bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " P2_3 ,Fast GPIO input data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " P2_2 ,Fast GPIO input data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P2_1 ,Fast GPIO input data bit 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P2_0 ,Fast GPIO input data bit 0" "Low,High"
|
|
elif cpuis("S6E1C11D")||cpuis("S6E1C12D")||cpuis("S6E1C31D")||cpuis("S6E1C32D")
|
|
rgroup.long 0x08++0x07
|
|
line.long 0x00 "FPDIR2,Fast GPIO Input Data Register 2"
|
|
bitfld.long 0x00 15. " P2_F ,Fast GPIO input data bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " P2_E ,Fast GPIO input data bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " P2_D ,Fast GPIO input data bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " P2_C ,Fast GPIO input data bit 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P2_B ,Fast GPIO input data bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " P2_A ,Fast GPIO input data bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " P2_9 ,Fast GPIO input data bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " P2_8 ,Fast GPIO input data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P2_7 ,Fast GPIO input data bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " P2_6 ,Fast GPIO input data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " P2_5 ,Fast GPIO input data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " P2_4 ,Fast GPIO input data bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P2_3 ,Fast GPIO input data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " P2_2 ,Fast GPIO input data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P2_1 ,Fast GPIO input data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " P2_0 ,Fast GPIO input data bit 0" "Low,High"
|
|
line.long 0x04 "FPDIR3,Fast GPIO Input Data Register 3"
|
|
bitfld.long 0x04 5. " P3_5 ,Fast GPIO input data bit 5" "Low,High"
|
|
bitfld.long 0x04 4. " P3_4 ,Fast GPIO input data bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P3_3 ,Fast GPIO input data bit 3" "Low,High"
|
|
bitfld.long 0x04 2. " P3_2 ,Fast GPIO input data bit 2" "Low,High"
|
|
bitfld.long 0x04 1. " P3_1 ,Fast GPIO input data bit 1" "Low,High"
|
|
bitfld.long 0x04 0. " P3_0 ,Fast GPIO input data bit 0" "Low,High"
|
|
endif
|
|
endif
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FPDOR0,Fast GPIO Output Data Register 0"
|
|
bitfld.long 0x00 15. " P0_F ,Fast GPIO output data bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " P0_E ,Fast GPIO output data bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " P0_D ,Fast GPIO output data bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " P0_C ,Fast GPIO output data bit 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P0_B ,Fast GPIO output data bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " P0_A ,Fast GPIO output data bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " P0_9 ,Fast GPIO output data bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " P0_8 ,Fast GPIO output data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P0_7 ,Fast GPIO output data bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " P0_6 ,Fast GPIO output data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " P0_5 ,Fast GPIO output data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " P0_4 ,Fast GPIO output data bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P0_3 ,Fast GPIO output data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " P0_2 ,Fast GPIO output data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P0_1 ,Fast GPIO output data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " P0_0 ,Fast GPIO output data bit 0" "Low,High"
|
|
sif cpuis("S6E1A11B")||cpuis("S6E1A12B")||cpuis("S6E1C11B")||cpuis("S6E1C12B")||cpuis("S6E1C31B")||cpuis("S6E1C32B")
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "FPDOR1,Fast GPIO Output Data Register 1"
|
|
sif cpuis("S6E1C11B")||cpuis("S6E1C12B")||cpuis("S6E1C31B")||cpuis("S6E1C32B")
|
|
bitfld.long 0x00 7. " P1_7 ,Fast GPIO output data bit 7" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " P1_6 ,Fast GPIO output data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " P1_5 ,Fast GPIO output data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " P1_4 ,Fast GPIO output data bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " P1_3 ,Fast GPIO output data bit 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P1_2 ,Fast GPIO output data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P1_1 ,Fast GPIO output data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " P1_0 ,Fast GPIO output data bit 0" "Low,High"
|
|
elif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C31C")||cpuis("S6E1C32C")||cpuis("S6E1C11D")||cpuis("S6E1C12D")||cpuis("S6E1C31D")||cpuis("S6E1C32D")
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "FPDOR1,Fast GPIO Output Data Register 1"
|
|
bitfld.long 0x00 15. " P1_F ,Fast GPIO output data bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " P1_E ,Fast GPIO output data bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " P1_D ,Fast GPIO output data bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " P1_C ,Fast GPIO output data bit 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P1_B ,Fast GPIO output data bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " P1_A ,Fast GPIO output data bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " P1_9 ,Fast GPIO output data bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " P1_8 ,Fast GPIO output data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P1_7 ,Fast GPIO output data bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " P1_6 ,Fast GPIO output data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " P1_5 ,Fast GPIO output data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " P1_4 ,Fast GPIO output data bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P1_3 ,Fast GPIO output data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " P1_2 ,Fast GPIO output data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P1_1 ,Fast GPIO output data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " P1_0 ,Fast GPIO output data bit 0" "Low,High"
|
|
sif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C31C")||cpuis("S6E1C32C")
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "FPDOR2,Fast GPIO Output Data Register 2"
|
|
sif cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C31C")||cpuis("S6E1C32C")
|
|
bitfld.long 0x00 5. " P2_5 ,Fast GPIO output data bit 5" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " P2_4 ,Fast GPIO output data bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " P2_3 ,Fast GPIO output data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " P2_2 ,Fast GPIO output data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P2_1 ,Fast GPIO output data bit 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P2_0 ,Fast GPIO output data bit 0" "Low,High"
|
|
elif cpuis("S6E1C11D")||cpuis("S6E1C12D")||cpuis("S6E1C31D")||cpuis("S6E1C32D")
|
|
group.long 0x48++0x07
|
|
line.long 0x00 "FPDOR2,Fast GPIO Output Data Register 2"
|
|
bitfld.long 0x00 15. " P2_F ,Fast GPIO output data bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " P2_E ,Fast GPIO output data bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " P2_D ,Fast GPIO output data bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " P2_C ,Fast GPIO output data bit 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P2_B ,Fast GPIO output data bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " P2_A ,Fast GPIO output data bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " P2_9 ,Fast GPIO output data bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " P2_8 ,Fast GPIO output data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P2_7 ,Fast GPIO output data bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " P2_6 ,Fast GPIO output data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " P2_5 ,Fast GPIO output data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " P2_4 ,Fast GPIO output data bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P2_3 ,Fast GPIO output data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " P2_2 ,Fast GPIO output data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P2_1 ,Fast GPIO output data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " P2_0 ,Fast GPIO output data bit 0" "Low,High"
|
|
line.long 0x04 "FPDOR3,Fast GPIO Output Data Register 3"
|
|
bitfld.long 0x04 5. " P3_5 ,Fast GPIO output data bit 5" "Low,High"
|
|
bitfld.long 0x04 4. " P3_4 ,Fast GPIO output data bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P3_3 ,Fast GPIO output data bit 3" "Low,High"
|
|
bitfld.long 0x04 2. " P3_2 ,Fast GPIO output data bit 2" "Low,High"
|
|
bitfld.long 0x04 1. " P3_1 ,Fast GPIO output data bit 1" "Low,High"
|
|
bitfld.long 0x04 0. " P3_0 ,Fast GPIO output data bit 0" "Low,High"
|
|
endif
|
|
endif
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "M_FPDIR0,Mirror Fast GPIO Input Data Register 0"
|
|
bitfld.long 0x00 15. " P0_F ,Mirror fast GPIO input data bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " P0_E ,Mirror fast GPIO input data bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " P0_D ,Mirror fast GPIO input data bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " P0_C ,Mirror fast GPIO input data bit 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P0_B ,Mirror fast GPIO input data bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " P0_A ,Mirror fast GPIO input data bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " P0_9 ,Mirror fast GPIO input data bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " P0_8 ,Mirror fast GPIO input data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P0_7 ,Mirror fast GPIO input data bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " P0_6 ,Mirror fast GPIO input data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " P0_5 ,Mirror fast GPIO input data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " P0_4 ,Mirror fast GPIO input data bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P0_3 ,Mirror fast GPIO input data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " P0_2 ,Mirror fast GPIO input data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P0_1 ,Mirror fast GPIO input data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " P0_0 ,Mirror fast GPIO input data bit 0" "Low,High"
|
|
sif cpuis("S6E1A11B")||cpuis("S6E1A12B")||cpuis("S6E1C11B")||cpuis("S6E1C12B")||cpuis("S6E1C31B")||cpuis("S6E1C32B")
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "M_FPDIR1,Mirror Fast GPIO Input Data Register 1"
|
|
sif cpuis("S6E1C11B")||cpuis("S6E1C12B")||cpuis("S6E1C31B")||cpuis("S6E1C32B")
|
|
bitfld.long 0x00 7. " P1_7 ,Mirror fast GPIO input data bit 7" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " P1_6 ,Mirror fast GPIO input data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " P1_5 ,Mirror fast GPIO input data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " P1_4 ,Mirror fast GPIO input data bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " P1_3 ,Mirror fast GPIO input data bit 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P1_2 ,Mirror fast GPIO input data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P1_1 ,Mirror fast GPIO input data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " P1_0 ,Mirror fast GPIO input data bit 0" "Low,High"
|
|
elif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C31C")||cpuis("S6E1C32C")||cpuis("S6E1C11D")||cpuis("S6E1C12D")||cpuis("S6E1C31D")||cpuis("S6E1C32D")
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "M_FPDIR1,Mirror Fast GPIO Input Data Register 1"
|
|
bitfld.long 0x00 15. " P1_F ,Mirror fast GPIO input data bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " P1_E ,Mirror fast GPIO input data bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " P1_D ,Mirror fast GPIO input data bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " P1_C ,Mirror fast GPIO input data bit 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P1_B ,Mirror fast GPIO input data bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " P1_A ,Mirror fast GPIO input data bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " P1_9 ,Mirror fast GPIO input data bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " P1_8 ,Mirror fast GPIO input data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P1_7 ,Mirror fast GPIO input data bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " P1_6 ,Mirror fast GPIO input data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " P1_5 ,Mirror fast GPIO input data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " P1_4 ,Mirror fast GPIO input data bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P1_3 ,Mirror fast GPIO input data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " P1_2 ,Mirror fast GPIO input data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P1_1 ,Mirror fast GPIO input data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " P1_0 ,Mirror fast GPIO input data bit 0" "Low,High"
|
|
sif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C31C")||cpuis("S6E1C32C")
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "M_FPDIR2,Mirror Fast GPIO Input Data Register 2"
|
|
sif cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C31C")||cpuis("S6E1C32C")
|
|
bitfld.long 0x00 5. " P2_5 ,Mirror fast GPIO input data bit 5" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " P2_4 ,Mirror fast GPIO input data bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " P2_3 ,Mirror fast GPIO input data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " P2_2 ,Mirror fast GPIO input data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P2_1 ,Mirror fast GPIO input data bit 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P2_0 ,Mirror fast GPIO input data bit 0" "Low,High"
|
|
elif cpuis("S6E1C11D")||cpuis("S6E1C12D")||cpuis("S6E1C31D")||cpuis("S6E1C32D")
|
|
rgroup.long 0x88++0x07
|
|
line.long 0x00 "M_FPDIR2,Mirror Fast GPIO Input Data Register 2"
|
|
bitfld.long 0x00 15. " P2_F ,Mirror fast GPIO input data bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " P2_E ,Mirror fast GPIO input data bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " P2_D ,Mirror fast GPIO input data bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " P2_C ,Mirror fast GPIO input data bit 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P2_B ,Mirror fast GPIO input data bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " P2_A ,Mirror fast GPIO input data bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " P2_9 ,Mirror fast GPIO input data bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " P2_8 ,Mirror fast GPIO input data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P2_7 ,Mirror fast GPIO input data bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " P2_6 ,Mirror fast GPIO input data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " P2_5 ,Mirror fast GPIO input data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " P2_4 ,Mirror fast GPIO input data bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P2_3 ,Mirror fast GPIO input data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " P2_2 ,Mirror fast GPIO input data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P2_1 ,Mirror fast GPIO input data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " P2_0 ,Mirror fast GPIO input data bit 0" "Low,High"
|
|
line.long 0x04 "M_FPDIR3,Mirror Fast GPIO Input Data Register 3"
|
|
bitfld.long 0x04 5. " P3_5 ,Mirror fast GPIO input data bit 5" "Low,High"
|
|
bitfld.long 0x04 4. " P3_4 ,Mirror fast GPIO input data bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P3_3 ,Mirror fast GPIO input data bit 3" "Low,High"
|
|
bitfld.long 0x04 2. " P3_2 ,Mirror fast GPIO input data bit 2" "Low,High"
|
|
bitfld.long 0x04 1. " P3_1 ,Mirror fast GPIO input data bit 1" "Low,High"
|
|
bitfld.long 0x04 0. " P3_0 ,Mirror fast GPIO input data bit 0" "Low,High"
|
|
endif
|
|
endif
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "M_FPDOR0,Mirror Fast GPIO Output Data Register 0"
|
|
bitfld.long 0x00 15. " P0_F ,Mirror fast GPIO output data bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " P0_E ,Mirror fast GPIO output data bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " P0_D ,Mirror fast GPIO output data bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " P0_C ,Mirror fast GPIO output data bit 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P0_B ,Mirror fast GPIO output data bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " P0_A ,Mirror fast GPIO output data bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " P0_9 ,Mirror fast GPIO output data bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " P0_8 ,Mirror fast GPIO output data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P0_7 ,Mirror fast GPIO output data bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " P0_6 ,Mirror fast GPIO output data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " P0_5 ,Mirror fast GPIO output data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " P0_4 ,Mirror fast GPIO output data bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P0_3 ,Mirror fast GPIO output data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " P0_2 ,Mirror fast GPIO output data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P0_1 ,Mirror fast GPIO output data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " P0_0 ,Mirror fast GPIO output data bit 0" "Low,High"
|
|
sif cpuis("S6E1A11B")||cpuis("S6E1A12B")||cpuis("S6E1C11B")||cpuis("S6E1C12B")||cpuis("S6E1C31B")||cpuis("S6E1C32B")
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "M_FPDOR1,Mirror Fast GPIO Output Data Register 1"
|
|
sif cpuis("S6E1C11B")||cpuis("S6E1C12B")||cpuis("S6E1C31B")||cpuis("S6E1C32B")
|
|
bitfld.long 0x00 7. " P1_7 ,Mirror fast GPIO output data bit 7" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " P1_6 ,Mirror fast GPIO output data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " P1_5 ,Mirror fast GPIO output data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " P1_4 ,Mirror fast GPIO output data bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " P1_3 ,Mirror fast GPIO output data bit 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P1_2 ,Mirror fast GPIO output data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P1_1 ,Mirror fast GPIO output data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " P1_0 ,Mirror fast GPIO output data bit 0" "Low,High"
|
|
elif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C31C")||cpuis("S6E1C32C")||cpuis("S6E1C11D")||cpuis("S6E1C12D")||cpuis("S6E1C31D")||cpuis("S6E1C32D")
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "M_FPDOR1,Mirror Fast GPIO Output Data Register 1"
|
|
bitfld.long 0x00 15. " P1_F ,Mirror fast GPIO output data bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " P1_E ,Mirror fast GPIO output data bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " P1_D ,Mirror fast GPIO output data bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " P1_C ,Mirror fast GPIO output data bit 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P1_B ,Mirror fast GPIO output data bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " P1_A ,Mirror fast GPIO output data bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " P1_9 ,Mirror fast GPIO output data bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " P1_8 ,Mirror fast GPIO output data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P1_7 ,Mirror fast GPIO output data bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " P1_6 ,Mirror fast GPIO output data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " P1_5 ,Mirror fast GPIO output data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " P1_4 ,Mirror fast GPIO output data bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P1_3 ,Mirror fast GPIO output data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " P1_2 ,Mirror fast GPIO output data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P1_1 ,Mirror fast GPIO output data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " P1_0 ,Mirror fast GPIO output data bit 0" "Low,High"
|
|
sif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C31C")||cpuis("S6E1C32C")
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "M_FPDOR2,Mirror Fast GPIO Output Data Register 2"
|
|
sif cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C31C")||cpuis("S6E1C32C")
|
|
bitfld.long 0x00 5. " P2_5 ,Mirror fast GPIO output data bit 5" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " P2_4 ,Mirror fast GPIO output data bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " P2_3 ,Mirror fast GPIO output data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " P2_2 ,Mirror fast GPIO output data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P2_1 ,Mirror fast GPIO output data bit 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P2_0 ,Mirror fast GPIO output data bit 0" "Low,High"
|
|
elif cpuis("S6E1C11D")||cpuis("S6E1C12D")||cpuis("S6E1C31D")||cpuis("S6E1C32D")
|
|
group.long 0xC8++0x07
|
|
line.long 0x00 "M_FPDOR2,Mirror Fast GPIO Output Data Register 2"
|
|
bitfld.long 0x00 15. " P2_F ,Mirror fast GPIO output data bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " P2_E ,Mirror fast GPIO output data bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " P2_D ,Mirror fast GPIO output data bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " P2_C ,Mirror fast GPIO output data bit 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P2_B ,Mirror fast GPIO output data bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " P2_A ,Mirror fast GPIO output data bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " P2_9 ,Mirror fast GPIO output data bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " P2_8 ,Mirror fast GPIO output data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P2_7 ,Mirror fast GPIO output data bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " P2_6 ,Mirror fast GPIO output data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " P2_5 ,Mirror fast GPIO output data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " P2_4 ,Mirror fast GPIO output data bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P2_3 ,Mirror fast GPIO output data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " P2_2 ,Mirror fast GPIO output data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P2_1 ,Mirror fast GPIO output data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " P2_0 ,Mirror fast GPIO output data bit 0" "Low,High"
|
|
line.long 0x04 "M_FPDOR3,Mirror Fast GPIO Output Data Register 3"
|
|
bitfld.long 0x04 5. " P3_5 ,Mirror fast GPIO output data bit 5" "Low,High"
|
|
bitfld.long 0x04 4. " P3_4 ,Mirror fast GPIO output data bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P3_3 ,Mirror fast GPIO output data bit 3" "Low,High"
|
|
bitfld.long 0x04 2. " P3_2 ,Mirror fast GPIO output data bit 2" "Low,High"
|
|
bitfld.long 0x04 1. " P3_1 ,Mirror fast GPIO output data bit 1" "Low,High"
|
|
bitfld.long 0x04 0. " P3_0 ,Mirror fast GPIO output data bit 0" "Low,High"
|
|
endif
|
|
endif
|
|
base ad:0x40033000
|
|
sif cpuis("S6E1C*")
|
|
group.long 0x900++0x03
|
|
line.long 0x00 "FPOER0,Fast GPIO Output Enable Register 0"
|
|
bitfld.long 0x00 15. " P0_F ,Fast GPIO output enable bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " P0_E ,Fast GPIO output enable bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " P0_D ,Fast GPIO output enable bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " P0_C ,Fast GPIO output enable bit 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P0_B ,Fast GPIO output enable bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " P0_A ,Fast GPIO output enable bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " P0_9 ,Fast GPIO output enable bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " P0_8 ,Fast GPIO output enable bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P0_7 ,Fast GPIO output enable bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " P0_6 ,Fast GPIO output enable bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " P0_5 ,Fast GPIO output enable bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " P0_4 ,Fast GPIO output enable bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P0_3 ,Fast GPIO output enable bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " P0_2 ,Fast GPIO output enable bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P0_1 ,Fast GPIO output enable bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " P0_0 ,Fast GPIO output enable bit 0" "Low,High"
|
|
else
|
|
wgroup.long 0x900++0x03
|
|
line.long 0x00 "FPOER0,Fast GPIO Output Enable Register 0"
|
|
bitfld.long 0x00 15. " P0_F ,Fast GPIO output enable bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " P0_E ,Fast GPIO output enable bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " P0_D ,Fast GPIO output enable bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " P0_C ,Fast GPIO output enable bit 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P0_B ,Fast GPIO output enable bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " P0_A ,Fast GPIO output enable bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " P0_9 ,Fast GPIO output enable bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " P0_8 ,Fast GPIO output enable bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P0_7 ,Fast GPIO output enable bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " P0_6 ,Fast GPIO output enable bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " P0_5 ,Fast GPIO output enable bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " P0_4 ,Fast GPIO output enable bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P0_3 ,Fast GPIO output enable bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " P0_2 ,Fast GPIO output enable bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P0_1 ,Fast GPIO output enable bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " P0_0 ,Fast GPIO output enable bit 0" "Low,High"
|
|
endif
|
|
sif cpuis("S6E1A11B")||cpuis("S6E1A12B")
|
|
wgroup.long 0x904++0x03
|
|
line.long 0x00 "FPOER1,Fast GPIO Output Enable Register 1"
|
|
bitfld.long 0x00 6. " P1_6 ,Fast GPIO output enable bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " P1_5 ,Fast GPIO output enable bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " P1_4 ,Fast GPIO output enable bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " P1_3 ,Fast GPIO output enable bit 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P1_2 ,Fast GPIO output enable bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P1_1 ,Fast GPIO output enable bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " P1_0 ,Fast GPIO output enable bit 0" "Low,High"
|
|
elif cpuis("S6E1C11B")||cpuis("S6E1C12B")||cpuis("S6E1C31B")||cpuis("S6E1C32B")
|
|
group.long 0x904++0x03
|
|
line.long 0x00 "FPOER1,Fast GPIO Output Enable Register 1"
|
|
bitfld.long 0x00 7. " P1_7 ,Fast GPIO output enable bit 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P1_6 ,Fast GPIO output enable bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " P1_5 ,Fast GPIO output enable bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " P1_4 ,Fast GPIO output enable bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " P1_3 ,Fast GPIO output enable bit 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P1_2 ,Fast GPIO output enable bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P1_1 ,Fast GPIO output enable bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " P1_0 ,Fast GPIO output enable bit 0" "Low,High"
|
|
elif cpuis("S6E1A11C")||cpuis("S6E1A12C")
|
|
wgroup.long 0x904++0x07
|
|
line.long 0x00 "FPOER1,Fast GPIO Output Enable Register 1"
|
|
bitfld.long 0x00 15. " P1_F ,Fast GPIO output enable bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " P1_E ,Fast GPIO output enable bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " P1_D ,Fast GPIO output enable bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " P1_C ,Fast GPIO output enable bit 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P1_B ,Fast GPIO output enable bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " P1_A ,Fast GPIO output enable bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " P1_9 ,Fast GPIO output enable bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " P1_8 ,Fast GPIO output enable bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P1_7 ,Fast GPIO output enable bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " P1_6 ,Fast GPIO output enable bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " P1_5 ,Fast GPIO output enable bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " P1_4 ,Fast GPIO output enable bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P1_3 ,Fast GPIO output enable bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " P1_2 ,Fast GPIO output enable bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P1_1 ,Fast GPIO output enable bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " P1_0 ,Fast GPIO output enable bit 0" "Low,High"
|
|
line.long 0x04 "FPOER2,Fast GPIO Output Enable Register 2"
|
|
bitfld.long 0x04 4. " P2_4 ,Fast GPIO output enable bit 4" "Low,High"
|
|
bitfld.long 0x04 3. " P2_3 ,Fast GPIO output enable bit 3" "Low,High"
|
|
bitfld.long 0x04 2. " P2_2 ,Fast GPIO output enable bit 2" "Low,High"
|
|
bitfld.long 0x04 1. " P2_1 ,Fast GPIO output enable bit 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 0. " P2_0 ,Fast GPIO output enable bit 0" "Low,High"
|
|
elif cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C31C")||cpuis("S6E1C32C")
|
|
group.long 0x904++0x07
|
|
line.long 0x00 "FPOER1,Fast GPIO Output Enable Register 1"
|
|
bitfld.long 0x00 15. " P1_F ,Fast GPIO output enable bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " P1_E ,Fast GPIO output enable bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " P1_D ,Fast GPIO output enable bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " P1_C ,Fast GPIO output enable bit 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P1_B ,Fast GPIO output enable bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " P1_A ,Fast GPIO output enable bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " P1_9 ,Fast GPIO output enable bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " P1_8 ,Fast GPIO output enable bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P1_7 ,Fast GPIO output enable bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " P1_6 ,Fast GPIO output enable bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " P1_5 ,Fast GPIO output enable bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " P1_4 ,Fast GPIO output enable bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P1_3 ,Fast GPIO output enable bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " P1_2 ,Fast GPIO output enable bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P1_1 ,Fast GPIO output enable bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " P1_0 ,Fast GPIO output enable bit 0" "Low,High"
|
|
line.long 0x04 "FPOER2,Fast GPIO Output Enable Register 2"
|
|
bitfld.long 0x04 5. " P2_5 ,Fast GPIO output enable bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 4. " P2_4 ,Fast GPIO output enable bit 4" "Low,High"
|
|
bitfld.long 0x04 3. " P2_3 ,Fast GPIO output enable bit 3" "Low,High"
|
|
bitfld.long 0x04 2. " P2_2 ,Fast GPIO output enable bit 2" "Low,High"
|
|
bitfld.long 0x04 1. " P2_1 ,Fast GPIO output enable bit 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 0. " P2_0 ,Fast GPIO output enable bit 0" "Low,High"
|
|
elif cpuis("S6E1C11D")||cpuis("S6E1C12D")||cpuis("S6E1C31D")||cpuis("S6E1C32D")
|
|
group.long 0x904++0x0B
|
|
line.long 0x00 "FPOER1,Fast GPIO Output Enable Register 1"
|
|
bitfld.long 0x00 15. " P1_F ,Fast GPIO output enable bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " P1_E ,Fast GPIO output enable bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " P1_D ,Fast GPIO output enable bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " P1_C ,Fast GPIO output enable bit 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P1_B ,Fast GPIO output enable bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " P1_A ,Fast GPIO output enable bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " P1_9 ,Fast GPIO output enable bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " P1_8 ,Fast GPIO output enable bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P1_7 ,Fast GPIO output enable bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " P1_6 ,Fast GPIO output enable bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " P1_5 ,Fast GPIO output enable bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " P1_4 ,Fast GPIO output enable bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P1_3 ,Fast GPIO output enable bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " P1_2 ,Fast GPIO output enable bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " P1_1 ,Fast GPIO output enable bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " P1_0 ,Fast GPIO output enable bit 0" "Low,High"
|
|
line.long 0x04 "FPOER2,Fast GPIO Output Enable Register 2"
|
|
bitfld.long 0x04 15. " P2_F ,Fast GPIO output enable bit 15" "Low,High"
|
|
bitfld.long 0x04 14. " P2_E ,Fast GPIO output enable bit 14" "Low,High"
|
|
bitfld.long 0x04 13. " P2_D ,Fast GPIO output enable bit 13" "Low,High"
|
|
bitfld.long 0x04 12. " P2_C ,Fast GPIO output enable bit 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 11. " P2_B ,Fast GPIO output enable bit 11" "Low,High"
|
|
bitfld.long 0x04 10. " P2_A ,Fast GPIO output enable bit 10" "Low,High"
|
|
bitfld.long 0x04 9. " P2_9 ,Fast GPIO output enable bit 9" "Low,High"
|
|
bitfld.long 0x04 8. " P2_8 ,Fast GPIO output enable bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 7. " P2_7 ,Fast GPIO output enable bit 7" "Low,High"
|
|
bitfld.long 0x04 6. " P2_6 ,Fast GPIO output enable bit 6" "Low,High"
|
|
bitfld.long 0x04 5. " P2_5 ,Fast GPIO output enable bit 5" "Low,High"
|
|
bitfld.long 0x04 4. " P2_4 ,Fast GPIO output enable bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P2_3 ,Fast GPIO output enable bit 3" "Low,High"
|
|
bitfld.long 0x04 2. " P2_2 ,Fast GPIO output enable bit 2" "Low,High"
|
|
bitfld.long 0x04 1. " P2_1 ,Fast GPIO output enable bit 1" "Low,High"
|
|
bitfld.long 0x04 0. " P2_0 ,Fast GPIO output enable bit 0" "Low,High"
|
|
line.long 0x08 "FPOER3,Fast GPIO Output Enable Register 3"
|
|
bitfld.long 0x08 5. " P3_5 ,Fast GPIO output enable bit 5" "Low,High"
|
|
bitfld.long 0x08 4. " P3_4 ,Fast GPIO output enable bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 3. " P3_3 ,Fast GPIO output enable bit 3" "Low,High"
|
|
bitfld.long 0x08 2. " P3_2 ,Fast GPIO output enable bit 2" "Low,High"
|
|
bitfld.long 0x08 1. " P3_1 ,Fast GPIO output enable bit 1" "Low,High"
|
|
bitfld.long 0x08 0. " P3_0 ,Fast GPIO output enable bit 0" "Low,High"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "CRC (Cyclic Redundancy Check)"
|
|
base ad:0x40039000
|
|
width 9.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "CRCCR,CRC Control Register"
|
|
bitfld.byte 0x00 6. " FXOR ,Final XOR control bit" "None,Yes"
|
|
bitfld.byte 0x00 5. " CRCLSF ,CRC result bit-order setting bit" "MSB First,LSB First"
|
|
bitfld.byte 0x00 4. " CRCLTE ,CRC result byte-order setting bit" "Big,Little"
|
|
bitfld.byte 0x00 3. " LSBFST ,Bit-order setting bit" "MSB First,LSB First"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " LTLEND ,Byte-order setting bit" "Big,Little"
|
|
bitfld.byte 0x00 1. " CRC32 ,CRC mode selection bit" "CRC16,CRC32"
|
|
bitfld.byte 0x00 0. " INIT ,Initialization bit" "Invalid,Initialization"
|
|
if ((per.b(ad:0x40039000)&0x02)==0x02)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CRCINIT,Initial Value Register"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CRCINIT,Initial Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " D[15:0] ,Initial value bits"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CRCIN,Input Data Register"
|
|
if ((per.b(ad:0x40039000)&0x12)==0x00)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CRCR,CRC Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " D[15:0] ,CRC bits"
|
|
elif ((per.b(ad:0x40039000)&0x12)==0x10)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CRCR,CRC Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " D[31:16] ,CRC bits"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CRCR,CRC Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "MTB_DWT (Micro Trace Buffer Data Watchpoint and Trace)"
|
|
base ad:0xF0001000
|
|
width 16.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CMP_ADDR_START,Address Compare Start Trace Register"
|
|
line.long 0x04 "CMP_DATA_START,Data Compare Start Trace Register"
|
|
line.long 0x08 "CMP_MASK_START,Mask Data Compare Start Trace Register"
|
|
sif cpuis("S6E1C12*")||cpuis("S6E1C32*")||cpuis("S6E1C11*")||cpuis("S6E1C31*")
|
|
bitfld.long 0x08 31. " MSK_STA[31] ,Data compare start trace register mask bits 31" "No effect,Masked"
|
|
bitfld.long 0x08 30. " [30] ,Data compare start trace register mask bits 30" "No effect,Masked"
|
|
bitfld.long 0x08 29. " [29] ,Data compare start trace register mask bits 29" "No effect,Masked"
|
|
bitfld.long 0x08 28. " [28] ,Data compare start trace register mask bits 28" "No effect,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 27. " [27] ,Data compare start trace register mask bits 27" "No effect,Masked"
|
|
bitfld.long 0x08 26. " [26] ,Data compare start trace register mask bits 26" "No effect,Masked"
|
|
bitfld.long 0x08 25. " [25] ,Data compare start trace register mask bits 25" "No effect,Masked"
|
|
bitfld.long 0x08 24. " [24] ,Data compare start trace register mask bits 24" "No effect,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 23. " [23] ,Data compare start trace register mask bits 23" "No effect,Masked"
|
|
bitfld.long 0x08 22. " [22] ,Data compare start trace register mask bits 22" "No effect,Masked"
|
|
bitfld.long 0x08 21. " [21] ,Data compare start trace register mask bits 21" "No effect,Masked"
|
|
bitfld.long 0x08 20. " [20] ,Data compare start trace register mask bits 20" "No effect,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 19. " [19] ,Data compare start trace register mask bits 19" "No effect,Masked"
|
|
bitfld.long 0x08 18. " [18] ,Data compare start trace register mask bits 18" "No effect,Masked"
|
|
bitfld.long 0x08 17. " [17] ,Data compare start trace register mask bits 17" "No effect,Masked"
|
|
bitfld.long 0x08 16. " [16] ,Data compare start trace register mask bits 16" "No effect,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 15. " [15] ,Data compare start trace register mask bits 15" "No effect,Masked"
|
|
bitfld.long 0x08 14. " [14] ,Data compare start trace register mask bits 14" "No effect,Masked"
|
|
bitfld.long 0x08 13. " [13] ,Data compare start trace register mask bits 13" "No effect,Masked"
|
|
bitfld.long 0x08 12. " [12] ,Data compare start trace register mask bits 12" "No effect,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 11. " [11] ,Data compare start trace register mask bits 11" "No effect,Masked"
|
|
bitfld.long 0x08 10. " [10] ,Data compare start trace register mask bits 10" "No effect,Masked"
|
|
bitfld.long 0x08 9. " [9] ,Data compare start trace register mask bits 9" "No effect,Masked"
|
|
bitfld.long 0x08 8. " [8] ,Data compare start trace register mask bits 8" "No effect,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 7. " [7] ,Data compare start trace register mask bits 7" "No effect,Masked"
|
|
bitfld.long 0x08 6. " [6] ,Data compare start trace register mask bits 6" "No effect,Masked"
|
|
bitfld.long 0x08 5. " [5] ,Data compare start trace register mask bits 5" "No effect,Masked"
|
|
bitfld.long 0x08 4. " [4] ,Data compare start trace register mask bits 4" "No effect,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [3] ,Data compare start trace register mask bits 3" "No effect,Masked"
|
|
bitfld.long 0x08 2. " [2] ,Data compare start trace register mask bits 2" "No effect,Masked"
|
|
bitfld.long 0x08 1. " [1] ,Data compare start trace register mask bits 1" "No effect,Masked"
|
|
bitfld.long 0x08 0. " [0] ,Data compare start trace register mask bits 0" "No effect,Masked"
|
|
endif
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "CMP_ADDR_STOP,Address Compare Stop Trace Register"
|
|
line.long 0x04 "CMP_DATA_STOP,Data Compare Stop Trace Register"
|
|
line.long 0x08 "CMP_MASK_STOP,Mask Data Compare Stop Trace Register"
|
|
sif cpuis("S6E1C12*")||cpuis("S6E1C32*")||cpuis("S6E1C11*")||cpuis("S6E1C31*")
|
|
bitfld.long 0x08 31. " MSK_STO[31] ,Data compare stop trace register mask bits 31" "No effect,Masked"
|
|
bitfld.long 0x08 30. " [30] ,Data compare stop trace register mask bits 30" "No effect,Masked"
|
|
bitfld.long 0x08 29. " [29] ,Data compare stop trace register mask bits 29" "No effect,Masked"
|
|
bitfld.long 0x08 28. " [28] ,Data compare stop trace register mask bits 28" "No effect,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 27. " [27] ,Data compare stop trace register mask bits 27" "No effect,Masked"
|
|
bitfld.long 0x08 26. " [26] ,Data compare stop trace register mask bits 26" "No effect,Masked"
|
|
bitfld.long 0x08 25. " [25] ,Data compare stop trace register mask bits 25" "No effect,Masked"
|
|
bitfld.long 0x08 24. " [24] ,Data compare stop trace register mask bits 24" "No effect,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 23. " [23] ,Data compare stop trace register mask bits 23" "No effect,Masked"
|
|
bitfld.long 0x08 22. " [22] ,Data compare stop trace register mask bits 22" "No effect,Masked"
|
|
bitfld.long 0x08 21. " [21] ,Data compare stop trace register mask bits 21" "No effect,Masked"
|
|
bitfld.long 0x08 20. " [20] ,Data compare stop trace register mask bits 20" "No effect,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 19. " [19] ,Data compare stop trace register mask bits 19" "No effect,Masked"
|
|
bitfld.long 0x08 18. " [18] ,Data compare stop trace register mask bits 18" "No effect,Masked"
|
|
bitfld.long 0x08 17. " [17] ,Data compare stop trace register mask bits 17" "No effect,Masked"
|
|
bitfld.long 0x08 16. " [16] ,Data compare stop trace register mask bits 16" "No effect,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 15. " [15] ,Data compare stop trace register mask bits 15" "No effect,Masked"
|
|
bitfld.long 0x08 14. " [14] ,Data compare stop trace register mask bits 14" "No effect,Masked"
|
|
bitfld.long 0x08 13. " [13] ,Data compare stop trace register mask bits 13" "No effect,Masked"
|
|
bitfld.long 0x08 12. " [12] ,Data compare stop trace register mask bits 12" "No effect,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 11. " [11] ,Data compare stop trace register mask bits 11" "No effect,Masked"
|
|
bitfld.long 0x08 10. " [10] ,Data compare stop trace register mask bits 10" "No effect,Masked"
|
|
bitfld.long 0x08 9. " [9] ,Data compare stop trace register mask bits 9" "No effect,Masked"
|
|
bitfld.long 0x08 8. " [8] ,Data compare stop trace register mask bits 8" "No effect,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 7. " [7] ,Data compare stop trace register mask bits 7" "No effect,Masked"
|
|
bitfld.long 0x08 6. " [6] ,Data compare stop trace register mask bits 6" "No effect,Masked"
|
|
bitfld.long 0x08 5. " [5] ,Data compare stop trace register mask bits 5" "No effect,Masked"
|
|
bitfld.long 0x08 4. " [4] ,Data compare stop trace register mask bits 4" "No effect,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [3] ,Data compare stop trace register mask bits 3" "No effect,Masked"
|
|
bitfld.long 0x08 2. " [2] ,Data compare stop trace register mask bits 2" "No effect,Masked"
|
|
bitfld.long 0x08 1. " [1] ,Data compare stop trace register mask bits 1" "No effect,Masked"
|
|
bitfld.long 0x08 0. " [0] ,Data compare stop trace register mask bits 0" "No effect,Masked"
|
|
endif
|
|
textline " "
|
|
width 6.
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FCT,MTB_DWT Function Register"
|
|
bitfld.long 0x00 6.--7. " DSTP ,Data size stop bits" "Byte,Half-word,Word,?..."
|
|
bitfld.long 0x00 4.--5. " DDSTA ,Data size start bits" "Byte,Half-word,Word,?..."
|
|
bitfld.long 0x00 2.--3. " STPEN ,Enable MTB_DWT stop MTB function bits" "Disabled,Read,Write,Write/Read"
|
|
bitfld.long 0x00 0.--1. " STAEN ,Enable MTB_DWT start MTB function bits" "Disabled,Read,Write,Write/Read"
|
|
rgroup.long 0xFD0++0x1F
|
|
line.long 0x10 "PID0 ,Peripheral ID0 Register"
|
|
line.long 0x14 "PID1 ,Peripheral ID1 Register"
|
|
line.long 0x18 "PID2 ,Peripheral ID2 Register"
|
|
line.long 0x1C "PID3 ,Peripheral ID3 Register"
|
|
line.long 0x00 "PID4 ,Peripheral ID4 Register"
|
|
line.long 0x04 "PID5 ,Peripheral ID5 Register"
|
|
line.long 0x08 "PID6 ,Peripheral ID6 Register"
|
|
line.long 0x0C "PID7 ,Peripheral ID7 Register"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 Register"
|
|
line.long 0x04 "CID1,Component ID1 Register"
|
|
line.long 0x08 "CID2,Component ID2 Register"
|
|
line.long 0x0C "CID3,Component ID3 Register"
|
|
width 0xB
|
|
tree.end
|
|
tree "Flash Memory"
|
|
base ad:0x40000000
|
|
width 8.
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "FRWTR,Flash Read Wait Register"
|
|
sif cpuis("S6E1C*")
|
|
bitfld.byte 0x00 0.--2. " RWT ,Read wait cycle" "0 cycle,0-1 cycle,,0-3 cycle,,,,Fixed"
|
|
else
|
|
bitfld.byte 0x00 0.--1. " RWT ,Read wait cycle" "0 cycle,0-1 cycle,,Fixed"
|
|
endif
|
|
rgroup.byte 0x08++0x00
|
|
line.byte 0x00 "FSTR,Flash Status Register"
|
|
bitfld.byte 0x00 5. " PGMS ,Flash program status" "Not written,Written"
|
|
bitfld.byte 0x00 4. " SERS ,Flash sector erase status" "Not erased,Erased"
|
|
bitfld.byte 0x00 3. " ESPS ,Flash erase suspend status" "Not suspended,Suspended"
|
|
bitfld.byte 0x00 2. " CERS ,Flash chip erase status" "Not erased,Erased"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " HNG ,Flash hang status" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " RDY ,Flash ready status" "Not ready,Ready"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "FICR,Flash Interrupt Control Register"
|
|
bitfld.byte 0x00 1. " HANGIE ,HANG interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " RDYIE ,RDY interrupt enable" "Disabled,Enabled"
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "FISR,Flash Interrupt Status Register"
|
|
bitfld.byte 0x00 1. " HANGIF ,HANG interrupt flag" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " RDYIF ,RDY interrupt flag" "Not detected,Detected"
|
|
wgroup.byte 0x28++0x00
|
|
line.byte 0x00 "FICLR,Flash Interrupt Clear Register"
|
|
bitfld.byte 0x00 1. " HANGC ,HANG interrupt clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " RDYC ,RDY interrupt flag" "No effect,Clear"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "CRTRMM,CR Trimming Data Mirror Register"
|
|
bitfld.long 0x00 16.--20. " TTRMM ,CR temperature trimming data mirror bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--9. 1. " TRMM ,CR trimming data mirror bit"
|
|
group.byte 0x010++0x00
|
|
line.byte 0x00 "FSYNDN,Flash Sync Down Register"
|
|
bitfld.byte 0x00 0.--3. " SD ,Sync down (wait cycles)" ",1 cycle,,3 cycles,,5 cycles,,7 cycles,,9 cycles,,11 cycles,,13 cycles,,15 cycles"
|
|
width 0xB
|
|
tree.end
|
|
sif cpuis("S6E1C*")
|
|
tree "UIDR (Unique ID Register)"
|
|
base ad:0x40000200
|
|
width 7.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "UIDR0,Unique ID Register 0"
|
|
hexmask.long 0x00 4.--31. 1. " UID ,Unique ID register[27:0]"
|
|
line.long 0x04 "UIDR1,Unique ID Register 1"
|
|
hexmask.long.word 0x04 0.--12. 1. " UID ,Unique ID register[40:28]"
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "UIDR (Unique ID Register)"
|
|
base ad:0x40000200
|
|
width 4.
|
|
rgroup.byte 0x00++0x03 "UIDR_0"
|
|
line.byte 0x00 "LL,Unique ID Register 0 LL"
|
|
bitfld.byte 0x00 4.--7. " UID[3:0] ,Unique ID 0-3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "LH,Unique ID Register 0 LH"
|
|
hexmask.byte 0x01 0.--7. 1. " UID[11:4] ,Unique ID 11-4"
|
|
line.byte 0x02 "HL,Unique ID Register 0 HL"
|
|
hexmask.byte 0x02 0.--7. 1. " UID[19:12] ,Unique ID 19-12"
|
|
line.byte 0x03 "HH,Unique ID Register 0 HH"
|
|
hexmask.byte 0x03 0.--7. 1. " UID[27:20] ,Unique ID 27-20"
|
|
rgroup.byte 0x04++0x03 "UIDR_1"
|
|
line.byte 0x00 "LL,Unique ID Register 1 LL"
|
|
bitfld.byte 0x00 4.--7. " UID[3:0] ,Unique ID 0-3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "LH,Unique ID Register 1 LH"
|
|
hexmask.byte 0x01 0.--7. 1. " UID[11:4] ,Unique ID 11-4"
|
|
line.byte 0x02 "HL,Unique ID Register 1 HL"
|
|
hexmask.byte 0x02 0.--7. 1. " UID[19:12] ,Unique ID 19-12"
|
|
line.byte 0x03 "HH,Unique ID Register 1 HH"
|
|
hexmask.byte 0x03 0.--7. 1. " UID[27:20] ,Unique ID 27-20"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
sif cpuis("S6E1C*")
|
|
tree "DSTC (Descriptor System Data Transfer Controller)"
|
|
base ad:0x40061000
|
|
width 19.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "DESTP,Register Sets The Start Address Of The Descriptor Area"
|
|
line.long 0x04 "HWDESP,Hardware DES pointer"
|
|
hexmask.long.word 0x04 16.--29. 1. " HWDESP ,Register sets the DESP that the DSTC refers to"
|
|
hexmask.long.byte 0x04 0.--7. 1. " CHANNEL ,Register sets the the channel number for the HWDESP"
|
|
group.byte 0x08++0x01
|
|
line.byte 0x00 "CMD,Register Issues A Command To The DSTC And Reads The State Of The DSTC"
|
|
bitfld.byte 0x00 2.--7. " CMD[7:2] ,Command issued to the DSTC" ",Standby release,Standby transition,,SWCLR,,,,ERCLR,,,,,,,,,,,,,,,,,,,,,,,,MKCLR,?..."
|
|
rbitfld.byte 0x00 0.--1. " CMD[1:0] ,DSTC status" "Normal,Standby,Transition 1,Transition 2"
|
|
line.byte 0x01 "CFG,Register Sets Operation Functions Of The DSTC"
|
|
bitfld.byte 0x01 4.--6. " SWPR ,Software transfer priority" "Highest,1/2,1/3,1/7,1/15,1/31,1/63,Lowest"
|
|
bitfld.byte 0x01 3. " ESTE ,Error stop enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " RBDIS ,Read skip buffer disable" "Yes,No"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " ERINTE ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " SWINTE ,Software interrupt enable" "Disabled,Enabled"
|
|
group.word 0x0A++0x01
|
|
line.word 0x00 "SWTR,Software Trigger Register"
|
|
rbitfld.word 0x00 15. " SWST ,Software status" "Transfer failed,Transfer success"
|
|
rbitfld.word 0x00 14. " SWREQ ,Software request" "Not requested,Requested"
|
|
hexmask.word 0x00 0.--13. 1. " SWDESP ,Software DES pointer"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "MONERS,Register Shows Details Of A Transfer Error That Has Occurred"
|
|
hexmask.long.word 0x00 16.--29. 1. " EDESP ,Error DES pointer"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ECH ,Error hardware channel"
|
|
bitfld.long 0x00 6. " EHS ,Error hardware software" "SW,HW"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ESTOP ,Error stop" "No error,Error"
|
|
bitfld.long 0x00 3. " DER ,Double error" "No error,Error"
|
|
bitfld.long 0x00 0.--2. " EST ,Error status" "No error,Source access,Destination access,Transfer stopped compulsorily,DES access,DES open,?..."
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "DREQENB[31:0],DMA Request Enable (Channels - 31:0)"
|
|
bitfld.long 0x00 31. " DREQENB31 ,HW Channel 31 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DREQENB30 ,HW Channel 30 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " DREQENB29 ,HW Channel 29 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DREQENB28 ,HW Channel 28 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DREQENB27 ,HW Channel 27 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " DREQENB26 ,HW Channel 26 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " DREQENB25 ,HW Channel 25 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DREQENB24 ,HW Channel 24 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DREQENB23 ,HW Channel 23 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " DREQENB22 ,HW Channel 22 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " DREQENB21 ,HW Channel 21 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " DREQENB20 ,HW Channel 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DREQENB19 ,HW Channel 19 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DREQENB18 ,HW Channel 18 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " DREQENB17 ,HW Channel 17 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DREQENB16 ,HW Channel 16 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DREQENB15 ,HW Channel 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DREQENB14 ,HW Channel 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DREQENB13 ,HW Channel 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DREQENB12 ,HW Channel 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DREQENB11 ,HW Channel 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DREQENB10 ,HW Channel 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DREQENB09 ,HW Channel 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DREQENB08 ,HW Channel 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DREQENB07 ,HW Channel 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DREQENB06 ,HW Channel 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DREQENB05 ,HW Channel 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DREQENB04 ,HW Channel 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DREQENB03 ,HW Channel 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DREQENB02 ,HW Channel 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DREQENB01 ,HW Channel 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DREQENB00 ,HW Channel 0 Enable" "Disabled,Enabled"
|
|
line.long 0x04 "DREQENB[63:32],DMA Request Enable (Channels - 63:32)"
|
|
bitfld.long 0x04 31. " DREQENB63 ,HW Channel 63 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " DREQENB62 ,HW Channel 62 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " DREQENB61 ,HW Channel 61 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " DREQENB60 ,HW Channel 60 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " DREQENB59 ,HW Channel 59 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " DREQENB58 ,HW Channel 58 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " DREQENB57 ,HW Channel 57 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " DREQENB56 ,HW Channel 56 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " DREQENB55 ,HW Channel 55 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " DREQENB54 ,HW Channel 54 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " DREQENB53 ,HW Channel 53 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " DREQENB52 ,HW Channel 52 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " DREQENB51 ,HW Channel 51 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " DREQENB50 ,HW Channel 50 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " DREQENB49 ,HW Channel 49 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " DREQENB48 ,HW Channel 48 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " DREQENB47 ,HW Channel 47 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " DREQENB46 ,HW Channel 46 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " DREQENB45 ,HW Channel 45 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " DREQENB44 ,HW Channel 44 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " DREQENB43 ,HW Channel 43 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " DREQENB42 ,HW Channel 42 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " DREQENB41 ,HW Channel 41 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " DREQENB40 ,HW Channel 40 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " DREQENB39 ,HW Channel 39 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " DREQENB38 ,HW Channel 38 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " DREQENB37 ,HW Channel 37 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " DREQENB36 ,HW Channel 36 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DREQENB35 ,HW Channel 35 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " DREQENB34 ,HW Channel 34 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " DREQENB33 ,HW Channel 33 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " DREQENB32 ,HW Channel 32 Enable" "Disabled,Enabled"
|
|
sif !cpuis("S6E1C12*")&&!cpuis("S6E1C32*")&&!cpuis("S6E1C11*")&&!cpuis("S6E1C31*")
|
|
group.long 0x18++0x07
|
|
line.long 0x00 "DREQENB[95:64],DMA Request Enable (Channels - 95:64)"
|
|
bitfld.long 0x00 31. " DREQENB95 ,HW Channel 95 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DREQENB94 ,HW Channel 94 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " DREQENB93 ,HW Channel 93 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DREQENB92 ,HW Channel 92 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DREQENB91 ,HW Channel 91 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " DREQENB90 ,HW Channel 90 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " DREQENB89 ,HW Channel 89 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DREQENB88 ,HW Channel 88 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DREQENB87 ,HW Channel 87 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " DREQENB86 ,HW Channel 86 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " DREQENB85 ,HW Channel 85 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " DREQENB84 ,HW Channel 84 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DREQENB83 ,HW Channel 83 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DREQENB82 ,HW Channel 82 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " DREQENB81 ,HW Channel 81 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DREQENB80 ,HW Channel 80 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DREQENB79 ,HW Channel 79 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DREQENB78 ,HW Channel 78 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DREQENB77 ,HW Channel 77 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DREQENB76 ,HW Channel 76 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DREQENB75 ,HW Channel 75 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DREQENB74 ,HW Channel 74 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DREQENB73 ,HW Channel 73 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DREQENB72 ,HW Channel 72 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DREQENB71 ,HW Channel 71 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DREQENB70 ,HW Channel 70 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DREQENB69 ,HW Channel 69 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DREQENB68 ,HW Channel 68 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DREQENB67 ,HW Channel 67 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DREQENB66 ,HW Channel 66 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DREQENB65 ,HW Channel 65 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DREQENB64 ,HW Channel 64 Enable" "Disabled,Enabled"
|
|
line.long 0x04 "DREQENB[127:96],DMA Request Enable (Channels - 127:96)"
|
|
bitfld.long 0x04 31. " DREQENB127 ,HW Channel 127 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " DREQENB126 ,HW Channel 126 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " DREQENB125 ,HW Channel 125 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " DREQENB124 ,HW Channel 124 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " DREQENB123 ,HW Channel 123 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " DREQENB122 ,HW Channel 122 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " DREQENB121 ,HW Channel 121 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " DREQENB120 ,HW Channel 120 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " DREQENB119 ,HW Channel 119 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " DREQENB118 ,HW Channel 118 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " DREQENB117 ,HW Channel 117 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " DREQENB116 ,HW Channel 116 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " DREQENB115 ,HW Channel 115 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " DREQENB114 ,HW Channel 114 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " DREQENB113 ,HW Channel 113 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " DREQENB112 ,HW Channel 112 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " DREQENB111 ,HW Channel 111 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " DREQENB110 ,HW Channel 110 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " DREQENB109 ,HW Channel 109 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " DREQENB108 ,HW Channel 108 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " DREQENB107 ,HW Channel 107 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " DREQENB106 ,HW Channel 106 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " DREQENB105 ,HW Channel 105 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " DREQENB104 ,HW Channel 104 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " DREQENB103 ,HW Channel 103 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " DREQENB102 ,HW Channel 102 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " DREQENB101 ,HW Channel 101 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " DREQENB100 ,HW Channel 100 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DREQENB99 ,HW Channel 99 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " DREQENB98 ,HW Channel 98 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " DREQENB97 ,HW Channel 97 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " DREQENB96 ,HW Channel 96 Enable" "Disabled,Enabled"
|
|
sif cpuis("S6E2C*")
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "DREQENB[159:128],DMA Request Enable (Channels - 159:128)"
|
|
bitfld.long 0x00 31. " DREQENB159 ,HW Channel 159 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DREQENB158 ,HW Channel 158 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " DREQENB157 ,HW Channel 157 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DREQENB156 ,HW Channel 156 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DREQENB155 ,HW Channel 155 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " DREQENB154 ,HW Channel 154 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " DREQENB153 ,HW Channel 153 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DREQENB152 ,HW Channel 152 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DREQENB151 ,HW Channel 151 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " DREQENB150 ,HW Channel 150 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " DREQENB149 ,HW Channel 149 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " DREQENB148 ,HW Channel 148 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DREQENB147 ,HW Channel 147 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DREQENB146 ,HW Channel 146 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " DREQENB145 ,HW Channel 145 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DREQENB144 ,HW Channel 144 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DREQENB143 ,HW Channel 143 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DREQENB142 ,HW Channel 142 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DREQENB141 ,HW Channel 141 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DREQENB140 ,HW Channel 140 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DREQENB139 ,HW Channel 139 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DREQENB138 ,HW Channel 138 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DREQENB137 ,HW Channel 137 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DREQENB136 ,HW Channel 136 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DREQENB135 ,HW Channel 135 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DREQENB134 ,HW Channel 134 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DREQENB133 ,HW Channel 133 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DREQENB132 ,HW Channel 132 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DREQENB131 ,HW Channel 131 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DREQENB130 ,HW Channel 130 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DREQENB129 ,HW Channel 129 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DREQENB128 ,HW Channel 128 Enable" "Disabled,Enabled"
|
|
line.long 0x04 "DREQENB[191:160],DMA Request Enable (Channels - 191:160)"
|
|
bitfld.long 0x04 31. " DREQENB191 ,HW Channel 191 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " DREQENB190 ,HW Channel 190 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " DREQENB189 ,HW Channel 189 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " DREQENB188 ,HW Channel 188 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " DREQENB187 ,HW Channel 187 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " DREQENB186 ,HW Channel 186 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " DREQENB185 ,HW Channel 185 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " DREQENB184 ,HW Channel 184 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " DREQENB183 ,HW Channel 183 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " DREQENB182 ,HW Channel 182 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " DREQENB181 ,HW Channel 181 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " DREQENB180 ,HW Channel 180 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " DREQENB179 ,HW Channel 179 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " DREQENB178 ,HW Channel 178 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " DREQENB177 ,HW Channel 177 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " DREQENB176 ,HW Channel 176 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " DREQENB175 ,HW Channel 175 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " DREQENB174 ,HW Channel 174 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " DREQENB173 ,HW Channel 173 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " DREQENB172 ,HW Channel 172 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " DREQENB171 ,HW Channel 171 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " DREQENB170 ,HW Channel 170 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " DREQENB169 ,HW Channel 169 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " DREQENB168 ,HW Channel 168 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " DREQENB167 ,HW Channel 167 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " DREQENB166 ,HW Channel 166 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " DREQENB165 ,HW Channel 165 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " DREQENB164 ,HW Channel 164 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DREQENB163 ,HW Channel 163 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " DREQENB162 ,HW Channel 162 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " DREQENB161 ,HW Channel 161 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " DREQENB160 ,HW Channel 160 Enable" "Disabled,Enabled"
|
|
line.long 0x08 "DREQENB[223:192],DMA Request Enable (Channels - 223:192)"
|
|
bitfld.long 0x08 31. " DREQENB223 ,HW Channel 223 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " DREQENB222 ,HW Channel 222 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " DREQENB221 ,HW Channel 221 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " DREQENB220 ,HW Channel 220 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " DREQENB219 ,HW Channel 219 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " DREQENB219 ,HW Channel 219 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " DREQENB218 ,HW Channel 218 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " DREQENB217 ,HW Channel 217 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " DREQENB216 ,HW Channel 216 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " DREQENB215 ,HW Channel 215 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " DREQENB214 ,HW Channel 214 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " DREQENB213 ,HW Channel 213 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " DREQENB212 ,HW Channel 212 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " DREQENB211 ,HW Channel 211 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " DREQENB210 ,HW Channel 210 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " DREQENB209 ,HW Channel 209 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " DREQENB208 ,HW Channel 208 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " DREQENB207 ,HW Channel 207 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " DREQENB206 ,HW Channel 206 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " DREQENB205 ,HW Channel 205 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " DREQENB204 ,HW Channel 204 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " DREQENB203 ,HW Channel 203 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " DREQENB202 ,HW Channel 202 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " DREQENB201 ,HW Channel 201 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " DREQENB200 ,HW Channel 200 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " DREQENB199 ,HW Channel 199 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " DREQENB198 ,HW Channel 198 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " DREQENB197 ,HW Channel 197 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DREQENB196 ,HW Channel 196 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " DREQENB195 ,HW Channel 195 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " DREQENB194 ,HW Channel 194 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " DREQENB193 ,HW Channel 193 Enable" "Disabled,Enabled"
|
|
line.long 0x0C "DREQENB[255:224],DMA Request Enable (channels - 255:224)"
|
|
bitfld.long 0x0C 31. " DREQENB255 ,HW Channel 255 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " DREQENB254 ,HW Channel 254 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " DREQENB253 ,HW Channel 253 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " DREQENB252 ,HW Channel 252 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " DREQENB251 ,HW Channel 251 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " DREQENB250 ,HW Channel 250 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 25. " DREQENB249 ,HW Channel 249 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " DREQENB248 ,HW Channel 248 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " DREQENB247 ,HW Channel 247 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " DREQENB246 ,HW Channel 246 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " DREQENB245 ,HW Channel 245 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " DREQENB244 ,HW Channel 244 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " DREQENB243 ,HW Channel 243 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " DREQENB242 ,HW Channel 242 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " DREQENB241 ,HW Channel 241 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " DREQENB240 ,HW Channel 240 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " DREQENB239 ,HW Channel 239 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " DREQENB238 ,HW Channel 238 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " DREQENB237 ,HW Channel 237 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " DREQENB236 ,HW Channel 236 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " DREQENB235 ,HW Channel 235 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " DREQENB234 ,HW Channel 234 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " DREQENB233 ,HW Channel 233 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " DREQENB232 ,HW Channel 232 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " DREQENB231 ,HW Channel 231 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " DREQENB230 ,HW Channel 230 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " DREQENB229 ,HW Channel 229 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " DREQENB228 ,HW Channel 227 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " DREQENB227 ,HW Channel 227 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " DREQENB226 ,HW Channel 226 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " DREQENB225 ,HW Channel 225 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " DREQENB224 ,HW Channel 224 Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.long 0x30++0x07
|
|
line.long 0x00 "HWINT[31:0],Hardware Transfer Interrupt (Channels - 31:0)"
|
|
bitfld.long 0x00 31. " HWINT31 ,HW transfer started has ended normally (Channel 31)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " HWINT30 ,HW transfer started has ended normally (Channel 30)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 29. " HWINT29 ,HW transfer started has ended normally (Channel 29)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 28. " HWINT28 ,HW transfer started has ended normally (Channel 28)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 27. " HWINT27 ,HW transfer started has ended normally (Channel 27)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26. " HWINT26 ,HW transfer started has ended normally (Channel 26)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 25. " HWINT25 ,HW transfer started has ended normally (Channel 25)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " HWINT24 ,HW transfer started has ended normally (Channel 24)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 23. " HWINT23 ,HW transfer started has ended normally (Channel 23)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " HWINT22 ,HW transfer started has ended normally (Channel 22)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 21. " HWINT21 ,HW transfer started has ended normally (Channel 21)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " HWINT20 ,HW transfer started has ended normally (Channel 20)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 19. " HWINT19 ,HW transfer started has ended normally (Channel 19)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " HWINT18 ,HW transfer started has ended normally (Channel 18)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " HWINT17 ,HW transfer started has ended normally (Channel 17)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 16. " HWINT16 ,HW transfer started has ended normally (Channel 16)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 15. " HWINT15 ,HW transfer started has ended normally (Channel 15)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " HWINT14 ,HW transfer started has ended normally (Channel 14)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " HWINT13 ,HW transfer started has ended normally (Channel 13)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " HWINT12 ,HW transfer started has ended normally (Channel 12)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " HWINT11 ,HW transfer started has ended normally (Channel 11)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " HWINT10 ,HW transfer started has ended normally (Channel 10)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " HWINT09 ,HW transfer started has ended normally (Channel 9)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " HWINT08 ,HW transfer started has ended normally (Channel 8)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HWINT07 ,HW transfer started has ended normally (Channel 7)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " HWINT06 ,HW transfer started has ended normally (Channel 6)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " HWINT05 ,HW transfer started has ended normally (Channel 5)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " HWINT04 ,HW transfer started has ended normally (Channel 4)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " HWINT03 ,HW transfer started has ended normally (Channel 3)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " HWINT02 ,HW transfer started has ended normally (Channel 2)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " HWINT01 ,HW transfer started has ended normally (Channel 1)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " HWINT00 ,HW transfer started has ended normally (Channel 0)" "Not occurred,Occurred"
|
|
line.long 0x04 "HWINT[63:32],Hardware Transfer Interrupt (Channels - 63:32)"
|
|
bitfld.long 0x04 31. " HWINT63 ,HW transfer started has ended normally (Channel 63)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 30. " HWINT62 ,HW transfer started has ended normally (Channel 62)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 29. " HWINT61 ,HW transfer started has ended normally (Channel 61)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 28. " HWINT60 ,HW transfer started has ended normally (Channel 60)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 27. " HWINT59 ,HW transfer started has ended normally (Channel 59)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 26. " HWINT58 ,HW transfer started has ended normally (Channel 58)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 25. " HWINT57 ,HW transfer started has ended normally (Channel 57)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 24. " HWINT56 ,HW transfer started has ended normally (Channel 56)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 23. " HWINT55 ,HW transfer started has ended normally (Channel 55)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 22. " HWINT54 ,HW transfer started has ended normally (Channel 54)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 21. " HWINT53 ,HW transfer started has ended normally (Channel 53)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 20. " HWINT52 ,HW transfer started has ended normally (Channel 52)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 19. " HWINT51 ,HW transfer started has ended normally (Channel 51)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 18. " HWINT50 ,HW transfer started has ended normally (Channel 50)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 17. " HWINT49 ,HW transfer started has ended normally (Channel 49)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 16. " HWINT48 ,HW transfer started has ended normally (Channel 48)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 15. " HWINT47 ,HW transfer started has ended normally (Channel 47)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 14. " HWINT46 ,HW transfer started has ended normally (Channel 46)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 13. " HWINT45 ,HW transfer started has ended normally (Channel 45)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 12. " HWINT44 ,HW transfer started has ended normally (Channel 44)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 11. " HWINT43 ,HW transfer started has ended normally (Channel 43)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 10. " HWINT42 ,HW transfer started has ended normally (Channel 42)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 9. " HWINT41 ,HW transfer started has ended normally (Channel 41)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 8. " HWINT40 ,HW transfer started has ended normally (Channel 40)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 7. " HWINT39 ,HW transfer started has ended normally (Channel 39)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 6. " HWINT38 ,HW transfer started has ended normally (Channel 38)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 5. " HWINT37 ,HW transfer started has ended normally (Channel 37)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 4. " HWINT36 ,HW transfer started has ended normally (Channel 36)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 3. " HWINT35 ,HW transfer started has ended normally (Channel 35)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 2. " HWINT34 ,HW transfer started has ended normally (Channel 34)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 1. " HWINT33 ,HW transfer started has ended normally (Channel 33)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 0. " HWINT32 ,HW transfer started has ended normally (Channel 32)" "Not occurred,Occurred"
|
|
sif !cpuis("S6E1C12*")&&!cpuis("S6E1C32*")&&!cpuis("S6E1C11*")&&!cpuis("S6E1C31*")
|
|
rgroup.long 0x38++0x07
|
|
line.long 0x00 "HWINT[95:64],Hardware Transfer Interrupt (Channels - 95:64)"
|
|
bitfld.long 0x00 31. " HWINT95 ,HW transfer started has ended normally (Channel 95)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " HWINT94 ,HW transfer started has ended normally (Channel 94)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 29. " HWINT93 ,HW transfer started has ended normally (Channel 93)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 28. " HWINT92 ,HW transfer started has ended normally (Channel 92)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 27. " HWINT91 ,HW transfer started has ended normally (Channel 91)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26. " HWINT90 ,HW transfer started has ended normally (Channel 90)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 25. " HWINT89 ,HW transfer started has ended normally (Channel 89)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " HWINT88 ,HW transfer started has ended normally (Channel 88)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 23. " HWINT87 ,HW transfer started has ended normally (Channel 87)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " HWINT86 ,HW transfer started has ended normally (Channel 86)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 21. " HWINT85 ,HW transfer started has ended normally (Channel 85)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " HWINT84 ,HW transfer started has ended normally (Channel 84)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 19. " HWINT83 ,HW transfer started has ended normally (Channel 83)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " HWINT82 ,HW transfer started has ended normally (Channel 82)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " HWINT81 ,HW transfer started has ended normally (Channel 81)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 16. " HWINT80 ,HW transfer started has ended normally (Channel 80)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 15. " HWINT79 ,HW transfer started has ended normally (Channel 79)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " HWINT78 ,HW transfer started has ended normally (Channel 78)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " HWINT77 ,HW transfer started has ended normally (Channel 77)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " HWINT76 ,HW transfer started has ended normally (Channel 76)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " HWINT75 ,HW transfer started has ended normally (Channel 75)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " HWINT74 ,HW transfer started has ended normally (Channel 74)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " HWINT73 ,HW transfer started has ended normally (Channel 73)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " HWINT72 ,HW transfer started has ended normally (Channel 72)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HWINT71 ,HW transfer started has ended normally (Channel 71)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " HWINT70 ,HW transfer started has ended normally (Channel 70)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " HWINT69 ,HW transfer started has ended normally (Channel 69)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " HWINT68 ,HW transfer started has ended normally (Channel 68)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " HWINT67 ,HW transfer started has ended normally (Channel 67)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " HWINT66 ,HW transfer started has ended normally (Channel 66)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " HWINT65 ,HW transfer started has ended normally (Channel 65)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " HWINT64 ,HW transfer started has ended normally (Channel 64)" "Not occurred,Occurred"
|
|
line.long 0x04 "HWINT[127:96],Hardware Transfer Interrupt (Channels - 127:96)"
|
|
bitfld.long 0x04 31. " HWINT127 ,HW transfer started has ended normally (Channel 127)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 30. " HWINT126 ,HW transfer started has ended normally (Channel 126)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 29. " HWINT125 ,HW transfer started has ended normally (Channel 125)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 28. " HWINT124 ,HW transfer started has ended normally (Channel 124)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 27. " HWINT123 ,HW transfer started has ended normally (Channel 123)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 26. " HWINT122 ,HW transfer started has ended normally (Channel 122)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 25. " HWINT121 ,HW transfer started has ended normally (Channel 121)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 24. " HWINT120 ,HW transfer started has ended normally (Channel 120)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 23. " HWINT119 ,HW transfer started has ended normally (Channel 119)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 22. " HWINT118 ,HW transfer started has ended normally (Channel 118)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 21. " HWINT117 ,HW transfer started has ended normally (Channel 117)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 20. " HWINT116 ,HW transfer started has ended normally (Channel 116)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 19. " HWINT115 ,HW transfer started has ended normally (Channel 115)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 18. " HWINT114 ,HW transfer started has ended normally (Channel 114)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 17. " HWINT113 ,HW transfer started has ended normally (Channel 113)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 16. " HWINT112 ,HW transfer started has ended normally (Channel 112)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 15. " HWINT111 ,HW transfer started has ended normally (Channel 111)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 14. " HWINT110 ,HW transfer started has ended normally (Channel 110)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 13. " HWINT109 ,HW transfer started has ended normally (Channel 109)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 12. " HWINT108 ,HW transfer started has ended normally (Channel 108)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 11. " HWINT107 ,HW transfer started has ended normally (Channel 107)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 10. " HWINT106 ,HW transfer started has ended normally (Channel 106)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 9. " HWINT105 ,HW transfer started has ended normally (Channel105)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 8. " HWINT104 ,HW transfer started has ended normally (Channel104)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 7. " HWINT103 ,HW transfer started has ended normally (Channel 103)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 6. " HWINT102 ,HW transfer started has ended normally (Channel 102)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 5. " HWINT101 ,HW transfer started has ended normally (Channel 101)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 4. " HWINT100 ,HW transfer started has ended normally (Channel 100)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 3. " HWINT99 ,HW transfer started has ended normally (Channel 99)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 2. " HWINT98 ,HW transfer started has ended normally (Channel 98)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 1. " HWINT97 ,HW transfer started has ended normally (Channel 97)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 0. " HWINT96 ,HW transfer started has ended normally (Channel 96)" "Not occurred,Occurred"
|
|
sif cpuis("S6E2C*")
|
|
rgroup.long 0x40++0x0F
|
|
line.long 0x00 "HWINT[159:128],Hardware Transfer Interrupt (Channels - 128:159)"
|
|
bitfld.long 0x00 31. " HWINT159 ,HW transfer started has ended normally (Channel 159)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " HWINT158 ,HW transfer started has ended normally (Channel 158)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 29. " HWINT157 ,HW transfer started has ended normally (Channel 157)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 28. " HWINT156 ,HW transfer started has ended normally (Channel 156)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 27. " HWINT155 ,HW transfer started has ended normally (Channel 155)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26. " HWINT154 ,HW transfer started has ended normally (Channel 154)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 25. " HWINT153 ,HW transfer started has ended normally (Channel 153)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " HWINT152 ,HW transfer started has ended normally (Channel 152)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 23. " HWINT151 ,HW transfer started has ended normally (Channel 151)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " HWINT150 ,HW transfer started has ended normally (Channel 150)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 21. " HWINT149 ,HW transfer started has ended normally (Channel 149)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " HWINT148 ,HW transfer started has ended normally (Channel 148)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 19. " HWINT147 ,HW transfer started has ended normally (Channel 147)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " HWINT146 ,HW transfer started has ended normally (Channel 146)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " HWINT145 ,HW transfer started has ended normally (Channel 145)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 16. " HWINT144 ,HW transfer started has ended normally (Channel 144)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 15. " HWINT143 ,HW transfer started has ended normally (Channel 143)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " HWINT142 ,HW transfer started has ended normally (Channel 142)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " HWINT141 ,HW transfer started has ended normally (Channel 141)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " HWINT140 ,HW transfer started has ended normally (Channel 140)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " HWINT139 ,HW transfer started has ended normally (Channel 139)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " HWINT138 ,HW transfer started has ended normally (Channel 138)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " HWINT137 ,HW transfer started has ended normally (Channel 137)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " HWINT136 ,HW transfer started has ended normally (Channe1 136)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HWINT135 ,HW transfer started has ended normally (Channel 135)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " HWINT134 ,HW transfer started has ended normally (Channel 134)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " HWINT133 ,HW transfer started has ended normally (Channel 133)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " HWINT132 ,HW transfer started has ended normally (Channel 132)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " HWINT131 ,HW transfer started has ended normally (Channel 131)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " HWINT130 ,HW transfer started has ended normally (Channel 130)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " HWINT129 ,HW transfer started has ended normally (Channel 129)" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " HWINT128 ,HW transfer started has ended normally (Channel 128)" "Not occurred,Occurred"
|
|
line.long 0x04 "HWINT[191:160],Hardware Transfer Interrupt (Channels - 191:160)"
|
|
bitfld.long 0x04 31. " HWINT191 ,HW transfer started has ended normally (Channel 191)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 30. " HWINT190 ,HW transfer started has ended normally (Channel 190)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 29. " HWINT189 ,HW transfer started has ended normally (Channel 189)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 28. " HWINT188 ,HW transfer started has ended normally (Channel 188)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 27. " HWINT187 ,HW transfer started has ended normally (Channel 187)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 26. " HWINT186 ,HW transfer started has ended normally (Channel 186)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 25. " HWINT185 ,HW transfer started has ended normally (Channel 185)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 24. " HWINT184 ,HW transfer started has ended normally (Channel 184)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 23. " HWINT183 ,HW transfer started has ended normally (Channel 183)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 22. " HWINT182 ,HW transfer started has ended normally (Channel 182)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 21. " HWINT181 ,HW transfer started has ended normally (Channel 181)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 20. " HWINT180 ,HW transfer started has ended normally (Channel 180)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 19. " HWINT179 ,HW transfer started has ended normally (Channel 179)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 18. " HWINT178 ,HW transfer started has ended normally (Channel 178)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 17. " HWINT177 ,HW transfer started has ended normally (Channel 177)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 16. " HWINT176 ,HW transfer started has ended normally (Channel 176)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 15. " HWINT175 ,HW transfer started has ended normally (Channel 175)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 14. " HWINT174 ,HW transfer started has ended normally (Channel 174)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 13. " HWINT173 ,HW transfer started has ended normally (Channel 173)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 12. " HWINT172 ,HW transfer started has ended normally (Channel 172)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 11. " HWINT171 ,HW transfer started has ended normally (Channel 171)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 10. " HWINT170 ,HW transfer started has ended normally (Channel 170)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 9. " HWINT169 ,HW transfer started has ended normally (Channel 169)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 8. " HWINT168 ,HW transfer started has ended normally (Channe1 168)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 7. " HWINT167 ,HW transfer started has ended normally (Channel 167)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 6. " HWINT166 ,HW transfer started has ended normally (Channel 166)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 5. " HWINT165 ,HW transfer started has ended normally (Channel 165)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 4. " HWINT164 ,HW transfer started has ended normally (Channel 164)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 3. " HWINT163 ,HW transfer started has ended normally (Channel 163)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 2. " HWINT162 ,HW transfer started has ended normally (Channel 162)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 1. " HWINT161 ,HW transfer started has ended normally (Channel 161)" "Not occurred,Occurred"
|
|
bitfld.long 0x04 0. " HWINT160 ,HW transfer started has ended normally (Channel 160)" "Not occurred,Occurred"
|
|
line.long 0x08 "HWINT[223:192],Hardware Transfer Interrupt (Channels - 223:192)"
|
|
bitfld.long 0x08 31. " HWINT223 ,HW transfer started has ended normally (Channel 223)" "Not occurred,Occurred"
|
|
bitfld.long 0x08 30. " HWINT222 ,HW transfer started has ended normally (Channel 222)" "Not occurred,Occurred"
|
|
bitfld.long 0x08 29. " HWINT221 ,HW transfer started has ended normally (Channel 221)" "Not occurred,Occurred"
|
|
bitfld.long 0x08 28. " HWINT220 ,HW transfer started has ended normally (Channel 220)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x08 27. " HWINT219 ,HW transfer started has ended normally (Channel 219)" "Not occurred,Occurred"
|
|
bitfld.long 0x08 26. " HWINT218 ,HW transfer started has ended normally (Channel 218)" "Not occurred,Occurred"
|
|
bitfld.long 0x08 25. " HWINT217 ,HW transfer started has ended normally (Channel 217)" "Not occurred,Occurred"
|
|
bitfld.long 0x08 24. " HWINT216 ,HW transfer started has ended normally (Channel 216)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x08 23. " HWINT215 ,HW transfer started has ended normally (Channel 215)" "Not occurred,Occurred"
|
|
bitfld.long 0x08 22. " HWINT214 ,HW transfer started has ended normally (Channel 214)" "Not occurred,Occurred"
|
|
bitfld.long 0x08 21. " HWINT213 ,HW transfer started has ended normally (Channel 213)" "Not occurred,Occurred"
|
|
bitfld.long 0x08 20. " HWINT212 ,HW transfer started has ended normally (Channel 212)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x08 19. " HWINT211 ,HW transfer started has ended normally (Channel 211)" "Not occurred,Occurred"
|
|
bitfld.long 0x08 18. " HWINT210 ,HW transfer started has ended normally (Channel 210)" "Not occurred,Occurred"
|
|
bitfld.long 0x08 17. " HWINT209 ,HW transfer started has ended normally (Channel 209)" "Not occurred,Occurred"
|
|
bitfld.long 0x08 16. " HWINT208 ,HW transfer started has ended normally (Channel 208)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x08 15. " HWINT207 ,HW transfer started has ended normally (Channel 207)" "Not occurred,Occurred"
|
|
bitfld.long 0x08 14. " HWINT206 ,HW transfer started has ended normally (Channel 206)" "Not occurred,Occurred"
|
|
bitfld.long 0x08 13. " HWINT205 ,HW transfer started has ended normally (Channel 205)" "Not occurred,Occurred"
|
|
bitfld.long 0x08 12. " HWINT204 ,HW transfer started has ended normally (Channel 204)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x08 11. " HWINT203 ,HW transfer started has ended normally (Channel 203)" "Not occurred,Occurred"
|
|
bitfld.long 0x08 10. " HWINT202 ,HW transfer started has ended normally (Channel 202)" "Not occurred,Occurred"
|
|
bitfld.long 0x08 9. " HWINT201 ,HW transfer started has ended normally (Channel 201)" "Not occurred,Occurred"
|
|
bitfld.long 0x08 8. " HWINT200 ,HW transfer started has ended normally (Channe1 200)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x08 7. " HWINT199 ,HW transfer started has ended normally (Channel 199)" "Not occurred,Occurred"
|
|
bitfld.long 0x08 6. " HWINT198 ,HW transfer started has ended normally (Channel 198)" "Not occurred,Occurred"
|
|
bitfld.long 0x08 5. " HWINT197 ,HW transfer started has ended normally (Channel 197)" "Not occurred,Occurred"
|
|
bitfld.long 0x08 4. " HWINT196 ,HW transfer started has ended normally (Channel 196)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x08 3. " HWINT195 ,HW transfer started has ended normally (Channel 195)" "Not occurred,Occurred"
|
|
bitfld.long 0x08 2. " HWINT194 ,HW transfer started has ended normally (Channel 194)" "Not occurred,Occurred"
|
|
bitfld.long 0x08 1. " HWINT193 ,HW transfer started has ended normally (Channel 193)" "Not occurred,Occurred"
|
|
bitfld.long 0x08 0. " HWINT192 ,HW transfer started has ended normally (Channel 192)" "Not occurred,Occurred"
|
|
line.long 0x0C "HWINT[255:224],Hardware Transfer Interrupt (Channels - 255:224)"
|
|
bitfld.long 0x0C 31. " HWINT255 ,HW transfer started has ended normally (Channel 255)" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 30. " HWINT254 ,HW transfer started has ended normally (Channel 254)" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 29. " HWINT253 ,HW transfer started has ended normally (Channel 253)" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 28. " HWINT252 ,HW transfer started has ended normally (Channel 252)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " HWINT251 ,HW transfer started has ended normally (Channel 251)" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 26. " HWINT250 ,HW transfer started has ended normally (Channel 250)" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 25. " HWINT249 ,HW transfer started has ended normally (Channel 249)" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 24. " HWINT248 ,HW transfer started has ended normally (Channel 248)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " HWINT247 ,HW transfer started has ended normally (Channel 247)" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 22. " HWINT246 ,HW transfer started has ended normally (Channel 246)" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 21. " HWINT245 ,HW transfer started has ended normally (Channel 245)" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 20. " HWINT244 ,HW transfer started has ended normally (Channel 244)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " HWINT243 ,HW transfer started has ended normally (Channel 243)" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 18. " HWINT242 ,HW transfer started has ended normally (Channel 242)" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 17. " HWINT241 ,HW transfer started has ended normally (Channel 241)" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 16. " HWINT240 ,HW transfer started has ended normally (Channel 240)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " HWINT239 ,HW transfer started has ended normally (Channel 239)" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 14. " HWINT238 ,HW transfer started has ended normally (Channel 238)" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 13. " HWINT237 ,HW transfer started has ended normally (Channel 237)" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 12. " HWINT236 ,HW transfer started has ended normally (Channel 236)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " HWINT235 ,HW transfer started has ended normally (Channel 235)" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 10. " HWINT234 ,HW transfer started has ended normally (Channel 234)" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 9. " HWINT233 ,HW transfer started has ended normally (Channel 233)" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 8. " HWINT232 ,HW transfer started has ended normally (Channe1 232)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " HWINT231 ,HW transfer started has ended normally (Channel 231)" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 6. " HWINT230 ,HW transfer started has ended normally (Channel 230)" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 5. " HWINT229 ,HW transfer started has ended normally (Channel 229)" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 4. " HWINT228 ,HW transfer started has ended normally (Channel 228)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " HWINT227 ,HW transfer started has ended normally (Channel 227)" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 2. " HWINT226 ,HW transfer started has ended normally (Channel 226)" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 1. " HWINT225 ,HW transfer started has ended normally (Channel 225)" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 0. " HWINT224 ,HW transfer started has ended normally (Channel 224)" "Not occurred,Occurred"
|
|
endif
|
|
endif
|
|
wgroup.long 0x50++0x07
|
|
line.long 0x00 "HWINTCLR[31:0],Hardware Transfer Interrupt Clear (Channels - 31:0)"
|
|
bitfld.long 0x00 31. " HWINTCLR31 ,HWINT 31 clear" "No effect,Clear"
|
|
bitfld.long 0x00 30. " HWINTCLR30 ,HWINT 30 clear" "No effect,Clear"
|
|
bitfld.long 0x00 29. " HWINTCLR29 ,HWINT 29 clear" "No effect,Clear"
|
|
bitfld.long 0x00 28. " HWINTCLR28 ,HWINT 28 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " HWINTCLR27 ,HWINT 27 clear" "No effect,Clear"
|
|
bitfld.long 0x00 26. " HWINTCLR26 ,HWINT 26 clear" "No effect,Clear"
|
|
bitfld.long 0x00 25. " HWINTCLR25 ,HWINT 25 clear" "No effect,Clear"
|
|
bitfld.long 0x00 24. " HWINTCLR24 ,HWINT 24 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " HWINTCLR23 ,HWINT 23 clear" "No effect,Clear"
|
|
bitfld.long 0x00 22. " HWINTCLR22 ,HWINT 22 clear" "No effect,Clear"
|
|
bitfld.long 0x00 21. " HWINTCLR21 ,HWINT 21 clear" "No effect,Clear"
|
|
bitfld.long 0x00 20. " HWINTCLR20 ,HWINT 20 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " HWINTCLR19 ,HWINT 19 clear" "No effect,Clear"
|
|
bitfld.long 0x00 18. " HWINTCLR18 ,HWINT 18 clear" "No effect,Clear"
|
|
bitfld.long 0x00 17. " HWINTCLR17 ,HWINT 17 clear" "No effect,Clear"
|
|
bitfld.long 0x00 16. " HWINTCLR16 ,HWINT 16 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " HWINTCLR15 ,HWINT 15 clear" "No effect,Clear"
|
|
bitfld.long 0x00 14. " HWINTCLR14 ,HWINT 14 clear" "No effect,Clear"
|
|
bitfld.long 0x00 13. " HWINTCLR13 ,HWINT 13 clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " HWINTCLR12 ,HWINT 12 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " HWINTCLR11 ,HWINT 11 clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " HWINTCLR10 ,HWINT 10 clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " HWINTCLR09 ,HWINT 9 clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " HWINTCLR08 ,HWINT 8 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HWINTCLR07 ,HWINT 7 clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " HWINTCLR06 ,HWINT 6 clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " HWINTCLR05 ,HWINT 5 clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " HWINTCLR04 ,HWINT 4 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " HWINTCLR03 ,HWINT 3 clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " HWINTCLR02 ,HWINT 2 clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " HWINTCLR01 ,HWINT 1 clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " HWINTCLR00 ,HWINT 0 clear" "No effect,Clear"
|
|
line.long 0x04 "HWINTCLR[63:32],Hardware Transfer Interrupt Clear (Channels - 63:32)"
|
|
bitfld.long 0x04 31. " HWINTCLR63 ,HWINT 63 clear" "No effect,Clear"
|
|
bitfld.long 0x04 30. " HWINTCLR62 ,HWINT 62 clear" "No effect,Clear"
|
|
bitfld.long 0x04 29. " HWINTCLR61 ,HWINT 61 clear" "No effect,Clear"
|
|
bitfld.long 0x04 28. " HWINTCLR60 ,HWINT 60 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 27. " HWINTCLR59 ,HWINT 59 clear" "No effect,Clear"
|
|
bitfld.long 0x04 26. " HWINTCLR58 ,HWINT 58 clear" "No effect,Clear"
|
|
bitfld.long 0x04 25. " HWINTCLR57 ,HWINT 57 clear" "No effect,Clear"
|
|
bitfld.long 0x04 24. " HWINTCLR56 ,HWINT 56 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 23. " HWINTCLR55 ,HWINT 55 clear" "No effect,Clear"
|
|
bitfld.long 0x04 22. " HWINTCLR54 ,HWINT 54 clear" "No effect,Clear"
|
|
bitfld.long 0x04 21. " HWINTCLR53 ,HWINT 53 clear" "No effect,Clear"
|
|
bitfld.long 0x04 20. " HWINTCLR52 ,HWINT 52 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 19. " HWINTCLR51 ,HWINT 51 clear" "No effect,Clear"
|
|
bitfld.long 0x04 18. " HWINTCLR50 ,HWINT 50 clear" "No effect,Clear"
|
|
bitfld.long 0x04 17. " HWINTCLR49 ,HWINT 49 clear" "No effect,Clear"
|
|
bitfld.long 0x04 16. " HWINTCLR48 ,HWINT 48 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 15. " HWINTCLR47 ,HWINT 47 clear" "No effect,Clear"
|
|
bitfld.long 0x04 14. " HWINTCLR46 ,HWINT 46 clear" "No effect,Clear"
|
|
bitfld.long 0x04 13. " HWINTCLR45 ,HWINT 45 clear" "No effect,Clear"
|
|
bitfld.long 0x04 12. " HWINTCLR44 ,HWINT 44 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 11. " HWINTCLR43 ,HWINT 43 clear" "No effect,Clear"
|
|
bitfld.long 0x04 10. " HWINTCLR42 ,HWINT 42 clear" "No effect,Clear"
|
|
bitfld.long 0x04 9. " HWINTCLR41 ,HWINT 41 clear" "No effect,Clear"
|
|
bitfld.long 0x04 8. " HWINTCLR40 ,HWINT 40 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " HWINTCLR39 ,HWINT 39 clear" "No effect,Clear"
|
|
bitfld.long 0x04 6. " HWINTCLR38 ,HWINT 38 clear" "No effect,Clear"
|
|
bitfld.long 0x04 5. " HWINTCLR37 ,HWINT 37 clear" "No effect,Clear"
|
|
bitfld.long 0x04 4. " HWINTCLR36 ,HWINT 36 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " HWINTCLR35 ,HWINT 35 clear" "No effect,Clear"
|
|
bitfld.long 0x04 2. " HWINTCLR34 ,HWINT 34 clear" "No effect,Clear"
|
|
bitfld.long 0x04 1. " HWINTCLR33 ,HWINT 33 clear" "No effect,Clear"
|
|
bitfld.long 0x04 0. " HWINTCLR32 ,HWINT 32 clear" "No effect,Clear"
|
|
sif !cpuis("S6E1C12*")&&!cpuis("S6E1C32*")&&!cpuis("S6E1C11*")&&!cpuis("S6E1C31*")
|
|
wgroup.long 0x58++0x07
|
|
line.long 0x00 "HWINTCLR[95:64],Hardware Transfer Interrupt Clear (Channels - 95:64)"
|
|
bitfld.long 0x00 31. " HWINTCLR95 ,HWINT 95 clear" "No effect,Clear"
|
|
bitfld.long 0x00 30. " HWINTCLR94 ,HWINT 94 clear" "No effect,Clear"
|
|
bitfld.long 0x00 29. " HWINTCLR93 ,HWINT 93 clear" "No effect,Clear"
|
|
bitfld.long 0x00 28. " HWINTCLR92 ,HWINT 92 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " HWINTCLR91 ,HWINT 91 clear" "No effect,Clear"
|
|
bitfld.long 0x00 26. " HWINTCLR90 ,HWINT 90 clear" "No effect,Clear"
|
|
bitfld.long 0x00 25. " HWINTCLR89 ,HWINT 89 clear" "No effect,Clear"
|
|
bitfld.long 0x00 24. " HWINTCLR88 ,HWINT 88 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " HWINTCLR87 ,HWINT 87 clear" "No effect,Clear"
|
|
bitfld.long 0x00 22. " HWINTCLR86 ,HWINT 86 clear" "No effect,Clear"
|
|
bitfld.long 0x00 21. " HWINTCLR85 ,HWINT 85 clear" "No effect,Clear"
|
|
bitfld.long 0x00 20. " HWINTCLR84 ,HWINT 84 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " HWINTCLR83 ,HWINT 83 clear" "No effect,Clear"
|
|
bitfld.long 0x00 18. " HWINTCLR82 ,HWINT 82 clear" "No effect,Clear"
|
|
bitfld.long 0x00 17. " HWINTCLR81 ,HWINT 81 clear" "No effect,Clear"
|
|
bitfld.long 0x00 16. " HWINTCLR80 ,HWINT 80 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " HWINTCLR79 ,HWINT 79 clear" "No effect,Clear"
|
|
bitfld.long 0x00 14. " HWINTCLR78 ,HWINT 78 clear" "No effect,Clear"
|
|
bitfld.long 0x00 13. " HWINTCLR77 ,HWINT 77 clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " HWINTCLR76 ,HWINT 76 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " HWINTCLR75 ,HWINT 75 clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " HWINTCLR74 ,HWINT 74 clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " HWINTCLR73 ,HWINT 73 clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " HWINTCLR72 ,HWINT 72 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HWINTCLR71 ,HWINT 71 clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " HWINTCLR70 ,HWINT 70 clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " HWINTCLR69 ,HWINT 69 clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " HWINTCLR68 ,HWINT 68 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " HWINTCLR67 ,HWINT 67 clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " HWINTCLR66 ,HWINT 66 clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " HWINTCLR65 ,HWINT 65 clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " HWINTCLR64 ,HWINT 64 clear" "No effect,Clear"
|
|
line.long 0x04 "HWINTCLR[127:96],Hardware Transfer Interrupt Clear (Channels - 127:96)"
|
|
bitfld.long 0x04 31. " HWINTCLR127 ,HWINT 127 clear" "No effect,Clear"
|
|
bitfld.long 0x04 30. " HWINTCLR126 ,HWINT 126 clear" "No effect,Clear"
|
|
bitfld.long 0x04 29. " HWINTCLR125 ,HWINT 125 clear" "No effect,Clear"
|
|
bitfld.long 0x04 28. " HWINTCLR124 ,HWINT 124 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 27. " HWINTCLR123 ,HWINT 123 clear" "No effect,Clear"
|
|
bitfld.long 0x04 26. " HWINTCLR122 ,HWINT 122 clear" "No effect,Clear"
|
|
bitfld.long 0x04 25. " HWINTCLR121 ,HWINT 121 clear" "No effect,Clear"
|
|
bitfld.long 0x04 24. " HWINTCLR120 ,HWINT 120 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 23. " HWINTCLR119 ,HWINT 119 clear" "No effect,Clear"
|
|
bitfld.long 0x04 22. " HWINTCLR118 ,HWINT 118 clear" "No effect,Clear"
|
|
bitfld.long 0x04 21. " HWINTCLR117 ,HWINT 117 clear" "No effect,Clear"
|
|
bitfld.long 0x04 20. " HWINTCLR116 ,HWINT 116 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 19. " HWINTCLR115 ,HWINT 115 clear" "No effect,Clear"
|
|
bitfld.long 0x04 18. " HWINTCLR114 ,HWINT 114 clear" "No effect,Clear"
|
|
bitfld.long 0x04 17. " HWINTCLR113 ,HWINT 113 clear" "No effect,Clear"
|
|
bitfld.long 0x04 16. " HWINTCLR112 ,HWINT 112 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 15. " HWINTCLR111 ,HWINT 111 clear" "No effect,Clear"
|
|
bitfld.long 0x04 14. " HWINTCLR110 ,HWINT 110 clear" "No effect,Clear"
|
|
bitfld.long 0x04 13. " HWINTCLR109 ,HWINT 109 clear" "No effect,Clear"
|
|
bitfld.long 0x04 12. " HWINTCLR108 ,HWINT 108 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 11. " HWINTCLR107 ,HWINT 107 clear" "No effect,Clear"
|
|
bitfld.long 0x04 10. " HWINTCLR106 ,HWINT 106 clear" "No effect,Clear"
|
|
bitfld.long 0x04 9. " HWINTCLR105 ,HWINT 105 clear" "No effect,Clear"
|
|
bitfld.long 0x04 8. " HWINTCLR104 ,HWINT 104 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " HWINTCLR103 ,HWINT 103 clear" "No effect,Clear"
|
|
bitfld.long 0x04 6. " HWINTCLR102 ,HWINT 102 clear" "No effect,Clear"
|
|
bitfld.long 0x04 5. " HWINTCLR101 ,HWINT 101 clear" "No effect,Clear"
|
|
bitfld.long 0x04 4. " HWINTCLR100 ,HWINT 100 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " HWINTCLR99 ,HWINT 99 clear" "No effect,Clear"
|
|
bitfld.long 0x04 2. " HWINTCLR98 ,HWINT 98 clear" "No effect,Clear"
|
|
bitfld.long 0x04 1. " HWINTCLR97 ,HWINT 97 clear" "No effect,Clear"
|
|
bitfld.long 0x04 0. " HWINTCLR96 ,HWINT 96 clear" "No effect,Clear"
|
|
sif cpuis("S6E2C*")
|
|
wgroup.long 0x60++0x0F
|
|
line.long 0x00 "HWINTCLR[159:128],Hardware Transfer Interrupt Clear (Channels - 159:128)"
|
|
bitfld.long 0x00 31. " HWINTCLR159 ,HWINT 159 clear" "No effect,Clear"
|
|
bitfld.long 0x00 30. " HWINTCLR158 ,HWINT 158 clear" "No effect,Clear"
|
|
bitfld.long 0x00 29. " HWINTCLR157 ,HWINT 157 clear" "No effect,Clear"
|
|
bitfld.long 0x00 28. " HWINTCLR156 ,HWINT 156 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " HWINTCLR155 ,HWINT 155 clear" "No effect,Clear"
|
|
bitfld.long 0x00 26. " HWINTCLR154 ,HWINT 154 clear" "No effect,Clear"
|
|
bitfld.long 0x00 25. " HWINTCLR153 ,HWINT 153 clear" "No effect,Clear"
|
|
bitfld.long 0x00 24. " HWINTCLR152 ,HWINT 152 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " HWINTCLR151 ,HWINT 151 clear" "No effect,Clear"
|
|
bitfld.long 0x00 22. " HWINTCLR150 ,HWINT 150 clear" "No effect,Clear"
|
|
bitfld.long 0x00 21. " HWINTCLR149 ,HWINT 149 clear" "No effect,Clear"
|
|
bitfld.long 0x00 20. " HWINTCLR148 ,HWINT 148 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " HWINTCLR147 ,HWINT 147 clear" "No effect,Clear"
|
|
bitfld.long 0x00 18. " HWINTCLR146 ,HWINT 146 clear" "No effect,Clear"
|
|
bitfld.long 0x00 17. " HWINTCLR145 ,HWINT 145 clear" "No effect,Clear"
|
|
bitfld.long 0x00 16. " HWINTCLR144 ,HWINT 144 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " HWINTCLR143 ,HWINT 143 clear" "No effect,Clear"
|
|
bitfld.long 0x00 14. " HWINTCLR142 ,HWINT 142 clear" "No effect,Clear"
|
|
bitfld.long 0x00 13. " HWINTCLR141 ,HWINT 141 clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " HWINTCLR140 ,HWINT 140 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " HWINTCLR139 ,HWINT 139 clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " HWINTCLR138 ,HWINT 138 clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " HWINTCLR137 ,HWINT 137 clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " HWINTCLR136 ,HWINT 136 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HWINTCLR135 ,HWINT 135 clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " HWINTCLR134 ,HWINT 134 clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " HWINTCLR133 ,HWINT 133 clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " HWINTCLR132 ,HWINT 132 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " HWINTCLR131 ,HWINT 131 clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " HWINTCLR130 ,HWINT 130 clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " HWINTCLR129 ,HWINT 129 clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " HWINTCLR128 ,HWINT 128 clear" "No effect,Clear"
|
|
line.long 0x04 "HWINTCLR[191:160],Hardware Transfer Interrupt Clear (Channels - 191:160)"
|
|
bitfld.long 0x04 31. " HWINTCLR191 ,HWINT 191 clear" "No effect,Clear"
|
|
bitfld.long 0x04 30. " HWINTCLR190 ,HWINT 190 clear" "No effect,Clear"
|
|
bitfld.long 0x04 29. " HWINTCLR189 ,HWINT 189 clear" "No effect,Clear"
|
|
bitfld.long 0x04 28. " HWINTCLR188 ,HWINT 188 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 27. " HWINTCLR187 ,HWINT 187 clear" "No effect,Clear"
|
|
bitfld.long 0x04 26. " HWINTCLR186 ,HWINT 186 clear" "No effect,Clear"
|
|
bitfld.long 0x04 25. " HWINTCLR185 ,HWINT 185 clear" "No effect,Clear"
|
|
bitfld.long 0x04 24. " HWINTCLR184 ,HWINT 184 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 23. " HWINTCLR183 ,HWINT 183 clear" "No effect,Clear"
|
|
bitfld.long 0x04 22. " HWINTCLR182 ,HWINT 182 clear" "No effect,Clear"
|
|
bitfld.long 0x04 21. " HWINTCLR181 ,HWINT 181 clear" "No effect,Clear"
|
|
bitfld.long 0x04 20. " HWINTCLR180 ,HWINT 180 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 19. " HWINTCLR179 ,HWINT 179 clear" "No effect,Clear"
|
|
bitfld.long 0x04 18. " HWINTCLR178 ,HWINT 178 clear" "No effect,Clear"
|
|
bitfld.long 0x04 17. " HWINTCLR177 ,HWINT 177 clear" "No effect,Clear"
|
|
bitfld.long 0x04 16. " HWINTCLR176 ,HWINT 176 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 15. " HWINTCLR175 ,HWINT 175 clear" "No effect,Clear"
|
|
bitfld.long 0x04 14. " HWINTCLR174 ,HWINT 174 clear" "No effect,Clear"
|
|
bitfld.long 0x04 13. " HWINTCLR173 ,HWINT 173 clear" "No effect,Clear"
|
|
bitfld.long 0x04 12. " HWINTCLR172 ,HWINT 172 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 11. " HWINTCLR171 ,HWINT 171 clear" "No effect,Clear"
|
|
bitfld.long 0x04 10. " HWINTCLR170 ,HWINT 170 clear" "No effect,Clear"
|
|
bitfld.long 0x04 9. " HWINTCLR169 ,HWINT 169 clear" "No effect,Clear"
|
|
bitfld.long 0x04 8. " HWINTCLR168 ,HWINT 168 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " HWINTCLR167 ,HWINT 167 clear" "No effect,Clear"
|
|
bitfld.long 0x04 6. " HWINTCLR166 ,HWINT 166 clear" "No effect,Clear"
|
|
bitfld.long 0x04 5. " HWINTCLR165 ,HWINT 165 clear" "No effect,Clear"
|
|
bitfld.long 0x04 4. " HWINTCLR164 ,HWINT 164 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " HWINTCLR163 ,HWINT 163 clear" "No effect,Clear"
|
|
bitfld.long 0x04 2. " HWINTCLR162 ,HWINT 162 clear" "No effect,Clear"
|
|
bitfld.long 0x04 1. " HWINTCLR161 ,HWINT 161 clear" "No effect,Clear"
|
|
bitfld.long 0x04 0. " HWINTCLR160 ,HWINT 160 clear" "No effect,Clear"
|
|
line.long 0x08 "HWINTCLR[223:192],Hardware Transfer Interrupt Clear (Channels - 223:192)"
|
|
bitfld.long 0x08 31. " HWINTCLR223 ,HWINT 223 clear" "No effect,Clear"
|
|
bitfld.long 0x08 30. " HWINTCLR222 ,HWINT 222 clear" "No effect,Clear"
|
|
bitfld.long 0x08 29. " HWINTCLR221 ,HWINT 221 clear" "No effect,Clear"
|
|
bitfld.long 0x08 28. " HWINTCLR220 ,HWINT 220 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 27. " HWINTCLR219 ,HWINT 219 clear" "No effect,Clear"
|
|
bitfld.long 0x08 26. " HWINTCLR218 ,HWINT 218 clear" "No effect,Clear"
|
|
bitfld.long 0x08 25. " HWINTCLR217 ,HWINT 217 clear" "No effect,Clear"
|
|
bitfld.long 0x08 24. " HWINTCLR216 ,HWINT 216 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 23. " HWINTCLR215 ,HWINT 215 clear" "No effect,Clear"
|
|
bitfld.long 0x08 22. " HWINTCLR214 ,HWINT 214 clear" "No effect,Clear"
|
|
bitfld.long 0x08 21. " HWINTCLR213 ,HWINT 213 clear" "No effect,Clear"
|
|
bitfld.long 0x08 20. " HWINTCLR212 ,HWINT 212 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 19. " HWINTCLR211 ,HWINT 211 clear" "No effect,Clear"
|
|
bitfld.long 0x08 18. " HWINTCLR210 ,HWINT 210 clear" "No effect,Clear"
|
|
bitfld.long 0x08 17. " HWINTCLR209 ,HWINT 209 clear" "No effect,Clear"
|
|
bitfld.long 0x08 16. " HWINTCLR208 ,HWINT 208 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 15. " HWINTCLR207 ,HWINT 207 clear" "No effect,Clear"
|
|
bitfld.long 0x08 14. " HWINTCLR206 ,HWINT 206 clear" "No effect,Clear"
|
|
bitfld.long 0x08 13. " HWINTCLR205 ,HWINT 205 clear" "No effect,Clear"
|
|
bitfld.long 0x08 12. " HWINTCLR204 ,HWINT 204 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 11. " HWINTCLR203 ,HWINT 203 clear" "No effect,Clear"
|
|
bitfld.long 0x08 10. " HWINTCLR202 ,HWINT 202 clear" "No effect,Clear"
|
|
bitfld.long 0x08 9. " HWINTCLR201 ,HWINT 201 clear" "No effect,Clear"
|
|
bitfld.long 0x08 8. " HWINTCLR200 ,HWINT 200 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 7. " HWINTCLR199 ,HWINT 199 clear" "No effect,Clear"
|
|
bitfld.long 0x08 6. " HWINTCLR198 ,HWINT 198 clear" "No effect,Clear"
|
|
bitfld.long 0x08 5. " HWINTCLR197 ,HWINT 197 clear" "No effect,Clear"
|
|
bitfld.long 0x08 4. " HWINTCLR196 ,HWINT 196 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 3. " HWINTCLR195 ,HWINT 195 clear" "No effect,Clear"
|
|
bitfld.long 0x08 2. " HWINTCLR194 ,HWINT 194 clear" "No effect,Clear"
|
|
bitfld.long 0x08 1. " HWINTCLR193 ,HWINT 193 clear" "No effect,Clear"
|
|
bitfld.long 0x08 0. " HWINTCLR192 ,HWINT 192 clear" "No effect,Clear"
|
|
line.long 0x0C "HWINTCLR[255:224],Hardware Transfer Interrupt Clear (Channels - 255:224)"
|
|
bitfld.long 0x0C 31. " HWINTCLR255 ,HWINT 255 clear" "No effect,Clear"
|
|
bitfld.long 0x0C 30. " HWINTCLR254 ,HWINT 254 clear" "No effect,Clear"
|
|
bitfld.long 0x0C 29. " HWINTCLR253 ,HWINT 253 clear" "No effect,Clear"
|
|
bitfld.long 0x0C 28. " HWINTCLR252 ,HWINT 252 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " HWINTCLR251 ,HWINT 251 clear" "No effect,Clear"
|
|
bitfld.long 0x0C 26. " HWINTCLR250 ,HWINT 250 clear" "No effect,Clear"
|
|
bitfld.long 0x0C 25. " HWINTCLR249 ,HWINT 249 clear" "No effect,Clear"
|
|
bitfld.long 0x0C 24. " HWINTCLR248 ,HWINT 248 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " HWINTCLR247 ,HWINT 247 clear" "No effect,Clear"
|
|
bitfld.long 0x0C 22. " HWINTCLR246 ,HWINT 246 clear" "No effect,Clear"
|
|
bitfld.long 0x0C 21. " HWINTCLR245 ,HWINT 245 clear" "No effect,Clear"
|
|
bitfld.long 0x0C 20. " HWINTCLR244 ,HWINT 244 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " HWINTCLR243 ,HWINT 243 clear" "No effect,Clear"
|
|
bitfld.long 0x0C 18. " HWINTCLR242 ,HWINT 242 clear" "No effect,Clear"
|
|
bitfld.long 0x0C 17. " HWINTCLR241 ,HWINT 241 clear" "No effect,Clear"
|
|
bitfld.long 0x0C 16. " HWINTCLR240 ,HWINT 240 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " HWINTCLR239 ,HWINT 239 clear" "No effect,Clear"
|
|
bitfld.long 0x0C 14. " HWINTCLR238 ,HWINT 238 clear" "No effect,Clear"
|
|
bitfld.long 0x0C 13. " HWINTCLR237 ,HWINT 237 clear" "No effect,Clear"
|
|
bitfld.long 0x0C 12. " HWINTCLR236 ,HWINT 236 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " HWINTCLR235 ,HWINT 235 clear" "No effect,Clear"
|
|
bitfld.long 0x0C 10. " HWINTCLR234 ,HWINT 234 clear" "No effect,Clear"
|
|
bitfld.long 0x0C 9. " HWINTCLR233 ,HWINT 233 clear" "No effect,Clear"
|
|
bitfld.long 0x0C 8. " HWINTCLR232 ,HWINT 232 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " HWINTCLR231 ,HWINT 231 clear" "No effect,Clear"
|
|
bitfld.long 0x0C 6. " HWINTCLR230 ,HWINT 230 clear" "No effect,Clear"
|
|
bitfld.long 0x0C 5. " HWINTCLR229 ,HWINT 229 clear" "No effect,Clear"
|
|
bitfld.long 0x0C 4. " HWINTCLR228 ,HWINT 228 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " HWINTCLR227 ,HWINT 227 clear" "No effect,Clear"
|
|
bitfld.long 0x0C 2. " HWINTCLR226 ,HWINT 226 clear" "No effect,Clear"
|
|
bitfld.long 0x0C 1. " HWINTCLR225 ,HWINT 225 clear" "No effect,Clear"
|
|
bitfld.long 0x0C 0. " HWINTCLR224 ,HWINT 224 clear" "No effect,Clear"
|
|
endif
|
|
endif
|
|
rgroup.long 0x070++0x0F
|
|
line.long 0x00 "DQMSK[31:0],DMA Request Mask (Channels - 31:0)"
|
|
bitfld.long 0x00 31. " DQMSK31 ,DMA request mask (Channel 31)" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " DQMSK30 ,DMA request mask (Channel 30)" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " DQMSK29 ,DMA request mask (Channel 29)" "Not masked,Masked"
|
|
bitfld.long 0x00 28. " DQMSK28 ,DMA request mask (Channel 28)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DQMSK27 ,DMA request mask (Channel 27)" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " DQMSK26 ,DMA request mask (Channel 26)" "Not masked,Masked"
|
|
bitfld.long 0x00 25. " DQMSK25 ,DMA request mask (Channel 25)" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " DQMSK24 ,DMA request mask (Channel 24)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DQMSK23 ,DMA request mask (Channel 23)" "Not masked,Masked"
|
|
bitfld.long 0x00 22. " DQMSK22 ,DMA request mask (Channel 22)" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " DQMSK21 ,DMA request mask (Channel 21)" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " DQMSK20 ,DMA request mask (Channel 20)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DQMSK19 ,DMA request mask (Channel 19)" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " DQMSK18 ,DMA request mask (Channel 18)" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " DQMSK17 ,DMA request mask (Channel 17)" "Not masked,Masked"
|
|
bitfld.long 0x00 16. " DQMSK16 ,DMA request mask (Channel 16)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DQMSK15 ,DMA request mask (Channel 15)" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " DQMSK14 ,DMA request mask (Channel 14)" "Not masked,Masked"
|
|
bitfld.long 0x00 13. " DQMSK13 ,DMA request mask (Channel 13)" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " DQMSK12 ,DMA request mask (Channel 12)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DQMSK11 ,DMA request mask (Channel 11)" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " DQMSK10 ,DMA request mask (Channel 10)" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " DQMSK09 ,DMA request mask (Channel 9)" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " DQMSK08 ,DMA request mask (Channel 8)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DQMSK07 ,DMA request mask (Channel 7)" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " DQMSK06 ,DMA request mask (Channel 6)" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " DQMSK05 ,DMA request mask (Channel 5)" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " DQMSK04 ,DMA request mask (Channel 4)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DQMSK03 ,DMA request mask (Channel 3)" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " DQMSK02 ,DMA request mask (Channel 2)" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " DQMSK01 ,DMA request mask (Channel 1)" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " DQMSK00 ,DMA request mask (Channel 0)" "Not masked,Masked"
|
|
line.long 0x04 "DQMSK[63:32],DMA Request Mask (Channels - 63:32)"
|
|
bitfld.long 0x04 31. " DQMSK63 ,DMA request mask (Channel 63)" "Not masked,Masked"
|
|
bitfld.long 0x04 30. " DQMSK62 ,DMA request mask (Channel 62)" "Not masked,Masked"
|
|
bitfld.long 0x04 29. " DQMSK61 ,DMA request mask (Channel 61)" "Not masked,Masked"
|
|
bitfld.long 0x04 28. " DQMSK60 ,DMA request mask (Channel 60)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 27. " DQMSK59 ,DMA request mask (Channel 59)" "Not masked,Masked"
|
|
bitfld.long 0x04 26. " DQMSK58 ,DMA request mask (Channel 58)" "Not masked,Masked"
|
|
bitfld.long 0x04 25. " DQMSK57 ,DMA request mask (Channel 57)" "Not masked,Masked"
|
|
bitfld.long 0x04 24. " DQMSK56 ,DMA request mask (Channel 56)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 23. " DQMSK55 ,DMA request mask (Channel 55)" "Not masked,Masked"
|
|
bitfld.long 0x04 22. " DQMSK54 ,DMA request mask (Channel 54)" "Not masked,Masked"
|
|
bitfld.long 0x04 21. " DQMSK53 ,DMA request mask (Channel 53)" "Not masked,Masked"
|
|
bitfld.long 0x04 20. " DQMSK52 ,DMA request mask (Channel 52)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " DQMSK51 ,DMA request mask (Channel 51)" "Not masked,Masked"
|
|
bitfld.long 0x04 18. " DQMSK50 ,DMA request mask (Channel 50)" "Not masked,Masked"
|
|
bitfld.long 0x04 17. " DQMSK49 ,DMA request mask (Channel 49)" "Not masked,Masked"
|
|
bitfld.long 0x04 16. " DQMSK48 ,DMA request mask (Channel 48)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 15. " DQMSK47 ,DMA request mask (Channel 47)" "Not masked,Masked"
|
|
bitfld.long 0x04 14. " DQMSK46 ,DMA request mask (Channel 46)" "Not masked,Masked"
|
|
bitfld.long 0x04 13. " DQMSK45 ,DMA request mask (Channel 45)" "Not masked,Masked"
|
|
bitfld.long 0x04 12. " DQMSK44 ,DMA request mask (Channel 44)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 11. " DQMSK43 ,DMA request mask (Channel 43)" "Not masked,Masked"
|
|
bitfld.long 0x04 10. " DQMSK42 ,DMA request mask (Channel 42)" "Not masked,Masked"
|
|
bitfld.long 0x04 9. " DQMSK41 ,DMA request mask (Channel 41)" "Not masked,Masked"
|
|
bitfld.long 0x04 8. " DQMSK40 ,DMA request mask (Channel 40)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 7. " DQMSK39 ,DMA request mask (Channel 39)" "Not masked,Masked"
|
|
bitfld.long 0x04 6. " DQMSK38 ,DMA request mask (Channel 38)" "Not masked,Masked"
|
|
bitfld.long 0x04 5. " DQMSK37 ,DMA request mask (Channel 37)" "Not masked,Masked"
|
|
bitfld.long 0x04 4. " DQMSK36 ,DMA request mask (Channel 36)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DQMSK35 ,DMA request mask (Channel 35)" "Not masked,Masked"
|
|
bitfld.long 0x04 2. " DQMSK34 ,DMA request mask (Channel 34)" "Not masked,Masked"
|
|
bitfld.long 0x04 1. " DQMSK33 ,DMA request mask (Channel 33)" "Not masked,Masked"
|
|
bitfld.long 0x04 0. " DQMSK32 ,DMA request mask (Channel 32)" "Not masked,Masked"
|
|
sif !cpuis("S6E1C12*")&&!cpuis("S6E1C32*")&&!cpuis("S6E1C11*")&&!cpuis("S6E1C31*")
|
|
rgroup.long 0x78++0x07
|
|
line.long 0x00 "DQMSK[95:64],DMA Request Mask (Channels - 95:64)"
|
|
bitfld.long 0x00 31. " DQMSK95 ,DMA request mask (Channel 95)" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " DQMSK94 ,DMA request mask (Channel 94)" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " DQMSK93 ,DMA request mask (Channel 93)" "Not masked,Masked"
|
|
bitfld.long 0x00 28. " DQMSK92 ,DMA request mask (Channel 92)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DQMSK91 ,DMA request mask (Channel 91)" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " DQMSK90 ,DMA request mask (Channel 90)" "Not masked,Masked"
|
|
bitfld.long 0x00 25. " DQMSK89 ,DMA request mask (Channel 89)" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " DQMSK88 ,DMA request mask (Channel 88)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DQMSK87 ,DMA request mask (Channel 87)" "Not masked,Masked"
|
|
bitfld.long 0x00 22. " DQMSK86 ,DMA request mask (Channel 86)" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " DQMSK85 ,DMA request mask (Channel 85)" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " DQMSK84 ,DMA request mask (Channel 84)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DQMSK83 ,DMA request mask (Channel 83)" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " DQMSK82 ,DMA request mask (Channel 82)" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " DQMSK81 ,DMA request mask (Channel 81)" "Not masked,Masked"
|
|
bitfld.long 0x00 16. " DQMSK80 ,DMA request mask (Channel 80)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DQMSK79 ,DMA request mask (Channel 79)" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " DQMSK78 ,DMA request mask (Channel 78)" "Not masked,Masked"
|
|
bitfld.long 0x00 13. " DQMSK77 ,DMA request mask (Channel 77)" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " DQMSK76 ,DMA request mask (Channel 76)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DQMSK75 ,DMA request mask (Channel 75)" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " DQMSK74 ,DMA request mask (Channel 74)" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " DQMSK73 ,DMA request mask (Channel 73)" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " DQMSK72 ,DMA request mask (Channel 72)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DQMSK71 ,DMA request mask (Channel 71)" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " DQMSK70 ,DMA request mask (Channel 70)" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " DQMSK69 ,DMA request mask (Channel 69)" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " DQMSK68 ,DMA request mask (Channel 68)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DQMSK67 ,DMA request mask (Channel 67)" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " DQMSK66 ,DMA request mask (Channel 66)" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " DQMSK65 ,DMA request mask (Channel 65)" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " DQMSK64 ,DMA request mask (Channel 64)" "Not masked,Masked"
|
|
line.long 0x04 "DQMSK[127:96],DMA Request Mask (Channels - 127:96)"
|
|
bitfld.long 0x04 31. " DQMSK127 ,DMA request mask (Channel 127)" "Not masked,Masked"
|
|
bitfld.long 0x04 30. " DQMSK126 ,DMA request mask (Channel 126)" "Not masked,Masked"
|
|
bitfld.long 0x04 29. " DQMSK125 ,DMA request mask (Channel 125)" "Not masked,Masked"
|
|
bitfld.long 0x04 28. " DQMSK124 ,DMA request mask (Channel 124)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 27. " DQMSK123 ,DMA request mask (Channel 123)" "Not masked,Masked"
|
|
bitfld.long 0x04 26. " DQMSK122 ,DMA request mask (Channel 122)" "Not masked,Masked"
|
|
bitfld.long 0x04 25. " DQMSK121 ,DMA request mask (Channel 121)" "Not masked,Masked"
|
|
bitfld.long 0x04 24. " DQMSK120 ,DMA request mask (Channel 120)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 23. " DQMSK119 ,DMA request mask (Channel 119)" "Not masked,Masked"
|
|
bitfld.long 0x04 22. " DQMSK118 ,DMA request mask (Channel 118)" "Not masked,Masked"
|
|
bitfld.long 0x04 21. " DQMSK117 ,DMA request mask (Channel 117)" "Not masked,Masked"
|
|
bitfld.long 0x04 20. " DQMSK116 ,DMA request mask (Channel 116)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " DQMSK115 ,DMA request mask (Channel 115)" "Not masked,Masked"
|
|
bitfld.long 0x04 18. " DQMSK114 ,DMA request mask (Channel 114)" "Not masked,Masked"
|
|
bitfld.long 0x04 17. " DQMSK113 ,DMA request mask (Channel 113)" "Not masked,Masked"
|
|
bitfld.long 0x04 16. " DQMSK112 ,DMA request mask (Channel 112)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 15. " DQMSK111 ,DMA request mask (Channel 111)" "Not masked,Masked"
|
|
bitfld.long 0x04 14. " DQMSK110 ,DMA request mask (Channel 110)" "Not masked,Masked"
|
|
bitfld.long 0x04 13. " DQMSK109 ,DMA request mask (Channel 109)" "Not masked,Masked"
|
|
bitfld.long 0x04 12. " DQMSK108 ,DMA request mask (Channel 108)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 11. " DQMSK107 ,DMA request mask (Channel 107)" "Not masked,Masked"
|
|
bitfld.long 0x04 10. " DQMSK106 ,DMA request mask (Channel 106)" "Not masked,Masked"
|
|
bitfld.long 0x04 9. " DQMSK105 ,DMA request mask (Channel 105)" "Not masked,Masked"
|
|
bitfld.long 0x04 8. " DQMSK104 ,DMA request mask (Channel 104)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 7. " DQMSK103 ,DMA request mask (Channel 103)" "Not masked,Masked"
|
|
bitfld.long 0x04 6. " DQMSK102 ,DMA request mask (Channel 102)" "Not masked,Masked"
|
|
bitfld.long 0x04 5. " DQMSK101 ,DMA request mask (Channel 101)" "Not masked,Masked"
|
|
bitfld.long 0x04 4. " DQMSK100 ,DMA request mask (Channel 100)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DQMSK99 ,DMA request mask (Channel 99)" "Not masked,Masked"
|
|
bitfld.long 0x04 2. " DQMSK98 ,DMA request mask (Channel 98)" "Not masked,Masked"
|
|
bitfld.long 0x04 1. " DQMSK97 ,DMA request mask (Channel 97)" "Not masked,Masked"
|
|
bitfld.long 0x04 0. " DQMSK96 ,DMA request mask (Channel 96)" "Not masked,Masked"
|
|
sif cpuis("S6E2C*")
|
|
rgroup.long 0x080++0x0F
|
|
line.long 0x00 "DQMSK[159:128],DMA Request Mask (Channels - 159:128)"
|
|
bitfld.long 0x00 31. " DQMSK159 ,DMA request mask (Channel 159)" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " DQMSK158 ,DMA request mask (Channel 158)" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " DQMSK157 ,DMA request mask (Channel 157)" "Not masked,Masked"
|
|
bitfld.long 0x00 28. " DQMSK156 ,DMA request mask (Channel 156)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DQMSK155 ,DMA request mask (Channel 155)" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " DQMSK154 ,DMA request mask (Channel 154)" "Not masked,Masked"
|
|
bitfld.long 0x00 25. " DQMSK153 ,DMA request mask (Channel 153)" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " DQMSK152 ,DMA request mask (Channel 152)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DQMSK151 ,DMA request mask (Channel 151)" "Not masked,Masked"
|
|
bitfld.long 0x00 22. " DQMSK150 ,DMA request mask (Channel 150)" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " DQMSK149 ,DMA request mask (Channel 149)" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " DQMSK148 ,DMA request mask (Channel 148)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DQMSK147 ,DMA request mask (Channel 147)" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " DQMSK146 ,DMA request mask (Channel 146)" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " DQMSK145 ,DMA request mask (Channel 145)" "Not masked,Masked"
|
|
bitfld.long 0x00 16. " DQMSK144 ,DMA request mask (Channel 144)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DQMSK143 ,DMA request mask (Channel 143)" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " DQMSK142 ,DMA request mask (Channel 142)" "Not masked,Masked"
|
|
bitfld.long 0x00 13. " DQMSK141 ,DMA request mask (Channel 141)" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " DQMSK140 ,DMA request mask (Channel 140)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DQMSK139 ,DMA request mask (Channel 139)" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " DQMSK138 ,DMA request mask (Channel 138)" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " DQMSK137 ,DMA request mask (Channel 137)" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " DQMSK136 ,DMA request mask (Channel 136)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DQMSK135 ,DMA request mask (Channel 135)" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " DQMSK134 ,DMA request mask (Channel 134)" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " DQMSK133 ,DMA request mask (Channel 133)" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " DQMSK132 ,DMA request mask (Channel 132)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DQMSK131 ,DMA request mask (Channel 131)" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " DQMSK130 ,DMA request mask (Channel 130)" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " DQMSK129 ,DMA request mask (Channel 129)" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " DQMSK128 ,DMA request mask (Channel 128)" "Not masked,Masked"
|
|
line.long 0x04 "DQMSK[191:160],DMA Request Mask (Channels - 191:160)"
|
|
bitfld.long 0x04 31. " DQMSK191 ,DMA request mask (Channel 191)" "Not masked,Masked"
|
|
bitfld.long 0x04 30. " DQMSK190 ,DMA request mask (Channel 190)" "Not masked,Masked"
|
|
bitfld.long 0x04 29. " DQMSK189 ,DMA request mask (Channel 189)" "Not masked,Masked"
|
|
bitfld.long 0x04 28. " DQMSK188 ,DMA request mask (Channel 188)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 27. " DQMSK187 ,DMA request mask (Channel 187)" "Not masked,Masked"
|
|
bitfld.long 0x04 26. " DQMSK186 ,DMA request mask (Channel 186)" "Not masked,Masked"
|
|
bitfld.long 0x04 25. " DQMSK185 ,DMA request mask (Channel 185)" "Not masked,Masked"
|
|
bitfld.long 0x04 24. " DQMSK184 ,DMA request mask (Channel 184)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 23. " DQMSK183 ,DMA request mask (Channel 183)" "Not masked,Masked"
|
|
bitfld.long 0x04 22. " DQMSK182 ,DMA request mask (Channel 182)" "Not masked,Masked"
|
|
bitfld.long 0x04 21. " DQMSK181 ,DMA request mask (Channel 181)" "Not masked,Masked"
|
|
bitfld.long 0x04 20. " DQMSK180 ,DMA request mask (Channel 180)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " DQMSK179 ,DMA request mask (Channel 179)" "Not masked,Masked"
|
|
bitfld.long 0x04 18. " DQMSK178 ,DMA request mask (Channel 178)" "Not masked,Masked"
|
|
bitfld.long 0x04 17. " DQMSK177 ,DMA request mask (Channel 177)" "Not masked,Masked"
|
|
bitfld.long 0x04 16. " DQMSK176 ,DMA request mask (Channel 176)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 15. " DQMSK175 ,DMA request mask (Channel 175)" "Not masked,Masked"
|
|
bitfld.long 0x04 14. " DQMSK174 ,DMA request mask (Channel 174)" "Not masked,Masked"
|
|
bitfld.long 0x04 13. " DQMSK173 ,DMA request mask (Channel 173)" "Not masked,Masked"
|
|
bitfld.long 0x04 12. " DQMSK172 ,DMA request mask (Channel 172)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 11. " DQMSK171 ,DMA request mask (Channel 171)" "Not masked,Masked"
|
|
bitfld.long 0x04 10. " DQMSK170 ,DMA request mask (Channel 170)" "Not masked,Masked"
|
|
bitfld.long 0x04 9. " DQMSK169 ,DMA request mask (Channel 169)" "Not masked,Masked"
|
|
bitfld.long 0x04 8. " DQMSK168 ,DMA request mask (Channel 168)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 7. " DQMSK167 ,DMA request mask (Channel 167)" "Not masked,Masked"
|
|
bitfld.long 0x04 6. " DQMSK166 ,DMA request mask (Channel 166)" "Not masked,Masked"
|
|
bitfld.long 0x04 5. " DQMSK165 ,DMA request mask (Channel 165)" "Not masked,Masked"
|
|
bitfld.long 0x04 4. " DQMSK164 ,DMA request mask (Channel 164)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DQMSK163 ,DMA request mask (Channel 163)" "Not masked,Masked"
|
|
bitfld.long 0x04 2. " DQMSK162 ,DMA request mask (Channel 162)" "Not masked,Masked"
|
|
bitfld.long 0x04 1. " DQMSK161 ,DMA request mask (Channel 161)" "Not masked,Masked"
|
|
bitfld.long 0x04 0. " DQMSK160 ,DMA request mask (Channel 160)" "Not masked,Masked"
|
|
line.long 0x08 "DQMSK[223:192],DMA Request Mask (Channels - 223:192)"
|
|
bitfld.long 0x08 31. " DQMSK223 ,DMA request mask (Channel 223)" "Not masked,Masked"
|
|
bitfld.long 0x08 30. " DQMSK222 ,DMA request mask (Channel 222)" "Not masked,Masked"
|
|
bitfld.long 0x08 29. " DQMSK221 ,DMA request mask (Channel 221)" "Not masked,Masked"
|
|
bitfld.long 0x08 28. " DQMSK220 ,DMA request mask (Channel 220)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 27. " DQMSK219 ,DMA request mask (Channel 219)" "Not masked,Masked"
|
|
bitfld.long 0x08 26. " DQMSK218 ,DMA request mask (Channel 218)" "Not masked,Masked"
|
|
bitfld.long 0x08 25. " DQMSK217 ,DMA request mask (Channel 217)" "Not masked,Masked"
|
|
bitfld.long 0x08 24. " DQMSK216 ,DMA request mask (Channel 216)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 23. " DQMSK215 ,DMA request mask (Channel 215)" "Not masked,Masked"
|
|
bitfld.long 0x08 22. " DQMSK214 ,DMA request mask (Channel 214)" "Not masked,Masked"
|
|
bitfld.long 0x08 21. " DQMSK213 ,DMA request mask (Channel 213)" "Not masked,Masked"
|
|
bitfld.long 0x08 20. " DQMSK212 ,DMA request mask (Channel 212)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 19. " DQMSK211 ,DMA request mask (Channel 211)" "Not masked,Masked"
|
|
bitfld.long 0x08 18. " DQMSK210 ,DMA request mask (Channel 210)" "Not masked,Masked"
|
|
bitfld.long 0x08 17. " DQMSK209 ,DMA request mask (Channel 209)" "Not masked,Masked"
|
|
bitfld.long 0x08 16. " DQMSK208 ,DMA request mask (Channel 208)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 15. " DQMSK207 ,DMA request mask (Channel 207)" "Not masked,Masked"
|
|
bitfld.long 0x08 14. " DQMSK206 ,DMA request mask (Channel 206)" "Not masked,Masked"
|
|
bitfld.long 0x08 13. " DQMSK205 ,DMA request mask (Channel 205)" "Not masked,Masked"
|
|
bitfld.long 0x08 12. " DQMSK204 ,DMA request mask (Channel 204)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 11. " DQMSK203 ,DMA request mask (Channel 203)" "Not masked,Masked"
|
|
bitfld.long 0x08 10. " DQMSK202 ,DMA request mask (Channel 202)" "Not masked,Masked"
|
|
bitfld.long 0x08 9. " DQMSK201 ,DMA request mask (Channel 201)" "Not masked,Masked"
|
|
bitfld.long 0x08 8. " DQMSK200 ,DMA request mask (Channel 200)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 7. " DQMSK199 ,DMA request mask (Channel 199)" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " DQMSK198 ,DMA request mask (Channel 198)" "Not masked,Masked"
|
|
bitfld.long 0x08 5. " DQMSK197 ,DMA request mask (Channel 197)" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " DQMSK196 ,DMA request mask (Channel 196)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DQMSK195 ,DMA request mask (Channel 195)" "Not masked,Masked"
|
|
bitfld.long 0x08 2. " DQMSK194 ,DMA request mask (Channel 194)" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " DQMSK193 ,DMA request mask (Channel 193)" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " DQMSK192 ,DMA request mask (Channel 192)" "Not masked,Masked"
|
|
line.long 0x0C "DQMSK[255:224],DMA Request Mask (Channels - 255:224)"
|
|
bitfld.long 0x0C 31. " DQMSK255 ,DMA request mask (Channel 255)" "Not masked,Masked"
|
|
bitfld.long 0x0C 30. " DQMSK254 ,DMA request mask (Channel 254)" "Not masked,Masked"
|
|
bitfld.long 0x0C 29. " DQMSK253 ,DMA request mask (Channel 253)" "Not masked,Masked"
|
|
bitfld.long 0x0C 28. " DQMSK252 ,DMA request mask (Channel 252)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " DQMSK251 ,DMA request mask (Channel 251)" "Not masked,Masked"
|
|
bitfld.long 0x0C 26. " DQMSK250 ,DMA request mask (Channel 250)" "Not masked,Masked"
|
|
bitfld.long 0x0C 25. " DQMSK249 ,DMA request mask (Channel 249)" "Not masked,Masked"
|
|
bitfld.long 0x0C 24. " DQMSK248 ,DMA request mask (Channel 248)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " DQMSK247 ,DMA request mask (Channel 247)" "Not masked,Masked"
|
|
bitfld.long 0x0C 22. " DQMSK246 ,DMA request mask (Channel 246)" "Not masked,Masked"
|
|
bitfld.long 0x0C 21. " DQMSK245 ,DMA request mask (Channel 245)" "Not masked,Masked"
|
|
bitfld.long 0x0C 20. " DQMSK244 ,DMA request mask (Channel 244)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " DQMSK243 ,DMA request mask (Channel 243)" "Not masked,Masked"
|
|
bitfld.long 0x0C 18. " DQMSK242 ,DMA request mask (Channel 242)" "Not masked,Masked"
|
|
bitfld.long 0x0C 17. " DQMSK241 ,DMA request mask (Channel 241)" "Not masked,Masked"
|
|
bitfld.long 0x0C 16. " DQMSK240 ,DMA request mask (Channel 240)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " DQMSK239 ,DMA request mask (Channel 239)" "Not masked,Masked"
|
|
bitfld.long 0x0C 14. " DQMSK238 ,DMA request mask (Channel 238)" "Not masked,Masked"
|
|
bitfld.long 0x0C 13. " DQMSK237 ,DMA request mask (Channel 237)" "Not masked,Masked"
|
|
bitfld.long 0x0C 12. " DQMSK236 ,DMA request mask (Channel 236)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " DQMSK235 ,DMA request mask (Channel 235)" "Not masked,Masked"
|
|
bitfld.long 0x0C 10. " DQMSK234 ,DMA request mask (Channel 234)" "Not masked,Masked"
|
|
bitfld.long 0x0C 9. " DQMSK233 ,DMA request mask (Channel 233)" "Not masked,Masked"
|
|
bitfld.long 0x0C 8. " DQMSK232 ,DMA request mask (Channel 232)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " DQMSK231 ,DMA request mask (Channel 231)" "Not masked,Masked"
|
|
bitfld.long 0x0C 6. " DQMSK230 ,DMA request mask (Channel 230)" "Not masked,Masked"
|
|
bitfld.long 0x0C 5. " DQMSK229 ,DMA request mask (Channel 229)" "Not masked,Masked"
|
|
bitfld.long 0x0C 4. " DQMSK228 ,DMA request mask (Channel 228)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " DQMSK227 ,DMA request mask (Channel 227)" "Not masked,Masked"
|
|
bitfld.long 0x0C 2. " DQMSK226 ,DMA request mask (Channel 226)" "Not masked,Masked"
|
|
bitfld.long 0x0C 1. " DQMSK225 ,DMA request mask (Channel 225)" "Not masked,Masked"
|
|
bitfld.long 0x0C 0. " DQMSK224 ,DMA request mask (Channel 224)" "Not masked,Masked"
|
|
endif
|
|
endif
|
|
wgroup.long 0x90++0x0F
|
|
line.long 0x00 "DQMSKCLR[31:0],Register For Clearing The DQMSK"
|
|
bitfld.long 0x00 31. " DQMSKCLR31 ,DQMSK31 clear (Channel 31)" "No effect,Clear"
|
|
bitfld.long 0x00 30. " DQMSKCLR30 ,DQMSK30 clear (Channel 30)" "No effect,Clear"
|
|
bitfld.long 0x00 29. " DQMSKCLR29 ,DQMSK29 clear (Channel 29)" "No effect,Clear"
|
|
bitfld.long 0x00 28. " DQMSKCLR28 ,DQMSK28 clear (Channel 28)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DQMSKCLR27 ,DQMSK27 clear (Channel 27)" "No effect,Clear"
|
|
bitfld.long 0x00 26. " DQMSKCLR26 ,DQMSK26 clear (Channel 26)" "No effect,Clear"
|
|
bitfld.long 0x00 25. " DQMSKCLR25 ,DQMSK25 clear (Channel 25)" "No effect,Clear"
|
|
bitfld.long 0x00 24. " DQMSKCLR24 ,DQMSK24 clear (Channel 24)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DQMSKCLR23 ,DQMSK23 clear (Channel 23)" "No effect,Clear"
|
|
bitfld.long 0x00 22. " DQMSKCLR22 ,DQMSK22 clear (Channel 22)" "No effect,Clear"
|
|
bitfld.long 0x00 21. " DQMSKCLR21 ,DQMSK21 clear (Channel 21)" "No effect,Clear"
|
|
bitfld.long 0x00 20. " DQMSKCLR20 ,DQMSK20 clear (Channel 20)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DQMSKCLR19 ,DQMSK19 clear (Channel 19)" "No effect,Clear"
|
|
bitfld.long 0x00 18. " DQMSKCLR18 ,DQMSK18 clear (Channel 18)" "No effect,Clear"
|
|
bitfld.long 0x00 17. " DQMSKCLR17 ,DQMSK17 clear (Channel 17)" "No effect,Clear"
|
|
bitfld.long 0x00 16. " DQMSKCLR16 ,DQMSK16 clear (Channel 16)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DQMSKCLR15 ,DQMSK15 clear (Channel 15)" "No effect,Clear"
|
|
bitfld.long 0x00 14. " DQMSKCLR14 ,DQMSK14 clear (Channel 14)" "No effect,Clear"
|
|
bitfld.long 0x00 13. " DQMSKCLR13 ,DQMSK13 clear (Channel 13)" "No effect,Clear"
|
|
bitfld.long 0x00 12. " DQMSKCLR12 ,DQMSK12 clear (Channel 12)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DQMSKCLR11 ,DQMSK clear11 (Channel 11)" "No effect,Clear"
|
|
bitfld.long 0x00 10. " DQMSKCLR10 ,DQMSK clear10 (Channel 10)" "No effect,Clear"
|
|
bitfld.long 0x00 9. " DQMSKCLR09 ,DQMSK clear09 (Channel 9)" "No effect,Clear"
|
|
bitfld.long 0x00 8. " DQMSKCLR08 ,DQMSK clear08 (Channel 8)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DQMSKCLR07 ,DQMSK clear 07 (Channel 7)" "No effect,Clear"
|
|
bitfld.long 0x00 6. " DQMSKCLR06 ,DQMSK clear 06 (Channel 6)" "No effect,Clear"
|
|
bitfld.long 0x00 5. " DQMSKCLR05 ,DQMSK clear 05 (Channel 5)" "No effect,Clear"
|
|
bitfld.long 0x00 4. " DQMSKCLR04 ,DQMSK clear 04 (Channel 4)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DQMSKCLR03 ,DQMSK clear 03 (Channel 3)" "No effect,Clear"
|
|
bitfld.long 0x00 2. " DQMSKCLR02 ,DQMSK clear 02 (Channel 2)" "No effect,Clear"
|
|
bitfld.long 0x00 1. " DQMSKCLR01 ,DQMSK clear 01 (Channel 1)" "No effect,Clear"
|
|
bitfld.long 0x00 0. " DQMSKCLR00 ,DQMSK clear 00 (Channel 0)" "No effect,Clear"
|
|
line.long 0x04 "DQMSKCLR[63:32],Register For Clearing The DQMSK"
|
|
bitfld.long 0x04 31. " DQMSKCLR63 ,DQMSK63 clear (Channel 63)" "No effect,Clear"
|
|
bitfld.long 0x04 30. " DQMSKCLR62 ,DQMSK62 clear (Channel 62)" "No effect,Clear"
|
|
bitfld.long 0x04 29. " DQMSKCLR61 ,DQMSK61 clear (Channel 61)" "No effect,Clear"
|
|
bitfld.long 0x04 28. " DQMSKCLR60 ,DQMSK60 clear (Channel 60)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 27. " DQMSKCLR59 ,DQMSK59 clear (Channel 59)" "No effect,Clear"
|
|
bitfld.long 0x04 26. " DQMSKCLR58 ,DQMSK58 clear (Channel 58)" "No effect,Clear"
|
|
bitfld.long 0x04 25. " DQMSKCLR57 ,DQMSK57 clear (Channel 57)" "No effect,Clear"
|
|
bitfld.long 0x04 24. " DQMSKCLR56 ,DQMSK56 clear (Channel 56)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 23. " DQMSKCLR55 ,DQMSK55 clear (Channel 55)" "No effect,Clear"
|
|
bitfld.long 0x04 22. " DQMSKCLR54 ,DQMSK54 clear (Channel 54)" "No effect,Clear"
|
|
bitfld.long 0x04 21. " DQMSKCLR53 ,DQMSK53 clear (Channel 53)" "No effect,Clear"
|
|
bitfld.long 0x04 20. " DQMSKCLR52 ,DQMSK52 clear (Channel 52)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 19. " DQMSKCLR51 ,DQMSK51 clear (Channel 51)" "No effect,Clear"
|
|
bitfld.long 0x04 18. " DQMSKCLR50 ,DQMSK50 clear (Channel 50)" "No effect,Clear"
|
|
bitfld.long 0x04 17. " DQMSKCLR49 ,DQMSK49 clear (Channel 49)" "No effect,Clear"
|
|
bitfld.long 0x04 16. " DQMSKCLR48 ,DQMSK48 clear (Channel 48)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 15. " DQMSKCLR47 ,DQMSK47 clear (Channel 47)" "No effect,Clear"
|
|
bitfld.long 0x04 14. " DQMSKCLR46 ,DQMSK46 clear (Channel 46)" "No effect,Clear"
|
|
bitfld.long 0x04 13. " DQMSKCLR45 ,DQMSK45 clear (Channel 45)" "No effect,Clear"
|
|
bitfld.long 0x04 12. " DQMSKCLR44 ,DQMSK44 clear (Channel 44)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 11. " DQMSKCLR43 ,DQMSK clear 43 (Channel 43)" "No effect,Clear"
|
|
bitfld.long 0x04 10. " DQMSKCLR42 ,DQMSK clear 42 (Channel 42)" "No effect,Clear"
|
|
bitfld.long 0x04 9. " DQMSKCLR41 ,DQMSK clear 41 (Channel 41)" "No effect,Clear"
|
|
bitfld.long 0x04 8. " DQMSKCLR40 ,DQMSK clear 40 (Channel 40)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " DQMSKCLR39 ,DQMSK clear 39 (Channel 39)" "No effect,Clear"
|
|
bitfld.long 0x04 6. " DQMSKCLR38 ,DQMSK clear 38 (Channel 38)" "No effect,Clear"
|
|
bitfld.long 0x04 5. " DQMSKCLR37 ,DQMSK clear 37 (Channel 37)" "No effect,Clear"
|
|
bitfld.long 0x04 4. " DQMSKCLR36 ,DQMSK clear 36 (Channel 36)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DQMSKCLR35 ,DQMSK clear 35 (Channel 35)" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DQMSKCLR34 ,DQMSK clear 34 (Channel 34)" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DQMSKCLR33 ,DQMSK clear 33 (Channel 33)" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DQMSKCLR32 ,DQMSK clear 32 (Channel 32)" "No effect,Clear"
|
|
sif !cpuis("S6E1C12*")&&!cpuis("S6E1C32*")&&!cpuis("S6E1C11*")&&!cpuis("S6E1C31*")
|
|
wgroup.long 0x98++0x07
|
|
line.long 0x00 "DQMSKCLR[95:64],Register For Clearing The DQMSK"
|
|
bitfld.long 0x00 31. " DQMSKCLR95 ,DQMSK95 clear (Channel 95)" "No effect,Clear"
|
|
bitfld.long 0x00 30. " DQMSKCLR94 ,DQMSK94 clear (Channel 94)" "No effect,Clear"
|
|
bitfld.long 0x00 29. " DQMSKCLR93 ,DQMSK93 clear (Channel 93)" "No effect,Clear"
|
|
bitfld.long 0x00 28. " DQMSKCLR92 ,DQMSK92 clear (Channel 92)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DQMSKCLR91 ,DQMSK91 clear (Channel 91)" "No effect,Clear"
|
|
bitfld.long 0x00 26. " DQMSKCLR90 ,DQMSK90 clear (Channel 90)" "No effect,Clear"
|
|
bitfld.long 0x00 25. " DQMSKCLR89 ,DQMSK89 clear (Channel 89)" "No effect,Clear"
|
|
bitfld.long 0x00 24. " DQMSKCLR88 ,DQMSK88 clear (Channel 88)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DQMSKCLR87 ,DQMSK87 clear (Channel 87)" "No effect,Clear"
|
|
bitfld.long 0x00 22. " DQMSKCLR86 ,DQMSK86 clear (Channel 86)" "No effect,Clear"
|
|
bitfld.long 0x00 21. " DQMSKCLR85 ,DQMSK85 clear (Channel 85)" "No effect,Clear"
|
|
bitfld.long 0x00 20. " DQMSKCLR84 ,DQMSK84 clear (Channel 84)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DQMSKCLR83 ,DQMSK83 clear (Channel 83)" "No effect,Clear"
|
|
bitfld.long 0x00 18. " DQMSKCLR82 ,DQMSK82 clear (Channel 82)" "No effect,Clear"
|
|
bitfld.long 0x00 17. " DQMSKCLR81 ,DQMSK81 clear (Channel 81)" "No effect,Clear"
|
|
bitfld.long 0x00 16. " DQMSKCLR80 ,DQMSK80 clear (Channel 80)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DQMSKCLR79 ,DQMSK79 clear (Channel 79)" "No effect,Clear"
|
|
bitfld.long 0x00 14. " DQMSKCLR78 ,DQMSK78 clear (Channel 78)" "No effect,Clear"
|
|
bitfld.long 0x00 13. " DQMSKCLR77 ,DQMSK77 clear (Channel 77)" "No effect,Clear"
|
|
bitfld.long 0x00 12. " DQMSKCLR76 ,DQMSK76 clear (Channel 76)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DQMSKCLR75 ,DQMSK clear 75 (Channel 75)" "No effect,Clear"
|
|
bitfld.long 0x00 10. " DQMSKCLR74 ,DQMSK clear 74 (Channel 74)" "No effect,Clear"
|
|
bitfld.long 0x00 9. " DQMSKCLR73 ,DQMSK clear 73 (Channel 73)" "No effect,Clear"
|
|
bitfld.long 0x00 8. " DQMSKCLR72 ,DQMSK clear 72 (Channel 72)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DQMSKCLR71 ,DQMSK clear 71 (Channel 71)" "No effect,Clear"
|
|
bitfld.long 0x00 6. " DQMSKCLR70 ,DQMSK clear 70 (Channel 70)" "No effect,Clear"
|
|
bitfld.long 0x00 5. " DQMSKCLR69 ,DQMSK clear 69 (Channel 69)" "No effect,Clear"
|
|
bitfld.long 0x00 4. " DQMSKCLR68 ,DQMSK clear 68 (Channel 68)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DQMSKCLR67 ,DQMSK clear 67 (Channel 67)" "No effect,Clear"
|
|
bitfld.long 0x00 2. " DQMSKCLR66 ,DQMSK clear 66 (Channel 66)" "No effect,Clear"
|
|
bitfld.long 0x00 1. " DQMSKCLR65 ,DQMSK clear 65 (Channel 65)" "No effect,Clear"
|
|
bitfld.long 0x00 0. " DQMSKCLR64 ,DQMSK clear 64 (Channel 64)" "No effect,Clear"
|
|
line.long 0x04 "DQMSKCLR[127:96],Register For Clearing The DQMSK"
|
|
bitfld.long 0x04 31. " DQMSKCLR127 ,DQMSK127 clear (Channel 127)" "No effect,Clear"
|
|
bitfld.long 0x04 30. " DQMSKCLR126 ,DQMSK126 clear (Channel 126)" "No effect,Clear"
|
|
bitfld.long 0x04 29. " DQMSKCLR125 ,DQMSK125 clear (Channel 125)" "No effect,Clear"
|
|
bitfld.long 0x04 28. " DQMSKCLR124 ,DQMSK124 clear (Channel 124)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 27. " DQMSKCLR123 ,DQMSK123 clear (Channel 123)" "No effect,Clear"
|
|
bitfld.long 0x04 26. " DQMSKCLR122 ,DQMSK122 clear (Channel 122)" "No effect,Clear"
|
|
bitfld.long 0x04 25. " DQMSKCLR121 ,DQMSK121 clear (Channel 121)" "No effect,Clear"
|
|
bitfld.long 0x04 24. " DQMSKCLR120 ,DQMSK120 clear (Channel 120)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 23. " DQMSKCLR119 ,DQMSK119 clear (Channel 119)" "No effect,Clear"
|
|
bitfld.long 0x04 22. " DQMSKCLR118 ,DQMSK118 clear (Channel 118)" "No effect,Clear"
|
|
bitfld.long 0x04 21. " DQMSKCLR117 ,DQMSK117 clear (Channel 117)" "No effect,Clear"
|
|
bitfld.long 0x04 20. " DQMSKCLR116 ,DQMSK116 clear (Channel 116)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 19. " DQMSKCLR115 ,DQMSK115 clear (Channel 115)" "No effect,Clear"
|
|
bitfld.long 0x04 18. " DQMSKCLR114 ,DQMSK114 clear (Channel 114)" "No effect,Clear"
|
|
bitfld.long 0x04 17. " DQMSKCLR113 ,DQMSK113 clear (Channel 113)" "No effect,Clear"
|
|
bitfld.long 0x04 16. " DQMSKCLR112 ,DQMSK112 clear (Channel 112)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 15. " DQMSKCLR111 ,DQMSK111 clear (Channel 111)" "No effect,Clear"
|
|
bitfld.long 0x04 14. " DQMSKCLR110 ,DQMSK110 clear (Channel 110)" "No effect,Clear"
|
|
bitfld.long 0x04 13. " DQMSKCLR109 ,DQMSK109 clear (Channel 109)" "No effect,Clear"
|
|
bitfld.long 0x04 12. " DQMSKCLR108 ,DQMSK108 clear (Channel 108)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 11. " DQMSKCLR107 ,DQMSK clear 107 (Channel 107)" "No effect,Clear"
|
|
bitfld.long 0x04 10. " DQMSKCLR106 ,DQMSK clear 106 (Channel 106)" "No effect,Clear"
|
|
bitfld.long 0x04 9. " DQMSKCLR105 ,DQMSK clear 105 (Channel 105)" "No effect,Clear"
|
|
bitfld.long 0x04 8. " DQMSKCLR104 ,DQMSK clear 104 (Channel 104)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " DQMSKCLR103 ,DQMSK clear 103 (Channel 103)" "No effect,Clear"
|
|
bitfld.long 0x04 6. " DQMSKCLR102 ,DQMSK clear 102 (Channel 102)" "No effect,Clear"
|
|
bitfld.long 0x04 5. " DQMSKCLR101 ,DQMSK clear 101 (Channel 101)" "No effect,Clear"
|
|
bitfld.long 0x04 4. " DQMSKCLR100 ,DQMSK clear 100 (Channel 100)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DQMSKCLR99 ,DQMSK clear 99 (Channel 99)" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DQMSKCLR98 ,DQMSK clear 98 (Channel 98)" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DQMSKCLR97 ,DQMSK clear 97 (Channel 97)" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DQMSKCLR96 ,DQMSK clear 96 (Channel 96)" "No effect,Clear"
|
|
sif cpuis("S6E2C*")
|
|
wgroup.long 0xA0++0x0F
|
|
line.long 0x00 "DQMSKCLR[159:128],Register For Clearing The DQMSK"
|
|
bitfld.long 0x00 31. " DQMSKCLR159 ,DQMSK159 clear (Channel 159)" "No effect,Clear"
|
|
bitfld.long 0x00 30. " DQMSKCLR158 ,DQMSK158 clear (Channel 158)" "No effect,Clear"
|
|
bitfld.long 0x00 29. " DQMSKCLR157 ,DQMSK157 clear (Channel 157)" "No effect,Clear"
|
|
bitfld.long 0x00 28. " DQMSKCLR156 ,DQMSK156 clear (Channel 156)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DQMSKCLR155 ,DQMSK155 clear (Channel 155)" "No effect,Clear"
|
|
bitfld.long 0x00 26. " DQMSKCLR154 ,DQMSK154 clear (Channel 154)" "No effect,Clear"
|
|
bitfld.long 0x00 25. " DQMSKCLR153 ,DQMSK153 clear (Channel 153)" "No effect,Clear"
|
|
bitfld.long 0x00 24. " DQMSKCLR152 ,DQMSK152 clear (Channel 152)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DQMSKCLR151 ,DQMSK151 clear (Channel 151)" "No effect,Clear"
|
|
bitfld.long 0x00 22. " DQMSKCLR150 ,DQMSK150 clear (Channel 150)" "No effect,Clear"
|
|
bitfld.long 0x00 21. " DQMSKCLR149 ,DQMSK149 clear (Channel 149)" "No effect,Clear"
|
|
bitfld.long 0x00 20. " DQMSKCLR148 ,DQMSK148 clear (Channel 148)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DQMSKCLR147 ,DQMSK147 clear (Channel 147)" "No effect,Clear"
|
|
bitfld.long 0x00 18. " DQMSKCLR146 ,DQMSK146 clear (Channel 146)" "No effect,Clear"
|
|
bitfld.long 0x00 17. " DQMSKCLR145 ,DQMSK145 clear (Channel 145)" "No effect,Clear"
|
|
bitfld.long 0x00 16. " DQMSKCLR144 ,DQMSK144 clear (Channel 144)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DQMSKCLR143 ,DQMSK143 clear (Channel 143)" "No effect,Clear"
|
|
bitfld.long 0x00 14. " DQMSKCLR142 ,DQMSK142 clear (Channel 142)" "No effect,Clear"
|
|
bitfld.long 0x00 13. " DQMSKCLR141 ,DQMSK141 clear (Channel 141)" "No effect,Clear"
|
|
bitfld.long 0x00 12. " DQMSKCLR140 ,DQMSK140 clear (Channel 140)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DQMSKCLR139 ,DQMSK clear 139 (Channel 139)" "No effect,Clear"
|
|
bitfld.long 0x00 10. " DQMSKCLR138 ,DQMSK clear 138 (Channel 138)" "No effect,Clear"
|
|
bitfld.long 0x00 9. " DQMSKCLR137 ,DQMSK clear 137 (Channel 137)" "No effect,Clear"
|
|
bitfld.long 0x00 8. " DQMSKCLR136 ,DQMSK clear 136 (Channel 136)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DQMSKCLR135 ,DQMSK clear 135 (Channel 135)" "No effect,Clear"
|
|
bitfld.long 0x00 6. " DQMSKCLR134 ,DQMSK clear 134 (Channel 134)" "No effect,Clear"
|
|
bitfld.long 0x00 5. " DQMSKCLR133 ,DQMSK clear 133 (Channel 133)" "No effect,Clear"
|
|
bitfld.long 0x00 4. " DQMSKCLR132 ,DQMSK clear 132 (Channel 132)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DQMSKCLR131 ,DQMSK clear 131 (Channel 131)" "No effect,Clear"
|
|
bitfld.long 0x00 2. " DQMSKCLR130 ,DQMSK clear 130 (Channel 130)" "No effect,Clear"
|
|
bitfld.long 0x00 1. " DQMSKCLR129 ,DQMSK clear 129 (Channel 129)" "No effect,Clear"
|
|
bitfld.long 0x00 0. " DQMSKCLR128 ,DQMSK clear 128 (Channel 128)" "No effect,Clear"
|
|
line.long 0x04 "DQMSKCLR[191:160],Register For Clearing The DQMSK"
|
|
bitfld.long 0x04 31. " DQMSKCLR191 ,DQMSK191 clear (Channel 191)" "No effect,Clear"
|
|
bitfld.long 0x04 30. " DQMSKCLR190 ,DQMSK190 clear (Channel 190)" "No effect,Clear"
|
|
bitfld.long 0x04 29. " DQMSKCLR189 ,DQMSK189 clear (Channel 189)" "No effect,Clear"
|
|
bitfld.long 0x04 28. " DQMSKCLR188 ,DQMSK188 clear (Channel 188)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 27. " DQMSKCLR187 ,DQMSK187 clear (Channel 187)" "No effect,Clear"
|
|
bitfld.long 0x04 26. " DQMSKCLR186 ,DQMSK186 clear (Channel 186)" "No effect,Clear"
|
|
bitfld.long 0x04 25. " DQMSKCLR185 ,DQMSK185 clear (Channel 185)" "No effect,Clear"
|
|
bitfld.long 0x04 24. " DQMSKCLR184 ,DQMSK184 clear (Channel 184)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 23. " DQMSKCLR183 ,DQMSK183 clear (Channel 183)" "No effect,Clear"
|
|
bitfld.long 0x04 22. " DQMSKCLR182 ,DQMSK182 clear (Channel 182)" "No effect,Clear"
|
|
bitfld.long 0x04 21. " DQMSKCLR181 ,DQMSK181 clear (Channel 181)" "No effect,Clear"
|
|
bitfld.long 0x04 20. " DQMSKCLR180 ,DQMSK180 clear (Channel 180)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 19. " DQMSKCLR179 ,DQMSK179 clear (Channel 179)" "No effect,Clear"
|
|
bitfld.long 0x04 18. " DQMSKCLR178 ,DQMSK178 clear (Channel 178)" "No effect,Clear"
|
|
bitfld.long 0x04 17. " DQMSKCLR177 ,DQMSK177 clear (Channel 177)" "No effect,Clear"
|
|
bitfld.long 0x04 16. " DQMSKCLR176 ,DQMSK176 clear (Channel 176)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 15. " DQMSKCLR175 ,DQMSK175 clear (Channel 175)" "No effect,Clear"
|
|
bitfld.long 0x04 14. " DQMSKCLR174 ,DQMSK174 clear (Channel 174)" "No effect,Clear"
|
|
bitfld.long 0x04 13. " DQMSKCLR173 ,DQMSK173 clear (Channel 173)" "No effect,Clear"
|
|
bitfld.long 0x04 12. " DQMSKCLR172 ,DQMSK172 clear (Channel 172)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 11. " DQMSKCLR171 ,DQMSK clear 171 (Channel 171)" "No effect,Clear"
|
|
bitfld.long 0x04 10. " DQMSKCLR170 ,DQMSK clear 170 (Channel 170)" "No effect,Clear"
|
|
bitfld.long 0x04 9. " DQMSKCLR169 ,DQMSK clear 169 (Channel 169)" "No effect,Clear"
|
|
bitfld.long 0x04 8. " DQMSKCLR168 ,DQMSK clear 168 (Channel 168)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " DQMSKCLR167 ,DQMSK clear 167 (Channel 167)" "No effect,Clear"
|
|
bitfld.long 0x04 6. " DQMSKCLR166 ,DQMSK clear 166 (Channel 166)" "No effect,Clear"
|
|
bitfld.long 0x04 5. " DQMSKCLR165 ,DQMSK clear 165 (Channel 165)" "No effect,Clear"
|
|
bitfld.long 0x04 4. " DQMSKCLR164 ,DQMSK clear 164 (Channel 164)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DQMSKCLR163 ,DQMSK clear 163 (Channel 163)" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DQMSKCLR162 ,DQMSK clear 162 (Channel 162)" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DQMSKCLR161 ,DQMSK clear 161 (Channel 161)" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DQMSKCLR160 ,DQMSK clear 160 (Channel 160)" "No effect,Clear"
|
|
line.long 0x08 "DQMSKCLR[223:192],Register For Clearing The DQMSK"
|
|
bitfld.long 0x08 31. " DQMSKCLR223 ,DQMSK223 clear (Channel 223)" "No effect,Clear"
|
|
bitfld.long 0x08 30. " DQMSKCLR222 ,DQMSK222 clear (Channel 222)" "No effect,Clear"
|
|
bitfld.long 0x08 29. " DQMSKCLR221 ,DQMSK221 clear (Channel 221)" "No effect,Clear"
|
|
bitfld.long 0x08 28. " DQMSKCLR220 ,DQMSK220 clear (Channel 220)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 27. " DQMSKCLR219 ,DQMSK219 clear (Channel 219)" "No effect,Clear"
|
|
bitfld.long 0x08 26. " DQMSKCLR218 ,DQMSK218 clear (Channel 218)" "No effect,Clear"
|
|
bitfld.long 0x08 25. " DQMSKCLR217 ,DQMSK217 clear (Channel 217)" "No effect,Clear"
|
|
bitfld.long 0x08 24. " DQMSKCLR216 ,DQMSK216 clear (Channel 216)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 23. " DQMSKCLR215 ,DQMSK215 clear (Channel 215)" "No effect,Clear"
|
|
bitfld.long 0x08 22. " DQMSKCLR214 ,DQMSK214 clear (Channel 214)" "No effect,Clear"
|
|
bitfld.long 0x08 21. " DQMSKCLR213 ,DQMSK213 clear (Channel 213)" "No effect,Clear"
|
|
bitfld.long 0x08 20. " DQMSKCLR212 ,DQMSK212 clear (Channel 212)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 19. " DQMSKCLR211 ,DQMSK211 clear (Channel 211)" "No effect,Clear"
|
|
bitfld.long 0x08 18. " DQMSKCLR210 ,DQMSK210 clear (Channel 210)" "No effect,Clear"
|
|
bitfld.long 0x08 17. " DQMSKCLR209 ,DQMSK209 clear (Channel 209)" "No effect,Clear"
|
|
bitfld.long 0x08 16. " DQMSKCLR208 ,DQMSK208 clear (Channel 208)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 15. " DQMSKCLR207 ,DQMSK207 clear (Channel 207)" "No effect,Clear"
|
|
bitfld.long 0x08 14. " DQMSKCLR206 ,DQMSK206 clear (Channel 206)" "No effect,Clear"
|
|
bitfld.long 0x08 13. " DQMSKCLR205 ,DQMSK205 clear (Channel 205)" "No effect,Clear"
|
|
bitfld.long 0x08 12. " DQMSKCLR204 ,DQMSK204 clear (Channel 204)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 11. " DQMSKCLR203 ,DQMSK clear 203 (Channel 203)" "No effect,Clear"
|
|
bitfld.long 0x08 10. " DQMSKCLR202 ,DQMSK clear 202 (Channel 202)" "No effect,Clear"
|
|
bitfld.long 0x08 9. " DQMSKCLR201 ,DQMSK clear 201 (Channel 201)" "No effect,Clear"
|
|
bitfld.long 0x08 8. " DQMSKCLR200 ,DQMSK clear 200 (Channel 200)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 7. " DQMSKCLR199 ,DQMSK clear 199 (Channel 199)" "No effect,Clear"
|
|
bitfld.long 0x08 6. " DQMSKCLR198 ,DQMSK clear 198 (Channel 198)" "No effect,Clear"
|
|
bitfld.long 0x08 5. " DQMSKCLR197 ,DQMSK clear 197 (Channel 197)" "No effect,Clear"
|
|
bitfld.long 0x08 4. " DQMSKCLR196 ,DQMSK clear 196 (Channel 196)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DQMSKCLR195 ,DQMSK clear 195 (Channel 195)" "No effect,Clear"
|
|
bitfld.long 0x08 2. " DQMSKCLR194 ,DQMSK clear 194 (Channel 194)" "No effect,Clear"
|
|
bitfld.long 0x08 1. " DQMSKCLR193 ,DQMSK clear 193 (Channel 193)" "No effect,Clear"
|
|
bitfld.long 0x08 0. " DQMSKCLR192 ,DQMSK clear 192 (Channel 192)" "No effect,Clear"
|
|
line.long 0x0C "DQMSKCLR[255:224],Register For Clearing The DQMSK"
|
|
bitfld.long 0x0C 31. " DQMSKCLR255 ,DQMSK255 clear (Channel 255)" "No effect,Clear"
|
|
bitfld.long 0x0C 30. " DQMSKCLR254 ,DQMSK254 clear (Channel 254)" "No effect,Clear"
|
|
bitfld.long 0x0C 29. " DQMSKCLR253 ,DQMSK253 clear (Channel 253)" "No effect,Clear"
|
|
bitfld.long 0x0C 28. " DQMSKCLR252 ,DQMSK252 clear (Channel 252)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " DQMSKCLR251 ,DQMSK251 clear (Channel 251)" "No effect,Clear"
|
|
bitfld.long 0x0C 26. " DQMSKCLR250 ,DQMSK250 clear (Channel 250)" "No effect,Clear"
|
|
bitfld.long 0x0C 25. " DQMSKCLR249 ,DQMSK249 clear (Channel 249)" "No effect,Clear"
|
|
bitfld.long 0x0C 24. " DQMSKCLR248 ,DQMSK248 clear (Channel 248)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " DQMSKCLR247 ,DQMSK247 clear (Channel 247)" "No effect,Clear"
|
|
bitfld.long 0x0C 22. " DQMSKCLR246 ,DQMSK246 clear (Channel 246)" "No effect,Clear"
|
|
bitfld.long 0x0C 21. " DQMSKCLR245 ,DQMSK245 clear (Channel 245)" "No effect,Clear"
|
|
bitfld.long 0x0C 20. " DQMSKCLR244 ,DQMSK244 clear (Channel 244)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " DQMSKCLR243 ,DQMSK243 clear (Channel 243)" "No effect,Clear"
|
|
bitfld.long 0x0C 18. " DQMSKCLR242 ,DQMSK242 clear (Channel 242)" "No effect,Clear"
|
|
bitfld.long 0x0C 17. " DQMSKCLR241 ,DQMSK241 clear (Channel 241)" "No effect,Clear"
|
|
bitfld.long 0x0C 16. " DQMSKCLR240 ,DQMSK240 clear (Channel 240)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " DQMSKCLR239 ,DQMSK239 clear (Channel 239)" "No effect,Clear"
|
|
bitfld.long 0x0C 14. " DQMSKCLR238 ,DQMSK238 clear (Channel 238)" "No effect,Clear"
|
|
bitfld.long 0x0C 13. " DQMSKCLR237 ,DQMSK237 clear (Channel 237)" "No effect,Clear"
|
|
bitfld.long 0x0C 12. " DQMSKCLR236 ,DQMSK236 clear (Channel 236)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " DQMSKCLR235 ,DQMSK clear 235 (Channel 235)" "No effect,Clear"
|
|
bitfld.long 0x0C 10. " DQMSKCLR234 ,DQMSK clear 234 (Channel 234)" "No effect,Clear"
|
|
bitfld.long 0x0C 9. " DQMSKCLR233 ,DQMSK clear 233 (Channel 233)" "No effect,Clear"
|
|
bitfld.long 0x0C 8. " DQMSKCLR232 ,DQMSK clear 232 (Channel 232)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " DQMSKCLR231 ,DQMSK clear 231 (Channel 231)" "No effect,Clear"
|
|
bitfld.long 0x0C 6. " DQMSKCLR230 ,DQMSK clear 230 (Channel 230)" "No effect,Clear"
|
|
bitfld.long 0x0C 5. " DQMSKCLR229 ,DQMSK clear 229 (Channel 229)" "No effect,Clear"
|
|
bitfld.long 0x0C 4. " DQMSKCLR228 ,DQMSK clear 228 (Channel 228)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " DQMSKCLR227 ,DQMSK clear 227 (Channel 227)" "No effect,Clear"
|
|
bitfld.long 0x0C 2. " DQMSKCLR226 ,DQMSK clear 226 (Channel 226)" "No effect,Clear"
|
|
bitfld.long 0x0C 1. " DQMSKCLR225 ,DQMSK clear 225 (Channel 225)" "No effect,Clear"
|
|
bitfld.long 0x0C 0. " DQMSKCLR224 ,DQMSK clear 224 (Channel 224)" "No effect,Clear"
|
|
endif
|
|
endif
|
|
sif cpuis("S6E2C*")||cpuis("MB9B*")
|
|
base ad:((per.l(ad:0x40061000))+((per.l(ad:0x40061000+0x04))&0xFF)+0x00)
|
|
textline ""
|
|
if ((((per.l(ad:0x40061000))+((per.l(ad:0x40061000+0x04))&0xFF))&0x03)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DES0,Descriptor 0"
|
|
bitfld.long 0x00 28.--31. " PCHK ,Parity check" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--25. " ACK ,Acknowledge" "No acknowledge,Acknowledge,?..."
|
|
bitfld.long 0x00 23. " CHLK ,Chain lock" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DMSET ,DREQ mask set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " CHRS[5:4] ,Chain & return status" "No interrupt/No start,Interrupt/No start,No interrupt/Start succeeding,?..."
|
|
bitfld.long 0x00 18.--19. " CHRS[3:2] ,Chain & return status" "No interrupt/No start,Interrupt/No start,No interrupt/Start,?..."
|
|
bitfld.long 0x00 16.--17. " CHRS[1:0] ,Chain & return status" "No interrupt/No start,Interrupt/No start,No interrupt/Start succeeding,No interrupt/Start current"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. " DAC ,Destination address control" "No InnerReload/TWx1 inc,InnerReload/TWx1 inc,No InnerReload/TWx2 inc,InnerReload/TWx2 inc,No InnerReload/TWx4 inc,Unchanged,No InnerReload/TWx1 dec,InnerReload/TWx1 dec"
|
|
bitfld.long 0x00 10.--12. " SAC ,Source address control" "No InnerReload/TWx1 inc,InnerReload/TWx1 inc,No InnerReload/TWx2 inc,InnerReload/TWx2 inc,No InnerReload/TWx4 inc,Unchanged,No InnerReload/TWx1 dec,InnerReload/TWx1 dec"
|
|
bitfld.long 0x00 8.--9. " TW ,Transfer width" "8 bits,16 bits,32 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " ORL2 ,Outer reload" "DES3 not executed/DES6 not required,DES3 executed/DES6 required"
|
|
bitfld.long 0x00 6. " ORL1 ,Outer reload" "DES2 not executed/DES5 not required,DES2 executed/DES5 required"
|
|
bitfld.long 0x00 5. " ORL0 ,Outer reload" "DES1 not executed/DES4 not required,DES1 executed/DES4 required"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODE ,Transfer mode" "Mode 0,Mode 1"
|
|
rbitfld.long 0x00 2.--3. " ST ,Transfer status" "No error,Error/source,Error/destination,Error/standby"
|
|
bitfld.long 0x00 0.--1. " DV ,Descriptor valid" "CPU/No transfer/No close,DSTC/Transfer/Close,DSTC/No transfer/Close,DSTC/Transfer/No close"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DES0,Descriptor 0"
|
|
rbitfld.long 0x00 28.--31. " PCHK ,Parity check" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--25. " ACK ,Acknowledge" "No acknowledge,Acknowledge,?..."
|
|
rbitfld.long 0x00 23. " CHLK ,Chain lock" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " DMSET ,DREQ mask set" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 20.--21. " CHRS[5:4] ,Chain & return status" "No interrupt/No start,Interrupt/No start,No interrupt/Start succeeding,?..."
|
|
rbitfld.long 0x00 18.--19. " CHRS[3:2] ,Chain & return status" "No interrupt/No start,Interrupt/No start,No interrupt/Start,?..."
|
|
rbitfld.long 0x00 16.--17. " CHRS[1:0] ,Chain & return status" "No interrupt/No start,Interrupt/No start,No interrupt/Start succeeding,No interrupt/Start current."
|
|
textline " "
|
|
rbitfld.long 0x00 13.--15. " DAC ,Destination address control" "No InnerReload/TWx1 inc,InnerReload/TWx1 inc,No InnerReload/TWx2 inc,InnerReload/TWx2 inc,No InnerReload/TWx4 inc,Unchanged,No InnerReload/TWx1 dec,InnerReload/TWx1 dec"
|
|
rbitfld.long 0x00 10.--12. " SAC ,Source address control" "No InnerReload/TWx1 inc,InnerReload/TWx1 inc,No InnerReload/TWx2 inc,InnerReload/TWx2 inc,No InnerReload/TWx4 inc,Unchanged,No InnerReload/TWx1 dec,InnerReload/TWx1 dec"
|
|
rbitfld.long 0x00 8.--9. " TW ,Transfer width" "8 bits,16 bits,32 bits,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 7. " ORL2 ,Outer reload" "DES3 not executed/DES6 not required,DES3 executed/DES6 required"
|
|
rbitfld.long 0x00 6. " ORL1 ,Outer reload" "DES2 not executed/DES5 not required,DES2 executed/DES5 required"
|
|
rbitfld.long 0x00 5. " ORL0 ,Outer reload" "DES1 not executed/DES4 not required,DES1 executed/DES4 required"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " MODE ,Transfer mode" "Mode 0,Mode 1"
|
|
bitfld.long 0x00 2.--3. " ST ,Transfer status" "No error,Error/source,Error/destination,Error/standby"
|
|
bitfld.long 0x00 0.--1. " DV ,Descriptor valid" "CPU/No transfer/No close,DSTC/Transfer/Close,DSTC/No transfer/Close,DSTC/Transfer/No close"
|
|
endif
|
|
if ((((per.l(ad:0x40061000))+((per.l(ad:0x40061000+0x04))&0xFF))&0x10)==0x10)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DES1,Descriptor 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " ORM ,Outer loop remain"
|
|
hexmask.long.byte 0x00 8.--15. 1. " IRM ,Inner loop remain"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IIN ,Inner loop initial"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DES1,Descriptor 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " ORM ,Outer loop remain"
|
|
hexmask.long.word 0x00 0.--15. 1. " IIN ,Inner loop initial"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DES2,Descriptor 2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DES3,Descriptor 3"
|
|
if ((((per.l(ad:0x40061000))+((per.l(ad:0x40061000+0x04))&0xFF))&0xE0)==0x20)
|
|
if ((((per.l(ad:0x40061000))+((per.l(ad:0x40061000+0x04))&0xFF))&0x03)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "DES4,Descriptor 4"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "DES4,Descriptor 4"
|
|
endif
|
|
elif ((((per.l(ad:0x40061000))+((per.l(ad:0x40061000+0x04))&0xFF))&0xE0)==0x40)
|
|
if ((((per.l(ad:0x40061000))+((per.l(ad:0x40061000+0x04))&0xFF))&0x03)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "DES5,Descriptor 5"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "DES5,Descriptor 5"
|
|
endif
|
|
elif ((((per.l(ad:0x40061000))+((per.l(ad:0x40061000+0x04))&0xFF))&0xE0)==0x80)
|
|
if ((((per.l(ad:0x40061000))+((per.l(ad:0x40061000+0x04))&0xFF))&0x03)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "DES6,Descriptor 6"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "DES6,Descriptor 6"
|
|
endif
|
|
elif ((((per.l(ad:0x40061000))+((per.l(ad:0x40061000+0x04))&0xFF))&0xE0)==0x60)
|
|
if ((((per.l(ad:0x40061000))+((per.l(ad:0x40061000+0x04))&0xFF))&0x03)==0x00)
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "DES4,Descriptor 4"
|
|
line.long 0x04 "DES5,Descriptor 5"
|
|
else
|
|
rgroup.long 0x10++0x07
|
|
line.long 0x00 "DES4,Descriptor 4"
|
|
line.long 0x04 "DES5,Descriptor 5"
|
|
endif
|
|
elif ((((per.l(ad:0x40061000))+((per.l(ad:0x40061000+0x04))&0xFF))&0xE0)==0xA0)
|
|
if ((((per.l(ad:0x40061000))+((per.l(ad:0x40061000+0x04))&0xFF))&0x03)==0x00)
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "DES4,Descriptor 4"
|
|
line.long 0x04 "DES6,Descriptor 6"
|
|
else
|
|
rgroup.long 0x10++0x07
|
|
line.long 0x00 "DES4,Descriptor 4"
|
|
line.long 0x04 "DES6,Descriptor 6"
|
|
endif
|
|
elif ((((per.l(ad:0x40061000))+((per.l(ad:0x40061000+0x04))&0xFF))&0xE0)==0xC0)
|
|
if ((((per.l(ad:0x40061000))+((per.l(ad:0x40061000+0x04))&0xFF))&0x03)==0x00)
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "DES5,Descriptor 5"
|
|
line.long 0x04 "DES6,Descriptor 6"
|
|
else
|
|
rgroup.long 0x10++0x07
|
|
line.long 0x00 "DES5,Descriptor 5"
|
|
line.long 0x04 "DES6,Descriptor 6"
|
|
endif
|
|
elif ((((per.l(ad:0x40061000))+((per.l(ad:0x40061000+0x04))&0xFF))&0xE0)==0xE0)
|
|
if ((((per.l(ad:0x40061000))+((per.l(ad:0x40061000+0x04))&0xFF))&0x03)==0x00)
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "DES5,Descriptor 4"
|
|
line.long 0x04 "DES6,Descriptor 5"
|
|
line.long 0x08 "DES6,Descriptor 6"
|
|
else
|
|
rgroup.long 0x10++0x0B
|
|
line.long 0x00 "DES5,Descriptor 4"
|
|
line.long 0x04 "DES6,Descriptor 5"
|
|
line.long 0x08 "DES6,Descriptor 6"
|
|
endif
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "Watchdog Timer"
|
|
base ad:0x40012000
|
|
width 9.
|
|
tree.open "Software"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LOAD,Software Watchdog Timer Load Register"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "VALUE,Software Watchdog Timer Value Register"
|
|
if ((per.b((ad:0x40012000+0x08))&0x11)==0x11)
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "CONTROL,Software Watchdog Timer Control Register"
|
|
rbitfld.byte 0x00 4. " SPM ,Software Watchdog window watchdog mode enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2.--3. " TWD ,Timing window setting bit of the software watchdog (period of WdogLoad)" "100%,75%,50%,25%"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " INTEN ,Interrupt and counter enable bit of the software watchdog" "Disabled,Enabled"
|
|
elif ((per.b((ad:0x40012000+0x08))&0x01)==0x01)
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "CONTROL,Software Watchdog Timer Control Register"
|
|
rbitfld.byte 0x00 4. " SPM ,Software Watchdog window watchdog mode enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2.--3. " TWD ,Timing window setting bit of the software watchdog (period of WdogLoad)" "100%,75%,50%,25%"
|
|
bitfld.byte 0x00 1. " RESEN ,Reset enable bit of the software watchdog" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " INTEN ,Interrupt and counter enable bit of the software watchdog" "Disabled,Enabled"
|
|
elif ((per.b((ad:0x40012000+0x08))&0x10)==0x10)
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "CONTROL,Software Watchdog Timer Control Register"
|
|
bitfld.byte 0x00 4. " SPM ,Software Watchdog window watchdog mode enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. " TWD ,Timing window setting bit of the software watchdog (period of WdogLoad)" "100%,75%,50%,25%"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " INTEN ,Interrupt and counter enable bit of the software watchdog" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "CONTROL,Software Watchdog Timer Control Register"
|
|
bitfld.byte 0x00 4. " SPM ,Software Watchdog window watchdog mode enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. " TWD ,Timing window setting bit of the software watchdog (period of WdogLoad)" "100%,75%,50%,25%"
|
|
bitfld.byte 0x00 1. " RESEN ,Reset enable bit of the software watchdog" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " INTEN ,Interrupt and counter enable bit of the software watchdog" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "INTCLR,Software Watchdog Timer Clear Register"
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "RIS,Software Watchdog Timer Interrupt Status Register"
|
|
bitfld.byte 0x00 0. " RIS ,Software watchdog interrupt status bit" "Not generated,Generated"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "SPMC,Software Watchdog Timer Window Watchdog Mode Control Register"
|
|
bitfld.byte 0x00 0. " TGR ,Software watchdog trigger type bit" "Interrupt,Reset"
|
|
group.long 0xC00++0x003
|
|
line.long 0x00 "LOCK,Software Watchdog Timer Lock Register"
|
|
tree.end
|
|
sif cpuis("S6E1C*")
|
|
base ad:0x40011000
|
|
tree.open "Hardware"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LDR,Hardware Watchdog Timer Load Register"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "VLR,Hardware Watchdog Timer Value Register"
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "CTL,Hardware Watchdog Timer Value Register"
|
|
bitfld.byte 0x00 1. " RESEN ,Reset enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " INTEN ,Interrupt and counter enable" "Disabled,Enabled"
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "ICL,Hardware Watchdog Timer Clear Register"
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "RIS,Hardware Watchdog Timer Interrupt Status Register"
|
|
bitfld.byte 0x00 0. " RIS ,Interrupt status" "Not generated,Generated"
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "LCK,Hardware Watchdog Timer Lock Register"
|
|
tree.end
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree.open "Dual Timer"
|
|
tree "Timer 1"
|
|
base ad:0x40015000
|
|
width 9.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LOAD,Load Register"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "VALUE,Value Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CONTROL,Control Register"
|
|
bitfld.long 0x00 7. " TIMEREN ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TIMERMODE ,Mode bit" "Free-running,Periodic"
|
|
bitfld.long 0x00 5. " INTENABLE ,Interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " TIMERPRE ,Prescale bits" "1,1/16,1/256,"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TIMESIZE ,Counter size bit" "16-bit,32-bit"
|
|
bitfld.long 0x00 0. " ONESHOT ,One-shot mode bit" "Wrapping,One-shot"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "INTCLR,Interrupt Clear Register"
|
|
rgroup.long 0x10++0x07
|
|
line.long 0x00 "RIS,Interrupt Status Register"
|
|
bitfld.long 0x00 0. " TIMERRIS ,Interrupt status register bit" "Not generated,Generated"
|
|
line.long 0x04 "MIS,Masked Interrupt Status Register"
|
|
bitfld.long 0x04 0. " TIMERMIS ,Masked interrupt status bit" "Not generated,Generated"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "BGLOAD,Background Load Register"
|
|
width 0xB
|
|
tree.end
|
|
tree "Timer 2"
|
|
base ad:0x40015020
|
|
width 9.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LOAD,Load Register"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "VALUE,Value Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CONTROL,Control Register"
|
|
bitfld.long 0x00 7. " TIMEREN ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TIMERMODE ,Mode bit" "Free-running,Periodic"
|
|
bitfld.long 0x00 5. " INTENABLE ,Interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " TIMERPRE ,Prescale bits" "1,1/16,1/256,"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TIMESIZE ,Counter size bit" "16-bit,32-bit"
|
|
bitfld.long 0x00 0. " ONESHOT ,One-shot mode bit" "Wrapping,One-shot"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "INTCLR,Interrupt Clear Register"
|
|
rgroup.long 0x10++0x07
|
|
line.long 0x00 "RIS,Interrupt Status Register"
|
|
bitfld.long 0x00 0. " TIMERRIS ,Interrupt status register bit" "Not generated,Generated"
|
|
line.long 0x04 "MIS,Masked Interrupt Status Register"
|
|
bitfld.long 0x04 0. " TIMERMIS ,Masked interrupt status bit" "Not generated,Generated"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "BGLOAD,Background Load Register"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "Watch Counter Prescaler"
|
|
base ad:0x4003A000
|
|
width 10.
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "CLK_SEL,Clock Selection Register"
|
|
bitfld.word 0x00 8.--10. " SEL_OUT ,Output clock selection bit (WCCK3/WCCK2/WCCK1/WCCK0)" "2^15/2^14/2^13/2^12,2^25/2^24/2^23/2^22,2^4/2^3/2^2/2^1,2^8/2^7/2^6/2^5,2^12/2^11/2^10/2^9,2^19/2^18/2^17/2^16,2^23/2^22/2^21/2^20,"
|
|
bitfld.word 0x00 0.--1. " SEL_IN ,Input clock selection bit" "Sub clock,Main clock,CR,CLKLC"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "CLK_EN,Division Clock Enable Register"
|
|
bitfld.byte 0x00 1. " CLK_EN_R ,Division clock enable read bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " CLK_EN ,Division clock enable bit" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "Watch Counter"
|
|
base ad:0x4003A000
|
|
width 6.
|
|
group.byte 0x00++0x02
|
|
line.byte 0x00 "WCRD,Watch Counter Read Register"
|
|
rbitfld.byte 0x00 0.--5. " CTR ,Counter read bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x01 "WCRL,Watch Counter Reload Register"
|
|
bitfld.byte 0x01 0.--5. " RLC ,Counter reload value setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x02 "WCCR,Watch Counter Control Register"
|
|
bitfld.byte 0x02 5. " WCEN ,Watch counter operation enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x02 4. " WCOP ,Watch counter operating state flag" "Stopped,Active"
|
|
bitfld.byte 0x02 2.--3. " CS ,Count clock select bits" "WCCK0,WCCK1,WCCK2,WCCK3"
|
|
bitfld.byte 0x02 1. " WCIE ,Interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x02 0. " WCIF ,Interrupt request flag bit" "No underflow,Underflow"
|
|
width 0xB
|
|
tree.end
|
|
sif cpuis("S6E1C*")
|
|
tree "RTC (Real Time Clock)"
|
|
base ad:0x4003B000
|
|
width 10.
|
|
tree "RTC Count Block"
|
|
group.long 0x00++0x0b
|
|
line.long 0x00 "WTCR1,Control Register 1"
|
|
bitfld.long 0x00 31. " INTCRIE ,Year/month/date/hour/minute/second/day of the week counter value read completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " INTERIE ,Time rewrite error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INTALIE ,Alarm interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " INTTMIE ,Timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " INTHIE ,1-hour interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INTMIE ,1-minute interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INTSIE ,1-second interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " INTSSIE ,0.5-second interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " INTCRI ,Year/month/date/hour/minute/second/day of the week counter value read completion interrupt flag [read/write]" "No interrupt/Cleared,Interrupt/No Effect"
|
|
bitfld.long 0x00 22. " INTERI ,Time rewrite error interrupt flag" "No interrupt/Cleared,Interrupt/No Effect"
|
|
bitfld.long 0x00 21. " INTALI ,Alarm interrupt flag" "No interrupt/Cleared,Interrupt/No Effect"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INTTMI ,Timer interrupt flag" "No interrupt/Cleared,Interrupt/No Effect"
|
|
bitfld.long 0x00 19. " INTHI ,1-hour interrupt flag" "No interrupt/Cleared,Interrupt/No Effect"
|
|
bitfld.long 0x00 18. " INTMI ,1-minute interrupt flag" "No interrupt/Cleared,Interrupt/No Effect"
|
|
textline " "
|
|
bitfld.long 0x00 17. " INTSI ,1-second interrupt flag" "No interrupt/Cleared,Interrupt/No Effect"
|
|
bitfld.long 0x00 16. " INTSSI ,0.5-second interrupt flag" "No interrupt/Cleared,Interrupt/No Effect"
|
|
textline " "
|
|
bitfld.long 0x00 12. " YEN ,Alarm year register enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " MOEN ,Alarm month register enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DEN ,Alarm date register enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " HEN ,Alarm hour register enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MIEN ,Alarm minute register enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " BUSY ,Indicates that time rewriting is in process" "Idle,Busy"
|
|
bitfld.long 0x00 5. " SCRST ,Sub second generation/1-second generation counter reset" "No reset,Reset"
|
|
bitfld.long 0x00 4. " SCST ,1-second clock output stop" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SRST ,RTC reset bit" "Completed,Reset"
|
|
rbitfld.long 0x00 2. " RUN ,RTC count block operation" "No operation,Operation"
|
|
bitfld.long 0x00 0. " ST ,Operation start" "Stopped,Started"
|
|
line.long 0x04 "WTCR2,Control Register 2"
|
|
rbitfld.long 0x04 10. " TMRUN ,Timer counter operation" "No operation,Operation"
|
|
bitfld.long 0x04 9. " TMEN ,Timer counter control" "Time elapse,Time intervals"
|
|
textline " "
|
|
bitfld.long 0x04 8. " TMST ,Timer counter start" "Stopped,Started"
|
|
bitfld.long 0x04 0. " CREAD ,Year/month/date/hour/minute/second/day of the week counter value read control [read/write]" "Completed/No effect,In progress/Copied"
|
|
line.long 0x08 "WTBR,Counter Cycle Setting Register"
|
|
bitfld.long 0x08 23. " BR23 ,Counter cycle setting bit [23]" "0,1"
|
|
bitfld.long 0x08 22. " BR22 ,Counter cycle setting bit [22]" "0,1"
|
|
bitfld.long 0x08 21. " BR21 ,Counter cycle setting bit [21]" "0,1"
|
|
bitfld.long 0x08 20. " BR20 ,Counter cycle setting bit [20]" "0,1"
|
|
bitfld.long 0x08 19. " BR19 ,Counter cycle setting bit [19]" "0,1"
|
|
bitfld.long 0x08 18. " BR18 ,Counter cycle setting bit [18]" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 17. " BR17 ,Counter cycle setting bit [17]" "0,1"
|
|
bitfld.long 0x08 16. " BR16 ,Counter cycle setting bit [16]" "0,1"
|
|
bitfld.long 0x08 15. " BR15 ,Counter cycle setting bit [15]" "0,1"
|
|
bitfld.long 0x08 14. " BR14 ,Counter cycle setting bit [14]" "0,1"
|
|
bitfld.long 0x08 13. " BR13 ,Counter cycle setting bit [13]" "0,1"
|
|
bitfld.long 0x08 12. " BR12 ,Counter cycle setting bit [12]" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 11. " BR11 ,Counter cycle setting bit [11]" "0,1"
|
|
bitfld.long 0x08 10. " BR10 ,Counter cycle setting bit [10]" "0,1"
|
|
bitfld.long 0x08 9. " BR9 ,Counter cycle setting bit [9]" "0,1"
|
|
bitfld.long 0x08 8. " BR8 ,Counter cycle setting bit [8]" "0,1"
|
|
bitfld.long 0x08 7. " BR7 ,Counter cycle setting bit [7]" "0,1"
|
|
bitfld.long 0x08 6. " BR6 ,Counter cycle setting bit [6]" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 5. " BR5 ,Counter cycle setting bit [5]" "0,1"
|
|
bitfld.long 0x08 4. " BR4 ,Counter cycle setting bit [4]" "0,1"
|
|
bitfld.long 0x08 3. " BR3 ,Counter cycle setting bit [3]" "0,1"
|
|
bitfld.long 0x08 2. " BR2 ,Counter cycle setting bit [2]" "0,1"
|
|
bitfld.long 0x08 1. " BR1 ,Counter cycle setting bit [1]" "0,1"
|
|
bitfld.long 0x08 0. " BR0 ,Counter cycle setting bit [0]" "0,1"
|
|
if ((((d.b(ad:0x4003B000+0x11))&0x1f)==(0x01||0x3||0x5||0x7||0x8||0x10||0x12))&&(((d.b(ad:0x4003B000+0x0f))&0x30)!=0x30)&&(((d.b(ad:0x4003B000+0x0f))&0x3f)!=0x00))
|
|
group.byte 0x0f++0x00
|
|
line.byte 0x00 "WTDR,Date Register"
|
|
bitfld.byte 0x00 4.--5. " D ,Second digit of the date" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. ",First digit of the date" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif ((((d.b(ad:0x4003B000+0x11))&0x1f)==(0x01||0x3||0x5||0x7||0x8||0x10||0x12))&&(((d.b(ad:0x4003B000+0x0f))&0x3f)==0x00))
|
|
group.byte 0x0f++0x00
|
|
line.byte 0x00 "WTDR,Date Register"
|
|
bitfld.byte 0x00 4.--5. " D ,Second digit of the date" "-,1,2,3"
|
|
bitfld.byte 0x00 0.--3. ",First digit of the date" "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif ((((d.b(ad:0x4003B000+0x11))&0x1f)==(0x01||0x3||0x5||0x7||0x8||0x10||0x12))&&(((d.b(ad:0x4003B000+0x0f))&0x30)==0x30))
|
|
group.byte 0x0f++0x00
|
|
line.byte 0x00 "WTDR,Date Register"
|
|
bitfld.byte 0x00 4.--5. " D ,Second digit of the date" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. ",First digit of the date" "0,1,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
elif ((((d.b(ad:0x4003B000+0x11))&0x1f)==0x02)&&(((d.b(ad:0x4003B000+0x0f))&0x3f)!=0x00)&&(((d.b(ad:0x4003B000+0x0f))&0x30)!=0x30))
|
|
group.byte 0x0f++0x00
|
|
line.byte 0x00 "WTDR,Date Register"
|
|
bitfld.byte 0x00 4.--5. " D ,Second digit of the date" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",First digit of the date" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif ((((d.b(ad:0x4003B000+0x11))&0x1f)==0x02)&&(((d.b(ad:0x4003B000+0x0f))&0x3f)!=0x00)&&(((d.b(ad:0x4003B000+0x0f))&0x30)==0x30))
|
|
group.byte 0x0f++0x00
|
|
line.byte 0x00 "WTDR,Date Register"
|
|
bitfld.byte 0x00 4.--5. " D ,Second digit of the date" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",First digit of the date" "-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
elif ((((d.b(ad:0x4003B000+0x11))&0x1f)==0x02)&&(((d.b(ad:0x4003B000+0x0f))&0x3f)==0x00))
|
|
group.byte 0x0f++0x00
|
|
line.byte 0x00 "WTDR,Date Register"
|
|
bitfld.byte 0x00 4.--5. " D ,Second digit of the date" "-,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",First digit of the date" "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif ((((d.b(ad:0x4003B000+0x11))&0x1f)==(0x04||0x06||0x09||0x11))&&(((d.b(ad:0x4003B000+0x0f))&0x30)!=0x30)&&(((d.b(ad:0x4003B000+0x0f))&0x3f)!=0x00))
|
|
group.byte 0x0f++0x00
|
|
line.byte 0x00 "WTDR,Date Register"
|
|
bitfld.byte 0x00 4.--5. " D ,Second digit of the date" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. ",First digit of the date" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif ((((d.b(ad:0x4003B000+0x11))&0x1f)==(0x04||0x06||0x09||0x11))&&(((d.b(ad:0x4003B000+0x0f))&0x3f)==0x00))
|
|
group.byte 0x0f++0x00
|
|
line.byte 0x00 "WTDR,Date Register"
|
|
bitfld.byte 0x00 4.--5. " D ,Second digit of the date" "-,1,2,3"
|
|
bitfld.byte 0x00 0.--3. ",First digit of the date" "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif ((((d.b(ad:0x4003B000+0x11))&0x1f)==(0x04||0x06||0x09||0x11))&&((d.b(ad:0x4003B000+0x0f))&0x30)==0x30)
|
|
group.byte 0x0f++0x00
|
|
line.byte 0x00 "WTDR,Date Register"
|
|
bitfld.byte 0x00 4.--5. " D ,Second digit of the date" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. ",First digit of the date" "0,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
else
|
|
group.byte 0x0f++0x00
|
|
line.byte 0x00 "WTDR,Date Register"
|
|
bitfld.byte 0x00 4.--5. " D ,Second digit of the date" "-,?..."
|
|
bitfld.byte 0x00 0.--3. ",First digit of the date" "-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
endif
|
|
if (((d.b(ad:0x4003B000+0x0e))&0x30)==(0x00||0x10))
|
|
group.byte 0x0e++0x00
|
|
line.byte 0x00 "WTHR,Hour Register"
|
|
bitfld.byte 0x00 4.--5. " H ,Second digit of the hour" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",First digit of the hour" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((d.b(ad:0x4003B000+0x0e))&0x30)==0x20)
|
|
group.byte 0x0e++0x00
|
|
line.byte 0x00 "WTHR,Hour Register"
|
|
bitfld.byte 0x00 4.--5. " H ,Second digit of the hour" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",First digit of the hour" "0,1,2,3,-,-,-,-,-,-,-,-,-,?..."
|
|
else
|
|
group.byte 0x0e++0x00
|
|
line.byte 0x00 "WTHR,Hour Register"
|
|
bitfld.byte 0x00 4.--5. " H ,Second digit of the hour" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",First digit of the hour" "-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
endif
|
|
group.byte 0x0d++0x00
|
|
line.byte 0x00 "WTMIR,Minute Register"
|
|
bitfld.byte 0x00 4.--6. " MI ,Second digit of the minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.byte 0x00 0.--3. ",First digit of the minute" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
group.byte 0x0c++0x00
|
|
line.byte 0x00 "WTSR,Second Register"
|
|
bitfld.byte 0x00 4.--6. " S ,Second digit of the second" "0,1,2,3,4,5,-,-"
|
|
bitfld.byte 0x00 0.--3. ",First digit of the second" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "WTYR,Year Register"
|
|
bitfld.byte 0x00 4.--7. " Y ,First digit of the year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.byte 0x00 0.--3. ",First digit of the year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
if (((d.b(ad:0x4003B000+0x11))&0x10)==0x00)
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "WTMOR,Month Register"
|
|
bitfld.byte 0x00 4. " MO ,Second digit of the month" "0,1"
|
|
bitfld.byte 0x00 0.--3. ",First digit of the month" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
else
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "WTMOR,Month Register"
|
|
bitfld.byte 0x00 4. " MO ,Second digit of the month" "0,1"
|
|
bitfld.byte 0x00 0.--3. ",First digit of the month" "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "WTDW,Day of the Week Register"
|
|
bitfld.byte 0x00 0.--2. " DW ,Day of the week" "Sunday,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,-"
|
|
if ((((d.b(ad:0x4003B000+0x19))&0x1f)==(0x01||0x3||0x5||0x7||0x8||0x10||0x12))&&(((d.b(ad:0x4003B000+0x17))&0x30)!=0x30)&&(((d.b(ad:0x4003B000+0x17))&0x3f)!=0x00))
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "ALDR,Alarm Date Register"
|
|
bitfld.byte 0x00 4.--5. " AD ,Second digit of the alarm-set date" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. ",First digit of the alarm-set date" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif ((((d.b(ad:0x4003B000+0x19))&0x1f)==(0x01||0x3||0x5||0x7||0x8||0x10||0x12))&&(((d.b(ad:0x4003B000+0x17))&0x30)!=0x30)&&(((d.b(ad:0x4003B000+0x17))&0x3f)==0x00))
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "ALDR,Alarm Date Register"
|
|
bitfld.byte 0x00 4.--5. " AD ,Second digit of the alarm-set date" "-,1,2,3"
|
|
bitfld.byte 0x00 0.--3. ",First digit of the alarm-set date" "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif ((((d.b(ad:0x4003B000+0x19))&0x1f)==(0x01||0x3||0x5||0x7||0x8||0x10||0x12))&&(((d.b(ad:0x4003B000+0x17))&0x30)==0x30))
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "ALDR,Alarm Date Register"
|
|
bitfld.byte 0x00 4.--5. " AD ,Second digit of the alarm-set date" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. ",First digit of the alarm-set date" "0,1,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
elif ((((d.b(ad:0x4003B000+0x19))&0x1f)==0x02)&&(((d.b(ad:0x4003B000+0x17))&0x3f)!=0x00)&&(((d.b(ad:0x4003B000+0x17))&0x30)!=0x30))
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "ALDR,Alarm Date Register"
|
|
bitfld.byte 0x00 4.--5. " AD ,Second digit of the alarm-set date" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",First digit of the alarm-set date" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif ((((d.b(ad:0x4003B000+0x19))&0x1f)==0x02)&&(((d.b(ad:0x4003B000+0x17))&0x3f)==0x00))
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "ALDR,Alarm Date Register"
|
|
bitfld.byte 0x00 4.--5. " AD ,Second digit of the alarm-set date" "-,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",First digit of the alarm-set date" "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif ((((d.b(ad:0x4003B000+0x19))&0x1f)==0x02)&&(((d.b(ad:0x4003B000+0x17))&0x3f)!=0x00)&&(((d.b(ad:0x4003B000+0x17))&0x30)==0x30))
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "ALDR,Alarm Date Register"
|
|
bitfld.byte 0x00 4.--5. " AD ,Second digit of the alarm-set date" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",First digit of the alarm-set date" "-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
elif ((((d.b(ad:0x4003B000+0x19))&0x1f)==(0x04||0x06||0x09||0x19))&&(((d.b(ad:0x4003B000+0x17))&0x30)!=0x30)&&(((d.b(ad:0x4003B000+0x17))&0x3f)!=0x00))
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "ALDR,Alarm Date Register"
|
|
bitfld.byte 0x00 4.--5. " AD ,Second digit of the alarm-set date" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. ",First digit of the alarm-set date" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif ((((d.b(ad:0x4003B000+0x19))&0x1f)==(0x04||0x06||0x09||0x19))&&(((d.b(ad:0x4003B000+0x17))&0x30)!=0x30)&&(((d.b(ad:0x4003B000+0x17))&0x3f)==0x00))
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "ALDR,Alarm Date Register"
|
|
bitfld.byte 0x00 4.--5. " AD ,Second digit of the alarm-set date" "-,1,2,3"
|
|
bitfld.byte 0x00 0.--3. ",First digit of the alarm-set date" "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif ((((d.b(ad:0x4003B000+0x19))&0x1f)==(0x04||0x06||0x09||0x19))&&((d.b(ad:0x4003B000+0x17))&0x30)==0x30)
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "ALDR,Alarm Date Register"
|
|
bitfld.byte 0x00 4.--5. " AD ,Second digit of the alarm-set date" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. ",First digit of the alarm-set date" "0,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
else
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "ALDR,Alarm Date Register"
|
|
bitfld.byte 0x00 4.--5. " AD ,Second digit of the alarm-set date" "-,?..."
|
|
bitfld.byte 0x00 0.--3. ",First digit of the alarm-set date" "-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
endif
|
|
if (((d.b(ad:0x4003B000+0x16))&0x30)==(0x00||0x10))
|
|
group.byte 0x16++0x00
|
|
line.byte 0x00 "ALHR,Alarm Hour Register"
|
|
bitfld.byte 0x00 4.--5. " AH ,Second digit of the alarm-set hour" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",First digit of the alarm-set hour" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((d.b(ad:0x4003B000+0x16))&0x30)==0x20)
|
|
group.byte 0x16++0x00
|
|
line.byte 0x00 "ALHR,Alarm Hour Register"
|
|
bitfld.byte 0x00 4.--5. " AH ,Second digit of the alarm-set hour" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",First digit of the alarm-set hour" "0,1,2,3,-,-,-,-,-,-,-,-,-,?..."
|
|
else
|
|
group.byte 0x16++0x00
|
|
line.byte 0x00 "ALHR,Alarm Hour Register"
|
|
bitfld.byte 0x00 4.--5. " AH ,Second digit of the alarm-set hour" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",First digit of the alarm-set hour" "-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
endif
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "ALMIR,Alarm Minute Register"
|
|
bitfld.byte 0x00 4.--6. " AMI ,Second digit of the alarm-set minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.byte 0x00 0.--3. ",First digit of the alarm-set minute" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "ALYR,Alarm Year Register"
|
|
bitfld.byte 0x00 4.--7. " AY ,First digit of the alarm-set year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.byte 0x00 0.--3. ",First digit of the alarm-set year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
if (((d.b(ad:0x4003B000+0x19))&0x10)==0x00)
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "ALMOR,Alarm Month Register"
|
|
bitfld.byte 0x00 4. " AMO ,Second digit of the alarm-set month" "0,1"
|
|
bitfld.byte 0x00 0.--3. ",First digit of the alarm-set month" "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
else
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "ALMOR,Alarm Month Register"
|
|
bitfld.byte 0x00 4. " AMO ,Second digit of the alarm-set month" "0,1"
|
|
bitfld.byte 0x00 0.--3. ",First digit of the alarm-set month" "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
endif
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "WTTR,Timer Setting Register"
|
|
bitfld.long 0x00 17. " TM17 ,Timer setting information bit [17]" "0,1"
|
|
bitfld.long 0x00 16. " TM16 ,Timer setting information bit [16]" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TM15 ,Timer setting information bit [15]" "0,1"
|
|
bitfld.long 0x00 14. " TM14 ,Timer setting information bit [14]" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TM13 ,Timer setting information bit [13]" "0,1"
|
|
bitfld.long 0x00 12. " TM12 ,Timer setting information bit [12]" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TM11 ,Timer setting information bit [11]" "0,1"
|
|
bitfld.long 0x00 10. " TM10 ,Timer setting information bit [10]" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TM9 ,Timer setting information bit [9]" "0,1"
|
|
bitfld.long 0x00 8. " TM8 ,Timer setting information bit [8]" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TM7 ,Timer setting information bit [7]" "0,1"
|
|
bitfld.long 0x00 6. " TM6 ,Timer setting information bit [6]" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TM5 ,Timer setting information bit [5]" "0,1"
|
|
bitfld.long 0x00 4. " TM4 ,Timer setting information bit [4]" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TM3 ,Timer setting information bit [3]" "0,1"
|
|
bitfld.long 0x00 2. " TM2 ,Timer setting information bit [2]" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TM1 ,Timer setting information bit [1]" "0,1"
|
|
bitfld.long 0x00 0. " TM0 ,Timer setting information bit [0]" "0,1"
|
|
tree.end
|
|
tree "RTC Clock Control Block"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "WTCLKS,Clock Selection Register"
|
|
bitfld.byte 0x00 0. " WTCLKS ,Input clock select" "Sub clock,Main clock"
|
|
rgroup.byte 0x21++0x00
|
|
line.byte 0x00 "WTCLKM,Selection Clock Status Register"
|
|
bitfld.byte 0x00 0.--1. " WTCLKM ,Clock selection status" "Not operating,Not operating,Sub clock,Main clock"
|
|
sif (cpuis("MB9AF?4?L")||cpuis("MB9AF?4?M")||cpuis("MB9AF?4?N")||cpuis("MB9AF?3?M")||cpuis("MB9AF?3?N")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9BF32??")||cpuis("MB9BF52??")||cpuis("MB9BF42?S")||cpuis("MB9BF42?T")||cpuis("MB9BF12??")||cpuis("MB9AF?21K")||cpuis("MB9AF?21L")||cpuis("MB9AF15?M")||cpuis("MB9AF15?N")||cpuis("MB9AF15?R")||cpuis("MB9AFAA??")||cpuis("MB9AF1A??"))
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "WTCAL,Frequency Correction Value Setting Register"
|
|
hexmask.word 0x00 0.--9. 1. " WTCAL ,Frequency correction value setting bits"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "WTCALEN,Frequency Correction Enable Register"
|
|
bitfld.byte 0x00 0. " WTCALEN ,Frequency correction enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x24++0x01
|
|
line.byte 0x00 "WTCAL,Frequency Correction Value Setting Register"
|
|
hexmask.byte 0x00 0.--6. 1. " WTCAL ,Frequency correction value setting bits"
|
|
line.byte 0x01 "WTCALEN,Frequency Correction Enable Register"
|
|
bitfld.byte 0x01 0. " WTCALEN ,Frequency correction enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x28++0x01
|
|
line.byte 0x00 "WTDIV,Divider Ratio Setting Register"
|
|
bitfld.byte 0x00 0.--3. " WTDIV ,Divider ratio" "Not divided,/2,/4,/8,/16,/32,/64,/128,/256,/512,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
line.byte 0x01 "WTDIVEN,Divider Output Enable Register"
|
|
rbitfld.byte 0x01 1. " WTDIVRDY ,Divider status" "No operation,Operation"
|
|
bitfld.byte 0x01 0. " WTDIVEN ,Divider enable" "Disabled,Enabled"
|
|
sif (cpuis("MB9AF?4?L")||cpuis("MB9AF?4?M")||cpuis("MB9AF?4?N")||cpuis("MB9AF?3?M")||cpuis("MB9AF?3?N")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9BF32??")||cpuis("MB9BF52??")||cpuis("MB9BF42?S")||cpuis("MB9BF42?T")||cpuis("MB9BF12??")||cpuis("MB9AF?21K")||cpuis("MB9AF?21L")||cpuis("MB9AF15?M")||cpuis("MB9AF15?N")||cpuis("MB9AF15?R")||cpuis("MB9AFAA??")||cpuis("MB9AF1A??"))
|
|
group.byte 0x2c++0x00
|
|
line.byte 0x00 "WTCALPRD,Frequency Correction Cycle Setting Register"
|
|
hexmask.byte 0x00 0.--5. 1. " WTCALPRD ,Frequency correction value setting bits"
|
|
group.byte 0x30++0x00
|
|
line.byte 0x00 "WTCOSEL,RTCCO Output Selection Register"
|
|
bitfld.byte 0x00 0. " WTCOSEL ,RTCCO output select" "CO,CO/2"
|
|
endif
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
else
|
|
tree.open "RTC (Real Time Clock)"
|
|
tree "RTC Count Block"
|
|
base ad:0x4003B000
|
|
width 7.
|
|
group.long 0x000++0x00B
|
|
line.long 0x00 "WTCR1,Control Register 1"
|
|
bitfld.long 0x00 31. " INTCRIE ,Year/month/date/hour/minute/second/day of the week counter value read completion interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " INTERIE ,Time rewrite error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " INTALIE ,Alarm interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " INTTMIE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " INTHIE ,1-hour interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INTMIE ,1-minute interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " INTSIE ,1-second interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " INTSSIE ,0.5-second interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " INTCRI ,Year/month/date/hour/minute/second/day of the week counter value read completion interrupt flag bit (read/write)" "No interrupt/Cleared,Interrupt/No effect"
|
|
bitfld.long 0x00 22. " INTERI ,Time rewrite error interrupt flag bit (read/write)" "No interrupt/Cleared,Interrupt/No effect"
|
|
bitfld.long 0x00 21. " INTALI ,Alarm coinciding flag bit (read/write)" "Not generated/Cleared,Generated/No effect"
|
|
bitfld.long 0x00 20. " INTTMI ,Timer underflow flag bit (read/write)" "Not generated/Cleared,Generated/No effect"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTHI ,1-hour flag bit (read/write)" "No interrupt/Cleared,Interrupt/No effect"
|
|
bitfld.long 0x00 18. " INTMI ,1-minute flag bit (read/write)" "No interrupt/Cleared,Interrupt/No effect"
|
|
bitfld.long 0x00 17. " INTSI ,1-second flag bit (read/write)" "No interrupt/Cleared,Interrupt/No effect"
|
|
bitfld.long 0x00 16. " INTSSI ,0.5-second flag bit (read/write)" "No interrupt/Cleared,Interrupt/No effect"
|
|
textline " "
|
|
bitfld.long 0x00 12. " YEN ,Alarm year register enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " MOEN ,Alarm month register enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DEN ,Alarm date register enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " HEN ,Alarm hour register enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MIEN ,Alarm minute register enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BUSY ,Busy bit" "Idle,Busy"
|
|
bitfld.long 0x00 5. " SCRST ,Sub second generation/1-second generation counter reset bit" "No reset,Reset"
|
|
bitfld.long 0x00 4. " SCST ,1-second clock output stop bit" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SRST ,RTC reset bit" "Completed,Reset"
|
|
rbitfld.long 0x00 2. " RUN ,RTC count block operation bit" "Not in operation,In operation"
|
|
bitfld.long 0x00 0. " ST ,Start bit" "Stop,Start"
|
|
line.long 0x04 "WTCR2,Control Register 2"
|
|
rbitfld.long 0x04 10. " TMRUN ,Timer counter operation bit" "Not in operation,In operation"
|
|
bitfld.long 0x04 9. " TMEN ,Timer counter control bit" "Time elapse,Time intervals"
|
|
bitfld.long 0x04 8. " TMST ,Timer counter start bit" "Stop,Start"
|
|
bitfld.long 0x04 0. " CREAD ,Year/month/date/hour/minute/second/day of the week counter value read control bit (read/write)" "Completed/No effect,In progress/Copied"
|
|
line.long 0x08 "WTBR,Counter Cycle Setting Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " BR ,Counter cycle setting"
|
|
textline " "
|
|
if ((d.b(ad:0x4003B000+0x11)&0x1f)==(0x01||0x03||0x05||0x07||0x08||0x10||0x12))&&((d.b(ad:0x4003B000+0x0F)&0x30)!=0x30)&&((d.b(ad:0x4003B000+0x0F)&0x3f)!=0x00)
|
|
group.byte 0x0F++0x00
|
|
line.byte 0x00 "WTDR,Date Register"
|
|
bitfld.byte 0x00 4.--5. " TD ,Second digit of the date" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the date" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif ((d.b(ad:0x4003B000+0x11)&0x1f)==(0x01||0x03||0x05||0x07||0x08||0x10||0x12))&&((d.b(ad:0x4003B000+0x0F)&0x3f)==0x00)
|
|
group.byte 0x0F++0x00
|
|
line.byte 0x00 "WTDR,Date Register"
|
|
bitfld.byte 0x00 4.--5. " TD ,Second digit of the date" "-,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the date" "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif ((d.b(ad:0x4003B000+0x11)&0x1f)==(0x01||0x03||0x05||0x07||0x08||0x10||0x12))&&((d.b(ad:0x4003B000+0x0F)&0x30)==0x30)
|
|
group.byte 0x0F++0x00
|
|
line.byte 0x00 "WTDR,Date Register"
|
|
bitfld.byte 0x00 4.--5. " TD ,Second digit of the date" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the date" "0,1,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
elif ((d.b(ad:0x4003B000+0x11)&0x1f)==(0x04||0x06||0x09||0x11))&&((d.b(ad:0x4003B000+0x0F)&0x30)!=0x30)&&((d.b(ad:0x4003B000+0x0F)&0x3f)!=0x00)
|
|
group.byte 0x0F++0x00
|
|
line.byte 0x00 "WTDR,Date Register"
|
|
bitfld.byte 0x00 4.--5. " TD ,Second digit of the date" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the date" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif ((d.b(ad:0x4003B000+0x11)&0x1f)==(0x04||0x06||0x09||0x11))&&((d.b(ad:0x4003B000+0x0F)&0x3f)==0x00)
|
|
group.byte 0x0F++0x00
|
|
line.byte 0x00 "WTDR,Date Register"
|
|
bitfld.byte 0x00 4.--5. " TD ,Second digit of the date" "-,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the date" "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif ((d.b(ad:0x4003B000+0x11)&0x1f)==(0x04||0x06||0x09||0x11))&&((d.b(ad:0x4003B000+0x0F)&0x30)==0x30)
|
|
group.byte 0x0F++0x00
|
|
line.byte 0x00 "WTDR,Date Register"
|
|
bitfld.byte 0x00 4.--5. " TD ,Second digit of the date" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the date" "0,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
elif ((d.b(ad:0x4003B000+0x11)&0x1f)==0x02)&&((d.b(ad:0x4003B000+0x0F)&0x3f)!=0x00)
|
|
group.byte 0x0F++0x00
|
|
line.byte 0x00 "WTDR,Date Register"
|
|
bitfld.byte 0x00 4.--5. " TD ,Second digit of the date" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the date" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif ((d.b(ad:0x4003B000+0x11)&0x1f)==0x02)&&((d.b(ad:0x4003B000+0x0F)&0x3f)==0x00)
|
|
group.byte 0x0F++0x00
|
|
line.byte 0x00 "WTDR,Date Register"
|
|
bitfld.byte 0x00 4.--5. " TD ,Second digit of the date" "-,1,2,-"
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the date" "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
else
|
|
group.byte 0x0F++0x00
|
|
line.byte 0x00 "WTDR,Date Register"
|
|
bitfld.byte 0x00 4.--5. " TD ,Second digit of the date" "-,-,-,-"
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the date" "-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
endif
|
|
if ((d.b(ad:0x4003B000+0x0E)&0x30)==(0x00||0x10))
|
|
group.byte 0x0E++0x00
|
|
line.byte 0x00 "WTHR,Hour register"
|
|
bitfld.byte 0x00 4.--5. " TH ,Second digit of the hour" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the hour" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif ((d.b(ad:0x4003B000+0x0E)&0x30)==0x20)
|
|
group.byte 0x0E++0x00
|
|
line.byte 0x00 "WTHR,Hour register"
|
|
bitfld.byte 0x00 4.--5. " TH ,Second digit of the hour" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the hour" "0,1,2,3,-,-,-,-,-,-,-,-,-,?..."
|
|
else
|
|
group.byte 0x0E++0x00
|
|
line.byte 0x00 "WTHR,Hour register"
|
|
bitfld.byte 0x00 4.--5. " TH ,Second digit of the hour" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the hour" "-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
endif
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "WTMIR,Minute Register"
|
|
bitfld.byte 0x00 4.--6. " TMI ,Second digit of the minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the minute" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "WTSR,Second Register"
|
|
bitfld.byte 0x00 4.--6. " TS ,Second digit of the second" "0,1,2,3,4,5,-,-"
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the second" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
group.byte 0x012++0x00
|
|
line.byte 0x00 "WTYR,Year Register"
|
|
bitfld.byte 0x00 4.--7. " TY ,Second digit of the year" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the year" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
if ((d.b(ad:0x4003B000+0x11)&0x10)==0x10)
|
|
group.byte 0x011++0x00
|
|
line.byte 0x00 "WTMOR,Month Register"
|
|
bitfld.byte 0x00 4. " TMO ,Second digit of the month" "0,1"
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the month" "0,1,2,-,-,-,-,-,-,-,?..."
|
|
elif ((d.b(ad:0x4003B000+0x11)&0x0f)==0x00)
|
|
group.byte 0x011++0x00
|
|
line.byte 0x00 "WTMOR,Month Register"
|
|
bitfld.byte 0x00 4. " TMO ,Second digit of the month" "-,1"
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the month" "-,1,2,3,4,5,6,7,8,9,?..."
|
|
else
|
|
group.byte 0x011++0x00
|
|
line.byte 0x00 "WTMOR,Month Register"
|
|
bitfld.byte 0x00 4. " TMO ,Second digit of the month" "0,1"
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the month" "-,1,2,3,4,5,6,7,8,9,?..."
|
|
endif
|
|
group.byte 0x010++0x00
|
|
line.byte 0x00 "WTDW,Day of the Week Register"
|
|
bitfld.byte 0x00 0.--2. " DW ,Day of the week" "Sunday,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,"
|
|
if ((d.b(ad:0x4003B000+0x19)&0x1f)==(0x01||0x03||0x05||0x07||0x08||0x10||0x12))&&((d.b(ad:0x4003B000+0x17)&0x30)!=0x30)&&((d.b(ad:0x4003B000+0x17)&0x3f)!=0x00)
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "ALDR,Alarm Date Register"
|
|
bitfld.byte 0x00 4.--5. " TAD ,Second digit of the alarm-set date" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the alarm-set date" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif ((d.b(ad:0x4003B000+0x19)&0x1f)==(0x01||0x03||0x05||0x07||0x08||0x10||0x12))&&((d.b(ad:0x4003B000+0x17)&0x3f)==0x00)
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "ALDR,Alarm Date Register"
|
|
bitfld.byte 0x00 4.--5. " TAD ,Second digit of the alarm-set date" "-,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the alarm-set date" "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif ((d.b(ad:0x4003B000+0x19)&0x1f)==(0x01||0x03||0x05||0x07||0x08||0x10||0x12))&&((d.b(ad:0x4003B000+0x17)&0x30)==0x30)
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "ALDR,Alarm Date Register"
|
|
bitfld.byte 0x00 4.--5. " TAD ,Second digit of the alarm-set date" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the alarm-set date" "0,1,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
elif ((d.b(ad:0x4003B000+0x19)&0x1f)==(0x04||0x06||0x09||0x11))&&((d.b(ad:0x4003B000+0x17)&0x30)!=0x30)&&((d.b(ad:0x4003B000+0x17)&0x3f)!=0x00)
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "ALDR,Alarm Date Register"
|
|
bitfld.byte 0x00 4.--5. " TAD ,Second digit of the alarm-set date" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the alarm-set date" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif ((d.b(ad:0x4003B000+0x19)&0x1f)==(0x04||0x06||0x09||0x11))&&((d.b(ad:0x4003B000+0x17)&0x3f)==0x00)
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "ALDR,Alarm Date Register"
|
|
bitfld.byte 0x00 4.--5. " TAD ,Second digit of the alarm-set date" "-,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the alarm-set date" "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif ((d.b(ad:0x4003B000+0x19)&0x1f)==(0x04||0x06||0x09||0x11))&&((d.b(ad:0x4003B000+0x17)&0x30)==0x30)
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "ALDR,Alarm Date Register"
|
|
bitfld.byte 0x00 4.--5. " TAD ,Second digit of the alarm-set date" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the alarm-set date" "0,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
elif ((d.b(ad:0x4003B000+0x19)&0x1f)==0x02)&&((d.b(ad:0x4003B000+0x17)&0x3f)!=0x00)
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "ALDR,Alarm Date Register"
|
|
bitfld.byte 0x00 4.--5. " TAD ,Second digit of the alarm-set date" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the alarm-set date" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif ((d.b(ad:0x4003B000+0x19)&0x1f)==0x02)&&((d.b(ad:0x4003B000+0x17)&0x3f)==0x00)
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "ALDR,Alarm Date Register"
|
|
bitfld.byte 0x00 4.--5. " TAD ,Second digit of the alarm-set date" "-,1,2,-"
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the alarm-set date" "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
else
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "ALDR,Alarm Date Register"
|
|
bitfld.byte 0x00 4.--5. " TAD ,Second digit of the alarm-set date" "D,-,-,-"
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the alarm-set date" "-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
endif
|
|
if ((d.b(ad:0x4003B000+0x16)&0x30)==(0x00||0x10))
|
|
group.byte 0x16++0x00
|
|
line.byte 0x00 "ALHR,Alarm Hour Register"
|
|
bitfld.byte 0x00 4.--5. " TAH ,Second digit of the alarm-set hour" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the alarm-set hour" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif ((d.b(ad:0x4003B000+0x16)&0x30)==0x20)
|
|
group.byte 0x16++0x00
|
|
line.byte 0x00 "ALHR,Alarm Hour Register"
|
|
bitfld.byte 0x00 4.--5. " TAH ,Second digit of the alarm-set hour" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the alarm-set hour" "0,1,2,3,-,-,-,-,-,-,-,-,-,?..."
|
|
else
|
|
group.byte 0x16++0x00
|
|
line.byte 0x00 "ALHR,Alarm Hour Register"
|
|
bitfld.byte 0x00 4.--5. " TAH ,Second digit of the alarm-set hour" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the alarm-set hour" "-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
endif
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "ALMIR,Alarm Minute Register"
|
|
bitfld.byte 0x00 4.--6. " TAMI ,Second digit of the alarm-set minute" "0,1,2,3,4,5,?..."
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the alarm-set minute" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
group.byte 0x01A++0x00
|
|
line.byte 0x00 "ALYR,Alarm Years Register"
|
|
bitfld.byte 0x00 4.--7. " TAY ,Second digit of the alarm-set year" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the alarm-set year" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
if ((d.b(ad:0x4003B000+0x19)&0x10)==0x10)
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "ALMOR,Alarm Month Register"
|
|
bitfld.byte 0x00 4. " TAMO ,Second digit of the alarm-set month" "0,1"
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the alarm-set month" "0,1,2,-,-,-,-,-,-,-,?..."
|
|
elif ((d.b(ad:0x4003B000+0x19)&0x0f)==0x00)
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "ALMOR,Alarm Month Register"
|
|
bitfld.byte 0x00 4. " TAMO ,Second digit of the alarm-set month" "-,1"
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the alarm-set month" "-,1,2,3,4,5,6,7,8,9,?..."
|
|
else
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "ALMOR,Alarm Month Register"
|
|
bitfld.byte 0x00 4. " TAMO ,Second digit of the alarm-set month" "0,1"
|
|
bitfld.byte 0x00 0.--3. " ,First digit of the alarm-set month" "-,1,2,3,4,5,6,7,8,9,?..."
|
|
endif
|
|
textline " "
|
|
group.long 0x01C++0x003
|
|
line.long 0x00 "WTTR,Timer Setting Register"
|
|
hexmask.long.tbyte 0x00 0.--17. " TM ,Timer setting information bits"
|
|
width 0xB
|
|
tree.end
|
|
tree "RTC Clock Control Block"
|
|
base ad:0x4003B000
|
|
width 10.
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "WTCLKS,Clock Selection Register"
|
|
bitfld.byte 0x00 0. " WTCLKS ,Input clock selection bit" "Sub clock,Main clock"
|
|
rgroup.byte 0x21++0x00
|
|
line.byte 0x00 "WTCLKM,Selection Clock Status Register"
|
|
bitfld.byte 0x00 0.--1. " WTCLKM ,Clock selection status bits" "No operation,No operation,Sub clock,Main clock"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "WTCAL,Frequency Correction Value Setting Register"
|
|
hexmask.word 0x00 0.--9. 1. " WTCAL ,Frequency correction value setting bits"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "WTCALEN,Frequency Correction Enable Register"
|
|
bitfld.byte 0x00 0. " WTCALEN ,Frequency correction enable bit" "Disabled,Enabled"
|
|
group.byte 0x28++0x01
|
|
line.byte 0x00 "WTDIV,Divider Ratio Setting Register"
|
|
bitfld.byte 0x00 0.--3. " WTDIV ,Divider ratio setting bits" "Not divided,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
line.byte 0x01 "WTDIVEN,Divider Output Enable Register"
|
|
rbitfld.byte 0x01 1. " WTDIVRDY ,Divider status bit" "Not in operation,In operation"
|
|
bitfld.byte 0x01 0. " WTDIVEN ,Divider enable bit" "Disabled,Enabled"
|
|
group.byte 0x2C++0x00
|
|
line.byte 0x00 "WTCALPRD,Frequency Correction Cycle Setting Register"
|
|
bitfld.byte 0x00 0.--5. " WTCALPRD ,Frequency correction value setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x30++0x00
|
|
line.byte 0x00 "WTCOSEL,RTCCO Output Selection Register"
|
|
bitfld.byte 0x00 0. " WTCOSEL ,RTCCO output selection bit" "CO,2 divisions of CO"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("S6E1C*")
|
|
tree "Base Timer I/O Select Function"
|
|
base ad:0x40025100
|
|
width 13.
|
|
group.byte 0x00++0x00
|
|
sif (cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
line.byte 0x00 "BTSEL0123,I/O Selection Register"
|
|
bitfld.byte 0x00 4.--7. " BTSEL23 ,I/O mode selection bits" "Standard 16-bit timer,Timer full mode,Shared external trigger,Shared channel signal trigger,Timer start/stop,Software-based simultaneous startup mode,Software-based startup and timer start/stop,Timer start,Shared channel signal trigger and timer start stop,Shared channel signal trigger and timer start/stop,Event counter,?..."
|
|
bitfld.byte 0x00 0.--3. " BTSEL01 ,I/O mode selection bits" "Standard 16-bit timer,Timer full mode,Shared external trigger,Shared channel signal trigger,Timer start/stop,Software-based simultaneous startup mode,Software-based startup and timer start/stop,Timer start,Shared channel signal trigger and timer start stop,Shared channel signal trigger and timer start/stop,Event counter,?..."
|
|
else
|
|
line.byte 0x00 "BTSEL0123,I/O Selection Register"
|
|
bitfld.byte 0x00 0.--3. " BTSEL01 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Timer start/stop and simultaneous soft start,Timer start,?..."
|
|
endif
|
|
sif (cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
else
|
|
endif
|
|
width 0x0B
|
|
base ad:0x40025300
|
|
width 13.
|
|
group.byte 0x00++0x00
|
|
sif (cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
line.byte 0x00 "BTSEL4567,I/O Selection Register"
|
|
bitfld.byte 0x00 4.--7. " BTSEL67 ,I/O mode selection bits" "Standard 16-bit timer,Timer full mode,Shared external trigger,Shared channel signal trigger,Timer start/stop,Software-based simultaneous startup mode,Software-based startup and timer start/stop,Timer start,Shared channel signal trigger and timer start stop,Shared channel signal trigger and timer start/stop,Event counter,?..."
|
|
bitfld.byte 0x00 0.--3. " BTSEL45 ,I/O mode selection bits" "Standard 16-bit timer,Timer full mode,Shared external trigger,Shared channel signal trigger,Timer start/stop,Software-based simultaneous startup mode,Software-based startup and timer start/stop,Timer start,Shared channel signal trigger and timer start stop,Shared channel signal trigger and timer start/stop,Event counter,?..."
|
|
else
|
|
line.byte 0x00 "BTSEL4567,I/O Selection Register"
|
|
bitfld.byte 0x00 0.--3. " BTSEL01 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Timer start/stop and simultaneous soft start,Timer start,?..."
|
|
endif
|
|
sif (cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
else
|
|
endif
|
|
width 0x0B
|
|
base ad:0x40025500
|
|
width 13.
|
|
group.byte 0x00++0x00
|
|
sif (cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
line.byte 0x00 "BTSEL89AB,I/O Selection Register"
|
|
bitfld.byte 0x00 4.--7. " BTSELAB ,I/O mode selection bits" "Standard 16-bit timer,Timer full mode,Shared external trigger,Shared channel signal trigger,Timer start/stop,Software-based simultaneous startup mode,Software-based startup and timer start/stop,Timer start,Shared channel signal trigger and timer start stop,Shared channel signal trigger and timer start/stop,Event counter,?..."
|
|
bitfld.byte 0x00 0.--3. " BTSEL89 ,I/O mode selection bits" "Standard 16-bit timer,Timer full mode,Shared external trigger,Shared channel signal trigger,Timer start/stop,Software-based simultaneous startup mode,Software-based startup and timer start/stop,Timer start,Shared channel signal trigger and timer start stop,Shared channel signal trigger and timer start/stop,Event counter,?..."
|
|
else
|
|
line.byte 0x00 "BTSEL89AB,I/O Selection Register"
|
|
bitfld.byte 0x00 0.--3. " BTSEL01 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Timer start/stop and simultaneous soft start,Timer start,?..."
|
|
endif
|
|
sif (cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
else
|
|
endif
|
|
width 0x0B
|
|
base ad:0x40025700
|
|
width 13.
|
|
group.byte 0x00++0x00
|
|
sif (cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
line.byte 0x00 "BTSELCDEF,I/O Selection Register"
|
|
bitfld.byte 0x00 4.--7. " BTSELEF ,I/O mode selection bits" "Standard 16-bit timer,Timer full mode,Shared external trigger,Shared channel signal trigger,Timer start/stop,Software-based simultaneous startup mode,Software-based startup and timer start/stop,Timer start,Shared channel signal trigger and timer start stop,Shared channel signal trigger and timer start/stop,Event counter,?..."
|
|
bitfld.byte 0x00 0.--3. " BTSELCD ,I/O mode selection bits" "Standard 16-bit timer,Timer full mode,Shared external trigger,Shared channel signal trigger,Timer start/stop,Software-based simultaneous startup mode,Software-based startup and timer start/stop,Timer start,Shared channel signal trigger and timer start stop,Shared channel signal trigger and timer start/stop,Event counter,?..."
|
|
else
|
|
line.byte 0x00 "BTSELCDEF,I/O Selection Register"
|
|
bitfld.byte 0x00 0.--3. " BTSEL01 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Timer start/stop and simultaneous soft start,Timer start,?..."
|
|
endif
|
|
sif (cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
textline " "
|
|
group.word 0x800++0x01
|
|
line.word 0x00 "BTSSSR,Simultaneous Soft Start Register"
|
|
bitfld.word 0x00 15. " SSSR15 ,Simultaneous soft start channel 15" "No effect,Started"
|
|
bitfld.word 0x00 14. " SSSR14 ,Simultaneous soft start channel 14" "No effect,Started"
|
|
bitfld.word 0x00 13. " SSSR13 ,Simultaneous soft start channel 13" "No effect,Started"
|
|
bitfld.word 0x00 12. " SSSR12 ,Simultaneous soft start channel 12" "No effect,Started"
|
|
textline " "
|
|
bitfld.word 0x00 11. " SSSR11 ,Simultaneous soft start channel 11" "No effect,Started"
|
|
bitfld.word 0x00 10. " SSSR10 ,Simultaneous soft start channel 10" "No effect,Started"
|
|
bitfld.word 0x00 9. " SSSR9 ,Simultaneous soft start channel 9" "No effect,Started"
|
|
bitfld.word 0x00 8. " SSSR8 ,Simultaneous soft start channel 8" "No effect,Started"
|
|
textline " "
|
|
bitfld.word 0x00 7. " SSSR7 ,Simultaneous soft start channel 7" "No effect,Started"
|
|
bitfld.word 0x00 6. " SSSR6 ,Simultaneous soft start channel 6" "No effect,Started"
|
|
bitfld.word 0x00 5. " SSSR5 ,Simultaneous soft start channel 5" "No effect,Started"
|
|
bitfld.word 0x00 4. " SSSR4 ,Simultaneous soft start channel 4" "No effect,Started"
|
|
textline " "
|
|
bitfld.word 0x00 3. " SSSR3 ,Simultaneous soft start channel 3" "No effect,Started"
|
|
bitfld.word 0x00 2. " SSSR2 ,Simultaneous soft start channel 2" "No effect,Started"
|
|
bitfld.word 0x00 1. " SSSR1 ,Simultaneous soft start channel 1" "No effect,Started"
|
|
bitfld.word 0x00 0. " SSSR0 ,Simultaneous soft start channel 0" "No effect,Started"
|
|
else
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "Base Timer I/O Select Function"
|
|
base ad:0x40025100
|
|
width 11.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "BTSEL0123,I/O Select Register"
|
|
bitfld.word 0x00 12.--15. " SEL23 ,I/O select bits for Ch.2/Ch.3" "Mode 0,Mode 1,Mode 2,Mode 3,Mode 4,Mode 5,Mode 6,Mode 7,Mode 8,?..."
|
|
bitfld.word 0x00 8.--11. " SEL01 ,I/O select bits for Ch.0/Ch.1" "Mode 0,Mode 1,Mode 2,Mode 3,Mode 4,Mode 5,Mode 6,Mode 7,Mode 8,?..."
|
|
base ad:0x40025F00
|
|
wgroup.word 0xEFC++0x01
|
|
line.word 0x00 "BTSSSR,Software-based Simultaneous Startup Register"
|
|
bitfld.word 0x00 3. " SSSR3 ,Software-based simultaneous startup bit [3]" ",Started Ch.3"
|
|
bitfld.word 0x00 2. " SSSR2 ,Software-based simultaneous startup bit [2]" ",Started Ch.2"
|
|
bitfld.word 0x00 1. " SSSR1 ,Software-based simultaneous startup bit [1]" ",Started Ch.1"
|
|
bitfld.word 0x00 0. " SSSR0 ,Software-based simultaneous startup bit [0]" ",Started Ch.0"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
sif cpuis("S6E1C*")
|
|
tree.open "Base Timer"
|
|
tree "Channel 1"
|
|
base ad:0x40025000
|
|
width 7.
|
|
if (((per.w(ad:0x40025000+0x0C))&0x70)==0x10)
|
|
if (((per.w(ad:0x40025000+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0x40025000+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
else
|
|
if (((per.w(ad:0x40025000+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 5. " DTIEC ,Duty match interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 5. " DTIES ,Duty match interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,PWM Cycle Setting Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PDUT,PWM Duty Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0x40025000+0x0C))&0x70)==0x20)
|
|
if (((per.w(ad:0x40025000+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0x40025000+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0x40025000+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PRLL,L Width Setting Reload Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PRLH,H Width Setting Reload Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0x40025000+0x0C))&0x70)==0x30)
|
|
if (((per.w(ad:0x40025000+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0x40025000+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0x40025000+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,Cycle Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0x40025000+0x0C))&0x70)==0x40)
|
|
if (((per.w(ad:0x40025000+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0x40025000+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0x40025000+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 6. " EDIE ,Measurement end interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " EDIEC ,Measurement end interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " OVIEC ,Overflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " EDIES ,Measurement end interrupt enable set" ",Set"
|
|
bitfld.byte 0x00 4. " OVIES ,Overflow interrupt request enable set" ",Set"
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "DTBF,Data Buffer Register"
|
|
in
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
textline ""
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 2"
|
|
base ad:0x40025040
|
|
width 7.
|
|
if (((per.w(ad:0x40025040+0x0C))&0x70)==0x10)
|
|
if (((per.w(ad:0x40025040+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0x40025040+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
else
|
|
if (((per.w(ad:0x40025040+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 5. " DTIEC ,Duty match interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 5. " DTIES ,Duty match interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,PWM Cycle Setting Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PDUT,PWM Duty Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0x40025040+0x0C))&0x70)==0x20)
|
|
if (((per.w(ad:0x40025040+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0x40025040+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0x40025040+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PRLL,L Width Setting Reload Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PRLH,H Width Setting Reload Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0x40025040+0x0C))&0x70)==0x30)
|
|
if (((per.w(ad:0x40025040+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0x40025040+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0x40025040+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,Cycle Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0x40025040+0x0C))&0x70)==0x40)
|
|
if (((per.w(ad:0x40025040+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0x40025040+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0x40025040+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 6. " EDIE ,Measurement end interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " EDIEC ,Measurement end interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " OVIEC ,Overflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " EDIES ,Measurement end interrupt enable set" ",Set"
|
|
bitfld.byte 0x00 4. " OVIES ,Overflow interrupt request enable set" ",Set"
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "DTBF,Data Buffer Register"
|
|
in
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
textline ""
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 2"
|
|
base ad:0x40025080
|
|
width 7.
|
|
if (((per.w(ad:0x40025080+0x0C))&0x70)==0x10)
|
|
if (((per.w(ad:0x40025080+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0x40025080+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
else
|
|
if (((per.w(ad:0x40025080+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 5. " DTIEC ,Duty match interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 5. " DTIES ,Duty match interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,PWM Cycle Setting Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PDUT,PWM Duty Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0x40025080+0x0C))&0x70)==0x20)
|
|
if (((per.w(ad:0x40025080+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0x40025080+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0x40025080+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PRLL,L Width Setting Reload Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PRLH,H Width Setting Reload Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0x40025080+0x0C))&0x70)==0x30)
|
|
if (((per.w(ad:0x40025080+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0x40025080+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0x40025080+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,Cycle Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0x40025080+0x0C))&0x70)==0x40)
|
|
if (((per.w(ad:0x40025080+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0x40025080+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0x40025080+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 6. " EDIE ,Measurement end interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " EDIEC ,Measurement end interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " OVIEC ,Overflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " EDIES ,Measurement end interrupt enable set" ",Set"
|
|
bitfld.byte 0x00 4. " OVIES ,Overflow interrupt request enable set" ",Set"
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "DTBF,Data Buffer Register"
|
|
in
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
textline ""
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 3"
|
|
base ad:0x400250C0
|
|
width 7.
|
|
if (((per.w(ad:0x400250C0+0x0C))&0x70)==0x10)
|
|
if (((per.w(ad:0x400250C0+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0x400250C0+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
else
|
|
if (((per.w(ad:0x400250C0+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 5. " DTIEC ,Duty match interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 5. " DTIES ,Duty match interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,PWM Cycle Setting Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PDUT,PWM Duty Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0x400250C0+0x0C))&0x70)==0x20)
|
|
if (((per.w(ad:0x400250C0+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0x400250C0+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0x400250C0+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PRLL,L Width Setting Reload Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PRLH,H Width Setting Reload Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0x400250C0+0x0C))&0x70)==0x30)
|
|
if (((per.w(ad:0x400250C0+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0x400250C0+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0x400250C0+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,Cycle Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0x400250C0+0x0C))&0x70)==0x40)
|
|
if (((per.w(ad:0x400250C0+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0x400250C0+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0x400250C0+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 6. " EDIE ,Measurement end interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " EDIEC ,Measurement end interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " OVIEC ,Overflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " EDIES ,Measurement end interrupt enable set" ",Set"
|
|
bitfld.byte 0x00 4. " OVIES ,Overflow interrupt request enable set" ",Set"
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "DTBF,Data Buffer Register"
|
|
in
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
textline ""
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 4"
|
|
base ad:0x40025200
|
|
width 7.
|
|
if (((per.w(ad:0x40025200+0x0C))&0x70)==0x10)
|
|
if (((per.w(ad:0x40025200+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0x40025200+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
else
|
|
if (((per.w(ad:0x40025200+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 5. " DTIEC ,Duty match interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 5. " DTIES ,Duty match interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,PWM Cycle Setting Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PDUT,PWM Duty Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0x40025200+0x0C))&0x70)==0x20)
|
|
if (((per.w(ad:0x40025200+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0x40025200+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0x40025200+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PRLL,L Width Setting Reload Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PRLH,H Width Setting Reload Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0x40025200+0x0C))&0x70)==0x30)
|
|
if (((per.w(ad:0x40025200+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0x40025200+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0x40025200+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,Cycle Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0x40025200+0x0C))&0x70)==0x40)
|
|
if (((per.w(ad:0x40025200+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0x40025200+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0x40025200+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 6. " EDIE ,Measurement end interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " EDIEC ,Measurement end interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " OVIEC ,Overflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " EDIES ,Measurement end interrupt enable set" ",Set"
|
|
bitfld.byte 0x00 4. " OVIES ,Overflow interrupt request enable set" ",Set"
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "DTBF,Data Buffer Register"
|
|
in
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
textline ""
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 5"
|
|
base ad:0x40025240
|
|
width 7.
|
|
if (((per.w(ad:0x40025240+0x0C))&0x70)==0x10)
|
|
if (((per.w(ad:0x40025240+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0x40025240+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
else
|
|
if (((per.w(ad:0x40025240+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 5. " DTIEC ,Duty match interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 5. " DTIES ,Duty match interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,PWM Cycle Setting Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PDUT,PWM Duty Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0x40025240+0x0C))&0x70)==0x20)
|
|
if (((per.w(ad:0x40025240+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0x40025240+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0x40025240+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PRLL,L Width Setting Reload Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PRLH,H Width Setting Reload Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0x40025240+0x0C))&0x70)==0x30)
|
|
if (((per.w(ad:0x40025240+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0x40025240+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0x40025240+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,Cycle Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0x40025240+0x0C))&0x70)==0x40)
|
|
if (((per.w(ad:0x40025240+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0x40025240+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0x40025240+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 6. " EDIE ,Measurement end interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " EDIEC ,Measurement end interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " OVIEC ,Overflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " EDIES ,Measurement end interrupt enable set" ",Set"
|
|
bitfld.byte 0x00 4. " OVIES ,Overflow interrupt request enable set" ",Set"
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "DTBF,Data Buffer Register"
|
|
in
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
textline ""
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 6"
|
|
base ad:0x40025280
|
|
width 7.
|
|
if (((per.w(ad:0x40025280+0x0C))&0x70)==0x10)
|
|
if (((per.w(ad:0x40025280+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0x40025280+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
else
|
|
if (((per.w(ad:0x40025280+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 5. " DTIEC ,Duty match interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 5. " DTIES ,Duty match interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,PWM Cycle Setting Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PDUT,PWM Duty Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0x40025280+0x0C))&0x70)==0x20)
|
|
if (((per.w(ad:0x40025280+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0x40025280+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0x40025280+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PRLL,L Width Setting Reload Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PRLH,H Width Setting Reload Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0x40025280+0x0C))&0x70)==0x30)
|
|
if (((per.w(ad:0x40025280+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0x40025280+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0x40025280+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,Cycle Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0x40025280+0x0C))&0x70)==0x40)
|
|
if (((per.w(ad:0x40025280+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0x40025280+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0x40025280+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 6. " EDIE ,Measurement end interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " EDIEC ,Measurement end interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " OVIEC ,Overflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " EDIES ,Measurement end interrupt enable set" ",Set"
|
|
bitfld.byte 0x00 4. " OVIES ,Overflow interrupt request enable set" ",Set"
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "DTBF,Data Buffer Register"
|
|
in
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
textline ""
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 7"
|
|
base ad:0x400252C0
|
|
width 7.
|
|
if (((per.w(ad:0x400252C0+0x0C))&0x70)==0x10)
|
|
if (((per.w(ad:0x400252C0+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0x400252C0+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
else
|
|
if (((per.w(ad:0x400252C0+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 5. " DTIEC ,Duty match interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 5. " DTIES ,Duty match interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,PWM Cycle Setting Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PDUT,PWM Duty Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0x400252C0+0x0C))&0x70)==0x20)
|
|
if (((per.w(ad:0x400252C0+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0x400252C0+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0x400252C0+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIES ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIES ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PRLL,L Width Setting Reload Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "PRLH,H Width Setting Reload Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0x400252C0+0x0C))&0x70)==0x30)
|
|
if (((per.w(ad:0x400252C0+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0x400252C0+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
rbitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0x400252C0+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,Rising,Falling,Both"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification" "Normal,Inverse"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Reload,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "No effect,Trigger"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
wgroup.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " TGIEC ,Trigger interrupt request enable set" ",Set"
|
|
bitfld.byte 0x00 4. " UDIEC ,Underflow interrupt request enable set" ",Set"
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PCSR,Cycle Setting Register"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "TMR,Timer Register"
|
|
in
|
|
elif (((per.w(ad:0x400252C0+0x0C))&0x70)==0x40)
|
|
if (((per.w(ad:0x400252C0+0x0C))&0x02)==0x02)
|
|
if (((per.w(ad:0x400252C0+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
rbitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
rbitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
rbitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
rbitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
else
|
|
if (((per.w(ad:0x400252C0+0x11))&0x01)==0x01)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/512,/1024,/2048,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS ,Count clock selection" "/1,/4,/16,/128,/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection" "H pulse width measurement,Cycle measurement between rising edges,Cycle measurement between falling edges,Pulse width measurement between all edges,L pulse width measurement,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,Single"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit 3" "0,1"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 6. " EDIE ,Measurement end interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt"
|
|
bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "No interrupt,Interrupt"
|
|
sif !(cpuis("S6E1C11B")||cpuis("S6E1C11D")||cpuis("S6E1C12B")||cpuis("S6E1C11C")||cpuis("S6E1C12C")||cpuis("S6E1C12D")||cpuis("S6E1C31B")||cpuis("S6E1C31C")||cpuis("S6E1C31D")||cpuis("S6E1C32B")||cpuis("S6E1C32C")||cpuis("S6E1C32D"))
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 6. " EDIEC ,Measurement end interrupt request enable clear" ",Clear"
|
|
bitfld.byte 0x00 4. " OVIEC ,Overflow interrupt request enable clear" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "STCS,Status Control Set Register"
|
|
bitfld.byte 0x00 6. " EDIES ,Measurement end interrupt enable set" ",Set"
|
|
bitfld.byte 0x00 4. " OVIES ,Overflow interrupt request enable set" ",Set"
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "DTBF,Data Buffer Register"
|
|
in
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TMCR,Timer Control Register"
|
|
textline ""
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif !cpuis("S6E1C*")
|
|
tree.open "MFT (Multifunction Timer)"
|
|
tree "FRT (Free-run Timer)"
|
|
base ad:0x40020000
|
|
width 6.
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "TCAL,FRT Simultaneous Start Control Register"
|
|
bitfld.long 0x00 18. " SCLR02 ,Mirror of the SCLR register in MFT0 CH2" "No effect,FRT cleared"
|
|
bitfld.long 0x00 17. " SCLR01 ,Mirror of the SCLR register in MFT0 CH1" "No effect,FRT cleared"
|
|
bitfld.long 0x00 16. " SCLR00 ,Mirror of the SCLR register in MFT0 CH0" "No effect,FRT cleared"
|
|
bitfld.long 0x00 2. " STOP02 ,Mirror of the STOP register in MFT0 CH2" "Running,Stopped"
|
|
bitfld.long 0x00 1. " STOP01 ,Mirror of the STOP register in MFT0 CH1" "Running,Stopped"
|
|
bitfld.long 0x00 0. " STOP00 ,Mirror of the STOP register in MFT0 CH0" "Running,Stopped"
|
|
width 0xB
|
|
tree "Channel 0"
|
|
base ad:0x40020000
|
|
width 7.
|
|
group.word 0x148++0x01
|
|
line.word 0x00 "TCSA0,FRT-ch.0 Control Register A"
|
|
bitfld.word 0x00 15. " ECKE ,Count clock select" "PCLK,FRCK"
|
|
bitfld.word 0x00 14. " IRQZF ,Zero value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/Interrupt"
|
|
bitfld.word 0x00 13. " IRQZE ,Enable IRQZF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " ICLR ,TCCP value detection on FRT interrupt (Write/Read)" "Clear/No interrupt,No effect/Interrupt"
|
|
bitfld.word 0x00 8. " ICRE ,Enable ICLR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " BFE ,Enable TCCP buffer" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " STOP ,Start and stop control of the FRT's operation" "Running,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MODE ,FRT's count mode select" "Up-count,Up/Down-count"
|
|
bitfld.word 0x00 4. " SCLR ,FRT operation state initialization request" "Not requested,Requested"
|
|
bitfld.word 0x00 0.--3. " CLK ,Count clock cycle of FRT" "PCLK,PCLK*2,PCLK*4,PCLK*8,PCLK*16,PCLK*32,PCLK*64,PCLK*128,PCLK*256,PCLK*512,PCLK*1024,?..."
|
|
group.word 0x14A++0x01
|
|
line.word 0x00 "TCSC0,FRT-ch.0 Control Register C"
|
|
rbitfld.word 0x00 12.--15. " MSPC ,Value of a Peak value detection mask counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.word 0x00 8.--11. " MSZC ,Value from a Zero value detection mask counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 4.--7. " MSPI ,Number of masked Peak value detections" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " MSZI ,Sets the number of masked Zero value detections" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x142++0x01
|
|
line.word 0x00 "TCCP0,FRT-ch.0 Cycle Setting Register"
|
|
group.word 0x146++0x01
|
|
line.word 0x00 "TCDT0,FRT-ch.0 Count Value Register"
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0x4002000C
|
|
width 7.
|
|
group.word 0x148++0x01
|
|
line.word 0x00 "TCSA1,FRT-ch.1 Control Register A"
|
|
bitfld.word 0x00 15. " ECKE ,Count clock select" "PCLK,FRCK"
|
|
bitfld.word 0x00 14. " IRQZF ,Zero value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/Interrupt"
|
|
bitfld.word 0x00 13. " IRQZE ,Enable IRQZF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " ICLR ,TCCP value detection on FRT interrupt (Write/Read)" "Clear/No interrupt,No effect/Interrupt"
|
|
bitfld.word 0x00 8. " ICRE ,Enable ICLR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " BFE ,Enable TCCP buffer" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " STOP ,Start and stop control of the FRT's operation" "Running,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MODE ,FRT's count mode select" "Up-count,Up/Down-count"
|
|
bitfld.word 0x00 4. " SCLR ,FRT operation state initialization request" "Not requested,Requested"
|
|
bitfld.word 0x00 0.--3. " CLK ,Count clock cycle of FRT" "PCLK,PCLK*2,PCLK*4,PCLK*8,PCLK*16,PCLK*32,PCLK*64,PCLK*128,PCLK*256,PCLK*512,PCLK*1024,?..."
|
|
group.word 0x14A++0x01
|
|
line.word 0x00 "TCSC1,FRT-ch.1 Control Register C"
|
|
rbitfld.word 0x00 12.--15. " MSPC ,Value of a Peak value detection mask counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.word 0x00 8.--11. " MSZC ,Value from a Zero value detection mask counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 4.--7. " MSPI ,Number of masked Peak value detections" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " MSZI ,Sets the number of masked Zero value detections" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x142++0x01
|
|
line.word 0x00 "TCCP1,FRT-ch.1 Cycle Setting Register"
|
|
group.word 0x146++0x01
|
|
line.word 0x00 "TCDT1,FRT-ch.1 Count Value Register"
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 2"
|
|
base ad:0x40020018
|
|
width 7.
|
|
group.word 0x148++0x01
|
|
line.word 0x00 "TCSA2,FRT-ch.2 Control Register A"
|
|
bitfld.word 0x00 15. " ECKE ,Count clock select" "PCLK,FRCK"
|
|
bitfld.word 0x00 14. " IRQZF ,Zero value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/Interrupt"
|
|
bitfld.word 0x00 13. " IRQZE ,Enable IRQZF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " ICLR ,TCCP value detection on FRT interrupt (Write/Read)" "Clear/No interrupt,No effect/Interrupt"
|
|
bitfld.word 0x00 8. " ICRE ,Enable ICLR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " BFE ,Enable TCCP buffer" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " STOP ,Start and stop control of the FRT's operation" "Running,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MODE ,FRT's count mode select" "Up-count,Up/Down-count"
|
|
bitfld.word 0x00 4. " SCLR ,FRT operation state initialization request" "Not requested,Requested"
|
|
bitfld.word 0x00 0.--3. " CLK ,Count clock cycle of FRT" "PCLK,PCLK*2,PCLK*4,PCLK*8,PCLK*16,PCLK*32,PCLK*64,PCLK*128,PCLK*256,PCLK*512,PCLK*1024,?..."
|
|
group.word 0x14A++0x01
|
|
line.word 0x00 "TCSC2,FRT-ch.2 Control Register C"
|
|
rbitfld.word 0x00 12.--15. " MSPC ,Value of a Peak value detection mask counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.word 0x00 8.--11. " MSZC ,Value from a Zero value detection mask counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 4.--7. " MSPI ,Number of masked Peak value detections" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " MSZI ,Sets the number of masked Zero value detections" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x142++0x01
|
|
line.word 0x00 "TCCP2,FRT-ch.2 Cycle Setting Register"
|
|
group.word 0x146++0x01
|
|
line.word 0x00 "TCDT2,FRT-ch.2 Count Value Register"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "OCU (Output Compare Unit)"
|
|
base ad:0x40020000
|
|
width 8.
|
|
tree "Channel 0 and 1"
|
|
group.byte 0x168++0x00
|
|
line.byte 0x00 "OCFS10,OCU Connecting FRT Select Register of Ch.0 and Ch.1"
|
|
bitfld.byte 0x00 4.--7. " FSO1 ,Selects FRT channel to be connected to OCU Ch.1" "Ch.0,Ch.1,Ch.2,?..."
|
|
bitfld.byte 0x00 0.--3. " FSO0 ,Selects FRT channel to be connected to OCU Ch.0" "Ch.0,Ch.1,Ch.2,?..."
|
|
group.byte 0x118++0x00
|
|
line.byte 0x00 "OCSA10,OCU Control Register A of Ch.0 and Ch.1"
|
|
bitfld.byte 0x00 7. " IOP1 ,Match detection between OCU Ch.1 and OCCP1 (Read/Write)" "Not detected/Cleared,Detected/No effect"
|
|
bitfld.byte 0x00 6. " IOP0 ,Match detection between OCU Ch.0 and OCCP0(Read/Write)" "Not detected/Cleared,Detected/No effect"
|
|
bitfld.byte 0x00 5. " IOE1 ,IOP1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " IOE0 ,IOP0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " CST1 ,Operation state of OCU Ch.1" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " CST0 ,Operation state of OCU Ch.0" "Disabled,Enabled"
|
|
group.byte 0x119++0x00
|
|
line.byte 0x00 "OCSB10,OCU Control Register B of Ch.0 and Ch.1"
|
|
bitfld.byte 0x00 7. " FM4 ,Operating Mode" "FM3-compatible,FM4"
|
|
bitfld.byte 0x00 4. " CMOD ,OCU's operating mode in FM3" "0,1"
|
|
bitfld.byte 0x00 1. " OTD1 ,State of RT1" "Low,High"
|
|
bitfld.byte 0x00 0. " OTD0 ,State of RT0" "Low,High"
|
|
group.byte 0x125++0x00
|
|
line.byte 0x00 "OCSC,OCU Control Register C"
|
|
bitfld.byte 0x00 5. " MOD5 ,Channel 5 mode" "0,1"
|
|
bitfld.byte 0x00 4. " MOD4 ,Channel 4 mode" "0,1"
|
|
bitfld.byte 0x00 3. " MOD3 ,Channel 3 mode" "0,1"
|
|
bitfld.byte 0x00 2. " MOD2 ,Channel 2 mode" "0,1"
|
|
bitfld.byte 0x00 1. " MOD1 ,Channel 1 mode" "0,1"
|
|
bitfld.byte 0x00 0. " MOD0 ,Channel 0 mode" "0,1"
|
|
group.byte 0x11A++0x00
|
|
line.byte 0x00 "OCSD10,OCU Control Register D of Ch.0 and Ch.1"
|
|
bitfld.byte 0x00 6.--7. " OCSE1BUFE ,OCSE1 buffer function enable/Timing of transfers" "Disabled,Enabled/FRT_CH1=0x00,Enabled/FRT_CH1=TCCP,Enabled/Both"
|
|
bitfld.byte 0x00 4.--5. " OCSE0BUFE ,OCSE0 buffer function enable/Timing of transfers" "Disabled,Enabled/FRT_CH0=0x00,Enabled/FRT_CH0=TCCP,Enabled/Both"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " OCCP1BUFE ,OCCP1 buffer function enable/Timing of transfers" "Disabled,Enabled/FRT_CH1=0x00,Enabled/FRT_CH1=TCCP,Enabled/Both"
|
|
bitfld.byte 0x00 0.--1. " OCCP0BUFE ,OCCP0 buffer function enable/Timing of transfers" "Disabled,Enabled/FRT_CH0=0x00,Enabled/FRT_CH0=TCCP,Enabled/Both"
|
|
if (d.b(ad:0x40020000+0x119)&0x80)==0x80
|
|
group.word 0x128++0x01
|
|
line.word 0x00 "OCSE0,OCU Control Register E of Ch.0"
|
|
bitfld.word 0x00 14.--15. " RSB1415 ,Condition 1.FRT=0x0000 and 2.FRT/=OCCP0, set RT0" "Hold,Set,Reset,Reverse"
|
|
bitfld.word 0x00 12.--13. " RSB1213 ,Condition 1.FRT=TCCP and 2.FRT/=OCCP0, set RT0" "Hold,Set,Reset,Reverse"
|
|
bitfld.word 0x00 10.--11. " RSB1011 ,Condition 1.FRT=0x0000 and 2.FRT=OCCP0, set RT0" "Hold,Set,Reset,Reverse"
|
|
bitfld.word 0x00 8.--9. " RSB0809 ,Condition 1.FRT=UP and 2.FRT=OCCP0, set RT0" "Hold,Set,Reset,Reverse"
|
|
bitfld.word 0x00 6.--7. " RSB0607 ,Condition 1.FRT=TCCP and 2.FRT=OCCP0, set RT0" "Hold,Set,Reset,Reverse"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " RSB0405 ,Condition 1.FRT=DOWN and 2.FRT=OCCP0, set RT0" "Hold,Set,Reset,Reverse"
|
|
bitfld.word 0x00 3. " RSB3 ,Condition 1.FRT=0x0000 and 2.FRT=OCCP0, set IOP0" "Hold,Set"
|
|
bitfld.word 0x00 2. " RSB2 ,Condition 1.FRT=UP and 2.FRT=OCCP0, set IOP0" "Hold,Set"
|
|
bitfld.word 0x00 1. " RSB1 ,Condition 1.FRT=TCCP and 2.FRT=OCCP0, set IOP0" "Hold,Set"
|
|
bitfld.word 0x00 0. " RSB0 ,Condition 1.FRT=DOWN and 2.FRT=OCCP0,set IOP0" "Hold,Set"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "OCSE1,OCU Control Register E of Ch.1"
|
|
bitfld.long 0x00 30.--31. " RSB3031 ,Condition 1.FRT=0x0000,2.FRT/=OCCP1 and 3.FRT=OCCP0, set RT1" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 28.--29. " RSB2627 ,Condition 1.FRT=TCCP,2.FRT/=OCCP1 and 3.FRT=OCCP0, set RT1" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 26.--27. " RSB2627 ,Condition 1.FRT=0x0000,2.FRT=OCCP1 and 3.FRT=OCCP0, set RT1" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 24.--25. " RSB2425 ,Condition 1.FRT=UP,2.FRT=OCCP1 and 3.FRT=OCCP0, set RT1" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 22.--23. " RSB2223 ,Condition 1.FRT=TCCP,2.FRT=OCCP1 and 3.FRT=OCCP0, set RT1" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 20.--21. " RSB2021 ,Condition 1.FRT=DOWN,2.FRT=OCCP1 and 3.FRT=OCCP0, set RT1" "Hold,Set,Reset,Reverse"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " RSB1819 ,Condition 1.FRT=UP,2.FRT/=OCCP1 and 3.FRT=OCCP0, set RT1" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 16.--17. " RSB1617 ,Condition 1.FRT=DOWN,2.FRT/=OCCP1 and 3.FRT=OCCP0, set RT1" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 14.--15. " RSB1415 ,Condition 1.FRT=0x0000,2.FRT/=OCCP1 and 3.FRT/=OCCP0, set RT1" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 12.--13. " RSB1213 ,Condition 1.FRT=TCCP,2.FRT/=OCCP1 and 3.FRT/=OCCP0, set RT1" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 10.--11. " RSB1011 ,Condition 1.FRT=0x0000,2.FRT=OCCP1 and 3.FRT/=OCCP0, set RT1" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 8.--9. " RSB0809 ,Condition 1.FRT=UP,2.FRT=OCCP1 and 3.FRT/=OCCP0, set RT1" "Hold,Set,Reset,Reverse"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " RSB0607 ,Condition 1.FRT=TCCP,2.FRT=OCCP1 and 3.FRT/=OCCP0, set RT1" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 4.--5. " RSB0405 ,Condition 1.FRT=DOWN,2.FRT=OCCP1 and 3.FRT/=OCCP0, set RT1" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 3. " RSB3 ,Condition 1.FRT=0x0000 and 2.FRT=OCCP1, set IOP1" "Hold,Set"
|
|
bitfld.long 0x00 2. " RSB2 ,Condition 1.FRT=UP and 2.FRT=OCCP1, set IOP1" "Hold,Set"
|
|
bitfld.long 0x00 1. " RSB1 ,Condition 1.FRT=TCCP and 2.FRT=OCCP1, set IOP1" "Hold,Set"
|
|
bitfld.long 0x00 0. " RSB0 ,Condition 1.FRT=DOWN and 2.FRT=OCCP1,set IOP1" "Hold,Set"
|
|
else
|
|
hgroup.word 0x128++0x01
|
|
hide.word 0x00 "OCSE0,OCU Control Register E of Ch.0"
|
|
hgroup.long 0x12C++0x03
|
|
hide.long 0x00 "OCSE1,OCU Control Register E of Ch.1"
|
|
endif
|
|
group.word 0x102++0x01
|
|
line.word 0x00 "OCCP0,OCU Compare Value Store Register of Ch.0"
|
|
group.word 0x106++0x01
|
|
line.word 0x00 "OCCP1,OCU Compare Value Store Register of Ch.1"
|
|
tree.end
|
|
tree "Channel 2 and 3"
|
|
group.byte 0x169++0x00
|
|
line.byte 0x00 "OCFS32,OCU Connecting FRT Select Register of Ch.2 and Ch.3"
|
|
bitfld.byte 0x00 4.--7. " FSO3 ,Selects FRT channel to be connected to OCU Ch.3" "Ch.0,Ch.1,Ch.2,?..."
|
|
bitfld.byte 0x00 0.--3. " FSO2 ,Selects FRT channel to be connected to OCU Ch.2" "Ch.0,Ch.1,Ch.2,?..."
|
|
group.byte 0x11C++0x00
|
|
line.byte 0x00 "OCSA32,OCU Control Register A of Ch.2 and Ch.3"
|
|
bitfld.byte 0x00 7. " IOP3 ,Match detection between OCU Ch.3 and OCCP3 (Read/Write)" "Not detected/Cleared,Detected/No effect"
|
|
bitfld.byte 0x00 6. " IOP2 ,Match detection between OCU Ch.2 and OCCP2 (Read/Write)" "Not detected/Cleared,Detected/No effect"
|
|
bitfld.byte 0x00 5. " IOE3 ,IOP3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " IOE2 ,IOE2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " CST3 ,Operation state of OCU Ch.3" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " CST2 ,Operation state of OCU Ch.2" "Disabled,Enabled"
|
|
group.byte 0x11D++0x00
|
|
line.byte 0x00 "OCSB32,OCU Control Register B"
|
|
bitfld.byte 0x00 7. " FM4 ,Operating Mode" "FM3-compatible,FM4"
|
|
bitfld.byte 0x00 4. " CMOD ,OCU's operating mode in FM3" "0,1"
|
|
bitfld.byte 0x00 1. " OTD3 ,State of RT3" "Low,High"
|
|
bitfld.byte 0x00 0. " OTD2 ,State of RT2" "Low,High"
|
|
group.byte 0x125++0x00
|
|
line.byte 0x00 "OCSC,OCU Control Register C"
|
|
bitfld.byte 0x00 5. " MOD5 ,Channel 5 mode" "0,1"
|
|
bitfld.byte 0x00 4. " MOD4 ,Channel 4 mode" "0,1"
|
|
bitfld.byte 0x00 3. " MOD3 ,Channel 3 mode" "0,1"
|
|
bitfld.byte 0x00 2. " MOD2 ,Channel 2 mode" "0,1"
|
|
bitfld.byte 0x00 1. " MOD1 ,Channel 1 mode" "0,1"
|
|
bitfld.byte 0x00 0. " MOD0 ,Channel 0 mode" "0,1"
|
|
group.byte 0x11E++0x00
|
|
line.byte 0x00 "OCSD32,OCU Control Register D of Ch.2 and Ch.3"
|
|
bitfld.byte 0x00 6.--7. " OCSE3BUFE ,OCSE3 buffer function enable/Timing of transfers" "Disabled,Enabled/FRT_CH3=0x00,Enabled/FRT_CH3=TCCP,Enabled/Both"
|
|
bitfld.byte 0x00 4.--5. " OCSE2BUFE ,OCSE2 buffer function enable/Timing of transfers" "Disabled,Enabled/FRT_CH2=0x00,Enabled/FRT_CH2=TCCP,Enabled/Both"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " OCCP3BUFE ,OCCP3 buffer function enable/Timing of transfers" "Disabled,Enabled/FRT_CH3=0x00,Enabled/FRT_CH3=TCCP,Enabled/Both"
|
|
bitfld.byte 0x00 0.--1. " OCCP2BUFE ,OCCP2 buffer function enable/Timing of transfers" "Disabled,Enabled/FRT_CH2=0x00,Enabled/FRT_CH2=TCCP,Enabled/Both"
|
|
if (d.b(ad:0x40020000+0x11D)&0x80)==0x80
|
|
group.word 0x130++0x01
|
|
line.word 0x00 "OCSE2,OCU Control Register E of Ch.2"
|
|
bitfld.word 0x00 14.--15. " RSB1415 ,Condition 1.FRT=0x0000 and 2.FRT/=OCCP2, set RT2" "Hold,Set,Reset,Reverse"
|
|
bitfld.word 0x00 12.--13. " RSB1213 ,Condition 1.FRT=TCCP and 2.FRT/=OCCP2, set RT2" "Hold,Set,Reset,Reverse"
|
|
bitfld.word 0x00 10.--11. " RSB1011 ,Condition 1.FRT=0x0000 and 2.FRT=OCCP2, set RT2" "Hold,Set,Reset,Reverse"
|
|
bitfld.word 0x00 8.--9. " RSB0809 ,Condition 1.FRT=UP and 2.FRT=OCCP2, set RT2" "Hold,Set,Reset,Reverse"
|
|
bitfld.word 0x00 6.--7. " RSB0607 ,Condition 1.FRT=TCCP and 2.FRT=OCCP2, set RT2" "Hold,Set,Reset,Reverse"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " RSB0405 ,Condition 1.FRT=DOWN and 2.FRT=OCCP2, set RT2" "Hold,Set,Reset,Reverse"
|
|
bitfld.word 0x00 3. " RSB3 ,Condition 1.FRT=0x0000 and 2.FRT=OCCP2, set IOP2" "Hold,Set"
|
|
bitfld.word 0x00 2. " RSB2 ,Condition 1.FRT=UP and 2.FRT=OCCP2, set IOP2" "Hold,Set"
|
|
bitfld.word 0x00 1. " RSB1 ,Condition 1.FRT=TCCP and 2.FRT=OCCP2, set IOP2" "Hold,Set"
|
|
bitfld.word 0x00 0. " RSB0 ,Condition 1.FRT=DOWN and 2.FRT=OCCP2,set IOP2" "Hold,Set"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "OCSE3,OCU Control Register E of Ch.3"
|
|
bitfld.long 0x00 30.--31. " RSB3031 ,Condition 1.FRT=0x0000,2.FRT/=OCCP3 and 3.FRT=OCCP2, set RT3" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 28.--29. " RSB2627 ,Condition 1.FRT=TCCP,2.FRT/=OCCP3 and 3.FRT=OCCP2, set RT3" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 26.--27. " RSB2627 ,Condition 1.FRT=0x0000,2.FRT=OCCP3 and 3.FRT=OCCP2, set RT3" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 24.--25. " RSB2425 ,Condition 1.FRT=UP,2.FRT=OCCP3 and 3.FRT=OCCP2, set RT3" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 22.--23. " RSB2223 ,Condition 1.FRT=TCCP,2.FRT=OCCP3 and 3.FRT=OCCP2, set RT3" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 20.--21. " RSB2021 ,Condition 1.FRT=DOWN,2.FRT=OCCP3 and 3.FRT=OCCP2, set RT3" "Hold,Set,Reset,Reverse"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " RSB1819 ,Condition 1.FRT=UP,2.FRT/=OCCP3 and 3.FRT=OCCP2, set RT3" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 16.--17. " RSB1617 ,Condition 1.FRT=DOWN,2.FRT/=OCCP3 and 3.FRT=OCCP2, set RT3" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 14.--15. " RSB1415 ,Condition 1.FRT=0x0000,2.FRT/=OCCP3 and 3.FRT/=OCCP2, set RT3" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 12.--13. " RSB1213 ,Condition 1.FRT=TCCP,2.FRT/=OCCP3 and 3.FRT/=OCCP2, set RT3" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 10.--11. " RSB1011 ,Condition 1.FRT=0x0000,2.FRT=OCCP3 and 3.FRT/=OCCP2, set RT3" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 8.--9. " RSB0809 ,Condition 1.FRT=UP,2.FRT=OCCP3 and 3.FRT/=OCCP2, set RT3" "Hold,Set,Reset,Reverse"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " RSB0607 ,Condition 1.FRT=TCCP,2.FRT=OCCP3 and 3.FRT/=OCCP2, set RT3" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 4.--5. " RSB0405 ,Condition 1.FRT=DOWN,2.FRT=OCCP3 and 3.FRT/=OCCP2, set RT3" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 3. " RSB3 ,Condition 1.FRT=0x0000 and 2.FRT=OCCP3, set IOP3" "Hold,Set"
|
|
bitfld.long 0x00 2. " RSB2 ,Condition 1.FRT=UP and 2.FRT=OCCP3, set IOP3" "Hold,Set"
|
|
bitfld.long 0x00 1. " RSB1 ,Condition 1.FRT=TCCP and 2.FRT=OCCP3, set IOP3" "Hold,Set"
|
|
bitfld.long 0x00 0. " RSB0 ,Condition 1.FRT=DOWN and 2.FRT=OCCP3,set IOP3" "Hold,Set"
|
|
else
|
|
hgroup.word 0x130++0x01
|
|
hide.word 0x00 "OCSE2,OCU Control Register E of Ch.2"
|
|
hgroup.long 0x134++0x03
|
|
hide.long 0x00 "OCSE3,OCU Control Register E of Ch.3"
|
|
endif
|
|
group.word 0x10A++0x01
|
|
line.word 0x00 "OCCP2,OCU Compare Value Store Register of Ch.2"
|
|
group.word 0x10E++0x01
|
|
line.word 0x00 "OCCP3,OCU Compare Value Store Register of Ch.3"
|
|
tree.end
|
|
tree "Channel 4 and 5"
|
|
group.byte 0x16A++0x00
|
|
line.byte 0x00 "OCFS54,OCU Connecting FRT Select Register of Ch.4 and Ch.5"
|
|
bitfld.byte 0x00 4.--7. " FSO5 ,Selects FRT channel to be connected to OCU Ch.5" "Ch.0,Ch.1,Ch.2,?..."
|
|
bitfld.byte 0x00 0.--3. " FSO5 ,Selects FRT channel to be connected to OCU Ch.4" "Ch.0,Ch.1,Ch.2,?..."
|
|
group.byte 0x120++0x00
|
|
line.byte 0x00 "OCSA54,OCU Control Register A of Ch.4 and Ch.5"
|
|
bitfld.byte 0x00 7. " IOP5 ,Match detection between OCU Ch.5 and OCCP5 (Read/Write)" "Not detected/Cleared,Detected/No effect"
|
|
bitfld.byte 0x00 6. " IOP4 ,Match detection between OCU Ch.4 and OCCP4(Read/Write)" "Not detected/Cleared,Detected/No effect"
|
|
bitfld.byte 0x00 5. " IOE5 ,IOP5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " IOE4 ,IOP4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " CST1 ,Operation state of OCU Ch.5" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " CST0 ,Operation state of OCU Ch.4" "Disabled,Enabled"
|
|
group.byte 0x121++0x00
|
|
line.byte 0x00 "OCSB54,OCU Control Register B of Ch.4 and Ch.5"
|
|
bitfld.byte 0x00 7. " FM4 ,Operating Mode" "FM3-compatible,FM4"
|
|
bitfld.byte 0x00 4. " CMOD ,OCU's operating mode in FM3" "0,1"
|
|
bitfld.byte 0x00 1. " OTD5 ,State of RT5" "Low,High"
|
|
bitfld.byte 0x00 0. " OTD4 ,State of RT4" "Low,High"
|
|
group.byte 0x125++0x00
|
|
line.byte 0x00 "OCSC,OCU Control Register C"
|
|
bitfld.byte 0x00 5. " MOD5 ,Channel 5 mode" "0,1"
|
|
bitfld.byte 0x00 4. " MOD4 ,Channel 4 mode" "0,1"
|
|
bitfld.byte 0x00 3. " MOD3 ,Channel 3 mode" "0,1"
|
|
bitfld.byte 0x00 2. " MOD2 ,Channel 2 mode" "0,1"
|
|
bitfld.byte 0x00 1. " MOD1 ,Channel 1 mode" "0,1"
|
|
bitfld.byte 0x00 0. " MOD0 ,Channel 0 mode" "0,1"
|
|
group.byte 0x122++0x00
|
|
line.byte 0x00 "OCSD54,OCU Control Register D of Ch.4 and Ch.5"
|
|
bitfld.byte 0x00 6.--7. " OCSE5BUFE ,OCSE5 buffer function enable/Timing of transfers" "Disabled,Enabled/FRT_CH5=0x00,Enabled/FRT_CH5=TCCP,Enabled/Both"
|
|
bitfld.byte 0x00 4.--5. " OCSE4BUFE ,OCSE4 buffer function enable/Timing of transfers" "Disabled,Enabled/FRT_CH4=0x00,Enabled/FRT_CH4=TCCP,Enabled/Both"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " OCCP5BUFE ,OCCP5 buffer function enable/Timing of transfers" "Disabled,Enabled/FRT_CH5=0x00,Enabled/FRT_CH5=TCCP,Enabled/Both"
|
|
bitfld.byte 0x00 0.--1. " OCCP4BUFE ,OCCP4 buffer function enable/Timing of transfers" "Disabled,Enabled/FRT_CH4=0x00,Enabled/FRT_CH4=TCCP,Enabled/Both"
|
|
if (d.b(ad:0x40020000+0x121)&0x80)==0x80
|
|
group.word 0x138++0x01
|
|
line.word 0x00 "OCSE4,OCU Control Register E of Ch.4"
|
|
bitfld.word 0x00 14.--15. " RSB1415 ,Condition 1.FRT=0x0000 and 2.FRT/=OCCP4, set RT4" "Hold,Set,Reset,Reverse"
|
|
bitfld.word 0x00 12.--13. " RSB1213 ,Condition 1.FRT=TCCP and 2.FRT/=OCCP4, set RT4" "Hold,Set,Reset,Reverse"
|
|
bitfld.word 0x00 10.--11. " RSB1011 ,Condition 1.FRT=0x0000 and 2.FRT=OCCP4, set RT4" "Hold,Set,Reset,Reverse"
|
|
bitfld.word 0x00 8.--9. " RSB0809 ,Condition 1.FRT=UP and 2.FRT=OCCP4, set RT4" "Hold,Set,Reset,Reverse"
|
|
bitfld.word 0x00 6.--7. " RSB0607 ,Condition 1.FRT=TCCP and 2.FRT=OCCP4, set RT4" "Hold,Set,Reset,Reverse"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " RSB0405 ,Condition 1.FRT=DOWN and 2.FRT=OCCP4, set RT4" "Hold,Set,Reset,Reverse"
|
|
bitfld.word 0x00 3. " RSB3 ,Condition 1.FRT=0x0000 and 2.FRT=OCCP4, set IOP4" "Hold,Set"
|
|
bitfld.word 0x00 2. " RSB2 ,Condition 1.FRT=UP and 2.FRT=OCCP4, set IOP4" "Hold,Set"
|
|
bitfld.word 0x00 1. " RSB1 ,Condition 1.FRT=TCCP and 2.FRT=OCCP4, set IOP4" "Hold,Set"
|
|
bitfld.word 0x00 0. " RSB0 ,Condition 1.FRT=DOWN and 2.FRT=OCCP4,set IOP4" "Hold,Set"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "OCSE5,OCU Control Register E of Ch.53"
|
|
bitfld.long 0x00 30.--31. " RSB3031 ,Condition 1.FRT=0x0000,2.FRT/=OCCP5 and 3.FRT=OCCP4, set RT5" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 28.--29. " RSB2627 ,Condition 1.FRT=TCCP,2.FRT/=OCCP5 and 3.FRT=OCCP4, set RT5" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 26.--27. " RSB2627 ,Condition 1.FRT=0x0000,2.FRT=OCCP5 and 3.FRT=OCCP4, set RT5" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 24.--25. " RSB2425 ,Condition 1.FRT=UP,2.FRT=OCCP5 and 3.FRT=OCCP4, set RT5" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 22.--23. " RSB2223 ,Condition 1.FRT=TCCP,2.FRT=OCCP5 and 3.FRT=OCCP4, set RT5" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 20.--21. " RSB2021 ,Condition 1.FRT=DOWN,2.FRT=OCCP5 and 3.FRT=OCCP4, set RT5" "Hold,Set,Reset,Reverse"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " RSB1819 ,Condition 1.FRT=UP,2.FRT/=OCCP5 and 3.FRT=OCCP4, set RT5" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 16.--17. " RSB1617 ,Condition 1.FRT=DOWN,2.FRT/=OCCP5 and 3.FRT=OCCP4, set RT5" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 14.--15. " RSB1415 ,Condition 1.FRT=0x0000,2.FRT/=OCCP5 and 3.FRT/=OCCP4, set RT5" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 12.--13. " RSB1213 ,Condition 1.FRT=TCCP,2.FRT/=OCCP5 and 3.FRT/=OCCP4, set RT5" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 10.--11. " RSB1011 ,Condition 1.FRT=0x0000,2.FRT=OCCP5 and 3.FRT/=OCCP4, set RT5" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 8.--9. " RSB0809 ,Condition 1.FRT=UP,2.FRT=OCCP5 and 3.FRT/=OCCP4, set RT5" "Hold,Set,Reset,Reverse"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " RSB0607 ,Condition 1.FRT=TCCP,2.FRT=OCCP5 and 3.FRT/=OCCP4, set RT5" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 4.--5. " RSB0405 ,Condition 1.FRT=DOWN,2.FRT=OCCP5 and 3.FRT/=OCCP4, set RT5" "Hold,Set,Reset,Reverse"
|
|
bitfld.long 0x00 3. " RSB3 ,Condition 1.FRT=0x0000 and 2.FRT=OCCP5, set IOP5" "Hold,Set"
|
|
bitfld.long 0x00 2. " RSB2 ,Condition 1.FRT=UP and 2.FRT=OCCP5, set IOP5" "Hold,Set"
|
|
bitfld.long 0x00 1. " RSB1 ,Condition 1.FRT=TCCP and 2.FRT=OCCP5, set IOP5" "Hold,Set"
|
|
bitfld.long 0x00 0. " RSB0 ,Condition 1.FRT=DOWN and 2.FRT=OCCP5,set IOP5" "Hold,Set"
|
|
else
|
|
hgroup.word 0x138++0x01
|
|
hide.word 0x00 "OCSE4,OCU Control Register E of Ch.4"
|
|
hgroup.long 0x13C++0x03
|
|
hide.long 0x00 "OCSE5,OCU Control Register E of Ch.5"
|
|
endif
|
|
group.word 0x112++0x01
|
|
line.word 0x00 "OCCP4,OCU Compare Value Store Register of Ch.4"
|
|
group.word 0x116++0x01
|
|
line.word 0x00 "OCCP5,OCU Compare Value Store Register of Ch.5"
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "WFG (Waveform Generator)"
|
|
base ad:0x40020000
|
|
width 8.
|
|
tree "Channel 1_0"
|
|
group.word 0x1A4++0x01
|
|
line.word 0x00 "WFSA10,WFG Ch.10 Control Register A"
|
|
bitfld.word 0x00 12.--13. " DMOD ,Polarity for RTO0 and RTO1" "Not reversed,Reversed,?..."
|
|
bitfld.word 0x00 10.--11. " PGEN ,Reflection of the CH_PPG signal" "Not reflected,Signal(0),Signal(1),Logic OR"
|
|
bitfld.word 0x00 8.--9. " PSEL ,Set PPG as output GATE signal and input source of PPG" "Ch.0,Ch.2,Ch.4,"
|
|
bitfld.word 0x00 6.--7. " GTEN ,Generation of the CH_GATE signal" "Not generated,Generated,Generated,Generated"
|
|
textline " "
|
|
bitfld.word 0x00 3.--5. " TMD ,WFG's operation mode" "Through,RT-PPG,Timer-PPG,,RT-dead timer,RT-dead timer filter,PPG-dead timer filter,PPG-dead timer"
|
|
bitfld.word 0x00 0.--2. " DCK ,Clock count cycle value" "PCLK*1,PCLK*2,PCLK*4,PCLK*8,PCLK*16,PCLK*32,PCLK*64,PCLK*128"
|
|
group.word 0x190++0x003
|
|
line.word 0x00 "WFTA10,WFG Ch.10 Timer Value Register A"
|
|
line.word 0x02 "WFTB10,WFG Ch.10 Timer Value Register B"
|
|
if (((d.w(ad:0x40020000+0x1A4)&(0x38))==0x28)||((d.w(ad:0x40020000+0x1A4)&(0x38))==0x30))
|
|
group.word 0x18E++0x01
|
|
line.word 0x00 "WFTF10,WFG ch.10 Pulse Counter Value Register - Number of filter counts"
|
|
elif ((d.w(ad:0x40020000+0x1A4)&(0x38))==0x18)
|
|
hgroup.word 0x18E++0x01
|
|
hide.word 0x00 "WFTF10,WFG ch.10 Pulse Counter Value Register"
|
|
else
|
|
group.word 0x18E++0x01
|
|
line.word 0x00 "WFTF10,WFG ch.10 Pulse Counter Value Register - Number of 16-bit reload timer counts"
|
|
endif
|
|
tree.end
|
|
tree "Channel 3_2"
|
|
group.word 0x1A8++0x01
|
|
line.word 0x00 "WFSA32,WFG Ch.32 Control Register A"
|
|
bitfld.word 0x00 12.--13. " DMOD ,Polarity for RTO2 and RTO3" "Not reversed,Reversed,?..."
|
|
bitfld.word 0x00 10.--11. " PGEN ,Reflection of the CH_PPG signal" "Not reflected,Signal(0),Signal(1),Logic OR"
|
|
bitfld.word 0x00 8.--9. " PSEL ,Set PPG as output GATE signal and input source of PPG" "Ch.0,Ch.2,Ch.4,"
|
|
bitfld.word 0x00 6.--7. " GTEN ,Generation of the CH_GATE signal" "Not generated,Generated,Generated,Generated"
|
|
textline " "
|
|
bitfld.word 0x00 3.--5. " TMD ,WFG's operation mode" "Through,RT-PPG,Timer-PPG,,RT-dead timer,RT-dead timer filter,PPG-dead timer filter,PPG-dead timer"
|
|
bitfld.word 0x00 0.--2. " DCK ,Clock count cycle value" "PCLK*1,PCLK*2,PCLK*4,PCLK*8,PCLK*16,PCLK*32,PCLK*64,PCLK*128"
|
|
group.word 0x198++0x003
|
|
line.word 0x00 "WFTA32,WFG Ch.32 Timer Value Register A"
|
|
line.word 0x02 "WFTB32,WFG Ch.32 Timer Value Register B"
|
|
if (((d.w(ad:0x40020000+0x1A8)&(0x38))==0x28)||((d.w(ad:0x40020000+0x1A8)&(0x38))==0x30))
|
|
group.word 0x196++0x01
|
|
line.word 0x00 "WFTF32,WFG ch.32 Pulse Counter Value Register - Number of filter counts"
|
|
elif ((d.w(ad:0x40020000+0x1A8)&(0x38))==0x18)
|
|
hgroup.word 0x196++0x01
|
|
hide.word 0x00 "WFTF32,WFG ch.32 Pulse Counter Value Register"
|
|
else
|
|
group.word 0x196++0x01
|
|
line.word 0x00 "WFTF32,WFG ch.32 Pulse Counter Value Register - Number of 16-bit reload timer counts"
|
|
endif
|
|
tree.end
|
|
tree "Channel 5_4"
|
|
group.word 0x1AC++0x01
|
|
line.word 0x00 "WFSA54,WFG Ch.54 Control Register A"
|
|
bitfld.word 0x00 12.--13. " DMOD ,Polarity for RTO4 and RTO5" "Not reversed,Reversed,?..."
|
|
bitfld.word 0x00 10.--11. " PGEN ,Reflection of the CH_PPG signal" "Not reflected,Signal(0),Signal(1),Logic OR"
|
|
bitfld.word 0x00 8.--9. " PSEL ,Set PPG as output GATE signal and input source of PPG" "Ch.0,Ch.2,Ch.4,"
|
|
bitfld.word 0x00 6.--7. " GTEN ,Generation of the CH_GATE signal" "Not generated,Generated,Generated,Generated"
|
|
textline " "
|
|
bitfld.word 0x00 3.--5. " TMD ,WFG's operation mode" "Through,RT-PPG,Timer-PPG,,RT-dead timer,RT-dead timer filter,PPG-dead timer filter,PPG-dead timer"
|
|
bitfld.word 0x00 0.--2. " DCK ,Clock count cycle value" "PCLK*1,PCLK*2,PCLK*4,PCLK*8,PCLK*16,PCLK*32,PCLK*64,PCLK*128"
|
|
group.word 0x1A0++0x003
|
|
line.word 0x00 "WFTA54,WFG Ch.54 Timer Value Register A"
|
|
line.word 0x02 "WFTB54,WFG Ch.54 Timer Value Register B"
|
|
if (((d.w(ad:0x40020000+0x1AC)&(0x38))==0x28)||((d.w(ad:0x40020000+0x1AC)&(0x38))==0x30))
|
|
group.word 0x19E++0x01
|
|
line.word 0x00 "WFTF54,WFG ch.54 Pulse Counter Value Register - Number of filter counts"
|
|
elif ((d.w(ad:0x40020000+0x1AC)&(0x38))==0x18)
|
|
hgroup.word 0x19E++0x01
|
|
hide.word 0x00 "WFTF54,WFG ch.54 Pulse Counter Value Register"
|
|
else
|
|
group.word 0x19E++0x01
|
|
line.word 0x00 "WFTF54,WFG ch.54 Pulse Counter Value Register - Number of 16-bit reload timer counts"
|
|
endif
|
|
tree.end
|
|
tree "NZCL registers"
|
|
group.word 0x1B4++0x01
|
|
line.word 0x00 "NZCL,NZCL Control Register"
|
|
bitfld.word 0x00 14. " WIM54 ,WFG54 reload timer interrupt mask when the WFIR_TMIF54 flag is set" "Not masked,Masked"
|
|
bitfld.word 0x00 13. " WIM32 ,WFG32 reload timer interrupt mask when the WFIR_TMIF32 flag is set" "Not masked,Masked"
|
|
bitfld.word 0x00 12. " WIM10 ,WFG10 reload timer interrupt mask when the WFIR_TMIF10 flag is set" "Not masked,Masked"
|
|
bitfld.word 0x00 9. " DIMB ,DTIF interrupt mask - WFIR_TIFDTIFB" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8. " DIMA ,DTIF interrupt mask - WFIR_DTIFA" "Not masked,Masked"
|
|
bitfld.word 0x00 5. " DTIEB ,Setting the WFIR_DTIFB flag for the path from the DTTIX pin" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " SDTI ,Setting the WFIR_DTIFA" "No effect,Set"
|
|
bitfld.word 0x00 1.--3. " NWS ,Noise-canceling width for a digital noise-canceller" "Disabled,4 cycles,8 cycles,16 cycles,32 cycles,64 cycles,128 cycles,"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DTIEA ,WFIR_DTIFA setting for the path via digital noise filter from the DTTIX input pin enable" "Disabled,Enabled"
|
|
group.word 0x1B0++0x01
|
|
line.word 0x00 "WFIR,WFG Interrupt Control Register"
|
|
bitfld.word 0x00 15. " TMIS54 ,Stopping the WFG52 reload timer and clearing TMIF52" "No effect,Stopped"
|
|
bitfld.word 0x00 14. " TMIE54 ,Starting WFG54 reload timer and checking its operation state" "Stopped,Started"
|
|
bitfld.word 0x00 13. " TMIC54 ,Clearing TIMF54 bit" "No effect,Clear"
|
|
rbitfld.word 0x00 12. " TMIF54 ,WFG54 reload timer interrupt occurrence" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.word 0x00 11. " TMIS32 ,Stopping the WFG32 reload timer and clearing TMIF32" "No effect,Stopped"
|
|
bitfld.word 0x00 10. " TMIE32 ,Starting WFG32 reload timer and checking its operation state" "Stopped,Started"
|
|
bitfld.word 0x00 9. " TMIC32 ,Clearing TIMF32 bit" "No effect,Clear"
|
|
rbitfld.word 0x00 8. " TMIF32 ,WFG32 reload timer interrupt occurrence" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TMIS10 ,Stopping the WFG10 reload timer and clearing TMIF10" "No effect,Stopped"
|
|
bitfld.word 0x00 6. " TMIE10 ,Starting WFG10 reload timer and checking its operation state" "Stopped,Started"
|
|
bitfld.word 0x00 5. " TMIC10 ,Clearing TIMF10 bit" "No effect,Clear"
|
|
rbitfld.word 0x00 4. " TMIF10 ,WFG10 reload timer interrupt occurrence" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DTICB ,Clearing of the DTIFB interrupt flag" "No effect,Clear"
|
|
rbitfld.word 0x00 2. " DTIFB ,Detection of DTTIX signal input via analog noise filter" "Not detected,Detected"
|
|
bitfld.word 0x00 1. " DTICA ,Clearing of the DTIFA interrupt flag" "No effect,Clear"
|
|
rbitfld.word 0x00 0. " DTIFA ,Event of DTTIX signal input via digital noise-canceller" "Flag not set,Flag set"
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "ICU (Input Capture Unit)"
|
|
base ad:0x40020000
|
|
width 8.
|
|
tree "Channel 0 and 1"
|
|
group.byte 0x16C++0x00
|
|
line.byte 0x00 "ICFS10,ICU Ch.0 and Ch.1 Connecting FRT Select Register"
|
|
bitfld.byte 0x00 4.--7. " FSI1 ,Select FRT channel to connect to ICU Ch.1" "Ch.0,Ch.1,Ch.2,?..."
|
|
bitfld.byte 0x00 0.--3. " FSI0 ,Select FRT channel to connect to ICU Ch.0" "Ch.0,Ch.1,Ch.2,?..."
|
|
group.byte 0x184++0x00
|
|
line.byte 0x00 "ICSA10,ICU Ch.0 and Ch.1 Control Register A"
|
|
bitfld.byte 0x00 7. " ICP1 ,Edge or operation detection at ICU Ch.1 (Read/Write)" "Not detected/Cleared,Detected/No effect"
|
|
bitfld.byte 0x00 6. " ICP0 ,Edge or operation detection at ICU Ch.0 (Read/Write)" "Not detected/Cleared,Detected/No effect"
|
|
bitfld.byte 0x00 5. " ICE1 ,ICP1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ICE0 ,ICP0 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " EG1 ,ICU Ch.1 operation enable/Edge select" "Disabled/Ignored,Enabled/Rising,Enabled/Falling,Enabled/Both"
|
|
bitfld.byte 0x00 0.--1. " EG0 ,ICU Ch.0 operation enable/Edge select" "Disabled/Ignored,Enabled/Rising,Enabled/Falling,Enabled/Both"
|
|
rgroup.byte 0x185++0x00
|
|
line.byte 0x00 "ICSB10,ICU Ch.0 and Ch.1 Control Register B"
|
|
bitfld.byte 0x00 1. " IEI1 ,Latest edge of ICU Ch.1" "Falling,Rising"
|
|
bitfld.byte 0x00 0. " IEI0 ,Latest edge of ICU Ch.0" "Falling,Rising"
|
|
rgroup.word 0x176++0x01
|
|
line.word 0x00 "ICCP0,ICU Ch.0 Capture Value Store Register"
|
|
rgroup.word 0x17A++0x01
|
|
line.word 0x00 "ICCP1,ICU Ch.1 Capture Value Store Register"
|
|
tree.end
|
|
tree "Channel 2 and 3"
|
|
group.byte 0x16D++0x00
|
|
line.byte 0x00 "ICFS32,ICU Ch.2 and Ch.3 Connecting FRT Select Register"
|
|
bitfld.byte 0x00 4.--7. " FSI3 ,Select FRT channel to connect to ICU Ch.3" "Ch.0,Ch.1,Ch.2,?..."
|
|
bitfld.byte 0x00 0.--3. " FSI2 ,Select FRT channel to connect to ICU Ch.2" "Ch.0,Ch.1,Ch.2,?..."
|
|
group.byte 0x188++0x00
|
|
line.byte 0x00 "ICSA32,ICU Ch.2 and Ch.3 Control Register A"
|
|
bitfld.byte 0x00 7. " ICP3 ,Edge or operation detection at ICU Ch.3 (Read/Write)" "Not detected/Cleared,Detected/No effect"
|
|
bitfld.byte 0x00 6. " ICP2 ,Edge or operation detection at ICU Ch.2 (Read/Write)" "Not detected/Cleared,Detected/No effect"
|
|
bitfld.byte 0x00 5. " ICE3 ,ICP3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ICE2 ,ICP2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " EG3 ,ICU Ch.3 operation enable/Edge select" "Disabled/Ignored,Enabled/Rising,Enabled/Falling,Enabled/Both"
|
|
bitfld.byte 0x00 0.--1. " EG2 ,ICU Ch.2 operation enable/Edge select" "Disabled/Ignored,Enabled/Rising,Enabled/Falling,Enabled/Both"
|
|
rgroup.byte 0x189++0x00
|
|
line.byte 0x00 "ICSB32,ICU Ch.2 and Ch.3 Control Register B"
|
|
bitfld.byte 0x00 1. " IEI3 ,Latest edge of ICU Ch.3" "Falling,Rising"
|
|
bitfld.byte 0x00 0. " IEI2 ,Latest edge of ICU Ch.2" "Falling,Rising"
|
|
rgroup.word 0x17E++0x01
|
|
line.word 0x00 "ICCP2,ICU Ch.2 Capture Value Store Register"
|
|
rgroup.word 0x182++0x01
|
|
line.word 0x00 "ICCP3,ICU Ch.3 Capture Value Store Register"
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "ADCMP (ADC Start Compare)"
|
|
base ad:0x40020000
|
|
width 8.
|
|
group.byte 0x170++0x00 "Channel 0 and 1"
|
|
line.byte 0x00 "ACFS10,ADCMP Ch.0 and Ch.1 Connecting FRT Select Register"
|
|
bitfld.byte 0x00 4.--7. " FSA1 ,Select FRT channel to connect to ADCMP Ch.1" "Ch.0,Ch.1,Ch.2,?..."
|
|
bitfld.byte 0x00 0.--3. " FSA0 ,Select FRT channel to connect to ADCMP Ch.0" "Ch.0,Ch.1,Ch.2,?..."
|
|
if (((d.w(ad:0x40020000+0x1D5)&0xFF)==0x00)&&((d.w(ad:0x40020000+0x1D9)&0xFF)==0x00))&&((d.w(ad:0x40020000+0x1DD)&0xFF)==0x00)
|
|
group.word 0x1D0++0x01
|
|
line.word 0x00 "ACSA,ADCMP Ch.0, Ch.1, Ch.2 Control Register A"
|
|
bitfld.word 0x00 10.--11. " SEL32 ,ADCMP Ch.2 and Ch.3 operation select (Ch.2/Ch.3)" "Example 1/Not used,Example 2/Not used,Example 3/Not used,Example 4/Example 4"
|
|
bitfld.word 0x00 8.--9. " SEL10 ,ADCMP Ch.0 and Ch.1 operation select (Ch.0/Ch.1)" "Example 1/Not used,Example 2/Not used,Example 3/Not used,Example 4/Example 4"
|
|
bitfld.word 0x00 2.--3. " CE32 ,Compatibility of ADCMP Ch.2 and Ch.3 with FM3 Family enable" "Disabled,Enabled,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CE10 ,Compatibility of ADCMP Ch.0 and Ch.1 with FM3 Family enable" "Disabled,Enabled,?..."
|
|
elif (((d.w(ad:0x40020000+0x1D5)&0xFF)==0x00)&&((d.w(ad:0x40020000+0x1D9)&0xFF)==0x00))&&((d.w(ad:0x40020000+0x1DD)&0xFF)!=0x00)
|
|
group.word 0x1D0++0x01
|
|
line.word 0x00 "ACSA,ADCMP Ch.0, Ch.1, Ch.2 Control Register A"
|
|
bitfld.word 0x00 10.--11. " SEL32 ,ADCMP Ch.2 and Ch.3 operation select (Ch.2/Ch.3)" "Example 1/Not used,Example 2/Not used,Example 3/Not used,Example 4/Example 4"
|
|
bitfld.word 0x00 8.--9. " SEL10 ,ADCMP Ch.0 and Ch.1 operation select (Ch.0/Ch.1)" "Example 1/Not used,Example 2/Not used,Example 3/Not used,Example 4/Example 4"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CE10 ,Compatibility of ADCMP Ch.0 and Ch.1 with FM3 Family enable" "Disabled,Enabled,?..."
|
|
elif (((d.w(ad:0x40020000+0x1D5)&0xFF)!=0x00)||((d.w(ad:0x40020000+0x1D9)&0xFF)!=0x00))&&((d.w(ad:0x40020000+0x1DD)&0xFF)==0x00)
|
|
group.word 0x1D0++0x01
|
|
line.word 0x00 "ACSA,ADCMP Ch.0, Ch.1, Ch.2 Control Register A"
|
|
bitfld.word 0x00 10.--11. " SEL32 ,ADCMP Ch.2 and Ch.3 operation select (Ch.2/Ch.3)" "Example 1/Not used,Example 2/Not used,Example 3/Not used,Example 4/Example 4"
|
|
bitfld.word 0x00 8.--9. " SEL10 ,ADCMP Ch.0 and Ch.1 operation select (Ch.0/Ch.1)" "Example 1/Not used,Example 2/Not used,Example 3/Not used,Example 4/Example 4"
|
|
bitfld.word 0x00 2.--3. " CE32 ,Compatibility of ADCMP Ch.2 and Ch.3 with FM3 Family enable" "Disabled,Enabled,?..."
|
|
textline " "
|
|
else
|
|
group.word 0x1D0++0x01
|
|
line.word 0x00 "ACSA,ADCMP Ch.0, Ch.1, Ch.2 Control Register A"
|
|
bitfld.word 0x00 10.--11. " SEL32 ,ADCMP Ch.2 and Ch.3 operation select (Ch.2/Ch.3)" "Example 1/Not used,Example 2/Not used,Example 3/Not used,Example 4/Example 4"
|
|
bitfld.word 0x00 8.--9. " SEL10 ,ADCMP Ch.0 and Ch.1 operation select (Ch.0/Ch.1)" "Example 1/Not used,Example 2/Not used,Example 3/Not used,Example 4/Example 4"
|
|
textline " "
|
|
endif
|
|
group.byte 0x1D4++0x00
|
|
line.byte 0x00 "ACSC0,ADCMP Ch.0 Control Register C"
|
|
bitfld.byte 0x00 2.--4. " ADSEL ,Output ADC start trigger select" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0.--1. " BUFE ,Buffer function transfer timing of the ACMP" "Disabled,FRT=0x0000,FRT=TCCP,Both"
|
|
group.byte 0x1D8++0x00
|
|
line.byte 0x00 "ACSC1,ADCMP Ch.1 Control Register C"
|
|
bitfld.byte 0x00 2.--4. " ADSEL ,Output ADC start trigger select" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0.--1. " BUFE ,Buffer function transfer timing of the ACMP" "Disabled,FRT=0x0000,FRT=TCCP,Both"
|
|
group.byte 0x1D5++0x00
|
|
line.byte 0x00 "ACSD0,ADCMP Ch.0 Control Register D"
|
|
bitfld.byte 0x00 7. " ZE ,ADCMP operation when FRT=0x00" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " UE ,ADCMP counting UP for FRT enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " PE ,ADCMP counting DOWN at PEAK of FRT enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " DE ,ADCMP counting DOWN for FRT enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " OCUS ,OCU OCCP select to start offset" "OCCP0,OCCP1"
|
|
bitfld.byte 0x00 0. " AMOD ,ADCMP operation mode select " "Normal,Offset"
|
|
group.byte 0x1D9++0x00
|
|
line.byte 0x00 "ACSD1,ADCMP Ch.1 Control Register D"
|
|
bitfld.byte 0x00 7. " ZE ,ADCMP operation when FRT=0x00" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " UE ,ADCMP counting UP for FRT enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " PE ,ADCMP counting DOWN at PEAK of FRT enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " DE ,ADCMP counting DOWN for FRT enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " OCUS ,OCU OCCP select to start offset" "OCCP0,OCCP1"
|
|
bitfld.byte 0x00 0. " AMOD ,ADCMP operation mode select " "Normal,Offset"
|
|
group.word 0x1BA++0x01
|
|
line.word 0x00 "ACMP0,ADCMP Ch.0 Compare Value Store Register"
|
|
group.word 0x1BE++0x01
|
|
line.word 0x00 "ACMP1,ADCMP Ch.1 Compare Value Store Register"
|
|
group.byte 0x170++0x00 "Channel 2"
|
|
line.byte 0x00 "ACFS32,ADCMP Ch.2 Connecting FRT Select Register"
|
|
bitfld.byte 0x00 0.--3. " FSA2 ,Select FRT channel to connect to ADCMP Ch.2" "Ch.0,Ch.1,Ch.2,?..."
|
|
group.byte 0x1DC++0x00
|
|
line.byte 0x00 "ACSC2,ADCMP Ch.2 Control Register C"
|
|
bitfld.byte 0x00 2.--4. " ADSEL ,Output ADC start trigger select" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0.--1. " BUFE ,Buffer function transfer timing of the ACMP" "Disabled,FRT=0x0000,FRT=TCCP,Both"
|
|
group.byte 0x1DD++0x00
|
|
line.byte 0x00 "ACSD2,ADCMP Ch.2 Control Register D"
|
|
bitfld.byte 0x00 7. " ZE ,ADCMP operation when FRT=0x0000" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " UE ,ADCMP counting UP for FRT enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " PE ,ADCMP counting DOWN at PEAK of FRT enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " DE ,ADCMP counting DOWN for FRT enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " OCUS ,OCU OCCP select to start offset" "OCCP2,OCCP3"
|
|
bitfld.byte 0x00 0. " AMOD ,ADCMP operation mode select " "Normal,Offset"
|
|
group.word 0x1C2++0x01
|
|
line.word 0x00 "ACMP2,ADCMP Ch.2 Compare Value Store Register"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif !cpuis("S6E1C*")
|
|
tree "PPG (Programmable Pulse Generator)"
|
|
base ad:0x40024000
|
|
width 10.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "TTCR0,PPG Start Trigger Control Register 0"
|
|
bitfld.byte 0x00 7. " TRG6O ,PPG6TG start trigger" "Disabled,No Effect"
|
|
bitfld.byte 0x00 6. " TRG4O ,PPG4TG start trigger" "Disabled,No Effect"
|
|
bitfld.byte 0x00 5. " TRG2O ,PPG2TG start trigger" "Disabled,No Effect"
|
|
bitfld.byte 0x00 4. " TRG0O ,PPG0TG start trigger" "Disabled,No Effect"
|
|
bitfld.byte 0x00 2.--3. " CS0 ,8-bit UP counter clock select" "PCLK/2,PCLK/8,PCLK/32,PCLK/64"
|
|
rbitfld.byte 0x00 1. " MONI0 ,8-bit UP counter operation state" "Stopped,Started"
|
|
bitfld.byte 0x00 0. " STR0 ,8-bit UP counter operation enable" "No effect,Enabled"
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "TTCR1,PPG Start Trigger Control Register 1"
|
|
bitfld.byte 0x00 7. " TRG7O ,PPG14TG start trigger" "Disabled,No Effect"
|
|
bitfld.byte 0x00 6. " TRG5O ,PPG12TG start trigger" "Disabled,No Effect"
|
|
bitfld.byte 0x00 5. " TRG3O ,PPG10TG start trigger" "Disabled,No Effect"
|
|
bitfld.byte 0x00 4. " TRG1O ,PPG8TG start trigger" "Disabled,No Effect"
|
|
bitfld.byte 0x00 2.--3. " CS1 ,8-bit UP counter clock select" "PCLK/2,PCLK/8,PCLK/32,PCLK/64"
|
|
rbitfld.byte 0x00 1. " MONI1 ,8-bit UP counter operation state" "Stopped,Started"
|
|
bitfld.byte 0x00 0. " STR1 ,8-bit UP counter operation enable" "No effect,Enabled"
|
|
group.byte 0x41++0x00
|
|
line.byte 0x00 "TTCR2,PPG Start Trigger Control Register 2"
|
|
bitfld.byte 0x00 7. " TRG22O ,PPG22TG start trigger" "Disabled,No Effect"
|
|
bitfld.byte 0x00 6. " TRG20O ,PPG20TG start trigger" "Disabled,No Effect"
|
|
bitfld.byte 0x00 5. " TRG18O ,PPG18TG start trigger" "Disabled,No Effect"
|
|
bitfld.byte 0x00 4. " TRG16O ,PPG16TG start trigger" "Disabled,No Effect"
|
|
bitfld.byte 0x00 2.--3. " CS2 ,8-bit UP counter clock select" "PCLK/2,PCLK/8,PCLK/32,PCLK/64"
|
|
rbitfld.byte 0x00 1. " MONI2 ,8-bit UP counter operation state" "Stopped,Started"
|
|
bitfld.byte 0x00 0. " STR2 ,8-bit UP counter operation enable" "No effect,Enabled"
|
|
group.byte 0x09++0x00
|
|
line.byte 0x00 "COMP0,PPG Compare Register 0"
|
|
group.byte 0x29++0x00
|
|
line.byte 0x00 "COMP1,PPG Compare Register 1"
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "COMP2,PPG Compare Register 2"
|
|
group.byte 0x2C++0x00
|
|
line.byte 0x00 "COMP3,PPG Compare Register 3"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "COMP4,PPG Compare Register 4"
|
|
group.byte 0x31++0x00
|
|
line.byte 0x00 "COMP5,PPG Compare Register 5"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "COMP6,PPG Compare Register 6"
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "COMP7,PPG Compare Register 7"
|
|
group.byte 0x49++0x00
|
|
line.byte 0x00 "COMP8,PPG Compare Register 8"
|
|
group.byte 0x4C++0x00
|
|
line.byte 0x00 "COMP10,PPG Compare Register 10"
|
|
group.byte 0x51++0x00
|
|
line.byte 0x00 "COMP12,PPG Compare Register 12"
|
|
group.byte 0x54++0x00
|
|
line.byte 0x00 "COMP14,PPG Compare Register 14"
|
|
group.word 0x100++0x01
|
|
line.word 0x00 "TRG0,PPG Start Register 0"
|
|
bitfld.word 0x00 15. " PEN15 ,PPG15 start trigger" "Stopped,Started"
|
|
bitfld.word 0x00 14. " PEN14 ,PPG14 start trigger" "Stopped,Started"
|
|
bitfld.word 0x00 13. " PEN13 ,PPG13 start trigger" "Stopped,Started"
|
|
bitfld.word 0x00 12. " PEN12 ,PPG12 start trigger" "Stopped,Started"
|
|
bitfld.word 0x00 11. " PEN11 ,PPG11 start trigger" "Stopped,Started"
|
|
bitfld.word 0x00 10. " PEN10 ,PPG10 start trigger" "Stopped,Started"
|
|
bitfld.word 0x00 9. " PEN09 ,PPG9 start trigger" "Stopped,Started"
|
|
bitfld.word 0x00 8. " PEN08 ,PPG8 start trigger" "Stopped,Started"
|
|
textline " "
|
|
bitfld.word 0x00 7. " PEN07 ,PPG7 start trigger" "Stopped,Started"
|
|
bitfld.word 0x00 6. " PEN06 ,PPG6 start trigger" "Stopped,Started"
|
|
bitfld.word 0x00 5. " PEN05 ,PPG5 start trigger" "Stopped,Started"
|
|
bitfld.word 0x00 4. " PEN04 ,PPG4 start trigger" "Stopped,Started"
|
|
bitfld.word 0x00 3. " PEN03 ,PPG3 start trigger" "Stopped,Started"
|
|
bitfld.word 0x00 2. " PEN02 ,PPG2 start trigger" "Stopped,Started"
|
|
bitfld.word 0x00 1. " PEN01 ,PPG1 start trigger" "Stopped,Started"
|
|
bitfld.word 0x00 0. " PEN00 ,PPG0 start trigger" "Stopped,Started"
|
|
group.word 0x140++0x01
|
|
line.word 0x00 "TRG1,PPG Start Register 1"
|
|
bitfld.word 0x00 7. " PEN23 ,PPG23 start trigger" "Stopped,Started"
|
|
bitfld.word 0x00 6. " PEN22 ,PPG22 start trigger" "Stopped,Started"
|
|
bitfld.word 0x00 5. " PEN21 ,PPG21 start trigger" "Stopped,Started"
|
|
bitfld.word 0x00 4. " PEN20 ,PPG20 start trigger" "Stopped,Started"
|
|
bitfld.word 0x00 3. " PEN19 ,PPG19 start trigger" "Stopped,Started"
|
|
bitfld.word 0x00 2. " PEN18 ,PPG18 start trigger" "Stopped,Started"
|
|
bitfld.word 0x00 1. " PEN17 ,PPG17 start trigger" "Stopped,Started"
|
|
bitfld.word 0x00 0. " PEN16 ,PPG16 start trigger" "Stopped,Started"
|
|
group.word 0x104++0x01
|
|
line.word 0x00 "REVC0,Output Reverse Register 0"
|
|
bitfld.word 0x00 15. " REV15 ,PPG15 Output Reverse Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " REV14 ,PPG14 Output Reverse Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " REV13 ,PPG13 Output Reverse Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " REV12 ,PPG12 Output Reverse Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " REV11 ,PPG11 Output Reverse Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " REV10 ,PPG10 Output Reverse Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " REV09 ,PPG9 Output Reverse Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " REV08 ,PPG8 Output Reverse Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " REV07 ,PPG7 Output Reverse Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " REV06 ,PPG6 Output Reverse Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " REV05 ,PPG5 Output Reverse Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " REV04 ,PPG4 Output Reverse Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " REV03 ,PPG3 Output Reverse Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " REV02 ,PPG2 Output Reverse Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " REV01 ,PPG1 Output Reverse Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " REV00 ,PPG0 Output Reverse Enable" "Disabled,Enabled"
|
|
group.word 0x144++0x01
|
|
line.word 0x00 "REVC1,Output Reverse Register 1"
|
|
bitfld.word 0x00 7. " REV23 ,PPG23 Output Reverse Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " REV22 ,PPG22 Output Reverse Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " REV21 ,PPG21 Output Reverse Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " REV20 ,PPG20 Output Reverse Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " REV19 ,PPG19 Output Reverse Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " REV18 ,PPG18 Output Reverse Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " REV17 ,PPG17 Output Reverse Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " REV16 ,PPG16 Output Reverse Enable" "Disabled,Enabled"
|
|
group.byte 0x201++0x00
|
|
line.byte 0x00 "PPGC0,PPG Operation Mode Control Register 0"
|
|
bitfld.byte 0x00 7. " PIE ,PPG0 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " PUF ,PPG0 Counter Underflow" "No underflow,Underflow"
|
|
bitfld.byte 0x00 5. " INTM ,Interrupt Mode Select" "PPLH or PPLL,PPLH"
|
|
bitfld.byte 0x00 3.--4. " PCS ,PPG0 DOWN Counter Operation Clock Select" "PCLK,PCLK/4,PCLK/16,PCLK/64"
|
|
bitfld.byte 0x00 1.--2. " MD ,PPG0 Operation Mode Set" "8bit,8+8bit,16bit,16+16bit"
|
|
bitfld.byte 0x00 0. " TTRG ,PPG0 start trigger select" "TRG,TGC"
|
|
group.byte 0x200++0x00
|
|
line.byte 0x00 "PPGC1,PPG Operation Mode Control Register 1"
|
|
bitfld.byte 0x00 7. " PIE ,PPG1 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " PUF ,PPG1 Counter Underflow" "No underflow,Underflow"
|
|
bitfld.byte 0x00 5. " INTM ,Interrupt Mode Select" "PPLH or PPLL,PPLH"
|
|
bitfld.byte 0x00 3.--4. " PCS ,PPG1 DOWN Counter Operation Clock Select" "PCLK,PCLK/4,PCLK/16,PCLK/64"
|
|
group.byte 0x205++0x00
|
|
line.byte 0x00 "PPGC2,PPG Operation Mode Control Register 2"
|
|
bitfld.byte 0x00 7. " PIE ,PPG2 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " PUF ,PPG2 Counter Underflow" "No underflow,Underflow"
|
|
bitfld.byte 0x00 5. " INTM ,Interrupt Mode Select" "PPLH or PPLL,PPLH"
|
|
bitfld.byte 0x00 3.--4. " PCS ,PPG2 DOWN Counter Operation Clock Select" "PCLK,PCLK/4,PCLK/16,PCLK/64"
|
|
bitfld.byte 0x00 1.--2. " MD ,PPG2 Operation Mode Set" "8bit,8+8bit,16bit,16+16bit"
|
|
bitfld.byte 0x00 0. " TTRG ,PPG2 start trigger select" "TRG,TGC"
|
|
group.byte 0x204++0x00
|
|
line.byte 0x00 "PPGC3,PPG Operation Mode Control Register 3"
|
|
bitfld.byte 0x00 7. " PIE ,PPG3 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " PUF ,PPG3 Counter Underflow" "No underflow,Underflow"
|
|
bitfld.byte 0x00 5. " INTM ,Interrupt Mode Select" "PPLH or PPLL,PPLH"
|
|
bitfld.byte 0x00 3.--4. " PCS ,PPG3 DOWN Counter Operation Clock Select" "PCLK,PCLK/4,PCLK/16,PCLK/64"
|
|
group.byte 0x241++0x00
|
|
line.byte 0x00 "PPGC4,PPG Operation Mode Control Register 4"
|
|
bitfld.byte 0x00 7. " PIE ,PPG4 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " PUF ,PPG4 Counter Underflow" "No underflow,Underflow"
|
|
bitfld.byte 0x00 5. " INTM ,Interrupt Mode Select" "PPLH or PPLL,PPLH"
|
|
bitfld.byte 0x00 3.--4. " PCS ,PPG4 DOWN Counter Operation Clock Select" "PCLK,PCLK/4,PCLK/16,PCLK/64"
|
|
bitfld.byte 0x00 1.--2. " MD ,PPG4 Operation Mode Set" "8bit,8+8bit,16bit,16+16bit"
|
|
bitfld.byte 0x00 0. " TTRG ,PPG4 start trigger select" "TRG,TGC"
|
|
group.byte 0x240++0x00
|
|
line.byte 0x00 "PPGC5,PPG Operation Mode Control Register 5"
|
|
bitfld.byte 0x00 7. " PIE ,PPG5 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " PUF ,PPG5 Counter Underflow" "No underflow,Underflow"
|
|
bitfld.byte 0x00 5. " INTM ,Interrupt Mode Select" "PPLH or PPLL,PPLH"
|
|
bitfld.byte 0x00 3.--4. " PCS ,PPG5 DOWN Counter Operation Clock Select" "PCLK,PCLK/4,PCLK/16,PCLK/64"
|
|
group.byte 0x245++0x00
|
|
line.byte 0x00 "PPGC6,PPG Operation Mode Control Register 6"
|
|
bitfld.byte 0x00 7. " PIE ,PPG6 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " PUF ,PPG6 Counter Underflow" "No underflow,Underflow"
|
|
bitfld.byte 0x00 5. " INTM ,Interrupt Mode Select" "PPLH or PPLL,PPLH"
|
|
bitfld.byte 0x00 3.--4. " PCS ,PPG6 DOWN Counter Operation Clock Select" "PCLK,PCLK/4,PCLK/16,PCLK/64"
|
|
bitfld.byte 0x00 1.--2. " MD ,PPG6 Operation Mode Set" "8bit,8+8bit,16bit,16+16bit"
|
|
bitfld.byte 0x00 0. " TTRG ,PPG6 start trigger select" "TRG,TGC"
|
|
group.byte 0x244++0x00
|
|
line.byte 0x00 "PPGC7,PPG Operation Mode Control Register 7"
|
|
bitfld.byte 0x00 7. " PIE ,PPG7 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " PUF ,PPG7 Counter Underflow" "No underflow,Underflow"
|
|
bitfld.byte 0x00 5. " INTM ,Interrupt Mode Select" "PPLH or PPLL,PPLH"
|
|
bitfld.byte 0x00 3.--4. " PCS ,PPG7 DOWN Counter Operation Clock Select" "PCLK,PCLK/4,PCLK/16,PCLK/64"
|
|
group.byte 0x281++0x00
|
|
line.byte 0x00 "PPGC8,PPG Operation Mode Control Register 8"
|
|
bitfld.byte 0x00 7. " PIE ,PPG8 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " PUF ,PPG8 Counter Underflow" "No underflow,Underflow"
|
|
bitfld.byte 0x00 5. " INTM ,Interrupt Mode Select" "PPLH or PPLL,PPLH"
|
|
bitfld.byte 0x00 3.--4. " PCS ,PPG8 DOWN Counter Operation Clock Select" "PCLK,PCLK/4,PCLK/16,PCLK/64"
|
|
bitfld.byte 0x00 1.--2. " MD ,PPG8 Operation Mode Set" "8bit,8+8bit,16bit,16+16bit"
|
|
bitfld.byte 0x00 0. " TTRG ,PPG8 start trigger select" "TRG,TGC"
|
|
group.byte 0x280++0x00
|
|
line.byte 0x00 "PPGC9,PPG Operation Mode Control Register 9"
|
|
bitfld.byte 0x00 7. " PIE ,PPG9 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " PUF ,PPG9 Counter Underflow" "No underflow,Underflow"
|
|
bitfld.byte 0x00 5. " INTM ,Interrupt Mode Select" "PPLH or PPLL,PPLH"
|
|
bitfld.byte 0x00 3.--4. " PCS ,PPG9 DOWN Counter Operation Clock Select" "PCLK,PCLK/4,PCLK/16,PCLK/64"
|
|
group.byte 0x285++0x00
|
|
line.byte 0x00 "PPGC10,PPG Operation Mode Control Register 10"
|
|
bitfld.byte 0x00 7. " PIE ,PPG10 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " PUF ,PPG10 Counter Underflow" "No underflow,Underflow"
|
|
bitfld.byte 0x00 5. " INTM ,Interrupt Mode Select" "PPLH or PPLL,PPLH"
|
|
bitfld.byte 0x00 3.--4. " PCS ,PPG10 DOWN Counter Operation Clock Select" "PCLK,PCLK/4,PCLK/16,PCLK/64"
|
|
bitfld.byte 0x00 1.--2. " MD ,PPG10 Operation Mode Set" "8bit,8+8bit,16bit,16+16bit"
|
|
bitfld.byte 0x00 0. " TTRG ,PPG10 start trigger select" "TRG,TGC"
|
|
group.byte 0x284++0x00
|
|
line.byte 0x00 "PPGC11,PPG Operation Mode Control Register 11"
|
|
bitfld.byte 0x00 7. " PIE ,PPG11 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " PUF ,PPG11 Counter Underflow" "No underflow,Underflow"
|
|
bitfld.byte 0x00 5. " INTM ,Interrupt Mode Select" "PPLH or PPLL,PPLH"
|
|
bitfld.byte 0x00 3.--4. " PCS ,PPG11 DOWN Counter Operation Clock Select" "PCLK,PCLK/4,PCLK/16,PCLK/64"
|
|
group.byte 0x2C1++0x00
|
|
line.byte 0x00 "PPGC12,PPG Operation Mode Control Register 12"
|
|
bitfld.byte 0x00 7. " PIE ,PPG12 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " PUF ,PPG12 Counter Underflow" "No underflow,Underflow"
|
|
bitfld.byte 0x00 5. " INTM ,Interrupt Mode Select" "PPLH or PPLL,PPLH"
|
|
bitfld.byte 0x00 3.--4. " PCS ,PPG12 DOWN Counter Operation Clock Select" "PCLK,PCLK/4,PCLK/16,PCLK/64"
|
|
bitfld.byte 0x00 1.--2. " MD ,PPG12 Operation Mode Set" "8bit,8+8bit,16bit,16+16bit"
|
|
bitfld.byte 0x00 0. " TTRG ,PPG12 start trigger select" "TRG,TGC"
|
|
group.byte 0x2C0++0x00
|
|
line.byte 0x00 "PPGC13,PPG Operation Mode Control Register 13"
|
|
bitfld.byte 0x00 7. " PIE ,PPG13 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " PUF ,PPG13 Counter Underflow" "No underflow,Underflow"
|
|
bitfld.byte 0x00 5. " INTM ,Interrupt Mode Select" "PPLH or PPLL,PPLH"
|
|
bitfld.byte 0x00 3.--4. " PCS ,PPG13 DOWN Counter Operation Clock Select" "PCLK,PCLK/4,PCLK/16,PCLK/64"
|
|
group.byte 0x2C5++0x00
|
|
line.byte 0x00 "PPGC14,PPG Operation Mode Control Register 14"
|
|
bitfld.byte 0x00 7. " PIE ,PPG14 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " PUF ,PPG14 Counter Underflow" "No underflow,Underflow"
|
|
bitfld.byte 0x00 5. " INTM ,Interrupt Mode Select" "PPLH or PPLL,PPLH"
|
|
bitfld.byte 0x00 3.--4. " PCS ,PPG14 DOWN Counter Operation Clock Select" "PCLK,PCLK/4,PCLK/16,PCLK/64"
|
|
bitfld.byte 0x00 1.--2. " MD ,PPG14 Operation Mode Set" "8bit,8+8bit,16bit,16+16bit"
|
|
bitfld.byte 0x00 0. " TTRG ,PPG14 start trigger select" "TRG,TGC"
|
|
group.byte 0x2C4++0x00
|
|
line.byte 0x00 "PPGC15,PPG Operation Mode Control Register 15"
|
|
bitfld.byte 0x00 7. " PIE ,PPG15 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " PUF ,PPG15 Counter Underflow" "No underflow,Underflow"
|
|
bitfld.byte 0x00 5. " INTM ,Interrupt Mode Select" "PPLH or PPLL,PPLH"
|
|
bitfld.byte 0x00 3.--4. " PCS ,PPG15 DOWN Counter Operation Clock Select" "PCLK,PCLK/4,PCLK/16,PCLK/64"
|
|
group.byte 0x301++0x00
|
|
line.byte 0x00 "PPGC16,PPG Operation Mode Control Register 16"
|
|
bitfld.byte 0x00 7. " PIE ,PPG16 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " PUF ,PPG16 Counter Underflow" "No underflow,Underflow"
|
|
bitfld.byte 0x00 5. " INTM ,Interrupt Mode Select" "PPLH or PPLL,PPLH"
|
|
bitfld.byte 0x00 3.--4. " PCS ,PPG16 DOWN Counter Operation Clock Select" "PCLK,PCLK/4,PCLK/16,PCLK/64"
|
|
bitfld.byte 0x00 1.--2. " MD ,PPG16 Operation Mode Set" "8bit,8+8bit,16bit,16+16bit"
|
|
bitfld.byte 0x00 0. " TTRG ,PPG16 start trigger select" "TRG,TGC"
|
|
group.byte 0x300++0x00
|
|
line.byte 0x00 "PPGC17,PPG Operation Mode Control Register 17"
|
|
bitfld.byte 0x00 7. " PIE ,PPG17 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " PUF ,PPG17 Counter Underflow" "No underflow,Underflow"
|
|
bitfld.byte 0x00 5. " INTM ,Interrupt Mode Select" "PPLH or PPLL,PPLH"
|
|
bitfld.byte 0x00 3.--4. " PCS ,PPG17 DOWN Counter Operation Clock Select" "PCLK,PCLK/4,PCLK/16,PCLK/64"
|
|
group.byte 0x305++0x00
|
|
line.byte 0x00 "PPGC18,PPG Operation Mode Control Register 18"
|
|
bitfld.byte 0x00 7. " PIE ,PPG18 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " PUF ,PPG18 Counter Underflow" "No underflow,Underflow"
|
|
bitfld.byte 0x00 5. " INTM ,Interrupt Mode Select" "PPLH or PPLL,PPLH"
|
|
bitfld.byte 0x00 3.--4. " PCS ,PPG18 DOWN Counter Operation Clock Select" "PCLK,PCLK/4,PCLK/16,PCLK/64"
|
|
bitfld.byte 0x00 1.--2. " MD ,PPG18 Operation Mode Set" "8bit,8+8bit,16bit,16+16bit"
|
|
bitfld.byte 0x00 0. " TTRG ,PPG18 start trigger select" "TRG,TGC"
|
|
group.byte 0x304++0x00
|
|
line.byte 0x00 "PPGC19,PPG Operation Mode Control Register 19"
|
|
bitfld.byte 0x00 7. " PIE ,PPG19 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " PUF ,PPG19 Counter Underflow" "No underflow,Underflow"
|
|
bitfld.byte 0x00 5. " INTM ,Interrupt Mode Select" "PPLH or PPLL,PPLH"
|
|
bitfld.byte 0x00 3.--4. " PCS ,PPG19 DOWN Counter Operation Clock Select" "PCLK,PCLK/4,PCLK/16,PCLK/64"
|
|
group.byte 0x341++0x00
|
|
line.byte 0x00 "PPGC20,PPG Operation Mode Control Register 20"
|
|
bitfld.byte 0x00 7. " PIE ,PPG20 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " PUF ,PPG20 Counter Underflow" "No underflow,Underflow"
|
|
bitfld.byte 0x00 5. " INTM ,Interrupt Mode Select" "PPLH or PPLL,PPLH"
|
|
bitfld.byte 0x00 3.--4. " PCS ,PPG20 DOWN Counter Operation Clock Select" "PCLK,PCLK/4,PCLK/16,PCLK/64"
|
|
bitfld.byte 0x00 1.--2. " MD ,PPG20 Operation Mode Set" "8bit,8+8bit,16bit,16+16bit"
|
|
bitfld.byte 0x00 0. " TTRG ,PPG20 start trigger select" "TRG,TGC"
|
|
group.byte 0x340++0x00
|
|
line.byte 0x00 "PPGC21,PPG Operation Mode Control Register 21"
|
|
bitfld.byte 0x00 7. " PIE ,PPG21 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " PUF ,PPG21 Counter Underflow" "No underflow,Underflow"
|
|
bitfld.byte 0x00 5. " INTM ,Interrupt Mode Select" "PPLH or PPLL,PPLH"
|
|
bitfld.byte 0x00 3.--4. " PCS ,PPG21 DOWN Counter Operation Clock Select" "PCLK,PCLK/4,PCLK/16,PCLK/64"
|
|
group.byte 0x345++0x00
|
|
line.byte 0x00 "PPGC22,PPG Operation Mode Control Register 22"
|
|
bitfld.byte 0x00 7. " PIE ,PPG22 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " PUF ,PPG22 Counter Underflow" "No underflow,Underflow"
|
|
bitfld.byte 0x00 5. " INTM ,Interrupt Mode Select" "PPLH or PPLL,PPLH"
|
|
bitfld.byte 0x00 3.--4. " PCS ,PPG22 DOWN Counter Operation Clock Select" "PCLK,PCLK/4,PCLK/16,PCLK/64"
|
|
bitfld.byte 0x00 1.--2. " MD ,PPG22 Operation Mode Set" "8bit,8+8bit,16bit,16+16bit"
|
|
bitfld.byte 0x00 0. " TTRG ,PPG22 start trigger select" "TRG,TGC"
|
|
group.byte 0x344++0x00
|
|
line.byte 0x00 "PPGC23,PPG Operation Mode Control Register 23"
|
|
bitfld.byte 0x00 7. " PIE ,PPG23 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " PUF ,PPG23 Counter Underflow" "No underflow,Underflow"
|
|
bitfld.byte 0x00 5. " INTM ,Interrupt Mode Select" "PPLH or PPLL,PPLH"
|
|
bitfld.byte 0x00 3.--4. " PCS ,PPG23 DOWN Counter Operation Clock Select" "PCLK,PCLK/4,PCLK/16,PCLK/64"
|
|
group.byte 0x208++0x01
|
|
line.byte 0x00 "PRLL0,PPG0 Reload Level-LOW Register"
|
|
line.byte 0x01 "PRLH0,PPG0 Reload Level-HIGH Register"
|
|
group.byte 0x20C++0x01
|
|
line.byte 0x00 "PRLL1,PPG1 Reload Level-LOW Register"
|
|
line.byte 0x01 "PRLH1,PPG1 Reload Level-HIGH Register"
|
|
group.byte 0x210++0x01
|
|
line.byte 0x00 "PRLL2,PPG2 Reload Level-LOW Register"
|
|
line.byte 0x01 "PRLH2,PPG2 Reload Level-HIGH Register"
|
|
group.byte 0x214++0x01
|
|
line.byte 0x00 "PRLL3,PPG3 Reload Level-LOW Register"
|
|
line.byte 0x01 "PRLH3,PPG3 Reload Level-HIGH Register"
|
|
group.byte 0x248++0x01
|
|
line.byte 0x00 "PRLL4,PPG4 Reload Level-LOW Register"
|
|
line.byte 0x01 "PRLH4,PPG4 Reload Level-HIGH Register"
|
|
group.byte 0x24C++0x01
|
|
line.byte 0x00 "PRLL5,PPG5 Reload Level-LOW Register"
|
|
line.byte 0x01 "PRLH5,PPG5 Reload Level-HIGH Register"
|
|
group.byte 0x250++0x01
|
|
line.byte 0x00 "PRLL6,PPG6 Reload Level-LOW Register"
|
|
line.byte 0x01 "PRLH6,PPG6 Reload Level-HIGH Register"
|
|
group.byte 0x254++0x01
|
|
line.byte 0x00 "PRLL7,PPG7 Reload Level-LOW Register"
|
|
line.byte 0x01 "PRLH7,PPG7 Reload Level-HIGH Register"
|
|
group.byte 0x288++0x01
|
|
line.byte 0x00 "PRLL8,PPG8 Reload Level-LOW Register"
|
|
line.byte 0x01 "PRLH8,PPG8 Reload Level-HIGH Register"
|
|
group.byte 0x28C++0x01
|
|
line.byte 0x00 "PRLL9,PPG9 Reload Level-LOW Register"
|
|
line.byte 0x01 "PRLH9,PPG9 Reload Level-HIGH Register"
|
|
group.byte 0x290++0x01
|
|
line.byte 0x00 "PRLL10,PPG10 Reload Level-LOW Register"
|
|
line.byte 0x01 "PRLH10,PPG10 Reload Level-HIGH Register"
|
|
group.byte 0x294++0x01
|
|
line.byte 0x00 "PRLL11,PPG11 Reload Level-LOW Register"
|
|
line.byte 0x01 "PRLH11,PPG11 Reload Level-HIGH Register"
|
|
group.byte 0x2C8++0x01
|
|
line.byte 0x00 "PRLL12,PPG12 Reload Level-LOW Register"
|
|
line.byte 0x01 "PRLH12,PPG12 Reload Level-HIGH Register"
|
|
group.byte 0x2CC++0x01
|
|
line.byte 0x00 "PRLL13,PPG13 Reload Level-LOW Register"
|
|
line.byte 0x01 "PRLH13,PPG13 Reload Level-HIGH Register"
|
|
group.byte 0x2D0++0x01
|
|
line.byte 0x00 "PRLL14,PPG14 Reload Level-LOW Register"
|
|
line.byte 0x01 "PRLH14,PPG14 Reload Level-HIGH Register"
|
|
group.byte 0x2D4++0x01
|
|
line.byte 0x00 "PRLL15,PPG15 Reload Level-LOW Register"
|
|
line.byte 0x01 "PRLH15,PPG15 Reload Level-HIGH Register"
|
|
group.byte 0x308++0x01
|
|
line.byte 0x00 "PRLL16,PPG16 Reload Level-LOW Register"
|
|
line.byte 0x01 "PRLH16,PPG16 Reload Level-HIGH Register"
|
|
group.byte 0x30C++0x01
|
|
line.byte 0x00 "PRLL17,PPG17 Reload Level-LOW Register"
|
|
line.byte 0x01 "PRLH17,PPG17 Reload Level-HIGH Register"
|
|
group.byte 0x310++0x01
|
|
line.byte 0x00 "PRLL18,PPG18 Reload Level-LOW Register"
|
|
line.byte 0x01 "PRLH18,PPG18 Reload Level-HIGH Register"
|
|
group.byte 0x314++0x01
|
|
line.byte 0x00 "PRLL19,PPG19 Reload Level-LOW Register"
|
|
line.byte 0x01 "PRLH19,PPG19 Reload Level-HIGH Register"
|
|
group.byte 0x348++0x01
|
|
line.byte 0x00 "PRLL20,PPG20 Reload Level-LOW Register"
|
|
line.byte 0x01 "PRLH20,PPG20 Reload Level-HIGH Register"
|
|
group.byte 0x34C++0x01
|
|
line.byte 0x00 "PRLL21,PPG21 Reload Level-LOW Register"
|
|
line.byte 0x01 "PRLH21,PPG21 Reload Level-HIGH Register"
|
|
group.byte 0x350++0x01
|
|
line.byte 0x00 "PRLL22,PPG22 Reload Level-LOW Register"
|
|
line.byte 0x01 "PRLH22,PPG22 Reload Level-HIGH Register"
|
|
group.byte 0x354++0x01
|
|
line.byte 0x00 "PRLL23,PPG23 Reload Level-LOW Register"
|
|
line.byte 0x01 "PRLH23,PPG23 Reload Level-HIGH Register"
|
|
group.byte 0x218++0x00
|
|
line.byte 0x00 "GATEC0,PPG0,PPG2 Gate Function Control Register"
|
|
bitfld.byte 0x00 5. " STRG2 ,Select trigger signal for PPG2" "TRG,GATE"
|
|
bitfld.byte 0x00 4. " EDGE2 ,Start Effective Level Select for GATE2" "High,Low"
|
|
bitfld.byte 0x00 1. " STRG0 ,Select trigger signal for PPG0" "TRG,GATE"
|
|
bitfld.byte 0x00 0. " EDGE0 ,Start Effective Level Select for GATE0" "High,Low"
|
|
group.byte 0x258++0x00
|
|
line.byte 0x00 "GATEC4,PPG4,PPG6 Gate Function Control Register"
|
|
bitfld.byte 0x00 5. " STRG6 ,Select trigger signal for PPG6" "TRG,GATE"
|
|
bitfld.byte 0x00 4. " EDGE6 ,Start Effective Level Select for GATE6" "High,Low"
|
|
bitfld.byte 0x00 1. " STRG4 ,Select trigger signal for PPG4" "TRG,GATE"
|
|
bitfld.byte 0x00 0. " EDGE4 ,Start Effective Level Select for GATE4" "High,Low"
|
|
group.byte 0x298++0x00
|
|
line.byte 0x00 "GATEC8,PPG8,PPG10 Gate Function Control Register"
|
|
bitfld.byte 0x00 5. " STRG10 ,Select trigger signal for PPG10" "TRG,GATE"
|
|
bitfld.byte 0x00 4. " EDGE10 ,Start Effective Level Select for GATE10" "High,Low"
|
|
bitfld.byte 0x00 1. " STRG8 ,Select trigger signal for PPG8" "TRG,GATE"
|
|
bitfld.byte 0x00 0. " EDGE8 ,Start Effective Level Select for GATE8" "High,Low"
|
|
group.byte 0x2D8++0x00
|
|
line.byte 0x00 "GATEC12,PPG12,PPG14 Gate Function Control Register"
|
|
bitfld.byte 0x00 5. " STRG14 ,Select trigger signal for PPG14" "TRG,GATE"
|
|
bitfld.byte 0x00 4. " EDGE14 ,Start Effective Level Select for GATE14" "High,Low"
|
|
bitfld.byte 0x00 1. " STRG12 ,Select trigger signal for PPG12" "TRG,GATE"
|
|
bitfld.byte 0x00 0. " EDGE12 ,Start Effective Level Select for GATE12" "High,Low"
|
|
group.byte 0x318++0x00
|
|
line.byte 0x00 "GATEC16,PPG16,PPG18 Gate Function Control Register"
|
|
bitfld.byte 0x00 5. " STRG18 ,Select trigger signal for PPG18" "TRG,GATE"
|
|
bitfld.byte 0x00 4. " EDGE18 ,Start Effective Level Select for GATE18" "High,Low"
|
|
bitfld.byte 0x00 1. " STRG16 ,Select trigger signal for PPG16" "TRG,GATE"
|
|
bitfld.byte 0x00 0. " EDGE16 ,Start Effective Level Select for GATE16" "High,Low"
|
|
group.byte 0x358++0x00
|
|
line.byte 0x00 "GATEC20,PPG20,PPG22 Gate Function Control Register"
|
|
bitfld.byte 0x00 5. " STRG22 ,Select trigger signal for PPG22" "TRG,GATE"
|
|
bitfld.byte 0x00 4. " EDGE22 ,Start Effective Level Select for GATE22" "High,Low"
|
|
bitfld.byte 0x00 1. " STRG20 ,Select trigger signal for PPG20" "TRG,GATE"
|
|
bitfld.byte 0x00 0. " EDGE20 ,Start Effective Level Select for GATE20" "High,Low"
|
|
group.byte 0x380++0x00
|
|
line.byte 0x00 "IGBTC,IGBT Mode Control Register"
|
|
bitfld.byte 0x00 7. " IGATIH ,Stop prohibition mode selection in output active bit" "Normal,Prohibition"
|
|
bitfld.byte 0x00 4.--6. " IGNFW ,Noise filter width selection bit" "Disabled,4 PCLK,8 PCLK,16 PCLK,32 PCLK,?..."
|
|
bitfld.byte 0x00 3. " IGOSEL1 ,IGBT1 output level selection bit" "Normal,Inverted"
|
|
bitfld.byte 0x00 2. " IGOSEL0 ,IGBT0 output level selection bit" "Normal,Inverted"
|
|
bitfld.byte 0x00 1. " IGTRGLV ,Trigger input level selection bit" "Normal,Inverted"
|
|
bitfld.byte 0x00 0. " IGBTMD ,IGBT mode selection bit" "Normal,IGBT"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
sif !cpuis("S6E1C*")
|
|
tree "QPRC (Quadrature Position/Revolution Counter)"
|
|
base ad:0x40026000
|
|
width 9.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "QPCR,Quad Position and Revolution Counter Position Count Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "QRCR,QPRC Revolution Count Register"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "QPCCR,QPRC Position Counter Compare Register"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "QPRCR,QPRC Position and Revolution Counter Compare Register"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "QCRL,Low-Order Bytes of QPRC Control Register"
|
|
bitfld.byte 0x00 7. " SWAP ,Swap of the AIN/BIN" "Not swapped,Swapped"
|
|
bitfld.byte 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution"
|
|
bitfld.byte 0x00 5. " CGSC ,Count clear or gate selection bit" "Counter clear,Gate"
|
|
bitfld.byte 0x00 4. " PSTP ,Position counter stop bit" "No stop,Stop"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " RCM ,Revolution counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3"
|
|
bitfld.byte 0x00 0.--1. " PCM ,Position counter mode bits" "PC_Mode0,PC_Mode1,PC_Mode2,PC_Mode3"
|
|
if (((d.w(ad:0x40026000+0x18))&0x23)==0x20)||(((d.w(ad:0x40026000+0x18))&0x23)==0x23)
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "QCRH,High-Order Bytes of QPRC Control Register"
|
|
bitfld.byte 0x00 6.--7. " CGE ,Detection edge selection bits" "Disabled,Level L,Level H,Disabled"
|
|
bitfld.byte 0x00 4.--5. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling"
|
|
bitfld.byte 0x00 2.--3. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling"
|
|
bitfld.byte 0x00 0.--1. " PCRM ,Position counter reset mask bits" "No reset,Twice,Four,Eight"
|
|
else
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "QCRH,High-Order Bytes of QPRC Control Register"
|
|
bitfld.byte 0x00 6.--7. " CGE ,Detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling"
|
|
bitfld.byte 0x00 4.--5. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling"
|
|
bitfld.byte 0x00 2.--3. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "QECR,QPRC Extension Control Register"
|
|
bitfld.word 0x00 2. " ORNGIE ,Outrange interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " ORNGF ,Outrange interrupt request flag bit" "Not detected,Detected"
|
|
bitfld.word 0x00 0. " ORNGMD ,Outrange mode selection bit" "Positive number,8K value"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "QICRL,Low-Order Bytes of QPRC Interrupt Control Register"
|
|
bitfld.byte 0x00 7. " ZIIF ,Zero index interrupt request flag bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 6. " OFDF ,Overflow interrupt request flag bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 5. " UFDF ,Underflow interrupt request flag bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 4. " OUZIE ,Overflow, underflow, or zero index interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " QPRCMF ,PC and RC match interrupt request flag bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 2. " QPRCMIE ,PC and RC match interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " QPCMF ,PC match interrupt request flag bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 0. " QPCMIE ,PC match interrupt enable bit" "Disabled,Enabled"
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "QICRH,High-Order Bytes of QPRC Interrupt Control Register"
|
|
bitfld.byte 0x00 5. " QPCNRCMF ,PC match and RC match interrupt request flag bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 4. " QPCNRCMIE ,PC match and RC match interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 3. " DIROU ,Last position counter flow direction bit" "Incremented,Decremented"
|
|
rbitfld.byte 0x00 2. " DIRPC ,Last position counter direction bit" "Incremented,Decremented"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " CDCF ,Count inversion interrupt request flag bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 0. " CDCIE ,Count inversion interrupt enable bit" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "QMPR,QPRC Maximum Position Register"
|
|
group.word 0x100++0x01
|
|
line.word 0x00 "NFCTLA,AIN Noise Control Register"
|
|
bitfld.word 0x00 5. " AINMD ,Mask bit" "Not masked,Masked"
|
|
bitfld.word 0x00 4. " AINLV ,Input invert bit" "Not inverted,Inverted"
|
|
bitfld.word 0x00 0.--2. " AINNWS ,Noise filter width select bits (PCLK cycles)" "No filter,4 cycles,8 cycles,16 cycles,32 cycles,64 cycles,128 cycles,256 cycles"
|
|
group.word 0x104++0x01
|
|
line.word 0x00 "NFCTLB,BIN Noise Control Register"
|
|
bitfld.word 0x00 5. " BINMD ,Mask bit" "Not masked,Masked"
|
|
bitfld.word 0x00 4. " BINLV ,Input invert bit" "Not inverted,Inverted"
|
|
bitfld.word 0x00 0.--2. " BINNWS ,Noise filter width select bits (PCLK cycles)" "No filter,4 cycles,8 cycles,16 cycles,32 cycles,64 cycles,128 cycles,256 cycles"
|
|
group.word 0x108++0x01
|
|
line.word 0x00 "NFRCTLZ,ZIN Noise Control Register"
|
|
bitfld.word 0x00 5. " ZINMD ,Mask bit" "Not masked,Masked"
|
|
bitfld.word 0x00 4. " ZINLV ,Input invert bit" "Not inverted,Inverted"
|
|
bitfld.word 0x00 0.--2. " ZINNWS ,Noise filter width select bits (PCLK cycles)" "No filter,4 cycles,8 cycles,16 cycles,32 cycles,64 cycles,128 cycles,256 cycles"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree "ADC (12-bit A/D Converter)"
|
|
tree "Unit 0"
|
|
base ad:0x40027000
|
|
width 9.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "ADCR,A/D Control Register"
|
|
bitfld.byte 0x00 7. " SCIF ,Scan conversion interrupt request bit (Read/Write)" "Not requested/Cleared,No effect"
|
|
bitfld.byte 0x00 6. " PCIF ,Priority conversion interrupt request bit (Read/Write)" "Not requested/Cleared,No effect"
|
|
bitfld.byte 0x00 5. " CMPIF ,Conversion result comparison interrupt request bit (Read/Write)" "Not requested/Cleared,No effect"
|
|
bitfld.byte 0x00 3. " SCIE ,Scan conversion interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " PCIE ,Priority conversion interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " CMPIE ,Conversion result comparison interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " OVRIE ,FIFO overrun interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "ADSR,A/D Status Register"
|
|
bitfld.byte 0x00 7. " ADSTP ,A/D conversion forced stop bit" "No effect,Stopped"
|
|
bitfld.byte 0x00 6. " FDAS ,FIFO data placement selection bit" "MSB,LSB"
|
|
rbitfld.byte 0x00 2. " PCNS ,Priority conversion pending flag" "Not pending,Pending"
|
|
rbitfld.byte 0x00 1. " PCS ,Priority conversion status flag" "Stopped,In progress"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " SCS ,Scan conversion status flag" "Stopped,In progress"
|
|
group.byte 0x09++0x00
|
|
line.byte 0x00 "SCCR,Scan Conversion Control Register"
|
|
rbitfld.byte 0x00 7. " SEMP ,Scan conversion FIFO empty bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 6. " SFUL ,Scan conversion FIFO full bit" "Not full,Full"
|
|
bitfld.byte 0x00 5. " SOVR ,Scan conversion overrun flag" "No overrun/Cleared,Overrun/No effect"
|
|
bitfld.byte 0x00 4. " SFCLR ,Scan conversion FIFO clear bit" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RPT ,Scan conversion repeat bit" "Single,Repeat"
|
|
bitfld.byte 0x00 1. " SHEN ,Scan conversion timer start enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " SSTR ,Scan conversion start bit" "No effect,Started"
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "SFNS,Scan Conversion FIFO Stage Count Setup Register"
|
|
bitfld.byte 0x00 0.--3. " SFS ,Scan conversion FIFO stage count setting bit" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SCFD,Scan Conversion FIFO Data Register"
|
|
bitfld.long 0x00 31. " SD_11 ,Scan conversion result bit [11]" "Low,High"
|
|
bitfld.long 0x00 30. " SD_10 ,Scan conversion result bit [10]" "Low,High"
|
|
bitfld.long 0x00 29. " SD_9 ,Scan conversion result bit [9]" "Low,High"
|
|
bitfld.long 0x00 28. " SD_8 ,Scan conversion result bit [8]" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SD_7 ,Scan conversion result bit [7]" "Low,High"
|
|
bitfld.long 0x00 26. " SD_6 ,Scan conversion result bit [6]" "Low,High"
|
|
bitfld.long 0x00 25. " SD_5 ,Scan conversion result bit [5]" "Low,High"
|
|
bitfld.long 0x00 24. " SD_4 ,Scan conversion result bit [4]" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SD_3 ,Scan conversion result bit [3]" "Low,High"
|
|
bitfld.long 0x00 22. " SD_2 ,Scan conversion result bit [2]" "Low,High"
|
|
bitfld.long 0x00 21. " SD_1 ,Scan conversion result bit [1]" "Low,High"
|
|
bitfld.long 0x00 20. " SD_0 ,Scan conversion result bit [0]" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " INVL ,A/D conversion result disable bit" "Valid,Invalid"
|
|
bitfld.long 0x00 8.--9. " RS ,Conversion start factor" ",Software,Timer,"
|
|
bitfld.long 0x00 0.--4. " SC ,Conversion input channel bits [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (per.b(ad:0x40027000)&0x3)==0x0
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "SCIS3,Scan Conversion Input Selection Register 3"
|
|
bitfld.byte 0x00 7. " AN_31 ,Analog input selection bit [31]" "Low,High"
|
|
bitfld.byte 0x00 6. " AN_30 ,Analog input selection bit [30]" "Low,High"
|
|
bitfld.byte 0x00 5. " AN_29 ,Analog input selection bit [29]" "Low,High"
|
|
bitfld.byte 0x00 4. " AN_28 ,Analog input selection bit [28]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " AN_27 ,Analog input selection bit [27]" "Low,High"
|
|
bitfld.byte 0x00 2. " AN_26 ,Analog input selection bit [26]" "Low,High"
|
|
bitfld.byte 0x00 1. " AN_25 ,Analog input selection bit [25]" "Low,High"
|
|
bitfld.byte 0x00 0. " AN_24 ,Analog input selection bit [24]" "Low,High"
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "SCIS2,Scan Conversion Input Selection Register 2"
|
|
bitfld.byte 0x00 7. " AN_23 ,Analog input selection bit [23]" "Low,High"
|
|
bitfld.byte 0x00 6. " AN_22 ,Analog input selection bit [22]" "Low,High"
|
|
bitfld.byte 0x00 5. " AN_21 ,Analog input selection bit [21]" "Low,High"
|
|
bitfld.byte 0x00 4. " AN_20 ,Analog input selection bit [20]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " AN_19 ,Analog input selection bit [19]" "Low,High"
|
|
bitfld.byte 0x00 2. " AN_18 ,Analog input selection bit [18]" "Low,High"
|
|
bitfld.byte 0x00 1. " AN_17 ,Analog input selection bit [17]" "Low,High"
|
|
bitfld.byte 0x00 0. " AN_16 ,Analog input selection bit [16]" "Low,High"
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "SCIS1,Scan Conversion Input Selection Register 1"
|
|
bitfld.byte 0x00 7. " AN_15 ,Analog input selection bit [15]" "Low,High"
|
|
bitfld.byte 0x00 6. " AN_14 ,Analog input selection bit [14]" "Low,High"
|
|
bitfld.byte 0x00 5. " AN_13 ,Analog input selection bit [13]" "Low,High"
|
|
bitfld.byte 0x00 4. " AN_12 ,Analog input selection bit [12]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " AN_11 ,Analog input selection bit [11]" "Low,High"
|
|
bitfld.byte 0x00 2. " AN_10 ,Analog input selection bit [10]" "Low,High"
|
|
bitfld.byte 0x00 1. " AN_9 ,Analog input selection bit [9]" "Low,High"
|
|
bitfld.byte 0x00 0. " AN_8 ,Analog input selection bit [8]" "Low,High"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "SCIS0,Scan Conversion Input Selection Register 0"
|
|
bitfld.byte 0x00 7. " AN_7 ,Analog input selection bit [7]" "Low,High"
|
|
bitfld.byte 0x00 6. " AN_6 ,Analog input selection bit [6]" "Low,High"
|
|
bitfld.byte 0x00 5. " AN_5 ,Analog input selection bit [5]" "Low,High"
|
|
bitfld.byte 0x00 4. " AN_4 ,Analog input selection bit [4]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " AN_3 ,Analog input selection bit [3]" "Low,High"
|
|
bitfld.byte 0x00 2. " AN_2 ,Analog input selection bit [2]" "Low,High"
|
|
bitfld.byte 0x00 1. " AN_1 ,Analog input selection bit [1]" "Low,High"
|
|
bitfld.byte 0x00 0. " AN_0 ,Analog input selection bit [0]" "Low,High"
|
|
else
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "SCIS3,Scan Conversion Input Selection Register 3"
|
|
bitfld.byte 0x00 7. " AN_31 ,Analog input selection bit [31]" "Low,High"
|
|
bitfld.byte 0x00 6. " AN_30 ,Analog input selection bit [30]" "Low,High"
|
|
bitfld.byte 0x00 5. " AN_29 ,Analog input selection bit [29]" "Low,High"
|
|
bitfld.byte 0x00 4. " AN_28 ,Analog input selection bit [28]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " AN_27 ,Analog input selection bit [27]" "Low,High"
|
|
bitfld.byte 0x00 2. " AN_26 ,Analog input selection bit [26]" "Low,High"
|
|
bitfld.byte 0x00 1. " AN_25 ,Analog input selection bit [25]" "Low,High"
|
|
bitfld.byte 0x00 0. " AN_24 ,Analog input selection bit [24]" "Low,High"
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "SCIS2,Scan Conversion Input Selection Register 2"
|
|
bitfld.byte 0x00 7. " AN_23 ,Analog input selection bit [23]" "Low,High"
|
|
bitfld.byte 0x00 6. " AN_22 ,Analog input selection bit [22]" "Low,High"
|
|
bitfld.byte 0x00 5. " AN_21 ,Analog input selection bit [21]" "Low,High"
|
|
bitfld.byte 0x00 4. " AN_20 ,Analog input selection bit [20]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " AN_19 ,Analog input selection bit [19]" "Low,High"
|
|
bitfld.byte 0x00 2. " AN_18 ,Analog input selection bit [18]" "Low,High"
|
|
bitfld.byte 0x00 1. " AN_17 ,Analog input selection bit [17]" "Low,High"
|
|
bitfld.byte 0x00 0. " AN_16 ,Analog input selection bit [16]" "Low,High"
|
|
rgroup.byte 0x15++0x00
|
|
line.byte 0x00 "SCIS1,Scan Conversion Input Selection Register 1"
|
|
bitfld.byte 0x00 7. " AN_15 ,Analog input selection bit [15]" "Low,High"
|
|
bitfld.byte 0x00 6. " AN_14 ,Analog input selection bit [14]" "Low,High"
|
|
bitfld.byte 0x00 5. " AN_13 ,Analog input selection bit [13]" "Low,High"
|
|
bitfld.byte 0x00 4. " AN_12 ,Analog input selection bit [12]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " AN_11 ,Analog input selection bit [11]" "Low,High"
|
|
bitfld.byte 0x00 2. " AN_10 ,Analog input selection bit [10]" "Low,High"
|
|
bitfld.byte 0x00 1. " AN_9 ,Analog input selection bit [9]" "Low,High"
|
|
bitfld.byte 0x00 0. " AN_8 ,Analog input selection bit [8]" "Low,High"
|
|
rgroup.byte 0x14++0x00
|
|
line.byte 0x00 "SCIS0,Scan Conversion Input Selection Register 0"
|
|
bitfld.byte 0x00 7. " AN_7 ,Analog input selection bit [7]" "Low,High"
|
|
bitfld.byte 0x00 6. " AN_6 ,Analog input selection bit [6]" "Low,High"
|
|
bitfld.byte 0x00 5. " AN_5 ,Analog input selection bit [5]" "Low,High"
|
|
bitfld.byte 0x00 4. " AN_4 ,Analog input selection bit [4]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " AN_3 ,Analog input selection bit [3]" "Low,High"
|
|
bitfld.byte 0x00 2. " AN_2 ,Analog input selection bit [2]" "Low,High"
|
|
bitfld.byte 0x00 1. " AN_1 ,Analog input selection bit [1]" "Low,High"
|
|
bitfld.byte 0x00 0. " AN_0 ,Analog input selection bit [0]" "Low,High"
|
|
endif
|
|
if (per.b(ad:0x40027000)&0x3)==0x0
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "PCCR,Priority Conversion Control Register"
|
|
rbitfld.byte 0x00 7. " PEMP ,Priority conversion FIFO empty bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 6. " PFUL ,Priority conversion FIFO full bit" "Not full,Full"
|
|
bitfld.byte 0x00 5. " POVR ,Priority conversion overrun flag (Read/Write)" "No overrun/Cleared,Overrun/No effect"
|
|
bitfld.byte 0x00 4. " PFCLR ,Priority conversion FIFO clear bit" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ESCE ,External trigger analog input selection bit" "P1A,External"
|
|
bitfld.byte 0x00 2. " PEEN ,Priority conversion external start enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " PHEN ,Priority conversion timer start enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " PSTR ,Priority conversion start bit" "No effect,Started"
|
|
else
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "PCCR,Priority Conversion Control Register"
|
|
rbitfld.byte 0x00 7. " PEMP ,Priority conversion FIFO empty bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 6. " PFUL ,Priority conversion FIFO full bit" "Not full,Full"
|
|
bitfld.byte 0x00 5. " POVR ,Priority conversion overrun flag (Read/Write)" "No overrun/Cleared,Overrun/No effect"
|
|
bitfld.byte 0x00 4. " PFCLR ,Priority conversion FIFO clear bit" "No effect,Cleared"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ESCE ,External trigger analog input selection bit" "P1A,External"
|
|
bitfld.byte 0x00 2. " PEEN ,Priority conversion external start enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " PHEN ,Priority conversion timer start enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " PSTR ,Priority conversion start bit" "No effect,Started"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "PFNS,Priority Conversion FIFO Stage Count Setup Register"
|
|
rbitfld.byte 0x00 4.--5. " TEST ,Test bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--1. " PFS ,Priority conversion FIFO stage count setting bits" "1st,2nd,3rd,4th"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "PCFD,Priority Conversion FIFO Data Register"
|
|
bitfld.long 0x00 31. " PD_11 ,Priority conversion result bit [11]" "Low,High"
|
|
bitfld.long 0x00 30. " PD_10 ,Priority conversion result bit [10]" "Low,High"
|
|
bitfld.long 0x00 29. " PD_9 ,Priority conversion result bit [9]" "Low,High"
|
|
bitfld.long 0x00 28. " PD_8 ,Priority conversion result bit [8]" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PD_7 ,Priority conversion result bit [7]" "Low,High"
|
|
bitfld.long 0x00 26. " PD_6 ,Priority conversion result bit [6]" "Low,High"
|
|
bitfld.long 0x00 25. " PD_5 ,Priority conversion result bit [5]" "Low,High"
|
|
bitfld.long 0x00 24. " PD_4 ,Priority conversion result bit [4]" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PD_3 ,Priority conversion result bit [3]" "Low,High"
|
|
bitfld.long 0x00 22. " PD_2 ,Priority conversion result bit [2]" "Low,High"
|
|
bitfld.long 0x00 21. " PD_1 ,Priority conversion result bit [1]" "Low,High"
|
|
bitfld.long 0x00 20. " PD_0 ,Priority conversion result bit [0]" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " INVL ,A/D conversion result disable bit" "Valid,Invalid"
|
|
bitfld.long 0x00 8.--10. " RS ,Conversion start factor" ",Software,Timer,,External,,,"
|
|
bitfld.long 0x00 0.--4. " PC ,Conversion input channel bits [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (per.b(ad:0x40027000)&0x3)==0x0
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "PCIS,Priority Conversion Input Selection Register"
|
|
sif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C12*")||cpuis("S6E1C32*")
|
|
bitfld.byte 0x00 3.--7. " P2A ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,?..."
|
|
elif cpuis("S6E1A11B")||cpuis("S6E1A12B")
|
|
bitfld.byte 0x00 3.--7. " P2A ,Priority level 2 analog input selection" "0,1,2,3,4,?..."
|
|
elif cpuis("S6E1C11*")||cpuis("S6E1C31*")
|
|
bitfld.byte 0x00 3.--7. " P2A ,Priority level 2 analog input selection" "0,1,2,3,4,5,?..."
|
|
endif
|
|
bitfld.byte 0x00 0.--2. " P1A ,Priority level 1 analog input selection" "0,1,2,3,4,5,6,7"
|
|
else
|
|
rgroup.byte 0x20++0x00
|
|
line.byte 0x00 "PCIS,Priority Conversion Input Selection Register"
|
|
sif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C12*")||cpuis("S6E1C32*")
|
|
bitfld.byte 0x00 3.--7. " P2A ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,?..."
|
|
elif cpuis("S6E1A11B")||cpuis("S6E1A12B")
|
|
bitfld.byte 0x00 3.--7. " P2A ,Priority level 2 analog input selection" "0,1,2,3,4,?..."
|
|
elif cpuis("S6E1C11*")||cpuis("S6E1C31*")
|
|
bitfld.byte 0x00 3.--7. " P2A ,Priority level 2 analog input selection" "0,1,2,3,4,5,?..."
|
|
endif
|
|
bitfld.byte 0x00 0.--2. " P1A ,Priority level 1 analog input selection" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
group.word 0x26++0x01
|
|
line.word 0x00 "CMPD,A/D Comparison Value Setup Register"
|
|
bitfld.word 0x00 15. " CMAD_11 ,A/D conversion result value setting bit [11]" "Low,High"
|
|
bitfld.word 0x00 14. " CMAD_10 ,A/D conversion result value setting bit [10]" "Low,High"
|
|
bitfld.word 0x00 13. " CMAD_9 ,A/D conversion result value setting bit [9]" "Low,High"
|
|
bitfld.word 0x00 12. " CMAD_8 ,A/D conversion result value setting bit [8]" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CMAD_7 ,A/D conversion result value setting bit [7]" "Low,High"
|
|
bitfld.word 0x00 10. " CMAD_6 ,A/D conversion result value setting bit [6]" "Low,High"
|
|
bitfld.word 0x00 9. " CMAD_5 ,A/D conversion result value setting bit [5]" "Low,High"
|
|
bitfld.word 0x00 8. " CMAD_4 ,A/D conversion result value setting bit [4]" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CMAD_3 ,A/D conversion result value setting bit [3]" "Low,High"
|
|
bitfld.word 0x00 6. " CMAD_2 ,A/D conversion result value setting bit [2]" "Low,High"
|
|
if (per.b(ad:0x40027000)&0x3)==0x0
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "CMPCR,A/D Comparison Control Register"
|
|
bitfld.byte 0x00 7. " CMPEN ,Conversion result comparison function operation" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CMD_1 ,Comparison mode 1" "<CMPD,>=CMPD"
|
|
bitfld.byte 0x00 5. " CMD_0 ,Comparison mode 0" "CCH,All"
|
|
sif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C12*")||cpuis("S6E1C32*")
|
|
bitfld.byte 0x00 0.--4. " CCH ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,?..."
|
|
elif cpuis("S6E1A11B")||cpuis("S6E1A12B")
|
|
bitfld.byte 0x00 0.--4. " CCH ,Comparison target analog input channel" "0,1,2,3,4,?..."
|
|
elif cpuis("S6E1C11*")||cpuis("S6E1C31*")
|
|
bitfld.byte 0x00 0.--4. " CCH ,Comparison target analog input channel" "0,1,2,3,4,5,?..."
|
|
endif
|
|
else
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "CMPCR,A/D Comparison Control Register"
|
|
bitfld.byte 0x00 7. " CMPEN ,Conversion result comparison function operation" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " CMD_1 ,Comparison mode 1" "<CMPD,>=CMPD"
|
|
bitfld.byte 0x00 5. " CMD_0 ,Comparison mode 0" "CCH,All"
|
|
sif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C12*")||cpuis("S6E1C32*")
|
|
bitfld.byte 0x00 0.--4. " CCH ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,?..."
|
|
elif cpuis("S6E1A11B")||cpuis("S6E1A12B")
|
|
bitfld.byte 0x00 0.--4. " CCH ,Comparison target analog input channel" "0,1,2,3,4,?..."
|
|
elif cpuis("S6E1C11*")||cpuis("S6E1C31*")
|
|
bitfld.byte 0x00 0.--4. " CCH ,Comparison target analog input channel" "0,1,2,3,4,5,?..."
|
|
endif
|
|
endif
|
|
if (per.b(ad:0x40027000)&0x3)==0x0
|
|
sif !(cpuis("S6E1A11B")||cpuis("S6E1A12B")||cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C12*")||cpuis("S6E1C32*")||cpuis("S6E1C11*")||cpuis("S6E1C31*"))
|
|
group.byte 0x29++0x00
|
|
line.byte 0x00 "ADSS3,Sampling Time Selection Register 3"
|
|
bitfld.byte 0x00 7. " TS_31 ,Sampling time selection bit [31]" "Low,High"
|
|
bitfld.byte 0x00 6. " TS_30 ,Sampling time selection bit [30]" "Low,High"
|
|
bitfld.byte 0x00 5. " TS_29 ,Sampling time selection bit [29]" "Low,High"
|
|
bitfld.byte 0x00 4. " TS_28 ,Sampling time selection bit [28]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_27 ,Sampling time selection bit [27]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_26 ,Sampling time selection bit [26]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_25 ,Sampling time selection bit [25]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_24 ,Sampling time selection bit [24]" "Low,High"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "ADSS2,Sampling Time Selection Register 2"
|
|
bitfld.byte 0x00 7. " TS_23 ,Sampling time selection bit [23]" "Low,High"
|
|
bitfld.byte 0x00 6. " TS_22 ,Sampling time selection bit [22]" "Low,High"
|
|
bitfld.byte 0x00 5. " TS_21 ,Sampling time selection bit [21]" "Low,High"
|
|
bitfld.byte 0x00 4. " TS_20 ,Sampling time selection bit [20]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_19 ,Sampling time selection bit [19]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_18 ,Sampling time selection bit [18]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_17 ,Sampling time selection bit [17]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_16 ,Sampling time selection bit [16]" "Low,High"
|
|
group.byte 0x2D++0x00
|
|
line.byte 0x00 "ADSS1,Sampling Time Selection Register 1"
|
|
bitfld.byte 0x00 7. " TS_15 ,Sampling time selection bit [15]" "Low,High"
|
|
bitfld.byte 0x00 6. " TS_14 ,Sampling time selection bit [14]" "Low,High"
|
|
bitfld.byte 0x00 5. " TS_13 ,Sampling time selection bit [13]" "Low,High"
|
|
bitfld.byte 0x00 4. " TS_12 ,Sampling time selection bit [12]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_11 ,Sampling time selection bit [11]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_10 ,Sampling time selection bit [10]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_9 ,Sampling time selection bit [9]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_8 ,Sampling time selection bit [8]" "Low,High"
|
|
endif
|
|
group.byte 0x2C++0x00
|
|
line.byte 0x00 "ADSS0,Sampling Time Selection Register 0"
|
|
sif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C12*")||cpuis("S6E1C32*")
|
|
bitfld.byte 0x00 7. " TS_7 ,Sampling time selection bit [7]" "Low,High"
|
|
bitfld.byte 0x00 6. " TS_6 ,Sampling time selection bit [6]" "Low,High"
|
|
bitfld.byte 0x00 5. " TS_5 ,Sampling time selection bit [5]" "Low,High"
|
|
bitfld.byte 0x00 4. " TS_4 ,Sampling time selection bit [4]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_3 ,Sampling time selection bit [3]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_2 ,Sampling time selection bit [2]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_1 ,Sampling time selection bit [1]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_0 ,Sampling time selection bit [0]" "Low,High"
|
|
elif cpuis("S6E1A11B")||cpuis("S6E1A12B")
|
|
bitfld.byte 0x00 4. " TS_4 ,Sampling time selection bit [4]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_3 ,Sampling time selection bit [3]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_2 ,Sampling time selection bit [2]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_1 ,Sampling time selection bit [1]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_0 ,Sampling time selection bit [0]" "Low,High"
|
|
elif cpuis("S6E1C11*")||cpuis("S6E1C31*")
|
|
bitfld.byte 0x00 5. " TS_5 ,Sampling time selection bit [5]" "Low,High"
|
|
bitfld.byte 0x00 4. " TS_4 ,Sampling time selection bit [4]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_3 ,Sampling time selection bit [3]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_2 ,Sampling time selection bit [2]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_1 ,Sampling time selection bit [1]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_0 ,Sampling time selection bit [0]" "Low,High"
|
|
endif
|
|
group.byte 0x31++0x00
|
|
line.byte 0x00 "ADST0,Sampling Time Setup Register 0"
|
|
bitfld.byte 0x00 5.--7. " STX_0 ,Sampling time N times setting bits" "x1,x4,x8,x16,x32,x64,x128,x256"
|
|
bitfld.byte 0x00 4. " ST_4 ,Sampling time setting bit [4]" "Low,High"
|
|
bitfld.byte 0x00 3. " ST_3 ,Sampling time setting bit [3]" "Low,High"
|
|
bitfld.byte 0x00 2. " ST_2 ,Sampling time setting bit [2]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " ST_1 ,Sampling time setting bit [1]" "Low,High"
|
|
bitfld.byte 0x00 0. " ST_0 ,Sampling time setting bit [0]" "Low,High"
|
|
group.byte 0x30++0x00
|
|
line.byte 0x00 "ADST1,Sampling Time Setup Register 1"
|
|
bitfld.byte 0x00 5.--7. " STX_1 ,Sampling time N times setting bits" "x1,x4,x8,x16,x32,x64,x128,x256"
|
|
bitfld.byte 0x00 4. " ST_14 ,Sampling time setting bit [14]" "Low,High"
|
|
bitfld.byte 0x00 3. " ST_13 ,Sampling time setting bit [13]" "Low,High"
|
|
bitfld.byte 0x00 2. " ST_12 ,Sampling time setting bit [12]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " ST_11 ,Sampling time setting bit [11]" "Low,High"
|
|
bitfld.byte 0x00 0. " ST_10 ,Sampling time setting bit [10]" "Low,High"
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "ADCT,Comparison Time Setup Register"
|
|
hexmask.byte 0x00 0.--7. 1. " CT ,Frequency division ratio"
|
|
else
|
|
sif !(cpuis("S6E1A11B")||cpuis("S6E1A12B")||cpuis("S6E1A11C")||cpuis("S6E1A12C"))
|
|
rgroup.byte 0x29++0x00
|
|
line.byte 0x00 "ADSS3,Sampling Time Selection Register 3"
|
|
bitfld.byte 0x00 7. " TS_31 ,Sampling time selection bit [31]" "Low,High"
|
|
bitfld.byte 0x00 6. " TS_30 ,Sampling time selection bit [30]" "Low,High"
|
|
bitfld.byte 0x00 5. " TS_29 ,Sampling time selection bit [29]" "Low,High"
|
|
bitfld.byte 0x00 4. " TS_28 ,Sampling time selection bit [28]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_27 ,Sampling time selection bit [27]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_26 ,Sampling time selection bit [26]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_25 ,Sampling time selection bit [25]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_24 ,Sampling time selection bit [24]" "Low,High"
|
|
rgroup.byte 0x28++0x00
|
|
line.byte 0x00 "ADSS2,Sampling Time Selection Register 2"
|
|
bitfld.byte 0x00 7. " TS_23 ,Sampling time selection bit [23]" "Low,High"
|
|
bitfld.byte 0x00 6. " TS_22 ,Sampling time selection bit [22]" "Low,High"
|
|
bitfld.byte 0x00 5. " TS_21 ,Sampling time selection bit [21]" "Low,High"
|
|
bitfld.byte 0x00 4. " TS_20 ,Sampling time selection bit [20]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_19 ,Sampling time selection bit [19]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_18 ,Sampling time selection bit [18]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_17 ,Sampling time selection bit [17]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_16 ,Sampling time selection bit [16]" "Low,High"
|
|
rgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "ADSS1,Sampling Time Selection Register 1"
|
|
bitfld.byte 0x00 7. " TS_15 ,Sampling time selection bit [15]" "Low,High"
|
|
bitfld.byte 0x00 6. " TS_14 ,Sampling time selection bit [14]" "Low,High"
|
|
bitfld.byte 0x00 5. " TS_13 ,Sampling time selection bit [13]" "Low,High"
|
|
bitfld.byte 0x00 4. " TS_12 ,Sampling time selection bit [12]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_11 ,Sampling time selection bit [11]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_10 ,Sampling time selection bit [10]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_9 ,Sampling time selection bit [9]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_8 ,Sampling time selection bit [8]" "Low,High"
|
|
endif
|
|
rgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "ADSS0,Sampling Time Selection Register 0"
|
|
sif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C12*")||cpuis("S6E1C32*")
|
|
bitfld.byte 0x00 7. " TS_7 ,Sampling time selection bit [7]" "Low,High"
|
|
bitfld.byte 0x00 6. " TS_6 ,Sampling time selection bit [6]" "Low,High"
|
|
bitfld.byte 0x00 5. " TS_5 ,Sampling time selection bit [5]" "Low,High"
|
|
bitfld.byte 0x00 4. " TS_4 ,Sampling time selection bit [4]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_3 ,Sampling time selection bit [3]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_2 ,Sampling time selection bit [2]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_1 ,Sampling time selection bit [1]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_0 ,Sampling time selection bit [0]" "Low,High"
|
|
elif cpuis("S6E1A11B")||cpuis("S6E1A12B")||cpuis("S6E1A11C")||cpuis("S6E1A12C")
|
|
bitfld.byte 0x00 4. " TS_4 ,Sampling time selection bit [4]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_3 ,Sampling time selection bit [3]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_2 ,Sampling time selection bit [2]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_1 ,Sampling time selection bit [1]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_0 ,Sampling time selection bit [0]" "Low,High"
|
|
elif cpuis("S6E1C11*")||cpuis("S6E1C31*")
|
|
bitfld.byte 0x00 5. " TS_5 ,Sampling time selection bit [5]" "Low,High"
|
|
bitfld.byte 0x00 4. " TS_4 ,Sampling time selection bit [4]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_3 ,Sampling time selection bit [3]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_2 ,Sampling time selection bit [2]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_1 ,Sampling time selection bit [1]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_0 ,Sampling time selection bit [0]" "Low,High"
|
|
endif
|
|
rgroup.byte 0x31++0x00
|
|
line.byte 0x00 "ADST0,Sampling Time Setup Register 0"
|
|
bitfld.byte 0x00 5.--7. " STX_0 ,Sampling time N times setting bits" "x1,x4,x8,x16,x32,x64,x128,x256"
|
|
bitfld.byte 0x00 4. " ST_4 ,Sampling time setting bit [4]" "Low,High"
|
|
bitfld.byte 0x00 3. " ST_3 ,Sampling time setting bit [3]" "Low,High"
|
|
bitfld.byte 0x00 2. " ST_2 ,Sampling time setting bit [2]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " ST_1 ,Sampling time setting bit [1]" "Low,High"
|
|
bitfld.byte 0x00 0. " ST_0 ,Sampling time setting bit [0]" "Low,High"
|
|
rgroup.byte 0x30++0x00
|
|
line.byte 0x00 "ADST1,Sampling Time Setup Register 1"
|
|
bitfld.byte 0x00 5.--7. " STX_1 ,Sampling time N times setting bits" "x1,x4,x8,x16,x32,x64,x128,x256"
|
|
bitfld.byte 0x00 4. " ST_14 ,Sampling time setting bit [14]" "Low,High"
|
|
bitfld.byte 0x00 3. " ST_13 ,Sampling time setting bit [13]" "Low,High"
|
|
bitfld.byte 0x00 2. " ST_12 ,Sampling time setting bit [12]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " ST_11 ,Sampling time setting bit [11]" "Low,High"
|
|
bitfld.byte 0x00 0. " ST_10 ,Sampling time setting bit [10]" "Low,High"
|
|
rgroup.byte 0x34++0x00
|
|
line.byte 0x00 "ADCT,Comparison Time Setup Register"
|
|
hexmask.byte 0x00 0.--7. 1. " CT ,Frequency division ratio"
|
|
endif
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "ADCEN,A/D Operation Enable Setup Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " ENBLTIME ,Enable state transition cycle selection bits"
|
|
rbitfld.word 0x00 1. " READY ,A/D operation enable state bit" "Stop state,Enable state"
|
|
bitfld.word 0x00 0. " ENBL ,A/D operation enable bit" "Disabled,Enabled"
|
|
group.word 0x52++0x01
|
|
line.word 0x00 "WCMPDH,Upper Limit Setup Register"
|
|
hexmask.word 0x00 6.--15. 0x40 " CMHD ,Upper limit"
|
|
if (per.b(ad:0x40027000+0x4C)&0x4)==0x0
|
|
group.byte 0x4C++0x00
|
|
line.byte 0x00 "WCMPCR,Range Comparison Control Register"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection specification count/state" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Selection bit of within-range and out-of-range confirmation" "Out,Within"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x4C++0x00
|
|
line.byte 0x00 "WCMPCR,Range Comparison Control Register"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection specification count/state" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Selection bit of within-range and out-of-range confirmation" "Out,Within"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "WCMPDL,Lower Limit Threshold Setup Register"
|
|
hexmask.word 0x00 6.--15. 0x40 " CMLD ,Lower limit threshold"
|
|
group.byte 0x4D++0x00
|
|
line.byte 0x00 "WCMPSR,Range Comparison Channel Select Register"
|
|
bitfld.byte 0x00 5. " WCMD ,Comparison mode select" "WCCH,All ch."
|
|
sif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C12*")||cpuis("S6E1C32*")
|
|
bitfld.byte 0x00 0.--4. " WCCH ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,?..."
|
|
elif cpuis("S6E1A11B")||cpuis("S6E1A12B")
|
|
bitfld.byte 0x00 0.--4. " WCCH ,Comparison target analog input channel" "0,1,2,3,4,?..."
|
|
elif cpuis("S6E1C11*")||cpuis("S6E1C31*")
|
|
bitfld.byte 0x00 0.--4. " WCCH ,Comparison target analog input channel" "0,1,2,3,4,5,?..."
|
|
endif
|
|
textline " "
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "WCMRCOT,Range Comparison Threshold Excess Flag Register"
|
|
bitfld.long 0x00 0. " RCOOF ,Threshold excess flag" "Below lower limit,Beyond upper limit"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "WCMRCIF,Range Comparison Flag Register"
|
|
bitfld.long 0x00 0. " RCINT ,Range comparison interrupt factor flag" "Clear,Detected"
|
|
tree.open "A/D Timer Trigger Selection"
|
|
width 7.
|
|
group.byte 0x39++0x00
|
|
line.byte 0x00 "SCTSL,Scan Conversion Timer Trigger Selection Register"
|
|
sif cpuis("S6E1C12*")||cpuis("S6E1C32*")
|
|
bitfld.byte 0x00 0.--3. " SCTSL ,Scan conversion timer trigger selection bit" "Not selected,MFT,0,1,2,3,4,5,6,7,?..."
|
|
elif cpuis("S6E1C11*")||cpuis("S6E1C31*")
|
|
bitfld.byte 0x00 0.--3. " SCTSL ,Scan conversion timer trigger selection bit" "Not selected,MFT,0,1,2,3,4,5,?..."
|
|
else
|
|
bitfld.byte 0x00 0.--3. " SCTSL ,Scan conversion timer trigger selection bit" "Not selected,MFT,0,1,2,3,?..."
|
|
endif
|
|
group.byte 0x38++0x00
|
|
line.byte 0x00 "PRTSL,Priority Conversion Timer Trigger Selection Register"
|
|
sif cpuis("S6E1C12*")||cpuis("S6E1C32*")
|
|
bitfld.byte 0x00 0.--3. " SCTSL ,Scan conversion timer trigger selection bit" "Not selected,MFT,0,1,2,3,4,5,6,7,?..."
|
|
elif cpuis("S6E1C11*")||cpuis("S6E1C31*")
|
|
bitfld.byte 0x00 0.--3. " SCTSL ,Scan conversion timer trigger selection bit" "Not selected,MFT,0,1,2,3,4,5,?..."
|
|
else
|
|
bitfld.byte 0x00 0.--3. " PRTSL ,Scan conversion timer trigger selection bit" "Not selected,MFT,0,1,2,3,?..."
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
sif !cpuis("S6E1C*")
|
|
tree "Unit 1"
|
|
base ad:0x40027100
|
|
width 9.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "ADCR,A/D Control Register"
|
|
bitfld.byte 0x00 7. " SCIF ,Scan conversion interrupt request bit (Read/Write)" "Not requested/Cleared,No effect"
|
|
bitfld.byte 0x00 6. " PCIF ,Priority conversion interrupt request bit (Read/Write)" "Not requested/Cleared,No effect"
|
|
bitfld.byte 0x00 5. " CMPIF ,Conversion result comparison interrupt request bit (Read/Write)" "Not requested/Cleared,No effect"
|
|
bitfld.byte 0x00 3. " SCIE ,Scan conversion interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " PCIE ,Priority conversion interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " CMPIE ,Conversion result comparison interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " OVRIE ,FIFO overrun interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "ADSR,A/D Status Register"
|
|
bitfld.byte 0x00 7. " ADSTP ,A/D conversion forced stop bit" "No effect,Stopped"
|
|
bitfld.byte 0x00 6. " FDAS ,FIFO data placement selection bit" "MSB,LSB"
|
|
rbitfld.byte 0x00 2. " PCNS ,Priority conversion pending flag" "Not pending,Pending"
|
|
rbitfld.byte 0x00 1. " PCS ,Priority conversion status flag" "Stopped,In progress"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " SCS ,Scan conversion status flag" "Stopped,In progress"
|
|
group.byte 0x09++0x00
|
|
line.byte 0x00 "SCCR,Scan Conversion Control Register"
|
|
rbitfld.byte 0x00 7. " SEMP ,Scan conversion FIFO empty bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 6. " SFUL ,Scan conversion FIFO full bit" "Not full,Full"
|
|
bitfld.byte 0x00 5. " SOVR ,Scan conversion overrun flag" "No overrun/Cleared,Overrun/No effect"
|
|
bitfld.byte 0x00 4. " SFCLR ,Scan conversion FIFO clear bit" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RPT ,Scan conversion repeat bit" "Single,Repeat"
|
|
bitfld.byte 0x00 1. " SHEN ,Scan conversion timer start enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " SSTR ,Scan conversion start bit" "No effect,Started"
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "SFNS,Scan Conversion FIFO Stage Count Setup Register"
|
|
bitfld.byte 0x00 0.--3. " SFS ,Scan conversion FIFO stage count setting bit" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SCFD,Scan Conversion FIFO Data Register"
|
|
bitfld.long 0x00 31. " SD_11 ,Scan conversion result bit [11]" "Low,High"
|
|
bitfld.long 0x00 30. " SD_10 ,Scan conversion result bit [10]" "Low,High"
|
|
bitfld.long 0x00 29. " SD_9 ,Scan conversion result bit [9]" "Low,High"
|
|
bitfld.long 0x00 28. " SD_8 ,Scan conversion result bit [8]" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SD_7 ,Scan conversion result bit [7]" "Low,High"
|
|
bitfld.long 0x00 26. " SD_6 ,Scan conversion result bit [6]" "Low,High"
|
|
bitfld.long 0x00 25. " SD_5 ,Scan conversion result bit [5]" "Low,High"
|
|
bitfld.long 0x00 24. " SD_4 ,Scan conversion result bit [4]" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SD_3 ,Scan conversion result bit [3]" "Low,High"
|
|
bitfld.long 0x00 22. " SD_2 ,Scan conversion result bit [2]" "Low,High"
|
|
bitfld.long 0x00 21. " SD_1 ,Scan conversion result bit [1]" "Low,High"
|
|
bitfld.long 0x00 20. " SD_0 ,Scan conversion result bit [0]" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " INVL ,A/D conversion result disable bit" "Valid,Invalid"
|
|
bitfld.long 0x00 8.--9. " RS ,Conversion start factor" ",Software,Timer,"
|
|
bitfld.long 0x00 0.--4. " SC ,Conversion input channel bits [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (per.b(ad:0x40027100)&0x3)==0x0
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "SCIS3,Scan Conversion Input Selection Register 3"
|
|
bitfld.byte 0x00 7. " AN_31 ,Analog input selection bit [31]" "Low,High"
|
|
bitfld.byte 0x00 6. " AN_30 ,Analog input selection bit [30]" "Low,High"
|
|
bitfld.byte 0x00 5. " AN_29 ,Analog input selection bit [29]" "Low,High"
|
|
bitfld.byte 0x00 4. " AN_28 ,Analog input selection bit [28]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " AN_27 ,Analog input selection bit [27]" "Low,High"
|
|
bitfld.byte 0x00 2. " AN_26 ,Analog input selection bit [26]" "Low,High"
|
|
bitfld.byte 0x00 1. " AN_25 ,Analog input selection bit [25]" "Low,High"
|
|
bitfld.byte 0x00 0. " AN_24 ,Analog input selection bit [24]" "Low,High"
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "SCIS2,Scan Conversion Input Selection Register 2"
|
|
bitfld.byte 0x00 7. " AN_23 ,Analog input selection bit [23]" "Low,High"
|
|
bitfld.byte 0x00 6. " AN_22 ,Analog input selection bit [22]" "Low,High"
|
|
bitfld.byte 0x00 5. " AN_21 ,Analog input selection bit [21]" "Low,High"
|
|
bitfld.byte 0x00 4. " AN_20 ,Analog input selection bit [20]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " AN_19 ,Analog input selection bit [19]" "Low,High"
|
|
bitfld.byte 0x00 2. " AN_18 ,Analog input selection bit [18]" "Low,High"
|
|
bitfld.byte 0x00 1. " AN_17 ,Analog input selection bit [17]" "Low,High"
|
|
bitfld.byte 0x00 0. " AN_16 ,Analog input selection bit [16]" "Low,High"
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "SCIS1,Scan Conversion Input Selection Register 1"
|
|
bitfld.byte 0x00 7. " AN_15 ,Analog input selection bit [15]" "Low,High"
|
|
bitfld.byte 0x00 6. " AN_14 ,Analog input selection bit [14]" "Low,High"
|
|
bitfld.byte 0x00 5. " AN_13 ,Analog input selection bit [13]" "Low,High"
|
|
bitfld.byte 0x00 4. " AN_12 ,Analog input selection bit [12]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " AN_11 ,Analog input selection bit [11]" "Low,High"
|
|
bitfld.byte 0x00 2. " AN_10 ,Analog input selection bit [10]" "Low,High"
|
|
bitfld.byte 0x00 1. " AN_9 ,Analog input selection bit [9]" "Low,High"
|
|
bitfld.byte 0x00 0. " AN_8 ,Analog input selection bit [8]" "Low,High"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "SCIS0,Scan Conversion Input Selection Register 0"
|
|
bitfld.byte 0x00 7. " AN_7 ,Analog input selection bit [7]" "Low,High"
|
|
bitfld.byte 0x00 6. " AN_6 ,Analog input selection bit [6]" "Low,High"
|
|
bitfld.byte 0x00 5. " AN_5 ,Analog input selection bit [5]" "Low,High"
|
|
bitfld.byte 0x00 4. " AN_4 ,Analog input selection bit [4]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " AN_3 ,Analog input selection bit [3]" "Low,High"
|
|
bitfld.byte 0x00 2. " AN_2 ,Analog input selection bit [2]" "Low,High"
|
|
bitfld.byte 0x00 1. " AN_1 ,Analog input selection bit [1]" "Low,High"
|
|
bitfld.byte 0x00 0. " AN_0 ,Analog input selection bit [0]" "Low,High"
|
|
else
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "SCIS3,Scan Conversion Input Selection Register 3"
|
|
bitfld.byte 0x00 7. " AN_31 ,Analog input selection bit [31]" "Low,High"
|
|
bitfld.byte 0x00 6. " AN_30 ,Analog input selection bit [30]" "Low,High"
|
|
bitfld.byte 0x00 5. " AN_29 ,Analog input selection bit [29]" "Low,High"
|
|
bitfld.byte 0x00 4. " AN_28 ,Analog input selection bit [28]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " AN_27 ,Analog input selection bit [27]" "Low,High"
|
|
bitfld.byte 0x00 2. " AN_26 ,Analog input selection bit [26]" "Low,High"
|
|
bitfld.byte 0x00 1. " AN_25 ,Analog input selection bit [25]" "Low,High"
|
|
bitfld.byte 0x00 0. " AN_24 ,Analog input selection bit [24]" "Low,High"
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "SCIS2,Scan Conversion Input Selection Register 2"
|
|
bitfld.byte 0x00 7. " AN_23 ,Analog input selection bit [23]" "Low,High"
|
|
bitfld.byte 0x00 6. " AN_22 ,Analog input selection bit [22]" "Low,High"
|
|
bitfld.byte 0x00 5. " AN_21 ,Analog input selection bit [21]" "Low,High"
|
|
bitfld.byte 0x00 4. " AN_20 ,Analog input selection bit [20]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " AN_19 ,Analog input selection bit [19]" "Low,High"
|
|
bitfld.byte 0x00 2. " AN_18 ,Analog input selection bit [18]" "Low,High"
|
|
bitfld.byte 0x00 1. " AN_17 ,Analog input selection bit [17]" "Low,High"
|
|
bitfld.byte 0x00 0. " AN_16 ,Analog input selection bit [16]" "Low,High"
|
|
rgroup.byte 0x15++0x00
|
|
line.byte 0x00 "SCIS1,Scan Conversion Input Selection Register 1"
|
|
bitfld.byte 0x00 7. " AN_15 ,Analog input selection bit [15]" "Low,High"
|
|
bitfld.byte 0x00 6. " AN_14 ,Analog input selection bit [14]" "Low,High"
|
|
bitfld.byte 0x00 5. " AN_13 ,Analog input selection bit [13]" "Low,High"
|
|
bitfld.byte 0x00 4. " AN_12 ,Analog input selection bit [12]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " AN_11 ,Analog input selection bit [11]" "Low,High"
|
|
bitfld.byte 0x00 2. " AN_10 ,Analog input selection bit [10]" "Low,High"
|
|
bitfld.byte 0x00 1. " AN_9 ,Analog input selection bit [9]" "Low,High"
|
|
bitfld.byte 0x00 0. " AN_8 ,Analog input selection bit [8]" "Low,High"
|
|
rgroup.byte 0x14++0x00
|
|
line.byte 0x00 "SCIS0,Scan Conversion Input Selection Register 0"
|
|
bitfld.byte 0x00 7. " AN_7 ,Analog input selection bit [7]" "Low,High"
|
|
bitfld.byte 0x00 6. " AN_6 ,Analog input selection bit [6]" "Low,High"
|
|
bitfld.byte 0x00 5. " AN_5 ,Analog input selection bit [5]" "Low,High"
|
|
bitfld.byte 0x00 4. " AN_4 ,Analog input selection bit [4]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " AN_3 ,Analog input selection bit [3]" "Low,High"
|
|
bitfld.byte 0x00 2. " AN_2 ,Analog input selection bit [2]" "Low,High"
|
|
bitfld.byte 0x00 1. " AN_1 ,Analog input selection bit [1]" "Low,High"
|
|
bitfld.byte 0x00 0. " AN_0 ,Analog input selection bit [0]" "Low,High"
|
|
endif
|
|
if (per.b(ad:0x40027100)&0x3)==0x0
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "PCCR,Priority Conversion Control Register"
|
|
rbitfld.byte 0x00 7. " PEMP ,Priority conversion FIFO empty bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 6. " PFUL ,Priority conversion FIFO full bit" "Not full,Full"
|
|
bitfld.byte 0x00 5. " POVR ,Priority conversion overrun flag (Read/Write)" "No overrun/Cleared,Overrun/No effect"
|
|
bitfld.byte 0x00 4. " PFCLR ,Priority conversion FIFO clear bit" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ESCE ,External trigger analog input selection bit" "P1A,External"
|
|
bitfld.byte 0x00 2. " PEEN ,Priority conversion external start enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " PHEN ,Priority conversion timer start enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " PSTR ,Priority conversion start bit" "No effect,Started"
|
|
else
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "PCCR,Priority Conversion Control Register"
|
|
rbitfld.byte 0x00 7. " PEMP ,Priority conversion FIFO empty bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 6. " PFUL ,Priority conversion FIFO full bit" "Not full,Full"
|
|
bitfld.byte 0x00 5. " POVR ,Priority conversion overrun flag (Read/Write)" "No overrun/Cleared,Overrun/No effect"
|
|
bitfld.byte 0x00 4. " PFCLR ,Priority conversion FIFO clear bit" "No effect,Cleared"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ESCE ,External trigger analog input selection bit" "P1A,External"
|
|
bitfld.byte 0x00 2. " PEEN ,Priority conversion external start enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " PHEN ,Priority conversion timer start enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " PSTR ,Priority conversion start bit" "No effect,Started"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "PFNS,Priority Conversion FIFO Stage Count Setup Register"
|
|
rbitfld.byte 0x00 4.--5. " TEST ,Test bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--1. " PFS ,Priority conversion FIFO stage count setting bits" "1st,2nd,3rd,4th"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "PCFD,Priority Conversion FIFO Data Register"
|
|
bitfld.long 0x00 31. " PD_11 ,Priority conversion result bit [11]" "Low,High"
|
|
bitfld.long 0x00 30. " PD_10 ,Priority conversion result bit [10]" "Low,High"
|
|
bitfld.long 0x00 29. " PD_9 ,Priority conversion result bit [9]" "Low,High"
|
|
bitfld.long 0x00 28. " PD_8 ,Priority conversion result bit [8]" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PD_7 ,Priority conversion result bit [7]" "Low,High"
|
|
bitfld.long 0x00 26. " PD_6 ,Priority conversion result bit [6]" "Low,High"
|
|
bitfld.long 0x00 25. " PD_5 ,Priority conversion result bit [5]" "Low,High"
|
|
bitfld.long 0x00 24. " PD_4 ,Priority conversion result bit [4]" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PD_3 ,Priority conversion result bit [3]" "Low,High"
|
|
bitfld.long 0x00 22. " PD_2 ,Priority conversion result bit [2]" "Low,High"
|
|
bitfld.long 0x00 21. " PD_1 ,Priority conversion result bit [1]" "Low,High"
|
|
bitfld.long 0x00 20. " PD_0 ,Priority conversion result bit [0]" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " INVL ,A/D conversion result disable bit" "Valid,Invalid"
|
|
bitfld.long 0x00 8.--10. " RS ,Conversion start factor" ",Software,Timer,,External,,,"
|
|
bitfld.long 0x00 0.--4. " PC ,Conversion input channel bits [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (per.b(ad:0x40027100)&0x3)==0x0
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "PCIS,Priority Conversion Input Selection Register"
|
|
sif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C12*")||cpuis("S6E1C32*")
|
|
bitfld.byte 0x00 3.--7. " P2A ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,?..."
|
|
elif cpuis("S6E1A11B")||cpuis("S6E1A12B")
|
|
bitfld.byte 0x00 3.--7. " P2A ,Priority level 2 analog input selection" "0,1,2,3,4,?..."
|
|
elif cpuis("S6E1C11*")||cpuis("S6E1C31*")
|
|
bitfld.byte 0x00 3.--7. " P2A ,Priority level 2 analog input selection" "0,1,2,3,4,5,?..."
|
|
endif
|
|
bitfld.byte 0x00 0.--2. " P1A ,Priority level 1 analog input selection" "0,1,2,3,4,5,6,7"
|
|
else
|
|
rgroup.byte 0x20++0x00
|
|
line.byte 0x00 "PCIS,Priority Conversion Input Selection Register"
|
|
sif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C12*")||cpuis("S6E1C32*")
|
|
bitfld.byte 0x00 3.--7. " P2A ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,?..."
|
|
elif cpuis("S6E1A11B")||cpuis("S6E1A12B")
|
|
bitfld.byte 0x00 3.--7. " P2A ,Priority level 2 analog input selection" "0,1,2,3,4,?..."
|
|
elif cpuis("S6E1C11*")||cpuis("S6E1C31*")
|
|
bitfld.byte 0x00 3.--7. " P2A ,Priority level 2 analog input selection" "0,1,2,3,4,5,?..."
|
|
endif
|
|
bitfld.byte 0x00 0.--2. " P1A ,Priority level 1 analog input selection" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
group.word 0x26++0x01
|
|
line.word 0x00 "CMPD,A/D Comparison Value Setup Register"
|
|
bitfld.word 0x00 15. " CMAD_11 ,A/D conversion result value setting bit [11]" "Low,High"
|
|
bitfld.word 0x00 14. " CMAD_10 ,A/D conversion result value setting bit [10]" "Low,High"
|
|
bitfld.word 0x00 13. " CMAD_9 ,A/D conversion result value setting bit [9]" "Low,High"
|
|
bitfld.word 0x00 12. " CMAD_8 ,A/D conversion result value setting bit [8]" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CMAD_7 ,A/D conversion result value setting bit [7]" "Low,High"
|
|
bitfld.word 0x00 10. " CMAD_6 ,A/D conversion result value setting bit [6]" "Low,High"
|
|
bitfld.word 0x00 9. " CMAD_5 ,A/D conversion result value setting bit [5]" "Low,High"
|
|
bitfld.word 0x00 8. " CMAD_4 ,A/D conversion result value setting bit [4]" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CMAD_3 ,A/D conversion result value setting bit [3]" "Low,High"
|
|
bitfld.word 0x00 6. " CMAD_2 ,A/D conversion result value setting bit [2]" "Low,High"
|
|
if (per.b(ad:0x40027100)&0x3)==0x0
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "CMPCR,A/D Comparison Control Register"
|
|
bitfld.byte 0x00 7. " CMPEN ,Conversion result comparison function operation" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CMD_1 ,Comparison mode 1" "<CMPD,>=CMPD"
|
|
bitfld.byte 0x00 5. " CMD_0 ,Comparison mode 0" "CCH,All"
|
|
sif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C12*")||cpuis("S6E1C32*")
|
|
bitfld.byte 0x00 0.--4. " CCH ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,?..."
|
|
elif cpuis("S6E1A11B")||cpuis("S6E1A12B")
|
|
bitfld.byte 0x00 0.--4. " CCH ,Comparison target analog input channel" "0,1,2,3,4,?..."
|
|
elif cpuis("S6E1C11*")||cpuis("S6E1C31*")
|
|
bitfld.byte 0x00 0.--4. " CCH ,Comparison target analog input channel" "0,1,2,3,4,5,?..."
|
|
endif
|
|
else
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "CMPCR,A/D Comparison Control Register"
|
|
bitfld.byte 0x00 7. " CMPEN ,Conversion result comparison function operation" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " CMD_1 ,Comparison mode 1" "<CMPD,>=CMPD"
|
|
bitfld.byte 0x00 5. " CMD_0 ,Comparison mode 0" "CCH,All"
|
|
sif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C12*")||cpuis("S6E1C32*")
|
|
bitfld.byte 0x00 0.--4. " CCH ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,?..."
|
|
elif cpuis("S6E1A11B")||cpuis("S6E1A12B")
|
|
bitfld.byte 0x00 0.--4. " CCH ,Comparison target analog input channel" "0,1,2,3,4,?..."
|
|
elif cpuis("S6E1C11*")||cpuis("S6E1C31*")
|
|
bitfld.byte 0x00 0.--4. " CCH ,Comparison target analog input channel" "0,1,2,3,4,5,?..."
|
|
endif
|
|
endif
|
|
if (per.b(ad:0x40027100)&0x3)==0x0
|
|
sif !(cpuis("S6E1A11B")||cpuis("S6E1A12B")||cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C12*")||cpuis("S6E1C32*")||cpuis("S6E1C11*")||cpuis("S6E1C31*"))
|
|
group.byte 0x29++0x00
|
|
line.byte 0x00 "ADSS3,Sampling Time Selection Register 3"
|
|
bitfld.byte 0x00 7. " TS_31 ,Sampling time selection bit [31]" "Low,High"
|
|
bitfld.byte 0x00 6. " TS_30 ,Sampling time selection bit [30]" "Low,High"
|
|
bitfld.byte 0x00 5. " TS_29 ,Sampling time selection bit [29]" "Low,High"
|
|
bitfld.byte 0x00 4. " TS_28 ,Sampling time selection bit [28]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_27 ,Sampling time selection bit [27]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_26 ,Sampling time selection bit [26]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_25 ,Sampling time selection bit [25]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_24 ,Sampling time selection bit [24]" "Low,High"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "ADSS2,Sampling Time Selection Register 2"
|
|
bitfld.byte 0x00 7. " TS_23 ,Sampling time selection bit [23]" "Low,High"
|
|
bitfld.byte 0x00 6. " TS_22 ,Sampling time selection bit [22]" "Low,High"
|
|
bitfld.byte 0x00 5. " TS_21 ,Sampling time selection bit [21]" "Low,High"
|
|
bitfld.byte 0x00 4. " TS_20 ,Sampling time selection bit [20]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_19 ,Sampling time selection bit [19]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_18 ,Sampling time selection bit [18]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_17 ,Sampling time selection bit [17]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_16 ,Sampling time selection bit [16]" "Low,High"
|
|
group.byte 0x2D++0x00
|
|
line.byte 0x00 "ADSS1,Sampling Time Selection Register 1"
|
|
bitfld.byte 0x00 7. " TS_15 ,Sampling time selection bit [15]" "Low,High"
|
|
bitfld.byte 0x00 6. " TS_14 ,Sampling time selection bit [14]" "Low,High"
|
|
bitfld.byte 0x00 5. " TS_13 ,Sampling time selection bit [13]" "Low,High"
|
|
bitfld.byte 0x00 4. " TS_12 ,Sampling time selection bit [12]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_11 ,Sampling time selection bit [11]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_10 ,Sampling time selection bit [10]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_9 ,Sampling time selection bit [9]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_8 ,Sampling time selection bit [8]" "Low,High"
|
|
endif
|
|
group.byte 0x2C++0x00
|
|
line.byte 0x00 "ADSS0,Sampling Time Selection Register 0"
|
|
sif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C12*")||cpuis("S6E1C32*")
|
|
bitfld.byte 0x00 7. " TS_7 ,Sampling time selection bit [7]" "Low,High"
|
|
bitfld.byte 0x00 6. " TS_6 ,Sampling time selection bit [6]" "Low,High"
|
|
bitfld.byte 0x00 5. " TS_5 ,Sampling time selection bit [5]" "Low,High"
|
|
bitfld.byte 0x00 4. " TS_4 ,Sampling time selection bit [4]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_3 ,Sampling time selection bit [3]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_2 ,Sampling time selection bit [2]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_1 ,Sampling time selection bit [1]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_0 ,Sampling time selection bit [0]" "Low,High"
|
|
elif cpuis("S6E1A11B")||cpuis("S6E1A12B")
|
|
bitfld.byte 0x00 4. " TS_4 ,Sampling time selection bit [4]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_3 ,Sampling time selection bit [3]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_2 ,Sampling time selection bit [2]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_1 ,Sampling time selection bit [1]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_0 ,Sampling time selection bit [0]" "Low,High"
|
|
elif cpuis("S6E1C11*")||cpuis("S6E1C31*")
|
|
bitfld.byte 0x00 5. " TS_5 ,Sampling time selection bit [5]" "Low,High"
|
|
bitfld.byte 0x00 4. " TS_4 ,Sampling time selection bit [4]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_3 ,Sampling time selection bit [3]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_2 ,Sampling time selection bit [2]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_1 ,Sampling time selection bit [1]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_0 ,Sampling time selection bit [0]" "Low,High"
|
|
endif
|
|
group.byte 0x31++0x00
|
|
line.byte 0x00 "ADST0,Sampling Time Setup Register 0"
|
|
bitfld.byte 0x00 5.--7. " STX_0 ,Sampling time N times setting bits" "x1,x4,x8,x16,x32,x64,x128,x256"
|
|
bitfld.byte 0x00 4. " ST_4 ,Sampling time setting bit [4]" "Low,High"
|
|
bitfld.byte 0x00 3. " ST_3 ,Sampling time setting bit [3]" "Low,High"
|
|
bitfld.byte 0x00 2. " ST_2 ,Sampling time setting bit [2]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " ST_1 ,Sampling time setting bit [1]" "Low,High"
|
|
bitfld.byte 0x00 0. " ST_0 ,Sampling time setting bit [0]" "Low,High"
|
|
group.byte 0x30++0x00
|
|
line.byte 0x00 "ADST1,Sampling Time Setup Register 1"
|
|
bitfld.byte 0x00 5.--7. " STX_1 ,Sampling time N times setting bits" "x1,x4,x8,x16,x32,x64,x128,x256"
|
|
bitfld.byte 0x00 4. " ST_14 ,Sampling time setting bit [14]" "Low,High"
|
|
bitfld.byte 0x00 3. " ST_13 ,Sampling time setting bit [13]" "Low,High"
|
|
bitfld.byte 0x00 2. " ST_12 ,Sampling time setting bit [12]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " ST_11 ,Sampling time setting bit [11]" "Low,High"
|
|
bitfld.byte 0x00 0. " ST_10 ,Sampling time setting bit [10]" "Low,High"
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "ADCT,Comparison Time Setup Register"
|
|
hexmask.byte 0x00 0.--7. 1. " CT ,Frequency division ratio"
|
|
else
|
|
sif !(cpuis("S6E1A11B")||cpuis("S6E1A12B")||cpuis("S6E1A11C")||cpuis("S6E1A12C"))
|
|
rgroup.byte 0x29++0x00
|
|
line.byte 0x00 "ADSS3,Sampling Time Selection Register 3"
|
|
bitfld.byte 0x00 7. " TS_31 ,Sampling time selection bit [31]" "Low,High"
|
|
bitfld.byte 0x00 6. " TS_30 ,Sampling time selection bit [30]" "Low,High"
|
|
bitfld.byte 0x00 5. " TS_29 ,Sampling time selection bit [29]" "Low,High"
|
|
bitfld.byte 0x00 4. " TS_28 ,Sampling time selection bit [28]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_27 ,Sampling time selection bit [27]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_26 ,Sampling time selection bit [26]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_25 ,Sampling time selection bit [25]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_24 ,Sampling time selection bit [24]" "Low,High"
|
|
rgroup.byte 0x28++0x00
|
|
line.byte 0x00 "ADSS2,Sampling Time Selection Register 2"
|
|
bitfld.byte 0x00 7. " TS_23 ,Sampling time selection bit [23]" "Low,High"
|
|
bitfld.byte 0x00 6. " TS_22 ,Sampling time selection bit [22]" "Low,High"
|
|
bitfld.byte 0x00 5. " TS_21 ,Sampling time selection bit [21]" "Low,High"
|
|
bitfld.byte 0x00 4. " TS_20 ,Sampling time selection bit [20]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_19 ,Sampling time selection bit [19]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_18 ,Sampling time selection bit [18]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_17 ,Sampling time selection bit [17]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_16 ,Sampling time selection bit [16]" "Low,High"
|
|
rgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "ADSS1,Sampling Time Selection Register 1"
|
|
bitfld.byte 0x00 7. " TS_15 ,Sampling time selection bit [15]" "Low,High"
|
|
bitfld.byte 0x00 6. " TS_14 ,Sampling time selection bit [14]" "Low,High"
|
|
bitfld.byte 0x00 5. " TS_13 ,Sampling time selection bit [13]" "Low,High"
|
|
bitfld.byte 0x00 4. " TS_12 ,Sampling time selection bit [12]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_11 ,Sampling time selection bit [11]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_10 ,Sampling time selection bit [10]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_9 ,Sampling time selection bit [9]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_8 ,Sampling time selection bit [8]" "Low,High"
|
|
endif
|
|
rgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "ADSS0,Sampling Time Selection Register 0"
|
|
sif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C12*")||cpuis("S6E1C32*")
|
|
bitfld.byte 0x00 7. " TS_7 ,Sampling time selection bit [7]" "Low,High"
|
|
bitfld.byte 0x00 6. " TS_6 ,Sampling time selection bit [6]" "Low,High"
|
|
bitfld.byte 0x00 5. " TS_5 ,Sampling time selection bit [5]" "Low,High"
|
|
bitfld.byte 0x00 4. " TS_4 ,Sampling time selection bit [4]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_3 ,Sampling time selection bit [3]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_2 ,Sampling time selection bit [2]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_1 ,Sampling time selection bit [1]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_0 ,Sampling time selection bit [0]" "Low,High"
|
|
elif cpuis("S6E1A11B")||cpuis("S6E1A12B")||cpuis("S6E1A11C")||cpuis("S6E1A12C")
|
|
bitfld.byte 0x00 4. " TS_4 ,Sampling time selection bit [4]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_3 ,Sampling time selection bit [3]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_2 ,Sampling time selection bit [2]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_1 ,Sampling time selection bit [1]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_0 ,Sampling time selection bit [0]" "Low,High"
|
|
elif cpuis("S6E1C11*")||cpuis("S6E1C31*")
|
|
bitfld.byte 0x00 5. " TS_5 ,Sampling time selection bit [5]" "Low,High"
|
|
bitfld.byte 0x00 4. " TS_4 ,Sampling time selection bit [4]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_3 ,Sampling time selection bit [3]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_2 ,Sampling time selection bit [2]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_1 ,Sampling time selection bit [1]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_0 ,Sampling time selection bit [0]" "Low,High"
|
|
endif
|
|
rgroup.byte 0x31++0x00
|
|
line.byte 0x00 "ADST0,Sampling Time Setup Register 0"
|
|
bitfld.byte 0x00 5.--7. " STX_0 ,Sampling time N times setting bits" "x1,x4,x8,x16,x32,x64,x128,x256"
|
|
bitfld.byte 0x00 4. " ST_4 ,Sampling time setting bit [4]" "Low,High"
|
|
bitfld.byte 0x00 3. " ST_3 ,Sampling time setting bit [3]" "Low,High"
|
|
bitfld.byte 0x00 2. " ST_2 ,Sampling time setting bit [2]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " ST_1 ,Sampling time setting bit [1]" "Low,High"
|
|
bitfld.byte 0x00 0. " ST_0 ,Sampling time setting bit [0]" "Low,High"
|
|
rgroup.byte 0x30++0x00
|
|
line.byte 0x00 "ADST1,Sampling Time Setup Register 1"
|
|
bitfld.byte 0x00 5.--7. " STX_1 ,Sampling time N times setting bits" "x1,x4,x8,x16,x32,x64,x128,x256"
|
|
bitfld.byte 0x00 4. " ST_14 ,Sampling time setting bit [14]" "Low,High"
|
|
bitfld.byte 0x00 3. " ST_13 ,Sampling time setting bit [13]" "Low,High"
|
|
bitfld.byte 0x00 2. " ST_12 ,Sampling time setting bit [12]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " ST_11 ,Sampling time setting bit [11]" "Low,High"
|
|
bitfld.byte 0x00 0. " ST_10 ,Sampling time setting bit [10]" "Low,High"
|
|
rgroup.byte 0x34++0x00
|
|
line.byte 0x00 "ADCT,Comparison Time Setup Register"
|
|
hexmask.byte 0x00 0.--7. 1. " CT ,Frequency division ratio"
|
|
endif
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "ADCEN,A/D Operation Enable Setup Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " ENBLTIME ,Enable state transition cycle selection bits"
|
|
rbitfld.word 0x00 1. " READY ,A/D operation enable state bit" "Stop state,Enable state"
|
|
bitfld.word 0x00 0. " ENBL ,A/D operation enable bit" "Disabled,Enabled"
|
|
group.word 0x52++0x01
|
|
line.word 0x00 "WCMPDH,Upper Limit Setup Register"
|
|
hexmask.word 0x00 6.--15. 0x40 " CMHD ,Upper limit"
|
|
if (per.b(ad:0x40027100+0x4C)&0x4)==0x0
|
|
group.byte 0x4C++0x00
|
|
line.byte 0x00 "WCMPCR,Range Comparison Control Register"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection specification count/state" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Selection bit of within-range and out-of-range confirmation" "Out,Within"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x4C++0x00
|
|
line.byte 0x00 "WCMPCR,Range Comparison Control Register"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection specification count/state" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Selection bit of within-range and out-of-range confirmation" "Out,Within"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "WCMPDL,Lower Limit Threshold Setup Register"
|
|
hexmask.word 0x00 6.--15. 0x40 " CMLD ,Lower limit threshold"
|
|
group.byte 0x4D++0x00
|
|
line.byte 0x00 "WCMPSR,Range Comparison Channel Select Register"
|
|
bitfld.byte 0x00 5. " WCMD ,Comparison mode select" "WCCH,All ch."
|
|
sif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C12*")||cpuis("S6E1C32*")
|
|
bitfld.byte 0x00 0.--4. " WCCH ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,?..."
|
|
elif cpuis("S6E1A11B")||cpuis("S6E1A12B")
|
|
bitfld.byte 0x00 0.--4. " WCCH ,Comparison target analog input channel" "0,1,2,3,4,?..."
|
|
elif cpuis("S6E1C11*")||cpuis("S6E1C31*")
|
|
bitfld.byte 0x00 0.--4. " WCCH ,Comparison target analog input channel" "0,1,2,3,4,5,?..."
|
|
endif
|
|
textline " "
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "WCMRCOT,Range Comparison Threshold Excess Flag Register"
|
|
bitfld.long 0x00 0. " RCOOF ,Threshold excess flag" "Below lower limit,Beyond upper limit"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "WCMRCIF,Range Comparison Flag Register"
|
|
bitfld.long 0x00 0. " RCINT ,Range comparison interrupt factor flag" "Clear,Detected"
|
|
tree.open "A/D Timer Trigger Selection"
|
|
width 7.
|
|
group.byte 0x39++0x00
|
|
line.byte 0x00 "SCTSL,Scan Conversion Timer Trigger Selection Register"
|
|
sif cpuis("S6E1C12*")||cpuis("S6E1C32*")
|
|
bitfld.byte 0x00 0.--3. " SCTSL ,Scan conversion timer trigger selection bit" "Not selected,MFT,0,1,2,3,4,5,6,7,?..."
|
|
elif cpuis("S6E1C11*")||cpuis("S6E1C31*")
|
|
bitfld.byte 0x00 0.--3. " SCTSL ,Scan conversion timer trigger selection bit" "Not selected,MFT,0,1,2,3,4,5,?..."
|
|
else
|
|
bitfld.byte 0x00 0.--3. " SCTSL ,Scan conversion timer trigger selection bit" "Not selected,MFT,0,1,2,3,?..."
|
|
endif
|
|
group.byte 0x38++0x00
|
|
line.byte 0x00 "PRTSL,Priority Conversion Timer Trigger Selection Register"
|
|
sif cpuis("S6E1C12*")||cpuis("S6E1C32*")
|
|
bitfld.byte 0x00 0.--3. " SCTSL ,Scan conversion timer trigger selection bit" "Not selected,MFT,0,1,2,3,4,5,6,7,?..."
|
|
elif cpuis("S6E1C11*")||cpuis("S6E1C31*")
|
|
bitfld.byte 0x00 0.--3. " SCTSL ,Scan conversion timer trigger selection bit" "Not selected,MFT,0,1,2,3,4,5,?..."
|
|
else
|
|
bitfld.byte 0x00 0.--3. " PRTSL ,Scan conversion timer trigger selection bit" "Not selected,MFT,0,1,2,3,?..."
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Unit 2"
|
|
base ad:0x40027200
|
|
width 9.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "ADCR,A/D Control Register"
|
|
bitfld.byte 0x00 7. " SCIF ,Scan conversion interrupt request bit (Read/Write)" "Not requested/Cleared,No effect"
|
|
bitfld.byte 0x00 6. " PCIF ,Priority conversion interrupt request bit (Read/Write)" "Not requested/Cleared,No effect"
|
|
bitfld.byte 0x00 5. " CMPIF ,Conversion result comparison interrupt request bit (Read/Write)" "Not requested/Cleared,No effect"
|
|
bitfld.byte 0x00 3. " SCIE ,Scan conversion interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " PCIE ,Priority conversion interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " CMPIE ,Conversion result comparison interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " OVRIE ,FIFO overrun interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "ADSR,A/D Status Register"
|
|
bitfld.byte 0x00 7. " ADSTP ,A/D conversion forced stop bit" "No effect,Stopped"
|
|
bitfld.byte 0x00 6. " FDAS ,FIFO data placement selection bit" "MSB,LSB"
|
|
rbitfld.byte 0x00 2. " PCNS ,Priority conversion pending flag" "Not pending,Pending"
|
|
rbitfld.byte 0x00 1. " PCS ,Priority conversion status flag" "Stopped,In progress"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " SCS ,Scan conversion status flag" "Stopped,In progress"
|
|
group.byte 0x09++0x00
|
|
line.byte 0x00 "SCCR,Scan Conversion Control Register"
|
|
rbitfld.byte 0x00 7. " SEMP ,Scan conversion FIFO empty bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 6. " SFUL ,Scan conversion FIFO full bit" "Not full,Full"
|
|
bitfld.byte 0x00 5. " SOVR ,Scan conversion overrun flag" "No overrun/Cleared,Overrun/No effect"
|
|
bitfld.byte 0x00 4. " SFCLR ,Scan conversion FIFO clear bit" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RPT ,Scan conversion repeat bit" "Single,Repeat"
|
|
bitfld.byte 0x00 1. " SHEN ,Scan conversion timer start enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " SSTR ,Scan conversion start bit" "No effect,Started"
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "SFNS,Scan Conversion FIFO Stage Count Setup Register"
|
|
bitfld.byte 0x00 0.--3. " SFS ,Scan conversion FIFO stage count setting bit" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SCFD,Scan Conversion FIFO Data Register"
|
|
bitfld.long 0x00 31. " SD_11 ,Scan conversion result bit [11]" "Low,High"
|
|
bitfld.long 0x00 30. " SD_10 ,Scan conversion result bit [10]" "Low,High"
|
|
bitfld.long 0x00 29. " SD_9 ,Scan conversion result bit [9]" "Low,High"
|
|
bitfld.long 0x00 28. " SD_8 ,Scan conversion result bit [8]" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SD_7 ,Scan conversion result bit [7]" "Low,High"
|
|
bitfld.long 0x00 26. " SD_6 ,Scan conversion result bit [6]" "Low,High"
|
|
bitfld.long 0x00 25. " SD_5 ,Scan conversion result bit [5]" "Low,High"
|
|
bitfld.long 0x00 24. " SD_4 ,Scan conversion result bit [4]" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SD_3 ,Scan conversion result bit [3]" "Low,High"
|
|
bitfld.long 0x00 22. " SD_2 ,Scan conversion result bit [2]" "Low,High"
|
|
bitfld.long 0x00 21. " SD_1 ,Scan conversion result bit [1]" "Low,High"
|
|
bitfld.long 0x00 20. " SD_0 ,Scan conversion result bit [0]" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " INVL ,A/D conversion result disable bit" "Valid,Invalid"
|
|
bitfld.long 0x00 8.--9. " RS ,Conversion start factor" ",Software,Timer,"
|
|
bitfld.long 0x00 0.--4. " SC ,Conversion input channel bits [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (per.b(ad:0x40027200)&0x3)==0x0
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "SCIS3,Scan Conversion Input Selection Register 3"
|
|
bitfld.byte 0x00 7. " AN_31 ,Analog input selection bit [31]" "Low,High"
|
|
bitfld.byte 0x00 6. " AN_30 ,Analog input selection bit [30]" "Low,High"
|
|
bitfld.byte 0x00 5. " AN_29 ,Analog input selection bit [29]" "Low,High"
|
|
bitfld.byte 0x00 4. " AN_28 ,Analog input selection bit [28]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " AN_27 ,Analog input selection bit [27]" "Low,High"
|
|
bitfld.byte 0x00 2. " AN_26 ,Analog input selection bit [26]" "Low,High"
|
|
bitfld.byte 0x00 1. " AN_25 ,Analog input selection bit [25]" "Low,High"
|
|
bitfld.byte 0x00 0. " AN_24 ,Analog input selection bit [24]" "Low,High"
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "SCIS2,Scan Conversion Input Selection Register 2"
|
|
bitfld.byte 0x00 7. " AN_23 ,Analog input selection bit [23]" "Low,High"
|
|
bitfld.byte 0x00 6. " AN_22 ,Analog input selection bit [22]" "Low,High"
|
|
bitfld.byte 0x00 5. " AN_21 ,Analog input selection bit [21]" "Low,High"
|
|
bitfld.byte 0x00 4. " AN_20 ,Analog input selection bit [20]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " AN_19 ,Analog input selection bit [19]" "Low,High"
|
|
bitfld.byte 0x00 2. " AN_18 ,Analog input selection bit [18]" "Low,High"
|
|
bitfld.byte 0x00 1. " AN_17 ,Analog input selection bit [17]" "Low,High"
|
|
bitfld.byte 0x00 0. " AN_16 ,Analog input selection bit [16]" "Low,High"
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "SCIS1,Scan Conversion Input Selection Register 1"
|
|
bitfld.byte 0x00 7. " AN_15 ,Analog input selection bit [15]" "Low,High"
|
|
bitfld.byte 0x00 6. " AN_14 ,Analog input selection bit [14]" "Low,High"
|
|
bitfld.byte 0x00 5. " AN_13 ,Analog input selection bit [13]" "Low,High"
|
|
bitfld.byte 0x00 4. " AN_12 ,Analog input selection bit [12]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " AN_11 ,Analog input selection bit [11]" "Low,High"
|
|
bitfld.byte 0x00 2. " AN_10 ,Analog input selection bit [10]" "Low,High"
|
|
bitfld.byte 0x00 1. " AN_9 ,Analog input selection bit [9]" "Low,High"
|
|
bitfld.byte 0x00 0. " AN_8 ,Analog input selection bit [8]" "Low,High"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "SCIS0,Scan Conversion Input Selection Register 0"
|
|
bitfld.byte 0x00 7. " AN_7 ,Analog input selection bit [7]" "Low,High"
|
|
bitfld.byte 0x00 6. " AN_6 ,Analog input selection bit [6]" "Low,High"
|
|
bitfld.byte 0x00 5. " AN_5 ,Analog input selection bit [5]" "Low,High"
|
|
bitfld.byte 0x00 4. " AN_4 ,Analog input selection bit [4]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " AN_3 ,Analog input selection bit [3]" "Low,High"
|
|
bitfld.byte 0x00 2. " AN_2 ,Analog input selection bit [2]" "Low,High"
|
|
bitfld.byte 0x00 1. " AN_1 ,Analog input selection bit [1]" "Low,High"
|
|
bitfld.byte 0x00 0. " AN_0 ,Analog input selection bit [0]" "Low,High"
|
|
else
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "SCIS3,Scan Conversion Input Selection Register 3"
|
|
bitfld.byte 0x00 7. " AN_31 ,Analog input selection bit [31]" "Low,High"
|
|
bitfld.byte 0x00 6. " AN_30 ,Analog input selection bit [30]" "Low,High"
|
|
bitfld.byte 0x00 5. " AN_29 ,Analog input selection bit [29]" "Low,High"
|
|
bitfld.byte 0x00 4. " AN_28 ,Analog input selection bit [28]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " AN_27 ,Analog input selection bit [27]" "Low,High"
|
|
bitfld.byte 0x00 2. " AN_26 ,Analog input selection bit [26]" "Low,High"
|
|
bitfld.byte 0x00 1. " AN_25 ,Analog input selection bit [25]" "Low,High"
|
|
bitfld.byte 0x00 0. " AN_24 ,Analog input selection bit [24]" "Low,High"
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "SCIS2,Scan Conversion Input Selection Register 2"
|
|
bitfld.byte 0x00 7. " AN_23 ,Analog input selection bit [23]" "Low,High"
|
|
bitfld.byte 0x00 6. " AN_22 ,Analog input selection bit [22]" "Low,High"
|
|
bitfld.byte 0x00 5. " AN_21 ,Analog input selection bit [21]" "Low,High"
|
|
bitfld.byte 0x00 4. " AN_20 ,Analog input selection bit [20]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " AN_19 ,Analog input selection bit [19]" "Low,High"
|
|
bitfld.byte 0x00 2. " AN_18 ,Analog input selection bit [18]" "Low,High"
|
|
bitfld.byte 0x00 1. " AN_17 ,Analog input selection bit [17]" "Low,High"
|
|
bitfld.byte 0x00 0. " AN_16 ,Analog input selection bit [16]" "Low,High"
|
|
rgroup.byte 0x15++0x00
|
|
line.byte 0x00 "SCIS1,Scan Conversion Input Selection Register 1"
|
|
bitfld.byte 0x00 7. " AN_15 ,Analog input selection bit [15]" "Low,High"
|
|
bitfld.byte 0x00 6. " AN_14 ,Analog input selection bit [14]" "Low,High"
|
|
bitfld.byte 0x00 5. " AN_13 ,Analog input selection bit [13]" "Low,High"
|
|
bitfld.byte 0x00 4. " AN_12 ,Analog input selection bit [12]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " AN_11 ,Analog input selection bit [11]" "Low,High"
|
|
bitfld.byte 0x00 2. " AN_10 ,Analog input selection bit [10]" "Low,High"
|
|
bitfld.byte 0x00 1. " AN_9 ,Analog input selection bit [9]" "Low,High"
|
|
bitfld.byte 0x00 0. " AN_8 ,Analog input selection bit [8]" "Low,High"
|
|
rgroup.byte 0x14++0x00
|
|
line.byte 0x00 "SCIS0,Scan Conversion Input Selection Register 0"
|
|
bitfld.byte 0x00 7. " AN_7 ,Analog input selection bit [7]" "Low,High"
|
|
bitfld.byte 0x00 6. " AN_6 ,Analog input selection bit [6]" "Low,High"
|
|
bitfld.byte 0x00 5. " AN_5 ,Analog input selection bit [5]" "Low,High"
|
|
bitfld.byte 0x00 4. " AN_4 ,Analog input selection bit [4]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " AN_3 ,Analog input selection bit [3]" "Low,High"
|
|
bitfld.byte 0x00 2. " AN_2 ,Analog input selection bit [2]" "Low,High"
|
|
bitfld.byte 0x00 1. " AN_1 ,Analog input selection bit [1]" "Low,High"
|
|
bitfld.byte 0x00 0. " AN_0 ,Analog input selection bit [0]" "Low,High"
|
|
endif
|
|
if (per.b(ad:0x40027200)&0x3)==0x0
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "PCCR,Priority Conversion Control Register"
|
|
rbitfld.byte 0x00 7. " PEMP ,Priority conversion FIFO empty bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 6. " PFUL ,Priority conversion FIFO full bit" "Not full,Full"
|
|
bitfld.byte 0x00 5. " POVR ,Priority conversion overrun flag (Read/Write)" "No overrun/Cleared,Overrun/No effect"
|
|
bitfld.byte 0x00 4. " PFCLR ,Priority conversion FIFO clear bit" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ESCE ,External trigger analog input selection bit" "P1A,External"
|
|
bitfld.byte 0x00 2. " PEEN ,Priority conversion external start enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " PHEN ,Priority conversion timer start enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " PSTR ,Priority conversion start bit" "No effect,Started"
|
|
else
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "PCCR,Priority Conversion Control Register"
|
|
rbitfld.byte 0x00 7. " PEMP ,Priority conversion FIFO empty bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 6. " PFUL ,Priority conversion FIFO full bit" "Not full,Full"
|
|
bitfld.byte 0x00 5. " POVR ,Priority conversion overrun flag (Read/Write)" "No overrun/Cleared,Overrun/No effect"
|
|
bitfld.byte 0x00 4. " PFCLR ,Priority conversion FIFO clear bit" "No effect,Cleared"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ESCE ,External trigger analog input selection bit" "P1A,External"
|
|
bitfld.byte 0x00 2. " PEEN ,Priority conversion external start enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " PHEN ,Priority conversion timer start enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " PSTR ,Priority conversion start bit" "No effect,Started"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "PFNS,Priority Conversion FIFO Stage Count Setup Register"
|
|
rbitfld.byte 0x00 4.--5. " TEST ,Test bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--1. " PFS ,Priority conversion FIFO stage count setting bits" "1st,2nd,3rd,4th"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "PCFD,Priority Conversion FIFO Data Register"
|
|
bitfld.long 0x00 31. " PD_11 ,Priority conversion result bit [11]" "Low,High"
|
|
bitfld.long 0x00 30. " PD_10 ,Priority conversion result bit [10]" "Low,High"
|
|
bitfld.long 0x00 29. " PD_9 ,Priority conversion result bit [9]" "Low,High"
|
|
bitfld.long 0x00 28. " PD_8 ,Priority conversion result bit [8]" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PD_7 ,Priority conversion result bit [7]" "Low,High"
|
|
bitfld.long 0x00 26. " PD_6 ,Priority conversion result bit [6]" "Low,High"
|
|
bitfld.long 0x00 25. " PD_5 ,Priority conversion result bit [5]" "Low,High"
|
|
bitfld.long 0x00 24. " PD_4 ,Priority conversion result bit [4]" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PD_3 ,Priority conversion result bit [3]" "Low,High"
|
|
bitfld.long 0x00 22. " PD_2 ,Priority conversion result bit [2]" "Low,High"
|
|
bitfld.long 0x00 21. " PD_1 ,Priority conversion result bit [1]" "Low,High"
|
|
bitfld.long 0x00 20. " PD_0 ,Priority conversion result bit [0]" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " INVL ,A/D conversion result disable bit" "Valid,Invalid"
|
|
bitfld.long 0x00 8.--10. " RS ,Conversion start factor" ",Software,Timer,,External,,,"
|
|
bitfld.long 0x00 0.--4. " PC ,Conversion input channel bits [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (per.b(ad:0x40027200)&0x3)==0x0
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "PCIS,Priority Conversion Input Selection Register"
|
|
sif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C12*")||cpuis("S6E1C32*")
|
|
bitfld.byte 0x00 3.--7. " P2A ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,?..."
|
|
elif cpuis("S6E1A11B")||cpuis("S6E1A12B")
|
|
bitfld.byte 0x00 3.--7. " P2A ,Priority level 2 analog input selection" "0,1,2,3,4,?..."
|
|
elif cpuis("S6E1C11*")||cpuis("S6E1C31*")
|
|
bitfld.byte 0x00 3.--7. " P2A ,Priority level 2 analog input selection" "0,1,2,3,4,5,?..."
|
|
endif
|
|
bitfld.byte 0x00 0.--2. " P1A ,Priority level 1 analog input selection" "0,1,2,3,4,5,6,7"
|
|
else
|
|
rgroup.byte 0x20++0x00
|
|
line.byte 0x00 "PCIS,Priority Conversion Input Selection Register"
|
|
sif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C12*")||cpuis("S6E1C32*")
|
|
bitfld.byte 0x00 3.--7. " P2A ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,?..."
|
|
elif cpuis("S6E1A11B")||cpuis("S6E1A12B")
|
|
bitfld.byte 0x00 3.--7. " P2A ,Priority level 2 analog input selection" "0,1,2,3,4,?..."
|
|
elif cpuis("S6E1C11*")||cpuis("S6E1C31*")
|
|
bitfld.byte 0x00 3.--7. " P2A ,Priority level 2 analog input selection" "0,1,2,3,4,5,?..."
|
|
endif
|
|
bitfld.byte 0x00 0.--2. " P1A ,Priority level 1 analog input selection" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
group.word 0x26++0x01
|
|
line.word 0x00 "CMPD,A/D Comparison Value Setup Register"
|
|
bitfld.word 0x00 15. " CMAD_11 ,A/D conversion result value setting bit [11]" "Low,High"
|
|
bitfld.word 0x00 14. " CMAD_10 ,A/D conversion result value setting bit [10]" "Low,High"
|
|
bitfld.word 0x00 13. " CMAD_9 ,A/D conversion result value setting bit [9]" "Low,High"
|
|
bitfld.word 0x00 12. " CMAD_8 ,A/D conversion result value setting bit [8]" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CMAD_7 ,A/D conversion result value setting bit [7]" "Low,High"
|
|
bitfld.word 0x00 10. " CMAD_6 ,A/D conversion result value setting bit [6]" "Low,High"
|
|
bitfld.word 0x00 9. " CMAD_5 ,A/D conversion result value setting bit [5]" "Low,High"
|
|
bitfld.word 0x00 8. " CMAD_4 ,A/D conversion result value setting bit [4]" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CMAD_3 ,A/D conversion result value setting bit [3]" "Low,High"
|
|
bitfld.word 0x00 6. " CMAD_2 ,A/D conversion result value setting bit [2]" "Low,High"
|
|
if (per.b(ad:0x40027200)&0x3)==0x0
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "CMPCR,A/D Comparison Control Register"
|
|
bitfld.byte 0x00 7. " CMPEN ,Conversion result comparison function operation" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CMD_1 ,Comparison mode 1" "<CMPD,>=CMPD"
|
|
bitfld.byte 0x00 5. " CMD_0 ,Comparison mode 0" "CCH,All"
|
|
sif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C12*")||cpuis("S6E1C32*")
|
|
bitfld.byte 0x00 0.--4. " CCH ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,?..."
|
|
elif cpuis("S6E1A11B")||cpuis("S6E1A12B")
|
|
bitfld.byte 0x00 0.--4. " CCH ,Comparison target analog input channel" "0,1,2,3,4,?..."
|
|
elif cpuis("S6E1C11*")||cpuis("S6E1C31*")
|
|
bitfld.byte 0x00 0.--4. " CCH ,Comparison target analog input channel" "0,1,2,3,4,5,?..."
|
|
endif
|
|
else
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "CMPCR,A/D Comparison Control Register"
|
|
bitfld.byte 0x00 7. " CMPEN ,Conversion result comparison function operation" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 6. " CMD_1 ,Comparison mode 1" "<CMPD,>=CMPD"
|
|
bitfld.byte 0x00 5. " CMD_0 ,Comparison mode 0" "CCH,All"
|
|
sif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C12*")||cpuis("S6E1C32*")
|
|
bitfld.byte 0x00 0.--4. " CCH ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,?..."
|
|
elif cpuis("S6E1A11B")||cpuis("S6E1A12B")
|
|
bitfld.byte 0x00 0.--4. " CCH ,Comparison target analog input channel" "0,1,2,3,4,?..."
|
|
elif cpuis("S6E1C11*")||cpuis("S6E1C31*")
|
|
bitfld.byte 0x00 0.--4. " CCH ,Comparison target analog input channel" "0,1,2,3,4,5,?..."
|
|
endif
|
|
endif
|
|
if (per.b(ad:0x40027200)&0x3)==0x0
|
|
sif !(cpuis("S6E1A11B")||cpuis("S6E1A12B")||cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C12*")||cpuis("S6E1C32*")||cpuis("S6E1C11*")||cpuis("S6E1C31*"))
|
|
group.byte 0x29++0x00
|
|
line.byte 0x00 "ADSS3,Sampling Time Selection Register 3"
|
|
bitfld.byte 0x00 7. " TS_31 ,Sampling time selection bit [31]" "Low,High"
|
|
bitfld.byte 0x00 6. " TS_30 ,Sampling time selection bit [30]" "Low,High"
|
|
bitfld.byte 0x00 5. " TS_29 ,Sampling time selection bit [29]" "Low,High"
|
|
bitfld.byte 0x00 4. " TS_28 ,Sampling time selection bit [28]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_27 ,Sampling time selection bit [27]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_26 ,Sampling time selection bit [26]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_25 ,Sampling time selection bit [25]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_24 ,Sampling time selection bit [24]" "Low,High"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "ADSS2,Sampling Time Selection Register 2"
|
|
bitfld.byte 0x00 7. " TS_23 ,Sampling time selection bit [23]" "Low,High"
|
|
bitfld.byte 0x00 6. " TS_22 ,Sampling time selection bit [22]" "Low,High"
|
|
bitfld.byte 0x00 5. " TS_21 ,Sampling time selection bit [21]" "Low,High"
|
|
bitfld.byte 0x00 4. " TS_20 ,Sampling time selection bit [20]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_19 ,Sampling time selection bit [19]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_18 ,Sampling time selection bit [18]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_17 ,Sampling time selection bit [17]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_16 ,Sampling time selection bit [16]" "Low,High"
|
|
group.byte 0x2D++0x00
|
|
line.byte 0x00 "ADSS1,Sampling Time Selection Register 1"
|
|
bitfld.byte 0x00 7. " TS_15 ,Sampling time selection bit [15]" "Low,High"
|
|
bitfld.byte 0x00 6. " TS_14 ,Sampling time selection bit [14]" "Low,High"
|
|
bitfld.byte 0x00 5. " TS_13 ,Sampling time selection bit [13]" "Low,High"
|
|
bitfld.byte 0x00 4. " TS_12 ,Sampling time selection bit [12]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_11 ,Sampling time selection bit [11]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_10 ,Sampling time selection bit [10]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_9 ,Sampling time selection bit [9]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_8 ,Sampling time selection bit [8]" "Low,High"
|
|
endif
|
|
group.byte 0x2C++0x00
|
|
line.byte 0x00 "ADSS0,Sampling Time Selection Register 0"
|
|
sif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C12*")||cpuis("S6E1C32*")
|
|
bitfld.byte 0x00 7. " TS_7 ,Sampling time selection bit [7]" "Low,High"
|
|
bitfld.byte 0x00 6. " TS_6 ,Sampling time selection bit [6]" "Low,High"
|
|
bitfld.byte 0x00 5. " TS_5 ,Sampling time selection bit [5]" "Low,High"
|
|
bitfld.byte 0x00 4. " TS_4 ,Sampling time selection bit [4]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_3 ,Sampling time selection bit [3]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_2 ,Sampling time selection bit [2]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_1 ,Sampling time selection bit [1]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_0 ,Sampling time selection bit [0]" "Low,High"
|
|
elif cpuis("S6E1A11B")||cpuis("S6E1A12B")
|
|
bitfld.byte 0x00 4. " TS_4 ,Sampling time selection bit [4]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_3 ,Sampling time selection bit [3]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_2 ,Sampling time selection bit [2]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_1 ,Sampling time selection bit [1]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_0 ,Sampling time selection bit [0]" "Low,High"
|
|
elif cpuis("S6E1C11*")||cpuis("S6E1C31*")
|
|
bitfld.byte 0x00 5. " TS_5 ,Sampling time selection bit [5]" "Low,High"
|
|
bitfld.byte 0x00 4. " TS_4 ,Sampling time selection bit [4]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_3 ,Sampling time selection bit [3]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_2 ,Sampling time selection bit [2]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_1 ,Sampling time selection bit [1]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_0 ,Sampling time selection bit [0]" "Low,High"
|
|
endif
|
|
group.byte 0x31++0x00
|
|
line.byte 0x00 "ADST0,Sampling Time Setup Register 0"
|
|
bitfld.byte 0x00 5.--7. " STX_0 ,Sampling time N times setting bits" "x1,x4,x8,x16,x32,x64,x128,x256"
|
|
bitfld.byte 0x00 4. " ST_4 ,Sampling time setting bit [4]" "Low,High"
|
|
bitfld.byte 0x00 3. " ST_3 ,Sampling time setting bit [3]" "Low,High"
|
|
bitfld.byte 0x00 2. " ST_2 ,Sampling time setting bit [2]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " ST_1 ,Sampling time setting bit [1]" "Low,High"
|
|
bitfld.byte 0x00 0. " ST_0 ,Sampling time setting bit [0]" "Low,High"
|
|
group.byte 0x30++0x00
|
|
line.byte 0x00 "ADST1,Sampling Time Setup Register 1"
|
|
bitfld.byte 0x00 5.--7. " STX_1 ,Sampling time N times setting bits" "x1,x4,x8,x16,x32,x64,x128,x256"
|
|
bitfld.byte 0x00 4. " ST_14 ,Sampling time setting bit [14]" "Low,High"
|
|
bitfld.byte 0x00 3. " ST_13 ,Sampling time setting bit [13]" "Low,High"
|
|
bitfld.byte 0x00 2. " ST_12 ,Sampling time setting bit [12]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " ST_11 ,Sampling time setting bit [11]" "Low,High"
|
|
bitfld.byte 0x00 0. " ST_10 ,Sampling time setting bit [10]" "Low,High"
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "ADCT,Comparison Time Setup Register"
|
|
hexmask.byte 0x00 0.--7. 1. " CT ,Frequency division ratio"
|
|
else
|
|
sif !(cpuis("S6E1A11B")||cpuis("S6E1A12B")||cpuis("S6E1A11C")||cpuis("S6E1A12C"))
|
|
rgroup.byte 0x29++0x00
|
|
line.byte 0x00 "ADSS3,Sampling Time Selection Register 3"
|
|
bitfld.byte 0x00 7. " TS_31 ,Sampling time selection bit [31]" "Low,High"
|
|
bitfld.byte 0x00 6. " TS_30 ,Sampling time selection bit [30]" "Low,High"
|
|
bitfld.byte 0x00 5. " TS_29 ,Sampling time selection bit [29]" "Low,High"
|
|
bitfld.byte 0x00 4. " TS_28 ,Sampling time selection bit [28]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_27 ,Sampling time selection bit [27]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_26 ,Sampling time selection bit [26]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_25 ,Sampling time selection bit [25]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_24 ,Sampling time selection bit [24]" "Low,High"
|
|
rgroup.byte 0x28++0x00
|
|
line.byte 0x00 "ADSS2,Sampling Time Selection Register 2"
|
|
bitfld.byte 0x00 7. " TS_23 ,Sampling time selection bit [23]" "Low,High"
|
|
bitfld.byte 0x00 6. " TS_22 ,Sampling time selection bit [22]" "Low,High"
|
|
bitfld.byte 0x00 5. " TS_21 ,Sampling time selection bit [21]" "Low,High"
|
|
bitfld.byte 0x00 4. " TS_20 ,Sampling time selection bit [20]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_19 ,Sampling time selection bit [19]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_18 ,Sampling time selection bit [18]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_17 ,Sampling time selection bit [17]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_16 ,Sampling time selection bit [16]" "Low,High"
|
|
rgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "ADSS1,Sampling Time Selection Register 1"
|
|
bitfld.byte 0x00 7. " TS_15 ,Sampling time selection bit [15]" "Low,High"
|
|
bitfld.byte 0x00 6. " TS_14 ,Sampling time selection bit [14]" "Low,High"
|
|
bitfld.byte 0x00 5. " TS_13 ,Sampling time selection bit [13]" "Low,High"
|
|
bitfld.byte 0x00 4. " TS_12 ,Sampling time selection bit [12]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_11 ,Sampling time selection bit [11]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_10 ,Sampling time selection bit [10]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_9 ,Sampling time selection bit [9]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_8 ,Sampling time selection bit [8]" "Low,High"
|
|
endif
|
|
rgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "ADSS0,Sampling Time Selection Register 0"
|
|
sif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C12*")||cpuis("S6E1C32*")
|
|
bitfld.byte 0x00 7. " TS_7 ,Sampling time selection bit [7]" "Low,High"
|
|
bitfld.byte 0x00 6. " TS_6 ,Sampling time selection bit [6]" "Low,High"
|
|
bitfld.byte 0x00 5. " TS_5 ,Sampling time selection bit [5]" "Low,High"
|
|
bitfld.byte 0x00 4. " TS_4 ,Sampling time selection bit [4]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_3 ,Sampling time selection bit [3]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_2 ,Sampling time selection bit [2]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_1 ,Sampling time selection bit [1]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_0 ,Sampling time selection bit [0]" "Low,High"
|
|
elif cpuis("S6E1A11B")||cpuis("S6E1A12B")||cpuis("S6E1A11C")||cpuis("S6E1A12C")
|
|
bitfld.byte 0x00 4. " TS_4 ,Sampling time selection bit [4]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_3 ,Sampling time selection bit [3]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_2 ,Sampling time selection bit [2]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_1 ,Sampling time selection bit [1]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_0 ,Sampling time selection bit [0]" "Low,High"
|
|
elif cpuis("S6E1C11*")||cpuis("S6E1C31*")
|
|
bitfld.byte 0x00 5. " TS_5 ,Sampling time selection bit [5]" "Low,High"
|
|
bitfld.byte 0x00 4. " TS_4 ,Sampling time selection bit [4]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TS_3 ,Sampling time selection bit [3]" "Low,High"
|
|
bitfld.byte 0x00 2. " TS_2 ,Sampling time selection bit [2]" "Low,High"
|
|
bitfld.byte 0x00 1. " TS_1 ,Sampling time selection bit [1]" "Low,High"
|
|
bitfld.byte 0x00 0. " TS_0 ,Sampling time selection bit [0]" "Low,High"
|
|
endif
|
|
rgroup.byte 0x31++0x00
|
|
line.byte 0x00 "ADST0,Sampling Time Setup Register 0"
|
|
bitfld.byte 0x00 5.--7. " STX_0 ,Sampling time N times setting bits" "x1,x4,x8,x16,x32,x64,x128,x256"
|
|
bitfld.byte 0x00 4. " ST_4 ,Sampling time setting bit [4]" "Low,High"
|
|
bitfld.byte 0x00 3. " ST_3 ,Sampling time setting bit [3]" "Low,High"
|
|
bitfld.byte 0x00 2. " ST_2 ,Sampling time setting bit [2]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " ST_1 ,Sampling time setting bit [1]" "Low,High"
|
|
bitfld.byte 0x00 0. " ST_0 ,Sampling time setting bit [0]" "Low,High"
|
|
rgroup.byte 0x30++0x00
|
|
line.byte 0x00 "ADST1,Sampling Time Setup Register 1"
|
|
bitfld.byte 0x00 5.--7. " STX_1 ,Sampling time N times setting bits" "x1,x4,x8,x16,x32,x64,x128,x256"
|
|
bitfld.byte 0x00 4. " ST_14 ,Sampling time setting bit [14]" "Low,High"
|
|
bitfld.byte 0x00 3. " ST_13 ,Sampling time setting bit [13]" "Low,High"
|
|
bitfld.byte 0x00 2. " ST_12 ,Sampling time setting bit [12]" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " ST_11 ,Sampling time setting bit [11]" "Low,High"
|
|
bitfld.byte 0x00 0. " ST_10 ,Sampling time setting bit [10]" "Low,High"
|
|
rgroup.byte 0x34++0x00
|
|
line.byte 0x00 "ADCT,Comparison Time Setup Register"
|
|
hexmask.byte 0x00 0.--7. 1. " CT ,Frequency division ratio"
|
|
endif
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "ADCEN,A/D Operation Enable Setup Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " ENBLTIME ,Enable state transition cycle selection bits"
|
|
rbitfld.word 0x00 1. " READY ,A/D operation enable state bit" "Stop state,Enable state"
|
|
bitfld.word 0x00 0. " ENBL ,A/D operation enable bit" "Disabled,Enabled"
|
|
group.word 0x52++0x01
|
|
line.word 0x00 "WCMPDH,Upper Limit Setup Register"
|
|
hexmask.word 0x00 6.--15. 0x40 " CMHD ,Upper limit"
|
|
if (per.b(ad:0x40027200+0x4C)&0x4)==0x0
|
|
group.byte 0x4C++0x00
|
|
line.byte 0x00 "WCMPCR,Range Comparison Control Register"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection specification count/state" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Selection bit of within-range and out-of-range confirmation" "Out,Within"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x4C++0x00
|
|
line.byte 0x00 "WCMPCR,Range Comparison Control Register"
|
|
rbitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection specification count/state" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Selection bit of within-range and out-of-range confirmation" "Out,Within"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "WCMPDL,Lower Limit Threshold Setup Register"
|
|
hexmask.word 0x00 6.--15. 0x40 " CMLD ,Lower limit threshold"
|
|
group.byte 0x4D++0x00
|
|
line.byte 0x00 "WCMPSR,Range Comparison Channel Select Register"
|
|
bitfld.byte 0x00 5. " WCMD ,Comparison mode select" "WCCH,All ch."
|
|
sif cpuis("S6E1A11C")||cpuis("S6E1A12C")||cpuis("S6E1C12*")||cpuis("S6E1C32*")
|
|
bitfld.byte 0x00 0.--4. " WCCH ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,?..."
|
|
elif cpuis("S6E1A11B")||cpuis("S6E1A12B")
|
|
bitfld.byte 0x00 0.--4. " WCCH ,Comparison target analog input channel" "0,1,2,3,4,?..."
|
|
elif cpuis("S6E1C11*")||cpuis("S6E1C31*")
|
|
bitfld.byte 0x00 0.--4. " WCCH ,Comparison target analog input channel" "0,1,2,3,4,5,?..."
|
|
endif
|
|
textline " "
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "WCMRCOT,Range Comparison Threshold Excess Flag Register"
|
|
bitfld.long 0x00 0. " RCOOF ,Threshold excess flag" "Below lower limit,Beyond upper limit"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "WCMRCIF,Range Comparison Flag Register"
|
|
bitfld.long 0x00 0. " RCINT ,Range comparison interrupt factor flag" "Clear,Detected"
|
|
tree.open "A/D Timer Trigger Selection"
|
|
width 7.
|
|
group.byte 0x39++0x00
|
|
line.byte 0x00 "SCTSL,Scan Conversion Timer Trigger Selection Register"
|
|
sif cpuis("S6E1C12*")||cpuis("S6E1C32*")
|
|
bitfld.byte 0x00 0.--3. " SCTSL ,Scan conversion timer trigger selection bit" "Not selected,MFT,0,1,2,3,4,5,6,7,?..."
|
|
elif cpuis("S6E1C11*")||cpuis("S6E1C31*")
|
|
bitfld.byte 0x00 0.--3. " SCTSL ,Scan conversion timer trigger selection bit" "Not selected,MFT,0,1,2,3,4,5,?..."
|
|
else
|
|
bitfld.byte 0x00 0.--3. " SCTSL ,Scan conversion timer trigger selection bit" "Not selected,MFT,0,1,2,3,?..."
|
|
endif
|
|
group.byte 0x38++0x00
|
|
line.byte 0x00 "PRTSL,Priority Conversion Timer Trigger Selection Register"
|
|
sif cpuis("S6E1C12*")||cpuis("S6E1C32*")
|
|
bitfld.byte 0x00 0.--3. " SCTSL ,Scan conversion timer trigger selection bit" "Not selected,MFT,0,1,2,3,4,5,6,7,?..."
|
|
elif cpuis("S6E1C11*")||cpuis("S6E1C31*")
|
|
bitfld.byte 0x00 0.--3. " SCTSL ,Scan conversion timer trigger selection bit" "Not selected,MFT,0,1,2,3,4,5,?..."
|
|
else
|
|
bitfld.byte 0x00 0.--3. " PRTSL ,Scan conversion timer trigger selection bit" "Not selected,MFT,0,1,2,3,?..."
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif !cpuis("S6E1C*")
|
|
tree.open "MFS (Multifunction Serial Interface)"
|
|
tree "Channel 0"
|
|
base ad:0x40038000
|
|
width 5.
|
|
if ((d.b(ad:0x40038000)&0xE0)==0x40)
|
|
width 5.
|
|
group.byte 0x00++0x00 "Mode Settings"
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..."
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit (Signal mark level)" "High,Low"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction select" "LSB first,MSB first"
|
|
bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
width 9.
|
|
group.byte 0x01++0x00 "CSIO"
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Cleared"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal synchronous,SPI correspond"
|
|
bitfld.byte 0x00 4. " RIE ,Received interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Data received enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Data transmission enable bit" "Disabled,Enabled"
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Received error flag clear bit" "No effect,Cleared"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Received data full flag bit" "Empty,Not empty"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Not idle,Idle"
|
|
if ((d.b((ad:0x40038000+0x1))&0x43)==0x40)||((d.b((ad:0x40038000+0x30))&0x1E)!=0x0)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmit/received wait select bits" "0-bit,1-bit,2-bit,3-bit"
|
|
bitfld.byte 0x00 0.--2. 6. " L ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
else
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High"
|
|
bitfld.byte 0x00 5. " CSFE ,Serial Chip Select Format enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmit/received wait select bits" "0-bit,1-bit,2-bit,3-bit"
|
|
bitfld.byte 0x00 0.--2. 6. " L ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
endif
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "RDR,Receive Data Register"
|
|
in
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "TDR,Transmit Data Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " D ,Data"
|
|
if ((d.b((ad:0x40038000+0x24))&0x01)==0x01)&&((d.b((ad:0x40038000+0x01))&0x40)==0x00)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "SACSR,Serial Support Control Register"
|
|
bitfld.word 0x00 13. " TBEEN ,Transfer Byte Error Enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CSEIE ,Chip Select Error Interupt Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CES ,Chip Select Error Flag" "No error,Error"
|
|
bitfld.word 0x00 8. " TINT ,Timer Interrupt Flag" "Not requested,Requested"
|
|
bitfld.word 0x00 7. " TINTE ,Timer Interrupt Enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 6. " TSYNE ,Synchronous Transmission Enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer Operation Clock Division bit" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.word 0x00 0. " TMRE ,Serial Timer Enable bit" "Disabled,Enabled"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "STMR,Serial Timer Register"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
elif ((d.b((ad:0x40038000+0x24))&0x01)==0x01)&&((d.b((ad:0x40038000+0x01))&0x40)==0x40)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "SACSR,Serial Support Control Register"
|
|
bitfld.word 0x00 12. " CSEIE ,Chip Select Error Interupt Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CES ,Chip Select Error Flag" "No error,Error"
|
|
bitfld.word 0x00 8. " TINT ,Timer Interrupt Flag" "Not requested,Requested"
|
|
bitfld.word 0x00 7. " TINTE ,Timer Interrupt Enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 6. " TSYNE ,Synchronous Transmission Enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer Operation Clock Division bit" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.word 0x00 0. " TMRE ,Serial Timer Enable bit" "Disabled,Enabled"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "STMR,Serial Timer Register"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
elif ((d.b((ad:0x40038000+0x24))&0x01)==0x00)&&((d.b((ad:0x40038000+0x01))&0x40)==0x00)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "SACSR,Serial Support Control Register"
|
|
bitfld.word 0x00 13. " TBEEN ,Transfer Byte Error Enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CSEIE ,Chip Select Error Interupt Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CES ,Chip Select Error Flag" "No error,Error"
|
|
bitfld.word 0x00 8. " TINT ,Timer Interrupt Flag" "Not requested,Requested"
|
|
bitfld.word 0x00 7. " TINTE ,Timer Interrupt Enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TSYNE ,Synchronous Transmission Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer Operation Clock Division bit" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.word 0x00 0. " TMRE ,Serial Timer Enable bit" "Disabled,Enabled"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "STMR,Serial Timer Register"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
elif ((d.b((ad:0x40038000+0x24))&0x00)==0x00)&&((d.b((ad:0x40038000+0x01))&0x40)==0x40)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "SACSR,Serial Support Control Register"
|
|
bitfld.word 0x00 12. " CSEIE ,Chip Select Error Interupt Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CES ,Chip Select Error Flag" "No error,Error"
|
|
bitfld.word 0x00 8. " TINT ,Timer Interrupt Flag" "Not requested,Requested"
|
|
bitfld.word 0x00 7. " TINTE ,Timer Interrupt Enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TSYNE ,Synchronous Transmission Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer Operation Clock Division bit" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.word 0x00 0. " TMRE ,Serial Timer Enable bit" "Disabled,Enabled"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "STMR,Serial Timer Register"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
if ((d.b((ad:0x40038000+0x1))&0x43)==0x40)
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial Chip Select Active Display bit" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial Chip Select Level Setting bit" "Low,High"
|
|
bitfld.word 0x00 1. " CSEN0 ,SCS0 Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial Chip Select Output Enable bit" "Disabled,Enabled"
|
|
elif ((d.b((ad:0x40038000+0x1))&0x40)==0x40)&&((d.b((ad:0x40038000+0x1))&0x03)!=0x00)
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial Chip Select Active Display bit" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial Chip Select Level Setting bit" "Low,High"
|
|
bitfld.word 0x00 1. " CSEN0 ,SCS0 Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial Chip Select Output Enable bit" "Disabled,Enabled"
|
|
elif ((d.b((ad:0x40038000+0x1))&0x43)==0x00)
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial Chip Select Active Start bit" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial Chip Select Active End bit" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 10.--11. " SCD ,Serial Chip Select Active Display bit" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 9. " SCAM ,Serial Chip Select Active Hold bit" "Not holding,Holding"
|
|
textline " "
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial Chip Select Timing Operation Clock Division bit" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,SCS3 Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CSEN2 ,SCS2 Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,SCS1 Enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,SCS0 Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial Chip Select Output Enable bit" "Disabled,Enabled"
|
|
elif ((d.b((ad:0x40038000+0x1))&0x40)==0x00)&&((d.b((ad:0x40038000+0x1))&0x03)!=0x0)
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial Chip Select Active Start bit" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial Chip Select Active End bit" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial Chip Select Active Display bit" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 9. " SCAM ,Serial Chip Select Active Hold bit" "Not holding,Holding"
|
|
textline " "
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial Chip Select Timing Operation Clock Division bit" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,SCS3 Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CSEN2 ,SCS2 Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,SCS1 Enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,SCS0 Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial Chip Select Output Enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((d.b((ad:0x40038000+0x1))&0x43)==0x00)&&((d.b((ad:0x40038000+0x4))&0x20)==0x20)
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "SCSTR3,Serial Chip Select Timing Register 3"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "SCSTR2,Serial Chip Select Timing Register 2"
|
|
group.byte 0x35++0x00
|
|
line.byte 0x00 "SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x00 7. " CS2CSLVL ,Serial Chip Select 2 Level Setting bit" "Low,High"
|
|
bitfld.byte 0x00 6. " CS2SCINV ,Serial Clock Invert bit of Serial Chip Select 2" "High,Low"
|
|
bitfld.byte 0x00 5. " CS2SPI ,SPI corresponding bit of Serial Chip Select 2" "Normal synchronous,SPI correspond"
|
|
bitfld.byte 0x00 4. " CS2BDS ,Transfer direction select bit of Serial Chip Select" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS2L ,Data length select bits of Serial Chip Select 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Serial Chip Select 1 Level Setting bit" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Serial Clock Invert bit of Serial Chip Select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,SPI corresponding bit of Serial Chip Select 1" "Normal synchronous,SPI correspond"
|
|
bitfld.byte 0x00 4. " CS1BDS ,Transfer direction select bit of Serial Chip Select 1" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Data length select bits of Serial Chip Select 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
group.byte 0x38++0x00
|
|
line.byte 0x00 "SCSFR2,Serial Chip Select Format Register 3"
|
|
bitfld.byte 0x00 7. " CS3CSLVL ,Serial Chip Select 3 Level Setting bit" "Low,High"
|
|
bitfld.byte 0x00 6. " CS3SCINV ,Serial Clock Invert bit of Serial Chip Select 3" "High,Low"
|
|
bitfld.byte 0x00 5. " CS3SPI ,SPI corresponding bit of Serial Chip Select 3" "Normal synchronous,SPI correspond"
|
|
bitfld.byte 0x00 4. " CS3BDS ,Transfer direction select bit of Serial Chip Select" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS3L ,Data length select bits of Serial Chip Select 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
elif ((d.b((ad:0x40038000+0x1))&0x43)==0x00)&&((d.b((ad:0x40038000+0x4))&0x20)==0x00)
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "SCSTR3,Serial Chip Select Timing Register 3"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "SCSTR2,Serial Chip Select Timing Register 2"
|
|
hgroup.byte 0x35++0x00
|
|
hide.byte 0x00 "SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x34++0x00
|
|
hide.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x38++0x00
|
|
hide.byte 0x00 "SCSFR2,Serial Chip Select Format Register 3"
|
|
elif (((d.b((ad:0x40038000+0x1))&0x40)==0x00)&&((d.b((ad:0x40038000+0x1))&0x03)!=0x0))&&((d.b((ad:0x40038000+0x4))&0x20)==0x20)
|
|
rgroup.byte 0x1D++0x00
|
|
line.byte 0x00 "SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.byte 0x1C++0x00
|
|
line.byte 0x00 "SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x21++0x00
|
|
line.byte 0x00 "SCSTR3,Serial Chip Select Timing Register 3"
|
|
rgroup.byte 0x20++0x00
|
|
line.byte 0x00 "SCSTR2,Serial Chip Select Timing Register 2"
|
|
rgroup.byte 0x35++0x00
|
|
line.byte 0x00 "SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x00 7. " CS2CSLVL ,Serial Chip Select 2 Level Setting bit" "Low,High"
|
|
bitfld.byte 0x00 6. " CS2SCINV ,Serial Clock Invert bit of Serial Chip Select 2" "High,Low"
|
|
bitfld.byte 0x00 5. " CS2SPI ,SPI corresponding bit of Serial Chip Select 2" "Normal synchronous,SPI correspond"
|
|
bitfld.byte 0x00 4. " CS2BDS ,Transfer direction select bit of Serial Chip Select" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS2L ,Data length select bits of Serial Chip Select 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
rgroup.byte 0x34++0x00
|
|
line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Serial Chip Select 1 Level Setting bit" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Serial Clock Invert bit of Serial Chip Select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,SPI corresponding bit of Serial Chip Select 1" "Normal synchronous,SPI correspond"
|
|
bitfld.byte 0x00 4. " CS1BDS ,Transfer direction select bit of Serial Chip Select 1" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Data length select bits of Serial Chip Select 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
rgroup.byte 0x38++0x00
|
|
line.byte 0x00 "SCSFR2,Serial Chip Select Format Register 3"
|
|
bitfld.byte 0x00 7. " CS3CSLVL ,Serial Chip Select 3 Level Setting bit" "Low,High"
|
|
bitfld.byte 0x00 6. " CS3SCINV ,Serial Clock Invert bit of Serial Chip Select 3" "High,Low"
|
|
bitfld.byte 0x00 5. " CS3SPI ,SPI corresponding bit of Serial Chip Select 3" "Normal synchronous,SPI correspond"
|
|
bitfld.byte 0x00 4. " CS3BDS ,Transfer direction select bit of Serial Chip Select" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS3L ,Data length select bits of Serial Chip Select 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
elif (((d.b((ad:0x40038000+0x1))&0x40)==0x00)&&((d.b((ad:0x40038000+0x1))&0x03)!=0x0))&&((d.b((ad:0x40038000+0x4))&0x20)==0x00)
|
|
rgroup.byte 0x1D++0x00
|
|
line.byte 0x00 "SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.byte 0x1C++0x00
|
|
line.byte 0x00 "SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x21++0x00
|
|
line.byte 0x00 "SCSTR3,Serial Chip Select Timing Register 3"
|
|
rgroup.byte 0x20++0x00
|
|
line.byte 0x00 "SCSTR2,Serial Chip Select Timing Register 2"
|
|
hgroup.byte 0x35++0x00
|
|
hide.byte 0x00 "SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x34++0x00
|
|
hide.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x38++0x00
|
|
hide.byte 0x00 "SCSFR2,Serial Chip Select Format Register 3"
|
|
else
|
|
hgroup.byte 0x1D++0x00
|
|
hide.byte 0x00 "SCSTR1,Serial Chip Select Timing Register 1"
|
|
hgroup.byte 0x1C++0x00
|
|
hide.byte 0x00 "SCSTR0,Serial Chip Select Timing Register 0"
|
|
hgroup.byte 0x21++0x00
|
|
hide.byte 0x00 "SCSTR3,Serial Chip Select Timing Register 3"
|
|
hgroup.byte 0x20++0x00
|
|
hide.byte 0x00 "SCSTR2,Serial Chip Select Timing Register 2"
|
|
hgroup.byte 0x35++0x00
|
|
hide.byte 0x00 "SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x34++0x00
|
|
hide.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x38++0x00
|
|
hide.byte 0x00 "SCSFR2,Serial Chip Select Format Register 3"
|
|
endif
|
|
if ((d.b((ad:0x40038000+0x1))&0x40)==0x00)
|
|
group.byte 0x3D++0x00
|
|
line.byte 0x00 "TBYTE1,Transfer Byte Register 1"
|
|
group.byte 0x3C++0x00
|
|
line.byte 0x00 "TBYTE0,Transfer Byte Register 0"
|
|
group.byte 0x41++0x00
|
|
line.byte 0x00 "TBYTE3,Transfer Byte Register 3"
|
|
group.byte 0x40++0x00
|
|
line.byte 0x00 "TBYTE2,Transfer Byte Register 2"
|
|
else
|
|
rgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "TBYTE1,Transfer Byte Register 1"
|
|
rgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "TBYTE0,Transfer Byte Register 0"
|
|
rgroup.byte 0x41++0x00
|
|
line.byte 0x00 "TBYTE3,Transfer Byte Register 3"
|
|
rgroup.byte 0x40++0x00
|
|
line.byte 0x00 "TBYTE2,Transfer Byte Register 2"
|
|
endif
|
|
group.byte 0xD++0x00
|
|
line.byte 0x00 "BGR_1,Baud Rate Generator Registers 1"
|
|
hexmask.byte 0x00 0.--6. 1. " BGR1 ,Baud Rate Generator Register 1"
|
|
group.byte 0xC++0x00
|
|
line.byte 0x00 "BGR_0,Baud Rate Generator Registers 0"
|
|
if ((d.b((ad:0x40038000+0x14))&0x3)==0x00)
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmit data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO select bit (Transmit/Receive)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmit data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmit data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO select bit (Transmit/Receive)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmit data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((d.b((ad:0x40038000+0x15))&0x1)==0x1)
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "FBYTE2,FIFO2 Transmit Register"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "FBYTE1,FIFO1 Receive Register"
|
|
else
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "FBYTE2,FIFO2 Receive Register"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "FBYTE1,FIFO1 Transmit Register"
|
|
endif
|
|
width 0xB
|
|
elif ((d.b(ad:0x40038000)&0xE0)==0x60)&&((d.b(ad:0x40038000+0x04)&0x40)==0x40)
|
|
width 5.
|
|
group.byte 0x00++0x00 "Mode Settings"
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..."
|
|
bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
width 9.
|
|
if ((d.b(ad:0x40038000+0x1)&0x40)==0x00)
|
|
group.byte 0x01++0x00 "LIN"
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "Not effect,Cleared"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "Not effected,LIN breakfield"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Received interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Data reception enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Data transmission enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00 "LIN"
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "Not effect,Cleared"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Received interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Data reception enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Data transmission enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Received error flag clear bit" "No effect,Cleared"
|
|
bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (Write/Read)" "Cleared/Not detected,No effect/Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Received data full flag bit" "Not full,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Not idle,Idle"
|
|
if ((d.b(ad:0x40038000)&0x08)==0x00)&&((d.b(ad:0x40038000+0x1)&0x40)==0x00)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1 bit,3 bits"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. " LBL ,Parity select bit" "13-bit,14-bit,15-bit,16-bit"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN Break delimiter length select bits" "1 bit,2 bits,3 bits,4 bits"
|
|
elif ((d.b(ad:0x40038000)&(0x08))==0x08)&&((d.b(ad:0x40038000+0x1)&0x40)==0x00)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "2 bits,4 bits"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. " LBL ,Parity select bit" "13-bit,14-bit,15-bit,16-bit"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN Break delimiter length select bits" "1 bit,2 bits,3 bits,4 bits"
|
|
elif ((d.b(ad:0x40038000)&0x08)==0x00)&&((d.b(ad:0x40038000+0x1)&0x40)==0x40)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1 bit,3 bits"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled"
|
|
elif ((d.b(ad:0x40038000)&(0x08))==0x08)&&((d.b(ad:0x40038000+0x1)&0x40)==0x40)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "2 bits,4 bits"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "RDR,Receive Data Register"
|
|
in
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "TDR,Transmit Data Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " D ,Data"
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "BGR_1,Baud Rate Generator Register 1"
|
|
hexmask.byte 0x00 0.--6. 1. " BGR_1 ,Baud Rate Generator Register 1"
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "BGR_0,Baud Rate Generator Register 0"
|
|
if ((d.b((ad:0x40038000+0x14))&0x3)==0x00)
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmit data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO select bit (Transmit/Receive)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
else
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmit data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO select bit (Transmit/Receive)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
endif
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
if ((d.b(ad:0x40038000+0x15)&0x01)==0x01)
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "FBYTE1,Receive FIFO"
|
|
line.byte 0x01 "FBYTE2,Transmit FIFO"
|
|
else
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "FBYTE1,Transmit FIFO"
|
|
line.byte 0x01 "FBYTE2,Receive FIFO"
|
|
endif
|
|
width 0xB
|
|
elif ((d.b(ad:0x40038000)&0xE0)==0x60)&&((d.b(ad:0x40038000+0x04)&0x40)==0x0)
|
|
width 5.
|
|
group.byte 0x00++0x00 "Mode Settings"
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..."
|
|
bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
width 9.
|
|
if ((d.b(ad:0x40038000+0x1)&0x40)==0x00)
|
|
group.byte 0x01++0x00 "LIN"
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "Not effect,Cleared"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "Not effected,LIN breakfield"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Received interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Data reception enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Data transmission enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00 "LIN"
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "Not effect,Cleared"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Received interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Data reception enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Data transmission enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Received error flag clear bit" "No effect,Cleared"
|
|
bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (Write/Read)" "Cleared/Not detected,No effect/Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Received data full flag bit" "Not full,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Not idle,Idle"
|
|
if ((d.b(ad:0x40038000)&0x08)==0x00)&&((d.b(ad:0x40038000+0x1)&0x40)==0x00)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1 bit,3 bits"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. " LBL ,Parity select bit" "13-bit,14-bit,15-bit,16-bit"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN Break delimiter length select bits" "1 bit,2 bits,3 bits,4 bits"
|
|
elif ((d.b(ad:0x40038000)&(0x08))==0x08)&&((d.b(ad:0x40038000+0x1)&0x40)==0x00)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "2 bits,4 bits"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. " LBL ,Parity select bit" "13-bit,14-bit,15-bit,16-bit"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN Break delimiter length select bits" "1 bit,2 bits,3 bits,4 bits"
|
|
elif ((d.b(ad:0x40038000)&0x08)==0x00)&&((d.b(ad:0x40038000+0x1)&0x40)==0x40)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1 bit,3 bits"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled"
|
|
elif ((d.b(ad:0x40038000)&(0x08))==0x08)&&((d.b(ad:0x40038000+0x1)&0x40)==0x40)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "2 bits,4 bits"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "RDR,Receive Data Register"
|
|
in
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "TDR,Transmit Data Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " D ,Data"
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "BGR_1,Baud Rate Generator Register 1"
|
|
hexmask.byte 0x00 0.--6. 1. " BGR_1 ,Baud Rate Generator Register 1"
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "BGR_0,Baud Rate Generator Register 0"
|
|
if ((d.b((ad:0x40038000+0x14))&0x3)==0x00)
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmit data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO select bit (Transmit/Receive)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
else
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmit data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO select bit (Transmit/Receive)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
endif
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
if ((d.b(ad:0x40038000+0x15)&0x01)==0x01)
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "FBYTE1,Receive FIFO"
|
|
line.byte 0x01 "FBYTE2,Transmit FIFO"
|
|
else
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "FBYTE1,Transmit FIFO"
|
|
line.byte 0x01 "FBYTE2,Receive FIFO"
|
|
endif
|
|
width 0xB
|
|
elif (((d.b(ad:0x40038000)&0xE0)==0x00)||((d.b(ad:0x40038000)&0xE0)==0x20))&&((d.b((ad:0x40038000+0x04))&0x40)==0x40)
|
|
width 5.
|
|
group.byte 0x00++0x00 "Mode Settings"
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction select" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
width 9.
|
|
group.byte 0x01++0x00 "UART"
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Cleared"
|
|
bitfld.byte 0x00 4. " RIE ,Received interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Received operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
if ((d.b(ad:0x40038000)&0xE0)==0x0)
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Received error flag clear bit" "No effect,Cleared"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Received data full flag bit" "Not full,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Not idle,Idle"
|
|
else
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Received error flag clear bit" "No effect,Cleared"
|
|
textline " "
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Received data full flag bit" "Not full,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Not idle,Idle"
|
|
endif
|
|
if ((d.b(ad:0x40038000)&0xE8)==0x28)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "2 bits,4 bits"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted NRZ"
|
|
textline " "
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
elif ((d.b(ad:0x40038000)&0xE8)==0x08)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "2 bits,4 bits"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted NRZ"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length select bit" "8-bit,,,7-bit,,?..."
|
|
elif ((d.b(ad:0x40038000)&0xE8)==0x20)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1 bit,3 bits"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted NRZ"
|
|
textline " "
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
elif ((d.b(ad:0x40038000)&0xE8)==0x00)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1 bit,3 bits"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted NRZ"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length select bit" "8-bit,,,7-bit,,?..."
|
|
endif
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "RDR,Receive Data Register"
|
|
in
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "TDR,Transmit Data Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " D ,Data"
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "BGR_1,Baud Rate Generator Register 1"
|
|
hexmask.byte 0x00 0.--6. 1. " BGR_1 ,Baud Rate Generator Register 1"
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "BGR_0,Baud Rate Generator Register 0"
|
|
if ((d.b((ad:0x40038000+0x14))&0x3)==0x00)
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit"
|
|
else
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit"
|
|
endif
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmit data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
if ((d.b((ad:0x40038000+0x15))&0x01)==0x01)
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "FBYTE1,Receive FIFO"
|
|
line.byte 0x01 "FBYTE2,Transmit FIFO"
|
|
elif ((d.b((ad:0x40038000+0x15))&0x01)==0x00)
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "FBYTE1,Transmit FIFO"
|
|
line.byte 0x01 "FBYTE2,Receive FIFO"
|
|
endif
|
|
width 0xB
|
|
elif (((d.b(ad:0x40038000)&0xE0)==0x00)||((d.b(ad:0x40038000)&0xE0)==0x20))&&((d.b(ad:0x40038000+0x04)&0x40)==0x0)
|
|
width 5.
|
|
group.byte 0x00++0x00 "Mode Settings"
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction select" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
width 9.
|
|
group.byte 0x01++0x00 "UART"
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Cleared"
|
|
bitfld.byte 0x00 4. " RIE ,Received interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Received operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
if ((d.b(ad:0x40038000)&0xE0)==0x0)
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Received error flag clear bit" "No effect,Cleared"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Received data full flag bit" "Not full,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Not idle,Idle"
|
|
else
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Received error flag clear bit" "No effect,Cleared"
|
|
textline " "
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Received data full flag bit" "Not full,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Not idle,Idle"
|
|
endif
|
|
if ((d.b(ad:0x40038000)&0xE8)==0x28)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "2 bits,4 bits"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted NRZ"
|
|
textline " "
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
elif ((d.b(ad:0x40038000)&0xE8)==0x08)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "2 bits,4 bits"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted NRZ"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length select bit" "8-bit,,,7-bit,,?..."
|
|
elif ((d.b(ad:0x40038000)&0xE8)==0x20)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1 bit,3 bits"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted NRZ"
|
|
textline " "
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
elif ((d.b(ad:0x40038000)&0xE8)==0x00)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1 bit,3 bits"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted NRZ"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length select bit" "8-bit,,,7-bit,,?..."
|
|
endif
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "RDR,Receive Data Register"
|
|
in
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "TDR,Transmit Data Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " D ,Data"
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "BGR_1,Baud Rate Generator Register 1"
|
|
hexmask.byte 0x00 0.--6. 1. " BGR_1 ,Baud Rate Generator Register 1"
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "BGR_0,Baud Rate Generator Register 0"
|
|
if ((d.b((ad:0x40038000+0x14))&0x3)==0x00)
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit"
|
|
else
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit"
|
|
endif
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmit data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
if ((d.b((ad:0x40038000+0x15))&0x01)==0x01)
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "FBYTE1,Receive FIFO"
|
|
line.byte 0x01 "FBYTE2,Transmit FIFO"
|
|
elif ((d.b((ad:0x40038000+0x15))&0x01)==0x00)
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "FBYTE1,Transmit FIFO"
|
|
line.byte 0x01 "FBYTE2,Receive FIFO"
|
|
endif
|
|
width 0xB
|
|
elif ((d.b(ad:0x40038000)&0xE0)==0x80)
|
|
width 5.
|
|
group.byte 0x00++0x00 "Mode Settings"
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..."
|
|
bitfld.byte 0x00 3. " RIE ,Received interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled"
|
|
width 9.
|
|
group.byte 0x01++0x00 "I2C"
|
|
line.byte 0x00 "IBCR,I2C Bus Control Register"
|
|
bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master"
|
|
bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit (Read/Write)" "No operation/No effect,I2C/Generated"
|
|
bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "After acknowledgement,After data transfer"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " INT ,Interrupt flag bit (Read/Write)" "Not requested/Cleared,Requested/No effect"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "IBSR,I2C Bus Status Register"
|
|
rbitfld.byte 0x00 7. " FBT ,First byte bit" "Other,First"
|
|
rbitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High"
|
|
rbitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " TRX ,Data direction bit" "Received,Transmission"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy"
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Received error flag clear bit" "No effect,Cleared"
|
|
bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,TDRE=1"
|
|
bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "Not occurred,Occurred"
|
|
rbitfld.byte 0x00 2. " RDRF ,Received data full flag bit" "Empty,Not empty"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Empty,Not empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmit bus idle flag bit" "Busy,Idle"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "RDR,Receive Data Register"
|
|
in
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "TDR,Transmit Data Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " D ,Data"
|
|
if ((d.b(ad:0x40038000+0x11)&0x80)==0x80)&&((d.b(ad:0x40038000+0x1D)&0x2)==0x2)
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "EIBCR,Extension I2C Bus Control Register"
|
|
rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High"
|
|
rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High"
|
|
bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " BEC ,Noise Filter Time" "Aborted,Continued"
|
|
elif ((d.b(ad:0x40038000+0x11)&0x80)==0x80)&&((d.b(ad:0x40038000+0x1D)&0x2)==0x0)
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "EIBCR,Extension I2C Bus Control Register"
|
|
rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High"
|
|
rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " BEC ,Noise Filter Time" "Aborted,Continued"
|
|
elif ((d.b(ad:0x40038000+0x1D)&0x2)==0x2)
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "EIBCR,Extension I2C Bus Control Register"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High"
|
|
bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " BEC ,Noise Filter Time" "Aborted,Continued"
|
|
else
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "EIBCR,Extension I2C Bus Control Register"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " BEC ,Noise Filter Time" "Aborted,Continued"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "ISMK,7-bit Slave Address Mask Register"
|
|
bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked"
|
|
bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked"
|
|
bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked"
|
|
bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked"
|
|
bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked"
|
|
bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked"
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "ISBA,7-bit Slave Address Register"
|
|
bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled"
|
|
hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address"
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "BGR_1,Baud Rate Generator Register 1"
|
|
hexmask.byte 0x00 0.--6. 1. " BGR_1 ,Baud Rate Generator Register 1"
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "BGR_0,Baud Rate Generator Register 0"
|
|
if ((d.b((ad:0x40038000+0x14))&0x3)==0x00)
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmit data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO select bit (Transmit/Receive)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
else
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmit data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO select bit (Transmit/Receive)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
endif
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
if ((d.b(ad:0x40038000+0x15)&0x01)==0x01)
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "FBYTE1,Receive FIFO"
|
|
line.byte 0x01 "FBYTE2,Transmit FIFO"
|
|
else
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "FBYTE1,Transmit FIFO"
|
|
line.byte 0x01 "FBYTE2,Receive FIFO"
|
|
endif
|
|
width 0xB
|
|
else
|
|
width 5.
|
|
group.byte 0x00++0x00 "Mode Settings"
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..."
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0x40038100
|
|
width 5.
|
|
if ((d.b(ad:0x40038100)&0xE0)==0x40)
|
|
width 5.
|
|
group.byte 0x00++0x00 "Mode Settings"
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..."
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit (Signal mark level)" "High,Low"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction select" "LSB first,MSB first"
|
|
bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
width 9.
|
|
group.byte 0x01++0x00 "CSIO"
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Cleared"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal synchronous,SPI correspond"
|
|
bitfld.byte 0x00 4. " RIE ,Received interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Data received enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Data transmission enable bit" "Disabled,Enabled"
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Received error flag clear bit" "No effect,Cleared"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Received data full flag bit" "Empty,Not empty"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Not idle,Idle"
|
|
if ((d.b((ad:0x40038100+0x1))&0x43)==0x40)||((d.b((ad:0x40038100+0x30))&0x1E)!=0x0)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmit/received wait select bits" "0-bit,1-bit,2-bit,3-bit"
|
|
bitfld.byte 0x00 0.--2. 6. " L ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
else
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High"
|
|
bitfld.byte 0x00 5. " CSFE ,Serial Chip Select Format enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmit/received wait select bits" "0-bit,1-bit,2-bit,3-bit"
|
|
bitfld.byte 0x00 0.--2. 6. " L ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
endif
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "RDR,Receive Data Register"
|
|
in
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "TDR,Transmit Data Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " D ,Data"
|
|
if ((d.b((ad:0x40038100+0x24))&0x01)==0x01)&&((d.b((ad:0x40038100+0x01))&0x40)==0x00)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "SACSR,Serial Support Control Register"
|
|
bitfld.word 0x00 13. " TBEEN ,Transfer Byte Error Enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CSEIE ,Chip Select Error Interupt Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CES ,Chip Select Error Flag" "No error,Error"
|
|
bitfld.word 0x00 8. " TINT ,Timer Interrupt Flag" "Not requested,Requested"
|
|
bitfld.word 0x00 7. " TINTE ,Timer Interrupt Enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 6. " TSYNE ,Synchronous Transmission Enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer Operation Clock Division bit" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.word 0x00 0. " TMRE ,Serial Timer Enable bit" "Disabled,Enabled"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "STMR,Serial Timer Register"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
elif ((d.b((ad:0x40038100+0x24))&0x01)==0x01)&&((d.b((ad:0x40038100+0x01))&0x40)==0x40)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "SACSR,Serial Support Control Register"
|
|
bitfld.word 0x00 12. " CSEIE ,Chip Select Error Interupt Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CES ,Chip Select Error Flag" "No error,Error"
|
|
bitfld.word 0x00 8. " TINT ,Timer Interrupt Flag" "Not requested,Requested"
|
|
bitfld.word 0x00 7. " TINTE ,Timer Interrupt Enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 6. " TSYNE ,Synchronous Transmission Enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer Operation Clock Division bit" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.word 0x00 0. " TMRE ,Serial Timer Enable bit" "Disabled,Enabled"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "STMR,Serial Timer Register"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
elif ((d.b((ad:0x40038100+0x24))&0x01)==0x00)&&((d.b((ad:0x40038100+0x01))&0x40)==0x00)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "SACSR,Serial Support Control Register"
|
|
bitfld.word 0x00 13. " TBEEN ,Transfer Byte Error Enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CSEIE ,Chip Select Error Interupt Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CES ,Chip Select Error Flag" "No error,Error"
|
|
bitfld.word 0x00 8. " TINT ,Timer Interrupt Flag" "Not requested,Requested"
|
|
bitfld.word 0x00 7. " TINTE ,Timer Interrupt Enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TSYNE ,Synchronous Transmission Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer Operation Clock Division bit" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.word 0x00 0. " TMRE ,Serial Timer Enable bit" "Disabled,Enabled"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "STMR,Serial Timer Register"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
elif ((d.b((ad:0x40038100+0x24))&0x00)==0x00)&&((d.b((ad:0x40038100+0x01))&0x40)==0x40)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "SACSR,Serial Support Control Register"
|
|
bitfld.word 0x00 12. " CSEIE ,Chip Select Error Interupt Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CES ,Chip Select Error Flag" "No error,Error"
|
|
bitfld.word 0x00 8. " TINT ,Timer Interrupt Flag" "Not requested,Requested"
|
|
bitfld.word 0x00 7. " TINTE ,Timer Interrupt Enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TSYNE ,Synchronous Transmission Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer Operation Clock Division bit" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.word 0x00 0. " TMRE ,Serial Timer Enable bit" "Disabled,Enabled"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "STMR,Serial Timer Register"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
if ((d.b((ad:0x40038100+0x1))&0x43)==0x40)
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial Chip Select Active Display bit" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial Chip Select Level Setting bit" "Low,High"
|
|
bitfld.word 0x00 1. " CSEN0 ,SCS0 Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial Chip Select Output Enable bit" "Disabled,Enabled"
|
|
elif ((d.b((ad:0x40038100+0x1))&0x40)==0x40)&&((d.b((ad:0x40038100+0x1))&0x03)!=0x00)
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial Chip Select Active Display bit" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial Chip Select Level Setting bit" "Low,High"
|
|
bitfld.word 0x00 1. " CSEN0 ,SCS0 Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial Chip Select Output Enable bit" "Disabled,Enabled"
|
|
elif ((d.b((ad:0x40038100+0x1))&0x43)==0x00)
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial Chip Select Active Start bit" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial Chip Select Active End bit" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 10.--11. " SCD ,Serial Chip Select Active Display bit" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 9. " SCAM ,Serial Chip Select Active Hold bit" "Not holding,Holding"
|
|
textline " "
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial Chip Select Timing Operation Clock Division bit" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,SCS3 Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CSEN2 ,SCS2 Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,SCS1 Enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,SCS0 Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial Chip Select Output Enable bit" "Disabled,Enabled"
|
|
elif ((d.b((ad:0x40038100+0x1))&0x40)==0x00)&&((d.b((ad:0x40038100+0x1))&0x03)!=0x0)
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial Chip Select Active Start bit" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial Chip Select Active End bit" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial Chip Select Active Display bit" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 9. " SCAM ,Serial Chip Select Active Hold bit" "Not holding,Holding"
|
|
textline " "
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial Chip Select Timing Operation Clock Division bit" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,SCS3 Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CSEN2 ,SCS2 Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,SCS1 Enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,SCS0 Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial Chip Select Output Enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((d.b((ad:0x40038100+0x1))&0x43)==0x00)&&((d.b((ad:0x40038100+0x4))&0x20)==0x20)
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "SCSTR3,Serial Chip Select Timing Register 3"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "SCSTR2,Serial Chip Select Timing Register 2"
|
|
group.byte 0x35++0x00
|
|
line.byte 0x00 "SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x00 7. " CS2CSLVL ,Serial Chip Select 2 Level Setting bit" "Low,High"
|
|
bitfld.byte 0x00 6. " CS2SCINV ,Serial Clock Invert bit of Serial Chip Select 2" "High,Low"
|
|
bitfld.byte 0x00 5. " CS2SPI ,SPI corresponding bit of Serial Chip Select 2" "Normal synchronous,SPI correspond"
|
|
bitfld.byte 0x00 4. " CS2BDS ,Transfer direction select bit of Serial Chip Select" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS2L ,Data length select bits of Serial Chip Select 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Serial Chip Select 1 Level Setting bit" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Serial Clock Invert bit of Serial Chip Select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,SPI corresponding bit of Serial Chip Select 1" "Normal synchronous,SPI correspond"
|
|
bitfld.byte 0x00 4. " CS1BDS ,Transfer direction select bit of Serial Chip Select 1" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Data length select bits of Serial Chip Select 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
group.byte 0x38++0x00
|
|
line.byte 0x00 "SCSFR2,Serial Chip Select Format Register 3"
|
|
bitfld.byte 0x00 7. " CS3CSLVL ,Serial Chip Select 3 Level Setting bit" "Low,High"
|
|
bitfld.byte 0x00 6. " CS3SCINV ,Serial Clock Invert bit of Serial Chip Select 3" "High,Low"
|
|
bitfld.byte 0x00 5. " CS3SPI ,SPI corresponding bit of Serial Chip Select 3" "Normal synchronous,SPI correspond"
|
|
bitfld.byte 0x00 4. " CS3BDS ,Transfer direction select bit of Serial Chip Select" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS3L ,Data length select bits of Serial Chip Select 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
elif ((d.b((ad:0x40038100+0x1))&0x43)==0x00)&&((d.b((ad:0x40038100+0x4))&0x20)==0x00)
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "SCSTR3,Serial Chip Select Timing Register 3"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "SCSTR2,Serial Chip Select Timing Register 2"
|
|
hgroup.byte 0x35++0x00
|
|
hide.byte 0x00 "SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x34++0x00
|
|
hide.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x38++0x00
|
|
hide.byte 0x00 "SCSFR2,Serial Chip Select Format Register 3"
|
|
elif (((d.b((ad:0x40038100+0x1))&0x40)==0x00)&&((d.b((ad:0x40038100+0x1))&0x03)!=0x0))&&((d.b((ad:0x40038100+0x4))&0x20)==0x20)
|
|
rgroup.byte 0x1D++0x00
|
|
line.byte 0x00 "SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.byte 0x1C++0x00
|
|
line.byte 0x00 "SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x21++0x00
|
|
line.byte 0x00 "SCSTR3,Serial Chip Select Timing Register 3"
|
|
rgroup.byte 0x20++0x00
|
|
line.byte 0x00 "SCSTR2,Serial Chip Select Timing Register 2"
|
|
rgroup.byte 0x35++0x00
|
|
line.byte 0x00 "SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x00 7. " CS2CSLVL ,Serial Chip Select 2 Level Setting bit" "Low,High"
|
|
bitfld.byte 0x00 6. " CS2SCINV ,Serial Clock Invert bit of Serial Chip Select 2" "High,Low"
|
|
bitfld.byte 0x00 5. " CS2SPI ,SPI corresponding bit of Serial Chip Select 2" "Normal synchronous,SPI correspond"
|
|
bitfld.byte 0x00 4. " CS2BDS ,Transfer direction select bit of Serial Chip Select" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS2L ,Data length select bits of Serial Chip Select 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
rgroup.byte 0x34++0x00
|
|
line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Serial Chip Select 1 Level Setting bit" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Serial Clock Invert bit of Serial Chip Select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,SPI corresponding bit of Serial Chip Select 1" "Normal synchronous,SPI correspond"
|
|
bitfld.byte 0x00 4. " CS1BDS ,Transfer direction select bit of Serial Chip Select 1" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Data length select bits of Serial Chip Select 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
rgroup.byte 0x38++0x00
|
|
line.byte 0x00 "SCSFR2,Serial Chip Select Format Register 3"
|
|
bitfld.byte 0x00 7. " CS3CSLVL ,Serial Chip Select 3 Level Setting bit" "Low,High"
|
|
bitfld.byte 0x00 6. " CS3SCINV ,Serial Clock Invert bit of Serial Chip Select 3" "High,Low"
|
|
bitfld.byte 0x00 5. " CS3SPI ,SPI corresponding bit of Serial Chip Select 3" "Normal synchronous,SPI correspond"
|
|
bitfld.byte 0x00 4. " CS3BDS ,Transfer direction select bit of Serial Chip Select" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS3L ,Data length select bits of Serial Chip Select 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
elif (((d.b((ad:0x40038100+0x1))&0x40)==0x00)&&((d.b((ad:0x40038100+0x1))&0x03)!=0x0))&&((d.b((ad:0x40038100+0x4))&0x20)==0x00)
|
|
rgroup.byte 0x1D++0x00
|
|
line.byte 0x00 "SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.byte 0x1C++0x00
|
|
line.byte 0x00 "SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x21++0x00
|
|
line.byte 0x00 "SCSTR3,Serial Chip Select Timing Register 3"
|
|
rgroup.byte 0x20++0x00
|
|
line.byte 0x00 "SCSTR2,Serial Chip Select Timing Register 2"
|
|
hgroup.byte 0x35++0x00
|
|
hide.byte 0x00 "SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x34++0x00
|
|
hide.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x38++0x00
|
|
hide.byte 0x00 "SCSFR2,Serial Chip Select Format Register 3"
|
|
else
|
|
hgroup.byte 0x1D++0x00
|
|
hide.byte 0x00 "SCSTR1,Serial Chip Select Timing Register 1"
|
|
hgroup.byte 0x1C++0x00
|
|
hide.byte 0x00 "SCSTR0,Serial Chip Select Timing Register 0"
|
|
hgroup.byte 0x21++0x00
|
|
hide.byte 0x00 "SCSTR3,Serial Chip Select Timing Register 3"
|
|
hgroup.byte 0x20++0x00
|
|
hide.byte 0x00 "SCSTR2,Serial Chip Select Timing Register 2"
|
|
hgroup.byte 0x35++0x00
|
|
hide.byte 0x00 "SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x34++0x00
|
|
hide.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x38++0x00
|
|
hide.byte 0x00 "SCSFR2,Serial Chip Select Format Register 3"
|
|
endif
|
|
if ((d.b((ad:0x40038100+0x1))&0x40)==0x00)
|
|
group.byte 0x3D++0x00
|
|
line.byte 0x00 "TBYTE1,Transfer Byte Register 1"
|
|
group.byte 0x3C++0x00
|
|
line.byte 0x00 "TBYTE0,Transfer Byte Register 0"
|
|
group.byte 0x41++0x00
|
|
line.byte 0x00 "TBYTE3,Transfer Byte Register 3"
|
|
group.byte 0x40++0x00
|
|
line.byte 0x00 "TBYTE2,Transfer Byte Register 2"
|
|
else
|
|
rgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "TBYTE1,Transfer Byte Register 1"
|
|
rgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "TBYTE0,Transfer Byte Register 0"
|
|
rgroup.byte 0x41++0x00
|
|
line.byte 0x00 "TBYTE3,Transfer Byte Register 3"
|
|
rgroup.byte 0x40++0x00
|
|
line.byte 0x00 "TBYTE2,Transfer Byte Register 2"
|
|
endif
|
|
group.byte 0xD++0x00
|
|
line.byte 0x00 "BGR_1,Baud Rate Generator Registers 1"
|
|
hexmask.byte 0x00 0.--6. 1. " BGR1 ,Baud Rate Generator Register 1"
|
|
group.byte 0xC++0x00
|
|
line.byte 0x00 "BGR_0,Baud Rate Generator Registers 0"
|
|
if ((d.b((ad:0x40038100+0x14))&0x3)==0x00)
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmit data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO select bit (Transmit/Receive)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmit data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmit data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO select bit (Transmit/Receive)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmit data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((d.b((ad:0x40038100+0x15))&0x1)==0x1)
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "FBYTE2,FIFO2 Transmit Register"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "FBYTE1,FIFO1 Receive Register"
|
|
else
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "FBYTE2,FIFO2 Receive Register"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "FBYTE1,FIFO1 Transmit Register"
|
|
endif
|
|
width 0xB
|
|
elif ((d.b(ad:0x40038100)&0xE0)==0x60)&&((d.b(ad:0x40038100+0x04)&0x40)==0x40)
|
|
width 5.
|
|
group.byte 0x00++0x00 "Mode Settings"
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..."
|
|
bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
width 9.
|
|
if ((d.b(ad:0x40038100+0x1)&0x40)==0x00)
|
|
group.byte 0x01++0x00 "LIN"
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "Not effect,Cleared"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "Not effected,LIN breakfield"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Received interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Data reception enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Data transmission enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00 "LIN"
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "Not effect,Cleared"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Received interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Data reception enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Data transmission enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Received error flag clear bit" "No effect,Cleared"
|
|
bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (Write/Read)" "Cleared/Not detected,No effect/Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Received data full flag bit" "Not full,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Not idle,Idle"
|
|
if ((d.b(ad:0x40038100)&0x08)==0x00)&&((d.b(ad:0x40038100+0x1)&0x40)==0x00)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1 bit,3 bits"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. " LBL ,Parity select bit" "13-bit,14-bit,15-bit,16-bit"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN Break delimiter length select bits" "1 bit,2 bits,3 bits,4 bits"
|
|
elif ((d.b(ad:0x40038100)&(0x08))==0x08)&&((d.b(ad:0x40038100+0x1)&0x40)==0x00)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "2 bits,4 bits"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. " LBL ,Parity select bit" "13-bit,14-bit,15-bit,16-bit"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN Break delimiter length select bits" "1 bit,2 bits,3 bits,4 bits"
|
|
elif ((d.b(ad:0x40038100)&0x08)==0x00)&&((d.b(ad:0x40038100+0x1)&0x40)==0x40)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1 bit,3 bits"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled"
|
|
elif ((d.b(ad:0x40038100)&(0x08))==0x08)&&((d.b(ad:0x40038100+0x1)&0x40)==0x40)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "2 bits,4 bits"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "RDR,Receive Data Register"
|
|
in
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "TDR,Transmit Data Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " D ,Data"
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "BGR_1,Baud Rate Generator Register 1"
|
|
hexmask.byte 0x00 0.--6. 1. " BGR_1 ,Baud Rate Generator Register 1"
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "BGR_0,Baud Rate Generator Register 0"
|
|
if ((d.b((ad:0x40038100+0x14))&0x3)==0x00)
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmit data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO select bit (Transmit/Receive)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
else
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmit data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO select bit (Transmit/Receive)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
endif
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
if ((d.b(ad:0x40038100+0x15)&0x01)==0x01)
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "FBYTE1,Receive FIFO"
|
|
line.byte 0x01 "FBYTE2,Transmit FIFO"
|
|
else
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "FBYTE1,Transmit FIFO"
|
|
line.byte 0x01 "FBYTE2,Receive FIFO"
|
|
endif
|
|
width 0xB
|
|
elif ((d.b(ad:0x40038100)&0xE0)==0x60)&&((d.b(ad:0x40038100+0x04)&0x40)==0x0)
|
|
width 5.
|
|
group.byte 0x00++0x00 "Mode Settings"
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..."
|
|
bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
width 9.
|
|
if ((d.b(ad:0x40038100+0x1)&0x40)==0x00)
|
|
group.byte 0x01++0x00 "LIN"
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "Not effect,Cleared"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "Not effected,LIN breakfield"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Received interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Data reception enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Data transmission enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00 "LIN"
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "Not effect,Cleared"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Received interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Data reception enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Data transmission enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Received error flag clear bit" "No effect,Cleared"
|
|
bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (Write/Read)" "Cleared/Not detected,No effect/Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Received data full flag bit" "Not full,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Not idle,Idle"
|
|
if ((d.b(ad:0x40038100)&0x08)==0x00)&&((d.b(ad:0x40038100+0x1)&0x40)==0x00)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1 bit,3 bits"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. " LBL ,Parity select bit" "13-bit,14-bit,15-bit,16-bit"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN Break delimiter length select bits" "1 bit,2 bits,3 bits,4 bits"
|
|
elif ((d.b(ad:0x40038100)&(0x08))==0x08)&&((d.b(ad:0x40038100+0x1)&0x40)==0x00)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "2 bits,4 bits"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. " LBL ,Parity select bit" "13-bit,14-bit,15-bit,16-bit"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN Break delimiter length select bits" "1 bit,2 bits,3 bits,4 bits"
|
|
elif ((d.b(ad:0x40038100)&0x08)==0x00)&&((d.b(ad:0x40038100+0x1)&0x40)==0x40)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1 bit,3 bits"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled"
|
|
elif ((d.b(ad:0x40038100)&(0x08))==0x08)&&((d.b(ad:0x40038100+0x1)&0x40)==0x40)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "2 bits,4 bits"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "RDR,Receive Data Register"
|
|
in
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "TDR,Transmit Data Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " D ,Data"
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "BGR_1,Baud Rate Generator Register 1"
|
|
hexmask.byte 0x00 0.--6. 1. " BGR_1 ,Baud Rate Generator Register 1"
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "BGR_0,Baud Rate Generator Register 0"
|
|
if ((d.b((ad:0x40038100+0x14))&0x3)==0x00)
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmit data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO select bit (Transmit/Receive)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
else
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmit data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO select bit (Transmit/Receive)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
endif
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
if ((d.b(ad:0x40038100+0x15)&0x01)==0x01)
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "FBYTE1,Receive FIFO"
|
|
line.byte 0x01 "FBYTE2,Transmit FIFO"
|
|
else
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "FBYTE1,Transmit FIFO"
|
|
line.byte 0x01 "FBYTE2,Receive FIFO"
|
|
endif
|
|
width 0xB
|
|
elif (((d.b(ad:0x40038100)&0xE0)==0x00)||((d.b(ad:0x40038100)&0xE0)==0x20))&&((d.b((ad:0x40038100+0x04))&0x40)==0x40)
|
|
width 5.
|
|
group.byte 0x00++0x00 "Mode Settings"
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction select" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
width 9.
|
|
group.byte 0x01++0x00 "UART"
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Cleared"
|
|
bitfld.byte 0x00 4. " RIE ,Received interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Received operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
if ((d.b(ad:0x40038100)&0xE0)==0x0)
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Received error flag clear bit" "No effect,Cleared"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Received data full flag bit" "Not full,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Not idle,Idle"
|
|
else
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Received error flag clear bit" "No effect,Cleared"
|
|
textline " "
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Received data full flag bit" "Not full,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Not idle,Idle"
|
|
endif
|
|
if ((d.b(ad:0x40038100)&0xE8)==0x28)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "2 bits,4 bits"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted NRZ"
|
|
textline " "
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
elif ((d.b(ad:0x40038100)&0xE8)==0x08)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "2 bits,4 bits"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted NRZ"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length select bit" "8-bit,,,7-bit,,?..."
|
|
elif ((d.b(ad:0x40038100)&0xE8)==0x20)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1 bit,3 bits"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted NRZ"
|
|
textline " "
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
elif ((d.b(ad:0x40038100)&0xE8)==0x00)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1 bit,3 bits"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted NRZ"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length select bit" "8-bit,,,7-bit,,?..."
|
|
endif
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "RDR,Receive Data Register"
|
|
in
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "TDR,Transmit Data Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " D ,Data"
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "BGR_1,Baud Rate Generator Register 1"
|
|
hexmask.byte 0x00 0.--6. 1. " BGR_1 ,Baud Rate Generator Register 1"
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "BGR_0,Baud Rate Generator Register 0"
|
|
if ((d.b((ad:0x40038100+0x14))&0x3)==0x00)
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit"
|
|
else
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit"
|
|
endif
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmit data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
if ((d.b((ad:0x40038100+0x15))&0x01)==0x01)
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "FBYTE1,Receive FIFO"
|
|
line.byte 0x01 "FBYTE2,Transmit FIFO"
|
|
elif ((d.b((ad:0x40038100+0x15))&0x01)==0x00)
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "FBYTE1,Transmit FIFO"
|
|
line.byte 0x01 "FBYTE2,Receive FIFO"
|
|
endif
|
|
width 0xB
|
|
elif (((d.b(ad:0x40038100)&0xE0)==0x00)||((d.b(ad:0x40038100)&0xE0)==0x20))&&((d.b(ad:0x40038100+0x04)&0x40)==0x0)
|
|
width 5.
|
|
group.byte 0x00++0x00 "Mode Settings"
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction select" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
width 9.
|
|
group.byte 0x01++0x00 "UART"
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Cleared"
|
|
bitfld.byte 0x00 4. " RIE ,Received interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Received operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
if ((d.b(ad:0x40038100)&0xE0)==0x0)
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Received error flag clear bit" "No effect,Cleared"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Received data full flag bit" "Not full,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Not idle,Idle"
|
|
else
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Received error flag clear bit" "No effect,Cleared"
|
|
textline " "
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Received data full flag bit" "Not full,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Not idle,Idle"
|
|
endif
|
|
if ((d.b(ad:0x40038100)&0xE8)==0x28)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "2 bits,4 bits"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted NRZ"
|
|
textline " "
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
elif ((d.b(ad:0x40038100)&0xE8)==0x08)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "2 bits,4 bits"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted NRZ"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length select bit" "8-bit,,,7-bit,,?..."
|
|
elif ((d.b(ad:0x40038100)&0xE8)==0x20)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1 bit,3 bits"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted NRZ"
|
|
textline " "
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
elif ((d.b(ad:0x40038100)&0xE8)==0x00)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1 bit,3 bits"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted NRZ"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length select bit" "8-bit,,,7-bit,,?..."
|
|
endif
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "RDR,Receive Data Register"
|
|
in
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "TDR,Transmit Data Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " D ,Data"
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "BGR_1,Baud Rate Generator Register 1"
|
|
hexmask.byte 0x00 0.--6. 1. " BGR_1 ,Baud Rate Generator Register 1"
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "BGR_0,Baud Rate Generator Register 0"
|
|
if ((d.b((ad:0x40038100+0x14))&0x3)==0x00)
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit"
|
|
else
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit"
|
|
endif
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmit data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
if ((d.b((ad:0x40038100+0x15))&0x01)==0x01)
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "FBYTE1,Receive FIFO"
|
|
line.byte 0x01 "FBYTE2,Transmit FIFO"
|
|
elif ((d.b((ad:0x40038100+0x15))&0x01)==0x00)
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "FBYTE1,Transmit FIFO"
|
|
line.byte 0x01 "FBYTE2,Receive FIFO"
|
|
endif
|
|
width 0xB
|
|
elif ((d.b(ad:0x40038100)&0xE0)==0x80)
|
|
width 5.
|
|
group.byte 0x00++0x00 "Mode Settings"
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..."
|
|
bitfld.byte 0x00 3. " RIE ,Received interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled"
|
|
width 9.
|
|
group.byte 0x01++0x00 "I2C"
|
|
line.byte 0x00 "IBCR,I2C Bus Control Register"
|
|
bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master"
|
|
bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit (Read/Write)" "No operation/No effect,I2C/Generated"
|
|
bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "After acknowledgement,After data transfer"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " INT ,Interrupt flag bit (Read/Write)" "Not requested/Cleared,Requested/No effect"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "IBSR,I2C Bus Status Register"
|
|
rbitfld.byte 0x00 7. " FBT ,First byte bit" "Other,First"
|
|
rbitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High"
|
|
rbitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " TRX ,Data direction bit" "Received,Transmission"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy"
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Received error flag clear bit" "No effect,Cleared"
|
|
bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,TDRE=1"
|
|
bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "Not occurred,Occurred"
|
|
rbitfld.byte 0x00 2. " RDRF ,Received data full flag bit" "Empty,Not empty"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Empty,Not empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmit bus idle flag bit" "Busy,Idle"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "RDR,Receive Data Register"
|
|
in
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "TDR,Transmit Data Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " D ,Data"
|
|
if ((d.b(ad:0x40038100+0x11)&0x80)==0x80)&&((d.b(ad:0x40038100+0x1D)&0x2)==0x2)
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "EIBCR,Extension I2C Bus Control Register"
|
|
rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High"
|
|
rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High"
|
|
bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " BEC ,Noise Filter Time" "Aborted,Continued"
|
|
elif ((d.b(ad:0x40038100+0x11)&0x80)==0x80)&&((d.b(ad:0x40038100+0x1D)&0x2)==0x0)
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "EIBCR,Extension I2C Bus Control Register"
|
|
rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High"
|
|
rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " BEC ,Noise Filter Time" "Aborted,Continued"
|
|
elif ((d.b(ad:0x40038100+0x1D)&0x2)==0x2)
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "EIBCR,Extension I2C Bus Control Register"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High"
|
|
bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " BEC ,Noise Filter Time" "Aborted,Continued"
|
|
else
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "EIBCR,Extension I2C Bus Control Register"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " BEC ,Noise Filter Time" "Aborted,Continued"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "ISMK,7-bit Slave Address Mask Register"
|
|
bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked"
|
|
bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked"
|
|
bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked"
|
|
bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked"
|
|
bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked"
|
|
bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked"
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "ISBA,7-bit Slave Address Register"
|
|
bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled"
|
|
hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address"
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "BGR_1,Baud Rate Generator Register 1"
|
|
hexmask.byte 0x00 0.--6. 1. " BGR_1 ,Baud Rate Generator Register 1"
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "BGR_0,Baud Rate Generator Register 0"
|
|
if ((d.b((ad:0x40038100+0x14))&0x3)==0x00)
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmit data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO select bit (Transmit/Receive)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
else
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmit data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO select bit (Transmit/Receive)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
endif
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
if ((d.b(ad:0x40038100+0x15)&0x01)==0x01)
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "FBYTE1,Receive FIFO"
|
|
line.byte 0x01 "FBYTE2,Transmit FIFO"
|
|
else
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "FBYTE1,Transmit FIFO"
|
|
line.byte 0x01 "FBYTE2,Receive FIFO"
|
|
endif
|
|
width 0xB
|
|
else
|
|
width 5.
|
|
group.byte 0x00++0x00 "Mode Settings"
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..."
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 2"
|
|
base ad:0x40038200
|
|
width 5.
|
|
if ((d.b(ad:0x40038200)&0xE0)==0x40)
|
|
width 5.
|
|
group.byte 0x00++0x00 "Mode Settings"
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..."
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit (Signal mark level)" "High,Low"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction select" "LSB first,MSB first"
|
|
bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
width 9.
|
|
group.byte 0x01++0x00 "CSIO"
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Cleared"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal synchronous,SPI correspond"
|
|
bitfld.byte 0x00 4. " RIE ,Received interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Data received enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Data transmission enable bit" "Disabled,Enabled"
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Received error flag clear bit" "No effect,Cleared"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Received data full flag bit" "Empty,Not empty"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Not idle,Idle"
|
|
if ((d.b((ad:0x40038200+0x1))&0x43)==0x40)||((d.b((ad:0x40038200+0x30))&0x1E)!=0x0)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmit/received wait select bits" "0-bit,1-bit,2-bit,3-bit"
|
|
bitfld.byte 0x00 0.--2. 6. " L ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
else
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High"
|
|
bitfld.byte 0x00 5. " CSFE ,Serial Chip Select Format enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmit/received wait select bits" "0-bit,1-bit,2-bit,3-bit"
|
|
bitfld.byte 0x00 0.--2. 6. " L ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
endif
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "RDR,Receive Data Register"
|
|
in
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "TDR,Transmit Data Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " D ,Data"
|
|
if ((d.b((ad:0x40038200+0x24))&0x01)==0x01)&&((d.b((ad:0x40038200+0x01))&0x40)==0x00)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "SACSR,Serial Support Control Register"
|
|
bitfld.word 0x00 13. " TBEEN ,Transfer Byte Error Enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CSEIE ,Chip Select Error Interupt Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CES ,Chip Select Error Flag" "No error,Error"
|
|
bitfld.word 0x00 8. " TINT ,Timer Interrupt Flag" "Not requested,Requested"
|
|
bitfld.word 0x00 7. " TINTE ,Timer Interrupt Enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 6. " TSYNE ,Synchronous Transmission Enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer Operation Clock Division bit" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.word 0x00 0. " TMRE ,Serial Timer Enable bit" "Disabled,Enabled"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "STMR,Serial Timer Register"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
elif ((d.b((ad:0x40038200+0x24))&0x01)==0x01)&&((d.b((ad:0x40038200+0x01))&0x40)==0x40)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "SACSR,Serial Support Control Register"
|
|
bitfld.word 0x00 12. " CSEIE ,Chip Select Error Interupt Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CES ,Chip Select Error Flag" "No error,Error"
|
|
bitfld.word 0x00 8. " TINT ,Timer Interrupt Flag" "Not requested,Requested"
|
|
bitfld.word 0x00 7. " TINTE ,Timer Interrupt Enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 6. " TSYNE ,Synchronous Transmission Enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer Operation Clock Division bit" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.word 0x00 0. " TMRE ,Serial Timer Enable bit" "Disabled,Enabled"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "STMR,Serial Timer Register"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
elif ((d.b((ad:0x40038200+0x24))&0x01)==0x00)&&((d.b((ad:0x40038200+0x01))&0x40)==0x00)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "SACSR,Serial Support Control Register"
|
|
bitfld.word 0x00 13. " TBEEN ,Transfer Byte Error Enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CSEIE ,Chip Select Error Interupt Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CES ,Chip Select Error Flag" "No error,Error"
|
|
bitfld.word 0x00 8. " TINT ,Timer Interrupt Flag" "Not requested,Requested"
|
|
bitfld.word 0x00 7. " TINTE ,Timer Interrupt Enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TSYNE ,Synchronous Transmission Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer Operation Clock Division bit" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.word 0x00 0. " TMRE ,Serial Timer Enable bit" "Disabled,Enabled"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "STMR,Serial Timer Register"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
elif ((d.b((ad:0x40038200+0x24))&0x00)==0x00)&&((d.b((ad:0x40038200+0x01))&0x40)==0x40)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "SACSR,Serial Support Control Register"
|
|
bitfld.word 0x00 12. " CSEIE ,Chip Select Error Interupt Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CES ,Chip Select Error Flag" "No error,Error"
|
|
bitfld.word 0x00 8. " TINT ,Timer Interrupt Flag" "Not requested,Requested"
|
|
bitfld.word 0x00 7. " TINTE ,Timer Interrupt Enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TSYNE ,Synchronous Transmission Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer Operation Clock Division bit" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
bitfld.word 0x00 0. " TMRE ,Serial Timer Enable bit" "Disabled,Enabled"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "STMR,Serial Timer Register"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
if ((d.b((ad:0x40038200+0x1))&0x43)==0x40)
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial Chip Select Active Display bit" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial Chip Select Level Setting bit" "Low,High"
|
|
bitfld.word 0x00 1. " CSEN0 ,SCS0 Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial Chip Select Output Enable bit" "Disabled,Enabled"
|
|
elif ((d.b((ad:0x40038200+0x1))&0x40)==0x40)&&((d.b((ad:0x40038200+0x1))&0x03)!=0x00)
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial Chip Select Active Display bit" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial Chip Select Level Setting bit" "Low,High"
|
|
bitfld.word 0x00 1. " CSEN0 ,SCS0 Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial Chip Select Output Enable bit" "Disabled,Enabled"
|
|
elif ((d.b((ad:0x40038200+0x1))&0x43)==0x00)
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial Chip Select Active Start bit" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial Chip Select Active End bit" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 10.--11. " SCD ,Serial Chip Select Active Display bit" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 9. " SCAM ,Serial Chip Select Active Hold bit" "Not holding,Holding"
|
|
textline " "
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial Chip Select Timing Operation Clock Division bit" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,SCS3 Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CSEN2 ,SCS2 Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,SCS1 Enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,SCS0 Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial Chip Select Output Enable bit" "Disabled,Enabled"
|
|
elif ((d.b((ad:0x40038200+0x1))&0x40)==0x00)&&((d.b((ad:0x40038200+0x1))&0x03)!=0x0)
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial Chip Select Active Start bit" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial Chip Select Active End bit" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial Chip Select Active Display bit" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 9. " SCAM ,Serial Chip Select Active Hold bit" "Not holding,Holding"
|
|
textline " "
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial Chip Select Timing Operation Clock Division bit" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,SCS3 Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CSEN2 ,SCS2 Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,SCS1 Enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,SCS0 Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial Chip Select Output Enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((d.b((ad:0x40038200+0x1))&0x43)==0x00)&&((d.b((ad:0x40038200+0x4))&0x20)==0x20)
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "SCSTR3,Serial Chip Select Timing Register 3"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "SCSTR2,Serial Chip Select Timing Register 2"
|
|
group.byte 0x35++0x00
|
|
line.byte 0x00 "SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x00 7. " CS2CSLVL ,Serial Chip Select 2 Level Setting bit" "Low,High"
|
|
bitfld.byte 0x00 6. " CS2SCINV ,Serial Clock Invert bit of Serial Chip Select 2" "High,Low"
|
|
bitfld.byte 0x00 5. " CS2SPI ,SPI corresponding bit of Serial Chip Select 2" "Normal synchronous,SPI correspond"
|
|
bitfld.byte 0x00 4. " CS2BDS ,Transfer direction select bit of Serial Chip Select" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS2L ,Data length select bits of Serial Chip Select 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Serial Chip Select 1 Level Setting bit" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Serial Clock Invert bit of Serial Chip Select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,SPI corresponding bit of Serial Chip Select 1" "Normal synchronous,SPI correspond"
|
|
bitfld.byte 0x00 4. " CS1BDS ,Transfer direction select bit of Serial Chip Select 1" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Data length select bits of Serial Chip Select 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
group.byte 0x38++0x00
|
|
line.byte 0x00 "SCSFR2,Serial Chip Select Format Register 3"
|
|
bitfld.byte 0x00 7. " CS3CSLVL ,Serial Chip Select 3 Level Setting bit" "Low,High"
|
|
bitfld.byte 0x00 6. " CS3SCINV ,Serial Clock Invert bit of Serial Chip Select 3" "High,Low"
|
|
bitfld.byte 0x00 5. " CS3SPI ,SPI corresponding bit of Serial Chip Select 3" "Normal synchronous,SPI correspond"
|
|
bitfld.byte 0x00 4. " CS3BDS ,Transfer direction select bit of Serial Chip Select" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS3L ,Data length select bits of Serial Chip Select 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
elif ((d.b((ad:0x40038200+0x1))&0x43)==0x00)&&((d.b((ad:0x40038200+0x4))&0x20)==0x00)
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "SCSTR3,Serial Chip Select Timing Register 3"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "SCSTR2,Serial Chip Select Timing Register 2"
|
|
hgroup.byte 0x35++0x00
|
|
hide.byte 0x00 "SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x34++0x00
|
|
hide.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x38++0x00
|
|
hide.byte 0x00 "SCSFR2,Serial Chip Select Format Register 3"
|
|
elif (((d.b((ad:0x40038200+0x1))&0x40)==0x00)&&((d.b((ad:0x40038200+0x1))&0x03)!=0x0))&&((d.b((ad:0x40038200+0x4))&0x20)==0x20)
|
|
rgroup.byte 0x1D++0x00
|
|
line.byte 0x00 "SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.byte 0x1C++0x00
|
|
line.byte 0x00 "SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x21++0x00
|
|
line.byte 0x00 "SCSTR3,Serial Chip Select Timing Register 3"
|
|
rgroup.byte 0x20++0x00
|
|
line.byte 0x00 "SCSTR2,Serial Chip Select Timing Register 2"
|
|
rgroup.byte 0x35++0x00
|
|
line.byte 0x00 "SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x00 7. " CS2CSLVL ,Serial Chip Select 2 Level Setting bit" "Low,High"
|
|
bitfld.byte 0x00 6. " CS2SCINV ,Serial Clock Invert bit of Serial Chip Select 2" "High,Low"
|
|
bitfld.byte 0x00 5. " CS2SPI ,SPI corresponding bit of Serial Chip Select 2" "Normal synchronous,SPI correspond"
|
|
bitfld.byte 0x00 4. " CS2BDS ,Transfer direction select bit of Serial Chip Select" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS2L ,Data length select bits of Serial Chip Select 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
rgroup.byte 0x34++0x00
|
|
line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Serial Chip Select 1 Level Setting bit" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Serial Clock Invert bit of Serial Chip Select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,SPI corresponding bit of Serial Chip Select 1" "Normal synchronous,SPI correspond"
|
|
bitfld.byte 0x00 4. " CS1BDS ,Transfer direction select bit of Serial Chip Select 1" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Data length select bits of Serial Chip Select 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
rgroup.byte 0x38++0x00
|
|
line.byte 0x00 "SCSFR2,Serial Chip Select Format Register 3"
|
|
bitfld.byte 0x00 7. " CS3CSLVL ,Serial Chip Select 3 Level Setting bit" "Low,High"
|
|
bitfld.byte 0x00 6. " CS3SCINV ,Serial Clock Invert bit of Serial Chip Select 3" "High,Low"
|
|
bitfld.byte 0x00 5. " CS3SPI ,SPI corresponding bit of Serial Chip Select 3" "Normal synchronous,SPI correspond"
|
|
bitfld.byte 0x00 4. " CS3BDS ,Transfer direction select bit of Serial Chip Select" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " CS3L ,Data length select bits of Serial Chip Select 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..."
|
|
elif (((d.b((ad:0x40038200+0x1))&0x40)==0x00)&&((d.b((ad:0x40038200+0x1))&0x03)!=0x0))&&((d.b((ad:0x40038200+0x4))&0x20)==0x00)
|
|
rgroup.byte 0x1D++0x00
|
|
line.byte 0x00 "SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.byte 0x1C++0x00
|
|
line.byte 0x00 "SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x21++0x00
|
|
line.byte 0x00 "SCSTR3,Serial Chip Select Timing Register 3"
|
|
rgroup.byte 0x20++0x00
|
|
line.byte 0x00 "SCSTR2,Serial Chip Select Timing Register 2"
|
|
hgroup.byte 0x35++0x00
|
|
hide.byte 0x00 "SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x34++0x00
|
|
hide.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x38++0x00
|
|
hide.byte 0x00 "SCSFR2,Serial Chip Select Format Register 3"
|
|
else
|
|
hgroup.byte 0x1D++0x00
|
|
hide.byte 0x00 "SCSTR1,Serial Chip Select Timing Register 1"
|
|
hgroup.byte 0x1C++0x00
|
|
hide.byte 0x00 "SCSTR0,Serial Chip Select Timing Register 0"
|
|
hgroup.byte 0x21++0x00
|
|
hide.byte 0x00 "SCSTR3,Serial Chip Select Timing Register 3"
|
|
hgroup.byte 0x20++0x00
|
|
hide.byte 0x00 "SCSTR2,Serial Chip Select Timing Register 2"
|
|
hgroup.byte 0x35++0x00
|
|
hide.byte 0x00 "SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x34++0x00
|
|
hide.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x38++0x00
|
|
hide.byte 0x00 "SCSFR2,Serial Chip Select Format Register 3"
|
|
endif
|
|
if ((d.b((ad:0x40038200+0x1))&0x40)==0x00)
|
|
group.byte 0x3D++0x00
|
|
line.byte 0x00 "TBYTE1,Transfer Byte Register 1"
|
|
group.byte 0x3C++0x00
|
|
line.byte 0x00 "TBYTE0,Transfer Byte Register 0"
|
|
group.byte 0x41++0x00
|
|
line.byte 0x00 "TBYTE3,Transfer Byte Register 3"
|
|
group.byte 0x40++0x00
|
|
line.byte 0x00 "TBYTE2,Transfer Byte Register 2"
|
|
else
|
|
rgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "TBYTE1,Transfer Byte Register 1"
|
|
rgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "TBYTE0,Transfer Byte Register 0"
|
|
rgroup.byte 0x41++0x00
|
|
line.byte 0x00 "TBYTE3,Transfer Byte Register 3"
|
|
rgroup.byte 0x40++0x00
|
|
line.byte 0x00 "TBYTE2,Transfer Byte Register 2"
|
|
endif
|
|
group.byte 0xD++0x00
|
|
line.byte 0x00 "BGR_1,Baud Rate Generator Registers 1"
|
|
hexmask.byte 0x00 0.--6. 1. " BGR1 ,Baud Rate Generator Register 1"
|
|
group.byte 0xC++0x00
|
|
line.byte 0x00 "BGR_0,Baud Rate Generator Registers 0"
|
|
if ((d.b((ad:0x40038200+0x14))&0x3)==0x00)
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmit data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO select bit (Transmit/Receive)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmit data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmit data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO select bit (Transmit/Receive)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmit data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((d.b((ad:0x40038200+0x15))&0x1)==0x1)
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "FBYTE2,FIFO2 Transmit Register"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "FBYTE1,FIFO1 Receive Register"
|
|
else
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "FBYTE2,FIFO2 Receive Register"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "FBYTE1,FIFO1 Transmit Register"
|
|
endif
|
|
width 0xB
|
|
elif ((d.b(ad:0x40038200)&0xE0)==0x60)&&((d.b(ad:0x40038200+0x04)&0x40)==0x40)
|
|
width 5.
|
|
group.byte 0x00++0x00 "Mode Settings"
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..."
|
|
bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
width 9.
|
|
if ((d.b(ad:0x40038200+0x1)&0x40)==0x00)
|
|
group.byte 0x01++0x00 "LIN"
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "Not effect,Cleared"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "Not effected,LIN breakfield"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Received interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Data reception enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Data transmission enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00 "LIN"
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "Not effect,Cleared"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Received interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Data reception enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Data transmission enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Received error flag clear bit" "No effect,Cleared"
|
|
bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (Write/Read)" "Cleared/Not detected,No effect/Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Received data full flag bit" "Not full,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Not idle,Idle"
|
|
if ((d.b(ad:0x40038200)&0x08)==0x00)&&((d.b(ad:0x40038200+0x1)&0x40)==0x00)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1 bit,3 bits"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. " LBL ,Parity select bit" "13-bit,14-bit,15-bit,16-bit"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN Break delimiter length select bits" "1 bit,2 bits,3 bits,4 bits"
|
|
elif ((d.b(ad:0x40038200)&(0x08))==0x08)&&((d.b(ad:0x40038200+0x1)&0x40)==0x00)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "2 bits,4 bits"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. " LBL ,Parity select bit" "13-bit,14-bit,15-bit,16-bit"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN Break delimiter length select bits" "1 bit,2 bits,3 bits,4 bits"
|
|
elif ((d.b(ad:0x40038200)&0x08)==0x00)&&((d.b(ad:0x40038200+0x1)&0x40)==0x40)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1 bit,3 bits"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled"
|
|
elif ((d.b(ad:0x40038200)&(0x08))==0x08)&&((d.b(ad:0x40038200+0x1)&0x40)==0x40)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "2 bits,4 bits"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "RDR,Receive Data Register"
|
|
in
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "TDR,Transmit Data Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " D ,Data"
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "BGR_1,Baud Rate Generator Register 1"
|
|
hexmask.byte 0x00 0.--6. 1. " BGR_1 ,Baud Rate Generator Register 1"
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "BGR_0,Baud Rate Generator Register 0"
|
|
if ((d.b((ad:0x40038200+0x14))&0x3)==0x00)
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmit data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO select bit (Transmit/Receive)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
else
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmit data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO select bit (Transmit/Receive)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
endif
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
if ((d.b(ad:0x40038200+0x15)&0x01)==0x01)
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "FBYTE1,Receive FIFO"
|
|
line.byte 0x01 "FBYTE2,Transmit FIFO"
|
|
else
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "FBYTE1,Transmit FIFO"
|
|
line.byte 0x01 "FBYTE2,Receive FIFO"
|
|
endif
|
|
width 0xB
|
|
elif ((d.b(ad:0x40038200)&0xE0)==0x60)&&((d.b(ad:0x40038200+0x04)&0x40)==0x0)
|
|
width 5.
|
|
group.byte 0x00++0x00 "Mode Settings"
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..."
|
|
bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
width 9.
|
|
if ((d.b(ad:0x40038200+0x1)&0x40)==0x00)
|
|
group.byte 0x01++0x00 "LIN"
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "Not effect,Cleared"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "Not effected,LIN breakfield"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Received interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Data reception enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Data transmission enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00 "LIN"
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "Not effect,Cleared"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Received interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Data reception enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Data transmission enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Received error flag clear bit" "No effect,Cleared"
|
|
bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (Write/Read)" "Cleared/Not detected,No effect/Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Received data full flag bit" "Not full,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Not idle,Idle"
|
|
if ((d.b(ad:0x40038200)&0x08)==0x00)&&((d.b(ad:0x40038200+0x1)&0x40)==0x00)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1 bit,3 bits"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. " LBL ,Parity select bit" "13-bit,14-bit,15-bit,16-bit"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN Break delimiter length select bits" "1 bit,2 bits,3 bits,4 bits"
|
|
elif ((d.b(ad:0x40038200)&(0x08))==0x08)&&((d.b(ad:0x40038200+0x1)&0x40)==0x00)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "2 bits,4 bits"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. " LBL ,Parity select bit" "13-bit,14-bit,15-bit,16-bit"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN Break delimiter length select bits" "1 bit,2 bits,3 bits,4 bits"
|
|
elif ((d.b(ad:0x40038200)&0x08)==0x00)&&((d.b(ad:0x40038200+0x1)&0x40)==0x40)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1 bit,3 bits"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled"
|
|
elif ((d.b(ad:0x40038200)&(0x08))==0x08)&&((d.b(ad:0x40038200+0x1)&0x40)==0x40)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "2 bits,4 bits"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "RDR,Receive Data Register"
|
|
in
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "TDR,Transmit Data Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " D ,Data"
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "BGR_1,Baud Rate Generator Register 1"
|
|
hexmask.byte 0x00 0.--6. 1. " BGR_1 ,Baud Rate Generator Register 1"
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "BGR_0,Baud Rate Generator Register 0"
|
|
if ((d.b((ad:0x40038200+0x14))&0x3)==0x00)
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmit data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO select bit (Transmit/Receive)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
else
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmit data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO select bit (Transmit/Receive)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
endif
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
if ((d.b(ad:0x40038200+0x15)&0x01)==0x01)
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "FBYTE1,Receive FIFO"
|
|
line.byte 0x01 "FBYTE2,Transmit FIFO"
|
|
else
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "FBYTE1,Transmit FIFO"
|
|
line.byte 0x01 "FBYTE2,Receive FIFO"
|
|
endif
|
|
width 0xB
|
|
elif (((d.b(ad:0x40038200)&0xE0)==0x00)||((d.b(ad:0x40038200)&0xE0)==0x20))&&((d.b((ad:0x40038200+0x04))&0x40)==0x40)
|
|
width 5.
|
|
group.byte 0x00++0x00 "Mode Settings"
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction select" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
width 9.
|
|
group.byte 0x01++0x00 "UART"
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Cleared"
|
|
bitfld.byte 0x00 4. " RIE ,Received interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Received operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
if ((d.b(ad:0x40038200)&0xE0)==0x0)
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Received error flag clear bit" "No effect,Cleared"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Received data full flag bit" "Not full,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Not idle,Idle"
|
|
else
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Received error flag clear bit" "No effect,Cleared"
|
|
textline " "
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Received data full flag bit" "Not full,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Not idle,Idle"
|
|
endif
|
|
if ((d.b(ad:0x40038200)&0xE8)==0x28)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "2 bits,4 bits"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted NRZ"
|
|
textline " "
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
elif ((d.b(ad:0x40038200)&0xE8)==0x08)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "2 bits,4 bits"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted NRZ"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length select bit" "8-bit,,,7-bit,,?..."
|
|
elif ((d.b(ad:0x40038200)&0xE8)==0x20)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1 bit,3 bits"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted NRZ"
|
|
textline " "
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
elif ((d.b(ad:0x40038200)&0xE8)==0x00)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1 bit,3 bits"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted NRZ"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length select bit" "8-bit,,,7-bit,,?..."
|
|
endif
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "RDR,Receive Data Register"
|
|
in
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "TDR,Transmit Data Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " D ,Data"
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "BGR_1,Baud Rate Generator Register 1"
|
|
hexmask.byte 0x00 0.--6. 1. " BGR_1 ,Baud Rate Generator Register 1"
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "BGR_0,Baud Rate Generator Register 0"
|
|
if ((d.b((ad:0x40038200+0x14))&0x3)==0x00)
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit"
|
|
else
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit"
|
|
endif
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmit data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
if ((d.b((ad:0x40038200+0x15))&0x01)==0x01)
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "FBYTE1,Receive FIFO"
|
|
line.byte 0x01 "FBYTE2,Transmit FIFO"
|
|
elif ((d.b((ad:0x40038200+0x15))&0x01)==0x00)
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "FBYTE1,Transmit FIFO"
|
|
line.byte 0x01 "FBYTE2,Receive FIFO"
|
|
endif
|
|
width 0xB
|
|
elif (((d.b(ad:0x40038200)&0xE0)==0x00)||((d.b(ad:0x40038200)&0xE0)==0x20))&&((d.b(ad:0x40038200+0x04)&0x40)==0x0)
|
|
width 5.
|
|
group.byte 0x00++0x00 "Mode Settings"
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..."
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction select" "LSB first,MSB first"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
width 9.
|
|
group.byte 0x01++0x00 "UART"
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Cleared"
|
|
bitfld.byte 0x00 4. " RIE ,Received interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Received operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
if ((d.b(ad:0x40038200)&0xE0)==0x0)
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Received error flag clear bit" "No effect,Cleared"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Received data full flag bit" "Not full,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Not idle,Idle"
|
|
else
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Received error flag clear bit" "No effect,Cleared"
|
|
textline " "
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Received data full flag bit" "Not full,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Not idle,Idle"
|
|
endif
|
|
if ((d.b(ad:0x40038200)&0xE8)==0x28)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "2 bits,4 bits"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted NRZ"
|
|
textline " "
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
elif ((d.b(ad:0x40038200)&0xE8)==0x08)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "2 bits,4 bits"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted NRZ"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length select bit" "8-bit,,,7-bit,,?..."
|
|
elif ((d.b(ad:0x40038200)&0xE8)==0x20)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1 bit,3 bits"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted NRZ"
|
|
textline " "
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
elif ((d.b(ad:0x40038200)&0xE8)==0x00)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1 bit,3 bits"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted NRZ"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length select bit" "8-bit,,,7-bit,,?..."
|
|
endif
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "RDR,Receive Data Register"
|
|
in
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "TDR,Transmit Data Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " D ,Data"
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "BGR_1,Baud Rate Generator Register 1"
|
|
hexmask.byte 0x00 0.--6. 1. " BGR_1 ,Baud Rate Generator Register 1"
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "BGR_0,Baud Rate Generator Register 0"
|
|
if ((d.b((ad:0x40038200+0x14))&0x3)==0x00)
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit"
|
|
else
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit"
|
|
endif
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmit data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
if ((d.b((ad:0x40038200+0x15))&0x01)==0x01)
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "FBYTE1,Receive FIFO"
|
|
line.byte 0x01 "FBYTE2,Transmit FIFO"
|
|
elif ((d.b((ad:0x40038200+0x15))&0x01)==0x00)
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "FBYTE1,Transmit FIFO"
|
|
line.byte 0x01 "FBYTE2,Receive FIFO"
|
|
endif
|
|
width 0xB
|
|
elif ((d.b(ad:0x40038200)&0xE0)==0x80)
|
|
width 5.
|
|
group.byte 0x00++0x00 "Mode Settings"
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..."
|
|
bitfld.byte 0x00 3. " RIE ,Received interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled"
|
|
width 9.
|
|
group.byte 0x01++0x00 "I2C"
|
|
line.byte 0x00 "IBCR,I2C Bus Control Register"
|
|
bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master"
|
|
bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit (Read/Write)" "No operation/No effect,I2C/Generated"
|
|
bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "After acknowledgement,After data transfer"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " INT ,Interrupt flag bit (Read/Write)" "Not requested/Cleared,Requested/No effect"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "IBSR,I2C Bus Status Register"
|
|
rbitfld.byte 0x00 7. " FBT ,First byte bit" "Other,First"
|
|
rbitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High"
|
|
rbitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " TRX ,Data direction bit" "Received,Transmission"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy"
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Received error flag clear bit" "No effect,Cleared"
|
|
bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,TDRE=1"
|
|
bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "Not occurred,Occurred"
|
|
rbitfld.byte 0x00 2. " RDRF ,Received data full flag bit" "Empty,Not empty"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Empty,Not empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmit bus idle flag bit" "Busy,Idle"
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "RDR,Receive Data Register"
|
|
in
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "TDR,Transmit Data Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " D ,Data"
|
|
if ((d.b(ad:0x40038200+0x11)&0x80)==0x80)&&((d.b(ad:0x40038200+0x1D)&0x2)==0x2)
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "EIBCR,Extension I2C Bus Control Register"
|
|
rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High"
|
|
rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High"
|
|
bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " BEC ,Noise Filter Time" "Aborted,Continued"
|
|
elif ((d.b(ad:0x40038200+0x11)&0x80)==0x80)&&((d.b(ad:0x40038200+0x1D)&0x2)==0x0)
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "EIBCR,Extension I2C Bus Control Register"
|
|
rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High"
|
|
rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " BEC ,Noise Filter Time" "Aborted,Continued"
|
|
elif ((d.b(ad:0x40038200+0x1D)&0x2)==0x2)
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "EIBCR,Extension I2C Bus Control Register"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High"
|
|
bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " BEC ,Noise Filter Time" "Aborted,Continued"
|
|
else
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "EIBCR,Extension I2C Bus Control Register"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " BEC ,Noise Filter Time" "Aborted,Continued"
|
|
endif
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "ISMK,7-bit Slave Address Mask Register"
|
|
bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked"
|
|
bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked"
|
|
bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked"
|
|
bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked"
|
|
bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked"
|
|
bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked"
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "ISBA,7-bit Slave Address Register"
|
|
bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled"
|
|
hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address"
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "BGR_1,Baud Rate Generator Register 1"
|
|
hexmask.byte 0x00 0.--6. 1. " BGR_1 ,Baud Rate Generator Register 1"
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "BGR_0,Baud Rate Generator Register 0"
|
|
if ((d.b((ad:0x40038200+0x14))&0x3)==0x00)
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmit data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO select bit (Transmit/Receive)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
else
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmit data lost detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Received FIFO idle detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested"
|
|
bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO select bit (Transmit/Receive)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
endif
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
if ((d.b(ad:0x40038200+0x15)&0x01)==0x01)
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "FBYTE1,Receive FIFO"
|
|
line.byte 0x01 "FBYTE2,Transmit FIFO"
|
|
else
|
|
group.byte 0x18++0x01
|
|
line.byte 0x00 "FBYTE1,Transmit FIFO"
|
|
line.byte 0x01 "FBYTE2,Receive FIFO"
|
|
endif
|
|
width 0xB
|
|
else
|
|
width 5.
|
|
group.byte 0x00++0x00 "Mode Settings"
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..."
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif !cpuis("S6E1C*")
|
|
tree.open "CEC"
|
|
tree "Reception"
|
|
tree "Channel 0"
|
|
base ad:0x40034000
|
|
width 8.
|
|
group.byte 0x41++0x00
|
|
line.byte 0x00 "RCCR,Reception Control Register"
|
|
bitfld.byte 0x00 7. " THSEL ,Threshold value selection bit" "0 data,1 data"
|
|
bitfld.byte 0x00 3. " ADRCE ,Address comparison enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1.--2. " MOD ,Operation mode setting bits" "SIRCS,,NEC,HDMI-CEC"
|
|
bitfld.byte 0x00 0. " EN ,Operation enable bit" "Disabled,Enabled"
|
|
group.byte 0x40++0x00
|
|
line.byte 0x00 "RCST,Reception Interrupt Control Register"
|
|
bitfld.byte 0x00 7. " STIE ,Start bit interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ACKIE ,ACK interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " OVFIE ,Counter overflow interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " OVFSEL ,Counter overflow detection condition setting bit" "128 clocks,256 clocks"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ST ,Start bit detection bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " ACK ,ACK detection bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 1. " EOM ,EOM detection bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " OVF ,Counter overflow detection bit" "Not detected,Detected"
|
|
group.byte 0x4C++0x01
|
|
line.byte 0x00 "RCADR2,Device Address Setting Register 2"
|
|
bitfld.byte 0x00 0.--4. " RCADR2 ,Device address setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x01 "RCADR1,Device Address Setting Register 1"
|
|
bitfld.byte 0x01 0.--4. " RCADR1 ,Device address setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x45++0x00
|
|
line.byte 0x00 "RCSHW,Start Bit Detection Width Setting Register"
|
|
group.byte 0x44++0x00
|
|
line.byte 0x00 "RCDAHW,Minimum Pulse Width Setting Register"
|
|
group.byte 0x49++0x00
|
|
line.byte 0x00 "RCDBHW,Threshold Value Setting Register"
|
|
rgroup.byte 0x50++0x00
|
|
line.byte 0x00 "RCDTHH,Data Save Register HH"
|
|
rgroup.byte 0x49++0x00
|
|
line.byte 0x00 "RCDTHL,Data Save Register HL"
|
|
rgroup.byte 0x54++0x00
|
|
line.byte 0x00 "RCDTLH,Data Save Register LH"
|
|
rgroup.byte 0x53++0x00
|
|
line.byte 0x00 "RCDTLL,Data Save Register LL"
|
|
group.word 0x58++0x01
|
|
line.word 0x00 "RCCKD,Clock Division Setting Register"
|
|
bitfld.word 0x00 12. " CKSEL ,Operating clock selection bit" "PCLK,Sub-clock"
|
|
hexmask.word 0x00 0.--11. 1. " CKDIV ,Operating clock division setting bits"
|
|
group.byte 0x5D++0x00
|
|
line.byte 0x00 "RCRC,Repeat Code Interrupt Control Register"
|
|
bitfld.byte 0x00 4. " RCIE ,Repeat Code Interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " RC ,Repeat code detection flag bit (Read/Write)" "Not detected/Cleared,Detected/No effect"
|
|
group.byte 0x5C++0x00
|
|
line.byte 0x00 "RCRHW,Repeat Code Detection Width Setting Register"
|
|
group.byte 0x61++0x00
|
|
line.byte 0x00 "RCLE,Data Bit Width Violation Interrupt Control Register"
|
|
bitfld.byte 0x00 7. " LELIE ,Maximum data bit width violation interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " LESIE ,Minimum data bit width violation interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LELE ,Maximum data bit width violation detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LESE ,Minimum data bit width violation detection enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " EPE ,Error pulse output enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " LEL ,Maximum data bit width violation detection flag bit (Read/Write)" "Not detected/Cleared,Detected/No effect"
|
|
bitfld.byte 0x00 0. " LES ,Minimum data bit width violation detection flag bit (Read/Write)" "Not detected/Cleared,Detected/No effect"
|
|
group.byte 0x65++0x00
|
|
line.byte 0x00 "RCLELW,Maximum Data Bit Width Setting Register"
|
|
group.byte 0x64++0x00
|
|
line.byte 0x00 "RCLESW,Minimum Data Bit Width Setting Register"
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0x40034100
|
|
width 8.
|
|
group.byte 0x41++0x00
|
|
line.byte 0x00 "RCCR,Reception Control Register"
|
|
bitfld.byte 0x00 7. " THSEL ,Threshold value selection bit" "0 data,1 data"
|
|
bitfld.byte 0x00 3. " ADRCE ,Address comparison enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1.--2. " MOD ,Operation mode setting bits" "SIRCS,,NEC,HDMI-CEC"
|
|
bitfld.byte 0x00 0. " EN ,Operation enable bit" "Disabled,Enabled"
|
|
group.byte 0x40++0x00
|
|
line.byte 0x00 "RCST,Reception Interrupt Control Register"
|
|
bitfld.byte 0x00 7. " STIE ,Start bit interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ACKIE ,ACK interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " OVFIE ,Counter overflow interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " OVFSEL ,Counter overflow detection condition setting bit" "128 clocks,256 clocks"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ST ,Start bit detection bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " ACK ,ACK detection bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 1. " EOM ,EOM detection bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " OVF ,Counter overflow detection bit" "Not detected,Detected"
|
|
group.byte 0x4C++0x01
|
|
line.byte 0x00 "RCADR2,Device Address Setting Register 2"
|
|
bitfld.byte 0x00 0.--4. " RCADR2 ,Device address setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x01 "RCADR1,Device Address Setting Register 1"
|
|
bitfld.byte 0x01 0.--4. " RCADR1 ,Device address setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x45++0x00
|
|
line.byte 0x00 "RCSHW,Start Bit Detection Width Setting Register"
|
|
group.byte 0x44++0x00
|
|
line.byte 0x00 "RCDAHW,Minimum Pulse Width Setting Register"
|
|
group.byte 0x49++0x00
|
|
line.byte 0x00 "RCDBHW,Threshold Value Setting Register"
|
|
rgroup.byte 0x50++0x00
|
|
line.byte 0x00 "RCDTHH,Data Save Register HH"
|
|
rgroup.byte 0x49++0x00
|
|
line.byte 0x00 "RCDTHL,Data Save Register HL"
|
|
rgroup.byte 0x54++0x00
|
|
line.byte 0x00 "RCDTLH,Data Save Register LH"
|
|
rgroup.byte 0x53++0x00
|
|
line.byte 0x00 "RCDTLL,Data Save Register LL"
|
|
group.word 0x58++0x01
|
|
line.word 0x00 "RCCKD,Clock Division Setting Register"
|
|
bitfld.word 0x00 12. " CKSEL ,Operating clock selection bit" "PCLK,Sub-clock"
|
|
hexmask.word 0x00 0.--11. 1. " CKDIV ,Operating clock division setting bits"
|
|
group.byte 0x5D++0x00
|
|
line.byte 0x00 "RCRC,Repeat Code Interrupt Control Register"
|
|
bitfld.byte 0x00 4. " RCIE ,Repeat Code Interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " RC ,Repeat code detection flag bit (Read/Write)" "Not detected/Cleared,Detected/No effect"
|
|
group.byte 0x5C++0x00
|
|
line.byte 0x00 "RCRHW,Repeat Code Detection Width Setting Register"
|
|
group.byte 0x61++0x00
|
|
line.byte 0x00 "RCLE,Data Bit Width Violation Interrupt Control Register"
|
|
bitfld.byte 0x00 7. " LELIE ,Maximum data bit width violation interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " LESIE ,Minimum data bit width violation interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LELE ,Maximum data bit width violation detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LESE ,Minimum data bit width violation detection enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " EPE ,Error pulse output enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " LEL ,Maximum data bit width violation detection flag bit (Read/Write)" "Not detected/Cleared,Detected/No effect"
|
|
bitfld.byte 0x00 0. " LES ,Minimum data bit width violation detection flag bit (Read/Write)" "Not detected/Cleared,Detected/No effect"
|
|
group.byte 0x65++0x00
|
|
line.byte 0x00 "RCLELW,Maximum Data Bit Width Setting Register"
|
|
group.byte 0x64++0x00
|
|
line.byte 0x00 "RCLESW,Minimum Data Bit Width Setting Register"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "Transmission"
|
|
tree "Channel 0"
|
|
base ad:0x40034000
|
|
width 8.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "TXCTRL,Transmission Control Register"
|
|
bitfld.byte 0x00 5. " IBREN ,Bus error detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ITSTEN ,Transmission status interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " EOM ,EOM setting bit" "EOM0,EOM1"
|
|
bitfld.byte 0x00 2. " START ,START setting bit" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXEN ,Transmission operation enable bit" "Disabled,Enabled"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "TXDATA,Transmission Data Register"
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "TXSTS,Transmission Status Register"
|
|
bitfld.byte 0x00 5. " IBR ,Bus error detection interrupt request bit" "Cleared,Detected"
|
|
bitfld.byte 0x00 4. " ITST ,Transmission status interrupt request bit" "Cleared,Detected"
|
|
rbitfld.byte 0x00 0. " ACKSV ,ACK cycle value bit" "0 received,1 received"
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "SFREE,Signal Free Time Setting Register"
|
|
bitfld.byte 0x00 0.--3. " SFREE ,Signal free time setting bits (cycles)" "1-bit,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0x40034100
|
|
width 8.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "TXCTRL,Transmission Control Register"
|
|
bitfld.byte 0x00 5. " IBREN ,Bus error detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ITSTEN ,Transmission status interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " EOM ,EOM setting bit" "EOM0,EOM1"
|
|
bitfld.byte 0x00 2. " START ,START setting bit" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXEN ,Transmission operation enable bit" "Disabled,Enabled"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "TXDATA,Transmission Data Register"
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "TXSTS,Transmission Status Register"
|
|
bitfld.byte 0x00 5. " IBR ,Bus error detection interrupt request bit" "Cleared,Detected"
|
|
bitfld.byte 0x00 4. " ITST ,Transmission status interrupt request bit" "Cleared,Detected"
|
|
rbitfld.byte 0x00 0. " ACKSV ,ACK cycle value bit" "0 received,1 received"
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "SFREE,Signal Free Time Setting Register"
|
|
bitfld.byte 0x00 0.--3. " SFREE ,Signal free time setting bits (cycles)" "1-bit,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
textline ""
|