26133 lines
1.9 MiB
26133 lines
1.9 MiB
; --------------------------------------------------------------------------------
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; @Title: CYT2BL On-Chip Peripherals
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; @Props: Released
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; @Author: KWI, RSA, DAB, KRZ, NEJ
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; @Changelog: 2020-11-19 KWI
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; 2022-01-20 DAB
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; 2022-09-12 KRZ
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; 2023-10-12 KRZ
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; 2023-10-20 NEJ
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; 2023-11-08 KRZ
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; @Manufacturer: CYPRESS - Cypress Semiconductor Corporation
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; @Doc: Generated (TRACE32, build: 164352.), based on:
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; cyt2bl.svd (Ver. 1.0)
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; @Core: Cortex-M4F, Cortex-M0+
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; @Chip: CYT2BL3-CM0+, CYT2BL3-CM4, CYT2BL4-CM0+, CYT2BL4-CM4, CYT2BL5-CM0+,
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; CYT2BL5-CM4, CYT2BL7-CM0+, CYT2BL7-CM4, CYT2BL8-CM0+, CYT2BL8-CM4
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; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: percyt2bl.per 16948 2023-11-08 11:06:33Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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sif (CORENAME()=="CORTEXM0+")
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tree.close "Core Registers (Cortex-M0+)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 0x8
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if (CORENAME()=="CORTEXM1")
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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else
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
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bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
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else
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
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endif
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
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hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
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textline " "
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hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
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hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
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group.long 0xd04++0x03
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
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bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
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bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
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bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
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hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
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textline " "
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hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
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if (CORENAME()=="CORTEXM0+")
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group.long 0xd08++0x03
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line.long 0x00 "VTOR,Vector Table Offset Register"
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hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
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else
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textline " "
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endif
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group.long 0xd0c++0x03
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line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
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bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
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textline " "
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bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
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bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
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group.long 0xd10++0x03
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line.long 0x00 "SCR,System Control Register"
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bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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rgroup.long 0xd14++0x03
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line.long 0x00 "CCR,Configuration and Control Register"
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bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
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bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
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group.long 0xd1c++0x0b
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
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bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
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if (CORENAME()=="CORTEXM0+")
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hgroup.long 0x08++0x03
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hide.long 0x00 "ACTLR,Auxiliary Control Register"
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else
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textline " "
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endif
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Memory Protection Unit (MPU)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 15.
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rgroup.long 0xD90++0x03
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line.long 0x00 "MPU_TYPE,MPU Type Register"
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bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
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group.long 0xD94++0x03
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line.long 0x00 "MPU_CTRL,MPU Control Register"
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bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
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bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
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bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
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group.long 0xD98++0x03
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line.long 0x00 "MPU_RNR,MPU Region Number Register"
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hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
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tree.close "MPU regions"
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
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group.long 0xD9C++0x03 "Region 0"
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
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textline " "
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textline " "
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endif
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
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group.long 0xD9C++0x03 "Region 1"
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saveout 0xD98 %l 0x1
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line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x1
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line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
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saveout 0xD98 %l 0x1
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hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x1
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hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
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textline " "
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textline " "
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endif
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
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group.long 0xD9C++0x03 "Region 2"
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saveout 0xD98 %l 0x2
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line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x2
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line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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|
else
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|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
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|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
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|
hgroup.long 0xDA0++0x03
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|
saveout 0xD98 %l 0x2
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|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
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|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
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|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
tree.end
|
|
width 6.
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x00 "INT0,Interrupt Priority Register"
|
|
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
|
|
line.long 0x04 "INT1,Interrupt Priority Register"
|
|
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
|
|
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
|
|
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
|
|
line.long 0x08 "INT2,Interrupt Priority Register"
|
|
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
|
|
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
|
|
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
|
|
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
|
|
line.long 0x0C "INT3,Interrupt Priority Register"
|
|
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
|
|
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
|
|
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
|
|
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
|
|
line.long 0x10 "INT4,Interrupt Priority Register"
|
|
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
|
|
line.long 0x14 "INT5,Interrupt Priority Register"
|
|
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
|
|
line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
endif
|
|
sif (CORENAME()=="CORTEXM4F")
|
|
tree.close "Core Registers (Cortex-M4F)"
|
|
AUTOINDENT.PUSH
|
|
AUTOINDENT.OFF
|
|
tree "System Control"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ACTLR,Auxiliary Control Register"
|
|
bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
|
|
bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
|
|
bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
|
|
bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
|
|
rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
|
|
bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
|
|
bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
|
|
line.long 0x08 "SYST_CVR,SysTick Current Value Register"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
|
|
bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
|
|
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
|
|
rgroup.long 0xD00++0x03
|
|
line.long 0x00 "CPUID,CPU ID Base Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
|
|
bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
|
|
bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
|
|
bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xD04++0x23
|
|
line.long 0x00 "ICSR,Interrupt Control State Register"
|
|
bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
|
|
bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
|
|
bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
|
|
bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
|
|
hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
|
|
bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
|
|
line.long 0x04 "VTOR,Vector Table Offset Register"
|
|
hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
|
|
line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
|
|
rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
|
|
bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
|
|
bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
|
|
bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
|
|
line.long 0x0C "SCR,System Control Register"
|
|
bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
|
|
bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
|
|
bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
|
|
line.long 0x10 "CCR,Configuration Control Register"
|
|
bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
|
|
bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
|
|
bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
|
|
line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
|
|
textline " "
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
|
|
line.long 0x18 "SHPR2,System Handler Priority Register 2"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
|
|
textline " "
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
|
|
line.long 0x1C "SHPR3,System Handler Priority Register 3"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
|
|
textline " "
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
|
|
line.long 0x20 "SHCSR,System Handler Control and State Register"
|
|
bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
|
|
bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
|
|
bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
|
|
bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
|
|
bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
|
|
bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
|
|
bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
|
|
bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
|
|
bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
|
|
bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
|
|
group.byte 0xD28++0x1
|
|
line.byte 0x00 "MMFSR,MemManage Status Register"
|
|
bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
|
|
bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
|
|
line.byte 0x01 "BFSR,Bus Fault Status Register"
|
|
bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
|
|
bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
|
|
bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
|
|
bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
|
|
bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
|
|
group.word 0xD2A++0x1
|
|
line.word 0x00 "USAFAULT,Usage Fault Status Register"
|
|
bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
|
|
bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
|
|
bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
|
|
bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
|
|
bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
|
|
group.long 0xD2C++0x07
|
|
line.long 0x00 "HFSR,Hard Fault Status Register"
|
|
bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
|
|
line.long 0x04 "DFSR,Debug Fault Status Register"
|
|
bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
|
|
bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
|
|
bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
|
|
group.long 0xD34++0x0B
|
|
line.long 0x00 "MMFAR,MemManage Fault Address Register"
|
|
line.long 0x04 "BFAR,BusFault Address Register"
|
|
line.long 0x08 "AFSR,Auxiliary Fault Status Register"
|
|
group.long 0xD88++0x03
|
|
line.long 0x00 "CPACR,Coprocessor Access Control Register"
|
|
bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
|
|
wgroup.long 0xF00++0x03
|
|
line.long 0x00 "STIR,Software Trigger Interrupt Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
|
|
width 10.
|
|
tree "Feature Registers"
|
|
rgroup.long 0xD40++0x0B
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
|
|
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
|
|
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
|
|
hgroup.long 0xD4C++0x03
|
|
hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
rgroup.long 0xD50++0x03
|
|
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
|
|
bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
|
|
bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
|
|
hgroup.long 0xD54++0x03
|
|
hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
|
|
rgroup.long 0xD58++0x03
|
|
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
|
|
bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
|
|
rgroup.long 0xD60++0x13
|
|
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
|
|
bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
|
|
bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
|
|
bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
|
|
bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
|
|
line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
|
|
bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
|
|
bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
|
|
bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
|
|
line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
|
|
bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
|
|
bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
|
|
bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
|
|
bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
|
|
bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
|
|
line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
|
|
bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
|
|
bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
endif
|
|
tree "BACKUP (SRSS Backup Domain)"
|
|
base ad:0x40270000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "EN_CHARGE_KEY,When set to 3C the supercap charger circuit is enabled. Any other code disables the supercap charger. THIS CHARGING CIRCUIT IS FOR A SUPERCAP ONLY AND CANNOT SAFELY CHARGE A BATTERY. DO NOT WRITE THIS KEY WHEN VBACKUP IS CONNECTED TO A.."
|
|
newline
|
|
bitfld.long 0x0 19. "VBACKUP_MEAS,Connect vbackup supply to the vbackup_meas output for measurement by an ADC attached to amuxbusa_adft_vddd. The vbackup_meas signal is scaled to 10 percent of vbackup so it is within the supply range of the ADC." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17.--18. "VDDBAK_CTL,Controls the behavior of the switch that generates vddbak from vbackup or vddd." "0: automatically select vddd if its brownout..,?,?,3: force vddbak and vmax to select vbackup"
|
|
newline
|
|
bitfld.long 0x0 16. "WCO_BYPASS,Configures the WCO for different board-level connections to the WCO pins. For example this can be used to connect an external watch crystal oscillator instead of a watch crystal. In all cases the two related GPIO pins (WCO input and.." "0: Watch crystal,1: Clock signal"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "PRESCALER,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CLK_SEL,Clock select for RTC clock" "0: Watch-crystal oscillator input available in..,1: This allows to use the LFCLK selection as an..,2: Internal Low frequency Oscillator available in..,3: Low-power external crystal oscillator prescaler.."
|
|
newline
|
|
bitfld.long 0x0 3. "WCO_EN,Watch-crystal oscillator (WCO) enable. If there is a write in progress when this bit is cleared the WCO will be internally kept on until the write completes." "0,1"
|
|
group.long 0x8++0x7
|
|
line.long 0x0 "RTC_RW,RTC Read Write register"
|
|
bitfld.long 0x0 1. "WRITE,Write bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "READ,Read bit" "0,1"
|
|
line.long 0x4 "CAL_CTL,Oscillator calibration for absolute frequency"
|
|
bitfld.long 0x4 31. "CAL_OUT,Output enable for wave signal for calibration and allow CALIB_VAL to be written." "0,1"
|
|
newline
|
|
bitfld.long 0x4 28.--29. "CAL_SEL,Select calibration wave output signal" "0: 512Hz wave not affected by calibration setting..,1: N/A,2: 2Hz wave includes the effect of the calibration..,3: 1Hz wave includes the effect of the calibration.."
|
|
newline
|
|
bitfld.long 0x4 6. "CALIB_SIGN,Calibration sign:" "0: Negative sign: remove pulses,1: Positive sign: add pulses"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "CALIB_VAL,Calibration value for absolute frequency (at a fixed temperature). Each step causes 128 ticks to be added or removed each hour. Effectively that means that each step is 1.085ppm (= 128/(60*60*32 768))."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "STATUS,Status"
|
|
bitfld.long 0x0 2. "WCO_OK,Indicates that output has transitioned." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RTC_BUSY,Pending RTC write" "0,1"
|
|
group.long 0x14++0x23
|
|
line.long 0x0 "RTC_TIME,Calendar Seconds. Minutes. Hours. Day of Week"
|
|
bitfld.long 0x0 24.--26. "RTC_DAY,Calendar Day of the week 1-7" "?,1: Monday is recommended,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 22. "CTRL_12HR,Select 12/24HR mode: 1=12HR 0=24HR" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "RTC_HOUR,Calendar hours value depending on 12/24HR mode"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "RTC_MIN,Calendar minutes 0-59"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "RTC_SEC,Calendar seconds 0-59"
|
|
line.long 0x4 "RTC_DATE,Calendar Day of Month. Month. Year"
|
|
hexmask.long.byte 0x4 16.--22. 1. "RTC_YEAR,Calendar year 0-99"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "RTC_MON,Calendar Month 1-12"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "RTC_DATE,Calendar Day of the Month 1-31"
|
|
line.long 0x8 "ALM1_TIME,Alarm 1 Seconds. Minute. Hours. Day of Week"
|
|
bitfld.long 0x8 31. "ALM_DAY_EN,Alarm Day of the Week enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
newline
|
|
bitfld.long 0x8 24.--26. "ALM_DAY,Alarm Day of the week 1-7" "?,1: Monday is recommended,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x8 23. "ALM_HOUR_EN,Alarm hour enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--20. 1. "ALM_HOUR,Alarm hours value depending on 12/24HR mode"
|
|
newline
|
|
bitfld.long 0x8 15. "ALM_MIN_EN,Alarm minutes enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--13. 1. "ALM_MIN,Alarm minutes 0-59"
|
|
newline
|
|
bitfld.long 0x8 7. "ALM_SEC_EN,Alarm second enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--5. 1. "ALM_SEC,Alarm seconds 0-59"
|
|
line.long 0xC "ALM1_DATE,Alarm 1 Day of Month. Month"
|
|
bitfld.long 0xC 31. "ALM_EN,Master enable for alarm 1." "0: Alarm 1 is disabled,1: Alarm 1 is enabled"
|
|
newline
|
|
bitfld.long 0xC 15. "ALM_MON_EN,Alarm Month enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--11. 1. "ALM_MON,Alarm Month 1-12"
|
|
newline
|
|
bitfld.long 0xC 7. "ALM_DATE_EN,Alarm Day of the Month enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--4. 1. "ALM_DATE,Alarm Day of the Month 1-31"
|
|
line.long 0x10 "ALM2_TIME,Alarm 2 Seconds. Minute. Hours. Day of Week"
|
|
bitfld.long 0x10 31. "ALM_DAY_EN,Alarm Day of the Week enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
newline
|
|
bitfld.long 0x10 24.--26. "ALM_DAY,Alarm Day of the week 1-7" "?,1: Monday is recommended,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x10 23. "ALM_HOUR_EN,Alarm hour enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--20. 1. "ALM_HOUR,Alarm hours value depending on 12/24HR mode"
|
|
newline
|
|
bitfld.long 0x10 15. "ALM_MIN_EN,Alarm minutes enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--13. 1. "ALM_MIN,Alarm minutes 0-59"
|
|
newline
|
|
bitfld.long 0x10 7. "ALM_SEC_EN,Alarm second enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--5. 1. "ALM_SEC,Alarm seconds 0-59"
|
|
line.long 0x14 "ALM2_DATE,Alarm 2 Day of Month. Month"
|
|
bitfld.long 0x14 31. "ALM_EN,Master enable for alarm 2." "0: Alarm 2 is disabled,1: Alarm 2 is enabled"
|
|
newline
|
|
bitfld.long 0x14 15. "ALM_MON_EN,Alarm Month enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--11. 1. "ALM_MON,Alarm Month 1-12"
|
|
newline
|
|
bitfld.long 0x14 7. "ALM_DATE_EN,Alarm Day of the Month enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--4. 1. "ALM_DATE,Alarm Day of the Month 1-31"
|
|
line.long 0x18 "INTR,Interrupt request register"
|
|
bitfld.long 0x18 2. "CENTURY,Century overflow interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x18 1. "ALARM2,Alarm 2 Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "ALARM1,Alarm 1 Interrupt" "0,1"
|
|
line.long 0x1C "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x1C 2. "CENTURY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 1. "ALARM2,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "ALARM1,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x20 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x20 2. "CENTURY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x20 1. "ALARM2,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x20 0. "ALARM1,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x0 2. "CENTURY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ALARM2,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ALARM1,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "PMIC_CTL,PMIC control register"
|
|
bitfld.long 0x0 31. "PMIC_EN,Enable for external PMIC that supplies vddd (if present). This bit will only clear if UNLOCK was written correctly in a previous write operation and PMIC_ALWAYSEN=0. When PMIC_EN=0 the system functions normally until vddd is no longer present.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "PMIC_ALWAYSEN,Override normal PMIC controls to prevent accidentally turning off the PMIC by errant firmware." "0: Normal operation,1: PMIC_EN and PMIC_OUTEN are ignored and the.."
|
|
newline
|
|
bitfld.long 0x0 29. "PMIC_EN_OUTEN,Output enable for the output driver in the PMIC_EN pad." "0: Output pad is tristate for PMIC_EN pin,1: Output pad is enabled for PMIC_EN pin"
|
|
newline
|
|
bitfld.long 0x0 16. "POLARITY,N/A" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "UNLOCK,This byte must be set to 0x3A for PMIC to be disabled. When the UNLOCK code is not present: writes to PMIC_EN field are ignored and the hardware ignores the value in PMIC_EN. Do not change PMIC_EN in the same write cycle as setting/clearing the.."
|
|
line.long 0x4 "RESET,Backup reset register"
|
|
bitfld.long 0x4 31. "RESET,Writing 1 to this register resets the backup logic. Hardware clears it when the reset is complete. After setting this register firmware should confirm it reads as 0 before attempting to write other backup registers." "0,1"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "LPECO_CTL,Low-power external crystal oscillator control"
|
|
bitfld.long 0x0 31. "LPECO_EN,Master enable for LPECO oscillator. This also disables the LPECO prescaler." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LPECO_AMPDET_EN,Minimum amplitude detector enable/disable. Ignored when LPECO_EN==0." "0: Initially enabled,1: Keep minimum amplitude detector enabled as long.."
|
|
newline
|
|
bitfld.long 0x0 28. "LPECO_DIV_ENABLE,LPECO prescaler enable. Do not set this to '1' when LPECO_EN==0. SW sets this field to '1' to enable the divider and HW sets this field to '0' to indicate that divider enabling has completed. When the divider is enabled its integer.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "LPECO_AMP_SEL,Selects the oscillation amplitude. WARNING: the crystal can be permanently damaged by selecting an amplitude that exceeds the crystal limits." "0: maximum amplitude is 1,1: maximum amplitude is 1"
|
|
newline
|
|
bitfld.long 0x0 8. "LPECO_FRANGE,Specifies the crystal frequency range." "0: Crystal frequency is in range [4,1: Crystal frequency is in range [6"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "LPECO_CRANGE,Specifies the load capacitance of the chosen crystal." "0: load is in range [5pF,1: load is in range,2: load is in range,3: load is in range"
|
|
line.long 0x4 "LPECO_PRESCALE,Low-power external crystal oscillator prescaler"
|
|
hexmask.long.word 0x4 16.--25. 1. "LPECO_INT_DIV,Integer divide value allows for LPECO frequencies up to 8MHz to generate 32768 Hz. Subtract one from the desired divide value when writing this field. For example to divide by 1 write LPECO_INT_DIV=0. Do not change this setting when.."
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "LPECO_FRAC_DIV,Fractional value sufficient to get prescaler output within the +/-65ppm calibration range. Do not change this setting when LPECO Prescaler is enabled."
|
|
newline
|
|
rbitfld.long 0x4 0. "LPECO_DIV_ENABLED,LPECO prescaler enabled. HW sets this field to '1' as a result of an BACKUP_LPECO_CTL.LPECO_DIV_ENABLE. HW sets this field to '0' as a result of writing CLK_LPECO_CONFIG.LPECO_EN==0. This field does not update unless LPECO clock is.." "0,1"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "LPECO_STATUS,Low-power external crystal oscillator status"
|
|
bitfld.long 0x0 1. "LPECO_READY,Indicates the LPECO has had enough time to start. This field is driven by a stabilization counter clocked by IMO." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "LPECO_AMPDET_OK,Indicates sufficient oscillation amplitude reported by LPECO amplitude detector. This field will read as zero when the amplitude detector is off (see LPECO_CTL.LPECO_AMPDET_EN)." "0,1"
|
|
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1000)++0x3
|
|
line.long 0x0 "BREG[$1],Backup register region"
|
|
hexmask.long 0x0 0.--31. 1. "BREG,Backup memory that contains application-specific data. Memory is retained on vbackup supply."
|
|
repeat.end
|
|
tree.end
|
|
tree "CANFD (CAN Controller)"
|
|
base ad:0x0
|
|
tree "CANFD0"
|
|
base ad:0x40520000
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x40520000 ad:0x40520200 ad:0x40520400 ad:0x40520600)
|
|
tree "CH[$1]"
|
|
base $2
|
|
tree "M_TTCAN (TTCAN 3PIP includes FD)"
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "CREL,Core Release Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day"
|
|
line.long 0x4 "ENDN,Endian Register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value"
|
|
group.long ($2+0xC)++0x23
|
|
line.long 0x0 "DBTP,Data Bit Timing & Prescaler Register"
|
|
bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation" "0: Transmitter Delay Compensation disabled,1: Transmitter Delay Compensation enabled"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Bit Rate Prescaler"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re)Synchronization Jump Width"
|
|
line.long 0x4 "TEST,Test Register"
|
|
rbitfld.long 0x4 7. "RX,Receive Pin" "0: The CAN bus is dominant,1: The CAN bus is recessive"
|
|
bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 4. "LBCK,Loop Back Mode" "0: Reset value,1: Loop Back Mode is enabled"
|
|
bitfld.long 0x4 3. "CAT,ASC is not supported by M_TTCAN" "0: Output pin m_ttcan_asct = '0',?"
|
|
newline
|
|
bitfld.long 0x4 2. "CAM,ASC is not supported by M_TTCAN" "0: Output pin m_ttcan_ascm = '0',1: Output pin m_ttcan_ascm = '1'"
|
|
bitfld.long 0x4 1. "TAT,ASC is not supported by M_TTCAN" "0: Level at pin m_ttcan_asct controlled by FSE,1: Level at pin m_ttcan_asct = '1'"
|
|
newline
|
|
bitfld.long 0x4 0. "TAM,ASC is not supported by M_TTCAN" "0: Level at pin m_ttcan_ascm controlled by FSE,1: Level at pin m_ttcan_ascm = '1'"
|
|
line.long 0x8 "RWD,RAM Watchdog"
|
|
hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration"
|
|
line.long 0xC "CCCR,CC Control Register"
|
|
bitfld.long 0xC 15. "NISO,Non ISO Operation" "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.."
|
|
bitfld.long 0xC 14. "TXP,Transmit Pause" "0: Transmit pause disabled,1: Transmit pause enabled"
|
|
newline
|
|
bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.."
|
|
bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
|
|
newline
|
|
bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
|
|
bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled"
|
|
newline
|
|
bitfld.long 0xC 7. "TEST,Test Mode Enable" "0: Normal operation,1: Test Mode"
|
|
bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled"
|
|
newline
|
|
bitfld.long 0xC 5. "MON_,Bus Monitoring Mode" "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled"
|
|
bitfld.long 0xC 4. "CSR,Clock Stop Request not supported by M_TTCAN use CTL.STOP_REQ at the group level instead." "0: No clock stop is requested,1: Clock stop requested"
|
|
newline
|
|
bitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: M_TTCAN may be set in power down by stopping.."
|
|
bitfld.long 0xC 2. "ASM,Restricted Operation Mode" "0: Normal CAN operation,1: Restricted Operation Mode active"
|
|
newline
|
|
bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
|
|
bitfld.long 0xC 0. "INIT,Initialization" "0: Normal Operation,1: Initialization is started"
|
|
line.long 0x10 "NBTP,Nominal Bit Timing & Prescaler Register"
|
|
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width"
|
|
hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point"
|
|
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point"
|
|
line.long 0x14 "TSCC,Timestamp Counter Configuration"
|
|
hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler (still used for TOCC)"
|
|
bitfld.long 0x14 0.--1. "TSS,Timestamp Select should always be set to external timestamp counter" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,?,?"
|
|
line.long 0x18 "TSCV,Timestamp Counter Value"
|
|
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter not used for M_TTCAN"
|
|
line.long 0x1C "TOCC,Timeout Counter Configuration"
|
|
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period"
|
|
bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,?,?"
|
|
newline
|
|
bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled,1: Timeout Counter enabled"
|
|
line.long 0x20 "TOCV,Timeout Counter Value"
|
|
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter"
|
|
rgroup.long ($2+0x40)++0x7
|
|
line.long 0x0 "ECR,Error Counter Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging"
|
|
bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter"
|
|
line.long 0x4 "PSR,Protocol Status Register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
|
|
bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
|
|
newline
|
|
bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0: Since this bit was reset by the CPU,1: Message in CAN FD format with FDF flag set has.."
|
|
bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set"
|
|
newline
|
|
bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set"
|
|
bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The M_CAN is not Bus_Off,1: The M_CAN is in Bus_Off state"
|
|
bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
|
|
newline
|
|
bitfld.long 0x4 5. "EP,Error Passive" "0: The M_CAN is in the Error_Active state,1: The M_CAN is in the Error_Passive state"
|
|
bitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing,1: Idle,?,?"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "LEC,Last Error Code " "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: AckError: The message transmitted by the M_TTCAN..,4: Bit1Error: During the transmission of a message,5: Bit0Error: During the transmission of a message,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol Status.."
|
|
group.long ($2+0x48)++0x3
|
|
line.long 0x0 "TDCR,Transmitter Delay Compensation Register"
|
|
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
|
|
hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length"
|
|
group.long ($2+0x50)++0xF
|
|
line.long 0x0 "IR,Interrupt Register"
|
|
bitfld.long 0x0 29. "ARA,N/A" "0,1"
|
|
bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit Time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected"
|
|
newline
|
|
bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase (Nominal Bit Time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected"
|
|
bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY"
|
|
newline
|
|
bitfld.long 0x0 25. "BO_,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
|
|
bitfld.long 0x0 24. "EW_,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
|
|
newline
|
|
bitfld.long 0x0 23. "EP_,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
|
|
bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow,1: Overflow of CAN Error Logging Counter occurred"
|
|
newline
|
|
bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Bit error detected"
|
|
bitfld.long 0x0 20. "BEC,M_TTCAN reports correctable ECC fault to the generic fault structure this bit always reads as 0." "0: No bit error detected when reading from Message..,1: Bit error detected and corrected"
|
|
newline
|
|
bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0: No Rx Buffer updated,1: At least one received message stored into a Rx.."
|
|
bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached"
|
|
newline
|
|
bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
|
|
bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
|
|
newline
|
|
bitfld.long 0x0 15. "TEFL_,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost"
|
|
bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full"
|
|
newline
|
|
bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO fill level below watermark,1: Tx Event FIFO fill level reached watermark"
|
|
bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element"
|
|
newline
|
|
bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
|
|
bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
|
|
newline
|
|
bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed"
|
|
bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received"
|
|
newline
|
|
bitfld.long 0x0 7. "RF1L_,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost"
|
|
bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark"
|
|
bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
|
|
newline
|
|
bitfld.long 0x0 3. "RF0L_,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost"
|
|
bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
newline
|
|
bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark"
|
|
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
|
|
line.long 0x4 "IE,Interrupt Enable"
|
|
bitfld.long 0x4 29. "ARAE,N/A" "0,1"
|
|
bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0,1"
|
|
bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable (not used in M_TTCAN)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 12. "TEFNE,Tx Event FIDO New Entry Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1"
|
|
line.long 0x8 "ILS,Interrupt Line Select"
|
|
bitfld.long 0x8 29. "ARAL,N/A" "0,1"
|
|
bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0,1"
|
|
bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
|
|
bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0,1"
|
|
bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1"
|
|
bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line (not used in M_TTCAN)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1"
|
|
bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
|
|
bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
|
|
bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0,1"
|
|
bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1"
|
|
line.long 0xC "ILE,Interrupt Line Enable"
|
|
bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line m_ttcan_int1 disabled,1: Interrupt line m_ttcan_int1 enabled"
|
|
bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line m_ttcan_int0 disabled,1: Interrupt line m_ttcan_int0 enabled"
|
|
group.long ($2+0x80)++0xB
|
|
line.long 0x0 "GFC,Global Filter Configuration"
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
|
|
newline
|
|
bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
|
|
bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs"
|
|
line.long 0x4 "SIDFC,Standard ID Filter Configuration"
|
|
hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard"
|
|
hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address"
|
|
line.long 0x8 "XIDFC,Extended ID Filter Configuration"
|
|
hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended"
|
|
hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address"
|
|
group.long ($2+0x90)++0x3
|
|
line.long 0x0 "XIDAM,Extended ID AND Mask"
|
|
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask"
|
|
rgroup.long ($2+0x94)++0x3
|
|
line.long 0x0 "HPMS,High Priority Message Status"
|
|
bitfld.long 0x0 15. "FLST,Filter List" "0: Standard Filter List,1: Extended Filter List"
|
|
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO message lost,?,?"
|
|
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index"
|
|
group.long ($2+0x98)++0xB
|
|
line.long 0x0 "NDAT1,New Data 1"
|
|
hexmask.long 0x0 0.--31. 1. "ND,New Data"
|
|
line.long 0x4 "NDAT2,New Data 2"
|
|
hexmask.long 0x4 0.--31. 1. "ND,New Data"
|
|
line.long 0x8 "RXF0C,Rx FIFO 0 Configuration"
|
|
bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode"
|
|
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size"
|
|
hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address"
|
|
rgroup.long ($2+0xA4)++0x3
|
|
line.long 0x0 "RXF0S,Rx FIFO 0 Status"
|
|
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost"
|
|
bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index"
|
|
hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level"
|
|
group.long ($2+0xA8)++0xB
|
|
line.long 0x0 "RXF0A,Rx FIFO 0 Acknowledge"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index"
|
|
line.long 0x4 "RXBC,Rx Buffer Configuration"
|
|
hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address"
|
|
line.long 0x8 "RXF1C,Rx FIFO 1 Configuration"
|
|
bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode"
|
|
hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size"
|
|
hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address"
|
|
rgroup.long ($2+0xB4)++0x3
|
|
line.long 0x0 "RXF1S,Rx FIFO 1 Status"
|
|
bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state,1: Debug message A received,?,?"
|
|
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost"
|
|
newline
|
|
bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index"
|
|
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level"
|
|
group.long ($2+0xB8)++0xB
|
|
line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index"
|
|
line.long 0x4 "RXESC,Rx Buffer / FIFO Element Size Configuration"
|
|
bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "F0DS,N/A" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "TXBC,Tx Buffer Configuration"
|
|
bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation"
|
|
hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
|
|
hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address"
|
|
rgroup.long ($2+0xC4)++0x3
|
|
line.long 0x0 "TXFQS,Tx FIFO/Queue Status"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index"
|
|
hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level"
|
|
group.long ($2+0xC8)++0x3
|
|
line.long 0x0 "TXESC,Tx Buffer Element Size Configuration"
|
|
bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
|
|
rgroup.long ($2+0xCC)++0x3
|
|
line.long 0x0 "TXBRP,Tx Buffer Request Pending"
|
|
hexmask.long 0x0 0.--31. 1. "TRP,Transmission Request Pending"
|
|
group.long ($2+0xD0)++0x7
|
|
line.long 0x0 "TXBAR,Tx Buffer Add Request"
|
|
hexmask.long 0x0 0.--31. 1. "AR,Add Request"
|
|
line.long 0x4 "TXBCR,Tx Buffer Cancellation Request"
|
|
hexmask.long 0x4 0.--31. 1. "CR,Cancellation Request"
|
|
rgroup.long ($2+0xD8)++0x7
|
|
line.long 0x0 "TXBTO,Tx Buffer Transmission Occurred"
|
|
hexmask.long 0x0 0.--31. 1. "TO,Transmission Occurred"
|
|
line.long 0x4 "TXBCF,Tx Buffer Cancellation Finished"
|
|
hexmask.long 0x4 0.--31. 1. "CF,Cancellation Finished"
|
|
group.long ($2+0xE0)++0x7
|
|
line.long 0x0 "TXBTIE,Tx Buffer Transmission Interrupt Enable"
|
|
hexmask.long 0x0 0.--31. 1. "TIE,Transmission Interrupt Enable"
|
|
line.long 0x4 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
|
|
hexmask.long 0x4 0.--31. 1. "CFIE,Cancellation Finished Interrupt Enable"
|
|
group.long ($2+0xF0)++0x3
|
|
line.long 0x0 "TXEFC,Tx Event FIFO Configuration"
|
|
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark"
|
|
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address"
|
|
rgroup.long ($2+0xF4)++0x3
|
|
line.long 0x0 "TXEFS,Tx Event FIFO Status"
|
|
bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index"
|
|
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level"
|
|
group.long ($2+0xF8)++0x3
|
|
line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge"
|
|
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index"
|
|
group.long ($2+0x100)++0x2B
|
|
line.long 0x0 "TTTMC,TT Trigger Memory Configuration"
|
|
hexmask.long.byte 0x0 16.--22. 1. "TME,Trigger Memory Elements"
|
|
hexmask.long.word 0x0 2.--15. 1. "TMSA,Trigger Memory Start Address"
|
|
line.long 0x4 "TTRMC,TT Reference Message Configuration"
|
|
bitfld.long 0x4 31. "RMPS,Reference Message Payload Select" "0: Reference message has no additional payload,1: bytes 2-8"
|
|
bitfld.long 0x4 30. "XTD,Extended Identifier" "0,1"
|
|
newline
|
|
hexmask.long 0x4 0.--28. 1. "RID,Reference Identifier"
|
|
line.long 0x8 "TTOCF,TT Operation Configuration"
|
|
bitfld.long 0x8 26. "EVTP,Event Trigger Polarity" "0: Rising edge trigger,1: Falling edge trigger"
|
|
bitfld.long 0x8 25. "ECC,Enable Clock Calibration" "0: Automatic clock calibration in TTCAN Level 0,1: Automatic clock calibration in TTCAN Level 0"
|
|
newline
|
|
bitfld.long 0x8 24. "EGTF,Enable Global Time Filtering" "0: Global time filtering in TTCAN Level 0,1: Global time filtering in TTCAN Level 0"
|
|
hexmask.long.byte 0x8 16.--23. 1. "AWL,Application Watchdog Limit"
|
|
newline
|
|
bitfld.long 0x8 15. "EECS,Enable External Clock Synchronization" "0: External clock synchronization in TTCAN Level 0,1: External clock synchronization in TTCAN Level 0"
|
|
hexmask.long.byte 0x8 8.--14. 1. "IRTO,Initial Reference Trigger Offset"
|
|
newline
|
|
bitfld.long 0x8 5.--7. "LDSDL,LD of Synchronization Deviation Limit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 4. "TM,Time Master" "0: Time Master function disabled,1: Potential Time Master"
|
|
newline
|
|
bitfld.long 0x8 3. "GEN,Gap Enable" "0: Strictly time-triggered operation,1: External event-synchronized time-triggered.."
|
|
bitfld.long 0x8 0.--1. "OM,Operation Mode" "0: Event-driven CAN communication,1: TTCAN level 1,?,?"
|
|
line.long 0xC "TTMLM,TT Matrix Limits"
|
|
hexmask.long.word 0xC 16.--27. 1. "ENTT,Expected Number of Tx Triggers"
|
|
hexmask.long.byte 0xC 8.--11. 1. "TXEW,Tx Enable Window"
|
|
newline
|
|
bitfld.long 0xC 6.--7. "CSS,N/A" "0,1,2,3"
|
|
hexmask.long.byte 0xC 0.--5. 1. "CCM,N/A"
|
|
line.long 0x10 "TURCF,TUR Configuration"
|
|
bitfld.long 0x10 31. "ELT,Enable Local Time" "0: Local time is stopped,1: Local time is enabled"
|
|
hexmask.long.word 0x10 16.--29. 1. "DC,Denominator Configuration"
|
|
newline
|
|
hexmask.long.word 0x10 0.--15. 1. "NCL,Numerator Configuration Low"
|
|
line.long 0x14 "TTOCN,TT Operation Control"
|
|
rbitfld.long 0x14 15. "LCKC,TT Operation Control Register Locked" "0: Write access to TTOCN enabled,1: Write access to TTOCN locked"
|
|
bitfld.long 0x14 13. "ESCN,External Synchronization Control" "0: External synchronization disabled,1: External synchronization enabled"
|
|
newline
|
|
bitfld.long 0x14 12. "NIG,Next is Gap" "0: No action,1: Transmit next reference message with Next_is_Gap.."
|
|
bitfld.long 0x14 11. "TMG,Time Mark Gap" "0: Reset by each reference message,1: Next reference message started when Register.."
|
|
newline
|
|
bitfld.long 0x14 10. "FGP,Finish Gap" "0: No reference message requested,1: Application requested start of reference message"
|
|
bitfld.long 0x14 9. "GCS,Gap Control Select" "0: Gap control independent from m_ttcan_evt,1: Gap control by input pin m_ttcan_evt"
|
|
newline
|
|
bitfld.long 0x14 8. "TTIE,Trigger Time Mark Interrupt Pulse Enable" "0: Trigger Time Mark Interrupt output m_ttcan_tmp..,1: Trigger Time Mark Interrupt output m_ttcan_tmp.."
|
|
bitfld.long 0x14 6.--7. "TMC,Register Time Mark Compare" "0: No Register Time Mark Interrupt generated,1: Register Time Mark Interrupt if Time Mark =..,?,?"
|
|
newline
|
|
bitfld.long 0x14 5. "RTIE,Register Time Mark Interrupt Pulse Enable" "0: Register Time Mark Interrupt output m_ttcan_rtp..,1: Register Time Mark Interrupt output m_ttcan_rtp.."
|
|
bitfld.long 0x14 3.--4. "SWS,Stop Watch Source" "0: Stop Watch disabled,1: Actual value of cycle time is copied to TTCPT,?,?"
|
|
newline
|
|
bitfld.long 0x14 2. "SWP,Stop Watch Polarity" "0: Rising edge trigger,1: Falling edge trigger"
|
|
bitfld.long 0x14 1. "ECS,External Clock Synchronization" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "SGT,Set Global time" "0,1"
|
|
line.long 0x18 "TTGTP,TT Global Time Preset"
|
|
hexmask.long.word 0x18 16.--31. 1. "CTP,Cycle Time Target Phase"
|
|
hexmask.long.word 0x18 0.--15. 1. "TP,N/A"
|
|
line.long 0x1C "TTTMK,TT Time Mark"
|
|
rbitfld.long 0x1C 31. "LCKM,TT Time Mark Register Locked" "0: Write access to TTTMK enabled,1: Write access to TTTMK locked"
|
|
hexmask.long.byte 0x1C 16.--22. 1. "TICC,Time Mark Cycle Code"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--15. 1. "TM_,Time Mark"
|
|
line.long 0x20 "TTIR,TT Interrupt Register"
|
|
bitfld.long 0x20 18. "CER,Configuration Error" "0: No error found in trigger list,1: Error found in trigger list"
|
|
bitfld.long 0x20 17. "AW,Application Watchdog" "0: Application watchdog served in time,1: Application watchdog not served in time"
|
|
newline
|
|
bitfld.long 0x20 16. "WT,Watch Trigger" "0: cycle time 0xFF00),1: Missing reference message"
|
|
bitfld.long 0x20 15. "IWT,Initialization Watch Trigger" "0: No missing reference message during system startup,1: No system startup due to missing reference message"
|
|
newline
|
|
bitfld.long 0x20 14. "ELC,Error Level Changed" "0: No change in error level,1: Error level changed"
|
|
bitfld.long 0x20 13. "SE2,Scheduling Error 2" "0: No scheduling error 2,1: Scheduling error 2 occurred"
|
|
newline
|
|
bitfld.long 0x20 12. "SE1,Scheduling Error 1" "0: No scheduling error 1,1: Scheduling error 1 occurred"
|
|
bitfld.long 0x20 11. "TXO,Tx Count Overflow" "0: Number of Tx Trigger as expected,1: More Tx trigger than expected in one matrix cycle"
|
|
newline
|
|
bitfld.long 0x20 10. "TXU,Tx Count Underflow" "0: Number of Tx Trigger as expected,1: Less Tx trigger than expected in one matrix cycle"
|
|
bitfld.long 0x20 9. "GTE,Global Time Error" "0: Synchronization deviation within limit,1: Synchronization deviation exceeded limit"
|
|
newline
|
|
bitfld.long 0x20 8. "GTD,Global Time Discontinuity" "0: No discontinuity of global time,1: Discontinuity of global time"
|
|
bitfld.long 0x20 7. "GTW,Global Time Wrap" "0: No global time wrap occurred,1: Global time wrap from 0xFFFF to 0x0000 occurred"
|
|
newline
|
|
bitfld.long 0x20 6. "SWE,Stop Watch Event" "0: No rising/falling edge at stop watch trigger pin..,1: Rising/falling edge at stop watch trigger pin.."
|
|
bitfld.long 0x20 5. "TTMI,Trigger Time Mark Event Internal" "0: cycle time TTOCF,1: Time mark reached"
|
|
newline
|
|
bitfld.long 0x20 4. "RTMI,Register Time Mark Interrupt" "0: Time mark not reached,1: Time mark reached"
|
|
bitfld.long 0x20 3. "SOG,Start of Gap" "0: No reference message seen with Next_is_Gap bit set,1: Reference message with Next_is_Gap bit set.."
|
|
newline
|
|
bitfld.long 0x20 2. "CSM_,Change of Synchronization Mode" "0: No change in master to slave relation or..,1: Master to slave relation or schedule.."
|
|
bitfld.long 0x20 1. "SMC,Start of Matrix Cycle" "0: No Matrix Cycle started since bit has been reset,1: Matrix Cycle started"
|
|
newline
|
|
bitfld.long 0x20 0. "SBC,Start of Basic Cycle" "0: No Basic Cycle started since bit has been reset,1: Basic Cycle started"
|
|
line.long 0x24 "TTIE,TT Interrupt Enable"
|
|
bitfld.long 0x24 18. "CERE,Configuration Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x24 17. "AWE_,Application Watchdog Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x24 16. "WTE,Watch Trigger Interrupt Enable" "0,1"
|
|
bitfld.long 0x24 15. "IWTE,Initialization Watch Trigger Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x24 14. "ELCE,Change Error Level Interrupt Enable" "0,1"
|
|
bitfld.long 0x24 13. "SE2E,Scheduling Error 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x24 12. "SE1E,Scheduling Error 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x24 11. "TXOE,Tx Count Overflow Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x24 10. "TXUE,Tx Count Underflow Interrupt Enable" "0,1"
|
|
bitfld.long 0x24 9. "GTEE,Global Time Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x24 8. "GTDE,Global Time Discontinuity Interrupt Enable" "0,1"
|
|
bitfld.long 0x24 7. "GTWE,Global Time Wrap Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x24 6. "SWEE,Stop Watch Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x24 5. "TTMIE,Trigger Time Mark Event Internal Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x24 4. "RTMIE,Register Time Mark Interrupt Enable" "0,1"
|
|
bitfld.long 0x24 3. "SOGE,Start of Gap Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x24 2. "CSME,Change of Synchronization Mode Interrupt Enable" "0,1"
|
|
bitfld.long 0x24 1. "SMCE,Start of Matrix Cycle Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x24 0. "SBCE,Start of Basic Cycle Interrupt Enable" "0,1"
|
|
line.long 0x28 "TTILS,TT Interrupt Line Select"
|
|
bitfld.long 0x28 18. "CERL,Configuration Error Interrupt Line" "0,1"
|
|
bitfld.long 0x28 17. "AWL_,Application Watchdog Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x28 16. "WTL,Watch Trigger Interrupt Line" "0,1"
|
|
bitfld.long 0x28 15. "IWTL,Initialization Watch Trigger Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x28 14. "ELCL,Change Error Level Interrupt Line" "0,1"
|
|
bitfld.long 0x28 13. "SE2L,Scheduling Error 2 Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x28 12. "SE1L,Scheduling Error 1 Interrupt Line" "0,1"
|
|
bitfld.long 0x28 11. "TXOL,Tx Count Overflow Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x28 10. "TXUL,Tx Count Underflow Interrupt Line" "0,1"
|
|
bitfld.long 0x28 9. "GTEL,Global Time Error Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x28 8. "GTDL,Global Time Discontinuity Interrupt Line" "0,1"
|
|
bitfld.long 0x28 7. "GTWL,Global Time Wrap Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x28 6. "SWEL,Stop Watch Event Interrupt Line" "0,1"
|
|
bitfld.long 0x28 5. "TTMIL,Trigger Time Mark Event Internal Line" "0,1"
|
|
newline
|
|
bitfld.long 0x28 4. "RTMIL,Register Time Mark Interrupt Line" "0,1"
|
|
bitfld.long 0x28 3. "SOGL,Start of Gap Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x28 2. "CSML,Change of Synchronization Mode Interrupt Line" "0,1"
|
|
bitfld.long 0x28 1. "SMCL,Start of Matrix Cycle Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x28 0. "SBCL,Start of Basic Cycle Interrupt Line" "0,1"
|
|
rgroup.long ($2+0x12C)++0x17
|
|
line.long 0x0 "TTOST,TT Operation Status"
|
|
bitfld.long 0x0 31. "SPL,Schedule Phase Lock" "0: Phase outside range,1: Phase inside range"
|
|
bitfld.long 0x0 30. "WECS,Wait for External Clock Synchronization" "0: No external clock synchronization pending,1: Node waits for external clock synchronization to.."
|
|
newline
|
|
bitfld.long 0x0 29. "AWE,Application Watchdog Event" "0: Application Watchdog served in time,1: Failed to serve Application Watchdog in time"
|
|
bitfld.long 0x0 28. "WFE,Wait for Event" "0: No Gap announced,1: Reference message with Next_is_Gap = '1' received"
|
|
newline
|
|
bitfld.long 0x0 27. "GSI,Gap Started Indicator" "0: No Gap in schedule,1: Gap time after Basic Cycle has started"
|
|
bitfld.long 0x0 24.--26. "TMP,Time Master Priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 23. "GFI,Gap Finished Indicator" "0: Reset at the end of each reference message,1: Gap finished by M_TTCAN"
|
|
bitfld.long 0x0 22. "WGTD,Wait for Global Time Discontinuity" "0: No global time preset pending,1: Node waits for the global time preset to take.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RTO,Reference Trigger Offset"
|
|
bitfld.long 0x0 7. "QCS,Quality of Clock Speed" "0: Local clock speed not synchronized to Time..,1: Synchronization Deviation <= SDL"
|
|
newline
|
|
bitfld.long 0x0 6. "QGTP,Quality of Global Time Phase" "0: Global time not valid,1: Global time in phase with Time Master"
|
|
bitfld.long 0x0 4.--5. "SYS,Synchronization State" "0: Out of Synchronization,1: Synchronizing to TTCAN communication,?,?"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MS,Master State" "0: Master_Off,1: Operating as Time Slave,?,?"
|
|
bitfld.long 0x0 0.--1. "EL,Error Level" "0: Severity 0,1: Severity 1,?,?"
|
|
line.long 0x4 "TURNA,TUR Numerator Actual"
|
|
hexmask.long.tbyte 0x4 0.--17. 1. "NAV,N/A"
|
|
line.long 0x8 "TTLGT,TT Local & Global Time"
|
|
hexmask.long.word 0x8 16.--31. 1. "GT,Global Time"
|
|
hexmask.long.word 0x8 0.--15. 1. "LT,Local Time"
|
|
line.long 0xC "TTCTC,TT Cycle Time & Count"
|
|
hexmask.long.byte 0xC 16.--21. 1. "CC,Cycle Count"
|
|
hexmask.long.word 0xC 0.--15. 1. "CT,Cycle Time"
|
|
line.long 0x10 "TTCPT,TT Capture Time"
|
|
hexmask.long.word 0x10 16.--31. 1. "SWV,Stop Watch Value"
|
|
hexmask.long.byte 0x10 0.--5. 1. "CCV,Cycle Count Value"
|
|
line.long 0x14 "TTCSM,TT Cycle Sync Mark"
|
|
hexmask.long.word 0x14 0.--15. 1. "CSM,Cycle Sync Mark"
|
|
tree.end
|
|
group.long ($2+0x180)++0x3
|
|
newline
|
|
line.long 0x0 "RXFTOP_CTL,Receive FIFO Top control"
|
|
bitfld.long 0x0 1. "F1TPE,FIFO 1 Top Pointer Enable." "0,1"
|
|
bitfld.long 0x0 0. "F0TPE,FIFO 0 Top Pointer Enable." "0,1"
|
|
rgroup.long ($2+0x1A0)++0x3
|
|
line.long 0x0 "RXFTOP0_STAT,Receive FIFO 0 Top Status"
|
|
hexmask.long.word 0x0 0.--15. 1. "F0TA,Current FIFO 0 Top Address."
|
|
rgroup.long ($2+0x1A8)++0x3
|
|
line.long 0x0 "RXFTOP0_DATA,Receive FIFO 0 Top Data"
|
|
hexmask.long 0x0 0.--31. 1. "F0TD,When enabled (F0TPE=1) read data from MRAM at location FnTA. This register can have a read side effect if the following conditions are met:"
|
|
rgroup.long ($2+0x1B0)++0x3
|
|
line.long 0x0 "RXFTOP1_STAT,Receive FIFO 1 Top Status"
|
|
hexmask.long.word 0x0 0.--15. 1. "F1TA,See F0TA description"
|
|
rgroup.long ($2+0x1B8)++0x3
|
|
line.long 0x0 "RXFTOP1_DATA,Receive FIFO 1 Top Data"
|
|
hexmask.long 0x0 0.--31. 1. "F1TD,See F0TD description"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40520000
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "CTL,Global CAN control register"
|
|
bitfld.long 0x0 31. "MRAM_OFF,MRAM off" "0: Default MRAM on,1: Switch MRAM off"
|
|
hexmask.long.byte 0x0 0.--7. 1. "STOP_REQ,Clock Stop Request for each TTCAN IP ."
|
|
rgroup.long 0x1004++0x3
|
|
line.long 0x0 "STATUS,Global CAN status register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "STOP_ACK,Clock Stop Acknowledge for each TTCAN IP."
|
|
rgroup.long 0x1010++0x7
|
|
line.long 0x0 "INTR0_CAUSE,Consolidated interrupt0 cause register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT0,Show pending m_ttcan_int0 of each channel"
|
|
line.long 0x4 "INTR1_CAUSE,Consolidated interrupt1 cause register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "INT1,Show pending m_ttcan_int1 of each channel"
|
|
group.long 0x1020++0x7
|
|
line.long 0x0 "TS_CTL,Time Stamp control register"
|
|
bitfld.long 0x0 31. "ENABLED,Counter enable bit" "0: Count disabled,1: Count enabled"
|
|
hexmask.long.word 0x0 0.--15. 1. "PRESCALE,Time Stamp counter prescale value."
|
|
line.long 0x4 "TS_CNT,Time Stamp counter value"
|
|
hexmask.long.word 0x4 0.--15. 1. "VALUE,The counter value of the Time Stamp Counter."
|
|
group.long 0x1080++0x7
|
|
line.long 0x0 "ECC_CTL,ECC control"
|
|
bitfld.long 0x0 16. "ECC_EN,Enable ECC for CANFD SRAM" "0,1"
|
|
line.long 0x4 "ECC_ERR_INJ,ECC error injection"
|
|
hexmask.long.byte 0x4 24.--30. 1. "ERR_PAR,ECC Parity bits to use for ECC error injection at address ERR_ADDR."
|
|
bitfld.long 0x4 20. "ERR_EN,Enable error injection (ECC_EN must be 1)." "0,1"
|
|
hexmask.long.word 0x4 2.--15. 1. "ERR_ADDR,Specifies the address of the word where an error will be injected on write or an non-correctable error will be suppressed."
|
|
tree.end
|
|
tree "CANFD1"
|
|
base ad:0x40540000
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x40540000 ad:0x40540200 ad:0x40540400 ad:0x40540600)
|
|
tree "CH[$1]"
|
|
base $2
|
|
tree "M_TTCAN (TTCAN 3PIP includes FD)"
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "CREL,Core Release Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day"
|
|
line.long 0x4 "ENDN,Endian Register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value"
|
|
group.long ($2+0xC)++0x23
|
|
line.long 0x0 "DBTP,Data Bit Timing & Prescaler Register"
|
|
bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation" "0: Transmitter Delay Compensation disabled,1: Transmitter Delay Compensation enabled"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Bit Rate Prescaler"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re)Synchronization Jump Width"
|
|
line.long 0x4 "TEST,Test Register"
|
|
rbitfld.long 0x4 7. "RX,Receive Pin" "0: The CAN bus is dominant,1: The CAN bus is recessive"
|
|
bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 4. "LBCK,Loop Back Mode" "0: Reset value,1: Loop Back Mode is enabled"
|
|
bitfld.long 0x4 3. "CAT,ASC is not supported by M_TTCAN" "0: Output pin m_ttcan_asct = '0',?"
|
|
newline
|
|
bitfld.long 0x4 2. "CAM,ASC is not supported by M_TTCAN" "0: Output pin m_ttcan_ascm = '0',1: Output pin m_ttcan_ascm = '1'"
|
|
bitfld.long 0x4 1. "TAT,ASC is not supported by M_TTCAN" "0: Level at pin m_ttcan_asct controlled by FSE,1: Level at pin m_ttcan_asct = '1'"
|
|
newline
|
|
bitfld.long 0x4 0. "TAM,ASC is not supported by M_TTCAN" "0: Level at pin m_ttcan_ascm controlled by FSE,1: Level at pin m_ttcan_ascm = '1'"
|
|
line.long 0x8 "RWD,RAM Watchdog"
|
|
hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration"
|
|
line.long 0xC "CCCR,CC Control Register"
|
|
bitfld.long 0xC 15. "NISO,Non ISO Operation" "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.."
|
|
bitfld.long 0xC 14. "TXP,Transmit Pause" "0: Transmit pause disabled,1: Transmit pause enabled"
|
|
newline
|
|
bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.."
|
|
bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
|
|
newline
|
|
bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
|
|
bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled"
|
|
newline
|
|
bitfld.long 0xC 7. "TEST,Test Mode Enable" "0: Normal operation,1: Test Mode"
|
|
bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled"
|
|
newline
|
|
bitfld.long 0xC 5. "MON_,Bus Monitoring Mode" "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled"
|
|
bitfld.long 0xC 4. "CSR,Clock Stop Request not supported by M_TTCAN use CTL.STOP_REQ at the group level instead." "0: No clock stop is requested,1: Clock stop requested"
|
|
newline
|
|
bitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: M_TTCAN may be set in power down by stopping.."
|
|
bitfld.long 0xC 2. "ASM,Restricted Operation Mode" "0: Normal CAN operation,1: Restricted Operation Mode active"
|
|
newline
|
|
bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
|
|
bitfld.long 0xC 0. "INIT,Initialization" "0: Normal Operation,1: Initialization is started"
|
|
line.long 0x10 "NBTP,Nominal Bit Timing & Prescaler Register"
|
|
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width"
|
|
hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point"
|
|
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point"
|
|
line.long 0x14 "TSCC,Timestamp Counter Configuration"
|
|
hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler (still used for TOCC)"
|
|
bitfld.long 0x14 0.--1. "TSS,Timestamp Select should always be set to external timestamp counter" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,?,?"
|
|
line.long 0x18 "TSCV,Timestamp Counter Value"
|
|
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter not used for M_TTCAN"
|
|
line.long 0x1C "TOCC,Timeout Counter Configuration"
|
|
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period"
|
|
bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,?,?"
|
|
newline
|
|
bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled,1: Timeout Counter enabled"
|
|
line.long 0x20 "TOCV,Timeout Counter Value"
|
|
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter"
|
|
rgroup.long ($2+0x40)++0x7
|
|
line.long 0x0 "ECR,Error Counter Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging"
|
|
bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter"
|
|
line.long 0x4 "PSR,Protocol Status Register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
|
|
bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
|
|
newline
|
|
bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0: Since this bit was reset by the CPU,1: Message in CAN FD format with FDF flag set has.."
|
|
bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set"
|
|
newline
|
|
bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set"
|
|
bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The M_CAN is not Bus_Off,1: The M_CAN is in Bus_Off state"
|
|
bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
|
|
newline
|
|
bitfld.long 0x4 5. "EP,Error Passive" "0: The M_CAN is in the Error_Active state,1: The M_CAN is in the Error_Passive state"
|
|
bitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing,1: Idle,?,?"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "LEC,Last Error Code " "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: AckError: The message transmitted by the M_TTCAN..,4: Bit1Error: During the transmission of a message,5: Bit0Error: During the transmission of a message,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol Status.."
|
|
group.long ($2+0x48)++0x3
|
|
line.long 0x0 "TDCR,Transmitter Delay Compensation Register"
|
|
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
|
|
hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length"
|
|
group.long ($2+0x50)++0xF
|
|
line.long 0x0 "IR,Interrupt Register"
|
|
bitfld.long 0x0 29. "ARA,N/A" "0,1"
|
|
bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit Time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected"
|
|
newline
|
|
bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase (Nominal Bit Time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected"
|
|
bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY"
|
|
newline
|
|
bitfld.long 0x0 25. "BO_,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
|
|
bitfld.long 0x0 24. "EW_,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
|
|
newline
|
|
bitfld.long 0x0 23. "EP_,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
|
|
bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow,1: Overflow of CAN Error Logging Counter occurred"
|
|
newline
|
|
bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Bit error detected"
|
|
bitfld.long 0x0 20. "BEC,M_TTCAN reports correctable ECC fault to the generic fault structure this bit always reads as 0." "0: No bit error detected when reading from Message..,1: Bit error detected and corrected"
|
|
newline
|
|
bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0: No Rx Buffer updated,1: At least one received message stored into a Rx.."
|
|
bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached"
|
|
newline
|
|
bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
|
|
bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
|
|
newline
|
|
bitfld.long 0x0 15. "TEFL_,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost"
|
|
bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full"
|
|
newline
|
|
bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO fill level below watermark,1: Tx Event FIFO fill level reached watermark"
|
|
bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element"
|
|
newline
|
|
bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
|
|
bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
|
|
newline
|
|
bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed"
|
|
bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received"
|
|
newline
|
|
bitfld.long 0x0 7. "RF1L_,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost"
|
|
bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark"
|
|
bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
|
|
newline
|
|
bitfld.long 0x0 3. "RF0L_,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost"
|
|
bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
newline
|
|
bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark"
|
|
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
|
|
line.long 0x4 "IE,Interrupt Enable"
|
|
bitfld.long 0x4 29. "ARAE,N/A" "0,1"
|
|
bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0,1"
|
|
bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable (not used in M_TTCAN)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 12. "TEFNE,Tx Event FIDO New Entry Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1"
|
|
line.long 0x8 "ILS,Interrupt Line Select"
|
|
bitfld.long 0x8 29. "ARAL,N/A" "0,1"
|
|
bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0,1"
|
|
bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
|
|
bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0,1"
|
|
bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1"
|
|
bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line (not used in M_TTCAN)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1"
|
|
bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
|
|
bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
|
|
bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0,1"
|
|
bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1"
|
|
line.long 0xC "ILE,Interrupt Line Enable"
|
|
bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line m_ttcan_int1 disabled,1: Interrupt line m_ttcan_int1 enabled"
|
|
bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line m_ttcan_int0 disabled,1: Interrupt line m_ttcan_int0 enabled"
|
|
group.long ($2+0x80)++0xB
|
|
line.long 0x0 "GFC,Global Filter Configuration"
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
|
|
newline
|
|
bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
|
|
bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs"
|
|
line.long 0x4 "SIDFC,Standard ID Filter Configuration"
|
|
hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard"
|
|
hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address"
|
|
line.long 0x8 "XIDFC,Extended ID Filter Configuration"
|
|
hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended"
|
|
hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address"
|
|
group.long ($2+0x90)++0x3
|
|
line.long 0x0 "XIDAM,Extended ID AND Mask"
|
|
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask"
|
|
rgroup.long ($2+0x94)++0x3
|
|
line.long 0x0 "HPMS,High Priority Message Status"
|
|
bitfld.long 0x0 15. "FLST,Filter List" "0: Standard Filter List,1: Extended Filter List"
|
|
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO message lost,?,?"
|
|
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index"
|
|
group.long ($2+0x98)++0xB
|
|
line.long 0x0 "NDAT1,New Data 1"
|
|
hexmask.long 0x0 0.--31. 1. "ND,New Data"
|
|
line.long 0x4 "NDAT2,New Data 2"
|
|
hexmask.long 0x4 0.--31. 1. "ND,New Data"
|
|
line.long 0x8 "RXF0C,Rx FIFO 0 Configuration"
|
|
bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode"
|
|
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size"
|
|
hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address"
|
|
rgroup.long ($2+0xA4)++0x3
|
|
line.long 0x0 "RXF0S,Rx FIFO 0 Status"
|
|
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost"
|
|
bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index"
|
|
hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level"
|
|
group.long ($2+0xA8)++0xB
|
|
line.long 0x0 "RXF0A,Rx FIFO 0 Acknowledge"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index"
|
|
line.long 0x4 "RXBC,Rx Buffer Configuration"
|
|
hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address"
|
|
line.long 0x8 "RXF1C,Rx FIFO 1 Configuration"
|
|
bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode"
|
|
hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size"
|
|
hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address"
|
|
rgroup.long ($2+0xB4)++0x3
|
|
line.long 0x0 "RXF1S,Rx FIFO 1 Status"
|
|
bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state,1: Debug message A received,?,?"
|
|
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost"
|
|
newline
|
|
bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index"
|
|
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level"
|
|
group.long ($2+0xB8)++0xB
|
|
line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index"
|
|
line.long 0x4 "RXESC,Rx Buffer / FIFO Element Size Configuration"
|
|
bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "F0DS,N/A" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "TXBC,Tx Buffer Configuration"
|
|
bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation"
|
|
hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
|
|
hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address"
|
|
rgroup.long ($2+0xC4)++0x3
|
|
line.long 0x0 "TXFQS,Tx FIFO/Queue Status"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index"
|
|
hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level"
|
|
group.long ($2+0xC8)++0x3
|
|
line.long 0x0 "TXESC,Tx Buffer Element Size Configuration"
|
|
bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
|
|
rgroup.long ($2+0xCC)++0x3
|
|
line.long 0x0 "TXBRP,Tx Buffer Request Pending"
|
|
hexmask.long 0x0 0.--31. 1. "TRP,Transmission Request Pending"
|
|
group.long ($2+0xD0)++0x7
|
|
line.long 0x0 "TXBAR,Tx Buffer Add Request"
|
|
hexmask.long 0x0 0.--31. 1. "AR,Add Request"
|
|
line.long 0x4 "TXBCR,Tx Buffer Cancellation Request"
|
|
hexmask.long 0x4 0.--31. 1. "CR,Cancellation Request"
|
|
rgroup.long ($2+0xD8)++0x7
|
|
line.long 0x0 "TXBTO,Tx Buffer Transmission Occurred"
|
|
hexmask.long 0x0 0.--31. 1. "TO,Transmission Occurred"
|
|
line.long 0x4 "TXBCF,Tx Buffer Cancellation Finished"
|
|
hexmask.long 0x4 0.--31. 1. "CF,Cancellation Finished"
|
|
group.long ($2+0xE0)++0x7
|
|
line.long 0x0 "TXBTIE,Tx Buffer Transmission Interrupt Enable"
|
|
hexmask.long 0x0 0.--31. 1. "TIE,Transmission Interrupt Enable"
|
|
line.long 0x4 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
|
|
hexmask.long 0x4 0.--31. 1. "CFIE,Cancellation Finished Interrupt Enable"
|
|
group.long ($2+0xF0)++0x3
|
|
line.long 0x0 "TXEFC,Tx Event FIFO Configuration"
|
|
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark"
|
|
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address"
|
|
rgroup.long ($2+0xF4)++0x3
|
|
line.long 0x0 "TXEFS,Tx Event FIFO Status"
|
|
bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index"
|
|
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level"
|
|
group.long ($2+0xF8)++0x3
|
|
line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge"
|
|
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index"
|
|
group.long ($2+0x100)++0x2B
|
|
line.long 0x0 "TTTMC,TT Trigger Memory Configuration"
|
|
hexmask.long.byte 0x0 16.--22. 1. "TME,Trigger Memory Elements"
|
|
hexmask.long.word 0x0 2.--15. 1. "TMSA,Trigger Memory Start Address"
|
|
line.long 0x4 "TTRMC,TT Reference Message Configuration"
|
|
bitfld.long 0x4 31. "RMPS,Reference Message Payload Select" "0: Reference message has no additional payload,1: bytes 2-8"
|
|
bitfld.long 0x4 30. "XTD,Extended Identifier" "0,1"
|
|
newline
|
|
hexmask.long 0x4 0.--28. 1. "RID,Reference Identifier"
|
|
line.long 0x8 "TTOCF,TT Operation Configuration"
|
|
bitfld.long 0x8 26. "EVTP,Event Trigger Polarity" "0: Rising edge trigger,1: Falling edge trigger"
|
|
bitfld.long 0x8 25. "ECC,Enable Clock Calibration" "0: Automatic clock calibration in TTCAN Level 0,1: Automatic clock calibration in TTCAN Level 0"
|
|
newline
|
|
bitfld.long 0x8 24. "EGTF,Enable Global Time Filtering" "0: Global time filtering in TTCAN Level 0,1: Global time filtering in TTCAN Level 0"
|
|
hexmask.long.byte 0x8 16.--23. 1. "AWL,Application Watchdog Limit"
|
|
newline
|
|
bitfld.long 0x8 15. "EECS,Enable External Clock Synchronization" "0: External clock synchronization in TTCAN Level 0,1: External clock synchronization in TTCAN Level 0"
|
|
hexmask.long.byte 0x8 8.--14. 1. "IRTO,Initial Reference Trigger Offset"
|
|
newline
|
|
bitfld.long 0x8 5.--7. "LDSDL,LD of Synchronization Deviation Limit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 4. "TM,Time Master" "0: Time Master function disabled,1: Potential Time Master"
|
|
newline
|
|
bitfld.long 0x8 3. "GEN,Gap Enable" "0: Strictly time-triggered operation,1: External event-synchronized time-triggered.."
|
|
bitfld.long 0x8 0.--1. "OM,Operation Mode" "0: Event-driven CAN communication,1: TTCAN level 1,?,?"
|
|
line.long 0xC "TTMLM,TT Matrix Limits"
|
|
hexmask.long.word 0xC 16.--27. 1. "ENTT,Expected Number of Tx Triggers"
|
|
hexmask.long.byte 0xC 8.--11. 1. "TXEW,Tx Enable Window"
|
|
newline
|
|
bitfld.long 0xC 6.--7. "CSS,N/A" "0,1,2,3"
|
|
hexmask.long.byte 0xC 0.--5. 1. "CCM,N/A"
|
|
line.long 0x10 "TURCF,TUR Configuration"
|
|
bitfld.long 0x10 31. "ELT,Enable Local Time" "0: Local time is stopped,1: Local time is enabled"
|
|
hexmask.long.word 0x10 16.--29. 1. "DC,Denominator Configuration"
|
|
newline
|
|
hexmask.long.word 0x10 0.--15. 1. "NCL,Numerator Configuration Low"
|
|
line.long 0x14 "TTOCN,TT Operation Control"
|
|
rbitfld.long 0x14 15. "LCKC,TT Operation Control Register Locked" "0: Write access to TTOCN enabled,1: Write access to TTOCN locked"
|
|
bitfld.long 0x14 13. "ESCN,External Synchronization Control" "0: External synchronization disabled,1: External synchronization enabled"
|
|
newline
|
|
bitfld.long 0x14 12. "NIG,Next is Gap" "0: No action,1: Transmit next reference message with Next_is_Gap.."
|
|
bitfld.long 0x14 11. "TMG,Time Mark Gap" "0: Reset by each reference message,1: Next reference message started when Register.."
|
|
newline
|
|
bitfld.long 0x14 10. "FGP,Finish Gap" "0: No reference message requested,1: Application requested start of reference message"
|
|
bitfld.long 0x14 9. "GCS,Gap Control Select" "0: Gap control independent from m_ttcan_evt,1: Gap control by input pin m_ttcan_evt"
|
|
newline
|
|
bitfld.long 0x14 8. "TTIE,Trigger Time Mark Interrupt Pulse Enable" "0: Trigger Time Mark Interrupt output m_ttcan_tmp..,1: Trigger Time Mark Interrupt output m_ttcan_tmp.."
|
|
bitfld.long 0x14 6.--7. "TMC,Register Time Mark Compare" "0: No Register Time Mark Interrupt generated,1: Register Time Mark Interrupt if Time Mark =..,?,?"
|
|
newline
|
|
bitfld.long 0x14 5. "RTIE,Register Time Mark Interrupt Pulse Enable" "0: Register Time Mark Interrupt output m_ttcan_rtp..,1: Register Time Mark Interrupt output m_ttcan_rtp.."
|
|
bitfld.long 0x14 3.--4. "SWS,Stop Watch Source" "0: Stop Watch disabled,1: Actual value of cycle time is copied to TTCPT,?,?"
|
|
newline
|
|
bitfld.long 0x14 2. "SWP,Stop Watch Polarity" "0: Rising edge trigger,1: Falling edge trigger"
|
|
bitfld.long 0x14 1. "ECS,External Clock Synchronization" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "SGT,Set Global time" "0,1"
|
|
line.long 0x18 "TTGTP,TT Global Time Preset"
|
|
hexmask.long.word 0x18 16.--31. 1. "CTP,Cycle Time Target Phase"
|
|
hexmask.long.word 0x18 0.--15. 1. "TP,N/A"
|
|
line.long 0x1C "TTTMK,TT Time Mark"
|
|
rbitfld.long 0x1C 31. "LCKM,TT Time Mark Register Locked" "0: Write access to TTTMK enabled,1: Write access to TTTMK locked"
|
|
hexmask.long.byte 0x1C 16.--22. 1. "TICC,Time Mark Cycle Code"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--15. 1. "TM_,Time Mark"
|
|
line.long 0x20 "TTIR,TT Interrupt Register"
|
|
bitfld.long 0x20 18. "CER,Configuration Error" "0: No error found in trigger list,1: Error found in trigger list"
|
|
bitfld.long 0x20 17. "AW,Application Watchdog" "0: Application watchdog served in time,1: Application watchdog not served in time"
|
|
newline
|
|
bitfld.long 0x20 16. "WT,Watch Trigger" "0: cycle time 0xFF00),1: Missing reference message"
|
|
bitfld.long 0x20 15. "IWT,Initialization Watch Trigger" "0: No missing reference message during system startup,1: No system startup due to missing reference message"
|
|
newline
|
|
bitfld.long 0x20 14. "ELC,Error Level Changed" "0: No change in error level,1: Error level changed"
|
|
bitfld.long 0x20 13. "SE2,Scheduling Error 2" "0: No scheduling error 2,1: Scheduling error 2 occurred"
|
|
newline
|
|
bitfld.long 0x20 12. "SE1,Scheduling Error 1" "0: No scheduling error 1,1: Scheduling error 1 occurred"
|
|
bitfld.long 0x20 11. "TXO,Tx Count Overflow" "0: Number of Tx Trigger as expected,1: More Tx trigger than expected in one matrix cycle"
|
|
newline
|
|
bitfld.long 0x20 10. "TXU,Tx Count Underflow" "0: Number of Tx Trigger as expected,1: Less Tx trigger than expected in one matrix cycle"
|
|
bitfld.long 0x20 9. "GTE,Global Time Error" "0: Synchronization deviation within limit,1: Synchronization deviation exceeded limit"
|
|
newline
|
|
bitfld.long 0x20 8. "GTD,Global Time Discontinuity" "0: No discontinuity of global time,1: Discontinuity of global time"
|
|
bitfld.long 0x20 7. "GTW,Global Time Wrap" "0: No global time wrap occurred,1: Global time wrap from 0xFFFF to 0x0000 occurred"
|
|
newline
|
|
bitfld.long 0x20 6. "SWE,Stop Watch Event" "0: No rising/falling edge at stop watch trigger pin..,1: Rising/falling edge at stop watch trigger pin.."
|
|
bitfld.long 0x20 5. "TTMI,Trigger Time Mark Event Internal" "0: cycle time TTOCF,1: Time mark reached"
|
|
newline
|
|
bitfld.long 0x20 4. "RTMI,Register Time Mark Interrupt" "0: Time mark not reached,1: Time mark reached"
|
|
bitfld.long 0x20 3. "SOG,Start of Gap" "0: No reference message seen with Next_is_Gap bit set,1: Reference message with Next_is_Gap bit set.."
|
|
newline
|
|
bitfld.long 0x20 2. "CSM_,Change of Synchronization Mode" "0: No change in master to slave relation or..,1: Master to slave relation or schedule.."
|
|
bitfld.long 0x20 1. "SMC,Start of Matrix Cycle" "0: No Matrix Cycle started since bit has been reset,1: Matrix Cycle started"
|
|
newline
|
|
bitfld.long 0x20 0. "SBC,Start of Basic Cycle" "0: No Basic Cycle started since bit has been reset,1: Basic Cycle started"
|
|
line.long 0x24 "TTIE,TT Interrupt Enable"
|
|
bitfld.long 0x24 18. "CERE,Configuration Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x24 17. "AWE_,Application Watchdog Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x24 16. "WTE,Watch Trigger Interrupt Enable" "0,1"
|
|
bitfld.long 0x24 15. "IWTE,Initialization Watch Trigger Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x24 14. "ELCE,Change Error Level Interrupt Enable" "0,1"
|
|
bitfld.long 0x24 13. "SE2E,Scheduling Error 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x24 12. "SE1E,Scheduling Error 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x24 11. "TXOE,Tx Count Overflow Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x24 10. "TXUE,Tx Count Underflow Interrupt Enable" "0,1"
|
|
bitfld.long 0x24 9. "GTEE,Global Time Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x24 8. "GTDE,Global Time Discontinuity Interrupt Enable" "0,1"
|
|
bitfld.long 0x24 7. "GTWE,Global Time Wrap Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x24 6. "SWEE,Stop Watch Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x24 5. "TTMIE,Trigger Time Mark Event Internal Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x24 4. "RTMIE,Register Time Mark Interrupt Enable" "0,1"
|
|
bitfld.long 0x24 3. "SOGE,Start of Gap Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x24 2. "CSME,Change of Synchronization Mode Interrupt Enable" "0,1"
|
|
bitfld.long 0x24 1. "SMCE,Start of Matrix Cycle Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x24 0. "SBCE,Start of Basic Cycle Interrupt Enable" "0,1"
|
|
line.long 0x28 "TTILS,TT Interrupt Line Select"
|
|
bitfld.long 0x28 18. "CERL,Configuration Error Interrupt Line" "0,1"
|
|
bitfld.long 0x28 17. "AWL_,Application Watchdog Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x28 16. "WTL,Watch Trigger Interrupt Line" "0,1"
|
|
bitfld.long 0x28 15. "IWTL,Initialization Watch Trigger Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x28 14. "ELCL,Change Error Level Interrupt Line" "0,1"
|
|
bitfld.long 0x28 13. "SE2L,Scheduling Error 2 Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x28 12. "SE1L,Scheduling Error 1 Interrupt Line" "0,1"
|
|
bitfld.long 0x28 11. "TXOL,Tx Count Overflow Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x28 10. "TXUL,Tx Count Underflow Interrupt Line" "0,1"
|
|
bitfld.long 0x28 9. "GTEL,Global Time Error Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x28 8. "GTDL,Global Time Discontinuity Interrupt Line" "0,1"
|
|
bitfld.long 0x28 7. "GTWL,Global Time Wrap Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x28 6. "SWEL,Stop Watch Event Interrupt Line" "0,1"
|
|
bitfld.long 0x28 5. "TTMIL,Trigger Time Mark Event Internal Line" "0,1"
|
|
newline
|
|
bitfld.long 0x28 4. "RTMIL,Register Time Mark Interrupt Line" "0,1"
|
|
bitfld.long 0x28 3. "SOGL,Start of Gap Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x28 2. "CSML,Change of Synchronization Mode Interrupt Line" "0,1"
|
|
bitfld.long 0x28 1. "SMCL,Start of Matrix Cycle Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x28 0. "SBCL,Start of Basic Cycle Interrupt Line" "0,1"
|
|
rgroup.long ($2+0x12C)++0x17
|
|
line.long 0x0 "TTOST,TT Operation Status"
|
|
bitfld.long 0x0 31. "SPL,Schedule Phase Lock" "0: Phase outside range,1: Phase inside range"
|
|
bitfld.long 0x0 30. "WECS,Wait for External Clock Synchronization" "0: No external clock synchronization pending,1: Node waits for external clock synchronization to.."
|
|
newline
|
|
bitfld.long 0x0 29. "AWE,Application Watchdog Event" "0: Application Watchdog served in time,1: Failed to serve Application Watchdog in time"
|
|
bitfld.long 0x0 28. "WFE,Wait for Event" "0: No Gap announced,1: Reference message with Next_is_Gap = '1' received"
|
|
newline
|
|
bitfld.long 0x0 27. "GSI,Gap Started Indicator" "0: No Gap in schedule,1: Gap time after Basic Cycle has started"
|
|
bitfld.long 0x0 24.--26. "TMP,Time Master Priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 23. "GFI,Gap Finished Indicator" "0: Reset at the end of each reference message,1: Gap finished by M_TTCAN"
|
|
bitfld.long 0x0 22. "WGTD,Wait for Global Time Discontinuity" "0: No global time preset pending,1: Node waits for the global time preset to take.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RTO,Reference Trigger Offset"
|
|
bitfld.long 0x0 7. "QCS,Quality of Clock Speed" "0: Local clock speed not synchronized to Time..,1: Synchronization Deviation <= SDL"
|
|
newline
|
|
bitfld.long 0x0 6. "QGTP,Quality of Global Time Phase" "0: Global time not valid,1: Global time in phase with Time Master"
|
|
bitfld.long 0x0 4.--5. "SYS,Synchronization State" "0: Out of Synchronization,1: Synchronizing to TTCAN communication,?,?"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MS,Master State" "0: Master_Off,1: Operating as Time Slave,?,?"
|
|
bitfld.long 0x0 0.--1. "EL,Error Level" "0: Severity 0,1: Severity 1,?,?"
|
|
line.long 0x4 "TURNA,TUR Numerator Actual"
|
|
hexmask.long.tbyte 0x4 0.--17. 1. "NAV,N/A"
|
|
line.long 0x8 "TTLGT,TT Local & Global Time"
|
|
hexmask.long.word 0x8 16.--31. 1. "GT,Global Time"
|
|
hexmask.long.word 0x8 0.--15. 1. "LT,Local Time"
|
|
line.long 0xC "TTCTC,TT Cycle Time & Count"
|
|
hexmask.long.byte 0xC 16.--21. 1. "CC,Cycle Count"
|
|
hexmask.long.word 0xC 0.--15. 1. "CT,Cycle Time"
|
|
line.long 0x10 "TTCPT,TT Capture Time"
|
|
hexmask.long.word 0x10 16.--31. 1. "SWV,Stop Watch Value"
|
|
hexmask.long.byte 0x10 0.--5. 1. "CCV,Cycle Count Value"
|
|
line.long 0x14 "TTCSM,TT Cycle Sync Mark"
|
|
hexmask.long.word 0x14 0.--15. 1. "CSM,Cycle Sync Mark"
|
|
tree.end
|
|
group.long ($2+0x180)++0x3
|
|
newline
|
|
line.long 0x0 "RXFTOP_CTL,Receive FIFO Top control"
|
|
bitfld.long 0x0 1. "F1TPE,FIFO 1 Top Pointer Enable." "0,1"
|
|
bitfld.long 0x0 0. "F0TPE,FIFO 0 Top Pointer Enable." "0,1"
|
|
rgroup.long ($2+0x1A0)++0x3
|
|
line.long 0x0 "RXFTOP0_STAT,Receive FIFO 0 Top Status"
|
|
hexmask.long.word 0x0 0.--15. 1. "F0TA,Current FIFO 0 Top Address."
|
|
rgroup.long ($2+0x1A8)++0x3
|
|
line.long 0x0 "RXFTOP0_DATA,Receive FIFO 0 Top Data"
|
|
hexmask.long 0x0 0.--31. 1. "F0TD,When enabled (F0TPE=1) read data from MRAM at location FnTA. This register can have a read side effect if the following conditions are met:"
|
|
rgroup.long ($2+0x1B0)++0x3
|
|
line.long 0x0 "RXFTOP1_STAT,Receive FIFO 1 Top Status"
|
|
hexmask.long.word 0x0 0.--15. 1. "F1TA,See F0TA description"
|
|
rgroup.long ($2+0x1B8)++0x3
|
|
line.long 0x0 "RXFTOP1_DATA,Receive FIFO 1 Top Data"
|
|
hexmask.long 0x0 0.--31. 1. "F1TD,See F0TD description"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40540000
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "CTL,Global CAN control register"
|
|
bitfld.long 0x0 31. "MRAM_OFF,MRAM off" "0: Default MRAM on,1: Switch MRAM off"
|
|
hexmask.long.byte 0x0 0.--7. 1. "STOP_REQ,Clock Stop Request for each TTCAN IP ."
|
|
rgroup.long 0x1004++0x3
|
|
line.long 0x0 "STATUS,Global CAN status register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "STOP_ACK,Clock Stop Acknowledge for each TTCAN IP."
|
|
rgroup.long 0x1010++0x7
|
|
line.long 0x0 "INTR0_CAUSE,Consolidated interrupt0 cause register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT0,Show pending m_ttcan_int0 of each channel"
|
|
line.long 0x4 "INTR1_CAUSE,Consolidated interrupt1 cause register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "INT1,Show pending m_ttcan_int1 of each channel"
|
|
group.long 0x1020++0x7
|
|
line.long 0x0 "TS_CTL,Time Stamp control register"
|
|
bitfld.long 0x0 31. "ENABLED,Counter enable bit" "0: Count disabled,1: Count enabled"
|
|
hexmask.long.word 0x0 0.--15. 1. "PRESCALE,Time Stamp counter prescale value."
|
|
line.long 0x4 "TS_CNT,Time Stamp counter value"
|
|
hexmask.long.word 0x4 0.--15. 1. "VALUE,The counter value of the Time Stamp Counter."
|
|
group.long 0x1080++0x7
|
|
line.long 0x0 "ECC_CTL,ECC control"
|
|
bitfld.long 0x0 16. "ECC_EN,Enable ECC for CANFD SRAM" "0,1"
|
|
line.long 0x4 "ECC_ERR_INJ,ECC error injection"
|
|
hexmask.long.byte 0x4 24.--30. 1. "ERR_PAR,ECC Parity bits to use for ECC error injection at address ERR_ADDR."
|
|
bitfld.long 0x4 20. "ERR_EN,Enable error injection (ECC_EN must be 1)." "0,1"
|
|
hexmask.long.word 0x4 2.--15. 1. "ERR_ADDR,Specifies the address of the word where an error will be injected on write or an non-correctable error will be suppressed."
|
|
tree.end
|
|
tree.end
|
|
tree "CPUSS (CPU Subsystem)"
|
|
base ad:0x40200000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "IDENTITY,Identity"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MS,This field specifies the bus master identifier of the transfer that reads the register."
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,This field specifies the protection context of the transfer that reads the register."
|
|
newline
|
|
bitfld.long 0x0 1. "NS,This field specifies the security setting ('0': secure mode; '1': non-secure mode) of the transfer that reads the register." "0,1"
|
|
bitfld.long 0x0 0. "P,This field specifies the privileged setting ('0': user mode; '1': privileged mode) of the transfer that reads the register." "0,1"
|
|
line.long 0x4 "CM4_STATUS,CM4 status"
|
|
bitfld.long 0x4 4. "PWR_DONE,After a PWR_MODE change this flag indicates if the new power mode has taken effect or not." "0,1"
|
|
bitfld.long 0x4 1. "SLEEPDEEP,Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "SLEEPING,Specifies if the CPU is in Active Sleep or DeepSleep power mode:" "0,1"
|
|
group.long 0x8++0x7
|
|
line.long 0x0 "CM4_CLOCK_CTL,CM4 clock control"
|
|
hexmask.long.byte 0x0 8.--15. 1. "FAST_INT_DIV,Specifies the fast clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_fast'). Integer division by (1+FAST_INT_DIV). Allows for integer divisions in the range [1 256] (FAST_INT_DIV is in the range [0 255])."
|
|
line.long 0x4 "CM4_CTL,CM4 control"
|
|
bitfld.long 0x4 31. "IDC_MASK,CPU FPU exception mask for the CPU's FPCSR.IDC 'input denormalized' exception condition:" "0,1"
|
|
bitfld.long 0x4 28. "IXC_MASK,CPU FPU exception mask for the CPU's FPCSR.IXC 'inexact' exception condition:" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "UFC_MASK,CPU FPU exception mask for the CPU's FPCSR.UFC 'underflow' exception condition:" "0,1"
|
|
bitfld.long 0x4 26. "OFC_MASK,CPU FPU exception mask for the CPU's FPCSR.OFC 'overflow' exception condition:" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "DZC_MASK,CPU FPU exception mask for the CPU's FPCSR.DZC 'divide by zero' exception condition:" "0,1"
|
|
bitfld.long 0x4 24. "IOC_MASK,CPU floating point unit (FPU) exception mask for the CPU's FPCSR.IOC 'invalid operation' exception condition:" "0,1"
|
|
rgroup.long 0x100++0x1F
|
|
line.long 0x0 "CM4_INT0_STATUS,CM4 interrupt 0 status"
|
|
bitfld.long 0x0 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x0 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM4 activated system interrupt index for CPU interrupt 0."
|
|
line.long 0x4 "CM4_INT1_STATUS,CM4 interrupt 1 status"
|
|
bitfld.long 0x4 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM4 activated system interrupt index for CPU interrupt 1."
|
|
line.long 0x8 "CM4_INT2_STATUS,CM4 interrupt 2 status"
|
|
bitfld.long 0x8 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x8 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM4 activated system interrupt index for CPU interrupt 2."
|
|
line.long 0xC "CM4_INT3_STATUS,CM4 interrupt 3 status"
|
|
bitfld.long 0xC 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0xC 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM4 activated system interrupt index for CPU interrupt 3."
|
|
line.long 0x10 "CM4_INT4_STATUS,CM4 interrupt 4 status"
|
|
bitfld.long 0x10 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x10 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM4 activated system interrupt index for CPU interrupt 4."
|
|
line.long 0x14 "CM4_INT5_STATUS,CM4 interrupt 5 status"
|
|
bitfld.long 0x14 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x14 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM4 activated system interrupt index for CPU interrupt 5."
|
|
line.long 0x18 "CM4_INT6_STATUS,CM4 interrupt 6 status"
|
|
bitfld.long 0x18 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x18 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM4 activated system interrupt index for CPU interrupt 6."
|
|
line.long 0x1C "CM4_INT7_STATUS,CM4 interrupt 7 status"
|
|
bitfld.long 0x1C 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x1C 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM4 activated system interrupt index for CPU interrupt 7."
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "CM4_VECTOR_TABLE_BASE,CM4 vector table base"
|
|
hexmask.long.tbyte 0x0 10.--31. 1. "ADDR22,Address of CM4 vector table. This register is used for CM4 warm and cold boot purposes: the CM0+ CPU initializes the CM4_VECTOR_TABLE_BASE register and the CM4 boot code uses the register to initialize the CM4 internal VTOR register."
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x240)++0x3
|
|
line.long 0x0 "CM4_NMI_CTL[$1],CM4 NMI control"
|
|
hexmask.long.word 0x0 0.--9. 1. "SYSTEM_INT_IDX,System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset."
|
|
repeat.end
|
|
group.long 0x300++0x7
|
|
line.long 0x0 "UDB_PWR_CTL,UDB power control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)."
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Set Power mode for UDBs" "0: See CM4_PWR_CTL,1: See CM4_PWR_CTL,2: See CM4_PWR_CTL,3: See CM4_PWR_CTL"
|
|
line.long 0x4 "UDB_PWR_DELAY_CTL,UDB power control"
|
|
hexmask.long.word 0x4 0.--9. 1. "UP,Number clock cycles delay needed after power domain power up"
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "CM0_CTL,CM0+ control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)."
|
|
bitfld.long 0x0 1. "ENABLED,Processor enable:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SLV_STALL,Processor debug access control:" "0,1"
|
|
rgroup.long 0x1004++0x3
|
|
line.long 0x0 "CM0_STATUS,CM0+ status"
|
|
bitfld.long 0x0 1. "SLEEPDEEP,Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field." "0,1"
|
|
bitfld.long 0x0 0. "SLEEPING,Specifies if the CPU is in Active Sleep or DeepSleep power mode:" "0,1"
|
|
group.long 0x1008++0x3
|
|
line.long 0x0 "CM0_CLOCK_CTL,CM0+ clock control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PERI_INT_DIV,Specifies the peripheral clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_peri'). Integer division by (1+PERI_INT_DIV). Allows for integer divisions in the range [1 256] (PERI_INT_DIV is in the range [0 .."
|
|
hexmask.long.byte 0x0 8.--15. 1. "SLOW_INT_DIV,Specifies the slow clock divider (from the peripheral clock 'clk_peri' to the slow clock 'clk_slow'). Integer division by (1+SLOW_INT_DIV). Allows for integer divisions in the range [1 256] (SLOW_INT_DIV is in the range [0 255])."
|
|
rgroup.long 0x1100++0x1F
|
|
line.long 0x0 "CM0_INT0_STATUS,CM0+ interrupt 0 status"
|
|
bitfld.long 0x0 31. "SYSTEM_INT_VALID,Valid indication for SYSTEM_INT_IDX. When '0' no system interrupt for CPU interrupt 0 is valid/activated." "0,1"
|
|
hexmask.long.word 0x0 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 0."
|
|
line.long 0x4 "CM0_INT1_STATUS,CM0+ interrupt 1 status"
|
|
bitfld.long 0x4 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 1."
|
|
line.long 0x8 "CM0_INT2_STATUS,CM0+ interrupt 2 status"
|
|
bitfld.long 0x8 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x8 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 2."
|
|
line.long 0xC "CM0_INT3_STATUS,CM0+ interrupt 3 status"
|
|
bitfld.long 0xC 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0xC 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 3."
|
|
line.long 0x10 "CM0_INT4_STATUS,CM0+ interrupt 4 status"
|
|
bitfld.long 0x10 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x10 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 4."
|
|
line.long 0x14 "CM0_INT5_STATUS,CM0+ interrupt 5 status"
|
|
bitfld.long 0x14 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x14 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 5."
|
|
line.long 0x18 "CM0_INT6_STATUS,CM0+ interrupt 6 status"
|
|
bitfld.long 0x18 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x18 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 6."
|
|
line.long 0x1C "CM0_INT7_STATUS,CM0+ interrupt 7 status"
|
|
bitfld.long 0x1C 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x1C 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 7."
|
|
group.long 0x1120++0x3
|
|
line.long 0x0 "CM0_VECTOR_TABLE_BASE,CM0+ vector table base"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR24,Address of CM0+ vector table. This register is used for CM0+ warm boot purposes: the CM0+ warm boot code uses the register to initialize the CM0+ internal VTOR register."
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1140)++0x3
|
|
line.long 0x0 "CM0_NMI_CTL[$1],CM0+ NMI control"
|
|
hexmask.long.word 0x0 0.--9. 1. "SYSTEM_INT_IDX,System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset."
|
|
repeat.end
|
|
group.long 0x1200++0x7
|
|
line.long 0x0 "CM4_PWR_CTL,CM4 power control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)."
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Power mode." "0: Switch CM4 off Power off clock off isolate reset..,1: Reset CM4 Clock off no isolated no retain and..,2: Put CM4 in Retained mode This can only become..,3: Switch CM4 on. Power on clock on no isolate no.."
|
|
line.long 0x4 "CM4_PWR_DELAY_CTL,CM4 power control"
|
|
hexmask.long.word 0x4 0.--9. 1. "UP,Number clock cycles delay needed after power domain power up"
|
|
group.long 0x1300++0x3
|
|
line.long 0x0 "RAM0_CTL0,RAM 0 control"
|
|
bitfld.long 0x0 18. "ECC_INJ_EN,Enable error injection for system SRAM 0." "0,1"
|
|
bitfld.long 0x0 17. "ECC_AUTO_CORRECT,HW ECC autocorrect functionality:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ECC_EN,Enable ECC checking:" "0,1"
|
|
bitfld.long 0x0 8.--9. "FAST_WS,Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SLOW_WS,Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles." "0,1,2,3"
|
|
rgroup.long 0x1304++0x3
|
|
line.long 0x0 "RAM0_STATUS,RAM 0 status"
|
|
bitfld.long 0x0 0. "WB_EMPTY,Write buffer empty. This information is used when entering DeepSleep power mode: WB_EMPTY must be '1' before a transition to system DeepSleep power mode." "0,1"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1340)++0x3
|
|
line.long 0x0 "RAM0_PWR_MACRO_CTL[$1],RAM 0 power control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)."
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,SRAM Power mode." "0: Turn OFF the SRAM. This will trun OFF both array..,1: undefined,2: Keep SRAM in Retained mode. This will turn OFF..,3: Enable SRAM for regular operation. The SRAM.."
|
|
repeat.end
|
|
group.long 0x1380++0x3
|
|
line.long 0x0 "RAM1_CTL0,RAM 1 control"
|
|
bitfld.long 0x0 18. "ECC_INJ_EN,See RAM0_CTL." "0,1"
|
|
bitfld.long 0x0 17. "ECC_AUTO_CORRECT,See RAM0_CTL." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ECC_EN,See RAM0_CTL." "0,1"
|
|
bitfld.long 0x0 8.--9. "FAST_WS,See RAM0_CTL." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SLOW_WS,See RAM0_CTL." "0,1,2,3"
|
|
rgroup.long 0x1384++0x3
|
|
line.long 0x0 "RAM1_STATUS,RAM 1 status"
|
|
bitfld.long 0x0 0. "WB_EMPTY,See RAM0_STATUS." "0,1"
|
|
group.long 0x1388++0x3
|
|
line.long 0x0 "RAM1_PWR_CTL,RAM 1 power control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,See RAM0_PWR_MACRO_CTL."
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Power mode." "0: See RAM0_PWR_MACRO_CTL.,1: undefined,2: See RAM0_PWR_MACRO_CTL.,3: See RAM0_PWR_MACRO_CTL."
|
|
group.long 0x13A0++0x3
|
|
line.long 0x0 "RAM2_CTL0,RAM 2 control"
|
|
bitfld.long 0x0 18. "ECC_INJ_EN,See RAM0_CTL." "0,1"
|
|
bitfld.long 0x0 17. "ECC_AUTO_CORRECT,See RAM0_CTL." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ECC_EN,See RAM0_CTL." "0,1"
|
|
bitfld.long 0x0 8.--9. "FAST_WS,See RAM0_CTL." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SLOW_WS,See RAM0_CTL." "0,1,2,3"
|
|
rgroup.long 0x13A4++0x3
|
|
line.long 0x0 "RAM2_STATUS,RAM 2 status"
|
|
bitfld.long 0x0 0. "WB_EMPTY,See RAM0_STATUS." "0,1"
|
|
group.long 0x13A8++0x3
|
|
line.long 0x0 "RAM2_PWR_CTL,RAM 2 power control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,See RAM0_PWR_MACRO_CTL."
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Power mode." "0: See RAM0_PWR_MACRO_CTL.,1: undefined,2: See RAM0_PWR_MACRO_CTL.,3: See RAM0_PWR_MACRO_CTL."
|
|
group.long 0x13C0++0xB
|
|
line.long 0x0 "RAM_PWR_DELAY_CTL,Power up delay used for all SRAM power domains"
|
|
hexmask.long.word 0x0 0.--9. 1. "UP,Number clock cycles delay needed after power domain power up"
|
|
line.long 0x4 "ROM_CTL,ROM control"
|
|
bitfld.long 0x4 8.--9. "FAST_WS,Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles." "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "SLOW_WS,Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles." "0,1,2,3"
|
|
line.long 0x8 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x8 25.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR."
|
|
hexmask.long 0x8 0.--24. 1. "WORD_ADDR,Specifies the word address where an error will be injected."
|
|
rgroup.long 0x1400++0x3
|
|
line.long 0x0 "PRODUCT_ID,Product identifier and version (same as CoreSight RomTables)"
|
|
hexmask.long.byte 0x0 20.--23. 1. "MINOR_REV,Minor Revision starts with 1 increments with metal layer only tape-out (implemented with metal ECO-able tie-off)"
|
|
hexmask.long.byte 0x0 16.--19. 1. "MAJOR_REV,Major Revision starts with 1 increments with all layer tape-out (implemented with metal ECO-able tie-off)"
|
|
newline
|
|
hexmask.long.word 0x0 0.--11. 1. "FAMILY_ID,Family ID a.k.a. Partnumber a.k.a. Silicon ID"
|
|
rgroup.long 0x1410++0x3
|
|
line.long 0x0 "DP_STATUS,Debug port status"
|
|
bitfld.long 0x0 2. "SWJ_JTAG_SEL,Specifies if the JTAG or SWD interface is selected. This signal is valid when DP_CTL.PTM_SEL is '0' (SWJ mode selected) and SWJ_CONNECTED is '1' (SWJ is connected)." "0,1"
|
|
bitfld.long 0x0 1. "SWJ_DEBUG_EN,Specifies if SWJ debug is enabled i.e. CDBGPWRUPACK is '1' and thus debug clocks are on:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWJ_CONNECTED,Specifies if the SWJ debug port is connected; i.e. debug host interface is active:" "0,1"
|
|
group.long 0x1414++0x3
|
|
line.long 0x0 "AP_CTL,Access port control"
|
|
bitfld.long 0x0 18. "SYS_DISABLE,Disables the system AP interface:" "0,1"
|
|
bitfld.long 0x0 17. "CM4_DISABLE,Disables the CM4 AP interface:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "CM0_DISABLE,Disables the CM0 AP interface:" "0,1"
|
|
bitfld.long 0x0 2. "SYS_ENABLE,Enables the system AP interface:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CM4_ENABLE,Enables the CM4 AP interface:" "0,1"
|
|
bitfld.long 0x0 0. "CM0_ENABLE,Enables the CM0 AP interface:" "0,1"
|
|
group.long 0x1500++0x3
|
|
line.long 0x0 "BUFF_CTL,Buffer control"
|
|
bitfld.long 0x0 0. "WRITE_BUFF,Specifies if write transfer can be buffered in the bus infrastructure bridges:" "0,1"
|
|
group.long 0x1600++0x3
|
|
line.long 0x0 "SYSTICK_CTL,SysTick timer control"
|
|
bitfld.long 0x0 31. "NOREF,Specifies if an external clock source is provided:" "0,1"
|
|
bitfld.long 0x0 30. "SKEW,Specifies the precision of the clock source and if the TENMS field represents exactly 10 ms (clock source frequency is a multiple of 100 Hz). This affects the suitability of the SysTick timer as a SW real-time clock:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "CLOCK_SOURCE,Specifies an external clock source:" "0,1,2,3"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "TENMS,Specifies the number of clock source cycles (minus 1) that make up 10 ms. E.g. for a 32 768 Hz reference clock TENMS is 328 - 1 = 327."
|
|
rgroup.long 0x1704++0x3
|
|
line.long 0x0 "MBIST_STAT,Memory BIST status"
|
|
bitfld.long 0x0 1. "SFP_FAIL,Report status of the BIST run only valid if SFP_READY=1" "0,1"
|
|
bitfld.long 0x0 0. "SFP_READY,Flag indicating the BIST run is done. Note that after starting a BIST run this flag must be set before a new run can be started. For the first BIST run this will be 0." "0,1"
|
|
group.long 0x1800++0x7
|
|
line.long 0x0 "CAL_SUP_SET,Calibration support set and read"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Read without side effect write 1 to set"
|
|
line.long 0x4 "CAL_SUP_CLR,Calibration support clear and reset"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Read side effect: when read all bits are cleared write 1 to clear a specific bit"
|
|
group.long 0x2000++0x3
|
|
line.long 0x0 "CM0_PC_CTL,CM0+ protection context control"
|
|
hexmask.long.byte 0x0 0.--3. 1. "VALID,Valid fields for the protection context handler CM0_PCi_HANDLER registers:"
|
|
group.long 0x2040++0xF
|
|
line.long 0x0 "CM0_PC0_HANDLER,CM0+ protection context 0 handler"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Address of the protection context 0 handler. This field is used to detect entry to Cypress 'trusted' code through an exception/interrupt."
|
|
line.long 0x4 "CM0_PC1_HANDLER,CM0+ protection context 1 handler"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,Address of the protection context 1 handler."
|
|
line.long 0x8 "CM0_PC2_HANDLER,CM0+ protection context 2 handler"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,Address of the protection context 2 handler."
|
|
line.long 0xC "CM0_PC3_HANDLER,CM0+ protection context 3 handler"
|
|
hexmask.long 0xC 0.--31. 1. "ADDR,Address of the protection context 3 handler."
|
|
group.long 0x20C4++0x3
|
|
line.long 0x0 "PROTECTION,Protection status"
|
|
bitfld.long 0x0 0.--2. "STATE,Protection state:" "0,1,2,3,4,5,6,7"
|
|
group.long 0x2100++0x7
|
|
line.long 0x0 "TRIM_ROM_CTL,ROM trim control"
|
|
hexmask.long 0x0 0.--31. 1. "TRIM,N/A"
|
|
line.long 0x4 "TRIM_RAM_CTL,RAM trim control"
|
|
hexmask.long 0x4 0.--31. 1. "TRIM,N/A"
|
|
repeat 1023. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x8000)++0x3
|
|
line.long 0x0 "CM0_SYSTEM_INT_CTL[$1],CM0+ system interrupt control"
|
|
bitfld.long 0x0 31. "CPU_INT_VALID,Interrupt enable:" "0,1"
|
|
bitfld.long 0x0 0.--2. "CPU_INT_IDX,CPU interrupt index (legal range [0 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g. if CPU_INT_IDX is '6' the system interrupt is mapped to CPU interrupt '6'." "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
repeat 1023. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xA000)++0x3
|
|
line.long 0x0 "CM4_SYSTEM_INT_CTL[$1],CM4 system interrupt control"
|
|
bitfld.long 0x0 31. "CPU_INT_VALID,N/A" "0,1"
|
|
bitfld.long 0x0 0.--2. "CPU_INT_IDX,N/A" "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
tree.end
|
|
tree "CRYPTO (Cryptography Component)"
|
|
base ad:0x40100000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "ENABLED,IP enable:" "0: N/A,1: N/A"
|
|
bitfld.long 0x0 17. "ECC_INJ_EN,Enable parity injection for SRAM." "0,1"
|
|
bitfld.long 0x0 16. "ECC_EN,Enable ECC checking:" "0,1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
newline
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
group.long 0x8++0xB
|
|
line.long 0x0 "RAM_PWR_CTL,SRAM power control"
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Set power mode for memory buffer SRAM." "0: See CM4_PWR_CTL,1: undefined,2: See CM4_PWR_CTL,3: See CM4_PWR_CTL"
|
|
line.long 0x4 "RAM_PWR_DELAY_CTL,SRAM power delay control"
|
|
hexmask.long.word 0x4 0.--9. 1. "UP,Number clock cycles delay needed after power domain power up"
|
|
line.long 0x8 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x8 25.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR."
|
|
hexmask.long.word 0x8 0.--12. 1. "WORD_ADDR,Specifies the word address where the parity is injected."
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "ERROR_STATUS0,Error status 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Specifies error description information."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "ERROR_STATUS1,Error status 1"
|
|
bitfld.long 0x0 31. "VALID,Specifies if ERROR_STATUS0 and ERROR_STATUS1 specify valid error information. No new error information is captured as long as VALID is '1'; i.e. the error information of the first detected error is NOT overwritten." "0,1"
|
|
rbitfld.long 0x0 24.--26. "IDX,Error source:" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "DATA24,Specifies error description information."
|
|
group.long 0x100++0xB
|
|
line.long 0x0 "INTR,Interrupt register"
|
|
bitfld.long 0x0 21. "INSTR_DEV_KEY_ERROR,This interrupt cause is activated (HW sets the field to '1') when the LOAD_DEV_KEY instruction tries to load a device key whose DEV_KEY_ADDR_CTL.VALID or DEV_KEY_CTL.ALLOWED is set to '0'." "0,1"
|
|
bitfld.long 0x0 20. "TR_RC_DETECT_ERROR,This interrupt cause is activated (HW sets the field to '1') when the true random number generator monitor adaptive proportion test detects a disproportionate occurrence of a specific bit value." "0,1"
|
|
bitfld.long 0x0 19. "TR_AP_DETECT_ERROR,This interrupt cause is activated (HW sets the field to '1') when the true random number generator monitor adaptive proportion test detects a repetition of a specific bit value." "0,1"
|
|
bitfld.long 0x0 18. "BUS_ERROR,This interrupt cause is activated (HW sets the field to '1') when a AHB-Lite bus error is observed on the AHB-Lite master interface." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "INSTR_CC_ERROR,This interrupt cause is activated (HW sets the field to '1') when the instruction decoder encounters an instruction with a non-defined condition code. This error is only generated for VU instructions." "0,1"
|
|
bitfld.long 0x0 16. "INSTR_OPC_ERROR,This interrupt cause is activated (HW sets the field to '1') when the instruction decoder encounters an instruction with a non-defined operation code (opcode)." "0,1"
|
|
bitfld.long 0x0 4. "PR_DATA_AVAILABLE,This interrupt cause is activated (HW sets the field to '1') when the pseudo random number generator has generated a data value." "0,1"
|
|
bitfld.long 0x0 3. "TR_DATA_AVAILABLE,This interrupt cause is activated (HW sets the field to '1') when the true random number generator has generated a data value of the specified bit size." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TR_INITIALIZED,This interrupt cause is activated (HW sets the field to '1') when the true random number generator is initialized." "0,1"
|
|
bitfld.long 0x0 1. "INSTR_FF_OVERFLOW,This interrupt cause is activated (HW sets the field to '1') when the instruction FIFO overflows (an attempt is made to write to a full FIFO)." "0,1"
|
|
bitfld.long 0x0 0. "INSTR_FF_LEVEL,This interrupt cause is activated (HW sets the field to '1') when the instruction FIFO event is activated." "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set register"
|
|
bitfld.long 0x4 21. "INSTR_DEV_KEY_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x4 20. "TR_RC_DETECT_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x4 19. "TR_AP_DETECT_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x4 18. "BUS_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "INSTR_CC_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x4 16. "INSTR_OPC_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x4 4. "PR_DATA_AVAILABLE,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x4 3. "TR_DATA_AVAILABLE,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TR_INITIALIZED,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x4 1. "INSTR_FF_OVERFLOW,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x4 0. "INSTR_FF_LEVEL,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x8 21. "INSTR_DEV_KEY_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x8 20. "TR_RC_DETECT_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x8 19. "TR_AP_DETECT_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x8 18. "BUS_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "INSTR_CC_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x8 16. "INSTR_OPC_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x8 4. "PR_DATA_AVAILABLE,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x8 3. "TR_DATA_AVAILABLE,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "TR_INITIALIZED,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x8 1. "INSTR_FF_OVERFLOW,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x8 0. "INSTR_FF_LEVEL,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
rgroup.long 0x10C++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked register"
|
|
bitfld.long 0x0 21. "INSTR_DEV_KEY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 20. "TR_RC_DETECT_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 19. "TR_AP_DETECT_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 18. "BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "INSTR_CC_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 16. "INSTR_OPC_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 4. "PR_DATA_AVAILABLE,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 3. "TR_DATA_AVAILABLE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TR_INITIALIZED,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 1. "INSTR_FF_OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 0. "INSTR_FF_LEVEL,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0x200++0x13
|
|
line.long 0x0 "PR_LFSR_CTL0,Pseudo random LFSR control 0"
|
|
hexmask.long 0x0 0.--31. 1. "LFSR32,State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to generate a pseudo random bit sequence. This register needs to be initialized by SW. The initialization value should be different from '0'."
|
|
line.long 0x4 "PR_LFSR_CTL1,Pseudo random LFSR control 1"
|
|
hexmask.long 0x4 0.--30. 1. "LFSR31,State of a 31-bit Linear Feedback Shift Registers (LFSR) that is used to generate a pseudo random bit sequence. See PR_LFSR_CTL0."
|
|
line.long 0x8 "PR_LFSR_CTL2,Pseudo random LFSR control 2"
|
|
hexmask.long 0x8 0.--28. 1. "LFSR29,State of a 29-bit Linear Feedback Shift Registers (LFSR) that is used to generate a pseudo random bit sequence. See PR_LFSR_CTL0."
|
|
line.long 0xC "PR_MAX_CTL,Pseudo random maximum control"
|
|
hexmask.long 0xC 0.--31. 1. "DATA32,Maximum value of to be generated random number"
|
|
line.long 0x10 "PR_CMD,Pseudo random command"
|
|
bitfld.long 0x10 0. "START,Pseudo random command. On a generated number HW sets this field to '0' and sets INTR.PR_DATA_AVAILABLE to '1." "0,1"
|
|
group.long 0x218++0x3
|
|
line.long 0x0 "PR_RESULT,Pseudo random result"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Result of a pseudo random number generation operation. The resulting value DATA is in the range [0 PR_MAX_CTL.DATA32]. The PR_DATA_AVAILABLE interrupt cause is activated when the number is generated."
|
|
group.long 0x280++0xB
|
|
line.long 0x0 "TR_CTL0,True random control 0"
|
|
bitfld.long 0x0 29. "STOP_ON_RC_DETECT,Specifies if TRNG functionality is stopped on a repetition count test detection (when HW sets INTR.TR_RC_DETECT to '1'):" "0,1"
|
|
bitfld.long 0x0 28. "STOP_ON_AP_DETECT,Specifies if TRNG functionality is stopped on an adaptive proportion test detection (when HW sets INTR.TR_AP_DETECT to '1'):" "0,1"
|
|
bitfld.long 0x0 24. "VON_NEUMANN_CORR,Specifies if the 'von Neumann corrector' is disabled or enabled:" "0,1"
|
|
hexmask.long.byte 0x0 16.--23. 1. "INIT_DELAY,Specifies an initialization delay: number of removed/dropped samples before reduced bits are generated. This field should be programmed in the range [1 255]. After starting the oscillators at least the first 2 samples should be.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RED_CLOCK_DIV,Specifies the clock divider that is used to produce reduced bits."
|
|
hexmask.long.byte 0x0 0.--7. 1. "SAMPLE_CLOCK_DIV,Specifies the clock divider that is used to sample oscillator data. This clock divider is wrt. 'clk_sys'."
|
|
line.long 0x4 "TR_CTL1,True random control 1"
|
|
bitfld.long 0x4 5. "FIRO31_EN,FW sets this field to '1' to enable the programmable Fibonacci ring oscillator with up to 31 inverters. The TR_FIRO_CTL register specifies the programmable polynomial." "0,1"
|
|
bitfld.long 0x4 4. "FIRO15_EN,FW sets this field to '1' to enable the fixed Fibonacci ring oscillator with 15 inverters." "0,1"
|
|
bitfld.long 0x4 3. "GARO31_EN,FW sets this field to '1' to enable the programmable Galois ring oscillator with up to 31 inverters. The TR_GARO_CTL register specifies the programmable polynomial." "0,1"
|
|
bitfld.long 0x4 2. "GARO15_EN,FW sets this field to '1' to enable the fixed Galois ring oscillator with 15 inverters." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RO15_EN,FW sets this field to '1' to enable the ring oscillator with 15 inverters." "0,1"
|
|
bitfld.long 0x4 0. "RO11_EN,FW sets this field to '1' to enable the ring oscillator with 11 inverters." "0,1"
|
|
line.long 0x8 "TR_CTL2,True random control 2"
|
|
hexmask.long.byte 0x8 0.--5. 1. "SIZE,Bit size of generated random number in TR_RESULT. Legal range is in [0 32]."
|
|
rgroup.long 0x28C++0x3
|
|
line.long 0x0 "TR_STATUS,True random status"
|
|
bitfld.long 0x0 0. "INITIALIZED,Reflects the state of the true random number generator:" "0,1"
|
|
group.long 0x290++0x3
|
|
line.long 0x0 "TR_CMD,True random command"
|
|
bitfld.long 0x0 0. "START,True random command. On completion of the command HW sets this field to '0' and sets INTR.TR_DATA_AVAILABLE to '1 when:" "0,1"
|
|
group.long 0x298++0x3
|
|
line.long 0x0 "TR_RESULT,True random result"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Generated true random number. HW generates the number in the least significant bit positions (TR_CTL2.SIZE) of this field. The TR_DATA_AVAILABLE interrupt cause is activated when the number is generated."
|
|
group.long 0x2A0++0x7
|
|
line.long 0x0 "TR_GARO_CTL,True random GARO control"
|
|
hexmask.long 0x0 0.--30. 1. "POLYNOMIAL31,Polynomial for programmable Galois ring oscillator. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned such that the more significant bits (bit 30 and down) contain the.."
|
|
line.long 0x4 "TR_FIRO_CTL,True random FIRO control"
|
|
hexmask.long 0x4 0.--30. 1. "POLYNOMIAL31,Polynomial for programmable Fibonacci ring oscillator. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned such that the more significant bits (bit 30 and down) contain.."
|
|
group.long 0x2C0++0x3
|
|
line.long 0x0 "TR_MON_CTL,True random monitor control"
|
|
bitfld.long 0x0 0.--1. "BITSTREAM_SEL,Selection of the bitstream:" "0,1,2,3"
|
|
group.long 0x2C8++0x3
|
|
line.long 0x0 "TR_MON_CMD,True random monitor command"
|
|
bitfld.long 0x0 1. "START_RC,Repetition count (RC) test enable:" "0,1"
|
|
bitfld.long 0x0 0. "START_AP,Adaptive proportion (AP) test enable:" "0,1"
|
|
group.long 0x2D0++0x3
|
|
line.long 0x0 "TR_MON_RC_CTL,True random monitor RC control"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CUTOFF_COUNT8,Cutoff count (legal range is [1 255]):"
|
|
rgroup.long 0x2D8++0x7
|
|
line.long 0x0 "TR_MON_RC_STATUS0,True random monitor RC status 0"
|
|
bitfld.long 0x0 0. "BIT,Current active bit value:" "0,1"
|
|
line.long 0x4 "TR_MON_RC_STATUS1,True random monitor RC status 1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "REP_COUNT,Number of repetitions of the current active bit counter:"
|
|
group.long 0x2E0++0x3
|
|
line.long 0x0 "TR_MON_AP_CTL,True random monitor AP control"
|
|
hexmask.long.word 0x0 16.--31. 1. "WINDOW_SIZE,Window size (minus 1) :"
|
|
hexmask.long.word 0x0 0.--15. 1. "CUTOFF_COUNT16,Cutoff count (legal range is [1 65535])."
|
|
rgroup.long 0x2E8++0x7
|
|
line.long 0x0 "TR_MON_AP_STATUS0,True random monitor AP status 0"
|
|
bitfld.long 0x0 0. "BIT,Current active bit value:" "0,1"
|
|
line.long 0x4 "TR_MON_AP_STATUS1,True random monitor AP status 1"
|
|
hexmask.long.word 0x4 16.--31. 1. "WINDOW_INDEX,Counter to keep track of the current index in the window (counts from '0' to TR_MON_AP_CTL.WINDOW_SIZE to '0')."
|
|
hexmask.long.word 0x4 0.--15. 1. "OCC_COUNT,Number of occurrences of the current active bit counter:"
|
|
rgroup.long 0x1004++0x3
|
|
line.long 0x0 "STATUS,Status"
|
|
bitfld.long 0x0 31. "BUSY,Reflects the state of the IP:" "0,1"
|
|
group.long 0x1040++0x3
|
|
line.long 0x0 "INSTR_FF_CTL,Instruction FIFO control"
|
|
bitfld.long 0x0 17. "BLOCK,This field specifies the behavior when an instruction is written to a full FIFO (INSTR_FIFO_WR MMIO register):" "0,1"
|
|
bitfld.long 0x0 16. "CLEAR,When '1' the instruction FIFO is cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is.." "0,1"
|
|
bitfld.long 0x0 0.--2. "EVENT_LEVEL,Event level. When the number of entries in the instruction FIFO is less than the amount of this field an event is generated:" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x1044++0x3
|
|
line.long 0x0 "INSTR_FF_STATUS,Instruction FIFO status"
|
|
bitfld.long 0x0 16. "EVENT,Instruction FIFO event." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "USED,Number of instructions in the instruction FIFO. The value of this field ranges from 0 to 8."
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "INSTR_FF_WR,Instruction FIFO write"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Instruction or instruction operand data that is written to the instruction FIFO."
|
|
rgroup.long 0x10C0++0x3
|
|
line.long 0x0 "LOAD0_FF_STATUS,Load 0 FIFO status"
|
|
bitfld.long 0x0 31. "BUSY,Reflects the state of the FIFO:" "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "USED5,Number of Bytes in the FIFO. The value of this field is in the range [0 19]."
|
|
rgroup.long 0x10D0++0x3
|
|
line.long 0x0 "LOAD1_FF_STATUS,Load 1 FIFO status"
|
|
bitfld.long 0x0 31. "BUSY,See LOAD1_FF_STATUS.BUSY." "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "USED5,See LOAD1_FF_STATUS.USED."
|
|
rgroup.long 0x10F0++0x3
|
|
line.long 0x0 "STORE_FF_STATUS,Store FIFO status"
|
|
bitfld.long 0x0 31. "BUSY,Reflects the state of the FIFO:" "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "USED5,Number of Bytes in the FIFO. The value of this field is in the range [0 16]."
|
|
group.long 0x1100++0x3
|
|
line.long 0x0 "AES_CTL,AES control"
|
|
bitfld.long 0x0 0.--1. "KEY_SIZE,AES key size:" "0: N/A,1: N/A,2: N/A,?"
|
|
group.long 0x1180++0x3
|
|
line.long 0x0 "RESULT,Result"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,BLOCK_CMP operation (DATA[0]):"
|
|
group.long 0x1400++0x3
|
|
line.long 0x0 "CRC_CTL,CRC control"
|
|
bitfld.long 0x0 8. "REM_REVERSE,Specifies whether the remainder is bit reversed (reversal is performed after XORing):" "0,1"
|
|
bitfld.long 0x0 0. "DATA_REVERSE,Specifies the bit order in which a data Byte is processed (reversal is performed after XORing):" "0,1"
|
|
group.long 0x1410++0x3
|
|
line.long 0x0 "CRC_DATA_CTL,CRC data control"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA_XOR,Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal."
|
|
group.long 0x1420++0x3
|
|
line.long 0x0 "CRC_POL_CTL,CRC polynomial control"
|
|
hexmask.long 0x0 0.--31. 1. "POLYNOMIAL,CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less.."
|
|
group.long 0x1440++0x3
|
|
line.long 0x0 "CRC_REM_CTL,CRC remainder control"
|
|
hexmask.long 0x0 0.--31. 1. "REM_XOR,Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal."
|
|
rgroup.long 0x1448++0x3
|
|
line.long 0x0 "CRC_REM_RESULT,CRC remainder result"
|
|
hexmask.long 0x0 0.--31. 1. "REM,Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE:"
|
|
group.long 0x1480++0xB
|
|
line.long 0x0 "VU_CTL0,Vector unit control 0"
|
|
bitfld.long 0x0 0. "ALWAYS_EXECUTE,Specifies if a conditional instruction is executed or not when its condition code evaluates to false/'0'." "0,1"
|
|
line.long 0x4 "VU_CTL1,Vector unit control 1"
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "ADDR24,Specifies the memory address for the vector unit operand memory region. The register-file registers provide 13-bit word offsets within this memory region. Given ADDR[31:8] VU_VTL2.MASK[14:8] and a 13-bit word offset offset[14:2] a vector operand.."
|
|
line.long 0x8 "VU_CTL2,Vector unit control 2"
|
|
hexmask.long.byte 0x8 8.--14. 1. "MASK,Specifies the size of the vector operand memory region. Legal values:"
|
|
rgroup.long 0x1490++0x3
|
|
line.long 0x0 "VU_STATUS,Vector unit status"
|
|
bitfld.long 0x0 3. "ONE,STATUS ONE field." "0,1"
|
|
bitfld.long 0x0 2. "ZERO,STATUS ZERO field." "0,1"
|
|
bitfld.long 0x0 1. "EVEN,STATUS EVEN field." "0,1"
|
|
bitfld.long 0x0 0. "CARRY,STATUS CARRY field." "0,1"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x14C0)++0x3
|
|
line.long 0x0 "VU_RF_DATA[$1],Vector unit register-file"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Vector unit register-file data. A register-file register has the following layout:"
|
|
repeat.end
|
|
group.long 0x2000++0x7
|
|
line.long 0x0 "DEV_KEY_ADDR0_CTL,Device key address 0 control"
|
|
bitfld.long 0x0 31. "VALID,Specifies if the address in the associated DEV_KEY_ADDR0 is valid:" "0,1"
|
|
line.long 0x4 "DEV_KEY_ADDR0,Device key address 0"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR32,Specifies the memory address of the device key in memory. A LOAD_DEV_KEY instruction uses this address to load a device key from memory into the IP register buffer blocks 4 and 5."
|
|
group.long 0x2020++0x7
|
|
line.long 0x0 "DEV_KEY_ADDR1_CTL,Device key address 1 control"
|
|
bitfld.long 0x0 31. "VALID,See DEV_KEY_ADDR0_CTL." "0,1"
|
|
line.long 0x4 "DEV_KEY_ADDR1,Device key address 1 control"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR32,See DEV_KEY_ADDR0."
|
|
rgroup.long 0x2080++0x3
|
|
line.long 0x0 "DEV_KEY_STATUS,Device key status"
|
|
bitfld.long 0x0 0. "LOADED,Specifies if a device key is present in the IP register buffer blocks 4 and 5." "0,1"
|
|
group.long 0x2100++0x3
|
|
line.long 0x0 "DEV_KEY_CTL0,Device key control 0"
|
|
bitfld.long 0x0 0. "ALLOWED,Specifies if a LOAD_DEV_KEY instruction is allowed to use the device key in memory:" "0,1"
|
|
group.long 0x2120++0x3
|
|
line.long 0x0 "DEV_KEY_CTL1,Device key control 1"
|
|
bitfld.long 0x0 0. "ALLOWED,See DEV_KEY_CTL0." "0,1"
|
|
tree.end
|
|
tree "CXPI (Clock Extension Peripheral Interface)"
|
|
base ad:0x40510000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "ERROR_CTL,Error control"
|
|
bitfld.long 0x0 31. "ENABLED,Error injection enable:" "0,1"
|
|
bitfld.long 0x0 25. "TX_DATA_STOP_ERROR,The data field STOP bits are inverted to '0'." "0,1"
|
|
bitfld.long 0x0 20. "TX_DATA_LENGTH_ERROR,The transmitter continues to send logical '0' (during IFS) after CRC field is transmitted." "0,1"
|
|
bitfld.long 0x0 19. "TX_PID_PARITY_ERROR,In cxpi mode the PID parity bit P[1] is inverted from !(ID[5] ^ ID[4] ^ ID[3] ^ ID[1]) to (ID[5] ^ ID[4] ^ ID[3] ^ ID[1])." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TX_CRC_ERROR,The crc field is inverted." "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "CH_IDX,Specifies the channel index of the channel to which HW injected channel transmitter errors applies."
|
|
line.long 0x4 "TEST_CTL,Test control"
|
|
bitfld.long 0x4 31. "ENABLED,Test enable:" "0: Functional mode,1: Test mode"
|
|
bitfld.long 0x4 16. "MODE,Test mode:" "0: Partial disconnect,1: Full disconnect"
|
|
hexmask.long.byte 0x4 0.--4. 1. "CH_IDX,Specifies the channel index of the channel to which test applies. The channel IO signals of channel indices CH_IDX and CH_NR-1 are connected as specified by MODE. CH_IDX should be in the range [0 CH_NR-2] as channel index CH_NR-1 is always.."
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x40518000 ad:0x40518100 ad:0x40518200 ad:0x40518300)
|
|
tree "CH[$1]"
|
|
base $2
|
|
group.long ($2)++0xB
|
|
line.long 0x0 "CTL0,Control 0"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 30. "MASTER,CXPI master mode." "0: Slave mode,1: Master mode"
|
|
newline
|
|
bitfld.long 0x0 27. "BIT_ERROR_IGNORE,Specifies behavior on a detected bit error during header or response transmission:" "0: Message transfer is aborted,1: Message transfer is NOT aborted"
|
|
newline
|
|
hexmask.long.byte 0x0 21.--24. 1. "IBS,Inter Byte Space in bit periods:"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "IFS,Inter Frame Space in bit periods:"
|
|
newline
|
|
bitfld.long 0x0 8. "FILTER_EN,RX filter enable (for 'cxpi_rx_in')" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RXPIDZERO_CHECK_EN,Receive PID Zero Check Enable." "0: No action if received PID[6:0] = 0 and PID[7]=1'b1,1: If received PID[6:0] = 0 and PID[7]=1'b1"
|
|
newline
|
|
bitfld.long 0x0 4. "AUTO_EN,CXPI transceiver auto enable:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MODE,Mode of operation:" "0: NRZ mode,1: PWM mode"
|
|
line.long 0x4 "CTL1,Control 1"
|
|
hexmask.long.word 0x4 22.--30. 1. "T_OFFSET,The value of offset that is used for sampling the 'rx'."
|
|
newline
|
|
hexmask.long.word 0x4 12.--20. 1. "T_LOW0,Low count for logic 0. This is valid only for PWM mode."
|
|
newline
|
|
hexmask.long.word 0x4 0.--8. 1. "T_LOW1,Low count for logic 1. This is valid only for PWM mode."
|
|
line.long 0x8 "CTL2,Control 2"
|
|
bitfld.long 0x8 30.--31. "TIMEOUT_SEL,Timeout Select." "0: Timeout check is disabled.,1: Timeout check is enabled and HW will refer to..,2: Timeout check is enabled to check header-header..,?"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--19. 1. "TIMEOUT_LENGTH,Timeout Length (in Tbits). Specifies the number of Tbits to exceed timeout between frame bytes within a message frame. CXPI spec states that the maximum allowed inter byte space (IBS) is 9Tbits."
|
|
newline
|
|
hexmask.long.byte 0x8 8.--13. 1. "T_WAKEUP_LENGTH,Specifies the wake up pulse low period in Tbits that is transmitted during Standby mode."
|
|
newline
|
|
bitfld.long 0x8 0.--1. "RETRY,Number of retries after arbitration lost." "0,1,2,3"
|
|
rgroup.long ($2+0xC)++0x3
|
|
line.long 0x0 "STATUS,Status"
|
|
bitfld.long 0x0 30. "TX_FRAME_ERROR,Copy of INTR.TX_FRAME_ERROR." "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RX_FRAME_ERROR,Copy of INTR.RX_FRAME_ERROR." "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "TX_UNDERFLOW_ERROR,Copy of INTR.TX_UNDERFLOW_ERROR." "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RX_UNDERFLOW_ERROR,Copy of INTR.RX_UNDERFLOW_ERROR." "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TX_OVERFLOW_ERROR,Copy of INTR.TX_OVERFLOW_ERROR." "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RX_OVERFLOW_ERROR,Copy of INTR.RX_OVERFLOW_ERROR." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TX_DATA_LENGTH_ERROR,Copy of INTR.TX_DATA_LENGTH_ERROR." "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "RX_DATA_LENGTH_ERROR,Copy of INTR.RX_DATA_LENGTH_ERROR." "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "RX_HEADER_PARITY_ERROR,Copy of INTR.RX_HEADER_PARITY_ERROR." "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "RX_CRC_ERROR,Copy of INTR.RX_CRC_ERROR." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "TX_BIT_ERROR,Copy of INTR.TX_BIT_ERROR." "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TX_HEADER_ARB_LOST,Copy of INTR.TX_HEADER_ARB_LOST" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TIMEOUT,Copy of INTR.TIMEOUT" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RX_DONE,Receiver done:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "TX_DONE,Transmitter done:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RX_BUSY,Receiver busy." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TX_BUSY,Transmitter busy." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "HEADER_RESPONSE,Frame header/response identifier (only valid when TX_BUSY or RX_BUSY is '1')" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "RETRIES_COUNT,Retries count." "0,1,2,3"
|
|
group.long ($2+0x10)++0x3
|
|
line.long 0x0 "CMD,Command"
|
|
bitfld.long 0x0 9. "RX_RESPONSE,SW sets this field to '1' to receive a response. HW sets this field to '0' on successful completion of ANY of the legal command sequences (NOT set to '0' when an error is detected)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RX_HEADER,SW sets this field to '1' to receive a header. HW sets this field to '0' on successful completion of the ANY of the legal command sequences." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IFS_WAIT,SW sets this field to '1' to wait for IFS. HW clears this field to '0' after it detects logical '1' based on IFS." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TX_WAKE_PULSE,SW sets this field to '1' to direct HW to send wake up pulse. HW will transmit wake up pulse in Standby state only. HW will ignore this field when it's not in Standby state." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "WAKE_TO_STANDBY,SW sets this field to '1' to direct HW to wake up from Sleep mode to Standby mode. SW clears this field to '0' from '1' when it wants to direct HW from Standby to Normal mode. HW clears this field to '0' when it is in Normal mode or back.." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "SLEEP,SW sets this field to '1' to direct HW to sleep mode. HW transits from Normal to Sleep upon SLEEP=1 and both TX and RX is idle. HW sets this field to '0' when it is in Sleep mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TX_RESPONSE,SW sets this field to '1' to transmit a response. HW sets this field to '0' on successful completion of ANY of the legal command sequences (also set to '0' when an error is detected)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TX_HEADER,SW sets this field to '1' to transmit a header. HW sets this field to '0' on successful completion of ANY of the following legal command sequences (also set to '0' when an error (such as bit error if bit_ignore=0 arbitration loss tx data.." "0,1"
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "TX_RX_STATUS,TX/RX status"
|
|
bitfld.long 0x0 26. "EN_OUT,CXPI transceiver enable ('en_out' 'cxpi_en_out'). This field controls the enable (or low active sleep enable) of the external transceiver:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 24. "TX_OUT,CXPI transmitter output ('tx_out' 'cxpi_tx_out')." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 17. "RX_IN,CXPI receiver input ('rx_in' 'cxpi_rx_in' in functional mode)." "0,1"
|
|
newline
|
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rbitfld.long 0x0 16. "TX_IN,CXPI transmitter input ('tx_in' 'cxpi_tx_in' in functional mode). TX_IN and RX_IN can be used to determine a wakeup source. Note that wakeup source detection relies on the external transceiver functionality." "0,1"
|
|
group.long ($2+0x50)++0x3
|
|
line.long 0x0 "TXPID_FI,TXPID and Frame Information"
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLCEXT,Data Length Count Extension."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "FI,Frame Information."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "PID,Header protected identifier (PID)."
|
|
rgroup.long ($2+0x54)++0x7
|
|
line.long 0x0 "RXPID_FI,RXPID and Frame Information"
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLCEXT,Data Length Count Extension."
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "FI,Frame Information."
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "PID,Header protected identifier (PID)."
|
|
line.long 0x4 "CRC,CRC"
|
|
hexmask.long.byte 0x4 24.--31. 1. "TXCRC2,CRC second byte of CRC16. This is valid only for Long frames."
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "TXCRC1,CRC first byte for both CRC8 and CRC16. This is valid for both Normal frame and Long frame."
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "RXCRC2,CRC second byte of CRC16. This is valid only for Long frames."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXCRC1,CRC first byte for both CRC8 and CRC16. This is valid for both Normal frame and Long frame."
|
|
group.long ($2+0x80)++0x3
|
|
line.long 0x0 "TX_FIFO_CTL,TX FIFO control"
|
|
bitfld.long 0x0 17. "FREEZE,Freeze functionality:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "CLEAR,This is a synchronous clear signal to the TX FIFO. When '1' the TX FIFO content are cleared. If a quick clear is required the field should be set to '1' and followed by '0'. If a clear is required for an extended time the field should be set to.." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "TRIGGER_LEVEL,Trigger level. When the TX FIFO has less entries than the number of this field a transmitter trigger event is generated:"
|
|
rgroup.long ($2+0x84)++0x3
|
|
line.long 0x0 "TX_FIFO_STATUS,TX FIFO status"
|
|
hexmask.long.byte 0x0 16.--20. 1. "AVAIL,TX FIFO Avail"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "USED,Number of used/occupied entries in the TX FIFO. The field value is in the range [0 16]. When '0' the TX FIFO is empty. When '16' the TX FIFO is full."
|
|
wgroup.long ($2+0x88)++0x3
|
|
line.long 0x0 "TX_FIFO_WR,TX FIFO write"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,Transmit Data field."
|
|
group.long ($2+0xA0)++0x3
|
|
line.long 0x0 "RX_FIFO_CTL,RX FIFO control"
|
|
bitfld.long 0x0 17. "FREEZE,Freeze functionality:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "CLEAR,When '1' the RX FIFO content are popped. If a quick clear is required the field should be set to '1' and followed by '0'. If a clear is required for an extended time the field should be set to 1 during the complete time." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "TRIGGER_LEVEL,Trigger level. When RX FIFO has more entries than the number of this field a receiver trigger event is generated."
|
|
rgroup.long ($2+0xA4)++0xB
|
|
line.long 0x0 "RX_FIFO_STATUS,RX FIFO status"
|
|
hexmask.long.byte 0x0 16.--20. 1. "AVAIL,RX FIFO avail"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "USED,Number of used/occupied entries in the RX FIFO. The field value is in the range [0 16]. When '0' the RX FIFO is empty. When '16' the RX FIFO is full."
|
|
line.long 0x4 "RX_FIFO_RD,RX FIFO read"
|
|
hexmask.long.byte 0x4 0.--7. 1. "DATA,Received Data field. Software uses this data field."
|
|
line.long 0x8 "RX_FIFO_RD_SILENT,RX FIFO silent read"
|
|
hexmask.long.byte 0x8 0.--7. 1. "DATA,Data read from the RX FIFO. Reading data from this field would not pop the data from RX FIFO."
|
|
group.long ($2+0xC0)++0xB
|
|
line.long 0x0 "INTR,Interrupt"
|
|
bitfld.long 0x0 30. "TX_FRAME_ERROR,HW sets this field to '1' when the stop bit of a byte frame is incorrect." "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RX_FRAME_ERROR,HW sets this field to '1' when the stop bit of a byte frame is incorrect." "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "TX_UNDERFLOW_ERROR,HW sets this field to '1' when TX FIFO is empty and HW reads from it." "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RX_UNDERFLOW_ERROR,HW sets this field to '1' when RX FIFO is empty and SW reads from it." "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TX_OVERFLOW_ERROR,HW sets this field to '1' when the TX data is overwritten by SW before the HW reads from it to transmit to CXPI bus." "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RX_OVERFLOW_ERROR,HW sets this field to '1' when the RX data is overwritten by HW before the SW reads from it. In CXPI spec this error is denoted as overrun error." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TX_DATA_LENGTH_ERROR,HW sets this field to '1 when the transmit message frame's data fields are more than the value specified in DLC (for normal frame) or DLCEXT (for long frame) i.e. after transmitting CRC(s) byte HW is receiving logical '0' during.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "RX_DATA_LENGTH_ERROR,HW sets this field to '1 when the received message frame's data fields are more than the value specified in DLC (for normal frame) or DLCEXT (for long frame) i.e. after receiving CRC byte(s) HW is receiving logical '0' during EOF." "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "RX_HEADER_PARITY_ERROR,HW sets this field to '1' when the received PID field or PType field has a parity error." "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "RX_CRC_ERROR,HW sets this field to '1' when received CRC is not matching with the compute CRC from header and response." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "TX_BIT_ERROR,HW sets this field to '1' when a transmitted 'cxpi_tx_out' value does NOT match a received 'cxpi_rx_in' value." "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TX_HEADER_ARB_LOST,HW sets this field to '1' when it detects arbitration lost after the number of retries has exceed the maximum allowed retries." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TIMEOUT,HW sets this field to '1' when the transmitted/received bytes space within a message frame is > TIMEOUT_LENGTH." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TXRX_COMPLETE,HW sets this field to '1' when message frame ends after EOF is completed and TX/RX_DATA_LENGTH_ERROR=0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RX_HEADER_PID_DONE,HW sets this field to '1' when RX header (PID/PTYPE field) is received." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RX_FIFO_TRIGGER,HW sets this field to '1' when RX trigger is generated (#used RX FIFO > TRIGGER_LEVEL)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "RX_WAKEUP_DETECT,HW sets this field to '1' when RX fall is detected in Sleep mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RX_RESPONSE_DONE,HW sets this field to '1' when a frame response (frame information fields data fields and crc field) is received (the CMD.RX_RESPONSE is completed)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RX_HEADER_DONE,HW sets this field to '1' when a frame header (PID field or PType field) is received (the CMD.RX_HEADER is completed). Specifically:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TX_FIFO_TRIGGER,HW sets this field to '1' when TX trigger is generated (#used TX FIFO < TRIGGER_LEVEL)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TX_WAKEUP_DONE,HW sets this field to '1' when a wakeup signal is transmitted (per CTL2.T_WAKEUP_LENGTH). This interrupt cause is activated on a transition from dominant/'0' state to recessive/'1' state; i.e. at the end of the wakeup signal." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TX_RESPONSE_DONE,HW sets this field to '1' when a frame response (frame information fields data fields and crc field) is transmitted (the CMD.TX_RESPONSE is completed)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TX_HEADER_DONE,HW sets this field to '1' when a frame header (PID field or PType field) is transmitted (the CMD.TX_HEADER is completed). Specifically:" "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set"
|
|
bitfld.long 0x4 30. "TX_FRAME_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RX_FRAME_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "TX_UNDERFLOW_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "RX_UNDERFLOW_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "TX_OVERFLOW_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "RX_OVERFLOW_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "TX_DATA_LENGTH_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "RX_DATA_LENGTH_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "RX_HEADER_PARITY_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "RX_CRC_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "TX_BIT_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "TX_HEADER_ARB_LOST,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "TIMEOUT,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "TXRX_COMPLETE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "RX_HEADER_PID_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "RX_FIFO_TRIGGER,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "RX_WAKEUP_DETECT,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "RX_RESPONSE_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "RX_HEADER_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "TX_FIFO_TRIGGER,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TX_WAKEUP_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TX_RESPONSE_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TX_HEADER_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x8 30. "TX_FRAME_ERROR,Mask for corresponding field in INTR register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "RX_FRAME_ERROR,Mask for corresponding field in INTR register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 28. "TX_UNDERFLOW_ERROR,Mask for corresponding field in INTR register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "RX_UNDERFLOW_ERROR,Mask for corresponding field in INTR register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 26. "TX_OVERFLOW_ERROR,Mask for corresponding field in INTR register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "RX_OVERFLOW_ERROR,Mask for corresponding field in INTR register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 24. "TX_DATA_LENGTH_ERROR,Mask for corresponding field in INTR register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "RX_DATA_LENGTH_ERROR,Mask for corresponding field in INTR register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 22. "RX_HEADER_PARITY_ERROR,Mask for corresponding field in INTR register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "RX_CRC_ERROR,Mask for corresponding field in INTR register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "TX_BIT_ERROR,Mask for corresponding field in INTR register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "TX_HEADER_ARB_LOST,Mask for corresponding field in INTR register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 18. "TIMEOUT,Mask for corresponding field in INTR register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "TXRX_COMPLETE,Mask for corresponding field in INTR register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "RX_HEADER_PID_DONE,Mask for corresponding field in INTR register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "RX_FIFO_TRIGGER,Mask for corresponding field in INTR register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "RX_WAKEUP_DETECT,Mask for corresponding field in INTR register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "RX_RESPONSE_DONE,Mask for corresponding field in INTR register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "RX_HEADER_DONE,Mask for corresponding field in INTR register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "TX_FIFO_TRIGGER,Mask for corresponding field in INTR register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "TX_WAKEUP_DONE,Mask for corresponding field in INTR register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "TX_RESPONSE_DONE,Mask for corresponding field in INTR register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TX_HEADER_DONE,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0xCC)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 30. "TX_FRAME_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RX_FRAME_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "TX_UNDERFLOW_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RX_UNDERFLOW_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TX_OVERFLOW_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RX_OVERFLOW_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TX_DATA_LENGTH_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "RX_DATA_LENGTH_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "RX_HEADER_PARITY_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "RX_CRC_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "TX_BIT_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TX_HEADER_ARB_LOST,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TIMEOUT,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TXRX_COMPLETE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RX_HEADER_PID_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RX_FIFO_TRIGGER,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "RX_WAKEUP_DETECT,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RX_RESPONSE_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RX_HEADER_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TX_FIFO_TRIGGER,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TX_WAKEUP_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TX_RESPONSE_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TX_HEADER_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "DMAC"
|
|
base ad:0x402A0000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "ENABLED,IP enable:" "0: N/A,1: N/A"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "ACTIVE,Active channels"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ACTIVE,Specifies active channels; i.e. enabled channels whose trigger got activated."
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x402A1000 ad:0x402A1100 ad:0x402A1200 ad:0x402A1300)
|
|
tree "CH[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
rgroup.long ($2+0x10)++0xB
|
|
line.long 0x0 "IDX,Channel current indices"
|
|
hexmask.long.word 0x0 16.--31. 1. "Y,Specifies the Y loop index with Y_COUNT taken from the current descriptor."
|
|
hexmask.long.word 0x0 0.--15. 1. "X,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "SRC,Channel current source address"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,Current address of source location."
|
|
line.long 0x8 "DST,Channel current destination address"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,Current address of destination location."
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "CURR,Channel current descriptor pointer"
|
|
hexmask.long 0x0 2.--31. 1. "PTR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
group.long ($2+0x28)++0x3
|
|
line.long 0x0 "TR_CMD,Channle software trigger"
|
|
bitfld.long 0x0 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
rgroup.long ($2+0x40)++0x3
|
|
line.long 0x0 "DESCR_STATUS,Channel descriptor status"
|
|
bitfld.long 0x0 31. "VALID,Indicates whether the descriptor information present in DESCR_CTL DESCR_SRC DESCR_DST DESCR_X_SIZE DESCR_X_INCR DESCR_Y_SIZE DESCR_Y_INCR DESCR_NEXT status registers is valid or not." "0,1"
|
|
rgroup.long ($2+0x60)++0x1F
|
|
line.long 0x0 "DESCR_CTL,Channel descriptor control"
|
|
bitfld.long 0x0 28.--30. "DESCR_TYPE,N/A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 27. "DST_TRANSFER_SIZE,N/A" "0,1"
|
|
bitfld.long 0x0 26. "SRC_TRANSFER_SIZE,N/A" "0,1"
|
|
bitfld.long 0x0 24. "CH_DISABLE,N/A" "0,1"
|
|
bitfld.long 0x0 16.--17. "DATA_SIZE,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8. "DATA_PREFETCH,N/A" "0,1"
|
|
bitfld.long 0x0 6.--7. "TR_IN_TYPE,N/A" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "TR_OUT_TYPE,N/A" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "INTR_TYPE,N/A" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "WAIT_FOR_DEACT,N/A" "0,1,2,3"
|
|
line.long 0x4 "DESCR_SRC,Channel descriptor source"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,N/A"
|
|
line.long 0x8 "DESCR_DST,Channel descriptor destination"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,N/A"
|
|
line.long 0xC "DESCR_X_SIZE,Channel descriptor X size"
|
|
hexmask.long.word 0xC 0.--15. 1. "X_COUNT,N/A"
|
|
line.long 0x10 "DESCR_X_INCR,Channel descriptor X increment"
|
|
hexmask.long.word 0x10 16.--31. 1. "DST_X,N/A"
|
|
hexmask.long.word 0x10 0.--15. 1. "SRC_X,N/A"
|
|
line.long 0x14 "DESCR_Y_SIZE,Channel descriptor Y size"
|
|
hexmask.long.word 0x14 0.--15. 1. "Y_COUNT,N/A"
|
|
line.long 0x18 "DESCR_Y_INCR,Channel descriptor Y increment"
|
|
hexmask.long.word 0x18 16.--31. 1. "DST_Y,N/A"
|
|
hexmask.long.word 0x18 0.--15. 1. "SRC_Y,N/A"
|
|
line.long 0x1C "DESCR_NEXT,Channel descriptor next pointer"
|
|
hexmask.long 0x1C 2.--31. 1. "PTR,N/A"
|
|
group.long ($2+0x80)++0xB
|
|
line.long 0x0 "INTR,Interrupt"
|
|
bitfld.long 0x0 7. "DESCR_BUS_ERROR,Activated (set to '1') on a bus error for a load of the descriptor." "0,1"
|
|
bitfld.long 0x0 6. "ACTIVE_CH_DISABLED,Activated (set to '1') if the channel is disabled by SW (accidentally/incorrectly) when the data transfer engine is busy." "0,1"
|
|
bitfld.long 0x0 5. "CURR_PTR_NULL,Activated (set to '1') when the channel is enabled (CH_CTL.ENABLED is '1') and CH_CURR_PTR is '0'." "0,1"
|
|
bitfld.long 0x0 4. "DST_MISAL,Activated (set to '1') on a misalignment of the destination address." "0,1"
|
|
bitfld.long 0x0 3. "SRC_MISAL,Activated (set to '1') on a misalignment of the source address." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DST_BUS_ERROR,Activated (set to '1') on a bus error for a store to the destination." "0,1"
|
|
bitfld.long 0x0 1. "SRC_BUS_ERROR,Activated (set to '1') on a bus error for a load from the source." "0,1"
|
|
bitfld.long 0x0 0. "COMPLETION,Activated (set to '1') on completion of data transfer(s) as specified by the descriptor's CH_DESCR_CTL.INTR_TYPE." "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set"
|
|
bitfld.long 0x4 7. "DESCR_BUS_ERROR,N/A" "0,1"
|
|
bitfld.long 0x4 6. "ACTIVE_CH_DISABLED,N/A" "0,1"
|
|
bitfld.long 0x4 5. "CURR_PTR_NULL,N/A" "0,1"
|
|
bitfld.long 0x4 4. "DST_MISAL,N/A" "0,1"
|
|
bitfld.long 0x4 3. "SRC_MISAL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DST_BUS_ERROR,N/A" "0,1"
|
|
bitfld.long 0x4 1. "SRC_BUS_ERROR,N/A" "0,1"
|
|
bitfld.long 0x4 0. "COMPLETION,Write this field with '1' to set corresponding INTR field to '1' (a write of '0' has no effect)." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x8 7. "DESCR_BUS_ERROR,N/A" "0,1"
|
|
bitfld.long 0x8 6. "ACTIVE_CH_DISABLED,N/A" "0,1"
|
|
bitfld.long 0x8 5. "CURR_PTR_NULL,N/A" "0,1"
|
|
bitfld.long 0x8 4. "DST_MISAL,N/A" "0,1"
|
|
bitfld.long 0x8 3. "SRC_MISAL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "DST_BUS_ERROR,N/A" "0,1"
|
|
bitfld.long 0x8 1. "SRC_BUS_ERROR,N/A" "0,1"
|
|
bitfld.long 0x8 0. "COMPLETION,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x8C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 7. "DESCR_BUS_ERROR,N/A" "0,1"
|
|
bitfld.long 0x0 6. "ACTIVE_CH_DISABLED,N/A" "0,1"
|
|
bitfld.long 0x0 5. "CURR_PTR_NULL,N/A" "0,1"
|
|
bitfld.long 0x0 4. "DST_MISAL,N/A" "0,1"
|
|
bitfld.long 0x0 3. "SRC_MISAL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DST_BUS_ERROR,N/A" "0,1"
|
|
bitfld.long 0x0 1. "SRC_BUS_ERROR,N/A" "0,1"
|
|
bitfld.long 0x0 0. "COMPLETION,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "DW (Datawire Controller)"
|
|
base ad:0x0
|
|
tree "DW0"
|
|
base ad:0x40280000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "ENABLED,IP enable:" "0,1"
|
|
bitfld.long 0x0 1. "ECC_INJ_EN,Enable parity injection for SRAM." "0,1"
|
|
bitfld.long 0x0 0. "ECC_EN,Enable ECC checking:" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Status"
|
|
bitfld.long 0x0 31. "ACTIVE,Active channel present:" "0,1"
|
|
bitfld.long 0x0 28.--30. "STATE,State of the DW controller." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 16.--24. 1. "CH_IDX,Active channel index."
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Active channel preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Active channel priority." "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Active channel protection context."
|
|
newline
|
|
bitfld.long 0x0 2. "B,Active channel non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Active channel secure/non-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,Active channel user/privileged access control:" "0,1"
|
|
rgroup.long 0x20++0xB
|
|
line.long 0x0 "ACT_DESCR_CTL,Active descriptor control"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Copy of DESCR_CTL of the currently active descriptor."
|
|
line.long 0x4 "ACT_DESCR_SRC,Active descriptor source"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Copy of DESCR_SRC of the currently active descriptor."
|
|
line.long 0x8 "ACT_DESCR_DST,Active descriptor destination"
|
|
hexmask.long 0x8 0.--31. 1. "DATA,Copy of DESCR_DST of the currently active descriptor."
|
|
rgroup.long 0x30++0xB
|
|
line.long 0x0 "ACT_DESCR_X_CTL,Active descriptor X loop control"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Copy of DESCR_X_CTL of the currently active descriptor."
|
|
line.long 0x4 "ACT_DESCR_Y_CTL,Active descriptor Y loop control"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Copy of DESCR_Y_CTL of the currently active descriptor."
|
|
line.long 0x8 "ACT_DESCR_NEXT_PTR,Active descriptor next pointer"
|
|
hexmask.long 0x8 2.--31. 1. "ADDR,Copy of DESCR_NEXT_PTR of the currently active descriptor."
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x0 "ACT_SRC,Active source"
|
|
hexmask.long 0x0 0.--31. 1. "SRC_ADDR,Current address of source location."
|
|
line.long 0x4 "ACT_DST,Active destination"
|
|
hexmask.long 0x4 0.--31. 1. "DST_ADDR,Current address of destination location."
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x0 25.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR."
|
|
hexmask.long.word 0x0 0.--9. 1. "WORD_ADDR,Specifies the word address where an error will be injected."
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "CRC_CTL,CRC control"
|
|
bitfld.long 0x0 8. "REM_REVERSE,Specifies whether the remainder is bit reversed (reversal is performed after XORing):" "0,1"
|
|
bitfld.long 0x0 0. "DATA_REVERSE,Specifies the bit order in which a data Byte is processed (reversal is performed after XORing):" "0,1"
|
|
group.long 0x110++0x3
|
|
line.long 0x0 "CRC_DATA_CTL,CRC data control"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA_XOR,Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal."
|
|
group.long 0x120++0x3
|
|
line.long 0x0 "CRC_POL_CTL,CRC polynomial control"
|
|
hexmask.long 0x0 0.--31. 1. "POLYNOMIAL,CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less.."
|
|
group.long 0x130++0x3
|
|
line.long 0x0 "CRC_LFSR_CTL,CRC LFSR control"
|
|
hexmask.long 0x0 0.--31. 1. "LFSR32,State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to implement CRC. This register needs to be initialized by SW to provide the CRC seed value."
|
|
group.long 0x140++0x3
|
|
line.long 0x0 "CRC_REM_CTL,CRC remainder control"
|
|
hexmask.long 0x0 0.--31. 1. "REM_XOR,Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal."
|
|
rgroup.long 0x148++0x3
|
|
line.long 0x0 "CRC_REM_RESULT,CRC remainder result"
|
|
hexmask.long 0x0 0.--31. 1. "REM,Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE:"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40288000 ad:0x40288040 ad:0x40288080 ad:0x402880C0 ad:0x40288100 ad:0x40288140 ad:0x40288180 ad:0x402881C0 ad:0x40288200 ad:0x40288240 ad:0x40288280 ad:0x402882C0 ad:0x40288300 ad:0x40288340 ad:0x40288380 ad:0x402883C0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x40288400 ad:0x40288440 ad:0x40288480 ad:0x402884C0 ad:0x40288500 ad:0x40288540 ad:0x40288580 ad:0x402885C0 ad:0x40288600 ad:0x40288640 ad:0x40288680 ad:0x402886C0 ad:0x40288700 ad:0x40288740 ad:0x40288780 ad:0x402887C0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F)(list ad:0x40288800 ad:0x40288840 ad:0x40288880 ad:0x402888C0 ad:0x40288900 ad:0x40288940 ad:0x40288980 ad:0x402889C0 ad:0x40288A00 ad:0x40288A40 ad:0x40288A80 ad:0x40288AC0 ad:0x40288B00 ad:0x40288B40 ad:0x40288B80 ad:0x40288BC0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F)(list ad:0x40288C00 ad:0x40288C40 ad:0x40288C80 ad:0x40288CC0 ad:0x40288D00 ad:0x40288D40 ad:0x40288D80 ad:0x40288DC0 ad:0x40288E00 ad:0x40288E40 ad:0x40288E80 ad:0x40288EC0 ad:0x40288F00 ad:0x40288F40 ad:0x40288F80 ad:0x40288FC0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F)(list ad:0x40289000 ad:0x40289040 ad:0x40289080 ad:0x402890C0 ad:0x40289100 ad:0x40289140 ad:0x40289180 ad:0x402891C0 ad:0x40289200 ad:0x40289240 ad:0x40289280 ad:0x402892C0 ad:0x40289300 ad:0x40289340 ad:0x40289380 ad:0x402893C0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 12. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B)(list ad:0x40289400 ad:0x40289440 ad:0x40289480 ad:0x402894C0 ad:0x40289500 ad:0x40289540 ad:0x40289580 ad:0x402895C0 ad:0x40289600 ad:0x40289640 ad:0x40289680 ad:0x402896C0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "DW1"
|
|
base ad:0x40290000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "ENABLED,IP enable:" "0,1"
|
|
bitfld.long 0x0 1. "ECC_INJ_EN,Enable parity injection for SRAM." "0,1"
|
|
bitfld.long 0x0 0. "ECC_EN,Enable ECC checking:" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Status"
|
|
bitfld.long 0x0 31. "ACTIVE,Active channel present:" "0,1"
|
|
bitfld.long 0x0 28.--30. "STATE,State of the DW controller." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 16.--24. 1. "CH_IDX,Active channel index."
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Active channel preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Active channel priority." "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Active channel protection context."
|
|
newline
|
|
bitfld.long 0x0 2. "B,Active channel non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Active channel secure/non-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,Active channel user/privileged access control:" "0,1"
|
|
rgroup.long 0x20++0xB
|
|
line.long 0x0 "ACT_DESCR_CTL,Active descriptor control"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Copy of DESCR_CTL of the currently active descriptor."
|
|
line.long 0x4 "ACT_DESCR_SRC,Active descriptor source"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Copy of DESCR_SRC of the currently active descriptor."
|
|
line.long 0x8 "ACT_DESCR_DST,Active descriptor destination"
|
|
hexmask.long 0x8 0.--31. 1. "DATA,Copy of DESCR_DST of the currently active descriptor."
|
|
rgroup.long 0x30++0xB
|
|
line.long 0x0 "ACT_DESCR_X_CTL,Active descriptor X loop control"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Copy of DESCR_X_CTL of the currently active descriptor."
|
|
line.long 0x4 "ACT_DESCR_Y_CTL,Active descriptor Y loop control"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Copy of DESCR_Y_CTL of the currently active descriptor."
|
|
line.long 0x8 "ACT_DESCR_NEXT_PTR,Active descriptor next pointer"
|
|
hexmask.long 0x8 2.--31. 1. "ADDR,Copy of DESCR_NEXT_PTR of the currently active descriptor."
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x0 "ACT_SRC,Active source"
|
|
hexmask.long 0x0 0.--31. 1. "SRC_ADDR,Current address of source location."
|
|
line.long 0x4 "ACT_DST,Active destination"
|
|
hexmask.long 0x4 0.--31. 1. "DST_ADDR,Current address of destination location."
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x0 25.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR."
|
|
hexmask.long.word 0x0 0.--9. 1. "WORD_ADDR,Specifies the word address where an error will be injected."
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "CRC_CTL,CRC control"
|
|
bitfld.long 0x0 8. "REM_REVERSE,Specifies whether the remainder is bit reversed (reversal is performed after XORing):" "0,1"
|
|
bitfld.long 0x0 0. "DATA_REVERSE,Specifies the bit order in which a data Byte is processed (reversal is performed after XORing):" "0,1"
|
|
group.long 0x110++0x3
|
|
line.long 0x0 "CRC_DATA_CTL,CRC data control"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA_XOR,Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal."
|
|
group.long 0x120++0x3
|
|
line.long 0x0 "CRC_POL_CTL,CRC polynomial control"
|
|
hexmask.long 0x0 0.--31. 1. "POLYNOMIAL,CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less.."
|
|
group.long 0x130++0x3
|
|
line.long 0x0 "CRC_LFSR_CTL,CRC LFSR control"
|
|
hexmask.long 0x0 0.--31. 1. "LFSR32,State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to implement CRC. This register needs to be initialized by SW to provide the CRC seed value."
|
|
group.long 0x140++0x3
|
|
line.long 0x0 "CRC_REM_CTL,CRC remainder control"
|
|
hexmask.long 0x0 0.--31. 1. "REM_XOR,Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal."
|
|
rgroup.long 0x148++0x3
|
|
line.long 0x0 "CRC_REM_RESULT,CRC remainder result"
|
|
hexmask.long 0x0 0.--31. 1. "REM,Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE:"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40298000 ad:0x40298040 ad:0x40298080 ad:0x402980C0 ad:0x40298100 ad:0x40298140 ad:0x40298180 ad:0x402981C0 ad:0x40298200 ad:0x40298240 ad:0x40298280 ad:0x402982C0 ad:0x40298300 ad:0x40298340 ad:0x40298380 ad:0x402983C0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x40298400 ad:0x40298440 ad:0x40298480 ad:0x402984C0 ad:0x40298500 ad:0x40298540 ad:0x40298580 ad:0x402985C0 ad:0x40298600 ad:0x40298640 ad:0x40298680 ad:0x402986C0 ad:0x40298700 ad:0x40298740 ad:0x40298780 ad:0x402987C0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F)(list ad:0x40298800 ad:0x40298840 ad:0x40298880 ad:0x402988C0 ad:0x40298900 ad:0x40298940 ad:0x40298980 ad:0x402989C0 ad:0x40298A00 ad:0x40298A40 ad:0x40298A80 ad:0x40298AC0 ad:0x40298B00 ad:0x40298B40 ad:0x40298B80 ad:0x40298BC0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F)(list ad:0x40298C00 ad:0x40298C40 ad:0x40298C80 ad:0x40298CC0 ad:0x40298D00 ad:0x40298D40 ad:0x40298D80 ad:0x40298DC0 ad:0x40298E00 ad:0x40298E40 ad:0x40298E80 ad:0x40298EC0 ad:0x40298F00 ad:0x40298F40 ad:0x40298F80 ad:0x40298FC0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F)(list ad:0x40299000 ad:0x40299040 ad:0x40299080 ad:0x402990C0 ad:0x40299100 ad:0x40299140 ad:0x40299180 ad:0x402991C0 ad:0x40299200 ad:0x40299240 ad:0x40299280 ad:0x402992C0 ad:0x40299300 ad:0x40299340 ad:0x40299380 ad:0x402993C0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 12. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B)(list ad:0x40299400 ad:0x40299440 ad:0x40299480 ad:0x402994C0 ad:0x40299500 ad:0x40299540 ad:0x40299580 ad:0x402995C0 ad:0x40299600 ad:0x40299640 ad:0x40299680 ad:0x402996C0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree.end
|
|
tree "EFUSE (OTP eFuse Memory)"
|
|
base ad:0x0
|
|
tree "EFUSE_DATA"
|
|
base ad:0x402C0800
|
|
group.long 0x2C++0x17
|
|
line.long 0x0 "SECURE_HASH_WORD0,Secure 128 bits HASH word 0 that is used for authentication in SECURE protection state."
|
|
hexmask.long 0x0 0.--31. 1. "HASH_WORD0,Secure 128 bits HASH word 0 that is used for authentication in SECURE protection state."
|
|
line.long 0x4 "SECURE_HASH_WORD1,Secure 128 bits HASH word 1 that is used for authentication in SECURE protection state."
|
|
hexmask.long 0x4 0.--31. 1. "HASH_WORD1,Secure 128 bits HASH word 1 that is used for authentication in SECURE protection state."
|
|
line.long 0x8 "SECURE_HASH_WORD2,Secure 128 bits HASH word 2 that is used for authentication in SECURE protection state."
|
|
hexmask.long 0x8 0.--31. 1. "HASH_WORD2,Secure 128 bits HASH word 2 that is used for authentication in SECURE protection state."
|
|
line.long 0xC "SECURE_HASH_WORD3,Secure 128 bits HASH word 3 that is used for authentication in SECURE protection state."
|
|
hexmask.long 0xC 0.--31. 1. "HASH_WORD3,Secure 128 bits HASH word 3 that is used for authentication in SECURE protection state."
|
|
line.long 0x10 "SECURE_ACCESS_RESTRICT,Access restrictions for SECURE protection state in SECURE lifecycle stage"
|
|
hexmask.long.word 0x10 21.--31. 1. "RESEREVED,N/A"
|
|
bitfld.long 0x10 20. "SMIF_XIP_ENABLE,goes to SYS DAP MPU" "0,1"
|
|
bitfld.long 0x10 18.--19. "MMIO_ALLOWED,goes to SYS DAP MPU" "0,1,2,3"
|
|
bitfld.long 0x10 16.--17. "SFLASH_ALLOWED,goes to SYS DAP MPU" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 14.--15. "WORK_FLASH_ALLOWED,goes to SYS DAP MPU" "0,1,2,3"
|
|
bitfld.long 0x10 11.--13. "SRAM_ALLOWED,goes to SYS DAP MPU" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 8.--10. "FLASH_ALLOWED,goes to SYS DAP MPU" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 7. "DIRECT_EXECUTE_DISABLE,used by ROM boot" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. "SYS_AP_MPU_ENABLE,goes to SYS DAP MPU" "0,1"
|
|
bitfld.long 0x10 4.--5. "AP_CTL_SYS_DISABLE,goes to CPUSS.AP_CTL" "0,1,2,3"
|
|
bitfld.long 0x10 2.--3. "AP_CTL_CMX_DISABLE,goes to CPUSS.AP_CTL" "0,1,2,3"
|
|
bitfld.long 0x10 0.--1. "AP_CTL_CM0_DISABLE,goes to CPUSS.AP_CTL" "0,1,2,3"
|
|
line.long 0x14 "SECURE_DEAD_ACCESS_RESTRICT_ZEROS,Access restrictions for DEAD protection state in SECURE lifecycle stage and number of zeros for Secure fuse group"
|
|
hexmask.long.byte 0x14 24.--31. 1. "SECURE_GROUP_ZEROS,number of zeros for Secure fuse group covers secure hash secure access restriction secure hash zeros secure dead access restriction"
|
|
bitfld.long 0x14 20. "SMIF_XIP_ENABLE,goes to SYS DAP MPU" "0,1"
|
|
bitfld.long 0x14 18.--19. "MMIO_ALLOWED,goes to SYS DAP MPU" "0,1,2,3"
|
|
bitfld.long 0x14 16.--17. "SFLASH_ALLOWED,goes to SYS DAP MPU" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 14.--15. "WORK_FLASH_ALLOWED,goes to SYS DAP MPU" "0,1,2,3"
|
|
bitfld.long 0x14 11.--13. "SRAM_ALLOWED,goes to SYS DAP MPU" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 8.--10. "FLASH_ALLOWED,goes to SYS DAP MPU" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 7. "DIRECT_EXECUTE_DISABLE,used by ROM boot" "0,1"
|
|
newline
|
|
bitfld.long 0x14 6. "SYS_AP_MPU_ENABLE,goes to SYS DAP MPU" "0,1"
|
|
bitfld.long 0x14 4.--5. "AP_CTL_SYS_DISABLE,goes to CPUSS.AP_CTL" "0,1,2,3"
|
|
bitfld.long 0x14 2.--3. "AP_CTL_CMX_DISABLE,goes to CPUSS.AP_CTL" "0,1,2,3"
|
|
bitfld.long 0x14 0.--1. "AP_CTL_CM0_DISABLE,goes to CPUSS.AP_CTL" "0,1,2,3"
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x68)++0x3
|
|
line.long 0x0 "CUSTOMER_DATA[$1],Available EFUSE bits for customer usage.They can be programmed in NORMAL protection state via CMx/DAP and in SECURE protection state via CMx."
|
|
hexmask.long 0x0 0.--31. 1. "DATA_BYTE,Available EFUSE bits for customer usage.They can be programmed in NORMAL protection state via CMx/DAP and in SECURE protection state via CMx."
|
|
repeat.end
|
|
tree.end
|
|
tree "EFUSE_MXS40"
|
|
base ad:0x402C0000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "ENABLED,IP enable:" "0,1"
|
|
line.long 0x4 "TEST,Test"
|
|
bitfld.long 0x4 0.--1. "MARG_READ,Margin Read" "0: Low Resistance: -50 percent from nominal,1: Nominal resistance (Default read condition),2: High Resistance: +50 percent from nominal,3: Higher Resistance: +100 percent from nominal"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "CMD,Command"
|
|
bitfld.long 0x0 31. "START,FW sets this field to '1' to start a program operation. HW sets this field to '0' to indicate that the operation has completed." "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "MACRO_ADDR,Macro address. This field specifies an eFUSE macro."
|
|
hexmask.long.byte 0x0 8.--12. 1. "BYTE_ADDR,Byte address. This field specifies a Byte within a eFUSE macro (each macro has 32 B)."
|
|
bitfld.long 0x0 4.--6. "BIT_ADDR,Bit address. This field specifies a bit within a Byte." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0. "BIT_DATA,Bit data. This field specifies the bit value that is to be programmed into the eFUSE macro array. The address of the bit is specified by the BIT_ADDR BYTE_ADDR and MACRO_ADDR fields. This bit is a don't care for the MXS40 Macro." "0,1"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SEQ_DEFAULT,Sequencer Default value"
|
|
bitfld.long 0x0 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x0 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x0 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x0 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
bitfld.long 0x0 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x0 16. "STROBE_A,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
group.long 0x40++0x17
|
|
line.long 0x0 "SEQ_READ_CTL_0,Sequencer read control 0"
|
|
bitfld.long 0x0 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x0 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x0 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x0 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x0 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x0 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x0 16. "STROBE_A,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
hexmask.long.word 0x0 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x4 "SEQ_READ_CTL_1,Sequencer read control 1"
|
|
bitfld.long 0x4 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x4 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x4 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x4 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x4 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x4 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x4 16. "STROBE_A,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x8 "SEQ_READ_CTL_2,Sequencer read control 2"
|
|
bitfld.long 0x8 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x8 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x8 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x8 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x8 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x8 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x8 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x8 16. "STROBE_A,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
hexmask.long.word 0x8 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0xC "SEQ_READ_CTL_3,Sequencer read control 3"
|
|
bitfld.long 0xC 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0xC 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0xC 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0xC 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0xC 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0xC 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0xC 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0xC 16. "STROBE_A,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
hexmask.long.word 0xC 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x10 "SEQ_READ_CTL_4,Sequencer read control 4"
|
|
bitfld.long 0x10 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x10 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x10 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x10 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x10 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x10 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x10 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x10 16. "STROBE_A,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
hexmask.long.word 0x10 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x14 "SEQ_READ_CTL_5,Sequencer read control 5"
|
|
bitfld.long 0x14 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x14 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x14 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x14 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x14 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x14 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x14 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x14 16. "STROBE_A,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
hexmask.long.word 0x14 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
group.long 0x60++0x17
|
|
line.long 0x0 "SEQ_PROGRAM_CTL_0,Sequencer program control 0"
|
|
bitfld.long 0x0 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x0 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x0 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x0 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x0 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x0 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x0 16. "STROBE_A,Specifies value of eFUSE control signal strobe_a" "0,1"
|
|
hexmask.long.word 0x0 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x4 "SEQ_PROGRAM_CTL_1,Sequencer program control 1"
|
|
bitfld.long 0x4 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x4 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x4 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x4 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x4 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x4 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x4 16. "STROBE_A,Specifies value of eFUSE control signal strobe_a" "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x8 "SEQ_PROGRAM_CTL_2,Sequencer program control 2"
|
|
bitfld.long 0x8 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x8 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x8 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x8 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x8 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x8 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x8 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x8 16. "STROBE_A,Specifies value of eFUSE control signal strobe_a" "0,1"
|
|
hexmask.long.word 0x8 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0xC "SEQ_PROGRAM_CTL_3,Sequencer program control 3"
|
|
bitfld.long 0xC 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0xC 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0xC 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0xC 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0xC 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0xC 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0xC 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0xC 16. "STROBE_A,Specifies value of eFUSE control signal strobe_a" "0,1"
|
|
hexmask.long.word 0xC 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x10 "SEQ_PROGRAM_CTL_4,Sequencer program control 4"
|
|
bitfld.long 0x10 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x10 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x10 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x10 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x10 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x10 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x10 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x10 16. "STROBE_A,Specifies value of eFUSE control signal strobe_a" "0,1"
|
|
hexmask.long.word 0x10 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x14 "SEQ_PROGRAM_CTL_5,Sequencer program control 5"
|
|
bitfld.long 0x14 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x14 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x14 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x14 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x14 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x14 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x14 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x14 16. "STROBE_A,Specifies value of eFUSE control signal strobe_a" "0,1"
|
|
hexmask.long.word 0x14 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
tree.end
|
|
tree.end
|
|
tree "EVTGEN (Event Generator)"
|
|
base ad:0x403F0000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "ENABLED,IP enable:" "0: N/A,1: N/A"
|
|
rgroup.long 0x4++0x7
|
|
line.long 0x0 "COMP0_STATUS,Comparator structures comparator 0 status"
|
|
hexmask.long.word 0x0 0.--15. 1. "COMP0_OUT,Active comparator 'comp0_out[]' outputs."
|
|
line.long 0x4 "COMP1_STATUS,Comparator structures comparator 1 status"
|
|
hexmask.long.word 0x4 0.--15. 1. "COMP1_OUT,DeepSleep comparator 'comp1_out_lf[]' outputs (synchronized from clk_lf to the IP clock)."
|
|
rgroup.long 0x10++0x7
|
|
line.long 0x0 "COUNTER_STATUS,Counter status"
|
|
bitfld.long 0x0 31. "VALID,Active counter validity:" "0,1"
|
|
line.long 0x4 "COUNTER,Counter"
|
|
hexmask.long 0x4 0.--31. 1. "INT32,Active counter 'counter_int[31:0]' on clk_ref_div."
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "RATIO_CTL,Ratio control"
|
|
bitfld.long 0x0 31. "VALID,Ratio value valid:" "0,1"
|
|
bitfld.long 0x0 30. "DYNAMIC,Specifies if RATIO_CTL.VALID and RATIO are under SW or HW control:" "?,1: HW control"
|
|
bitfld.long 0x0 16.--18. "DYNAMIC_MODE,Weighted average calculation (only used when DYNAMIC is '1'):" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "RATIO,Ratio"
|
|
hexmask.long.word 0x4 16.--31. 1. "INT16,Integer component of ratio value."
|
|
hexmask.long.byte 0x4 8.--15. 1. "FRAC8,Fractional component of ratio value."
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "REF_CLOCK_CTL,Reference clock control"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_DIV,Divider control for clk_ref_div:"
|
|
group.long 0x700++0xB
|
|
line.long 0x0 "INTR,Interrupt"
|
|
hexmask.long.word 0x0 0.--15. 1. "COMP0,This interrupt cause field is activated (HW sets the field to '1') when a comparator 0 event is generated (Active counter 'counter_int[31:0]' becomes greater or equal to COMP0.INT[31:0])."
|
|
line.long 0x4 "INTR_SET,Interrupt set"
|
|
hexmask.long.word 0x4 0.--15. 1. "COMP0,SW writes a '1' to this field to set the corresponding field in the INTR register."
|
|
line.long 0x8 "INTR_MASK,Interrupt mask"
|
|
hexmask.long.word 0x8 0.--15. 1. "COMP0,Mask bit for corresponding field in the INTR register."
|
|
rgroup.long 0x70C++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
hexmask.long.word 0x0 0.--15. 1. "COMP0,Logical and of corresponding INTR and INTR_MASK fields."
|
|
group.long 0x710++0xB
|
|
line.long 0x0 "INTR_DPSLP,DeepSleep interrupt"
|
|
hexmask.long.word 0x0 0.--15. 1. "COMP1,This interrupt cause field is activated (HW sets the field to '1') when a comparator 1 event is generated (DeepSleep counter 'counter_int_lf[31:0]' becomes greater or equal to COMP1.INT[31:0])."
|
|
line.long 0x4 "INTR_DPSLP_SET,DeepSleep interrupt set"
|
|
hexmask.long.word 0x4 0.--15. 1. "COMP1,SW writes a '1' to this field to set the corresponding field in the INTR register."
|
|
line.long 0x8 "INTR_DPSLP_MASK,DeepSleep interrupt mask"
|
|
hexmask.long.word 0x8 0.--15. 1. "COMP1,Mask bit for corresponding field in the INTR register."
|
|
rgroup.long 0x71C++0x3
|
|
line.long 0x0 "INTR_DPSLP_MASKED,DeepSleep interrupt masked"
|
|
hexmask.long.word 0x0 0.--15. 1. "COMP1,Logical and of corresponding INTR and INTR_MASK fields."
|
|
repeat 11. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA)(list ad:0x403F0800 ad:0x403F0820 ad:0x403F0840 ad:0x403F0860 ad:0x403F0880 ad:0x403F08A0 ad:0x403F08C0 ad:0x403F08E0 ad:0x403F0900 ad:0x403F0920 ad:0x403F0940)
|
|
tree "COMP_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0xB
|
|
line.long 0x0 "COMP_CTL,Comparator control"
|
|
bitfld.long 0x0 31. "ENABLED,Comparator structure enable:" "0,1"
|
|
bitfld.long 0x0 16. "TR_OUT_EDGE,Specifies the 'tr_out' output trigger:" "0,1"
|
|
bitfld.long 0x0 1. "COMP1_EN,DeepSleep comparator (COMP1) enable:" "0,1"
|
|
bitfld.long 0x0 0. "COMP0_EN,Active comparator (COMP0) enable:" "0,1"
|
|
line.long 0x4 "COMP0,Comparator 0 (Active functionality)"
|
|
hexmask.long 0x4 0.--31. 1. "INT32,This value is a 32-bit unsigned integer in the range [0 2^32-1]. The comparator 'comp0_out' output is activated when the Active counter 'counter_int[31:0]' becomes greater or equal to COMP0."
|
|
line.long 0x8 "COMP1,Comparator 1 (DeepSleep functionality)"
|
|
hexmask.long 0x8 0.--31. 1. "INT32,This value is a 32-bit unsigned integer in the range [0 2^32-1]. The comparator 'comp1_out_lf' output is activated when the DeepSleep counter 'counter_int_lf[31:0]' becomes greater or equal to COMP1."
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "FAULT (Fault Structures)"
|
|
base ad:0x40210000
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x40210000 ad:0x40210100 ad:0x40210200 ad:0x40210300)
|
|
tree "STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTL,Fault control"
|
|
bitfld.long 0x0 2. "RESET_REQ_EN,Reset request enable:" "0,1"
|
|
bitfld.long 0x0 1. "OUT_EN,IO output signal enable:" "0,1"
|
|
bitfld.long 0x0 0. "TR_EN,Trigger output enable:" "0,1"
|
|
group.long ($2+0xC)++0x3
|
|
line.long 0x0 "STATUS,Fault status"
|
|
bitfld.long 0x0 31. "VALID,Valid indication:" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "IDX,The fault source index for which fault information is captured in DATA0 through DATA3. The fault information is fault source specific and described below."
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x10)++0x3
|
|
line.long 0x0 "DATA[$1],Fault data"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Captured fault source data."
|
|
repeat.end
|
|
rgroup.long ($2+0x40)++0xB
|
|
line.long 0x0 "PENDING0,Fault pending 0"
|
|
hexmask.long 0x0 0.--31. 1. "SOURCE,This field specifies the following sources:"
|
|
line.long 0x4 "PENDING1,Fault pending 1"
|
|
hexmask.long 0x4 0.--31. 1. "SOURCE,This field specifies the following sources:"
|
|
line.long 0x8 "PENDING2,Fault pending 2"
|
|
hexmask.long 0x8 0.--31. 1. "SOURCE,This field specifies the following sources:"
|
|
group.long ($2+0x50)++0xB
|
|
line.long 0x0 "MASK0,Fault mask 0"
|
|
hexmask.long 0x0 0.--31. 1. "SOURCE,Fault source enables:"
|
|
line.long 0x4 "MASK1,Fault mask 1"
|
|
hexmask.long 0x4 0.--31. 1. "SOURCE,Fault source enables:"
|
|
line.long 0x8 "MASK2,Fault mask 2"
|
|
hexmask.long 0x8 0.--31. 1. "SOURCE,Fault source enables:"
|
|
group.long ($2+0xC0)++0xB
|
|
line.long 0x0 "INTR,Interrupt"
|
|
bitfld.long 0x0 0. "FAULT,This interrupt cause field is activated (HW sets the field to '1') when an enabled (MASK0/MASK1/MASK2) pending fault source is captured:" "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set"
|
|
bitfld.long 0x4 0. "FAULT,SW writes a '1' to this field to set the corresponding field in the INTR register." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x8 0. "FAULT,Mask bit for corresponding field in the INTR register." "0,1"
|
|
rgroup.long ($2+0xCC)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "FAULT,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "FLASHC (Flash Controller)"
|
|
base ad:0x40240000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "FLASH_CTL,Control"
|
|
bitfld.long 0x0 22. "WORK_ERR_SILENT,Specifies bus transfer behavior for a non-recoverable error on the FLASH macro work interface (either a non-correctable ECC error a FLASH macro work interface internal error a FLASH macro work interface memory hole access):" "0: Bus transfer has a bus error,1: Bus transfer does NOT have a bus error; i"
|
|
bitfld.long 0x0 21. "WORK_ECC_INJ_EN,Enable error injection for FLASH work interface." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "WORK_ECC_EN,Enable ECC checking for FLASH work interface:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 18. "MAIN_ERR_SILENT,Specifies bus transfer behavior for a non-recoverable error on the FLASH macro main interface (either a non-correctable ECC error a FLASH macro main interface internal error a FLASH macro main interface memory hole access):" "0: Bus transfer has a bus error,1: Bus transfer does NOT have a bus error; i"
|
|
newline
|
|
bitfld.long 0x0 17. "MAIN_ECC_INJ_EN,Enable error injection for FLASH main interface." "0,1"
|
|
bitfld.long 0x0 16. "MAIN_ECC_EN,Enable ECC checking for FLASH main interface:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 13. "WORK_BANK_MODE,Specifies bank mode of FLASH macro work array." "0: Single bank mode,1: Dual bank mode"
|
|
bitfld.long 0x0 12. "MAIN_BANK_MODE,Specifies bank mode of FLASH macro main array." "0: Single bank mode,1: Dual bank mode"
|
|
newline
|
|
bitfld.long 0x0 9. "WORK_MAP,Specifies mapping of FLASH macro work array." "0: Mapping A,1: Mapping B"
|
|
bitfld.long 0x0 8. "MAIN_MAP,Specifies mapping of FLASH macro main array." "0: Mapping A,1: Mapping B"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "MAIN_WS,FLASH macro main interface wait states:"
|
|
line.long 0x4 "FLASH_PWR_CTL,Flash power control"
|
|
bitfld.long 0x4 1. "ENABLE_HV,Controls 'enable_hv' pin of the Flash memory." "0,1"
|
|
bitfld.long 0x4 0. "ENABLE,Controls 'enable' pin of the Flash memory." "0,1"
|
|
line.long 0x8 "FLASH_CMD,Command"
|
|
bitfld.long 0x8 1. "BUFF_INV,Invalidation of ALL buffers (does not invalidate the caches). SW writes a '1' to clear the buffers. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and.." "0,1"
|
|
bitfld.long 0x8 0. "INV,Invalidation of ALL caches (for CM0+ and CM4) and ALL buffers. SW writes a '1' to clear the caches. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and.." "0,1"
|
|
group.long 0x2A0++0x3
|
|
line.long 0x0 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR."
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "WORD_ADDR,Specifies the word address where an error will be injected."
|
|
group.long 0x2B0++0x7
|
|
line.long 0x0 "FM_SRAM_ECC_CTL0,eCT Flash SRAM ECC control 0"
|
|
hexmask.long 0x0 0.--31. 1. "ECC_INJ_DATA,32-bit data for ECC error injection test of eCT Flash SRAM ECC logic."
|
|
line.long 0x4 "FM_SRAM_ECC_CTL1,eCT Flash SRAM ECC control 1"
|
|
hexmask.long.byte 0x4 0.--6. 1. "ECC_INJ_PARITY,7-bit parity for ECC error injection test of eCT Flash SRAM ECC logic."
|
|
rgroup.long 0x2B8++0x3
|
|
line.long 0x0 "FM_SRAM_ECC_CTL2,eCT Flash SRAM ECC control 2"
|
|
hexmask.long 0x0 0.--31. 1. "CORRECTED_DATA,32-bit corrected data output of the ECC syndrome logic."
|
|
group.long 0x2BC++0x3
|
|
line.long 0x0 "FM_SRAM_ECC_CTL3,eCT Flash SRAM ECC control 3"
|
|
rbitfld.long 0x0 8. "ECC_TEST_FAIL,Status of ECC test." "0: ECC was performed,1: ECC test failed because eCT Flash macro is busy.."
|
|
bitfld.long 0x0 4. "ECC_INJ_EN,eCT Flash SRAM ECC error injection test enable. Follow the steps below for ECC logic test:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ECC_ENABLE,ECC generation/check enable for eCT Flash SRAM memory." "0,1"
|
|
group.long 0x400++0xB
|
|
line.long 0x0 "CM0_CA_CTL0,CM0+ cache control"
|
|
bitfld.long 0x0 31. "CA_EN,Cache enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 30. "PREF_EN,Prefetch enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "SET_ADDR,Specifies the cache set for which cache information is provided in CM0_CA_STATUS0/1/2." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--17. "WAY,Specifies the cache way for which cache information is provided in CM0_CA_STATUS0/1/2." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 1. "RAM_ECC_INJ_EN,Enable error injection for cache." "0,1"
|
|
bitfld.long 0x0 0. "RAM_ECC_EN,Enable ECC checking for cache accesses:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "CM0_CA_CTL1,CM0+ cache control"
|
|
hexmask.long.word 0x4 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)."
|
|
bitfld.long 0x4 0.--1. "PWR_MODE,Specifies power mode for CM0 cache." "0: Power OFF the CM0 cache SRAM.,1: Undefined,2: Put CM0 cache SRAM in retained mode.,3: Enable/Turn ON the CM0 cache SRAM."
|
|
line.long 0x8 "CM0_CA_CTL2,CM0+ cache control"
|
|
hexmask.long.word 0x8 0.--9. 1. "PWRUP_DELAY,Number clock cycles delay needed after power domain power up"
|
|
rgroup.long 0x440++0xB
|
|
line.long 0x0 "CM0_CA_STATUS0,CM0+ cache status 0"
|
|
hexmask.long 0x0 0.--31. 1. "VALID32,Sixteen valid bits of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR."
|
|
line.long 0x4 "CM0_CA_STATUS1,CM0+ cache status 1"
|
|
hexmask.long 0x4 0.--31. 1. "TAG,Cache line address of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR."
|
|
line.long 0x8 "CM0_CA_STATUS2,CM0+ cache status 2"
|
|
hexmask.long.byte 0x8 0.--5. 1. "LRU,Six bit LRU representation of the cache set specified by CM0_CA_CTL.SET_ADDR. The encoding of the field is as follows ('X_LRU_Y' indicates that way X is Less Recently Used than way Y):"
|
|
group.long 0x460++0x3
|
|
line.long 0x0 "CM0_STATUS,CM0+ interface status"
|
|
bitfld.long 0x0 1. "WORK_INTERNAL_ERR,See CM0_STATUS.MAIN_INTERNAL_ERROR." "0,1"
|
|
bitfld.long 0x0 0. "MAIN_INTERNAL_ERR,Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM0+ access." "0,1"
|
|
group.long 0x480++0xB
|
|
line.long 0x0 "CM4_CA_CTL0,CM4 cache control"
|
|
bitfld.long 0x0 31. "CA_EN,See CM0_CA_CTL." "0,1"
|
|
bitfld.long 0x0 30. "PREF_EN,See CM0_CA_CTL." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "SET_ADDR,See CM0_CA_CTL." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--17. "WAY,See CM0_CA_CTL." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 1. "RAM_ECC_INJ_EN,See CM0_CA_CTL." "0,1"
|
|
bitfld.long 0x0 0. "RAM_ECC_EN,See CM0_CA_CTL." "0,1"
|
|
line.long 0x4 "CM4_CA_CTL1,CM4 cache control"
|
|
hexmask.long.word 0x4 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)."
|
|
bitfld.long 0x4 0.--1. "PWR_MODE,Specifies power mode for CM4 cache. Refer CM0_CA_CTL1 for more details." "0: See CM0_CA_CTL1,1: Undefined,2: See CM0_CA_CTL1,3: See CM0_CA_CTL1"
|
|
line.long 0x8 "CM4_CA_CTL2,CM4 cache control"
|
|
hexmask.long.word 0x8 0.--9. 1. "PWRUP_DELAY,Number clock cycles delay needed after power domain power up"
|
|
rgroup.long 0x4C0++0xB
|
|
line.long 0x0 "CM4_CA_STATUS0,CM4 cache status 0"
|
|
hexmask.long 0x0 0.--31. 1. "VALID32,See CM0_CA_STATUS0."
|
|
line.long 0x4 "CM4_CA_STATUS1,CM4 cache status 1"
|
|
hexmask.long 0x4 0.--31. 1. "TAG,See CM0_CA_STATUS1."
|
|
line.long 0x8 "CM4_CA_STATUS2,CM4 cache status 2"
|
|
hexmask.long.byte 0x8 0.--5. 1. "LRU,See CM0_CA_STATUS2."
|
|
group.long 0x4E0++0x3
|
|
line.long 0x0 "CM4_STATUS,CM4 interface status"
|
|
bitfld.long 0x0 1. "WORK_INTERNAL_ERR,See CM0_STATUS.MAIN_INTERNAL_ERROR." "0,1"
|
|
bitfld.long 0x0 0. "MAIN_INTERNAL_ERR,See CM0_STATUS.MAIN_INTERNAL_ERROR." "0,1"
|
|
group.long 0x500++0x3
|
|
line.long 0x0 "CRYPTO_BUFF_CTL,Cryptography buffer control"
|
|
bitfld.long 0x0 30. "PREF_EN,Prefetch enable:" "0: Disabled,1: Enabled"
|
|
group.long 0x580++0x3
|
|
line.long 0x0 "DW0_BUFF_CTL,Datawire 0 buffer control"
|
|
bitfld.long 0x0 30. "PREF_EN,See CRYPTO_BUFF_CTL." "0,1"
|
|
group.long 0x600++0x3
|
|
line.long 0x0 "DW1_BUFF_CTL,Datawire 1 buffer control"
|
|
bitfld.long 0x0 30. "PREF_EN,See CRYPTO_BUFF_CTL." "0,1"
|
|
group.long 0x680++0x3
|
|
line.long 0x0 "DMAC_BUFF_CTL,DMA controller buffer control"
|
|
bitfld.long 0x0 30. "PREF_EN,See CRYPTO_BUFF_CTL." "0,1"
|
|
group.long 0x700++0x3
|
|
line.long 0x0 "EXT_MS0_BUFF_CTL,External master 0 buffer control"
|
|
bitfld.long 0x0 30. "PREF_EN,See CRYPTO_BUFF_CTL." "0,1"
|
|
group.long 0x780++0x3
|
|
line.long 0x0 "EXT_MS1_BUFF_CTL,External master 1 buffer control"
|
|
bitfld.long 0x0 30. "PREF_EN,See CRYPTO_BUFF_CTL." "0,1"
|
|
tree "FM_CTL_ECT (Flash Macro Registers)"
|
|
base ad:0x4024F000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "FM_CTL,Flash Macro Control"
|
|
bitfld.long 0x0 31. "EMB_START,'0': not active" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "FM_MODE,Flash macro mode selection:"
|
|
line.long 0x4 "FM_CODE_MARGIN,Flash Macro Margin Mode on Code Flash"
|
|
bitfld.long 0x4 31. "MARGIN_MODE_EN,when set puts the s40ect Flash IP In Margin mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "MARGIN_MODE_RDREG_CHNG_EN,when set will also use the MARGIN_RDREG_TRIM from above. Default is not to use" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "MARGIN_PGM_ERS_B,0: ERS Margin is checked" "0: ERS Margin is checked,1: PGM Margin is checked"
|
|
newline
|
|
hexmask.long.byte 0x4 10.--15. 1. "MARGIN_RDREG_TRIM,rdreg_c trim to be used in Margin mode if enabled by MARGIN_MODE_RDREG_CHNG_EN"
|
|
newline
|
|
bitfld.long 0x4 9. "MARGIN_DCS_TRIM_EN,0: internal device defaults used from Margin reads reference current" "0: internal device defaults used from Margin reads..,1: MARGIN_DCS_TRIM configuration is used during.."
|
|
newline
|
|
hexmask.long.word 0x4 0.--8. 1. "MARGIN_DCS_TRIM,see above table to set the DCS reference current value to be used during Margin mode. (default set to 5uS = 0x143) which gives a Margin to the Erase side. 7uA would probably be used for Margin to the PGM side"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "FM_ADDR,Flash Macro Address"
|
|
hexmask.long 0x0 0.--31. 1. "FM_ADDR,Code or Work Flash Address to be used during write operations (PGM/ERS)"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "INTR,Interrupt"
|
|
bitfld.long 0x0 0. "INTR,Set to '1' when event is detected. Write INTR field with '1' to clear bit. Write INTR_SET field with '1' to set bit." "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt Set"
|
|
bitfld.long 0x4 0. "INTR_SET,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt Mask"
|
|
bitfld.long 0x8 0. "INTR_MASK,Mask for corresponding field in the INTR register" "0,1"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt Masked"
|
|
bitfld.long 0x0 0. "INTR_MASKED,Logical and of corresponding request and mask fields." "0,1"
|
|
wgroup.long 0x30++0x3
|
|
line.long 0x0 "ECC_OVERRIDE,ECC Data In override information and control bits"
|
|
bitfld.long 0x0 31. "ECC_OVERRIDE_CODE,0: no override. Using internal ECC engine to calculate the ECC of the Code Flash" "0: no override,?"
|
|
newline
|
|
bitfld.long 0x0 30. "ECC_OVERRIDE_WORK,0: no override. Using internal ECC engine to calculate the ECC of the Work Flash" "0: no override,?"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "ECC_OVERRIDE_SYNDROME,The override syndrome itself to be used in case one of the enables are set. It will take [7:0] in the case of Code flash and [6:0] in the case of work flash to bypass the internal generated syndrome"
|
|
wgroup.long 0x40++0x3
|
|
line.long 0x0 "FM_DATA,Flash macro data_in[31 to 0] both Code and Work Flash"
|
|
hexmask.long 0x0 0.--31. 1. "FM_DATA,Pgm command data in going to the internal write buffer (WBUF)."
|
|
group.long 0x64++0x3
|
|
line.long 0x0 "BOOKMARK,Bookmark register - keeps the current FW HV seq"
|
|
hexmask.long 0x0 0.--31. 1. "BOOKMARK,Used by FW. Keeps the Current HV cycle sequence"
|
|
group.long 0x400++0x3
|
|
line.long 0x0 "MAIN_FLASH_SAFETY,Main (Code) Flash Security enable"
|
|
bitfld.long 0x0 0. "MAINFLASHWRITEENABLE,'0': Main Flash embedded operations are blocked" "0,1"
|
|
rgroup.long 0x404++0x3
|
|
line.long 0x0 "STATUS,Status read from Flash Macro"
|
|
bitfld.long 0x0 31. "BUSY,Whenever the device is in embedded mode the RDY goes low. Should be the same as c_interrupt pin of the IP (but inverted)" "0: rdy,1: busy in embedded"
|
|
newline
|
|
bitfld.long 0x0 30. "HANG,After embedded operation (pgm/erase) this flag will tell if it was successful or failed" "0: PASS,1: FAIL"
|
|
newline
|
|
bitfld.long 0x0 29. "NATIVE_POR,Indicates a Native Flash state (UV) or sorted one." "0: SORTED DEVICE,1: NATIVE"
|
|
newline
|
|
bitfld.long 0x0 28. "POR_2B_ECC_ERROR,Indicates an internal ECC error of 2b while downloading info in POR from NVM to VM." "0: No error,1: ECC 2b Error in POR"
|
|
newline
|
|
bitfld.long 0x0 27. "POR_1B_ECC_CORRECTED,Indicates internal ECC found 1b error while downloading info in POR from NVM to VM and fixed it." "0: No error,?"
|
|
newline
|
|
bitfld.long 0x0 6. "BLANK_CHCEK_PASS,Indicates the Blank check command result is PASS (Blank)" "0: Not Blank,1: Blank"
|
|
newline
|
|
bitfld.long 0x0 5. "BLANK_CHECK_WORK,Indicates if Blank Check mode is currently running on the work flash" "0: not running,1: running"
|
|
newline
|
|
bitfld.long 0x0 4. "ERS_SUSPEND,Indicates if Erase operation (Code/Work) is currently being suspended" "0: not suspended,1: suspended"
|
|
newline
|
|
bitfld.long 0x0 3. "ERASE_WORK,Indicates if active Erase operation to the Work flash is taking place" "0: not running,1: running"
|
|
newline
|
|
bitfld.long 0x0 2. "ERASE_CODE,Indicates if active Erase operation to the Code flash is taking place" "0: not running,1: running"
|
|
newline
|
|
bitfld.long 0x0 1. "PGM_WORK,Indicates if active PGM operation to the Work flash is taking place" "0: not running,1: running"
|
|
newline
|
|
bitfld.long 0x0 0. "PGM_CODE,Indicates if active PGM operation to the Code flash is taking place" "0: not running,1: running"
|
|
group.long 0x500++0x3
|
|
line.long 0x0 "WORK_FLASH_SAFETY,Work Flash Security enable"
|
|
bitfld.long 0x0 0. "WORKFLASHWRITEENABLE,0: Work Flash embedded operations are blocked" "0: Work Flash embedded operations are blocked,1: Work Flash embedded operations are enabled"
|
|
tree.end
|
|
tree.end
|
|
tree "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"
|
|
base ad:0x40310000
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40310000 ad:0x40310080 ad:0x40310100 ad:0x40310180 ad:0x40310200 ad:0x40310280 ad:0x40310300 ad:0x40310380 ad:0x40310400 ad:0x40310480 ad:0x40310500 ad:0x40310580 ad:0x40310600 ad:0x40310680 ad:0x40310700 ad:0x40310780)
|
|
tree "PRT[$1]"
|
|
base $2
|
|
group.long ($2)++0xF
|
|
line.long 0x0 "OUT,Port output data register"
|
|
bitfld.long 0x0 7. "OUT7,IO output data for pin 7" "0,1"
|
|
bitfld.long 0x0 6. "OUT6,IO output data for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OUT5,IO output data for pin 5" "0,1"
|
|
bitfld.long 0x0 4. "OUT4,IO output data for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OUT3,IO output data for pin 3" "0,1"
|
|
bitfld.long 0x0 2. "OUT2,IO output data for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OUT1,IO output data for pin 1" "0,1"
|
|
bitfld.long 0x0 0. "OUT0,IO output data for pin 0" "0,1"
|
|
line.long 0x4 "OUT_CLR,Port output data clear register"
|
|
bitfld.long 0x4 7. "OUT7,IO clear output for pin 7" "0,1"
|
|
bitfld.long 0x4 6. "OUT6,IO clear output for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OUT5,IO clear output for pin 5" "0,1"
|
|
bitfld.long 0x4 4. "OUT4,IO clear output for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OUT3,IO clear output for pin 3" "0,1"
|
|
bitfld.long 0x4 2. "OUT2,IO clear output for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "OUT1,IO clear output for pin 1" "0,1"
|
|
bitfld.long 0x4 0. "OUT0,IO clear output for pin 0:" "0,1"
|
|
line.long 0x8 "OUT_SET,Port output data set register"
|
|
bitfld.long 0x8 7. "OUT7,IO set output for pin 7" "0,1"
|
|
bitfld.long 0x8 6. "OUT6,IO set output for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OUT5,IO set output for pin 5" "0,1"
|
|
bitfld.long 0x8 4. "OUT4,IO set output for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "OUT3,IO set output for pin 3" "0,1"
|
|
bitfld.long 0x8 2. "OUT2,IO set output for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "OUT1,IO set output for pin 1" "0,1"
|
|
bitfld.long 0x8 0. "OUT0,IO set output for pin 0:" "0,1"
|
|
line.long 0xC "OUT_INV,Port output data invert register"
|
|
bitfld.long 0xC 7. "OUT7,IO invert output for pin 7" "0,1"
|
|
bitfld.long 0xC 6. "OUT6,IO invert output for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "OUT5,IO invert output for pin 5" "0,1"
|
|
bitfld.long 0xC 4. "OUT4,IO invert output for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "OUT3,IO invert output for pin 3" "0,1"
|
|
bitfld.long 0xC 2. "OUT2,IO invert output for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "OUT1,IO invert output for pin 1" "0,1"
|
|
bitfld.long 0xC 0. "OUT0,IO invert output for pin 0:" "0,1"
|
|
rgroup.long ($2+0x10)++0x3
|
|
line.long 0x0 "IN,Port input state register"
|
|
bitfld.long 0x0 8. "FLT_IN,Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register." "0,1"
|
|
bitfld.long 0x0 7. "IN7,IO pin state for pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "IN6,IO pin state for pin 6" "0,1"
|
|
bitfld.long 0x0 5. "IN5,IO pin state for pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IN4,IO pin state for pin 4" "0,1"
|
|
bitfld.long 0x0 3. "IN3,IO pin state for pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "IN2,IO pin state for pin 2" "0,1"
|
|
bitfld.long 0x0 1. "IN1,IO pin state for pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IN0,IO pin state for pin 0" "0,1"
|
|
group.long ($2+0x14)++0x7
|
|
line.long 0x0 "INTR,Port interrupt status register"
|
|
rbitfld.long 0x0 24. "FLT_IN_IN,Filtered pin state for pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
rbitfld.long 0x0 23. "IN_IN7,IO pin state for pin 7" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 22. "IN_IN6,IO pin state for pin 6" "0,1"
|
|
rbitfld.long 0x0 21. "IN_IN5,IO pin state for pin 5" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 20. "IN_IN4,IO pin state for pin 4" "0,1"
|
|
rbitfld.long 0x0 19. "IN_IN3,IO pin state for pin 3" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 18. "IN_IN2,IO pin state for pin 2" "0,1"
|
|
rbitfld.long 0x0 17. "IN_IN1,IO pin state for pin 1" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "IN_IN0,IO pin state for pin 0" "0,1"
|
|
bitfld.long 0x0 8. "FLT_EDGE,Edge detected on filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "EDGE7,Edge detect for IO pin 7" "0,1"
|
|
bitfld.long 0x0 6. "EDGE6,Edge detect for IO pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EDGE5,Edge detect for IO pin 5" "0,1"
|
|
bitfld.long 0x0 4. "EDGE4,Edge detect for IO pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EDGE3,Edge detect for IO pin 3" "0,1"
|
|
bitfld.long 0x0 2. "EDGE2,Edge detect for IO pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EDGE1,Edge detect for IO pin 1" "0,1"
|
|
bitfld.long 0x0 0. "EDGE0,Edge detect for IO pin 0" "0,1"
|
|
line.long 0x4 "INTR_MASK,Port interrupt mask register"
|
|
bitfld.long 0x4 8. "FLT_EDGE,Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
bitfld.long 0x4 7. "EDGE7,Masks edge interrupt on IO pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "EDGE6,Masks edge interrupt on IO pin 6" "0,1"
|
|
bitfld.long 0x4 5. "EDGE5,Masks edge interrupt on IO pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EDGE4,Masks edge interrupt on IO pin 4" "0,1"
|
|
bitfld.long 0x4 3. "EDGE3,Masks edge interrupt on IO pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "EDGE2,Masks edge interrupt on IO pin 2" "0,1"
|
|
bitfld.long 0x4 1. "EDGE1,Masks edge interrupt on IO pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "EDGE0,Masks edge interrupt on IO pin 0" "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Port interrupt masked status register"
|
|
bitfld.long 0x0 8. "FLT_EDGE,Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
bitfld.long 0x0 7. "EDGE7,Edge detected and masked on IO pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "EDGE6,Edge detected and masked on IO pin 6" "0,1"
|
|
bitfld.long 0x0 5. "EDGE5,Edge detected and masked on IO pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EDGE4,Edge detected and masked on IO pin 4" "0,1"
|
|
bitfld.long 0x0 3. "EDGE3,Edge detected and masked on IO pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EDGE2,Edge detected and masked on IO pin 2" "0,1"
|
|
bitfld.long 0x0 1. "EDGE1,Edge detected and masked on IO pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EDGE0,Edge detected AND masked on IO pin 0" "0,1"
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "INTR_SET,Port interrupt set register"
|
|
bitfld.long 0x0 8. "FLT_EDGE,Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
bitfld.long 0x0 7. "EDGE7,Sets edge detect interrupt for IO pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "EDGE6,Sets edge detect interrupt for IO pin 6" "0,1"
|
|
bitfld.long 0x0 5. "EDGE5,Sets edge detect interrupt for IO pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EDGE4,Sets edge detect interrupt for IO pin 4" "0,1"
|
|
bitfld.long 0x0 3. "EDGE3,Sets edge detect interrupt for IO pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EDGE2,Sets edge detect interrupt for IO pin 2" "0,1"
|
|
bitfld.long 0x0 1. "EDGE1,Sets edge detect interrupt for IO pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EDGE0,Sets edge detect interrupt for IO pin 0" "0,1"
|
|
group.long ($2+0x40)++0x13
|
|
line.long 0x0 "INTR_CFG,Port interrupt configuration register"
|
|
bitfld.long 0x0 18.--20. "FLT_SEL,Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--17. "FLT_EDGE_SEL,Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL" "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "EDGE7_SEL,Sets which edge will trigger an IRQ for IO pin 7" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "EDGE6_SEL,Sets which edge will trigger an IRQ for IO pin 6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "EDGE5_SEL,Sets which edge will trigger an IRQ for IO pin 5" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EDGE4_SEL,Sets which edge will trigger an IRQ for IO pin 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "EDGE3_SEL,Sets which edge will trigger an IRQ for IO pin 3" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "EDGE2_SEL,Sets which edge will trigger an IRQ for IO pin 2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "EDGE1_SEL,Sets which edge will trigger an IRQ for IO pin 1" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "EDGE0_SEL,Sets which edge will trigger an IRQ for IO pin 0" "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
|
|
line.long 0x4 "CFG,Port configuration register"
|
|
bitfld.long 0x4 31. "IN_EN7,Enables the input buffer for IO pin 7" "0,1"
|
|
bitfld.long 0x4 28.--30. "DRIVE_MODE7,The GPIO drive mode for IO pin 7" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 27. "IN_EN6,Enables the input buffer for IO pin 6" "0,1"
|
|
bitfld.long 0x4 24.--26. "DRIVE_MODE6,The GPIO drive mode for IO pin 6" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 23. "IN_EN5,Enables the input buffer for IO pin 5" "0,1"
|
|
bitfld.long 0x4 20.--22. "DRIVE_MODE5,The GPIO drive mode for IO pin 5" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 19. "IN_EN4,Enables the input buffer for IO pin 4" "0,1"
|
|
bitfld.long 0x4 16.--18. "DRIVE_MODE4,The GPIO drive mode for IO pin4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 15. "IN_EN3,Enables the input buffer for IO pin 3" "0,1"
|
|
bitfld.long 0x4 12.--14. "DRIVE_MODE3,The GPIO drive mode for IO pin 3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 11. "IN_EN2,Enables the input buffer for IO pin 2" "0,1"
|
|
bitfld.long 0x4 8.--10. "DRIVE_MODE2,The GPIO drive mode for IO pin 2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 7. "IN_EN1,Enables the input buffer for IO pin 1" "0,1"
|
|
bitfld.long 0x4 4.--6. "DRIVE_MODE1,The GPIO drive mode for IO pin 1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "IN_EN0,Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue." "0,1"
|
|
bitfld.long 0x4 0.--2. "DRIVE_MODE0,The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode." "0: Output buffer is off creating a high impedance..,1: N/A,2: Resistive pull up For GPIO & UDB/DSI..,3: Resistive pull down For GPIO & UDB/DSI..,4: Open drain drives low For GPIO & UDB/DSI..,5: Open drain drives high For GPIO & UDB/DSI..,6: Strong D_OUTput buffer For GPIO & UDB/DSI..,7: Pull up or pull down For GPIO & UDB/DSI.."
|
|
line.long 0x8 "CFG_IN,Port input buffer configuration register"
|
|
bitfld.long 0x8 7. "VTRIP_SEL7_0,Configures the pin 7 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 6. "VTRIP_SEL6_0,Configures the pin 6 input buffer mode (trip points and hysteresis)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "VTRIP_SEL5_0,Configures the pin 5 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 4. "VTRIP_SEL4_0,Configures the pin 4 input buffer mode (trip points and hysteresis)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "VTRIP_SEL3_0,Configures the pin 3 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 2. "VTRIP_SEL2_0,Configures the pin 2 input buffer mode (trip points and hysteresis)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "VTRIP_SEL1_0,Configures the pin 1 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 0. "VTRIP_SEL0_0,Configures the pin 0 input buffer mode (trip points and hysteresis)" "0: S40S: Input buffer compatible with CMOS and I2C..,1: S40S: Input buffer compatible with TTL and.."
|
|
line.long 0xC "CFG_OUT,Port output buffer configuration register"
|
|
bitfld.long 0xC 30.--31. "DRIVE_SEL7,Sets the GPIO drive strength for IO pin 7" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "DRIVE_SEL6,Sets the GPIO drive strength for IO pin 6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 26.--27. "DRIVE_SEL5,Sets the GPIO drive strength for IO pin 5" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "DRIVE_SEL4,Sets the GPIO drive strength for IO pin 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 22.--23. "DRIVE_SEL3,Sets the GPIO drive strength for IO pin 3" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "DRIVE_SEL2,Sets the GPIO drive strength for IO pin 2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 18.--19. "DRIVE_SEL1,Sets the GPIO drive strength for IO pin 1" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "DRIVE_SEL0,Sets the GPIO drive strength for IO pin 0" "0: S40E GPIO_STD/GPIO_ENH: Full drive strengh: GPIO..,1: S40E GPIO_STD/GPIO_ENH: Full drive strengh: GPIO..,2: S40E GPIO_STD/GPIO_ENH: 1/2 drive strength: GPIO..,3: S40E GPIO_STD/GPIO_ENH: 1/4 drive strength: GPIO.."
|
|
newline
|
|
bitfld.long 0xC 7. "SLOW7,Enables slow slew rate for IO pin 7" "0,1"
|
|
bitfld.long 0xC 6. "SLOW6,Enables slow slew rate for IO pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "SLOW5,Enables slow slew rate for IO pin 5" "0,1"
|
|
bitfld.long 0xC 4. "SLOW4,Enables slow slew rate for IO pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "SLOW3,Enables slow slew rate for IO pin 3" "0,1"
|
|
bitfld.long 0xC 2. "SLOW2,Enables slow slew rate for IO pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "SLOW1,Enables slow slew rate for IO pin 1" "0,1"
|
|
bitfld.long 0xC 0. "SLOW0,Enables slow slew rate for IO pin 0" "0,1"
|
|
line.long 0x10 "CFG_SIO,Port SIO configuration register"
|
|
bitfld.long 0x10 29.--31. "VOH_SEL67,See corresponding definition for IO pins 0 and 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 27.--28. "VREF_SEL67,See corresponding definition for IO pins 0 and 1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 26. "VTRIP_SEL67,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
bitfld.long 0x10 25. "IBUF_SEL67,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
newline
|
|
bitfld.long 0x10 24. "VREG_EN67,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
bitfld.long 0x10 21.--23. "VOH_SEL45,See corresponding definition for IO pins 0 and 1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 19.--20. "VREF_SEL45,See corresponding definition for IO pins 0 and 1" "0,1,2,3"
|
|
bitfld.long 0x10 18. "VTRIP_SEL45,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
newline
|
|
bitfld.long 0x10 17. "IBUF_SEL45,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
bitfld.long 0x10 16. "VREG_EN45,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13.--15. "VOH_SEL23,See corresponding definition for IO pins 0 and 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 11.--12. "VREF_SEL23,See corresponding definition for IO pins 0 and 1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 10. "VTRIP_SEL23,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
bitfld.long 0x10 9. "IBUF_SEL23,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "VREG_EN23,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
bitfld.long 0x10 5.--7. "VOH_SEL01,Selects the regulated Voh output level and trip point of the input buffer for a specific SIO pin pair. Voh depends on the selected reference voltage (VREF_SEL)." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 3.--4. "VREF_SEL01,Selects reference voltage (Vref) trip-point of the input buffer:" "0,1,2,3"
|
|
bitfld.long 0x10 2. "VTRIP_SEL01,Selects the input buffer trip-point in single ended input buffer mode (IBUF_SEL = '0'):" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "IBUF_SEL01,Selects the input buffer mode:" "0: Singled ended input buffer,1: Differential input buffer"
|
|
bitfld.long 0x10 0. "VREG_EN01,Selects the output buffer mode:" "0,1"
|
|
group.long ($2+0x58)++0x3
|
|
line.long 0x0 "CFG_IN_AUTOLVL,Port input buffer AUTOLVL configuration register"
|
|
bitfld.long 0x0 7. "VTRIP_SEL7_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 6. "VTRIP_SEL6_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "VTRIP_SEL5_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 4. "VTRIP_SEL4_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "VTRIP_SEL3_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 2. "VTRIP_SEL2_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "VTRIP_SEL1_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 0. "VTRIP_SEL0_1,Configures the input buffer mode (trip points and hysteresis) for GPIO upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. This field is used along with CFG_IN.VTRIP_SEL0_0 field as below:" "0: input buffer is compatible with automotive,1: input buffer is compatible with automotvie"
|
|
tree.end
|
|
repeat.end
|
|
repeat 8. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17)(list ad:0x40310800 ad:0x40310880 ad:0x40310900 ad:0x40310980 ad:0x40310A00 ad:0x40310A80 ad:0x40310B00 ad:0x40310B80)
|
|
tree "PRT[$1]"
|
|
base $2
|
|
group.long ($2)++0xF
|
|
line.long 0x0 "OUT,Port output data register"
|
|
bitfld.long 0x0 7. "OUT7,IO output data for pin 7" "0,1"
|
|
bitfld.long 0x0 6. "OUT6,IO output data for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OUT5,IO output data for pin 5" "0,1"
|
|
bitfld.long 0x0 4. "OUT4,IO output data for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OUT3,IO output data for pin 3" "0,1"
|
|
bitfld.long 0x0 2. "OUT2,IO output data for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OUT1,IO output data for pin 1" "0,1"
|
|
bitfld.long 0x0 0. "OUT0,IO output data for pin 0" "0,1"
|
|
line.long 0x4 "OUT_CLR,Port output data clear register"
|
|
bitfld.long 0x4 7. "OUT7,IO clear output for pin 7" "0,1"
|
|
bitfld.long 0x4 6. "OUT6,IO clear output for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OUT5,IO clear output for pin 5" "0,1"
|
|
bitfld.long 0x4 4. "OUT4,IO clear output for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OUT3,IO clear output for pin 3" "0,1"
|
|
bitfld.long 0x4 2. "OUT2,IO clear output for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "OUT1,IO clear output for pin 1" "0,1"
|
|
bitfld.long 0x4 0. "OUT0,IO clear output for pin 0:" "0,1"
|
|
line.long 0x8 "OUT_SET,Port output data set register"
|
|
bitfld.long 0x8 7. "OUT7,IO set output for pin 7" "0,1"
|
|
bitfld.long 0x8 6. "OUT6,IO set output for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OUT5,IO set output for pin 5" "0,1"
|
|
bitfld.long 0x8 4. "OUT4,IO set output for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "OUT3,IO set output for pin 3" "0,1"
|
|
bitfld.long 0x8 2. "OUT2,IO set output for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "OUT1,IO set output for pin 1" "0,1"
|
|
bitfld.long 0x8 0. "OUT0,IO set output for pin 0:" "0,1"
|
|
line.long 0xC "OUT_INV,Port output data invert register"
|
|
bitfld.long 0xC 7. "OUT7,IO invert output for pin 7" "0,1"
|
|
bitfld.long 0xC 6. "OUT6,IO invert output for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "OUT5,IO invert output for pin 5" "0,1"
|
|
bitfld.long 0xC 4. "OUT4,IO invert output for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "OUT3,IO invert output for pin 3" "0,1"
|
|
bitfld.long 0xC 2. "OUT2,IO invert output for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "OUT1,IO invert output for pin 1" "0,1"
|
|
bitfld.long 0xC 0. "OUT0,IO invert output for pin 0:" "0,1"
|
|
rgroup.long ($2+0x10)++0x3
|
|
line.long 0x0 "IN,Port input state register"
|
|
bitfld.long 0x0 8. "FLT_IN,Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register." "0,1"
|
|
bitfld.long 0x0 7. "IN7,IO pin state for pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "IN6,IO pin state for pin 6" "0,1"
|
|
bitfld.long 0x0 5. "IN5,IO pin state for pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IN4,IO pin state for pin 4" "0,1"
|
|
bitfld.long 0x0 3. "IN3,IO pin state for pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "IN2,IO pin state for pin 2" "0,1"
|
|
bitfld.long 0x0 1. "IN1,IO pin state for pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IN0,IO pin state for pin 0" "0,1"
|
|
group.long ($2+0x14)++0x7
|
|
line.long 0x0 "INTR,Port interrupt status register"
|
|
rbitfld.long 0x0 24. "FLT_IN_IN,Filtered pin state for pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
rbitfld.long 0x0 23. "IN_IN7,IO pin state for pin 7" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 22. "IN_IN6,IO pin state for pin 6" "0,1"
|
|
rbitfld.long 0x0 21. "IN_IN5,IO pin state for pin 5" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 20. "IN_IN4,IO pin state for pin 4" "0,1"
|
|
rbitfld.long 0x0 19. "IN_IN3,IO pin state for pin 3" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 18. "IN_IN2,IO pin state for pin 2" "0,1"
|
|
rbitfld.long 0x0 17. "IN_IN1,IO pin state for pin 1" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "IN_IN0,IO pin state for pin 0" "0,1"
|
|
bitfld.long 0x0 8. "FLT_EDGE,Edge detected on filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "EDGE7,Edge detect for IO pin 7" "0,1"
|
|
bitfld.long 0x0 6. "EDGE6,Edge detect for IO pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EDGE5,Edge detect for IO pin 5" "0,1"
|
|
bitfld.long 0x0 4. "EDGE4,Edge detect for IO pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EDGE3,Edge detect for IO pin 3" "0,1"
|
|
bitfld.long 0x0 2. "EDGE2,Edge detect for IO pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EDGE1,Edge detect for IO pin 1" "0,1"
|
|
bitfld.long 0x0 0. "EDGE0,Edge detect for IO pin 0" "0,1"
|
|
line.long 0x4 "INTR_MASK,Port interrupt mask register"
|
|
bitfld.long 0x4 8. "FLT_EDGE,Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
bitfld.long 0x4 7. "EDGE7,Masks edge interrupt on IO pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "EDGE6,Masks edge interrupt on IO pin 6" "0,1"
|
|
bitfld.long 0x4 5. "EDGE5,Masks edge interrupt on IO pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EDGE4,Masks edge interrupt on IO pin 4" "0,1"
|
|
bitfld.long 0x4 3. "EDGE3,Masks edge interrupt on IO pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "EDGE2,Masks edge interrupt on IO pin 2" "0,1"
|
|
bitfld.long 0x4 1. "EDGE1,Masks edge interrupt on IO pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "EDGE0,Masks edge interrupt on IO pin 0" "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Port interrupt masked status register"
|
|
bitfld.long 0x0 8. "FLT_EDGE,Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
bitfld.long 0x0 7. "EDGE7,Edge detected and masked on IO pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "EDGE6,Edge detected and masked on IO pin 6" "0,1"
|
|
bitfld.long 0x0 5. "EDGE5,Edge detected and masked on IO pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EDGE4,Edge detected and masked on IO pin 4" "0,1"
|
|
bitfld.long 0x0 3. "EDGE3,Edge detected and masked on IO pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EDGE2,Edge detected and masked on IO pin 2" "0,1"
|
|
bitfld.long 0x0 1. "EDGE1,Edge detected and masked on IO pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EDGE0,Edge detected AND masked on IO pin 0" "0,1"
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "INTR_SET,Port interrupt set register"
|
|
bitfld.long 0x0 8. "FLT_EDGE,Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
bitfld.long 0x0 7. "EDGE7,Sets edge detect interrupt for IO pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "EDGE6,Sets edge detect interrupt for IO pin 6" "0,1"
|
|
bitfld.long 0x0 5. "EDGE5,Sets edge detect interrupt for IO pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EDGE4,Sets edge detect interrupt for IO pin 4" "0,1"
|
|
bitfld.long 0x0 3. "EDGE3,Sets edge detect interrupt for IO pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EDGE2,Sets edge detect interrupt for IO pin 2" "0,1"
|
|
bitfld.long 0x0 1. "EDGE1,Sets edge detect interrupt for IO pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EDGE0,Sets edge detect interrupt for IO pin 0" "0,1"
|
|
group.long ($2+0x40)++0x13
|
|
line.long 0x0 "INTR_CFG,Port interrupt configuration register"
|
|
bitfld.long 0x0 18.--20. "FLT_SEL,Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--17. "FLT_EDGE_SEL,Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL" "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "EDGE7_SEL,Sets which edge will trigger an IRQ for IO pin 7" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "EDGE6_SEL,Sets which edge will trigger an IRQ for IO pin 6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "EDGE5_SEL,Sets which edge will trigger an IRQ for IO pin 5" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EDGE4_SEL,Sets which edge will trigger an IRQ for IO pin 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "EDGE3_SEL,Sets which edge will trigger an IRQ for IO pin 3" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "EDGE2_SEL,Sets which edge will trigger an IRQ for IO pin 2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "EDGE1_SEL,Sets which edge will trigger an IRQ for IO pin 1" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "EDGE0_SEL,Sets which edge will trigger an IRQ for IO pin 0" "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
|
|
line.long 0x4 "CFG,Port configuration register"
|
|
bitfld.long 0x4 31. "IN_EN7,Enables the input buffer for IO pin 7" "0,1"
|
|
bitfld.long 0x4 28.--30. "DRIVE_MODE7,The GPIO drive mode for IO pin 7" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 27. "IN_EN6,Enables the input buffer for IO pin 6" "0,1"
|
|
bitfld.long 0x4 24.--26. "DRIVE_MODE6,The GPIO drive mode for IO pin 6" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 23. "IN_EN5,Enables the input buffer for IO pin 5" "0,1"
|
|
bitfld.long 0x4 20.--22. "DRIVE_MODE5,The GPIO drive mode for IO pin 5" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 19. "IN_EN4,Enables the input buffer for IO pin 4" "0,1"
|
|
bitfld.long 0x4 16.--18. "DRIVE_MODE4,The GPIO drive mode for IO pin4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 15. "IN_EN3,Enables the input buffer for IO pin 3" "0,1"
|
|
bitfld.long 0x4 12.--14. "DRIVE_MODE3,The GPIO drive mode for IO pin 3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 11. "IN_EN2,Enables the input buffer for IO pin 2" "0,1"
|
|
bitfld.long 0x4 8.--10. "DRIVE_MODE2,The GPIO drive mode for IO pin 2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 7. "IN_EN1,Enables the input buffer for IO pin 1" "0,1"
|
|
bitfld.long 0x4 4.--6. "DRIVE_MODE1,The GPIO drive mode for IO pin 1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "IN_EN0,Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue." "0,1"
|
|
bitfld.long 0x4 0.--2. "DRIVE_MODE0,The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode." "0: Output buffer is off creating a high impedance..,1: N/A,2: Resistive pull up For GPIO & UDB/DSI..,3: Resistive pull down For GPIO & UDB/DSI..,4: Open drain drives low For GPIO & UDB/DSI..,5: Open drain drives high For GPIO & UDB/DSI..,6: Strong D_OUTput buffer For GPIO & UDB/DSI..,7: Pull up or pull down For GPIO & UDB/DSI.."
|
|
line.long 0x8 "CFG_IN,Port input buffer configuration register"
|
|
bitfld.long 0x8 7. "VTRIP_SEL7_0,Configures the pin 7 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 6. "VTRIP_SEL6_0,Configures the pin 6 input buffer mode (trip points and hysteresis)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "VTRIP_SEL5_0,Configures the pin 5 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 4. "VTRIP_SEL4_0,Configures the pin 4 input buffer mode (trip points and hysteresis)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "VTRIP_SEL3_0,Configures the pin 3 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 2. "VTRIP_SEL2_0,Configures the pin 2 input buffer mode (trip points and hysteresis)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "VTRIP_SEL1_0,Configures the pin 1 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 0. "VTRIP_SEL0_0,Configures the pin 0 input buffer mode (trip points and hysteresis)" "0: S40S: Input buffer compatible with CMOS and I2C..,1: S40S: Input buffer compatible with TTL and.."
|
|
line.long 0xC "CFG_OUT,Port output buffer configuration register"
|
|
bitfld.long 0xC 30.--31. "DRIVE_SEL7,Sets the GPIO drive strength for IO pin 7" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "DRIVE_SEL6,Sets the GPIO drive strength for IO pin 6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 26.--27. "DRIVE_SEL5,Sets the GPIO drive strength for IO pin 5" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "DRIVE_SEL4,Sets the GPIO drive strength for IO pin 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 22.--23. "DRIVE_SEL3,Sets the GPIO drive strength for IO pin 3" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "DRIVE_SEL2,Sets the GPIO drive strength for IO pin 2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 18.--19. "DRIVE_SEL1,Sets the GPIO drive strength for IO pin 1" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "DRIVE_SEL0,Sets the GPIO drive strength for IO pin 0" "0: S40E GPIO_STD/GPIO_ENH: Full drive strengh: GPIO..,1: S40E GPIO_STD/GPIO_ENH: Full drive strengh: GPIO..,2: S40E GPIO_STD/GPIO_ENH: 1/2 drive strength: GPIO..,3: S40E GPIO_STD/GPIO_ENH: 1/4 drive strength: GPIO.."
|
|
newline
|
|
bitfld.long 0xC 7. "SLOW7,Enables slow slew rate for IO pin 7" "0,1"
|
|
bitfld.long 0xC 6. "SLOW6,Enables slow slew rate for IO pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "SLOW5,Enables slow slew rate for IO pin 5" "0,1"
|
|
bitfld.long 0xC 4. "SLOW4,Enables slow slew rate for IO pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "SLOW3,Enables slow slew rate for IO pin 3" "0,1"
|
|
bitfld.long 0xC 2. "SLOW2,Enables slow slew rate for IO pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "SLOW1,Enables slow slew rate for IO pin 1" "0,1"
|
|
bitfld.long 0xC 0. "SLOW0,Enables slow slew rate for IO pin 0" "0,1"
|
|
line.long 0x10 "CFG_SIO,Port SIO configuration register"
|
|
bitfld.long 0x10 29.--31. "VOH_SEL67,See corresponding definition for IO pins 0 and 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 27.--28. "VREF_SEL67,See corresponding definition for IO pins 0 and 1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 26. "VTRIP_SEL67,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
bitfld.long 0x10 25. "IBUF_SEL67,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
newline
|
|
bitfld.long 0x10 24. "VREG_EN67,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
bitfld.long 0x10 21.--23. "VOH_SEL45,See corresponding definition for IO pins 0 and 1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 19.--20. "VREF_SEL45,See corresponding definition for IO pins 0 and 1" "0,1,2,3"
|
|
bitfld.long 0x10 18. "VTRIP_SEL45,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
newline
|
|
bitfld.long 0x10 17. "IBUF_SEL45,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
bitfld.long 0x10 16. "VREG_EN45,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13.--15. "VOH_SEL23,See corresponding definition for IO pins 0 and 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 11.--12. "VREF_SEL23,See corresponding definition for IO pins 0 and 1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 10. "VTRIP_SEL23,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
bitfld.long 0x10 9. "IBUF_SEL23,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "VREG_EN23,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
bitfld.long 0x10 5.--7. "VOH_SEL01,Selects the regulated Voh output level and trip point of the input buffer for a specific SIO pin pair. Voh depends on the selected reference voltage (VREF_SEL)." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 3.--4. "VREF_SEL01,Selects reference voltage (Vref) trip-point of the input buffer:" "0,1,2,3"
|
|
bitfld.long 0x10 2. "VTRIP_SEL01,Selects the input buffer trip-point in single ended input buffer mode (IBUF_SEL = '0'):" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "IBUF_SEL01,Selects the input buffer mode:" "0: Singled ended input buffer,1: Differential input buffer"
|
|
bitfld.long 0x10 0. "VREG_EN01,Selects the output buffer mode:" "0,1"
|
|
group.long ($2+0x58)++0x3
|
|
line.long 0x0 "CFG_IN_AUTOLVL,Port input buffer AUTOLVL configuration register"
|
|
bitfld.long 0x0 7. "VTRIP_SEL7_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 6. "VTRIP_SEL6_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "VTRIP_SEL5_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 4. "VTRIP_SEL4_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "VTRIP_SEL3_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 2. "VTRIP_SEL2_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "VTRIP_SEL1_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 0. "VTRIP_SEL0_1,Configures the input buffer mode (trip points and hysteresis) for GPIO upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. This field is used along with CFG_IN.VTRIP_SEL0_0 field as below:" "0: input buffer is compatible with automotive,1: input buffer is compatible with automotvie"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40310000
|
|
rgroup.long 0x4000++0x13
|
|
line.long 0x0 "INTR_CAUSE0,Interrupt port cause register 0"
|
|
hexmask.long 0x0 0.--31. 1. "PORT_INT,Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line.."
|
|
line.long 0x4 "INTR_CAUSE1,Interrupt port cause register 1"
|
|
hexmask.long 0x4 0.--31. 1. "PORT_INT,Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line.."
|
|
line.long 0x8 "INTR_CAUSE2,Interrupt port cause register 2"
|
|
hexmask.long 0x8 0.--31. 1. "PORT_INT,Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line.."
|
|
line.long 0xC "INTR_CAUSE3,Interrupt port cause register 3"
|
|
hexmask.long 0xC 0.--31. 1. "PORT_INT,Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line.."
|
|
line.long 0x10 "VDD_ACTIVE,Extern power supply detection register"
|
|
bitfld.long 0x10 31. "VDDD_ACTIVE,This bit indicates presence of the VDDD supply. This bit will always read-back 1. The VDDD supply has robust brown-out protection monitoring and it is not possible to read back this register without a valid supply. (This bit is used in.." "0,1"
|
|
bitfld.long 0x10 30. "VDDA_ACTIVE,Same as VDDIO_ACTIVE for the analog supply VDDA." "0,1"
|
|
hexmask.long.word 0x10 0.--15. 1. "VDDIO_ACTIVE,Indicates presence or absence of VDDIO supplies (i.e. other than VDDD VDDA) on the device (supplies are numbered 0..n-1). Note that VDDIO supplies have basic (crude) supply detectors only. If separate robust brown-out detection is.."
|
|
group.long 0x4014++0x7
|
|
line.long 0x0 "VDD_INTR,Supply detection interrupt register"
|
|
bitfld.long 0x0 31. "VDDD_ACTIVE,The VDDD supply is always present during operation so a supply transition can not occur. This bit will always read back '1'." "0,1"
|
|
bitfld.long 0x0 30. "VDDA_ACTIVE,Same as VDDIO_ACTIVE for the analog supply VDDA." "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "VDDIO_ACTIVE,Supply state change detected."
|
|
line.long 0x4 "VDD_INTR_MASK,Supply detection interrupt mask register"
|
|
bitfld.long 0x4 31. "VDDD_ACTIVE,Same as VDDIO_ACTIVE for the digital supply VDDD." "0,1"
|
|
bitfld.long 0x4 30. "VDDA_ACTIVE,Same as VDDIO_ACTIVE for the analog supply VDDA." "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "VDDIO_ACTIVE,Masks supply interrupt on VDDIO."
|
|
rgroup.long 0x401C++0x3
|
|
line.long 0x0 "VDD_INTR_MASKED,Supply detection interrupt masked register"
|
|
bitfld.long 0x0 31. "VDDD_ACTIVE,Same as VDDIO_ACTIVE for the digital supply VDDD." "0,1"
|
|
bitfld.long 0x0 30. "VDDA_ACTIVE,Same as VDDIO_ACTIVE for the analog supply VDDA." "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "VDDIO_ACTIVE,Supply transition detected AND masked"
|
|
group.long 0x4020++0x3
|
|
line.long 0x0 "VDD_INTR_SET,Supply detection interrupt set register"
|
|
bitfld.long 0x0 31. "VDDD_ACTIVE,Same as VDDIO_ACTIVE for the digital supply VDDD." "0,1"
|
|
bitfld.long 0x0 30. "VDDA_ACTIVE,Same as VDDIO_ACTIVE for the analog supply VDDA." "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "VDDIO_ACTIVE,Sets supply interrupt."
|
|
tree.end
|
|
tree "HSIOM (High Speed IO Matrix)"
|
|
base ad:0x40300000
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40300000 ad:0x40300010 ad:0x40300020 ad:0x40300030 ad:0x40300040 ad:0x40300050 ad:0x40300060 ad:0x40300070 ad:0x40300080 ad:0x40300090 ad:0x403000A0 ad:0x403000B0 ad:0x403000C0 ad:0x403000D0 ad:0x403000E0 ad:0x403000F0)
|
|
tree "PRT[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "PORT_SEL0,Port selection 0"
|
|
hexmask.long.byte 0x0 24.--28. 1. "IO3_SEL,Selects connection for IO pin 3 route."
|
|
hexmask.long.byte 0x0 16.--20. 1. "IO2_SEL,Selects connection for IO pin 2 route."
|
|
hexmask.long.byte 0x0 8.--12. 1. "IO1_SEL,Selects connection for IO pin 1 route."
|
|
hexmask.long.byte 0x0 0.--4. 1. "IO0_SEL,Selects connection for IO pin 0 route."
|
|
line.long 0x4 "PORT_SEL1,Port selection 1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "IO7_SEL,Selects connection for IO pin 7 route."
|
|
hexmask.long.byte 0x4 16.--20. 1. "IO6_SEL,Selects connection for IO pin 6 route."
|
|
hexmask.long.byte 0x4 8.--12. 1. "IO5_SEL,Selects connection for IO pin 5 route."
|
|
hexmask.long.byte 0x4 0.--4. 1. "IO4_SEL,Selects connection for IO pin 4 route."
|
|
tree.end
|
|
repeat.end
|
|
repeat 8. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17)(list ad:0x40300100 ad:0x40300110 ad:0x40300120 ad:0x40300130 ad:0x40300140 ad:0x40300150 ad:0x40300160 ad:0x40300170)
|
|
tree "PRT[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "PORT_SEL0,Port selection 0"
|
|
hexmask.long.byte 0x0 24.--28. 1. "IO3_SEL,Selects connection for IO pin 3 route."
|
|
hexmask.long.byte 0x0 16.--20. 1. "IO2_SEL,Selects connection for IO pin 2 route."
|
|
hexmask.long.byte 0x0 8.--12. 1. "IO1_SEL,Selects connection for IO pin 1 route."
|
|
hexmask.long.byte 0x0 0.--4. 1. "IO0_SEL,Selects connection for IO pin 0 route."
|
|
line.long 0x4 "PORT_SEL1,Port selection 1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "IO7_SEL,Selects connection for IO pin 7 route."
|
|
hexmask.long.byte 0x4 16.--20. 1. "IO6_SEL,Selects connection for IO pin 6 route."
|
|
hexmask.long.byte 0x4 8.--12. 1. "IO5_SEL,Selects connection for IO pin 5 route."
|
|
hexmask.long.byte 0x4 0.--4. 1. "IO4_SEL,Selects connection for IO pin 4 route."
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40300000
|
|
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x2000)++0x3
|
|
line.long 0x0 "AMUX_SPLIT_CTL[$1],AMUX splitter cell control"
|
|
bitfld.long 0x0 6. "SWITCH_BB_S0,T-switch control for AMUXBUSB vssa/ground switch." "0,1"
|
|
bitfld.long 0x0 5. "SWITCH_BB_SR,T-switch control for Right AMUXBUSB switch." "0,1"
|
|
bitfld.long 0x0 4. "SWITCH_BB_SL,T-switch control for Left AMUXBUSB switch." "0,1"
|
|
bitfld.long 0x0 2. "SWITCH_AA_S0,T-switch control for AMUXBUSA vssa/ground switch:" "0,1"
|
|
bitfld.long 0x0 1. "SWITCH_AA_SR,T-switch control for Right AMUXBUSA switch:" "0,1"
|
|
bitfld.long 0x0 0. "SWITCH_AA_SL,T-switch control for Left AMUXBUSA switch:" "0,1"
|
|
repeat.end
|
|
group.long 0x2200++0xF
|
|
line.long 0x0 "MONITOR_CTL_0,Power/Ground Monitor cell control 0"
|
|
hexmask.long 0x0 0.--31. 1. "MONITOR_EN,control for switch which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:"
|
|
line.long 0x4 "MONITOR_CTL_1,Power/Ground Monitor cell control 1"
|
|
hexmask.long 0x4 0.--31. 1. "MONITOR_EN,control for switch which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:"
|
|
line.long 0x8 "MONITOR_CTL_2,Power/Ground Monitor cell control 2"
|
|
hexmask.long 0x8 0.--31. 1. "MONITOR_EN,control for switch which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:"
|
|
line.long 0xC "MONITOR_CTL_3,Power/Ground Monitor cell control 3"
|
|
hexmask.long 0xC 0.--31. 1. "MONITOR_EN,control for switch which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:"
|
|
group.long 0x2240++0x3
|
|
line.long 0x0 "ALT_JTAG_EN,Alternate JTAG IF selection register"
|
|
bitfld.long 0x0 31. "ENABLE,Provides the selection for alternate JTAG IF connectivity." "0: Primary JTAG interface is selected,1: Secondary"
|
|
tree.end
|
|
tree "IPC (Interprocessor Communication)"
|
|
base ad:0x40220000
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x40220000 ad:0x40220020 ad:0x40220040 ad:0x40220060 ad:0x40220080 ad:0x402200A0 ad:0x402200C0 ad:0x402200E0)
|
|
tree "STRUCT[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "ACQUIRE,IPC acquire"
|
|
bitfld.long 0x0 31. "SUCCESS,Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED):" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MS,This field specifies the bus master identifier that successfully acquired the lock."
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,This field specifies the protection context that successfully acquired the lock."
|
|
bitfld.long 0x0 1. "NS,Secure/non-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
wgroup.long ($2+0x4)++0x7
|
|
line.long 0x0 "RELEASE,IPC release"
|
|
hexmask.long.word 0x0 0.--15. 1. "INTR_RELEASE,Writing this field releases a lock and allows for the generation of release events to the IPC interrupt structures but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC.."
|
|
line.long 0x4 "NOTIFY,IPC notification"
|
|
hexmask.long.word 0x4 0.--15. 1. "INTR_NOTIFY,This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1' but only for those IPC interrupt structures for which the.."
|
|
group.long ($2+0xC)++0x7
|
|
line.long 0x0 "DATA0,IPC data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,This field holds a 32-bit data element that is associated with the IPC structure."
|
|
line.long 0x4 "DATA1,IPC data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,This field holds a 32-bit data element that is associated with the IPC structure."
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "LOCK_STATUS,IPC lock status"
|
|
bitfld.long 0x0 31. "ACQUIRED,Specifies if the lock is acquired. This field is set to '1' if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1'). If zero P NS PC and MS are not valid." "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MS,This field specifies the bus master identifier that successfully acquired the lock."
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,This field specifies the protection context that successfully acquired the lock."
|
|
bitfld.long 0x0 1. "NS,This field specifies the secure/non-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,This field specifies the user/privileged access control:" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x40221000 ad:0x40221020 ad:0x40221040 ad:0x40221060 ad:0x40221080 ad:0x402210A0 ad:0x402210C0 ad:0x402210E0)
|
|
tree "INTR_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0xB
|
|
line.long 0x0 "INTR,Interrupt"
|
|
hexmask.long.word 0x0 16.--31. 1. "NOTIFY,These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause."
|
|
hexmask.long.word 0x0 0.--15. 1. "RELEASE,These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause."
|
|
line.long 0x4 "INTR_SET,Interrupt set"
|
|
hexmask.long.word 0x4 16.--31. 1. "NOTIFY,SW writes a '1' to this field to set the corresponding field in the INTR register."
|
|
hexmask.long.word 0x4 0.--15. 1. "RELEASE,SW writes a '1' to this field to set the corresponding field in the INTR register."
|
|
line.long 0x8 "INTR_MASK,Interrupt mask"
|
|
hexmask.long.word 0x8 16.--31. 1. "NOTIFY,Mask bit for corresponding field in the INTR register."
|
|
hexmask.long.word 0x8 0.--15. 1. "RELEASE,Mask bit for corresponding field in the INTR register."
|
|
rgroup.long ($2+0xC)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
hexmask.long.word 0x0 16.--31. 1. "NOTIFY,Logical and of corresponding INTR and INTR_MASK fields."
|
|
hexmask.long.word 0x0 0.--15. 1. "RELEASE,Logical and of corresponding request and mask bits."
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "LIN"
|
|
base ad:0x40500000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "ERROR_CTL,Error control"
|
|
bitfld.long 0x0 31. "ENABLED,Error injection enable:" "0,1"
|
|
bitfld.long 0x0 23. "TX_CHECKSUM_STOP_ERROR,The checksum field STOP bits are inverted to '0'." "0,1"
|
|
bitfld.long 0x0 22. "TX_CHECKSUM_ERROR,The checksum field is inverted." "0,1"
|
|
bitfld.long 0x0 21. "TX_DATA_STOP_ERROR,The data field STOP bits are inverted to '0'." "0,1"
|
|
bitfld.long 0x0 19. "TX_PID_STOP_ERROR,The PID field STOP bits are inverted to '0'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TX_PARITY_ERROR,In LIN mode the PID parity bit P[1] is inverted from !(ID[5] ^ ID[4] ^ ID[3] ^ ID[1]) to (ID[5] ^ ID[4] ^ ID[3] ^ ID[1])." "0,1"
|
|
bitfld.long 0x0 17. "TX_SYNC_STOP_ERROR,The synchronization field STOP bits are inverted to '0'." "0,1"
|
|
bitfld.long 0x0 16. "TX_SYNC_ERROR,The synchronization field is changed from 0x55 to 0x00." "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "CH_IDX,Specifies the channel index of the channel to which HW injected channel transmitter errors applies."
|
|
line.long 0x4 "TEST_CTL,Test control"
|
|
bitfld.long 0x4 31. "ENABLED,Test enable:" "0,1"
|
|
bitfld.long 0x4 16. "MODE,Test mode:" "0,1"
|
|
hexmask.long.byte 0x4 0.--4. 1. "CH_IDX,Specifies the channel index of the channel to which test applies. The channel IO signals of channel indices CH_IDX and CH_NR-1 are connected as specified by MODE. CH_IDX should be in the range [0 CH_NR-2] as channel index CH_NR-1 is always.."
|
|
repeat 12. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB)(list ad:0x40508000 ad:0x40508100 ad:0x40508200 ad:0x40508300 ad:0x40508400 ad:0x40508500 ad:0x40508600 ad:0x40508700 ad:0x40508800 ad:0x40508900 ad:0x40508A00 ad:0x40508B00)
|
|
tree "CH[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "CTL0,Control 0"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 30. "FILTER_EN,RX filter (for 'lin_rx_in'):" "0,1"
|
|
bitfld.long 0x0 29. "PARITY_EN,Parity generation enable:" "0,1"
|
|
bitfld.long 0x0 28. "PARITY,Parity mode:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "BIT_ERROR_IGNORE,Specifies behavior on a detected bit error during header or response transmission:" "0,1"
|
|
bitfld.long 0x0 24. "MODE,Mode of operation:" "0: LIN mode.,1: UART mode."
|
|
hexmask.long.byte 0x0 16.--20. 1. "BREAK_WAKEUP_LENGTH,Break/wakeup length (minus 1) in bit periods:"
|
|
bitfld.long 0x0 8.--9. "BREAK_DELIMITER_LENGTH,In LIN mode this field specifies the break delimiter length:" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 4. "AUTO_EN,LIN transceiver auto enable:" "0,1"
|
|
bitfld.long 0x0 0.--1. "STOP_BITS,STOP bit periods:" "0,1,2,3"
|
|
line.long 0x4 "CTL1,Control 1"
|
|
bitfld.long 0x4 24.--25. "FRAME_TIMEOUT_SEL,Specifies the frame timeout mode:" "0,1,2,3"
|
|
hexmask.long.byte 0x4 16.--23. 1. "FRAME_TIMEOUT,Specifies the maximum allowed length (timeout value) for a frame frame header or frame response in bit periods. The LIN specification prescribes to set the maximum length to 1.4x the nominal length (Theader_max = 1.4 x Theader_nom and.."
|
|
bitfld.long 0x4 8. "CHECKSUM_ENHANCED,Checksum mode:" "0,1"
|
|
bitfld.long 0x4 0.--2. "DATA_NR,Number of data fields (minus 1) in the response (not including the checksum):" "0,1,2,3,4,5,6,7"
|
|
rgroup.long ($2+0x8)++0x3
|
|
line.long 0x0 "STATUS,Status"
|
|
bitfld.long 0x0 28. "RX_RESPONSE_CHECKSUM_ERROR,Copy of INTR.RX_RESPONSE_CHECKSUM_ERROR." "0,1"
|
|
bitfld.long 0x0 27. "RX_RESPONSE_FRAME_ERROR,Copy of INTR.RX_RESPONSE_FRAME_ERROR." "0,1"
|
|
bitfld.long 0x0 26. "RX_HEADER_PARITY_ERROR,Copy of INTR.RX_HEADER_PARITY_ERROR." "0,1"
|
|
bitfld.long 0x0 25. "RX_HEADER_SYNC_ERROR,Copy of INTR.RX_HEADER_SYNC_ERROR." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "RX_HEADER_FRAME_ERROR,Copy of INTR.RX_HEADER_FRAME_ERROR." "0,1"
|
|
bitfld.long 0x0 17. "TX_RESPONSE_BIT_ERROR,Copy of INTR.TX_RESPONSE_BIT_ERROR." "0,1"
|
|
bitfld.long 0x0 16. "TX_HEADER_BIT_ERROR,Copy of INTR.TX_HEADER_BIT_ERROR." "0,1"
|
|
bitfld.long 0x0 13. "RX_DONE,Receiver done:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "TX_DONE,Transmitter done:" "0,1"
|
|
bitfld.long 0x0 9. "RX_BUSY,Receiver busy." "0,1"
|
|
bitfld.long 0x0 8. "TX_BUSY,Transmitter busy." "0,1"
|
|
bitfld.long 0x0 5. "RX_DATA0_FRAME_ERROR,Frame response first data field frame error. HW sets this field to '1' when the received STOP bits of the first response data field have an unexpected value (only after a RX_HEADER command) and this data byte is 0x00. HW clears.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "HEADER_RESPONSE,Frame header / response identifier (only valid when TX_BUSY or RX_BUSY is '1'):" "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DATA_IDX,Number of transferred data and checksum fields in the response (also acts as an index/address into response data field and checksum field registers (DATA0 DATA1 PID_CHECKSUM)) :"
|
|
group.long ($2+0x10)++0x3
|
|
line.long 0x0 "CMD,Command"
|
|
bitfld.long 0x0 9. "RX_RESPONSE,SW sets this field to '1' to receive a response. HW sets this field to '0' on successful completion of ANY of the legal command sequences (NOT set to '0' when an error is detected)." "0,1"
|
|
bitfld.long 0x0 8. "RX_HEADER,SW sets this field to '1' to receive a header. HW sets this field to '0' on successful completion of the ANY of the legal command sequences (NOT set to '0' when an error is detected in LIN mode)." "0,1"
|
|
bitfld.long 0x0 2. "TX_WAKEUP,SW sets this field to '1' to transmit a wakeup signal. HW sets this field to '0' on successful completion of ANY of the legal command sequences (also set to '0' when an error is detected)." "0,1"
|
|
bitfld.long 0x0 1. "TX_RESPONSE,SW sets this field to '1' to transmit a response. HW sets this field to '0' on successful completion of ANY of the legal command sequences (also set to '0' when an error is detected)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TX_HEADER,SW sets this field to '1' to transmit a header. HW sets this field to '0' on successful completion of ANY of the following legal command sequences (also set to '0' when an error is detected):" "0,1"
|
|
group.long ($2+0x60)++0x3
|
|
line.long 0x0 "TX_RX_STATUS,TX/RX status"
|
|
bitfld.long 0x0 26. "EN_OUT,LIN transceiver enable ('en_out' 'lin_en_out'). This field controls the enable (or low active sleep enable) of the external transceiver:" "0,1"
|
|
rbitfld.long 0x0 24. "TX_OUT,LIN transmitter output ('tx_out' 'lin_tx_out')." "0,1"
|
|
rbitfld.long 0x0 17. "RX_IN,LIN receiver input ('rx_in' 'lin_rx_in' in functional mode)." "0,1"
|
|
rbitfld.long 0x0 16. "TX_IN,LIN transmitter input ('tx_in' 'lin_tx_in' in functional mode). TX_IN and RX_IN can be used to determine a wakeup source. Note that wakeup source detection relies on the external transceiver functionality." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "SYNC_COUNTER,Synchronization counter in LIN channel clock periods. After the receipt of a synchronization field this fields reflects the duration of the synchronization field. Ideally SYNC_COUNTER = 8*16 = 128 (the synchronization fields consists of.."
|
|
group.long ($2+0x80)++0xB
|
|
line.long 0x0 "PID_CHECKSUM,PID and checksum"
|
|
hexmask.long.byte 0x0 8.--15. 1. "CHECKSUM,Checksum."
|
|
hexmask.long.byte 0x0 0.--7. 1. "PID,Header protected identifier (PID)."
|
|
line.long 0x4 "DATA0,Response data 0"
|
|
hexmask.long.byte 0x4 24.--31. 1. "DATA4,Data field 4."
|
|
hexmask.long.byte 0x4 16.--23. 1. "DATA3,Data field 3."
|
|
hexmask.long.byte 0x4 8.--15. 1. "DATA2,Data field 2."
|
|
hexmask.long.byte 0x4 0.--7. 1. "DATA1,Data field 1."
|
|
line.long 0x8 "DATA1,Response data 1"
|
|
hexmask.long.byte 0x8 24.--31. 1. "DATA8,Data field 8."
|
|
hexmask.long.byte 0x8 16.--23. 1. "DATA7,Data field 7."
|
|
hexmask.long.byte 0x8 8.--15. 1. "DATA6,Data field 6."
|
|
hexmask.long.byte 0x8 0.--7. 1. "DATA5,Data field 5."
|
|
group.long ($2+0xC0)++0xB
|
|
line.long 0x0 "INTR,Interrupt"
|
|
bitfld.long 0x0 28. "RX_RESPONSE_CHECKSUM_ERROR,HW sets this field to '1' when the calculated checksum over the received PID and data fields is not the same as the received checksum." "0,1"
|
|
bitfld.long 0x0 27. "RX_RESPONSE_FRAME_ERROR,HW sets this field to '1' when the received START or STOP bits have an unexpected value (during response reception). HW does NOT use this field for the STOP bits of the first data field after a RX_HEADER command if the received.." "0,1"
|
|
bitfld.long 0x0 26. "RX_HEADER_PARITY_ERROR,HW sets this field to '1' when the received PID field has a parity error." "0,1"
|
|
bitfld.long 0x0 25. "RX_HEADER_SYNC_ERROR,HW sets this field to '1' when the received synchronization field is not received within the synchronization counter range [106 152] (see TX_RX_STATUS.SYNC_COUNTER)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "RX_HEADER_FRAME_ERROR,HW sets this field to '1' when the received START or STOP bits have an unexpected value (during header reception)." "0,1"
|
|
bitfld.long 0x0 17. "TX_RESPONSE_BIT_ERROR,HW sets this field to '1' when a transmitted 'lin_tx_out' value does NOT match a received 'lin_rx_in' value (during response transmission)." "0,1"
|
|
bitfld.long 0x0 16. "TX_HEADER_BIT_ERROR,HW sets this field to '1' when a transmitted 'lin_tx_out' value does NOT match a received 'lin_rx_in' value (during header transmission). This specific test allows for delay through the external transceiver. This mismatch is an.." "0,1"
|
|
bitfld.long 0x0 14. "TIMEOUT,HW sets this field to '1' when a frame frame header or frame response timeout is detected (per CTL.FRAME_TIMEOUT_SEL)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RX_NOISE_DETECT,HW sets this field to '1' when isolated '0' or '1' 'in_rx_in' values are observed or when during sampling the last three 'lin_rx_in' values do NOT all have the same value. This mismatch is an indication of noise on the LIN line." "0,1"
|
|
bitfld.long 0x0 11. "RX_HEADER_SYNC_DONE,HW sets this field to '1' when a synchronization field is received (including trailing STOP bits)." "0,1"
|
|
bitfld.long 0x0 10. "RX_BREAK_WAKEUP_DONE,HW sets this field to '1' when a break or wakeup signal is received (per CTL.BREAK_WAKEUP_LENGTH). This cause is activated on a transition from dominant/'0' state to recessive/'1' state; i.e. at the end of the wakeup signal." "0,1"
|
|
bitfld.long 0x0 9. "RX_RESPONSE_DONE,HW sets this field to '1' when a frame response (data fields and checksum field) is received (the CMD.RX_RESPONSE is completed). If CTL.AUTO_EN is '1' this includes the 4-bit period external transceiver disable post-amble." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RX_HEADER_DONE,HW sets this field to '1' when a frame header (break field synchronization field and PID field) is received (the CMD.RX_HEADER is completed). Specifically:" "0,1"
|
|
bitfld.long 0x0 2. "TX_WAKEUP_DONE,HW sets this field to '1' when a wakeup signal is transmitted (per CTL.BREAK_WAKEUP_LENGTH). This cause is activated on a transition from dominant/'0' state to recessive/'1' state; i.e. at the end of the wakeup signal." "0,1"
|
|
bitfld.long 0x0 1. "TX_RESPONSE_DONE,HW sets this field to '1' when a frame response (data fields and checksum field) is transmitted (the CMD.TX_RESPONSE is completed). If CTL.AUTO_EN is '1' this includes the 4-bit period external transceiver disable post-amble." "0,1"
|
|
bitfld.long 0x0 0. "TX_HEADER_DONE,HW sets this field to '1' when a frame header (break field synchronization field and PID field) is transmitted (the CMD.TX_HEADER is completed). Specifically:" "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set"
|
|
bitfld.long 0x4 28. "RX_RESPONSE_CHECKSUM_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 27. "RX_RESPONSE_FRAME_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 26. "RX_HEADER_PARITY_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 25. "RX_HEADER_SYNC_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "RX_HEADER_FRAME_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 17. "TX_RESPONSE_BIT_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 16. "TX_HEADER_BIT_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 14. "TIMEOUT,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "RX_NOISE_DETECT,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 11. "RX_HEADER_SYNC_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 10. "RX_BREAK_WAKEUP_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 9. "RX_RESPONSE_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "RX_HEADER_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 2. "TX_WAKEUP_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 1. "TX_RESPONSE_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 0. "TX_HEADER_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x8 28. "RX_RESPONSE_CHECKSUM_ERROR,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 27. "RX_RESPONSE_FRAME_ERROR,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 26. "RX_HEADER_PARITY_ERROR,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 25. "RX_HEADER_SYNC_ERROR,Mask for corresponding field in INTR register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 24. "RX_HEADER_FRAME_ERROR,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 17. "TX_RESPONSE_BIT_ERROR,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 16. "TX_HEADER_BIT_ERROR,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 14. "TIMEOUT,Mask for corresponding field in INTR register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "RX_NOISE_DETECT,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 11. "RX_HEADER_SYNC_DONE,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 10. "RX_BREAK_WAKEUP_DONE,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 9. "RX_RESPONSE_DONE,Mask for corresponding field in INTR register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "RX_HEADER_DONE,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 2. "TX_WAKEUP_DONE,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 1. "TX_RESPONSE_DONE,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 0. "TX_HEADER_DONE,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0xCC)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 28. "RX_RESPONSE_CHECKSUM_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 27. "RX_RESPONSE_FRAME_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 26. "RX_HEADER_PARITY_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 25. "RX_HEADER_SYNC_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "RX_HEADER_FRAME_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 17. "TX_RESPONSE_BIT_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 16. "TX_HEADER_BIT_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 14. "TIMEOUT,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RX_NOISE_DETECT,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 11. "RX_HEADER_SYNC_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 10. "RX_BREAK_WAKEUP_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 9. "RX_RESPONSE_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RX_HEADER_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 2. "TX_WAKEUP_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 1. "TX_RESPONSE_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 0. "TX_HEADER_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "PASS (Programmable Analog Subsystem for S40E)"
|
|
base ad:0x40900000
|
|
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40900000 ad:0x40901000 ad:0x40902000)
|
|
tree "SAR[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "CTL,Analog control register."
|
|
bitfld.long 0x0 31. "ENABLED,- 0: SAR IP disabled (put analog in power down and stop clocks) also clears all pending triggers." "0: SAR IP disabled,1: SAR IP enabled"
|
|
bitfld.long 0x0 30. "ADC_EN,Enable the SAR ADC and SAR sequencer (only valid if ENABLED=1)" "0: SARADC and SARSEQ are disabled,1: SAR ADC and SARSEQ are enabled"
|
|
newline
|
|
bitfld.long 0x0 29. "SARMUX_EN,Enable the SARMUX (only valid if ENABLED=1)" "0: SARMUX disabled,1: SARMUX enabled"
|
|
bitfld.long 0x0 10. "HALF_LSB,When set take an extra cycle to convert the half LSB and add it to 12-bit result for Missing Code Recovery" "0: disable half LSB conversion,1: enable half LSB conversion"
|
|
newline
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|
bitfld.long 0x0 9. "MSB_STRETCH,When set use 2 cycles for the Most Significant Bit (MSB)" "0: Use 1 clock cycle for MSB,1: Use 2 clock cycles for MSB"
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|
bitfld.long 0x0 8. "IDLE_PWRDWN,When idle automatically power down the analog." "0,1"
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|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "PWRUP_TIME,Number cycles to wait to power up after IDLE_PWRDWN."
|
|
line.long 0x4 "DIAG_CTL,Diagnostic Reference control register."
|
|
bitfld.long 0x4 31. "DIAG_EN,Diagnostic Reference enable (only valid if ENABLED=1)" "0: Diagnostic Reference disabled,1: Diagnostic Reference enabled"
|
|
hexmask.long.byte 0x4 0.--3. 1. "DIAG_SEL,Select Diagnostic Reference function"
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|
group.long ($2+0x10)++0x3
|
|
line.long 0x0 "PRECOND_CTL,Preconditioning control register."
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|
hexmask.long.byte 0x0 0.--3. 1. "PRECOND_TIME,Number ADC clock cycles that Preconditioning is done before the sample window starts. If OVERLAP_EN=0 there will be 1 additional break before make cycle between preconditioning and sampling."
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|
group.long ($2+0x80)++0x7
|
|
line.long 0x0 "ANA_CAL,Current analog calibration values"
|
|
hexmask.long.byte 0x0 16.--20. 1. "AGAIN,Analog gain correction"
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hexmask.long.byte 0x0 0.--7. 1. "AOFFSET,Analog offset correction"
|
|
line.long 0x4 "DIG_CAL,Current digital calibration values"
|
|
hexmask.long.byte 0x4 16.--21. 1. "DGAIN,Digital gain correction."
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|
hexmask.long.word 0x4 0.--11. 1. "DOFFSET,Digital offset correction"
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|
group.long ($2+0x90)++0xB
|
|
line.long 0x0 "ANA_CAL_ALT,Alternate analog calibration values"
|
|
hexmask.long.byte 0x0 16.--20. 1. "AGAIN,See corresponding ANA_CAL field"
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|
hexmask.long.byte 0x0 0.--7. 1. "AOFFSET,See corresponding ANA_CAL field"
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|
line.long 0x4 "DIG_CAL_ALT,Alternate digital calibration values"
|
|
hexmask.long.byte 0x4 16.--21. 1. "DGAIN,See corresponding DIG_CAL field"
|
|
hexmask.long.word 0x4 0.--11. 1. "DOFFSET,See corresponding DIG_CAL field"
|
|
line.long 0x8 "CAL_UPD_CMD,Calibration update command"
|
|
bitfld.long 0x8 0. "UPDATE,Calibration update command: coherently copy values from alternate calibration regs to current calibration regs." "0,1"
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|
rgroup.long ($2+0x100)++0x3
|
|
line.long 0x0 "TR_PEND,Trigger pending status"
|
|
hexmask.long 0x0 0.--31. 1. "TR_PEND,Trigger Pending."
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|
rgroup.long ($2+0x180)++0xF
|
|
line.long 0x0 "WORK_VALID,Channel working data register 'valid' bits"
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|
hexmask.long 0x0 0.--31. 1. "WORK_VALID,If set the corresponding WORK register is valid i.e. was already acquired during the current group scan. If this bit is low then either the channel is not enabled not yet acquired or it is used as a pulse detect channel."
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|
line.long 0x4 "WORK_RANGE,Range detected"
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hexmask.long 0x4 0.--31. 1. "RANGE,N/A"
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|
line.long 0x8 "WORK_RANGE_HI,Range detect above Hi flag"
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hexmask.long 0x8 0.--31. 1. "ABOVE_HI,Out of range was detected and the value was above the Hi threshold"
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|
line.long 0xC "WORK_PULSE,Pulse detected"
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|
hexmask.long 0xC 0.--31. 1. "PULSE,N/A"
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|
rgroup.long ($2+0x1A0)++0x7
|
|
line.long 0x0 "RESULT_VALID,Channel result data register 'valid' bits"
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|
hexmask.long 0x0 0.--31. 1. "RESULT_VALID,If set the corresponding RESULT register is valid i.e. was acquired during the preceding group scan. If this bit is low after a group scan completed then either the channel is not enabled or is used as a pulse detect channel."
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line.long 0x4 "RESULT_RANGE_HI,Channel Range above Hi flags"
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|
hexmask.long 0x4 0.--31. 1. "ABOVE_HI,Out of range was detected and the value was above the Hi threshold"
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|
rgroup.long ($2+0x200)++0x7
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|
line.long 0x0 "STATUS,Current status of internal SAR registers (mostly for debug)"
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|
bitfld.long 0x0 31. "BUSY,If high then the SAR is busy with a conversion." "0,1"
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bitfld.long 0x0 30. "PWRUP_BUSY,If high then the SAR is waiting for PWRUP_TIME due to IDLE_PWRDWN" "0,1"
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newline
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bitfld.long 0x0 29. "DBG_FREEZE,If high then the SAR is prevented from starting a new acquisition see DBG_FREEZE_EN." "0,1"
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|
bitfld.long 0x0 12.--13. "CUR_PREEMPT_TYPE,Preempting type of current group/channel only valid if BUSY." "0,1,2,3"
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|
newline
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bitfld.long 0x0 8.--10. "CUR_PRIO,priority of current group/channel only valid if BUSY." "0,1,2,3,4,5,6,7"
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|
hexmask.long.byte 0x0 0.--4. 1. "CUR_CHAN,current channel being acquired only valid if BUSY."
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|
line.long 0x4 "AVG_STAT,Current averaging status (for debug)"
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|
hexmask.long.byte 0x4 24.--31. 1. "CUR_AVG_CNT,the current value of the averaging counter. Note that the value shown is updated after the sample window and therefore runs ahead of the accumulator update."
|
|
hexmask.long.tbyte 0x4 0.--19. 1. "CUR_AVG_ACCU,the current value of the averaging accumulator"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list 0x800 0x840 0x880 0x8C0 0x900 0x940 0x980 0x9C0 0xA00 0xA40 0xA80 0xAC0 0xB00 0xB40 0xB80 0xBC0)
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|
tree "CH[$1]"
|
|
group.long ($2)++0x1B
|
|
line.long 0x0 "TR_CTL,Trigger control."
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|
bitfld.long 0x0 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output" "0: tr_ch_done generates a 2 cycle pulse (clk_sys)..,1: tr_ch_done is a level output until the result.."
|
|
newline
|
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bitfld.long 0x0 11. "GROUP_END,0: continue group with next channel" "0: continue group with next channel,1: last channel of a group"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return Restart..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
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|
newline
|
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bitfld.long 0x0 4.--6. "PRIO,Channel priority:" "0,1,2,3,4,5,6,7"
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|
newline
|
|
bitfld.long 0x0 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first channel,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: N/A,4: N/A,5: N/A,6: N/A,7: Always triggered (also called idle) can only be.."
|
|
line.long 0x4 "SAMPLE_CTL,Sample control."
|
|
bitfld.long 0x4 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values." "0: use regular calibration values,1: use alternate calibration values"
|
|
newline
|
|
hexmask.long.word 0x4 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles. Minimum is 1 (0 gives the same result as 1) minimum time needed for proper settling is at least 300ns i.e. 6 clock cycles at the max frequency of 20MHz."
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|
newline
|
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bitfld.long 0x4 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used." "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input for..,3: Select Diagnostic reference instead of analog.."
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|
newline
|
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bitfld.long 0x4 12.--13. "PRECOND_MODE,Select preconditioning mode." "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output during.."
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|
newline
|
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bitfld.long 0x4 11. "EXT_MUX_EN,External analog mux enable." "0,1"
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|
newline
|
|
bitfld.long 0x4 8.--10. "EXT_MUX_SEL,External analog mux select." "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?,?,?,?,?,?"
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|
newline
|
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bitfld.long 0x4 6.--7. "PORT_ADDR,Select the physical port. This field is only valid for ADC0." "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0 undefined..,2: ADC0 uses SARMUX2 (only valid for ADC0 undefined..,3: ADC0 uses SARMUX3 (only valid for ADC0 undefined.."
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|
newline
|
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hexmask.long.byte 0x4 0.--5. 1. "PIN_ADDR,N/A"
|
|
line.long 0x8 "POST_CTL,Post processing control"
|
|
bitfld.long 0x8 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels" "0: Default: tr_sar_ch_done is set when the group is..,1: tr_sar_ch_done is only set if any of the.."
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|
newline
|
|
bitfld.long 0x8 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
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|
newline
|
|
hexmask.long.byte 0x8 16.--20. 1. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled)"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value"
|
|
newline
|
|
bitfld.long 0x8 7. "SIGN_EXT,Output data is sign extended" "0: Default: result data is unsigned (zero extended..,1: Result data is signed (sign extended if needed)"
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|
newline
|
|
bitfld.long 0x8 6. "LEFT_ALIGN,Left or right align data in result[15:0]." "0: the data is right aligned in result[11:0],1: the data is left aligned in result[15:4] with.."
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|
newline
|
|
bitfld.long 0x8 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: N/A,6: N/A,7: N/A"
|
|
line.long 0xC "RANGE_CTL,Range thresholds"
|
|
hexmask.long.word 0xC 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
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|
newline
|
|
hexmask.long.word 0xC 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
|
|
line.long 0x10 "INTR,Interrupt request register."
|
|
bitfld.long 0x10 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup. Write with '1' to clear bit." "0,1"
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|
newline
|
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bitfld.long 0x10 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero. This interrupt is mutual exclusive with Range detect interrupt. Write with '1' to clear bit." "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers. This interrupt is mutual exclusive with Pulse detect.." "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending. Write with '1' to clear bit." "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED. Note that it is possible that also the GRP_DONE interrupt is set. If that is the case one or more new triggers.." "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done. Write with '1' to clear bit." "0,1"
|
|
line.long 0x14 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x14 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x14 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x18 "INTR_MASK,Interrupt mask register."
|
|
bitfld.long 0x18 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x18 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x18 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x18 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x18 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long ($2+0x1C)++0xF
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x0 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
line.long 0x4 "WORK,Working data register"
|
|
bitfld.long 0x4 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "WORK,SAR conversion working data of the channel. The data is written here right after sampling this channel."
|
|
line.long 0x8 "RESULT,Result data register"
|
|
bitfld.long 0x8 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x8 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x8 0.--15. 1. "RESULT,SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled."
|
|
line.long 0xC "GRP_STAT,Group status register"
|
|
bitfld.long 0xC 16. "GRP_BUSY,Group acquisition busy." "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "CH_OVERFLOW,Channel Overflow." "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "CH_PULSE_COMPLETE,Channel Pulse complete." "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "CH_RANGE_COMPLETE,Channel Range complete." "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "GRP_OVERFLOW,Group Overflow." "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "GRP_CANCELLED,Group Cancelled." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "GRP_COMPLETE,Group acquisition complete." "0,1"
|
|
group.long ($2+0x38)++0x7
|
|
line.long 0x0 "ENABLE,Enable register"
|
|
bitfld.long 0x0 0. "CHAN_EN,Channel enable." "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
|
|
line.long 0x4 "TR_CMD,Software triggers"
|
|
bitfld.long 0x4 0. "START,Software start trigger. When written with '1' a start trigger is generated which sets the corresponding TR_PEND bit (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list 0xC00 0xC40 0xC80 0xCC0 0xD00 0xD40 0xD80 0xDC0 0xE00 0xE40 0xE80 0xEC0 0xF00 0xF40 0xF80 0xFC0)
|
|
tree "CH[$1]"
|
|
group.long ($2)++0x1B
|
|
line.long 0x0 "TR_CTL,Trigger control."
|
|
bitfld.long 0x0 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output" "0: tr_ch_done generates a 2 cycle pulse (clk_sys)..,1: tr_ch_done is a level output until the result.."
|
|
newline
|
|
bitfld.long 0x0 11. "GROUP_END,0: continue group with next channel" "0: continue group with next channel,1: last channel of a group"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return Restart..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
|
|
newline
|
|
bitfld.long 0x0 4.--6. "PRIO,Channel priority:" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first channel,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: N/A,4: N/A,5: N/A,6: N/A,7: Always triggered (also called idle) can only be.."
|
|
line.long 0x4 "SAMPLE_CTL,Sample control."
|
|
bitfld.long 0x4 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values." "0: use regular calibration values,1: use alternate calibration values"
|
|
newline
|
|
hexmask.long.word 0x4 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles. Minimum is 1 (0 gives the same result as 1) minimum time needed for proper settling is at least 300ns i.e. 6 clock cycles at the max frequency of 20MHz."
|
|
newline
|
|
bitfld.long 0x4 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used." "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input for..,3: Select Diagnostic reference instead of analog.."
|
|
newline
|
|
bitfld.long 0x4 12.--13. "PRECOND_MODE,Select preconditioning mode." "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output during.."
|
|
newline
|
|
bitfld.long 0x4 11. "EXT_MUX_EN,External analog mux enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--10. "EXT_MUX_SEL,External analog mux select." "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x4 6.--7. "PORT_ADDR,Select the physical port. This field is only valid for ADC0." "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0 undefined..,2: ADC0 uses SARMUX2 (only valid for ADC0 undefined..,3: ADC0 uses SARMUX3 (only valid for ADC0 undefined.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "PIN_ADDR,N/A"
|
|
line.long 0x8 "POST_CTL,Post processing control"
|
|
bitfld.long 0x8 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels" "0: Default: tr_sar_ch_done is set when the group is..,1: tr_sar_ch_done is only set if any of the.."
|
|
newline
|
|
bitfld.long 0x8 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--20. 1. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled)"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value"
|
|
newline
|
|
bitfld.long 0x8 7. "SIGN_EXT,Output data is sign extended" "0: Default: result data is unsigned (zero extended..,1: Result data is signed (sign extended if needed)"
|
|
newline
|
|
bitfld.long 0x8 6. "LEFT_ALIGN,Left or right align data in result[15:0]." "0: the data is right aligned in result[11:0],1: the data is left aligned in result[15:4] with.."
|
|
newline
|
|
bitfld.long 0x8 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: N/A,6: N/A,7: N/A"
|
|
line.long 0xC "RANGE_CTL,Range thresholds"
|
|
hexmask.long.word 0xC 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
|
|
newline
|
|
hexmask.long.word 0xC 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
|
|
line.long 0x10 "INTR,Interrupt request register."
|
|
bitfld.long 0x10 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup. Write with '1' to clear bit." "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero. This interrupt is mutual exclusive with Range detect interrupt. Write with '1' to clear bit." "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers. This interrupt is mutual exclusive with Pulse detect.." "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending. Write with '1' to clear bit." "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED. Note that it is possible that also the GRP_DONE interrupt is set. If that is the case one or more new triggers.." "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done. Write with '1' to clear bit." "0,1"
|
|
line.long 0x14 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x14 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x14 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x18 "INTR_MASK,Interrupt mask register."
|
|
bitfld.long 0x18 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x18 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x18 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x18 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x18 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long ($2+0x1C)++0xF
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x0 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
line.long 0x4 "WORK,Working data register"
|
|
bitfld.long 0x4 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "WORK,SAR conversion working data of the channel. The data is written here right after sampling this channel."
|
|
line.long 0x8 "RESULT,Result data register"
|
|
bitfld.long 0x8 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x8 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x8 0.--15. 1. "RESULT,SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled."
|
|
line.long 0xC "GRP_STAT,Group status register"
|
|
bitfld.long 0xC 16. "GRP_BUSY,Group acquisition busy." "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "CH_OVERFLOW,Channel Overflow." "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "CH_PULSE_COMPLETE,Channel Pulse complete." "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "CH_RANGE_COMPLETE,Channel Range complete." "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "GRP_OVERFLOW,Group Overflow." "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "GRP_CANCELLED,Group Cancelled." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "GRP_COMPLETE,Group acquisition complete." "0,1"
|
|
group.long ($2+0x38)++0x7
|
|
line.long 0x0 "ENABLE,Enable register"
|
|
bitfld.long 0x0 0. "CHAN_EN,Channel enable." "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
|
|
line.long 0x4 "TR_CMD,Software triggers"
|
|
bitfld.long 0x4 0. "START,Software start trigger. When written with '1' a start trigger is generated which sets the corresponding TR_PEND bit (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
tree "EPASS_MMIO (PASS top-level MMIO (Generic Triggers))"
|
|
base ad:0x409F0000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "PASS_CTL,PASS control register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "DBG_FREEZE_EN,Debug pause enable 1 per ADC."
|
|
bitfld.long 0x0 21.--22. "REFBUF_MODE,Reference mode." "0: No reference,1: Reference = buffered Vbg from SRSS,2: undefined,3: Reference = unbuffered Vbg from SRSS"
|
|
bitfld.long 0x0 5. "SUPPLY_MON_LVL_B,Supply monitor level select for AMUXBUS_B" "0: amuxbus_b_mon = VRL,1: amuxbus_b_mon = VRH"
|
|
newline
|
|
bitfld.long 0x0 4. "SUPPLY_MON_EN_B,Supply monitor enable for AMUXBUS_B (amuxbus_b_mon)" "0,1"
|
|
bitfld.long 0x0 1. "SUPPLY_MON_LVL_A,Supply monitor level select for AMUXBUS_A" "0: amuxbus_a_mon = VRL,1: amuxbus_a_mon = VRH"
|
|
bitfld.long 0x0 0. "SUPPLY_MON_EN_A,Supply monitor enable for AMUXBUS_A (amuxbus_a_mon)" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "SAR_TR_IN_SEL[$1],per SAR generic input trigger select"
|
|
hexmask.long.byte 0x0 16.--19. 1. "IN4_SEL,Select generic trigger for SAR generic trigger input 4"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IN3_SEL,Select generic trigger for SAR generic trigger input 3"
|
|
hexmask.long.byte 0x0 8.--11. 1. "IN2_SEL,Select generic trigger for SAR generic trigger input 2"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "IN1_SEL,Select generic trigger for SAR generic trigger input 1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "IN0_SEL,Select generic trigger for SAR generic trigger input 0"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "SAR_TR_OUT_SEL[$1],per SAR generic output trigger select"
|
|
hexmask.long.byte 0x0 8.--13. 1. "OUT1_SEL,Select SAR output trigger for generic trigger output 1"
|
|
hexmask.long.byte 0x0 0.--5. 1. "OUT0_SEL,Select SAR output trigger for generic trigger output 0"
|
|
repeat.end
|
|
tree.end
|
|
tree.end
|
|
tree "PERI (Peripheral Interconnect)"
|
|
base ad:0x40000000
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "TIMEOUT_CTL,Timeout control"
|
|
hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,This field specifies a number of clock cycles (clk_slow). If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection) the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and.."
|
|
group.long 0x220++0x3
|
|
line.long 0x0 "TR_CMD,Trigger command"
|
|
bitfld.long 0x0 31. "ACTIVATE,SW sets this field to '1' to activate (set to '1') a trigger as identified by TR_SEL TR_EDGE and OUT_SEL. HW sets this field to '0' for edge sensitive triggers AFTER the selected trigger is activated for two clk_peri cycles." "0,1"
|
|
bitfld.long 0x0 30. "OUT_SEL,Specifies whether trigger activation is for a specific input or output trigger of the trigger multiplexer. Activation of a specific input trigger will result in activation of all output triggers that have the specific input trigger selected.." "?,1: to-1 groups"
|
|
bitfld.long 0x0 29. "TR_EDGE,Specifies if the activated trigger is treated as a level sensitive or edge sensitive trigger." "0,1"
|
|
hexmask.long.byte 0x0 8.--12. 1. "GROUP_SEL,Specifies the trigger group:"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TR_SEL,Specifies the activated trigger when ACTIVATE is '1'. If the specified trigger is not present the trigger activation has no effect."
|
|
group.long 0x400++0x3
|
|
line.long 0x0 "DIV_CMD,Divider command"
|
|
bitfld.long 0x0 31. "ENABLE,Clock divider enable command (mutually exclusive with DISABLE). Typically SW sets this field to '1' to enable a divider and HW sets this field to '0' to indicate that divider enabling has completed. When a divider is enabled its integer and.." "0: Disable the divider using the DIV_CMD,1: Configure the divider's DIV_XXX_CTL register"
|
|
bitfld.long 0x0 30. "DISABLE,Clock divider disable command (mutually exclusive with ENABLE). SW sets this field to '1' and HW sets this field to '0'." "0,1"
|
|
bitfld.long 0x0 24.--25. "PA_TYPE_SEL,Specifies the divider type of the divider to which phase alignment is performed for the clock enable command:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--23. 1. "PA_DIV_SEL,(PA_TYPE_SEL PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other even when they are.."
|
|
newline
|
|
bitfld.long 0x0 8.--9. "TYPE_SEL,Specifies the divider type of the divider on which the command is performed:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DIV_SEL,(TYPE_SEL DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed."
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xC00)++0x3
|
|
line.long 0x0 "CLOCK_CTL[$1],Clock control"
|
|
bitfld.long 0x0 8.--9. "TYPE_SEL,Specifies divider type:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL."
|
|
repeat.end
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1000)++0x3
|
|
line.long 0x0 "DIV_8_CTL[$1],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x0 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1 256]. Note: this type of divider does NOT allow for a fractional division."
|
|
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
|
|
repeat.end
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1400)++0x3
|
|
line.long 0x0 "DIV_16_CTL[$1],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x0 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1 65 536]. Note: this type of divider does NOT allow for a fractional division."
|
|
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
|
|
repeat.end
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1800)++0x3
|
|
line.long 0x0 "DIV_16_5_CTL[$1],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x0 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1 65 536]. Note: combined with fractional division this divider type allows for a division in the range [1 65 536 31/32] in 1/32 increments."
|
|
hexmask.long.byte 0x0 3.--7. 1. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods."
|
|
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
|
|
repeat.end
|
|
repeat 255. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1C00)++0x3
|
|
line.long 0x0 "DIV_24_5_CTL[$1],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1 16 777 216]. Note: combined with fractional division this divider type allows for a division in the range [1 16 777 216 31/32] in 1/32 increments."
|
|
hexmask.long.byte 0x0 3.--7. 1. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods."
|
|
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
|
|
repeat.end
|
|
group.long 0x2000++0x3
|
|
line.long 0x0 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR."
|
|
bitfld.long 0x0 18. "ECC_INJ_EN,Enable error injection for PERI protection structure SRAM." "0,1"
|
|
bitfld.long 0x0 16. "ECC_EN,Enable ECC checking:" "0,1"
|
|
hexmask.long.word 0x0 0.--10. 1. "WORD_ADDR,Specifies the word address where the parity is injected."
|
|
repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list ad:0x40004000 ad:0x40004020 ad:0x40004040 ad:0x40004060 ad:0x40004080 ad:0x400040A0 ad:0x400040C0 ad:0x400040E0 ad:0x40004100 ad:0x40004120)
|
|
tree "GR[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CLOCK_CTL,Clock control"
|
|
hexmask.long.byte 0x0 8.--15. 1. "INT8_DIV,Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1 256]."
|
|
group.long ($2+0x10)++0x3
|
|
line.long 0x0 "SL_CTL,Slave control"
|
|
bitfld.long 0x0 31. "DISABLED_15,N/A" "0,1"
|
|
bitfld.long 0x0 30. "DISABLED_14,N/A" "0,1"
|
|
bitfld.long 0x0 29. "DISABLED_13,N/A" "0,1"
|
|
bitfld.long 0x0 28. "DISABLED_12,N/A" "0,1"
|
|
bitfld.long 0x0 27. "DISABLED_11,N/A" "0,1"
|
|
bitfld.long 0x0 26. "DISABLED_10,N/A" "0,1"
|
|
bitfld.long 0x0 25. "DISABLED_9,N/A" "0,1"
|
|
bitfld.long 0x0 24. "DISABLED_8,N/A" "0,1"
|
|
bitfld.long 0x0 23. "DISABLED_7,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "DISABLED_6,N/A" "0,1"
|
|
bitfld.long 0x0 21. "DISABLED_5,N/A" "0,1"
|
|
bitfld.long 0x0 20. "DISABLED_4,N/A" "0,1"
|
|
bitfld.long 0x0 19. "DISABLED_3,N/A" "0,1"
|
|
bitfld.long 0x0 18. "DISABLED_2,N/A" "0,1"
|
|
bitfld.long 0x0 17. "DISABLED_1,N/A" "0,1"
|
|
bitfld.long 0x0 16. "DISABLED_0,Peripheral group slave 0 permanent disable. Setting this bit to 1 has the same effect as setting ENABLED_0 to 0. However once set to 1 this bit cannot be changed back to 0 anymore." "0,1"
|
|
bitfld.long 0x0 15. "ENABLED_15,N/A" "0,1"
|
|
bitfld.long 0x0 14. "ENABLED_14,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENABLED_13,N/A" "0,1"
|
|
bitfld.long 0x0 12. "ENABLED_12,N/A" "0,1"
|
|
bitfld.long 0x0 11. "ENABLED_11,N/A" "0,1"
|
|
bitfld.long 0x0 10. "ENABLED_10,N/A" "0,1"
|
|
bitfld.long 0x0 9. "ENABLED_9,N/A" "0,1"
|
|
bitfld.long 0x0 8. "ENABLED_8,N/A" "0,1"
|
|
bitfld.long 0x0 7. "ENABLED_7,N/A" "0,1"
|
|
bitfld.long 0x0 6. "ENABLED_6,N/A" "0,1"
|
|
bitfld.long 0x0 5. "ENABLED_5,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENABLED_4,N/A" "0,1"
|
|
bitfld.long 0x0 3. "ENABLED_3,N/A" "0,1"
|
|
bitfld.long 0x0 2. "ENABLED_2,N/A" "0,1"
|
|
bitfld.long 0x0 1. "ENABLED_1,Peripheral group slave 1 enable. If the slave is disabled its clock is gated off (constant '0') and its resets are activated." "0,1"
|
|
bitfld.long 0x0 0. "ENABLED_0,Peripheral group slave 0 enable. If the slave is disabled its clock is gated off (constant '0') and its resets are activated." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 11. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA)(list ad:0x40008000 ad:0x40008400 ad:0x40008800 ad:0x40008C00 ad:0x40009000 ad:0x40009400 ad:0x40009800 ad:0x40009C00 ad:0x4000A000 ad:0x4000A400 ad:0x4000A800)
|
|
tree "TR_GR[$1]"
|
|
base $2
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "TR_CTL[$1],Trigger control register"
|
|
bitfld.long 0x0 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation." "0,1"
|
|
bitfld.long 0x0 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger." "0,1"
|
|
bitfld.long 0x0 8. "TR_INV,Specifies if the output trigger is inverted." "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TR_SEL,Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0.."
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
repeat 11. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA)(list ad:0x4000C000 ad:0x4000C400 ad:0x4000C800 ad:0x4000CC00 ad:0x4000D000 ad:0x4000D400 ad:0x4000D800 ad:0x4000DC00 ad:0x4000E000 ad:0x4000E400 ad:0x4000E800)
|
|
tree "TR_1TO1_GR[$1]"
|
|
base $2
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "TR_CTL[$1],Trigger control register"
|
|
bitfld.long 0x0 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation." "0,1"
|
|
bitfld.long 0x0 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger." "0,1"
|
|
bitfld.long 0x0 8. "TR_INV,Specifies if the output trigger is inverted." "0,1"
|
|
bitfld.long 0x0 0. "TR_SEL,Specifies input trigger:" "0,1"
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "PERI_MS (Peripheral interconnect - Master Interface)"
|
|
base ad:0x40010000
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40010000 ad:0x40010040 ad:0x40010080 ad:0x400100C0 ad:0x40010100 ad:0x40010140 ad:0x40010180 ad:0x400101C0 ad:0x40010200 ad:0x40010240 ad:0x40010280 ad:0x400102C0 ad:0x40010300 ad:0x40010340 ad:0x40010380 ad:0x400103C0)
|
|
tree "PPU_PR[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40010800 ad:0x40010840 ad:0x40010880 ad:0x400108C0 ad:0x40010900 ad:0x40010940 ad:0x40010980 ad:0x400109C0 ad:0x40010A00 ad:0x40010A40 ad:0x40010A80 ad:0x40010AC0 ad:0x40010B00 ad:0x40010B40 ad:0x40010B80 ad:0x40010BC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x40010C00 ad:0x40010C40 ad:0x40010C80 ad:0x40010CC0 ad:0x40010D00 ad:0x40010D40 ad:0x40010D80 ad:0x40010DC0 ad:0x40010E00 ad:0x40010E40 ad:0x40010E80 ad:0x40010EC0 ad:0x40010F00 ad:0x40010F40 ad:0x40010F80 ad:0x40010FC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F)(list ad:0x40011000 ad:0x40011040 ad:0x40011080 ad:0x400110C0 ad:0x40011100 ad:0x40011140 ad:0x40011180 ad:0x400111C0 ad:0x40011200 ad:0x40011240 ad:0x40011280 ad:0x400112C0 ad:0x40011300 ad:0x40011340 ad:0x40011380 ad:0x400113C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F)(list ad:0x40011400 ad:0x40011440 ad:0x40011480 ad:0x400114C0 ad:0x40011500 ad:0x40011540 ad:0x40011580 ad:0x400115C0 ad:0x40011600 ad:0x40011640 ad:0x40011680 ad:0x400116C0 ad:0x40011700 ad:0x40011740 ad:0x40011780 ad:0x400117C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F)(list ad:0x40011800 ad:0x40011840 ad:0x40011880 ad:0x400118C0 ad:0x40011900 ad:0x40011940 ad:0x40011980 ad:0x400119C0 ad:0x40011A00 ad:0x40011A40 ad:0x40011A80 ad:0x40011AC0 ad:0x40011B00 ad:0x40011B40 ad:0x40011B80 ad:0x40011BC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F)(list ad:0x40011C00 ad:0x40011C40 ad:0x40011C80 ad:0x40011CC0 ad:0x40011D00 ad:0x40011D40 ad:0x40011D80 ad:0x40011DC0 ad:0x40011E00 ad:0x40011E40 ad:0x40011E80 ad:0x40011EC0 ad:0x40011F00 ad:0x40011F40 ad:0x40011F80 ad:0x40011FC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F)(list ad:0x40012000 ad:0x40012040 ad:0x40012080 ad:0x400120C0 ad:0x40012100 ad:0x40012140 ad:0x40012180 ad:0x400121C0 ad:0x40012200 ad:0x40012240 ad:0x40012280 ad:0x400122C0 ad:0x40012300 ad:0x40012340 ad:0x40012380 ad:0x400123C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F)(list ad:0x40012400 ad:0x40012440 ad:0x40012480 ad:0x400124C0 ad:0x40012500 ad:0x40012540 ad:0x40012580 ad:0x400125C0 ad:0x40012600 ad:0x40012640 ad:0x40012680 ad:0x400126C0 ad:0x40012700 ad:0x40012740 ad:0x40012780 ad:0x400127C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F)(list ad:0x40012800 ad:0x40012840 ad:0x40012880 ad:0x400128C0 ad:0x40012900 ad:0x40012940 ad:0x40012980 ad:0x400129C0 ad:0x40012A00 ad:0x40012A40 ad:0x40012A80 ad:0x40012AC0 ad:0x40012B00 ad:0x40012B40 ad:0x40012B80 ad:0x40012BC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F)(list ad:0x40012C00 ad:0x40012C40 ad:0x40012C80 ad:0x40012CC0 ad:0x40012D00 ad:0x40012D40 ad:0x40012D80 ad:0x40012DC0 ad:0x40012E00 ad:0x40012E40 ad:0x40012E80 ad:0x40012EC0 ad:0x40012F00 ad:0x40012F40 ad:0x40012F80 ad:0x40012FC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF)(list ad:0x40013000 ad:0x40013040 ad:0x40013080 ad:0x400130C0 ad:0x40013100 ad:0x40013140 ad:0x40013180 ad:0x400131C0 ad:0x40013200 ad:0x40013240 ad:0x40013280 ad:0x400132C0 ad:0x40013300 ad:0x40013340 ad:0x40013380 ad:0x400133C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF)(list ad:0x40013400 ad:0x40013440 ad:0x40013480 ad:0x400134C0 ad:0x40013500 ad:0x40013540 ad:0x40013580 ad:0x400135C0 ad:0x40013600 ad:0x40013640 ad:0x40013680 ad:0x400136C0 ad:0x40013700 ad:0x40013740 ad:0x40013780 ad:0x400137C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF)(list ad:0x40013800 ad:0x40013840 ad:0x40013880 ad:0x400138C0 ad:0x40013900 ad:0x40013940 ad:0x40013980 ad:0x400139C0 ad:0x40013A00 ad:0x40013A40 ad:0x40013A80 ad:0x40013AC0 ad:0x40013B00 ad:0x40013B40 ad:0x40013B80 ad:0x40013BC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF)(list ad:0x40013C00 ad:0x40013C40 ad:0x40013C80 ad:0x40013CC0 ad:0x40013D00 ad:0x40013D40 ad:0x40013D80 ad:0x40013DC0 ad:0x40013E00 ad:0x40013E40 ad:0x40013E80 ad:0x40013EC0 ad:0x40013F00 ad:0x40013F40 ad:0x40013F80 ad:0x40013FC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF)(list ad:0x40014000 ad:0x40014040 ad:0x40014080 ad:0x400140C0 ad:0x40014100 ad:0x40014140 ad:0x40014180 ad:0x400141C0 ad:0x40014200 ad:0x40014240 ad:0x40014280 ad:0x400142C0 ad:0x40014300 ad:0x40014340 ad:0x40014380 ad:0x400143C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF)(list ad:0x40014400 ad:0x40014440 ad:0x40014480 ad:0x400144C0 ad:0x40014500 ad:0x40014540 ad:0x40014580 ad:0x400145C0 ad:0x40014600 ad:0x40014640 ad:0x40014680 ad:0x400146C0 ad:0x40014700 ad:0x40014740 ad:0x40014780 ad:0x400147C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x100 0x101 0x102 0x103 0x104 0x105 0x106 0x107 0x108 0x109 0x10A 0x10B 0x10C 0x10D 0x10E 0x10F)(list ad:0x40014800 ad:0x40014840 ad:0x40014880 ad:0x400148C0 ad:0x40014900 ad:0x40014940 ad:0x40014980 ad:0x400149C0 ad:0x40014A00 ad:0x40014A40 ad:0x40014A80 ad:0x40014AC0 ad:0x40014B00 ad:0x40014B40 ad:0x40014B80 ad:0x40014BC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x110 0x111 0x112 0x113 0x114 0x115 0x116 0x117 0x118 0x119 0x11A 0x11B 0x11C 0x11D 0x11E 0x11F)(list ad:0x40014C00 ad:0x40014C40 ad:0x40014C80 ad:0x40014CC0 ad:0x40014D00 ad:0x40014D40 ad:0x40014D80 ad:0x40014DC0 ad:0x40014E00 ad:0x40014E40 ad:0x40014E80 ad:0x40014EC0 ad:0x40014F00 ad:0x40014F40 ad:0x40014F80 ad:0x40014FC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x120 0x121 0x122 0x123 0x124 0x125 0x126 0x127 0x128 0x129 0x12A 0x12B 0x12C 0x12D 0x12E 0x12F)(list ad:0x40015000 ad:0x40015040 ad:0x40015080 ad:0x400150C0 ad:0x40015100 ad:0x40015140 ad:0x40015180 ad:0x400151C0 ad:0x40015200 ad:0x40015240 ad:0x40015280 ad:0x400152C0 ad:0x40015300 ad:0x40015340 ad:0x40015380 ad:0x400153C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x130 0x131 0x132 0x133 0x134 0x135 0x136 0x137 0x138 0x139 0x13A 0x13B 0x13C 0x13D 0x13E 0x13F)(list ad:0x40015400 ad:0x40015440 ad:0x40015480 ad:0x400154C0 ad:0x40015500 ad:0x40015540 ad:0x40015580 ad:0x400155C0 ad:0x40015600 ad:0x40015640 ad:0x40015680 ad:0x400156C0 ad:0x40015700 ad:0x40015740 ad:0x40015780 ad:0x400157C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x140 0x141 0x142 0x143 0x144 0x145 0x146 0x147 0x148 0x149 0x14A 0x14B 0x14C 0x14D 0x14E 0x14F)(list ad:0x40015800 ad:0x40015840 ad:0x40015880 ad:0x400158C0 ad:0x40015900 ad:0x40015940 ad:0x40015980 ad:0x400159C0 ad:0x40015A00 ad:0x40015A40 ad:0x40015A80 ad:0x40015AC0 ad:0x40015B00 ad:0x40015B40 ad:0x40015B80 ad:0x40015BC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x150 0x151 0x152 0x153 0x154 0x155 0x156 0x157 0x158 0x159 0x15A 0x15B 0x15C 0x15D 0x15E 0x15F)(list ad:0x40015C00 ad:0x40015C40 ad:0x40015C80 ad:0x40015CC0 ad:0x40015D00 ad:0x40015D40 ad:0x40015D80 ad:0x40015DC0 ad:0x40015E00 ad:0x40015E40 ad:0x40015E80 ad:0x40015EC0 ad:0x40015F00 ad:0x40015F40 ad:0x40015F80 ad:0x40015FC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x160 0x161 0x162 0x163 0x164 0x165 0x166 0x167 0x168 0x169 0x16A 0x16B 0x16C 0x16D 0x16E 0x16F)(list ad:0x40016000 ad:0x40016040 ad:0x40016080 ad:0x400160C0 ad:0x40016100 ad:0x40016140 ad:0x40016180 ad:0x400161C0 ad:0x40016200 ad:0x40016240 ad:0x40016280 ad:0x400162C0 ad:0x40016300 ad:0x40016340 ad:0x40016380 ad:0x400163C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x170 0x171 0x172 0x173 0x174 0x175 0x176 0x177 0x178 0x179 0x17A 0x17B 0x17C 0x17D 0x17E 0x17F)(list ad:0x40016400 ad:0x40016440 ad:0x40016480 ad:0x400164C0 ad:0x40016500 ad:0x40016540 ad:0x40016580 ad:0x400165C0 ad:0x40016600 ad:0x40016640 ad:0x40016680 ad:0x400166C0 ad:0x40016700 ad:0x40016740 ad:0x40016780 ad:0x400167C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x180 0x181 0x182 0x183 0x184 0x185 0x186 0x187 0x188 0x189 0x18A 0x18B 0x18C 0x18D 0x18E 0x18F)(list ad:0x40016800 ad:0x40016840 ad:0x40016880 ad:0x400168C0 ad:0x40016900 ad:0x40016940 ad:0x40016980 ad:0x400169C0 ad:0x40016A00 ad:0x40016A40 ad:0x40016A80 ad:0x40016AC0 ad:0x40016B00 ad:0x40016B40 ad:0x40016B80 ad:0x40016BC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x190 0x191 0x192 0x193 0x194 0x195 0x196 0x197 0x198 0x199 0x19A 0x19B 0x19C 0x19D 0x19E 0x19F)(list ad:0x40016C00 ad:0x40016C40 ad:0x40016C80 ad:0x40016CC0 ad:0x40016D00 ad:0x40016D40 ad:0x40016D80 ad:0x40016DC0 ad:0x40016E00 ad:0x40016E40 ad:0x40016E80 ad:0x40016EC0 ad:0x40016F00 ad:0x40016F40 ad:0x40016F80 ad:0x40016FC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x1A0 0x1A1 0x1A2 0x1A3 0x1A4 0x1A5 0x1A6 0x1A7 0x1A8 0x1A9 0x1AA 0x1AB 0x1AC 0x1AD 0x1AE 0x1AF)(list ad:0x40017000 ad:0x40017040 ad:0x40017080 ad:0x400170C0 ad:0x40017100 ad:0x40017140 ad:0x40017180 ad:0x400171C0 ad:0x40017200 ad:0x40017240 ad:0x40017280 ad:0x400172C0 ad:0x40017300 ad:0x40017340 ad:0x40017380 ad:0x400173C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x1B0 0x1B1 0x1B2 0x1B3 0x1B4 0x1B5 0x1B6 0x1B7 0x1B8 0x1B9 0x1BA 0x1BB 0x1BC 0x1BD 0x1BE 0x1BF)(list ad:0x40017400 ad:0x40017440 ad:0x40017480 ad:0x400174C0 ad:0x40017500 ad:0x40017540 ad:0x40017580 ad:0x400175C0 ad:0x40017600 ad:0x40017640 ad:0x40017680 ad:0x400176C0 ad:0x40017700 ad:0x40017740 ad:0x40017780 ad:0x400177C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x1C0 0x1C1 0x1C2 0x1C3 0x1C4 0x1C5 0x1C6 0x1C7 0x1C8 0x1C9 0x1CA 0x1CB 0x1CC 0x1CD 0x1CE 0x1CF)(list ad:0x40017800 ad:0x40017840 ad:0x40017880 ad:0x400178C0 ad:0x40017900 ad:0x40017940 ad:0x40017980 ad:0x400179C0 ad:0x40017A00 ad:0x40017A40 ad:0x40017A80 ad:0x40017AC0 ad:0x40017B00 ad:0x40017B40 ad:0x40017B80 ad:0x40017BC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x1D0 0x1D1 0x1D2 0x1D3 0x1D4 0x1D5 0x1D6 0x1D7 0x1D8 0x1D9 0x1DA 0x1DB 0x1DC 0x1DD 0x1DE 0x1DF)(list ad:0x40017C00 ad:0x40017C40 ad:0x40017C80 ad:0x40017CC0 ad:0x40017D00 ad:0x40017D40 ad:0x40017D80 ad:0x40017DC0 ad:0x40017E00 ad:0x40017E40 ad:0x40017E80 ad:0x40017EC0 ad:0x40017F00 ad:0x40017F40 ad:0x40017F80 ad:0x40017FC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 7. (list 0x1E0 0x1E1 0x1E2 0x1E3 0x1E4 0x1E5 0x1E6)(list ad:0x40018000 ad:0x40018040 ad:0x40018080 ad:0x400180C0 ad:0x40018100 ad:0x40018140 ad:0x40018180)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "PROT (Protection)"
|
|
base ad:0x40230000
|
|
tree "SMPU (SMPU)"
|
|
group.long 0x0++0x3F
|
|
line.long 0x0 "MS0_CTL,Master 0 protection context control"
|
|
hexmask.long.word 0x0 17.--31. 1. "PC_MASK_15_TO_1,Protection context mask for protection contexts '15' down to '1'. Bit PC_MASK_15_TO_1[i] indicates if the MPU MS_CTL.PC[3:0] protection context field can be set to the value 'i+1':"
|
|
rbitfld.long 0x0 16. "PC_MASK_0,Protection context mask for protection context '0'. This field is a constant '0':" "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Device wide bus arbitration priority setting ('0': highest priority '3': lowest priority)." "0,1,2,3"
|
|
bitfld.long 0x0 1. "NS,Security setting ('0': secure mode; '1': non-secure mode)." "0,1"
|
|
bitfld.long 0x0 0. "P,Privileged setting ('0': user mode; '1': privileged mode)." "0,1"
|
|
line.long 0x4 "MS1_CTL,Master 1 protection context control"
|
|
hexmask.long.word 0x4 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x4 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x4 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x4 1. "NS,See MS0_CTL.NS." "0,1"
|
|
bitfld.long 0x4 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x8 "MS2_CTL,Master 2 protection context control"
|
|
hexmask.long.word 0x8 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x8 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x8 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x8 1. "NS,See MS0_CTL.NS." "0,1"
|
|
bitfld.long 0x8 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0xC "MS3_CTL,Master 3 protection context control"
|
|
hexmask.long.word 0xC 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0xC 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0xC 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0xC 1. "NS,See MS0_CTL.NS." "0,1"
|
|
bitfld.long 0xC 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x10 "MS4_CTL,Master 4 protection context control"
|
|
hexmask.long.word 0x10 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x10 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x10 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x10 1. "NS,See MS0_CTL.NS." "0,1"
|
|
bitfld.long 0x10 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x14 "MS5_CTL,Master 5 protection context control"
|
|
hexmask.long.word 0x14 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x14 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x14 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x14 1. "NS,See MS0_CTL.NS." "0,1"
|
|
bitfld.long 0x14 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x18 "MS6_CTL,Master 6 protection context control"
|
|
hexmask.long.word 0x18 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x18 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x18 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x18 1. "NS,See MS0_CTL.NS." "0,1"
|
|
bitfld.long 0x18 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x1C "MS7_CTL,Master 7 protection context control"
|
|
hexmask.long.word 0x1C 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x1C 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x1C 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x1C 1. "NS,See MS0_CTL.NS." "0,1"
|
|
bitfld.long 0x1C 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x20 "MS8_CTL,Master 8 protection context control"
|
|
hexmask.long.word 0x20 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x20 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x20 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x20 1. "NS,See MS0_CTL.NS." "0,1"
|
|
bitfld.long 0x20 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x24 "MS9_CTL,Master 9 protection context control"
|
|
hexmask.long.word 0x24 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x24 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x24 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x24 1. "NS,See MS0_CTL.NS." "0,1"
|
|
bitfld.long 0x24 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x28 "MS10_CTL,Master 10 protection context control"
|
|
hexmask.long.word 0x28 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x28 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x28 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x28 1. "NS,See MS0_CTL.NS." "0,1"
|
|
bitfld.long 0x28 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x2C "MS11_CTL,Master 11 protection context control"
|
|
hexmask.long.word 0x2C 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x2C 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x2C 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x2C 1. "NS,See MS0_CTL.NS." "0,1"
|
|
bitfld.long 0x2C 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x30 "MS12_CTL,Master 12 protection context control"
|
|
hexmask.long.word 0x30 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x30 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x30 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x30 1. "NS,See MS0_CTL.NS." "0,1"
|
|
bitfld.long 0x30 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x34 "MS13_CTL,Master 13 protection context control"
|
|
hexmask.long.word 0x34 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x34 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x34 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x34 1. "NS,See MS0_CTL.NS." "0,1"
|
|
bitfld.long 0x34 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x38 "MS14_CTL,Master 14 protection context control"
|
|
hexmask.long.word 0x38 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x38 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x38 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x38 1. "NS,See MS0_CTL.NS." "0,1"
|
|
bitfld.long 0x38 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x3C "MS15_CTL,Master 15 protection context control"
|
|
hexmask.long.word 0x3C 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x3C 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x3C 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x3C 1. "NS,See MS0_CTL.NS." "0,1"
|
|
bitfld.long 0x3C 0. "P,See MS0_CTL.P." "0,1"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40232000 ad:0x40232040 ad:0x40232080 ad:0x402320C0 ad:0x40232100 ad:0x40232140 ad:0x40232180 ad:0x402321C0 ad:0x40232200 ad:0x40232240 ad:0x40232280 ad:0x402322C0 ad:0x40232300 ad:0x40232340 ad:0x40232380 ad:0x402323C0)
|
|
tree "SMPU_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "ADDR0,SMPU region address 0 (slave structure)"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR24,This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT0.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result some of the lesser significant address bits of.."
|
|
hexmask.long.byte 0x0 0.--7. 1. "SUBREGION_DISABLE,This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:"
|
|
line.long 0x4 "ATT0,SMPU region attributes 0 (slave structure)"
|
|
bitfld.long 0x4 31. "ENABLED,Region enable:" "0,1"
|
|
bitfld.long 0x4 30. "PC_MATCH,This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the region size:"
|
|
hexmask.long.word 0x4 9.--23. 1. "PC_MASK_15_TO_1,This field specifies protection context identifier based access control."
|
|
rbitfld.long 0x4 8. "PC_MASK_0,This field specifies protection context identifier based access control for protection context '0'." "0,1"
|
|
bitfld.long 0x4 6. "NS,Non-secure:" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PX,Privileged execute enable:" "0,1"
|
|
bitfld.long 0x4 4. "PW,Privileged write enable:" "0,1"
|
|
bitfld.long 0x4 3. "PR,Privileged read enable:" "0,1"
|
|
bitfld.long 0x4 2. "UX,User execute enable:" "0,1"
|
|
bitfld.long 0x4 1. "UW,User write enable:" "0,1"
|
|
bitfld.long 0x4 0. "UR,User read enable:" "0,1"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "ADDR1,SMPU region address 1 (master structure)"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR24,This field specifies the most significant bits of the 32-bit address of an address region."
|
|
hexmask.long.byte 0x0 0.--7. 1. "SUBREGION_DISABLE,This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:"
|
|
group.long ($2+0x24)++0x3
|
|
line.long 0x0 "ATT1,SMPU region attributes 1 (master structure)"
|
|
bitfld.long 0x0 31. "ENABLED,Region enable:" "0,1"
|
|
bitfld.long 0x0 30. "PC_MATCH,This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process:" "0,1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "REGION_SIZE,This field specifies the region size:"
|
|
hexmask.long.word 0x0 9.--23. 1. "PC_MASK_15_TO_1,This field specifies protection context identifier based access control."
|
|
rbitfld.long 0x0 8. "PC_MASK_0,This field specifies protection context identifier based access control for protection context '0'." "0,1"
|
|
bitfld.long 0x0 6. "NS,Non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 5. "PX,Privileged execute enable:" "0,1"
|
|
bitfld.long 0x0 4. "PW,Privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 3. "PR,Privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 2. "UX,User execute enable:" "0,1"
|
|
bitfld.long 0x0 1. "UW,User write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "UR,User read enable:" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40234000 ad:0x40234400 ad:0x40234800 ad:0x40234C00 ad:0x40235000 ad:0x40235400 ad:0x40235800 ad:0x40235C00 ad:0x40236000 ad:0x40236400 ad:0x40236800 ad:0x40236C00 ad:0x40237000 ad:0x40237400 ad:0x40237800 ad:0x40237C00)
|
|
tree "MPU[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "MS_CTL,Master control"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PC_SAVED,Saved protection context. Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields."
|
|
hexmask.long.byte 0x0 0.--3. 1. "PC,Active protection context (PC). Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. In addition a write transfer with protection context '0' can change this field (protection.."
|
|
repeat 127. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "MS_CTL_READ_MIR[$1],Master control read mirror"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PC,Read-only mirror of MS_CTL.PC"
|
|
repeat.end
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x200 0x220 0x240 0x260 0x280 0x2A0 0x2C0 0x2E0)
|
|
tree "MPU_STRUCT[$1]"
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "ADDR,MPU region address"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR24,This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result some of the lesser significant address bits of.."
|
|
hexmask.long.byte 0x0 0.--7. 1. "SUBREGION_DISABLE,This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:"
|
|
line.long 0x4 "ATT,MPU region attrributes"
|
|
bitfld.long 0x4 31. "ENABLED,Region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the region size:"
|
|
bitfld.long 0x4 6. "NS,Non-secure:" "0,1"
|
|
bitfld.long 0x4 5. "PX,Privileged execute enable:" "0,1"
|
|
bitfld.long 0x4 4. "PW,Privileged write enable:" "0,1"
|
|
bitfld.long 0x4 3. "PR,Privileged read enable:" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "UX,User execute enable:" "0,1"
|
|
bitfld.long 0x4 1. "UW,User write enable:" "0,1"
|
|
bitfld.long 0x4 0. "UR,User read enable:" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "SCB (Serial Communications Block (SPI/UART/I2C))"
|
|
base ad:0x0
|
|
tree "SCB0"
|
|
base ad:0x40600000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,IP enabled ('1') or not ('0'). The proper order in which to initialize the IP is as follows:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "EC_ACCESS,used to enable I2CS_EC or SPIS_EC access to internal SRAM memory." "0: enable clock_scb_en,1: disable clock_scb_en"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
|
|
newline
|
|
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the MMIO SW accesses to EZ memory coincide/collide this bit determines whether a SW access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MEM_WIDTH,Determines the number of bits per FIFO data element." "0: 8-bit FIFO data elements. This mode provides the..,1: 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH..,2: 32-bit FIFO data elements. This mode provides..,3: N/A"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1'). In EZ mode a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "EC_OP_MODE,Internally clocked mode ('0') or externally clocked mode ('1') operation. In internally clocked mode the serial interface protocols run off the peripheral clock. In externally clocked mode the serial interface protocols run off the clock as.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "EC_AM_MODE,Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI). In internally clocked mode the serial interface protocols run off the peripheral clock. In externally clocked mode the serial interface.." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Generic status"
|
|
bitfld.long 0x0 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a.." "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode write transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode write transfer (CTRL.MODE is SPI): at the start of a write transfer BASE_WE_ADDR is copied to.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode read transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode read transfer (CTRL.MODE is SPI): at the start of a read transfer BASE_RD_ADDR is copied to.."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
|
|
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP." "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SPI_CTRL,SPI control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,Master ('1') or slave ('0') mode. In master mode transmission will commence on availability of data frames in the TX FIFO. In slave mode when selected and there is no data frame in the TX FIFO the slave will transmit all '1's. In both.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "SSEL_INTER_FRAME_DEL,Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "SSEL_HOLD_DEL,Indicates the SPI SELECT hold delay (between SPI clock edge to sample the last MISO bit and SELECT deactivation)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SSEL_SETUP_DEL,Indicates the SPI SELECT setup delay (between SELECT activation and SCLK clock edge to sample the first MISO bit)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SSEL_POLARITY3,Slave select polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SSEL_POLARITY2,Slave select polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSEL_POLARITY1,Slave select polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "SSEL_POLARITY0,Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SCLK_CONTINUOUS,Only applicable in master mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPOL,Indicates the clock polarity. This field together with the CPHA field indicates when MOSI data is driven and MISO data is captured:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPHA,Indicates the clock phase. This field together with the CPOL field indicates when MOSI data is driven and MISO data is captured:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "SPI_STATUS,SPI status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the design."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1') as clock domain.."
|
|
newline
|
|
bitfld.long 0x0 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes the busy bit is '1' when the slave selection is activated. For TI submode the busy bit is '1' from the time the.." "0,1"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "SPI_TX_CTRL,SPI transmitter control"
|
|
bitfld.long 0x0 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity." "0,1"
|
|
line.long 0x4 "SPI_RX_CTRL,SPI receiver control"
|
|
bitfld.long 0x4 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity." "0,1"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "UART_CTRL,UART control"
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). When '0' the transmitter TX line 'uart_tx_out' is connected to the TX pin and the receiver RX line 'uart_rx_in' is connected to the RX pin. When '1' the transmitter TX line.." "0,1"
|
|
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
|
|
bitfld.long 0x4 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode parity generation is always enabled through hardware. In IrDA submode parity generation is always disabled through hardware" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "UART_RX_CTRL,UART receiver control"
|
|
bitfld.long 0x8 24. "BREAK_LEVEL,0: low level pulse detection like Break field in LIN protocol" "0: low level pulse detection,1: high level pulse detection"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
|
|
newline
|
|
bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'. This functionality is intended.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode parity checking is always enabled through hardware. In IrDA submode parity checking is always disabled through hardware." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "UART_RX_STATUS,UART receiver status"
|
|
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of peripheral clock periods that constitute a bit period."
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "UART_FLOW_CTRL,UART flow control"
|
|
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal 'uart_cts_in' by the UART transmitter:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal 'uart_cts_in':" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal 'uart_rts_out':" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal 'uart_rts_out' is activated. By setting this field to '0' flow control is effectively SW disabled (may be useful for.."
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "I2C_CTRL,I2C control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. When '0' the I2C SCL and SDA lines are connected to the I2C SCL and SDA pins. When '1' I2C SCL and SDA lines are routed internally in.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,For internally clocked logic only. Only used when:" "0: clock stretching is performed,1: a received data element byte the slave is.."
|
|
newline
|
|
bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when:" "0: clock stretching is performed,1: a received"
|
|
newline
|
|
bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element byte the master is immediately NACK'd when the receiver FIFO is full. When '0' clock stretching is used instead (till the receiver FIFO is no longer full)." "0,1"
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full." "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 peripheral clock periods constitute the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median.."
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 peripheral clock periods constitute the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal.."
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rgroup.long 0x64++0x3
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|
line.long 0x0 "I2C_STATUS,I2C status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the.."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 2. "I2CS_IC_BUSY,Indicates whether the internally clocked slave logic is being accessed by external I2C master." "0,1"
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bitfld.long 0x0 1. "I2C_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the IP is disabled BUS_BUSY is '0'. After enabling.." "0,1"
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|
group.long 0x68++0xB
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|
line.long 0x0 "I2C_M_CMD,I2C master command"
|
|
bitfld.long 0x0 4. "M_STOP,When '1' attempt to transmit a STOP. When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 3. "M_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result bus idle detection is only.." "0,1"
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START.." "0,1"
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line.long 0x4 "I2C_S_CMD,I2C slave command"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher.." "0,1"
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative 'i2c_sda_out' filter delay:" "0,1,2,3"
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2." "0,1,2,3"
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1." "0,1,2,3"
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0." "0,1,2,3"
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,Selection of 'i2c_scl_in' filter delay:" "0,1"
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter." "0,1,2,3"
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newline
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,Selection of 'i2c_sda_in' filter delay:" "0,1"
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0,1,2,3"
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group.long 0x200++0x7
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line.long 0x0 "TX_CTRL,Transmitter control"
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only valid.."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX.TRIGGER is generated."
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rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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wgroup.long 0x240++0x3
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line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
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hexmask.long 0x0 0.--31. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only DATA[15:0] are used."
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group.long 0x300++0x7
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line.long 0x0 "RX_CTRL,Receiver control"
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bitfld.long 0x0 9. "MEDIAN,Median filter. When '1' a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However its requires higher oversampling values. For UART IrDA submode this field should.." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only.."
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX.TRIGGER is generated."
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rgroup.long 0x308++0x3
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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group.long 0x310++0x3
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line.long 0x0 "RX_MATCH,Slave address and mask"
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hexmask.long.byte 0x0 16.--23. 1. "MASK,Slave device address mask. This field is a mask that specifies which of the ADDR field bits in the ADDR field take part in the matching of the slave address: MATCH = ((ADDR & MASK) == ('slave address' & MASK))."
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,Slave device address."
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rgroup.long 0x340++0x7
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line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
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hexmask.long 0x0 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only.."
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line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
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hexmask.long 0x4 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' .."
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rgroup.long 0xE00++0x3
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line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
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bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
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group.long 0xE80++0x3
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
|
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
|
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group.long 0xE88++0x3
|
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line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
|
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xE8C++0x3
|
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line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
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group.long 0xEC0++0x3
|
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line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
|
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request when externally clocked selection is '1'." "0,1"
|
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group.long 0xEC8++0x3
|
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line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
|
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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rgroup.long 0xECC++0x3
|
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line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
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bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF00++0xB
|
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line.long 0x0 "INTR_M,Master interrupt request"
|
|
bitfld.long 0x0 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected." "0,1"
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_STOP,I2C master STOP. Set to '1' when the master has transmitted a STOP." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "I2C_ACK,I2C master acknowledgement. Set to '1' when the master receives a ACK (typically after the master transmitted the slave address or TX data)." "0,1"
|
|
newline
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bitfld.long 0x0 1. "I2C_NACK,I2C master negative acknowledgement. Set to '1' when the master receives a NACK (typically after the master transmitted the slave address or TX data)." "0,1"
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newline
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line." "0,1"
|
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line.long 0x4 "INTR_M_SET,Master interrupt set request"
|
|
bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
|
bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
|
line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred." "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred." "0,1"
|
|
newline
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. The Firmware may decide.." "0,1"
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newline
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bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
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newline
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,I2C slave matching address received. If CTRL.ADDR_ACCEPT the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
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newline
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bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
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newline
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bitfld.long 0x0 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
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newline
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bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
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newline
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bitfld.long 0x0 2. "I2C_ACK,I2C slave acknowledgement received. Set to '1' when the slave receives a ACK (typically after the slave transmitted TX data)." "0,1"
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newline
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bitfld.long 0x0 1. "I2C_NACK,I2C slave negative acknowledgement received. Set to '1' when the slave receives a NACK (typically after the slave transmitted TX data)." "0,1"
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newline
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
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line.long 0x4 "INTR_S_SET,Slave interrupt set request"
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bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
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bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xF4C++0x3
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line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
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bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xF80++0xB
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line.long 0x0 "INTR_TX,Transmitter interrupt request"
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bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to.." "0,1"
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newline
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bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1' when event is detected. Write with.." "0,1"
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newline
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bitfld.long 0x0 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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newline
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bitfld.long 0x0 7. "BLOCKED,AHB-Lite write transfer can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
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newline
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bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and EMPTY is '1'." "0,1"
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newline
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bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
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newline
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bitfld.long 0x0 4. "EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
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newline
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bitfld.long 0x0 1. "NOT_FULL,TX FIFO is not full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
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newline
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bitfld.long 0x0 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
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line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
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bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
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bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xF8C++0x3
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line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
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bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xFC0++0xB
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line.long 0x0 "INTR_RX,Receiver interrupt request"
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bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
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newline
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bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier.." "0,1"
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newline
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bitfld.long 0x0 9. "PARITY_ERROR,Parity error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame.." "0,1"
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newline
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bitfld.long 0x0 8. "FRAME_ERROR,Frame error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error:" "0,1"
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newline
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bitfld.long 0x0 7. "BLOCKED,AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
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newline
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bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
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newline
|
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bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full RX FIFO. Note: in I2C mode the OVERFLOW is set when a data frame is received and the RX FIFO is full independent of whether it is ACK'd or NACK'd." "0,1"
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newline
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bitfld.long 0x0 3. "FULL,RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
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newline
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bitfld.long 0x0 2. "NOT_EMPTY,RX FIFO is not empty." "0,1"
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newline
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bitfld.long 0x0 0. "TRIGGER,More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
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line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
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bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
|
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bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
|
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bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
|
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bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
|
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bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
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bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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rgroup.long 0xFCC++0x3
|
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line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
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bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
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newline
|
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bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
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newline
|
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bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
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newline
|
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bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
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newline
|
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bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
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tree.end
|
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tree "SCB1"
|
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base ad:0x40610000
|
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group.long 0x0++0x3
|
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line.long 0x0 "CTRL,Generic control"
|
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bitfld.long 0x0 31. "ENABLED,IP enabled ('1') or not ('0'). The proper order in which to initialize the IP is as follows:" "0,1"
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newline
|
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bitfld.long 0x0 28. "EC_ACCESS,used to enable I2CS_EC or SPIS_EC access to internal SRAM memory." "0: enable clock_scb_en,1: disable clock_scb_en"
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newline
|
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
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newline
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bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the MMIO SW accesses to EZ memory coincide/collide this bit determines whether a SW access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0')." "0,1"
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newline
|
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bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')." "0,1"
|
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newline
|
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bitfld.long 0x0 14.--15. "MEM_WIDTH,Determines the number of bits per FIFO data element." "0: 8-bit FIFO data elements. This mode provides the..,1: 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH..,2: 32-bit FIFO data elements. This mode provides..,3: N/A"
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newline
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bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0,1"
|
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newline
|
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bitfld.long 0x0 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1'). In EZ mode a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory.." "0,1"
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newline
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bitfld.long 0x0 9. "EC_OP_MODE,Internally clocked mode ('0') or externally clocked mode ('1') operation. In internally clocked mode the serial interface protocols run off the peripheral clock. In externally clocked mode the serial interface protocols run off the clock as.." "0,1"
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newline
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bitfld.long 0x0 8. "EC_AM_MODE,Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI). In internally clocked mode the serial interface protocols run off the peripheral clock. In externally clocked mode the serial interface.." "0,1"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
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rgroup.long 0x4++0x3
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line.long 0x0 "STATUS,Generic status"
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bitfld.long 0x0 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a.." "0,1"
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group.long 0x8++0x3
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line.long 0x0 "CMD_RESP_CTRL,Command/response control"
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hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode write transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode write transfer (CTRL.MODE is SPI): at the start of a write transfer BASE_WE_ADDR is copied to.."
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hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode read transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode read transfer (CTRL.MODE is SPI): at the start of a read transfer BASE_RD_ADDR is copied to.."
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rgroup.long 0xC++0x3
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line.long 0x0 "CMD_RESP_STATUS,Command/response status"
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bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note:" "0,1"
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bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP." "0,1"
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hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
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hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
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group.long 0x20++0x3
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line.long 0x0 "SPI_CTRL,SPI control"
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bitfld.long 0x0 31. "MASTER_MODE,Master ('1') or slave ('0') mode. In master mode transmission will commence on availability of data frames in the TX FIFO. In slave mode when selected and there is no data frame in the TX FIFO the slave will transmit all '1's. In both.." "0,1"
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bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0,1"
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bitfld.long 0x0 14. "SSEL_INTER_FRAME_DEL,Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation)." "0,1"
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bitfld.long 0x0 13. "SSEL_HOLD_DEL,Indicates the SPI SELECT hold delay (between SPI clock edge to sample the last MISO bit and SELECT deactivation)." "0,1"
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bitfld.long 0x0 12. "SSEL_SETUP_DEL,Indicates the SPI SELECT setup delay (between SELECT activation and SCLK clock edge to sample the first MISO bit)." "0,1"
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bitfld.long 0x0 11. "SSEL_POLARITY3,Slave select polarity." "0,1"
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bitfld.long 0x0 10. "SSEL_POLARITY2,Slave select polarity." "0,1"
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bitfld.long 0x0 9. "SSEL_POLARITY1,Slave select polarity." "0,1"
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bitfld.long 0x0 8. "SSEL_POLARITY0,Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes:" "0,1"
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bitfld.long 0x0 5. "SCLK_CONTINUOUS,Only applicable in master mode." "0,1"
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bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
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bitfld.long 0x0 3. "CPOL,Indicates the clock polarity. This field together with the CPHA field indicates when MOSI data is driven and MISO data is captured:" "0,1"
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bitfld.long 0x0 2. "CPHA,Indicates the clock phase. This field together with the CPOL field indicates when MOSI data is driven and MISO data is captured:" "0,1"
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bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
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bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
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rgroup.long 0x24++0x3
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line.long 0x0 "SPI_STATUS,SPI status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the design."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes the busy bit is '1' when the slave selection is activated. For TI submode the busy bit is '1' from the time the.." "0,1"
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group.long 0x28++0x7
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line.long 0x0 "SPI_TX_CTRL,SPI transmitter control"
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bitfld.long 0x0 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x0 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity." "0,1"
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line.long 0x4 "SPI_RX_CTRL,SPI receiver control"
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bitfld.long 0x4 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity." "0,1"
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group.long 0x40++0xB
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line.long 0x0 "UART_CTRL,UART control"
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). When '0' the transmitter TX line 'uart_tx_out' is connected to the TX pin and the receiver RX line 'uart_rx_in' is connected to the RX pin. When '1' the transmitter TX line.." "0,1"
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line.long 0x4 "UART_TX_CTRL,UART transmitter control"
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bitfld.long 0x4 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode." "0,1"
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode parity generation is always enabled through hardware. In IrDA submode parity generation is always disabled through hardware" "0,1"
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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line.long 0x8 "UART_RX_CTRL,UART receiver control"
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bitfld.long 0x8 24. "BREAK_LEVEL,0: low level pulse detection like Break field in LIN protocol" "0: low level pulse detection,1: high level pulse detection"
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hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
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bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'. This functionality is intended.." "0,1"
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is.." "0,1"
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames.." "0,1"
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bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality." "0,1"
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bitfld.long 0x8 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode parity checking is always enabled through hardware. In IrDA submode parity checking is always disabled through hardware." "0,1"
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newline
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bitfld.long 0x8 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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rgroup.long 0x4C++0x3
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line.long 0x0 "UART_RX_STATUS,UART receiver status"
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hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of peripheral clock periods that constitute a bit period."
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group.long 0x50++0x3
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line.long 0x0 "UART_FLOW_CTRL,UART flow control"
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bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal 'uart_cts_in' by the UART transmitter:" "0,1"
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newline
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal 'uart_cts_in':" "0,1"
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal 'uart_rts_out':" "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal 'uart_rts_out' is activated. By setting this field to '0' flow control is effectively SW disabled (may be useful for.."
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group.long 0x60++0x3
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line.long 0x0 "I2C_CTRL,I2C control"
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bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself." "0,1"
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bitfld.long 0x0 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')." "0,1"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. When '0' the I2C SCL and SDA lines are connected to the I2C SCL and SDA pins. When '1' I2C SCL and SDA lines are routed internally in.." "0,1"
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newline
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,For internally clocked logic only. Only used when:" "0: clock stretching is performed,1: a received data element byte the slave is.."
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when:" "0: clock stretching is performed,1: a received"
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element byte the master is immediately NACK'd when the receiver FIFO is full. When '0' clock stretching is used instead (till the receiver FIFO is no longer full)." "0,1"
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full." "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 peripheral clock periods constitute the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median.."
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 peripheral clock periods constitute the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal.."
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rgroup.long 0x64++0x3
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line.long 0x0 "I2C_STATUS,I2C status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the.."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START REPEATED START STOP or an address this field is '0''." "0,1"
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newline
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bitfld.long 0x0 2. "I2CS_IC_BUSY,Indicates whether the internally clocked slave logic is being accessed by external I2C master." "0,1"
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bitfld.long 0x0 1. "I2C_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the IP is disabled BUS_BUSY is '0'. After enabling.." "0,1"
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group.long 0x68++0xB
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line.long 0x0 "I2C_M_CMD,I2C master command"
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bitfld.long 0x0 4. "M_STOP,When '1' attempt to transmit a STOP. When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 3. "M_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result bus idle detection is only.." "0,1"
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START.." "0,1"
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line.long 0x4 "I2C_S_CMD,I2C slave command"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher.." "0,1"
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative 'i2c_sda_out' filter delay:" "0,1,2,3"
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2." "0,1,2,3"
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1." "0,1,2,3"
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0." "0,1,2,3"
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,Selection of 'i2c_scl_in' filter delay:" "0,1"
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter." "0,1,2,3"
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,Selection of 'i2c_sda_in' filter delay:" "0,1"
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0,1,2,3"
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group.long 0x200++0x7
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line.long 0x0 "TX_CTRL,Transmitter control"
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only valid.."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX.TRIGGER is generated."
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rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
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newline
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
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newline
|
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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|
wgroup.long 0x240++0x3
|
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line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
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|
hexmask.long 0x0 0.--31. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only DATA[15:0] are used."
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group.long 0x300++0x7
|
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line.long 0x0 "RX_CTRL,Receiver control"
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bitfld.long 0x0 9. "MEDIAN,Median filter. When '1' a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However its requires higher oversampling values. For UART IrDA submode this field should.." "0,1"
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newline
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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newline
|
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only.."
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer." "0,1"
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|
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bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX.TRIGGER is generated."
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rgroup.long 0x308++0x3
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
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newline
|
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
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newline
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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group.long 0x310++0x3
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line.long 0x0 "RX_MATCH,Slave address and mask"
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hexmask.long.byte 0x0 16.--23. 1. "MASK,Slave device address mask. This field is a mask that specifies which of the ADDR field bits in the ADDR field take part in the matching of the slave address: MATCH = ((ADDR & MASK) == ('slave address' & MASK))."
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newline
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,Slave device address."
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rgroup.long 0x340++0x7
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line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
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hexmask.long 0x0 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only.."
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line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
|
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hexmask.long 0x4 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' .."
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rgroup.long 0xE00++0x3
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line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
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bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
|
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group.long 0xE80++0x3
|
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
|
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group.long 0xE88++0x3
|
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line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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rgroup.long 0xE8C++0x3
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line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
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group.long 0xEC0++0x3
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line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request when externally clocked selection is '1'." "0,1"
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|
group.long 0xEC8++0x3
|
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line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xECC++0x3
|
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line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
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group.long 0xF00++0xB
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line.long 0x0 "INTR_M,Master interrupt request"
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|
bitfld.long 0x0 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected." "0,1"
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newline
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)." "0,1"
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newline
|
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bitfld.long 0x0 4. "I2C_STOP,I2C master STOP. Set to '1' when the master has transmitted a STOP." "0,1"
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newline
|
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bitfld.long 0x0 2. "I2C_ACK,I2C master acknowledgement. Set to '1' when the master receives a ACK (typically after the master transmitted the slave address or TX data)." "0,1"
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newline
|
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bitfld.long 0x0 1. "I2C_NACK,I2C master negative acknowledgement. Set to '1' when the master receives a NACK (typically after the master transmitted the slave address or TX data)." "0,1"
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newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line." "0,1"
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line.long 0x4 "INTR_M_SET,Master interrupt set request"
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bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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line.long 0x8 "INTR_M_MASK,Master interrupt mask"
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bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
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line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
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bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
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newline
|
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
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newline
|
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bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
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newline
|
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bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
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line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
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newline
|
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bitfld.long 0x0 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred." "0,1"
|
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newline
|
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred." "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. The Firmware may decide.." "0,1"
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|
newline
|
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bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,I2C slave matching address received. If CTRL.ADDR_ACCEPT the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "I2C_ACK,I2C slave acknowledgement received. Set to '1' when the slave receives a ACK (typically after the slave transmitted TX data)." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "I2C_NACK,I2C slave negative acknowledgement received. Set to '1' when the slave receives a NACK (typically after the slave transmitted TX data)." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to.." "0,1"
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newline
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bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1' when event is detected. Write with.." "0,1"
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newline
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bitfld.long 0x0 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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newline
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bitfld.long 0x0 7. "BLOCKED,AHB-Lite write transfer can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
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newline
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bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and EMPTY is '1'." "0,1"
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newline
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bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
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newline
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bitfld.long 0x0 4. "EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
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newline
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bitfld.long 0x0 1. "NOT_FULL,TX FIFO is not full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
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newline
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bitfld.long 0x0 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
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line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
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bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
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bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xF8C++0x3
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line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
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bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xFC0++0xB
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line.long 0x0 "INTR_RX,Receiver interrupt request"
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bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
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newline
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bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier.." "0,1"
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newline
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bitfld.long 0x0 9. "PARITY_ERROR,Parity error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame.." "0,1"
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newline
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bitfld.long 0x0 8. "FRAME_ERROR,Frame error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error:" "0,1"
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newline
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bitfld.long 0x0 7. "BLOCKED,AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
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newline
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bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
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newline
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bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full RX FIFO. Note: in I2C mode the OVERFLOW is set when a data frame is received and the RX FIFO is full independent of whether it is ACK'd or NACK'd." "0,1"
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newline
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bitfld.long 0x0 3. "FULL,RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
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newline
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bitfld.long 0x0 2. "NOT_EMPTY,RX FIFO is not empty." "0,1"
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newline
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bitfld.long 0x0 0. "TRIGGER,More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
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line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
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bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
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bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xFCC++0x3
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line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
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bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
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tree.end
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tree "SCB2"
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base ad:0x40620000
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group.long 0x0++0x3
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line.long 0x0 "CTRL,Generic control"
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bitfld.long 0x0 31. "ENABLED,IP enabled ('1') or not ('0'). The proper order in which to initialize the IP is as follows:" "0,1"
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newline
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bitfld.long 0x0 28. "EC_ACCESS,used to enable I2CS_EC or SPIS_EC access to internal SRAM memory." "0: enable clock_scb_en,1: disable clock_scb_en"
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newline
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
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newline
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bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the MMIO SW accesses to EZ memory coincide/collide this bit determines whether a SW access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0')." "0,1"
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newline
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bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')." "0,1"
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newline
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bitfld.long 0x0 14.--15. "MEM_WIDTH,Determines the number of bits per FIFO data element." "0: 8-bit FIFO data elements. This mode provides the..,1: 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH..,2: 32-bit FIFO data elements. This mode provides..,3: N/A"
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newline
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bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0,1"
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newline
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bitfld.long 0x0 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1'). In EZ mode a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory.." "0,1"
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newline
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bitfld.long 0x0 9. "EC_OP_MODE,Internally clocked mode ('0') or externally clocked mode ('1') operation. In internally clocked mode the serial interface protocols run off the peripheral clock. In externally clocked mode the serial interface protocols run off the clock as.." "0,1"
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newline
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bitfld.long 0x0 8. "EC_AM_MODE,Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI). In internally clocked mode the serial interface protocols run off the peripheral clock. In externally clocked mode the serial interface.." "0,1"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
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rgroup.long 0x4++0x3
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line.long 0x0 "STATUS,Generic status"
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bitfld.long 0x0 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a.." "0,1"
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group.long 0x8++0x3
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line.long 0x0 "CMD_RESP_CTRL,Command/response control"
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hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode write transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode write transfer (CTRL.MODE is SPI): at the start of a write transfer BASE_WE_ADDR is copied to.."
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newline
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hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode read transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode read transfer (CTRL.MODE is SPI): at the start of a read transfer BASE_RD_ADDR is copied to.."
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rgroup.long 0xC++0x3
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line.long 0x0 "CMD_RESP_STATUS,Command/response status"
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bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note:" "0,1"
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newline
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bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP." "0,1"
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newline
|
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hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
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newline
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hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
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group.long 0x20++0x3
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line.long 0x0 "SPI_CTRL,SPI control"
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bitfld.long 0x0 31. "MASTER_MODE,Master ('1') or slave ('0') mode. In master mode transmission will commence on availability of data frames in the TX FIFO. In slave mode when selected and there is no data frame in the TX FIFO the slave will transmit all '1's. In both.." "0,1"
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newline
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bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
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newline
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0,1"
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newline
|
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bitfld.long 0x0 14. "SSEL_INTER_FRAME_DEL,Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation)." "0,1"
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newline
|
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bitfld.long 0x0 13. "SSEL_HOLD_DEL,Indicates the SPI SELECT hold delay (between SPI clock edge to sample the last MISO bit and SELECT deactivation)." "0,1"
|
|
newline
|
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bitfld.long 0x0 12. "SSEL_SETUP_DEL,Indicates the SPI SELECT setup delay (between SELECT activation and SCLK clock edge to sample the first MISO bit)." "0,1"
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newline
|
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bitfld.long 0x0 11. "SSEL_POLARITY3,Slave select polarity." "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "SSEL_POLARITY2,Slave select polarity." "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "SSEL_POLARITY1,Slave select polarity." "0,1"
|
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newline
|
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bitfld.long 0x0 8. "SSEL_POLARITY0,Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes:" "0,1"
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newline
|
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bitfld.long 0x0 5. "SCLK_CONTINUOUS,Only applicable in master mode." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
|
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newline
|
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bitfld.long 0x0 3. "CPOL,Indicates the clock polarity. This field together with the CPHA field indicates when MOSI data is driven and MISO data is captured:" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "CPHA,Indicates the clock phase. This field together with the CPOL field indicates when MOSI data is driven and MISO data is captured:" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
|
|
rgroup.long 0x24++0x3
|
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line.long 0x0 "SPI_STATUS,SPI status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the design."
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|
newline
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1') as clock domain.."
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newline
|
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bitfld.long 0x0 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are.." "0,1"
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|
newline
|
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bitfld.long 0x0 0. "BUS_BUSY,SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes the busy bit is '1' when the slave selection is activated. For TI submode the busy bit is '1' from the time the.." "0,1"
|
|
group.long 0x28++0x7
|
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line.long 0x0 "SPI_TX_CTRL,SPI transmitter control"
|
|
bitfld.long 0x0 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')." "0,1"
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newline
|
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bitfld.long 0x0 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity." "0,1"
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line.long 0x4 "SPI_RX_CTRL,SPI receiver control"
|
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bitfld.long 0x4 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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newline
|
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')." "0,1"
|
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newline
|
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity." "0,1"
|
|
group.long 0x40++0xB
|
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line.long 0x0 "UART_CTRL,UART control"
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). When '0' the transmitter TX line 'uart_tx_out' is connected to the TX pin and the receiver RX line 'uart_rx_in' is connected to the RX pin. When '1' the transmitter TX line.." "0,1"
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line.long 0x4 "UART_TX_CTRL,UART transmitter control"
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bitfld.long 0x4 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode." "0,1"
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode parity generation is always enabled through hardware. In IrDA submode parity generation is always disabled through hardware" "0,1"
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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line.long 0x8 "UART_RX_CTRL,UART receiver control"
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bitfld.long 0x8 24. "BREAK_LEVEL,0: low level pulse detection like Break field in LIN protocol" "0: low level pulse detection,1: high level pulse detection"
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hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
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bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'. This functionality is intended.." "0,1"
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is.." "0,1"
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames.." "0,1"
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bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality." "0,1"
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bitfld.long 0x8 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode parity checking is always enabled through hardware. In IrDA submode parity checking is always disabled through hardware." "0,1"
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bitfld.long 0x8 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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rgroup.long 0x4C++0x3
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line.long 0x0 "UART_RX_STATUS,UART receiver status"
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hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of peripheral clock periods that constitute a bit period."
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group.long 0x50++0x3
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line.long 0x0 "UART_FLOW_CTRL,UART flow control"
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bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal 'uart_cts_in' by the UART transmitter:" "0,1"
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal 'uart_cts_in':" "0,1"
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal 'uart_rts_out':" "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal 'uart_rts_out' is activated. By setting this field to '0' flow control is effectively SW disabled (may be useful for.."
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group.long 0x60++0x3
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line.long 0x0 "I2C_CTRL,I2C control"
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bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself." "0,1"
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bitfld.long 0x0 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. When '0' the I2C SCL and SDA lines are connected to the I2C SCL and SDA pins. When '1' I2C SCL and SDA lines are routed internally in.." "0,1"
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,For internally clocked logic only. Only used when:" "0: clock stretching is performed,1: a received data element byte the slave is.."
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when:" "0: clock stretching is performed,1: a received"
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element byte the master is immediately NACK'd when the receiver FIFO is full. When '0' clock stretching is used instead (till the receiver FIFO is no longer full)." "0,1"
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full." "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 peripheral clock periods constitute the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median.."
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 peripheral clock periods constitute the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal.."
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rgroup.long 0x64++0x3
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line.long 0x0 "I2C_STATUS,I2C status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the.."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 2. "I2CS_IC_BUSY,Indicates whether the internally clocked slave logic is being accessed by external I2C master." "0,1"
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bitfld.long 0x0 1. "I2C_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the IP is disabled BUS_BUSY is '0'. After enabling.." "0,1"
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group.long 0x68++0xB
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line.long 0x0 "I2C_M_CMD,I2C master command"
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bitfld.long 0x0 4. "M_STOP,When '1' attempt to transmit a STOP. When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 3. "M_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result bus idle detection is only.." "0,1"
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START.." "0,1"
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line.long 0x4 "I2C_S_CMD,I2C slave command"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher.." "0,1"
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative 'i2c_sda_out' filter delay:" "0,1,2,3"
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2." "0,1,2,3"
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1." "0,1,2,3"
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0." "0,1,2,3"
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,Selection of 'i2c_scl_in' filter delay:" "0,1"
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter." "0,1,2,3"
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,Selection of 'i2c_sda_in' filter delay:" "0,1"
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0,1,2,3"
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group.long 0x200++0x7
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line.long 0x0 "TX_CTRL,Transmitter control"
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only valid.."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX.TRIGGER is generated."
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rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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wgroup.long 0x240++0x3
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line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
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hexmask.long 0x0 0.--31. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only DATA[15:0] are used."
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group.long 0x300++0x7
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line.long 0x0 "RX_CTRL,Receiver control"
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bitfld.long 0x0 9. "MEDIAN,Median filter. When '1' a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However its requires higher oversampling values. For UART IrDA submode this field should.." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only.."
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX.TRIGGER is generated."
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rgroup.long 0x308++0x3
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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group.long 0x310++0x3
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line.long 0x0 "RX_MATCH,Slave address and mask"
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hexmask.long.byte 0x0 16.--23. 1. "MASK,Slave device address mask. This field is a mask that specifies which of the ADDR field bits in the ADDR field take part in the matching of the slave address: MATCH = ((ADDR & MASK) == ('slave address' & MASK))."
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,Slave device address."
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rgroup.long 0x340++0x7
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line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
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hexmask.long 0x0 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only.."
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line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
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hexmask.long 0x4 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' .."
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rgroup.long 0xE00++0x3
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line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
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bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
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group.long 0xE80++0x3
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
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group.long 0xE88++0x3
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line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xE8C++0x3
|
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line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xEC0++0x3
|
|
line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request when externally clocked selection is '1'." "0,1"
|
|
group.long 0xEC8++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xECC++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF00++0xB
|
|
line.long 0x0 "INTR_M,Master interrupt request"
|
|
bitfld.long 0x0 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,I2C master STOP. Set to '1' when the master has transmitted a STOP." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,I2C master acknowledgement. Set to '1' when the master receives a ACK (typically after the master transmitted the slave address or TX data)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,I2C master negative acknowledgement. Set to '1' when the master receives a NACK (typically after the master transmitted the slave address or TX data)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line." "0,1"
|
|
line.long 0x4 "INTR_M_SET,Master interrupt set request"
|
|
bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
|
bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
|
line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred." "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. The Firmware may decide.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
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|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,I2C slave matching address received. If CTRL.ADDR_ACCEPT the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,I2C slave acknowledgement received. Set to '1' when the slave receives a ACK (typically after the slave transmitted TX data)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,I2C slave negative acknowledgement received. Set to '1' when the slave receives a NACK (typically after the slave transmitted TX data)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1' when event is detected. Write with.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,AHB-Lite write transfer can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,TX FIFO is not full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
|
|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Parity error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Frame error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full RX FIFO. Note: in I2C mode the OVERFLOW is set when a data frame is received and the RX FIFO is full independent of whether it is ACK'd or NACK'd." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,RX FIFO is not empty." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TRIGGER,More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
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line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
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bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
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bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xFCC++0x3
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line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
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bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
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tree.end
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tree "SCB3"
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base ad:0x40630000
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group.long 0x0++0x3
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line.long 0x0 "CTRL,Generic control"
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bitfld.long 0x0 31. "ENABLED,IP enabled ('1') or not ('0'). The proper order in which to initialize the IP is as follows:" "0,1"
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newline
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bitfld.long 0x0 28. "EC_ACCESS,used to enable I2CS_EC or SPIS_EC access to internal SRAM memory." "0: enable clock_scb_en,1: disable clock_scb_en"
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newline
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
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newline
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bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the MMIO SW accesses to EZ memory coincide/collide this bit determines whether a SW access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0')." "0,1"
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newline
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bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')." "0,1"
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newline
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bitfld.long 0x0 14.--15. "MEM_WIDTH,Determines the number of bits per FIFO data element." "0: 8-bit FIFO data elements. This mode provides the..,1: 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH..,2: 32-bit FIFO data elements. This mode provides..,3: N/A"
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newline
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bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0,1"
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newline
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bitfld.long 0x0 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1'). In EZ mode a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory.." "0,1"
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newline
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bitfld.long 0x0 9. "EC_OP_MODE,Internally clocked mode ('0') or externally clocked mode ('1') operation. In internally clocked mode the serial interface protocols run off the peripheral clock. In externally clocked mode the serial interface protocols run off the clock as.." "0,1"
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newline
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bitfld.long 0x0 8. "EC_AM_MODE,Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI). In internally clocked mode the serial interface protocols run off the peripheral clock. In externally clocked mode the serial interface.." "0,1"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
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rgroup.long 0x4++0x3
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line.long 0x0 "STATUS,Generic status"
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bitfld.long 0x0 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a.." "0,1"
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group.long 0x8++0x3
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line.long 0x0 "CMD_RESP_CTRL,Command/response control"
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hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode write transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode write transfer (CTRL.MODE is SPI): at the start of a write transfer BASE_WE_ADDR is copied to.."
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newline
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hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode read transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode read transfer (CTRL.MODE is SPI): at the start of a read transfer BASE_RD_ADDR is copied to.."
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rgroup.long 0xC++0x3
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line.long 0x0 "CMD_RESP_STATUS,Command/response status"
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bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note:" "0,1"
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newline
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bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP." "0,1"
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newline
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hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
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newline
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hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
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group.long 0x20++0x3
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line.long 0x0 "SPI_CTRL,SPI control"
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bitfld.long 0x0 31. "MASTER_MODE,Master ('1') or slave ('0') mode. In master mode transmission will commence on availability of data frames in the TX FIFO. In slave mode when selected and there is no data frame in the TX FIFO the slave will transmit all '1's. In both.." "0,1"
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newline
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bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
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newline
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0,1"
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newline
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bitfld.long 0x0 14. "SSEL_INTER_FRAME_DEL,Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation)." "0,1"
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newline
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bitfld.long 0x0 13. "SSEL_HOLD_DEL,Indicates the SPI SELECT hold delay (between SPI clock edge to sample the last MISO bit and SELECT deactivation)." "0,1"
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newline
|
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bitfld.long 0x0 12. "SSEL_SETUP_DEL,Indicates the SPI SELECT setup delay (between SELECT activation and SCLK clock edge to sample the first MISO bit)." "0,1"
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newline
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bitfld.long 0x0 11. "SSEL_POLARITY3,Slave select polarity." "0,1"
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newline
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bitfld.long 0x0 10. "SSEL_POLARITY2,Slave select polarity." "0,1"
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newline
|
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bitfld.long 0x0 9. "SSEL_POLARITY1,Slave select polarity." "0,1"
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newline
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bitfld.long 0x0 8. "SSEL_POLARITY0,Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes:" "0,1"
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newline
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bitfld.long 0x0 5. "SCLK_CONTINUOUS,Only applicable in master mode." "0,1"
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newline
|
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bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
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newline
|
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bitfld.long 0x0 3. "CPOL,Indicates the clock polarity. This field together with the CPHA field indicates when MOSI data is driven and MISO data is captured:" "0,1"
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newline
|
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bitfld.long 0x0 2. "CPHA,Indicates the clock phase. This field together with the CPOL field indicates when MOSI data is driven and MISO data is captured:" "0,1"
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newline
|
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bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
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newline
|
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bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
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|
rgroup.long 0x24++0x3
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line.long 0x0 "SPI_STATUS,SPI status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the design."
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newline
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1') as clock domain.."
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newline
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bitfld.long 0x0 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are.." "0,1"
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newline
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bitfld.long 0x0 0. "BUS_BUSY,SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes the busy bit is '1' when the slave selection is activated. For TI submode the busy bit is '1' from the time the.." "0,1"
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group.long 0x28++0x7
|
|
line.long 0x0 "SPI_TX_CTRL,SPI transmitter control"
|
|
bitfld.long 0x0 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')." "0,1"
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newline
|
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bitfld.long 0x0 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity." "0,1"
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line.long 0x4 "SPI_RX_CTRL,SPI receiver control"
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bitfld.long 0x4 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
|
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newline
|
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')." "0,1"
|
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newline
|
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity." "0,1"
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group.long 0x40++0xB
|
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line.long 0x0 "UART_CTRL,UART control"
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
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newline
|
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). When '0' the transmitter TX line 'uart_tx_out' is connected to the TX pin and the receiver RX line 'uart_rx_in' is connected to the RX pin. When '1' the transmitter TX line.." "0,1"
|
|
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
|
|
bitfld.long 0x4 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode." "0,1"
|
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newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode parity generation is always enabled through hardware. In IrDA submode parity generation is always disabled through hardware" "0,1"
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newline
|
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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newline
|
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bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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line.long 0x8 "UART_RX_CTRL,UART receiver control"
|
|
bitfld.long 0x8 24. "BREAK_LEVEL,0: low level pulse detection like Break field in LIN protocol" "0: low level pulse detection,1: high level pulse detection"
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newline
|
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hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
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newline
|
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bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'. This functionality is intended.." "0,1"
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newline
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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newline
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bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is.." "0,1"
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newline
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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newline
|
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames.." "0,1"
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newline
|
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bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality." "0,1"
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newline
|
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bitfld.long 0x8 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode parity checking is always enabled through hardware. In IrDA submode parity checking is always disabled through hardware." "0,1"
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|
newline
|
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bitfld.long 0x8 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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newline
|
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bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "UART_RX_STATUS,UART receiver status"
|
|
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of peripheral clock periods that constitute a bit period."
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group.long 0x50++0x3
|
|
line.long 0x0 "UART_FLOW_CTRL,UART flow control"
|
|
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal 'uart_cts_in' by the UART transmitter:" "0,1"
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|
newline
|
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal 'uart_cts_in':" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal 'uart_rts_out':" "0,1"
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newline
|
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal 'uart_rts_out' is activated. By setting this field to '0' flow control is effectively SW disabled (may be useful for.."
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "I2C_CTRL,I2C control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself." "0,1"
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newline
|
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bitfld.long 0x0 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')." "0,1"
|
|
newline
|
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. When '0' the I2C SCL and SDA lines are connected to the I2C SCL and SDA pins. When '1' I2C SCL and SDA lines are routed internally in.." "0,1"
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newline
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,For internally clocked logic only. Only used when:" "0: clock stretching is performed,1: a received data element byte the slave is.."
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newline
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when:" "0: clock stretching is performed,1: a received"
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newline
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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newline
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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newline
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
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newline
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element byte the master is immediately NACK'd when the receiver FIFO is full. When '0' clock stretching is used instead (till the receiver FIFO is no longer full)." "0,1"
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newline
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full." "0,1"
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newline
|
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 peripheral clock periods constitute the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median.."
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newline
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 peripheral clock periods constitute the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal.."
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rgroup.long 0x64++0x3
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line.long 0x0 "I2C_STATUS,I2C status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the.."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 2. "I2CS_IC_BUSY,Indicates whether the internally clocked slave logic is being accessed by external I2C master." "0,1"
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bitfld.long 0x0 1. "I2C_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the IP is disabled BUS_BUSY is '0'. After enabling.." "0,1"
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group.long 0x68++0xB
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line.long 0x0 "I2C_M_CMD,I2C master command"
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bitfld.long 0x0 4. "M_STOP,When '1' attempt to transmit a STOP. When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 3. "M_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result bus idle detection is only.." "0,1"
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START.." "0,1"
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line.long 0x4 "I2C_S_CMD,I2C slave command"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher.." "0,1"
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative 'i2c_sda_out' filter delay:" "0,1,2,3"
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2." "0,1,2,3"
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1." "0,1,2,3"
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0." "0,1,2,3"
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,Selection of 'i2c_scl_in' filter delay:" "0,1"
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter." "0,1,2,3"
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newline
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,Selection of 'i2c_sda_in' filter delay:" "0,1"
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0,1,2,3"
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group.long 0x200++0x7
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line.long 0x0 "TX_CTRL,Transmitter control"
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only valid.."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX.TRIGGER is generated."
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rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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wgroup.long 0x240++0x3
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line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
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hexmask.long 0x0 0.--31. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only DATA[15:0] are used."
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group.long 0x300++0x7
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line.long 0x0 "RX_CTRL,Receiver control"
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bitfld.long 0x0 9. "MEDIAN,Median filter. When '1' a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However its requires higher oversampling values. For UART IrDA submode this field should.." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only.."
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX.TRIGGER is generated."
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rgroup.long 0x308++0x3
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
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newline
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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group.long 0x310++0x3
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line.long 0x0 "RX_MATCH,Slave address and mask"
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hexmask.long.byte 0x0 16.--23. 1. "MASK,Slave device address mask. This field is a mask that specifies which of the ADDR field bits in the ADDR field take part in the matching of the slave address: MATCH = ((ADDR & MASK) == ('slave address' & MASK))."
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,Slave device address."
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rgroup.long 0x340++0x7
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line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
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hexmask.long 0x0 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only.."
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line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
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hexmask.long 0x4 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' .."
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rgroup.long 0xE00++0x3
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line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
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bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
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group.long 0xE80++0x3
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
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group.long 0xE88++0x3
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line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xE8C++0x3
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line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
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bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xEC0++0x3
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line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request when externally clocked selection is '1'." "0,1"
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group.long 0xEC8++0x3
|
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line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xECC++0x3
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line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
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bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xF00++0xB
|
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line.long 0x0 "INTR_M,Master interrupt request"
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bitfld.long 0x0 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected." "0,1"
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)." "0,1"
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bitfld.long 0x0 4. "I2C_STOP,I2C master STOP. Set to '1' when the master has transmitted a STOP." "0,1"
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|
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bitfld.long 0x0 2. "I2C_ACK,I2C master acknowledgement. Set to '1' when the master receives a ACK (typically after the master transmitted the slave address or TX data)." "0,1"
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bitfld.long 0x0 1. "I2C_NACK,I2C master negative acknowledgement. Set to '1' when the master receives a NACK (typically after the master transmitted the slave address or TX data)." "0,1"
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newline
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line." "0,1"
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line.long 0x4 "INTR_M_SET,Master interrupt set request"
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bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
|
bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
|
line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
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|
newline
|
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bitfld.long 0x0 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred." "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred." "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. The Firmware may decide.." "0,1"
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bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,I2C slave matching address received. If CTRL.ADDR_ACCEPT the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
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newline
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bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
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newline
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bitfld.long 0x0 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
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|
newline
|
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bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
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newline
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bitfld.long 0x0 2. "I2C_ACK,I2C slave acknowledgement received. Set to '1' when the slave receives a ACK (typically after the slave transmitted TX data)." "0,1"
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newline
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bitfld.long 0x0 1. "I2C_NACK,I2C slave negative acknowledgement received. Set to '1' when the slave receives a NACK (typically after the slave transmitted TX data)." "0,1"
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newline
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
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|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
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|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
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bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xF4C++0x3
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line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
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bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xF80++0xB
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line.long 0x0 "INTR_TX,Transmitter interrupt request"
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bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to.." "0,1"
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newline
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bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1' when event is detected. Write with.." "0,1"
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newline
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bitfld.long 0x0 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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newline
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bitfld.long 0x0 7. "BLOCKED,AHB-Lite write transfer can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
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newline
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bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and EMPTY is '1'." "0,1"
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newline
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bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
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newline
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bitfld.long 0x0 4. "EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
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newline
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bitfld.long 0x0 1. "NOT_FULL,TX FIFO is not full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
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newline
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bitfld.long 0x0 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
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line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
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bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
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bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xF8C++0x3
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line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
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bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xFC0++0xB
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line.long 0x0 "INTR_RX,Receiver interrupt request"
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bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
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newline
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bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier.." "0,1"
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newline
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bitfld.long 0x0 9. "PARITY_ERROR,Parity error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame.." "0,1"
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newline
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bitfld.long 0x0 8. "FRAME_ERROR,Frame error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error:" "0,1"
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newline
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bitfld.long 0x0 7. "BLOCKED,AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
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newline
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bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
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newline
|
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bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full RX FIFO. Note: in I2C mode the OVERFLOW is set when a data frame is received and the RX FIFO is full independent of whether it is ACK'd or NACK'd." "0,1"
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newline
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bitfld.long 0x0 3. "FULL,RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
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newline
|
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bitfld.long 0x0 2. "NOT_EMPTY,RX FIFO is not empty." "0,1"
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newline
|
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bitfld.long 0x0 0. "TRIGGER,More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
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line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
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bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
|
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bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
|
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bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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|
newline
|
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
|
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bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
|
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bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
|
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bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
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bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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rgroup.long 0xFCC++0x3
|
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line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
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newline
|
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bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
tree "SCB4"
|
|
base ad:0x40640000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,IP enabled ('1') or not ('0'). The proper order in which to initialize the IP is as follows:" "0,1"
|
|
newline
|
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bitfld.long 0x0 28. "EC_ACCESS,used to enable I2CS_EC or SPIS_EC access to internal SRAM memory." "0: enable clock_scb_en,1: disable clock_scb_en"
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|
newline
|
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
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newline
|
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bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the MMIO SW accesses to EZ memory coincide/collide this bit determines whether a SW access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0')." "0,1"
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newline
|
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bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')." "0,1"
|
|
newline
|
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bitfld.long 0x0 14.--15. "MEM_WIDTH,Determines the number of bits per FIFO data element." "0: 8-bit FIFO data elements. This mode provides the..,1: 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH..,2: 32-bit FIFO data elements. This mode provides..,3: N/A"
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newline
|
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bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1'). In EZ mode a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory.." "0,1"
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newline
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bitfld.long 0x0 9. "EC_OP_MODE,Internally clocked mode ('0') or externally clocked mode ('1') operation. In internally clocked mode the serial interface protocols run off the peripheral clock. In externally clocked mode the serial interface protocols run off the clock as.." "0,1"
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newline
|
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bitfld.long 0x0 8. "EC_AM_MODE,Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI). In internally clocked mode the serial interface protocols run off the peripheral clock. In externally clocked mode the serial interface.." "0,1"
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newline
|
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hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
|
|
rgroup.long 0x4++0x3
|
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line.long 0x0 "STATUS,Generic status"
|
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bitfld.long 0x0 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a.." "0,1"
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|
group.long 0x8++0x3
|
|
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
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hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode write transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode write transfer (CTRL.MODE is SPI): at the start of a write transfer BASE_WE_ADDR is copied to.."
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hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode read transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode read transfer (CTRL.MODE is SPI): at the start of a read transfer BASE_RD_ADDR is copied to.."
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rgroup.long 0xC++0x3
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line.long 0x0 "CMD_RESP_STATUS,Command/response status"
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bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note:" "0,1"
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bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP." "0,1"
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hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
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hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
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group.long 0x20++0x3
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line.long 0x0 "SPI_CTRL,SPI control"
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bitfld.long 0x0 31. "MASTER_MODE,Master ('1') or slave ('0') mode. In master mode transmission will commence on availability of data frames in the TX FIFO. In slave mode when selected and there is no data frame in the TX FIFO the slave will transmit all '1's. In both.." "0,1"
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bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0,1"
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bitfld.long 0x0 14. "SSEL_INTER_FRAME_DEL,Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation)." "0,1"
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bitfld.long 0x0 13. "SSEL_HOLD_DEL,Indicates the SPI SELECT hold delay (between SPI clock edge to sample the last MISO bit and SELECT deactivation)." "0,1"
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bitfld.long 0x0 12. "SSEL_SETUP_DEL,Indicates the SPI SELECT setup delay (between SELECT activation and SCLK clock edge to sample the first MISO bit)." "0,1"
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bitfld.long 0x0 11. "SSEL_POLARITY3,Slave select polarity." "0,1"
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bitfld.long 0x0 10. "SSEL_POLARITY2,Slave select polarity." "0,1"
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bitfld.long 0x0 9. "SSEL_POLARITY1,Slave select polarity." "0,1"
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bitfld.long 0x0 8. "SSEL_POLARITY0,Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes:" "0,1"
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bitfld.long 0x0 5. "SCLK_CONTINUOUS,Only applicable in master mode." "0,1"
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bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
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bitfld.long 0x0 3. "CPOL,Indicates the clock polarity. This field together with the CPHA field indicates when MOSI data is driven and MISO data is captured:" "0,1"
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bitfld.long 0x0 2. "CPHA,Indicates the clock phase. This field together with the CPOL field indicates when MOSI data is driven and MISO data is captured:" "0,1"
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bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
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bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
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rgroup.long 0x24++0x3
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line.long 0x0 "SPI_STATUS,SPI status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the design."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes the busy bit is '1' when the slave selection is activated. For TI submode the busy bit is '1' from the time the.." "0,1"
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group.long 0x28++0x7
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line.long 0x0 "SPI_TX_CTRL,SPI transmitter control"
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bitfld.long 0x0 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x0 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity." "0,1"
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line.long 0x4 "SPI_RX_CTRL,SPI receiver control"
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bitfld.long 0x4 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity." "0,1"
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group.long 0x40++0xB
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line.long 0x0 "UART_CTRL,UART control"
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). When '0' the transmitter TX line 'uart_tx_out' is connected to the TX pin and the receiver RX line 'uart_rx_in' is connected to the RX pin. When '1' the transmitter TX line.." "0,1"
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line.long 0x4 "UART_TX_CTRL,UART transmitter control"
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bitfld.long 0x4 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode." "0,1"
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode parity generation is always enabled through hardware. In IrDA submode parity generation is always disabled through hardware" "0,1"
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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line.long 0x8 "UART_RX_CTRL,UART receiver control"
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bitfld.long 0x8 24. "BREAK_LEVEL,0: low level pulse detection like Break field in LIN protocol" "0: low level pulse detection,1: high level pulse detection"
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hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
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bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'. This functionality is intended.." "0,1"
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is.." "0,1"
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames.." "0,1"
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bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality." "0,1"
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bitfld.long 0x8 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode parity checking is always enabled through hardware. In IrDA submode parity checking is always disabled through hardware." "0,1"
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bitfld.long 0x8 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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rgroup.long 0x4C++0x3
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line.long 0x0 "UART_RX_STATUS,UART receiver status"
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hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of peripheral clock periods that constitute a bit period."
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group.long 0x50++0x3
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line.long 0x0 "UART_FLOW_CTRL,UART flow control"
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bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal 'uart_cts_in' by the UART transmitter:" "0,1"
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal 'uart_cts_in':" "0,1"
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal 'uart_rts_out':" "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal 'uart_rts_out' is activated. By setting this field to '0' flow control is effectively SW disabled (may be useful for.."
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group.long 0x60++0x3
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line.long 0x0 "I2C_CTRL,I2C control"
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bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself." "0,1"
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bitfld.long 0x0 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. When '0' the I2C SCL and SDA lines are connected to the I2C SCL and SDA pins. When '1' I2C SCL and SDA lines are routed internally in.." "0,1"
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,For internally clocked logic only. Only used when:" "0: clock stretching is performed,1: a received data element byte the slave is.."
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when:" "0: clock stretching is performed,1: a received"
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element byte the master is immediately NACK'd when the receiver FIFO is full. When '0' clock stretching is used instead (till the receiver FIFO is no longer full)." "0,1"
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full." "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 peripheral clock periods constitute the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median.."
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 peripheral clock periods constitute the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal.."
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rgroup.long 0x64++0x3
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line.long 0x0 "I2C_STATUS,I2C status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the.."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 2. "I2CS_IC_BUSY,Indicates whether the internally clocked slave logic is being accessed by external I2C master." "0,1"
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bitfld.long 0x0 1. "I2C_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the IP is disabled BUS_BUSY is '0'. After enabling.." "0,1"
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group.long 0x68++0xB
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line.long 0x0 "I2C_M_CMD,I2C master command"
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bitfld.long 0x0 4. "M_STOP,When '1' attempt to transmit a STOP. When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 3. "M_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result bus idle detection is only.." "0,1"
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START.." "0,1"
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line.long 0x4 "I2C_S_CMD,I2C slave command"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher.." "0,1"
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative 'i2c_sda_out' filter delay:" "0,1,2,3"
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2." "0,1,2,3"
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1." "0,1,2,3"
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0." "0,1,2,3"
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,Selection of 'i2c_scl_in' filter delay:" "0,1"
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter." "0,1,2,3"
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,Selection of 'i2c_sda_in' filter delay:" "0,1"
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0,1,2,3"
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group.long 0x200++0x7
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line.long 0x0 "TX_CTRL,Transmitter control"
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only valid.."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX.TRIGGER is generated."
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rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
|
|
wgroup.long 0x240++0x3
|
|
line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
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|
hexmask.long 0x0 0.--31. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only DATA[15:0] are used."
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|
group.long 0x300++0x7
|
|
line.long 0x0 "RX_CTRL,Receiver control"
|
|
bitfld.long 0x0 9. "MEDIAN,Median filter. When '1' a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However its requires higher oversampling values. For UART IrDA submode this field should.." "0,1"
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newline
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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|
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|
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only.."
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer." "0,1"
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|
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bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
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|
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|
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX.TRIGGER is generated."
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rgroup.long 0x308++0x3
|
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
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|
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
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|
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|
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
|
|
group.long 0x310++0x3
|
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line.long 0x0 "RX_MATCH,Slave address and mask"
|
|
hexmask.long.byte 0x0 16.--23. 1. "MASK,Slave device address mask. This field is a mask that specifies which of the ADDR field bits in the ADDR field take part in the matching of the slave address: MATCH = ((ADDR & MASK) == ('slave address' & MASK))."
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,Slave device address."
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rgroup.long 0x340++0x7
|
|
line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
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|
hexmask.long 0x0 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only.."
|
|
line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' .."
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|
rgroup.long 0xE00++0x3
|
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line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
|
|
bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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|
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
|
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|
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
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|
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
|
|
group.long 0xE80++0x3
|
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
|
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
|
|
group.long 0xE88++0x3
|
|
line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
|
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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rgroup.long 0xE8C++0x3
|
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line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
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group.long 0xEC0++0x3
|
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line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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|
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
|
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request when externally clocked selection is '1'." "0,1"
|
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group.long 0xEC8++0x3
|
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line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
|
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xECC++0x3
|
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line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
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group.long 0xF00++0xB
|
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line.long 0x0 "INTR_M,Master interrupt request"
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|
bitfld.long 0x0 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected." "0,1"
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newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)." "0,1"
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|
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bitfld.long 0x0 4. "I2C_STOP,I2C master STOP. Set to '1' when the master has transmitted a STOP." "0,1"
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|
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bitfld.long 0x0 2. "I2C_ACK,I2C master acknowledgement. Set to '1' when the master receives a ACK (typically after the master transmitted the slave address or TX data)." "0,1"
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newline
|
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bitfld.long 0x0 1. "I2C_NACK,I2C master negative acknowledgement. Set to '1' when the master receives a NACK (typically after the master transmitted the slave address or TX data)." "0,1"
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newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line." "0,1"
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line.long 0x4 "INTR_M_SET,Master interrupt set request"
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bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
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bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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rgroup.long 0xF0C++0x3
|
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line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
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bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
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newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
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newline
|
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
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line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
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newline
|
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bitfld.long 0x0 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred." "0,1"
|
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newline
|
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred." "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. The Firmware may decide.." "0,1"
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|
newline
|
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bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,I2C slave matching address received. If CTRL.ADDR_ACCEPT the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "I2C_ACK,I2C slave acknowledgement received. Set to '1' when the slave receives a ACK (typically after the slave transmitted TX data)." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "I2C_NACK,I2C slave negative acknowledgement received. Set to '1' when the slave receives a NACK (typically after the slave transmitted TX data)." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to.." "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1' when event is detected. Write with.." "0,1"
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newline
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bitfld.long 0x0 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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|
newline
|
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bitfld.long 0x0 7. "BLOCKED,AHB-Lite write transfer can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
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|
newline
|
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bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and EMPTY is '1'." "0,1"
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|
newline
|
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bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
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|
newline
|
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bitfld.long 0x0 4. "EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
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|
newline
|
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bitfld.long 0x0 1. "NOT_FULL,TX FIFO is not full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
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|
newline
|
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bitfld.long 0x0 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
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line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
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bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
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|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
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bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
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bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
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bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
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bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xF8C++0x3
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|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xFC0++0xB
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line.long 0x0 "INTR_RX,Receiver interrupt request"
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bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
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newline
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bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier.." "0,1"
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newline
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bitfld.long 0x0 9. "PARITY_ERROR,Parity error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame.." "0,1"
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newline
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bitfld.long 0x0 8. "FRAME_ERROR,Frame error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error:" "0,1"
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newline
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bitfld.long 0x0 7. "BLOCKED,AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
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newline
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bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
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newline
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bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full RX FIFO. Note: in I2C mode the OVERFLOW is set when a data frame is received and the RX FIFO is full independent of whether it is ACK'd or NACK'd." "0,1"
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newline
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bitfld.long 0x0 3. "FULL,RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
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newline
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bitfld.long 0x0 2. "NOT_EMPTY,RX FIFO is not empty." "0,1"
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newline
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bitfld.long 0x0 0. "TRIGGER,More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
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line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
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bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
|
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bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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|
newline
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bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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|
newline
|
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bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
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bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xFCC++0x3
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line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
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bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
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tree.end
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tree "SCB5"
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base ad:0x40650000
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group.long 0x0++0x3
|
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line.long 0x0 "CTRL,Generic control"
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bitfld.long 0x0 31. "ENABLED,IP enabled ('1') or not ('0'). The proper order in which to initialize the IP is as follows:" "0,1"
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newline
|
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bitfld.long 0x0 28. "EC_ACCESS,used to enable I2CS_EC or SPIS_EC access to internal SRAM memory." "0: enable clock_scb_en,1: disable clock_scb_en"
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newline
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
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newline
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bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the MMIO SW accesses to EZ memory coincide/collide this bit determines whether a SW access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0')." "0,1"
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newline
|
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bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')." "0,1"
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newline
|
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bitfld.long 0x0 14.--15. "MEM_WIDTH,Determines the number of bits per FIFO data element." "0: 8-bit FIFO data elements. This mode provides the..,1: 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH..,2: 32-bit FIFO data elements. This mode provides..,3: N/A"
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newline
|
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bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1'). In EZ mode a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory.." "0,1"
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newline
|
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bitfld.long 0x0 9. "EC_OP_MODE,Internally clocked mode ('0') or externally clocked mode ('1') operation. In internally clocked mode the serial interface protocols run off the peripheral clock. In externally clocked mode the serial interface protocols run off the clock as.." "0,1"
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newline
|
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bitfld.long 0x0 8. "EC_AM_MODE,Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI). In internally clocked mode the serial interface protocols run off the peripheral clock. In externally clocked mode the serial interface.." "0,1"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
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rgroup.long 0x4++0x3
|
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line.long 0x0 "STATUS,Generic status"
|
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bitfld.long 0x0 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a.." "0,1"
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group.long 0x8++0x3
|
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line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
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hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode write transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode write transfer (CTRL.MODE is SPI): at the start of a write transfer BASE_WE_ADDR is copied to.."
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newline
|
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hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode read transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode read transfer (CTRL.MODE is SPI): at the start of a read transfer BASE_RD_ADDR is copied to.."
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rgroup.long 0xC++0x3
|
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line.long 0x0 "CMD_RESP_STATUS,Command/response status"
|
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bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note:" "0,1"
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|
newline
|
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bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP." "0,1"
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|
newline
|
|
hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
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|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
|
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group.long 0x20++0x3
|
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line.long 0x0 "SPI_CTRL,SPI control"
|
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bitfld.long 0x0 31. "MASTER_MODE,Master ('1') or slave ('0') mode. In master mode transmission will commence on availability of data frames in the TX FIFO. In slave mode when selected and there is no data frame in the TX FIFO the slave will transmit all '1's. In both.." "0,1"
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|
newline
|
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bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
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newline
|
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
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newline
|
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0,1"
|
|
newline
|
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bitfld.long 0x0 14. "SSEL_INTER_FRAME_DEL,Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "SSEL_HOLD_DEL,Indicates the SPI SELECT hold delay (between SPI clock edge to sample the last MISO bit and SELECT deactivation)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SSEL_SETUP_DEL,Indicates the SPI SELECT setup delay (between SELECT activation and SCLK clock edge to sample the first MISO bit)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SSEL_POLARITY3,Slave select polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SSEL_POLARITY2,Slave select polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSEL_POLARITY1,Slave select polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "SSEL_POLARITY0,Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes:" "0,1"
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|
newline
|
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bitfld.long 0x0 5. "SCLK_CONTINUOUS,Only applicable in master mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPOL,Indicates the clock polarity. This field together with the CPHA field indicates when MOSI data is driven and MISO data is captured:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPHA,Indicates the clock phase. This field together with the CPOL field indicates when MOSI data is driven and MISO data is captured:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "SPI_STATUS,SPI status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the design."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1') as clock domain.."
|
|
newline
|
|
bitfld.long 0x0 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes the busy bit is '1' when the slave selection is activated. For TI submode the busy bit is '1' from the time the.." "0,1"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "SPI_TX_CTRL,SPI transmitter control"
|
|
bitfld.long 0x0 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity." "0,1"
|
|
line.long 0x4 "SPI_RX_CTRL,SPI receiver control"
|
|
bitfld.long 0x4 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity." "0,1"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "UART_CTRL,UART control"
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
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newline
|
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). When '0' the transmitter TX line 'uart_tx_out' is connected to the TX pin and the receiver RX line 'uart_rx_in' is connected to the RX pin. When '1' the transmitter TX line.." "0,1"
|
|
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
|
|
bitfld.long 0x4 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode." "0,1"
|
|
newline
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode parity generation is always enabled through hardware. In IrDA submode parity generation is always disabled through hardware" "0,1"
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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line.long 0x8 "UART_RX_CTRL,UART receiver control"
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bitfld.long 0x8 24. "BREAK_LEVEL,0: low level pulse detection like Break field in LIN protocol" "0: low level pulse detection,1: high level pulse detection"
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hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
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bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'. This functionality is intended.." "0,1"
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is.." "0,1"
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames.." "0,1"
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bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality." "0,1"
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bitfld.long 0x8 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode parity checking is always enabled through hardware. In IrDA submode parity checking is always disabled through hardware." "0,1"
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bitfld.long 0x8 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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rgroup.long 0x4C++0x3
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line.long 0x0 "UART_RX_STATUS,UART receiver status"
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hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of peripheral clock periods that constitute a bit period."
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group.long 0x50++0x3
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line.long 0x0 "UART_FLOW_CTRL,UART flow control"
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bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal 'uart_cts_in' by the UART transmitter:" "0,1"
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal 'uart_cts_in':" "0,1"
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal 'uart_rts_out':" "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal 'uart_rts_out' is activated. By setting this field to '0' flow control is effectively SW disabled (may be useful for.."
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group.long 0x60++0x3
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line.long 0x0 "I2C_CTRL,I2C control"
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bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself." "0,1"
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bitfld.long 0x0 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. When '0' the I2C SCL and SDA lines are connected to the I2C SCL and SDA pins. When '1' I2C SCL and SDA lines are routed internally in.." "0,1"
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,For internally clocked logic only. Only used when:" "0: clock stretching is performed,1: a received data element byte the slave is.."
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when:" "0: clock stretching is performed,1: a received"
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element byte the master is immediately NACK'd when the receiver FIFO is full. When '0' clock stretching is used instead (till the receiver FIFO is no longer full)." "0,1"
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full." "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 peripheral clock periods constitute the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median.."
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 peripheral clock periods constitute the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal.."
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rgroup.long 0x64++0x3
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line.long 0x0 "I2C_STATUS,I2C status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the.."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 2. "I2CS_IC_BUSY,Indicates whether the internally clocked slave logic is being accessed by external I2C master." "0,1"
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bitfld.long 0x0 1. "I2C_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the IP is disabled BUS_BUSY is '0'. After enabling.." "0,1"
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group.long 0x68++0xB
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line.long 0x0 "I2C_M_CMD,I2C master command"
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bitfld.long 0x0 4. "M_STOP,When '1' attempt to transmit a STOP. When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 3. "M_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result bus idle detection is only.." "0,1"
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START.." "0,1"
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line.long 0x4 "I2C_S_CMD,I2C slave command"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher.." "0,1"
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative 'i2c_sda_out' filter delay:" "0,1,2,3"
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2." "0,1,2,3"
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1." "0,1,2,3"
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0." "0,1,2,3"
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,Selection of 'i2c_scl_in' filter delay:" "0,1"
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter." "0,1,2,3"
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,Selection of 'i2c_sda_in' filter delay:" "0,1"
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0,1,2,3"
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group.long 0x200++0x7
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line.long 0x0 "TX_CTRL,Transmitter control"
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only valid.."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX.TRIGGER is generated."
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rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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wgroup.long 0x240++0x3
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line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
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hexmask.long 0x0 0.--31. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only DATA[15:0] are used."
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group.long 0x300++0x7
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line.long 0x0 "RX_CTRL,Receiver control"
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bitfld.long 0x0 9. "MEDIAN,Median filter. When '1' a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However its requires higher oversampling values. For UART IrDA submode this field should.." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only.."
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX.TRIGGER is generated."
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rgroup.long 0x308++0x3
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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group.long 0x310++0x3
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line.long 0x0 "RX_MATCH,Slave address and mask"
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hexmask.long.byte 0x0 16.--23. 1. "MASK,Slave device address mask. This field is a mask that specifies which of the ADDR field bits in the ADDR field take part in the matching of the slave address: MATCH = ((ADDR & MASK) == ('slave address' & MASK))."
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,Slave device address."
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rgroup.long 0x340++0x7
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line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
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hexmask.long 0x0 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only.."
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line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
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hexmask.long 0x4 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' .."
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rgroup.long 0xE00++0x3
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line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
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bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
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group.long 0xE80++0x3
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
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group.long 0xE88++0x3
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line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xE8C++0x3
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line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
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bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xEC0++0x3
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line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
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|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request when externally clocked selection is '1'." "0,1"
|
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group.long 0xEC8++0x3
|
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line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
|
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xECC++0x3
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line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF00++0xB
|
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line.long 0x0 "INTR_M,Master interrupt request"
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|
bitfld.long 0x0 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected." "0,1"
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newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)." "0,1"
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newline
|
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bitfld.long 0x0 4. "I2C_STOP,I2C master STOP. Set to '1' when the master has transmitted a STOP." "0,1"
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|
newline
|
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bitfld.long 0x0 2. "I2C_ACK,I2C master acknowledgement. Set to '1' when the master receives a ACK (typically after the master transmitted the slave address or TX data)." "0,1"
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newline
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bitfld.long 0x0 1. "I2C_NACK,I2C master negative acknowledgement. Set to '1' when the master receives a NACK (typically after the master transmitted the slave address or TX data)." "0,1"
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newline
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line." "0,1"
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line.long 0x4 "INTR_M_SET,Master interrupt set request"
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bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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line.long 0x8 "INTR_M_MASK,Master interrupt mask"
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bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
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line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
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newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
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line.long 0x0 "INTR_S,Slave interrupt request"
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bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
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newline
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bitfld.long 0x0 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred." "0,1"
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newline
|
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred." "0,1"
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newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. The Firmware may decide.." "0,1"
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newline
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bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
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newline
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,I2C slave matching address received. If CTRL.ADDR_ACCEPT the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
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newline
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bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
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newline
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bitfld.long 0x0 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
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newline
|
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bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
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newline
|
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bitfld.long 0x0 2. "I2C_ACK,I2C slave acknowledgement received. Set to '1' when the slave receives a ACK (typically after the slave transmitted TX data)." "0,1"
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newline
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bitfld.long 0x0 1. "I2C_NACK,I2C slave negative acknowledgement received. Set to '1' when the slave receives a NACK (typically after the slave transmitted TX data)." "0,1"
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newline
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
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line.long 0x4 "INTR_S_SET,Slave interrupt set request"
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bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
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bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
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line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
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line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to.." "0,1"
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|
newline
|
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bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1' when event is detected. Write with.." "0,1"
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newline
|
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bitfld.long 0x0 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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newline
|
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bitfld.long 0x0 7. "BLOCKED,AHB-Lite write transfer can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
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newline
|
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bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and EMPTY is '1'." "0,1"
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|
newline
|
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bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
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newline
|
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bitfld.long 0x0 4. "EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
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newline
|
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bitfld.long 0x0 1. "NOT_FULL,TX FIFO is not full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
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newline
|
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bitfld.long 0x0 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
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line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
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bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier.." "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "PARITY_ERROR,Parity error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame.." "0,1"
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|
newline
|
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bitfld.long 0x0 8. "FRAME_ERROR,Frame error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error:" "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "BLOCKED,AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full RX FIFO. Note: in I2C mode the OVERFLOW is set when a data frame is received and the RX FIFO is full independent of whether it is ACK'd or NACK'd." "0,1"
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|
newline
|
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bitfld.long 0x0 3. "FULL,RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
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|
newline
|
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bitfld.long 0x0 2. "NOT_EMPTY,RX FIFO is not empty." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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|
newline
|
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bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
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bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xFCC++0x3
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line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
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bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
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tree.end
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tree "SCB6"
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base ad:0x40660000
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group.long 0x0++0x3
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line.long 0x0 "CTRL,Generic control"
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bitfld.long 0x0 31. "ENABLED,IP enabled ('1') or not ('0'). The proper order in which to initialize the IP is as follows:" "0,1"
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newline
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bitfld.long 0x0 28. "EC_ACCESS,used to enable I2CS_EC or SPIS_EC access to internal SRAM memory." "0: enable clock_scb_en,1: disable clock_scb_en"
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newline
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
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newline
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bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the MMIO SW accesses to EZ memory coincide/collide this bit determines whether a SW access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0')." "0,1"
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newline
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bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')." "0,1"
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newline
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bitfld.long 0x0 14.--15. "MEM_WIDTH,Determines the number of bits per FIFO data element." "0: 8-bit FIFO data elements. This mode provides the..,1: 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH..,2: 32-bit FIFO data elements. This mode provides..,3: N/A"
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newline
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bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0,1"
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newline
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bitfld.long 0x0 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1'). In EZ mode a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory.." "0,1"
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newline
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bitfld.long 0x0 9. "EC_OP_MODE,Internally clocked mode ('0') or externally clocked mode ('1') operation. In internally clocked mode the serial interface protocols run off the peripheral clock. In externally clocked mode the serial interface protocols run off the clock as.." "0,1"
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newline
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bitfld.long 0x0 8. "EC_AM_MODE,Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI). In internally clocked mode the serial interface protocols run off the peripheral clock. In externally clocked mode the serial interface.." "0,1"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
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rgroup.long 0x4++0x3
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line.long 0x0 "STATUS,Generic status"
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bitfld.long 0x0 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a.." "0,1"
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group.long 0x8++0x3
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line.long 0x0 "CMD_RESP_CTRL,Command/response control"
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hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode write transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode write transfer (CTRL.MODE is SPI): at the start of a write transfer BASE_WE_ADDR is copied to.."
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newline
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hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode read transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode read transfer (CTRL.MODE is SPI): at the start of a read transfer BASE_RD_ADDR is copied to.."
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rgroup.long 0xC++0x3
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line.long 0x0 "CMD_RESP_STATUS,Command/response status"
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bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note:" "0,1"
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newline
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bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP." "0,1"
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newline
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hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
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newline
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hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
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group.long 0x20++0x3
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line.long 0x0 "SPI_CTRL,SPI control"
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bitfld.long 0x0 31. "MASTER_MODE,Master ('1') or slave ('0') mode. In master mode transmission will commence on availability of data frames in the TX FIFO. In slave mode when selected and there is no data frame in the TX FIFO the slave will transmit all '1's. In both.." "0,1"
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newline
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bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
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newline
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0,1"
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newline
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bitfld.long 0x0 14. "SSEL_INTER_FRAME_DEL,Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation)." "0,1"
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newline
|
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bitfld.long 0x0 13. "SSEL_HOLD_DEL,Indicates the SPI SELECT hold delay (between SPI clock edge to sample the last MISO bit and SELECT deactivation)." "0,1"
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newline
|
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bitfld.long 0x0 12. "SSEL_SETUP_DEL,Indicates the SPI SELECT setup delay (between SELECT activation and SCLK clock edge to sample the first MISO bit)." "0,1"
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newline
|
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bitfld.long 0x0 11. "SSEL_POLARITY3,Slave select polarity." "0,1"
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newline
|
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bitfld.long 0x0 10. "SSEL_POLARITY2,Slave select polarity." "0,1"
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newline
|
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bitfld.long 0x0 9. "SSEL_POLARITY1,Slave select polarity." "0,1"
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newline
|
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bitfld.long 0x0 8. "SSEL_POLARITY0,Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes:" "0,1"
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newline
|
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bitfld.long 0x0 5. "SCLK_CONTINUOUS,Only applicable in master mode." "0,1"
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newline
|
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bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
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newline
|
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bitfld.long 0x0 3. "CPOL,Indicates the clock polarity. This field together with the CPHA field indicates when MOSI data is driven and MISO data is captured:" "0,1"
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newline
|
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bitfld.long 0x0 2. "CPHA,Indicates the clock phase. This field together with the CPOL field indicates when MOSI data is driven and MISO data is captured:" "0,1"
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newline
|
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bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
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newline
|
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bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
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|
rgroup.long 0x24++0x3
|
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line.long 0x0 "SPI_STATUS,SPI status"
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|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the design."
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newline
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1') as clock domain.."
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newline
|
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bitfld.long 0x0 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are.." "0,1"
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|
newline
|
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bitfld.long 0x0 0. "BUS_BUSY,SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes the busy bit is '1' when the slave selection is activated. For TI submode the busy bit is '1' from the time the.." "0,1"
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|
group.long 0x28++0x7
|
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line.long 0x0 "SPI_TX_CTRL,SPI transmitter control"
|
|
bitfld.long 0x0 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')." "0,1"
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newline
|
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bitfld.long 0x0 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity." "0,1"
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line.long 0x4 "SPI_RX_CTRL,SPI receiver control"
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bitfld.long 0x4 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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|
newline
|
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')." "0,1"
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newline
|
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity." "0,1"
|
|
group.long 0x40++0xB
|
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line.long 0x0 "UART_CTRL,UART control"
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|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
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newline
|
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). When '0' the transmitter TX line 'uart_tx_out' is connected to the TX pin and the receiver RX line 'uart_rx_in' is connected to the RX pin. When '1' the transmitter TX line.." "0,1"
|
|
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
|
|
bitfld.long 0x4 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode parity generation is always enabled through hardware. In IrDA submode parity generation is always disabled through hardware" "0,1"
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|
newline
|
|
bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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|
newline
|
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bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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|
line.long 0x8 "UART_RX_CTRL,UART receiver control"
|
|
bitfld.long 0x8 24. "BREAK_LEVEL,0: low level pulse detection like Break field in LIN protocol" "0: low level pulse detection,1: high level pulse detection"
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newline
|
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hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
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newline
|
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bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'. This functionality is intended.." "0,1"
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newline
|
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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newline
|
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bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is.." "0,1"
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|
newline
|
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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|
newline
|
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames.." "0,1"
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|
newline
|
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bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality." "0,1"
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|
newline
|
|
bitfld.long 0x8 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode parity checking is always enabled through hardware. In IrDA submode parity checking is always disabled through hardware." "0,1"
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|
newline
|
|
bitfld.long 0x8 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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|
newline
|
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bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "UART_RX_STATUS,UART receiver status"
|
|
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of peripheral clock periods that constitute a bit period."
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|
group.long 0x50++0x3
|
|
line.long 0x0 "UART_FLOW_CTRL,UART flow control"
|
|
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal 'uart_cts_in' by the UART transmitter:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal 'uart_cts_in':" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal 'uart_rts_out':" "0,1"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal 'uart_rts_out' is activated. By setting this field to '0' flow control is effectively SW disabled (may be useful for.."
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|
group.long 0x60++0x3
|
|
line.long 0x0 "I2C_CTRL,I2C control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself." "0,1"
|
|
newline
|
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bitfld.long 0x0 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. When '0' the I2C SCL and SDA lines are connected to the I2C SCL and SDA pins. When '1' I2C SCL and SDA lines are routed internally in.." "0,1"
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newline
|
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,For internally clocked logic only. Only used when:" "0: clock stretching is performed,1: a received data element byte the slave is.."
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newline
|
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when:" "0: clock stretching is performed,1: a received"
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newline
|
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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newline
|
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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newline
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
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newline
|
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element byte the master is immediately NACK'd when the receiver FIFO is full. When '0' clock stretching is used instead (till the receiver FIFO is no longer full)." "0,1"
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newline
|
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full." "0,1"
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|
newline
|
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 peripheral clock periods constitute the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median.."
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newline
|
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 peripheral clock periods constitute the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal.."
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|
rgroup.long 0x64++0x3
|
|
line.long 0x0 "I2C_STATUS,I2C status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the.."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 2. "I2CS_IC_BUSY,Indicates whether the internally clocked slave logic is being accessed by external I2C master." "0,1"
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bitfld.long 0x0 1. "I2C_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the IP is disabled BUS_BUSY is '0'. After enabling.." "0,1"
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group.long 0x68++0xB
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line.long 0x0 "I2C_M_CMD,I2C master command"
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bitfld.long 0x0 4. "M_STOP,When '1' attempt to transmit a STOP. When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 3. "M_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result bus idle detection is only.." "0,1"
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START.." "0,1"
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line.long 0x4 "I2C_S_CMD,I2C slave command"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher.." "0,1"
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative 'i2c_sda_out' filter delay:" "0,1,2,3"
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2." "0,1,2,3"
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1." "0,1,2,3"
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0." "0,1,2,3"
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,Selection of 'i2c_scl_in' filter delay:" "0,1"
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter." "0,1,2,3"
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,Selection of 'i2c_sda_in' filter delay:" "0,1"
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0,1,2,3"
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group.long 0x200++0x7
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line.long 0x0 "TX_CTRL,Transmitter control"
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only valid.."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX.TRIGGER is generated."
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rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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wgroup.long 0x240++0x3
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line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
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hexmask.long 0x0 0.--31. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only DATA[15:0] are used."
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group.long 0x300++0x7
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line.long 0x0 "RX_CTRL,Receiver control"
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bitfld.long 0x0 9. "MEDIAN,Median filter. When '1' a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However its requires higher oversampling values. For UART IrDA submode this field should.." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only.."
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX.TRIGGER is generated."
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rgroup.long 0x308++0x3
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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group.long 0x310++0x3
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line.long 0x0 "RX_MATCH,Slave address and mask"
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hexmask.long.byte 0x0 16.--23. 1. "MASK,Slave device address mask. This field is a mask that specifies which of the ADDR field bits in the ADDR field take part in the matching of the slave address: MATCH = ((ADDR & MASK) == ('slave address' & MASK))."
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,Slave device address."
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rgroup.long 0x340++0x7
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line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
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hexmask.long 0x0 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only.."
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line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
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hexmask.long 0x4 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' .."
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rgroup.long 0xE00++0x3
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line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
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bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
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group.long 0xE80++0x3
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
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group.long 0xE88++0x3
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line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xE8C++0x3
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line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
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bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xEC0++0x3
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line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request when externally clocked selection is '1'." "0,1"
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group.long 0xEC8++0x3
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line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xECC++0x3
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line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
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bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xF00++0xB
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line.long 0x0 "INTR_M,Master interrupt request"
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bitfld.long 0x0 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected." "0,1"
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)." "0,1"
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bitfld.long 0x0 4. "I2C_STOP,I2C master STOP. Set to '1' when the master has transmitted a STOP." "0,1"
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bitfld.long 0x0 2. "I2C_ACK,I2C master acknowledgement. Set to '1' when the master receives a ACK (typically after the master transmitted the slave address or TX data)." "0,1"
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bitfld.long 0x0 1. "I2C_NACK,I2C master negative acknowledgement. Set to '1' when the master receives a NACK (typically after the master transmitted the slave address or TX data)." "0,1"
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line." "0,1"
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line.long 0x4 "INTR_M_SET,Master interrupt set request"
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bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_M_MASK,Master interrupt mask"
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bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xF0C++0x3
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line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
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bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xF40++0xB
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line.long 0x0 "INTR_S,Slave interrupt request"
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bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
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bitfld.long 0x0 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred." "0,1"
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred." "0,1"
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. The Firmware may decide.." "0,1"
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bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,I2C slave matching address received. If CTRL.ADDR_ACCEPT the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
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bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
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bitfld.long 0x0 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
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newline
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bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
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newline
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bitfld.long 0x0 2. "I2C_ACK,I2C slave acknowledgement received. Set to '1' when the slave receives a ACK (typically after the slave transmitted TX data)." "0,1"
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newline
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bitfld.long 0x0 1. "I2C_NACK,I2C slave negative acknowledgement received. Set to '1' when the slave receives a NACK (typically after the slave transmitted TX data)." "0,1"
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newline
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
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line.long 0x4 "INTR_S_SET,Slave interrupt set request"
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bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
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bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xF4C++0x3
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line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
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bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xF80++0xB
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line.long 0x0 "INTR_TX,Transmitter interrupt request"
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bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to.." "0,1"
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newline
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bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1' when event is detected. Write with.." "0,1"
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newline
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bitfld.long 0x0 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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newline
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bitfld.long 0x0 7. "BLOCKED,AHB-Lite write transfer can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
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bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and EMPTY is '1'." "0,1"
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newline
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bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
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bitfld.long 0x0 4. "EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
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newline
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bitfld.long 0x0 1. "NOT_FULL,TX FIFO is not full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
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newline
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bitfld.long 0x0 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
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line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
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bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
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bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xF8C++0x3
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line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
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bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xFC0++0xB
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line.long 0x0 "INTR_RX,Receiver interrupt request"
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bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
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newline
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bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier.." "0,1"
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newline
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bitfld.long 0x0 9. "PARITY_ERROR,Parity error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame.." "0,1"
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newline
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bitfld.long 0x0 8. "FRAME_ERROR,Frame error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error:" "0,1"
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newline
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bitfld.long 0x0 7. "BLOCKED,AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
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newline
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bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
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newline
|
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bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full RX FIFO. Note: in I2C mode the OVERFLOW is set when a data frame is received and the RX FIFO is full independent of whether it is ACK'd or NACK'd." "0,1"
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newline
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bitfld.long 0x0 3. "FULL,RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
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newline
|
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bitfld.long 0x0 2. "NOT_EMPTY,RX FIFO is not empty." "0,1"
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newline
|
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bitfld.long 0x0 0. "TRIGGER,More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
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line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
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bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
|
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bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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|
newline
|
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bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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|
newline
|
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bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
|
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bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
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newline
|
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bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
|
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
|
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bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
|
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bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
|
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bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
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bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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rgroup.long 0xFCC++0x3
|
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line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
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newline
|
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bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
tree "SCB7"
|
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base ad:0x40670000
|
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group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,IP enabled ('1') or not ('0'). The proper order in which to initialize the IP is as follows:" "0,1"
|
|
newline
|
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bitfld.long 0x0 28. "EC_ACCESS,used to enable I2CS_EC or SPIS_EC access to internal SRAM memory." "0: enable clock_scb_en,1: disable clock_scb_en"
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newline
|
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
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|
newline
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bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the MMIO SW accesses to EZ memory coincide/collide this bit determines whether a SW access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0')." "0,1"
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newline
|
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bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')." "0,1"
|
|
newline
|
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bitfld.long 0x0 14.--15. "MEM_WIDTH,Determines the number of bits per FIFO data element." "0: 8-bit FIFO data elements. This mode provides the..,1: 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH..,2: 32-bit FIFO data elements. This mode provides..,3: N/A"
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newline
|
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bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1'). In EZ mode a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory.." "0,1"
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newline
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bitfld.long 0x0 9. "EC_OP_MODE,Internally clocked mode ('0') or externally clocked mode ('1') operation. In internally clocked mode the serial interface protocols run off the peripheral clock. In externally clocked mode the serial interface protocols run off the clock as.." "0,1"
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newline
|
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bitfld.long 0x0 8. "EC_AM_MODE,Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI). In internally clocked mode the serial interface protocols run off the peripheral clock. In externally clocked mode the serial interface.." "0,1"
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newline
|
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hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
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rgroup.long 0x4++0x3
|
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line.long 0x0 "STATUS,Generic status"
|
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bitfld.long 0x0 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a.." "0,1"
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|
group.long 0x8++0x3
|
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line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode write transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode write transfer (CTRL.MODE is SPI): at the start of a write transfer BASE_WE_ADDR is copied to.."
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newline
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hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode read transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode read transfer (CTRL.MODE is SPI): at the start of a read transfer BASE_RD_ADDR is copied to.."
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rgroup.long 0xC++0x3
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line.long 0x0 "CMD_RESP_STATUS,Command/response status"
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bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note:" "0,1"
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bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP." "0,1"
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hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
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hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
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group.long 0x20++0x3
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line.long 0x0 "SPI_CTRL,SPI control"
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bitfld.long 0x0 31. "MASTER_MODE,Master ('1') or slave ('0') mode. In master mode transmission will commence on availability of data frames in the TX FIFO. In slave mode when selected and there is no data frame in the TX FIFO the slave will transmit all '1's. In both.." "0,1"
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bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0,1"
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bitfld.long 0x0 14. "SSEL_INTER_FRAME_DEL,Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation)." "0,1"
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bitfld.long 0x0 13. "SSEL_HOLD_DEL,Indicates the SPI SELECT hold delay (between SPI clock edge to sample the last MISO bit and SELECT deactivation)." "0,1"
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bitfld.long 0x0 12. "SSEL_SETUP_DEL,Indicates the SPI SELECT setup delay (between SELECT activation and SCLK clock edge to sample the first MISO bit)." "0,1"
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bitfld.long 0x0 11. "SSEL_POLARITY3,Slave select polarity." "0,1"
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bitfld.long 0x0 10. "SSEL_POLARITY2,Slave select polarity." "0,1"
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bitfld.long 0x0 9. "SSEL_POLARITY1,Slave select polarity." "0,1"
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bitfld.long 0x0 8. "SSEL_POLARITY0,Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes:" "0,1"
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bitfld.long 0x0 5. "SCLK_CONTINUOUS,Only applicable in master mode." "0,1"
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bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
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bitfld.long 0x0 3. "CPOL,Indicates the clock polarity. This field together with the CPHA field indicates when MOSI data is driven and MISO data is captured:" "0,1"
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bitfld.long 0x0 2. "CPHA,Indicates the clock phase. This field together with the CPOL field indicates when MOSI data is driven and MISO data is captured:" "0,1"
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bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
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bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
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rgroup.long 0x24++0x3
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line.long 0x0 "SPI_STATUS,SPI status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the design."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes the busy bit is '1' when the slave selection is activated. For TI submode the busy bit is '1' from the time the.." "0,1"
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group.long 0x28++0x7
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line.long 0x0 "SPI_TX_CTRL,SPI transmitter control"
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bitfld.long 0x0 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x0 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity." "0,1"
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line.long 0x4 "SPI_RX_CTRL,SPI receiver control"
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bitfld.long 0x4 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity." "0,1"
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group.long 0x40++0xB
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line.long 0x0 "UART_CTRL,UART control"
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). When '0' the transmitter TX line 'uart_tx_out' is connected to the TX pin and the receiver RX line 'uart_rx_in' is connected to the RX pin. When '1' the transmitter TX line.." "0,1"
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line.long 0x4 "UART_TX_CTRL,UART transmitter control"
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bitfld.long 0x4 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode." "0,1"
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode parity generation is always enabled through hardware. In IrDA submode parity generation is always disabled through hardware" "0,1"
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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line.long 0x8 "UART_RX_CTRL,UART receiver control"
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bitfld.long 0x8 24. "BREAK_LEVEL,0: low level pulse detection like Break field in LIN protocol" "0: low level pulse detection,1: high level pulse detection"
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hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
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bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'. This functionality is intended.." "0,1"
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is.." "0,1"
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames.." "0,1"
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bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality." "0,1"
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bitfld.long 0x8 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode parity checking is always enabled through hardware. In IrDA submode parity checking is always disabled through hardware." "0,1"
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bitfld.long 0x8 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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rgroup.long 0x4C++0x3
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line.long 0x0 "UART_RX_STATUS,UART receiver status"
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hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of peripheral clock periods that constitute a bit period."
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group.long 0x50++0x3
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line.long 0x0 "UART_FLOW_CTRL,UART flow control"
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bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal 'uart_cts_in' by the UART transmitter:" "0,1"
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal 'uart_cts_in':" "0,1"
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal 'uart_rts_out':" "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal 'uart_rts_out' is activated. By setting this field to '0' flow control is effectively SW disabled (may be useful for.."
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group.long 0x60++0x3
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line.long 0x0 "I2C_CTRL,I2C control"
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bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself." "0,1"
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bitfld.long 0x0 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. When '0' the I2C SCL and SDA lines are connected to the I2C SCL and SDA pins. When '1' I2C SCL and SDA lines are routed internally in.." "0,1"
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,For internally clocked logic only. Only used when:" "0: clock stretching is performed,1: a received data element byte the slave is.."
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when:" "0: clock stretching is performed,1: a received"
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element byte the master is immediately NACK'd when the receiver FIFO is full. When '0' clock stretching is used instead (till the receiver FIFO is no longer full)." "0,1"
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full." "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 peripheral clock periods constitute the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median.."
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 peripheral clock periods constitute the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal.."
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rgroup.long 0x64++0x3
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line.long 0x0 "I2C_STATUS,I2C status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the.."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 2. "I2CS_IC_BUSY,Indicates whether the internally clocked slave logic is being accessed by external I2C master." "0,1"
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bitfld.long 0x0 1. "I2C_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the IP is disabled BUS_BUSY is '0'. After enabling.." "0,1"
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group.long 0x68++0xB
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line.long 0x0 "I2C_M_CMD,I2C master command"
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bitfld.long 0x0 4. "M_STOP,When '1' attempt to transmit a STOP. When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 3. "M_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result bus idle detection is only.." "0,1"
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START.." "0,1"
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line.long 0x4 "I2C_S_CMD,I2C slave command"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher.." "0,1"
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative 'i2c_sda_out' filter delay:" "0,1,2,3"
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2." "0,1,2,3"
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1." "0,1,2,3"
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0." "0,1,2,3"
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,Selection of 'i2c_scl_in' filter delay:" "0,1"
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter." "0,1,2,3"
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,Selection of 'i2c_sda_in' filter delay:" "0,1"
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0,1,2,3"
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group.long 0x200++0x7
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line.long 0x0 "TX_CTRL,Transmitter control"
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only valid.."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX.TRIGGER is generated."
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rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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wgroup.long 0x240++0x3
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line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
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hexmask.long 0x0 0.--31. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only DATA[15:0] are used."
|
|
group.long 0x300++0x7
|
|
line.long 0x0 "RX_CTRL,Receiver control"
|
|
bitfld.long 0x0 9. "MEDIAN,Median filter. When '1' a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However its requires higher oversampling values. For UART IrDA submode this field should.." "0,1"
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|
newline
|
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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|
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|
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only.."
|
|
line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
|
|
bitfld.long 0x4 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer." "0,1"
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|
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bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
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|
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|
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX.TRIGGER is generated."
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rgroup.long 0x308++0x3
|
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
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newline
|
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
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|
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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|
group.long 0x310++0x3
|
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line.long 0x0 "RX_MATCH,Slave address and mask"
|
|
hexmask.long.byte 0x0 16.--23. 1. "MASK,Slave device address mask. This field is a mask that specifies which of the ADDR field bits in the ADDR field take part in the matching of the slave address: MATCH = ((ADDR & MASK) == ('slave address' & MASK))."
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|
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,Slave device address."
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rgroup.long 0x340++0x7
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line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
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hexmask.long 0x0 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only.."
|
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line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' .."
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|
rgroup.long 0xE00++0x3
|
|
line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
|
|
bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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|
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
|
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newline
|
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
|
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newline
|
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
|
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newline
|
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
|
|
group.long 0xE80++0x3
|
|
line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
|
|
group.long 0xE88++0x3
|
|
line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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rgroup.long 0xE8C++0x3
|
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line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
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group.long 0xEC0++0x3
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line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request when externally clocked selection is '1'." "0,1"
|
|
group.long 0xEC8++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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rgroup.long 0xECC++0x3
|
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line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
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group.long 0xF00++0xB
|
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line.long 0x0 "INTR_M,Master interrupt request"
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|
bitfld.long 0x0 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected." "0,1"
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newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)." "0,1"
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newline
|
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bitfld.long 0x0 4. "I2C_STOP,I2C master STOP. Set to '1' when the master has transmitted a STOP." "0,1"
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newline
|
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bitfld.long 0x0 2. "I2C_ACK,I2C master acknowledgement. Set to '1' when the master receives a ACK (typically after the master transmitted the slave address or TX data)." "0,1"
|
|
newline
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bitfld.long 0x0 1. "I2C_NACK,I2C master negative acknowledgement. Set to '1' when the master receives a NACK (typically after the master transmitted the slave address or TX data)." "0,1"
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newline
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line." "0,1"
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line.long 0x4 "INTR_M_SET,Master interrupt set request"
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bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
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bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
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line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
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line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
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|
newline
|
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bitfld.long 0x0 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred." "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred." "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. The Firmware may decide.." "0,1"
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|
newline
|
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bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,I2C slave matching address received. If CTRL.ADDR_ACCEPT the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "I2C_ACK,I2C slave acknowledgement received. Set to '1' when the slave receives a ACK (typically after the slave transmitted TX data)." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "I2C_NACK,I2C slave negative acknowledgement received. Set to '1' when the slave receives a NACK (typically after the slave transmitted TX data)." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to.." "0,1"
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|
newline
|
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bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1' when event is detected. Write with.." "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,AHB-Lite write transfer can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,TX FIFO is not full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
|
|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Parity error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Frame error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full RX FIFO. Note: in I2C mode the OVERFLOW is set when a data frame is received and the RX FIFO is full independent of whether it is ACK'd or NACK'd." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,RX FIFO is not empty." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "SMARTIO (Programmable IO Configuration)"
|
|
base ad:0x40320000
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40320000 ad:0x40320100 ad:0x40320200 ad:0x40320300 ad:0x40320400 ad:0x40320500 ad:0x40320600 ad:0x40320700 ad:0x40320800 ad:0x40320900 ad:0x40320A00 ad:0x40320B00 ad:0x40320C00 ad:0x40320D00 ad:0x40320E00 ad:0x40320F00)
|
|
tree "PRT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTL,Control register"
|
|
bitfld.long 0x0 31. "ENABLED,Enable for programmable IO. Should only be set to '1' when the programmable IO is completely configured:" "0,1"
|
|
bitfld.long 0x0 25. "PIPELINE_EN,Enable for pipeline register:" "0,1"
|
|
bitfld.long 0x0 24. "HLD_OVR,IO cell hold override functionality. In DeepSleep power mode the HSIOM holds the IO cell output and output enable signals if Active functionality is connected to the IO pads. This is undesirable if the SMARTIO is supposed to deliver DeepSleep.." "0,1"
|
|
hexmask.long.byte 0x0 8.--12. 1. "CLOCK_SRC,Clock ('clk_fabric') and reset ('rst_fabric_n') source selection:"
|
|
hexmask.long.byte 0x0 0.--7. 1. "BYPASS,Bypass of the programmable IO one bit for each IO pin: BYPASS[i] is for IO pin i. When ENABLED is '1' this field is used. When ENABLED is '0' this field is NOT used and SMARTIO fabric is always bypassed."
|
|
group.long ($2+0x10)++0x3
|
|
line.long 0x0 "SYNC_CTL,Synchronization control register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "CHIP_SYNC_EN,Synchronization of the chip input signals to 'clk_fabric' one bit for each input: CHIP_SYNC_EN[i] is for input i."
|
|
hexmask.long.byte 0x0 0.--7. 1. "IO_SYNC_EN,Synchronization of the IO pin input signals to 'clk_fabric' one bit for each IO pin: IO_SYNC_EN[i] is for IO pin i."
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "LUT_SEL[$1],LUT component input selection"
|
|
hexmask.long.byte 0x0 16.--19. 1. "LUT_TR2_SEL,LUT input signal 'tr2_in' source selection. Encoding is the same as for LUT_TR1_SEL."
|
|
hexmask.long.byte 0x0 8.--11. 1. "LUT_TR1_SEL,LUT input signal 'tr1_in' source selection:"
|
|
hexmask.long.byte 0x0 0.--3. 1. "LUT_TR0_SEL,LUT input signal 'tr0_in' source selection:"
|
|
repeat.end
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "LUT_CTL[$1],LUT component control register"
|
|
bitfld.long 0x0 8.--9. "LUT_OPC,LUT opcode specifies the LUT operation:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "LUT,LUT configuration. Depending on the LUT opcode LUT_OPC the internal state lut_reg (captured in a flip-flop) and the LUT input signals tr0_in tr1_in tr2_in the LUT configuration is used to determine the LUT output signal and the next sequential.."
|
|
repeat.end
|
|
group.long ($2+0xC0)++0x7
|
|
line.long 0x0 "DU_SEL,Data unit component input selection"
|
|
bitfld.long 0x0 28.--29. "DU_DATA1_SEL,Data unit input data 'data1_in' source selection. Encoding is the same as for DU_DATA0_SEL." "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "DU_DATA0_SEL,Data unit input data 'data0_in' source selection:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "DU_TR2_SEL,Data unit input signal 'tr2_in' source selection. Encoding is the same as for DU_TR0_SEL."
|
|
hexmask.long.byte 0x0 8.--11. 1. "DU_TR1_SEL,Data unit input signal 'tr1_in' source selection. Encoding is the same as for DU_TR0_SEL."
|
|
hexmask.long.byte 0x0 0.--3. 1. "DU_TR0_SEL,Data unit input signal 'tr0_in' source selection:"
|
|
line.long 0x4 "DU_CTL,Data unit component control register"
|
|
hexmask.long.byte 0x4 8.--11. 1. "DU_OPC,Data unit opcode specifies the data unit operation:"
|
|
bitfld.long 0x4 0.--2. "DU_SIZE,Size/width of the data unit data operands (in bits) is DU_SIZE+1. E.g. if DU_SIZE is 7 the width is 8 bits." "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0xF0)++0x3
|
|
line.long 0x0 "DATA,Data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,Data unit input data source."
|
|
tree.end
|
|
repeat.end
|
|
repeat 2. (list 0x10 0x11)(list ad:0x40321000 ad:0x40321100)
|
|
tree "PRT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTL,Control register"
|
|
bitfld.long 0x0 31. "ENABLED,Enable for programmable IO. Should only be set to '1' when the programmable IO is completely configured:" "0,1"
|
|
bitfld.long 0x0 25. "PIPELINE_EN,Enable for pipeline register:" "0,1"
|
|
bitfld.long 0x0 24. "HLD_OVR,IO cell hold override functionality. In DeepSleep power mode the HSIOM holds the IO cell output and output enable signals if Active functionality is connected to the IO pads. This is undesirable if the SMARTIO is supposed to deliver DeepSleep.." "0,1"
|
|
hexmask.long.byte 0x0 8.--12. 1. "CLOCK_SRC,Clock ('clk_fabric') and reset ('rst_fabric_n') source selection:"
|
|
hexmask.long.byte 0x0 0.--7. 1. "BYPASS,Bypass of the programmable IO one bit for each IO pin: BYPASS[i] is for IO pin i. When ENABLED is '1' this field is used. When ENABLED is '0' this field is NOT used and SMARTIO fabric is always bypassed."
|
|
group.long ($2+0x10)++0x3
|
|
line.long 0x0 "SYNC_CTL,Synchronization control register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "CHIP_SYNC_EN,Synchronization of the chip input signals to 'clk_fabric' one bit for each input: CHIP_SYNC_EN[i] is for input i."
|
|
hexmask.long.byte 0x0 0.--7. 1. "IO_SYNC_EN,Synchronization of the IO pin input signals to 'clk_fabric' one bit for each IO pin: IO_SYNC_EN[i] is for IO pin i."
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "LUT_SEL[$1],LUT component input selection"
|
|
hexmask.long.byte 0x0 16.--19. 1. "LUT_TR2_SEL,LUT input signal 'tr2_in' source selection. Encoding is the same as for LUT_TR1_SEL."
|
|
hexmask.long.byte 0x0 8.--11. 1. "LUT_TR1_SEL,LUT input signal 'tr1_in' source selection:"
|
|
hexmask.long.byte 0x0 0.--3. 1. "LUT_TR0_SEL,LUT input signal 'tr0_in' source selection:"
|
|
repeat.end
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "LUT_CTL[$1],LUT component control register"
|
|
bitfld.long 0x0 8.--9. "LUT_OPC,LUT opcode specifies the LUT operation:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "LUT,LUT configuration. Depending on the LUT opcode LUT_OPC the internal state lut_reg (captured in a flip-flop) and the LUT input signals tr0_in tr1_in tr2_in the LUT configuration is used to determine the LUT output signal and the next sequential.."
|
|
repeat.end
|
|
group.long ($2+0xC0)++0x7
|
|
line.long 0x0 "DU_SEL,Data unit component input selection"
|
|
bitfld.long 0x0 28.--29. "DU_DATA1_SEL,Data unit input data 'data1_in' source selection. Encoding is the same as for DU_DATA0_SEL." "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "DU_DATA0_SEL,Data unit input data 'data0_in' source selection:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "DU_TR2_SEL,Data unit input signal 'tr2_in' source selection. Encoding is the same as for DU_TR0_SEL."
|
|
hexmask.long.byte 0x0 8.--11. 1. "DU_TR1_SEL,Data unit input signal 'tr1_in' source selection. Encoding is the same as for DU_TR0_SEL."
|
|
hexmask.long.byte 0x0 0.--3. 1. "DU_TR0_SEL,Data unit input signal 'tr0_in' source selection:"
|
|
line.long 0x4 "DU_CTL,Data unit component control register"
|
|
hexmask.long.byte 0x4 8.--11. 1. "DU_OPC,Data unit opcode specifies the data unit operation:"
|
|
bitfld.long 0x4 0.--2. "DU_SIZE,Size/width of the data unit data operands (in bits) is DU_SIZE+1. E.g. if DU_SIZE is 7 the width is 8 bits." "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0xF0)++0x3
|
|
line.long 0x0 "DATA,Data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,Data unit input data source."
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "SRSS (SRSS Core Registers)"
|
|
base ad:0x40260000
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x0 "PWR_LVD_STATUS,High Voltage / Low Voltage Detector (HVLVD) Status Register"
|
|
bitfld.long 0x0 0. "HVLVD1_OUT,HVLVD1 output." "0: below voltage threshold,1: above voltage threshold"
|
|
line.long 0x4 "PWR_LVD_STATUS2,High Voltage / Low Voltage Detector (HVLVD) Status Register #2"
|
|
bitfld.long 0x4 0. "HVLVD2_OUT,HVLVD2 output." "0: below voltage threshold,1: above voltage threshold"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x100)++0x3
|
|
line.long 0x0 "CLK_DSI_SELECT[$1],Clock DSI Select Register"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DSI_MUX,Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH<i> using CLK_SELECT_PATH register. Using the output of this mux as HFCLK source will result in undefined behavior. It.."
|
|
repeat.end
|
|
group.long 0x140++0xB
|
|
line.long 0x0 "CLK_OUTPUT_FAST,Fast Clock Output Select Register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HFCLK_SEL1,Selects a HFCLK tree for use in fast clock output #1 logic"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "PATH_SEL1,Selects a clock path to use in fast clock output #1 logic."
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hexmask.long.byte 0x0 16.--19. 1. "FAST_SEL1,Select signal for fast clock output #1"
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hexmask.long.byte 0x0 8.--11. 1. "HFCLK_SEL0,Selects a HFCLK tree for use in fast clock output #0"
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hexmask.long.byte 0x0 4.--7. 1. "PATH_SEL0,Selects a clock path to use in fast clock output #0 logic."
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hexmask.long.byte 0x0 0.--3. 1. "FAST_SEL0,Select signal for fast clock output #0"
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line.long 0x4 "CLK_OUTPUT_SLOW,Slow Clock Output Select Register"
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hexmask.long.byte 0x4 4.--7. 1. "SLOW_SEL1,Select signal for slow clock output #1"
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hexmask.long.byte 0x4 0.--3. 1. "SLOW_SEL0,Select signal for slow clock output #0"
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line.long 0x8 "CLK_CAL_CNT1,Clock Calibration Counter 1"
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rbitfld.long 0x8 31. "CAL_COUNTER_DONE,Status bit indicating that the internal counter #1 is finished counting and CLK_CAL_CNT2.COUNTER stopped counting up" "0,1"
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hexmask.long.tbyte 0x8 0.--23. 1. "CAL_COUNTER1,Down-counter clocked on fast clock output #0 (see CLK_OUTPUT_FAST). This register always reads as zero. Counting starts internally when this register is written with a nonzero value. CAL_COUNTER_DONE goes immediately low to indicate that.."
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rgroup.long 0x14C++0x3
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line.long 0x0 "CLK_CAL_CNT2,Clock Calibration Counter 2"
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hexmask.long.tbyte 0x0 0.--23. 1. "CAL_COUNTER2,Up-counter clocked on fast clock output #1 (see CLK_OUTPUT_FAST). When CLK_CAL_CNT1.CAL_COUNTER_DONE==1 the counter is stopped and can be read by SW. Do not read this value unless CAL_COUNTER_DONE==1. The expected final value is related.."
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group.long 0x200++0xB
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line.long 0x0 "SRSS_INTR,SRSS Interrupt Register"
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bitfld.long 0x0 5. "CLK_CAL,Clock calibration counter is done. This field is reset during DEEPSLEEP mode." "0,1"
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bitfld.long 0x0 2. "HVLVD2,Interrupt for low voltage detector HVLVD2" "0,1"
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bitfld.long 0x0 1. "HVLVD1,Interrupt for low voltage detector HVLVD1" "0,1"
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line.long 0x4 "SRSS_INTR_SET,SRSS Interrupt Set Register"
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bitfld.long 0x4 5. "CLK_CAL,Set interrupt for clock calibration counter done. This field is reset during DEEPSLEEP mode." "0,1"
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bitfld.long 0x4 2. "HVLVD2,Set interrupt for low voltage detector HVLVD2" "0,1"
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bitfld.long 0x4 1. "HVLVD1,Set interrupt for low voltage detector HVLVD1" "0,1"
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line.long 0x8 "SRSS_INTR_MASK,SRSS Interrupt Mask Register"
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bitfld.long 0x8 5. "CLK_CAL,Mask for clock calibration done" "0,1"
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bitfld.long 0x8 2. "HVLVD2,Mask for low voltage detector HVLVD2" "0,1"
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bitfld.long 0x8 1. "HVLVD1,Mask for low voltage detector HVLVD1" "0,1"
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rgroup.long 0x20C++0x3
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line.long 0x0 "SRSS_INTR_MASKED,SRSS Interrupt Masked Register"
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bitfld.long 0x0 5. "CLK_CAL,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 2. "HVLVD2,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 1. "HVLVD1,Logical and of corresponding request and mask bits." "0,1"
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rgroup.long 0x1000++0x3
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line.long 0x0 "PWR_CTL,Power Mode Control"
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bitfld.long 0x0 5. "LPM_READY,Indicates whether certain low power functions are ready. The low current circuits take longer to startup after XRES HIBERNATE wakeup or supply supervision reset wakeup than the normal mode circuits. HIBERNATE mode may be entered regardless.." "0: If a low power circuit operation is requested,1: Normal operation"
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bitfld.long 0x0 4. "DEBUG_SESSION,Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1)" "0: No debug session active,1: Debug session is active. Power modes behave.."
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bitfld.long 0x0 0.--1. "POWER_MODE,Current power mode of the device. Note that this field cannot be read in all power modes on actual silicon." "0: System is resetting.,1: At least one CPU is running.,2: No CPUs are running. Peripherals may be running.,3: Main high-frequency clock is off; low speed.."
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group.long 0x1004++0x7
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line.long 0x0 "PWR_CTL2,Power Mode Control 2"
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bitfld.long 0x0 31. "PLL_LS_BYPASS,Bypass level shifter inside the PLL. Unused if no PLL is present in the product." "0: Do not bypass the level shifter,1: Bypass the level shifter"
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bitfld.long 0x0 28. "BGREF_LPMODE,Control the circuit-level power mode of the Bandgap Reference circuits." "0: Bandgap Reference circuits operate in higher..,1: Bandgap Reference circuits operate in low power"
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bitfld.long 0x0 27. "PORBOD_LPMODE,Control the power mode of the POR/BOD circuits. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES HIBERNATE wakeup or supply supervision reset." "0: POR/BOD circuits operate in normal mode,1: POR/BOD circuits operate in low power mode"
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bitfld.long 0x0 26. "REFI_LPMODE,Control the power mode of the reference current generator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES HIBERNATE wakeup or supply supervision reset." "0: Current reference generator operates in normal..,1: Current reference generator operates in low.."
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rbitfld.long 0x0 25. "REFI_OK,Indicates that the current reference is ready. Due to synchronization delays it may take two IMO clock cycles for hardware to clear this bit after asserting REFI_DIS=1." "0,1"
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bitfld.long 0x0 24. "REFI_DIS,N/A" "0,1"
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bitfld.long 0x0 22. "REFVBUF_LPMODE,Control the power mode of the 800mV voltage reference buffer. The value in this register is ignored and normal mode is used until LPM_READY==1." "0: Voltage Reference Buffer operates in normal mode,1: Voltage Reference Buffer operates in low power.."
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rbitfld.long 0x0 21. "REFVBUF_OK,Indicates that the voltage reference buffer is ready. Due to synchronization delays it may take two IMO clock cycles for hardware to clear this bit after asserting REFVBUF_DIS=1." "0,1"
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bitfld.long 0x0 20. "REFVBUF_DIS,Disable the voltage reference buffer. Firmware should only disable the buffer when there is no connected circuit that is using it. SRSS circuits that require it are the PLL and ECO. A particular product may have circuits outside the SRSS.." "0,1"
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rbitfld.long 0x0 17. "REFV_OK,Indicates that the normal mode of the voltage reference is ready." "0,1"
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bitfld.long 0x0 16. "REFV_DIS,N/A" "0,1"
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bitfld.long 0x0 12. "NWELL_REG_DIS,Explicitly disable the Nwell regulator. This register is only reset by XRES HIBERNATE wakeup or supply supervision reset." "0: Nwell Regulator is on,1: Nwell Regulator is explicitly disabled"
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bitfld.long 0x0 8. "RET_REG_DIS,Explicitly disable the Retention regulator. This register is only reset by XRES HIBERNATE wakeup or supply supervision reset." "0: Retention Regulator is not explicitly disabled,1: Retention Regulator is explicitly disabled"
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bitfld.long 0x0 4. "DPSLP_REG_DIS,Explicity disable the DeepSleep regulator including circuits shared with the Active Regulator. This register must not be set except as part of a Cypress-provided sequence or API such as the PMIC case described below. This register is.." "0: DeepSleep Regulator is not explicitly disabled,1: DeepSleep Regulator is explicitly disabled"
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bitfld.long 0x0 2. "LINREG_LPMODE,Control the power mode of the Linear Regulator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES HIBERNATE wakeup or supply supervision reset." "0: Linear Regulator operates in normal mode,1: Linear Regulator operates in low power mode"
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rbitfld.long 0x0 1. "LINREG_OK,Status of the linear Core Regulator." "0,1"
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bitfld.long 0x0 0. "LINREG_DIS,Explicitly disable the linear Core Regulator. Write zero for Traveo II devices. This register is only reset by XRES HIBERNATE wakeup or supply supervision reset." "0: Linear Core Regulator is not explicitly disabled,1: Linear Core Regulator is explicitly disabled"
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line.long 0x4 "PWR_HIBERNATE,HIBERNATE Mode Register"
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bitfld.long 0x4 31. "HIBERNATE,Firmware sets this bit to enter HIBERNATE mode. The system will enter HIBERNATE mode immediately after writing to this bit and will wakeup only in response to XRES or WAKEUP event. Both UNLOCK and FREEZE must have been set correctly in a.." "0,1"
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bitfld.long 0x4 30. "HIBERNATE_DISABLE,Hibernate disable bit." "0: Normal operation,1: Further writes to this register are ignored"
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hexmask.long.byte 0x4 24.--27. 1. "MASK_HIBPIN,When set HIBERNATE will wakeup if the corresponding pin input matches the POLARITY_HIBPIN setting. Each bit corresponds to one of the wakeup pins."
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hexmask.long.byte 0x4 20.--23. 1. "POLARITY_HIBPIN,Each bit sets the active polarity of the corresponding wakeup pin."
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bitfld.long 0x4 19. "MASK_HIBWDT,When set HIBERNATE will wakeup for WDT interrupt" "0,1"
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bitfld.long 0x4 18. "MASK_HIBALARM,When set HIBERNATE will wakeup for a RTC interrupt" "0,1"
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bitfld.long 0x4 17. "FREEZE,Firmware sets this bit to freeze the configuration mode and state of all GPIOs and SIOs in the system. When entering HIBERNATE mode the first write instructs DEEPSLEEP peripherals that they cannot ignore the upcoming freeze command. This.." "0,1"
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hexmask.long.byte 0x4 8.--15. 1. "UNLOCK,This byte must be set to 0x3A for FREEZE or HIBERNATE fields to operate. Any other value in this register will cause FREEZE/HIBERNATE to have no effect except as noted in the FREEZE description."
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hexmask.long.byte 0x4 0.--7. 1. "TOKEN,Contains a 8-bit token that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware to differentiate WAKEUP from a general RESET event. Note that waking up from HIBERNATE using XRES will reset this register."
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group.long 0x1010++0xB
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line.long 0x0 "PWR_BUCK_CTL,Buck Control Register"
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bitfld.long 0x0 31. "BUCK_OUT1_EN,Enable for vccbuck1 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. This register is only reset by XRES HIBERNATE wakeup or supply supervision reset. The regulator takes up to 600us to charge the external.." "0,1"
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bitfld.long 0x0 30. "BUCK_EN,Master enable for buck converter. This register is only reset by XRES HIBERNATE wakeup or supply supervision reset." "0,1"
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bitfld.long 0x0 0.--2. "BUCK_OUT1_SEL,Voltage output selection for vccbuck1 output. This register is only reset by XRES HIBERNATE wakeup or supply supervision reset. When increasing the voltage it can take up to 200us for the output voltage to settle. When decreasing the.." "0,1,2,3,4,5,6,7"
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line.long 0x4 "PWR_BUCK_CTL2,Buck Control Register 2"
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bitfld.long 0x4 31. "BUCK_OUT2_EN,Enable for vccbuck2 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging this will increase the.." "0,1"
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bitfld.long 0x4 30. "BUCK_OUT2_HW_SEL,Hardware control for vccbuck2 output. When this bit is set the value in BUCK_OUT2_EN is ignored and a hardware signal is used instead. If the product has supporting hardware it can directly control the enable signal for vccbuck2." "0,1"
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bitfld.long 0x4 0.--2. "BUCK_OUT2_SEL,Voltage output selection for vccbuck2 output. When increasing the voltage it can take up to 200us for the output voltage to settle. When decreasing the voltage the settling time depends on the load current." "0,1,2,3,4,5,6,7"
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line.long 0x8 "PWR_SSV_CTL,Supply Supervision Control Register"
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bitfld.long 0x8 27. "OVDVCCD_ENABLE,Enable for OVD on vccd. This cannot be disabled during normal operation." "0,1"
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bitfld.long 0x8 24. "OVDVDDA_ENABLE,Enable for OVD on vdda." "0,1"
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bitfld.long 0x8 22.--23. "OVDVDDA_ACTION,Action taken when the OVD on vdda triggers." "0: No action,1: Generate a fault,2: Reset the chip,?"
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newline
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bitfld.long 0x8 20. "OVDVDDA_VSEL,Selects the voltage threshold for OVD on vdda. Ensure OVDVDDA_ENABLE==0 before changing this setting to prevent false triggers" "0: vddd>5,1: vddd>5"
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bitfld.long 0x8 19. "OVDVDDD_ENABLE,Enable for OVD on vddd. This cannot be disabled during normal operation." "0,1"
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bitfld.long 0x8 16. "OVDVDDD_VSEL,Selects the voltage threshold for OVD on vddd. The OVD does not reliably monitor the supply during the transition." "0: vddd>5,1: vddd>5"
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bitfld.long 0x8 11. "BODVCCD_ENABLE,Enable for BOD on vccd. This cannot be disabled during normal operation." "0,1"
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bitfld.long 0x8 8. "BODVDDA_ENABLE,Enable for BOD on vdda. BODVDDA_ACTION will be triggered when the BOD is disabled. If no action is desired when disabling firmware must first write BODVDDA_ACTION=NOTHING in a separate write cycle." "0,1"
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bitfld.long 0x8 6.--7. "BODVDDA_ACTION,Action taken when the BOD on vdda triggers." "0: No action,1: Generate a fault,2: Reset the chip,?"
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newline
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bitfld.long 0x8 4. "BODVDDA_VSEL,Selects the voltage threshold for BOD on vdda. Ensure BODVDDA_ENABLE==0 before changing this setting to prevent false triggers." "0: vdda<2,1: vdda<3"
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newline
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bitfld.long 0x8 3. "BODVDDD_ENABLE,Enable for BOD on vddd. This cannot be disabled during normal operation." "0,1"
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newline
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bitfld.long 0x8 0. "BODVDDD_VSEL,Selects the voltage threshold for BOD on vddd. The BOD does not reliably monitor the supply during the transition." "0: vddd<2,1: vddd<3"
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rgroup.long 0x101C++0x3
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line.long 0x0 "PWR_SSV_STATUS,Supply Supervision Status Register"
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bitfld.long 0x0 17. "OCD_DPSLP_REG_OK,OCD indicates the current drawn from the linear DeepSleep Regulator is ok. This will always read 1 because a detected over-current condition will reset the chip." "0,1"
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bitfld.long 0x0 16. "OCD_ACT_LINREG_OK,OCD indicates the current drawn from the linear Active Regulator is ok. This will always read 1 because a detected over-current condition will reset the chip." "0,1"
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newline
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bitfld.long 0x0 10. "OVDVCCD_OK,OVD indicates vccd is ok. This will always read 1 because a detected over-over-voltage condition will reset the chip." "0,1"
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newline
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bitfld.long 0x0 9. "OVDVDDA_OK,OVD indicates vdda is ok." "0,1"
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newline
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bitfld.long 0x0 8. "OVDVDDD_OK,OVD indicates vddd is ok. This will always read 1 because a detected over-voltage condition will reset the chip." "0,1"
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newline
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bitfld.long 0x0 2. "BODVCCD_OK,BOD indicates vccd is ok. This will always read 1 because a detected brownout will reset the chip." "0,1"
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newline
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bitfld.long 0x0 1. "BODVDDA_OK,BOD indicates vdda is ok." "0,1"
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newline
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bitfld.long 0x0 0. "BODVDDD_OK,BOD indicates vddd is ok. This will always read 1 because a detected brownout will reset the chip." "0,1"
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group.long 0x1020++0xB
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line.long 0x0 "PWR_LVD_CTL,High Voltage / Low Voltage Detector (HVLVD) Configuration Register"
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bitfld.long 0x0 18. "HVLVD1_ACTION,Action taken when the threshold is crossed in the programmed directions(s)" "0: Generate an interrupt,1: Generate a fault"
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bitfld.long 0x0 16.--17. "HVLVD1_EDGE_SEL,Sets which edge(s) will trigger an action when the threshold is crossed." "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
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bitfld.long 0x0 15. "HVLVD1_EN_HT,Enable HVLVD1 voltage monitor. This detector monitors vddd only. Do not change other HVLVD1 settings when enabled." "0,1"
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bitfld.long 0x0 14. "HVLVD1_DPSLP_EN_HT,Keep HVLVD1 voltage monitor enabled during DEEPSLEEP mode. This field is only used when HVLVD1_EN_HT==1." "0,1"
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hexmask.long.byte 0x0 8.--12. 1. "HVLVD1_TRIPSEL_HT,N/A"
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bitfld.long 0x0 7. "HVLVD1_EN,Enable HVLVD1 voltage monitor. HVLVD1 does not function during DEEPSLEEP but it automatically returns to its configured setting after DEEPSLEEP wakeup. Do not change other HVLVD1 settings when enabled." "0,1"
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bitfld.long 0x0 4.--6. "HVLVD1_SRCSEL,Source selection for HVLVD1" "0: Select VDDD,1: Select AMUXBUSA (VDDD branch),2: N/A,3: N/A,4: Select AMUXBUSB (VDDD branch),?,?,?"
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hexmask.long.byte 0x0 0.--3. 1. "HVLVD1_TRIPSEL,Threshold selection for HVLVD1. Disable the detector (HVLVD1_EN=0) before changing the threshold."
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line.long 0x4 "PWR_LVD_CTL2,High Voltage / Low Voltage Detector (HVLVD) Configuration Register #2"
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bitfld.long 0x4 18. "HVLVD2_ACTION,Action taken when the threshold is crossed in the programmed directions(s)" "0: Generate an interrupt,1: Generate a fault"
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bitfld.long 0x4 16.--17. "HVLVD2_EDGE_SEL,Sets which edge(s) will trigger an action when the threshold is crossed." "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
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bitfld.long 0x4 15. "HVLVD2_EN_HT,Enable HVLVD2 voltage monitor. This detector monitors vddd only. Do not change other HVLVD2 settings when enabled." "0,1"
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bitfld.long 0x4 14. "HVLVD2_DPSLP_EN_HT,Keep HVLVD2 voltage monitor enabled during DEEPSLEEP mode. This field is only used when HVLVD1_EN_HT==1." "0,1"
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hexmask.long.byte 0x4 8.--12. 1. "HVLVD2_TRIPSEL_HT,N/A"
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line.long 0x8 "PWR_REGHC_CTL,REGHC Control Register"
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bitfld.long 0x8 31. "REGHC_CONFIGURED,Indicates the REGHC has been configured. This is used to know if REGHC should be enabled in response to a debug power up request. Do not change REGHC settings after this bit is set high." "0,1"
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bitfld.long 0x8 30. "REGHC_TRANS_USE_OCD,N/A" "0,1"
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hexmask.long.word 0x8 20.--29. 1. "REGHC_PMIC_STATUS_WAIT,Wait count in 4us steps after PMIC status ok. This is used by the hardware sequencer to allow additional settling time before disabling the internal regulator. The LSB is 32 IMO periods which results in a nominal LSB step of 4us."
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bitfld.long 0x8 19. "REGHC_PMIC_STATUS_POLARITY,The polarity used to trigger a reset action based on the PMIC status input. The reset system triggers a reset when the unmasked PMIC status matches this value." "0,1"
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bitfld.long 0x8 18. "REGHC_PMIC_STATUS_INEN,Input buffer enable for PMIC status input. Set this bit high to enable the input receiver." "0,1"
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bitfld.long 0x8 17. "REGHC_PMIC_CTL_POLARITY,Polarity used to enable the PMIC. The sequencer uses REGHC_PMIC_CTL_POLARITY to enable the PMIC and it uses the complement to disable the PMIC." "0,1"
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bitfld.long 0x8 16. "REGHC_PMIC_CTL_OUTEN,Output enable for PMIC enable pin. Set this bit high to enable the driver on this pin." "0,1"
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bitfld.long 0x8 12.--14. "REGHC_PMIC_RADJ,Reset voltage adjustment for PMIC as a factor (Vfbk/Vref) where Vfbk is the feedback voltage and Vref is the PMIC internal reference. The reset voltage adjustment circuit is enabled by the hardware sequencer if REGHC_PMIC_USE_RADJ=1." "0: Vfbk/Vref=1,1: Vfbk/Vref=1,2: Vfbk/Vref=1,3: Vfbk/Vref=1,4: Vfbk/Vref=1,5: Vfbk/Vref=1,6: Vfbk/Vref=1,7: Vfbk/Vref=1"
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bitfld.long 0x8 11. "REGHC_PMIC_USE_RADJ,Controls whether hardware sequencer enables reset voltage adjustment circuit when enabling a PMIC." "0,1"
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bitfld.long 0x8 10. "REGHC_PMIC_USE_LINREG,For REGHC external PMIC mode controls whether hardware sequencer keeps the internal Active Linear Regulator enabled to improve supply supervision of vccd. When using this feature if the PMIC fails to keep vccd above the internal.." "0: Internal Active Linear Regulator disabled after..,1: Internal Active Linear Regulator kept enabled"
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hexmask.long.byte 0x8 4.--8. 1. "REGHC_VADJ,Regulator output trim according to the formula vadj=(1.020V + REGHC_VADJ*0.005V) plus an offset described below. For example 0x1A=>1.15V (nominal)."
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bitfld.long 0x8 2.--3. "REGHC_PMIC_DRV_VOUT,Setting for DRV_VOUT pin for PMIC mode. See REGHC_VADJ for calculation of vadj." "0: DRV_VOUT=vccd*0,1: DRV_VOUT=vccd*0,2: DRV_VOUT=vccd*0,3: DRV_VOUT=vccd"
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bitfld.long 0x8 0. "REGHC_MODE,REGHC control mode:" "0: external transistor connected,1: external PMIC connected"
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rgroup.long 0x102C++0x3
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line.long 0x0 "PWR_REGHC_STATUS,REGHC Status Register"
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bitfld.long 0x0 31. "REGHC_SEQ_BUSY,Indicates the REGHC enable/disable sequencer is busy transitioning to/from REGHC." "0: Sequencer is not busy;,1: Sequencer is busy either enabling or disabling.."
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newline
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bitfld.long 0x0 12. "REGHC_PMIC_STATUS_OK,Indicates the PMIC status is ok. This includes polarity adjustment according to REGHC_PMIC_STATUS_POLARITY." "0: PMIC status is not ok or PMIC input buffer is..,1: PMIC status input buffer is enabled and.."
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newline
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bitfld.long 0x0 9. "REGHC_OV_OUT,N/A" "0,1"
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|
newline
|
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bitfld.long 0x0 8. "REGHC_UV_OUT,N/A" "0,1"
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newline
|
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bitfld.long 0x0 2. "REGHC_CKT_OK,Indicates the REGHC circuit is enabled and operating. It does not indicate that the voltage and current are within required limits for robust operation." "0: REGHC circuit is not ready,1: REGHC circuit is enabled and operating"
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newline
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bitfld.long 0x0 1. "REGHC_OCD_OK,Indicates the over-current detector is operating and the current drawn from REGHC is within limits. OCD is only a choice for transistor mode and it is disabled for PMIC mode." "0: Current measurement exceeds limit or detector is..,1: Current measurement within limit"
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newline
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bitfld.long 0x0 0. "REGHC_ENABLED,Indicates the state of the REGHC enable/disable sequencer. This bit is only valid when REGHC_SEQ_BUSY==0." "0: REGHC sequencer indicates REGHC is disabled,1: REGHC sequencer indicates REGHC is enabled"
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|
group.long 0x1030++0x3
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|
line.long 0x0 "PWR_REGHC_CTL2,REGHC Control Register 2"
|
|
bitfld.long 0x0 31. "REGHC_EN,Enable REGHC. This bit will not set if REGHC_CONFIGURED==0. Use PWR_REGHC_STATUS.ENABLED to know the actual status of REGHC. It will differ from this bit in the following cases:" "0,1"
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|
newline
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hexmask.long.byte 0x0 0.--7. 1. "REGHC_PMIC_STATUS_TIMEOUT,Timeout while waiting for REGHC_PMIC_STATUS_OK==1 when switching to PMIC."
|
|
group.long 0x1038++0x3
|
|
line.long 0x0 "PWR_REGHC_CTL4,REGHC Control Register 4"
|
|
bitfld.long 0x0 31. "REGHC_PMIC_DPSLP,When operating in PMIC mode configures PMIC behavior during DEEPSLEEP." "0: Device operates from internal regulators during..,1: DEEPSLEEP transition does not change PMIC enable"
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newline
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bitfld.long 0x0 30. "REGHC_PMIC_VADJ_DIS,When operating in PMIC mode disables the VADJ circuitry. This can be used to decrease current consumption if the entire feedback network is outside the device." "0: Device generates VADJ when PMIC is enabled,1: Device does not generate VADJ"
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|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
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|
group.long ($2+0x1040)++0x3
|
|
line.long 0x0 "PWR_HIB_DATA[$1],HIBERNATE Data Register"
|
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hexmask.long 0x0 0.--31. 1. "HIB_DATA,Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register."
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|
repeat.end
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group.long 0x10C0++0x3
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line.long 0x0 "PWR_PMIC_CTL,PMIC Control Register"
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|
bitfld.long 0x0 31. "PMIC_CONFIGURED,Indicates the PMIC has been configured. This is used to know if PMIC should be enabled in response to a debug power up request. Do not change PMIC settings after this bit is set high." "0,1"
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newline
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hexmask.long.word 0x0 20.--29. 1. "PMIC_STATUS_WAIT,Wait count in 4us steps after PMIC status ok. This is used by the hardware sequencer to allow additional settling time before disabling the internal regulator. The LSB is 32 IMO periods which results in a nominal LSB step of 4us."
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newline
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bitfld.long 0x0 19. "PMIC_STATUS_POLARITY,The polarity used to trigger a reset action based on the PMIC status input. The reset system triggers a reset when the unmasked PMIC status matches this value." "0,1"
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newline
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bitfld.long 0x0 18. "PMIC_STATUS_INEN,Input buffer enable for PMIC status input. Set this bit high to enable the input receiver." "0,1"
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newline
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bitfld.long 0x0 17. "PMIC_CTL_POLARITY,Polarity used to enable the PMIC. The sequencer uses PMIC_CTL_POLARITY to enable the PMIC and it uses the complement to disable the PMIC." "0,1"
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newline
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bitfld.long 0x0 16. "PMIC_CTL_OUTEN,Output enable for PMIC enable pin. Set this bit high to enable the driver on this pin." "0,1"
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newline
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bitfld.long 0x0 15. "PMIC_VADJ_BUF_EN,Analog buffer enable on voltage adjust output. Write this bit depending on the type of PMIC connected:" "0: Bypass buffer,1: Use analog buffer"
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newline
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bitfld.long 0x0 10. "PMIC_USE_LINREG,Controls whether hardware sequencer keeps the internal Active Linear Regulator enabled to improve supply supervision of vccd. When using this feature if the PMIC fails to keep vccd above the internal regulator target then the internal.." "0: Internal Active Linear Regulator disabled after..,1: Internal Active Linear Regulator kept enabled"
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newline
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hexmask.long.byte 0x0 4.--8. 1. "PMIC_VADJ,Voltage adjustment output setting. The lookup table in this field requires the proper setting in PMIC_VREF for the chosen PMIC. This field has no effect when PMIC_VREF selects no scaling. The feedback tap point is at a vccd pad inside the.."
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newline
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bitfld.long 0x0 2.--3. "PMIC_VREF,PMIC reference voltage setting. This selects the scaling factor used to generate the output voltage (vout) given the feedback voltage (vfb) for the chosen PMIC. For a PMIC that compares vfb to an internal reference voltage (vref) according to.." "0: Scale for vref=0,1: Scale for vref=0,2: Scale for vref=0,3: No scaling"
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|
rgroup.long 0x10C4++0x3
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line.long 0x0 "PWR_PMIC_STATUS,PMIC Status Register"
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|
bitfld.long 0x0 31. "PMIC_SEQ_BUSY,Indicates the PMIC enable/disable sequencer is busy transitioning to/from PMIC." "0: Sequencer is not busy;,1: Sequencer is busy either enabling or disabling.."
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newline
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bitfld.long 0x0 12. "PMIC_STATUS_OK,Indicates the PMIC status is ok. This includes polarity adjustment according to PMIC_STATUS_POLARITY." "0: PMIC status is not ok or PMIC input buffer is..,1: PMIC status input buffer is enabled and.."
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newline
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bitfld.long 0x0 0. "PMIC_ENABLED,Indicates the state of the PMIC enable/disable sequencer. This bit is only valid when PMIC_SEQ_BUSY==0." "0: PMIC sequencer indicates PMIC is disabled,1: PMIC sequencer indicates PMIC is enabled"
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|
group.long 0x10C8++0x3
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|
line.long 0x0 "PWR_PMIC_CTL2,PMIC Control Register 2"
|
|
bitfld.long 0x0 31. "PMIC_EN,Enable PMIC. This bit will not set if PMIC_CONFIGURED==0. Use PWR_PMIC_STATUS.ENABLED to know the actual status of PMIC. It will differ from this bit in the following cases:" "0,1"
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|
newline
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hexmask.long.byte 0x0 0.--7. 1. "PMIC_STATUS_TIMEOUT,Timeout while waiting for PMIC_STATUS_OK==1 when switching to PMIC."
|
|
group.long 0x10D0++0x3
|
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line.long 0x0 "PWR_PMIC_CTL4,PMIC Control Register 4"
|
|
bitfld.long 0x0 31. "PMIC_DPSLP,Configures PMIC behavior during DEEPSLEEP." "0: Device operates from internal regulators during..,1: DEEPSLEEP transition does not change PMIC enable"
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|
newline
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bitfld.long 0x0 30. "PMIC_VADJ_DIS,Disables the VADJ circuitry. This can be used to decrease current consumption if the entire feedback network is outside the device." "0: Device generates VADJ when PMIC is enabled,1: Device does not generate VADJ"
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|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1200)++0x3
|
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line.long 0x0 "CLK_PATH_SELECT[$1],Clock Path Select Register"
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bitfld.long 0x0 0.--2. "PATH_MUX,Selects a source for clock PATH<i>. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. It takes four cycles of the originally selected clock to switch away.." "0: IMO - Internal R/C Oscillator,1: EXTCLK - External Clock Pin,2: ECO - External-Crystal Oscillator,3: ALTHF - Alternate High-Frequency clock input..,4: DSI_MUX - Output of DSI mux for this path. Using..,5: LPECO - Low-Power External-Crystal Oscillator,?,?"
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|
repeat.end
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1240)++0x3
|
|
line.long 0x0 "CLK_ROOT_SELECT[$1],Clock Root Select Register"
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|
bitfld.long 0x0 31. "ENABLE,Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0 which cannot be disabled." "0,1"
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newline
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bitfld.long 0x0 8. "DIRECT_MUX,Direct selection mux that allows IMO to bypass most of the clock mux structure. For products with multiple regulators this mux can be used to reduce current without requiring significant reconfiguration of the clocking network. The.." "0: ROOT_MUX,1: Select ROOT_MUX selection"
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newline
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bitfld.long 0x0 4.--5. "ROOT_DIV,Selects predivider value for this clock root and DSI input. This divider is after DIRECT_MUX. For products with DSI the output of this mux is routed to DSI for use as a signal. For products with clock supervision the output of this mux is.." "0: Transparent mode feed through selected clock..,1: Divide selected clock source by 2,2: Divide selected clock source by 4,3: Divide selected clock source by 8"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "ROOT_MUX,Selects a clock path as the root of HFCLK<k> and for SRSS DSI input <k>. Use CLK_SELECT_PATH[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific) and the control and bypass mux selections of these are.."
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repeat.end
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|
tree "CSV_HF (Clock Supervisor (CSV) registers for Root clocks)"
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base ad:0x40261400
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repeat 3. (list 0x0 0x1 0x2)(list ad:0x40261400 ad:0x40261410 ad:0x40261420)
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|
tree "CSV[$1]"
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base $2
|
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group.long ($2)++0xB
|
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line.long 0x0 "REF_CTL,Clock Supervision Reference Control"
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bitfld.long 0x0 31. "CSV_EN,Enables clock supervision both frequency and loss." "0,1"
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bitfld.long 0x0 30. "CSV_ACTION,Specifies the action taken when an anomaly is detected on the monitored clock. CSV in DeepSleep domain always do a Fault report (which also wakes up the system)." "0: Do a Fault report.,1: Cause a power reset. This should only be used.."
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hexmask.long.word 0x0 0.--15. 1. "STARTUP,Startup delay time -1 (in reference clock cycles) after enable or DeepSleep wakeup from reference clock start to monitored clock start."
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line.long 0x4 "REF_LIMIT,Clock Supervision Reference Limits"
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hexmask.long.word 0x4 16.--31. 1. "UPPER,Cycle time upper limit. Set the upper limit -1 in reference clock cycles before (or same time) the next monitored clock event must happen. If a monitored clock event does not happen before this limit is reached or does not happen at all (clock.."
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hexmask.long.word 0x4 0.--15. 1. "LOWER,Cycle time lower limit. Set the lower limit -1 in reference clock cycles before the next monitored clock event is allowed to happen. If a monitored clock event happens before this limit is reached a CSV error is detected."
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line.long 0x8 "MON_CTL,Clock Supervision Monitor Control"
|
|
hexmask.long.word 0x8 0.--15. 1. "PERIOD,Period time. Set the Period -1 in monitored clock cycles before the next monitored clock event happens."
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tree.end
|
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repeat.end
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tree.end
|
|
base ad:0x40260000
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|
group.long 0x1500++0xF
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newline
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line.long 0x0 "CLK_SELECT,Clock selection register"
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bitfld.long 0x0 15. "PUMP_ENABLE,Enable the pump clock. PUMP_ENABLE and the PUMP_SEL mux are not glitch-free to minimize side-effects avoid changing the PUMP_SEL and PUMP_DIV while changing PUMP_ENABLE. To change the settings do the following:" "0,1"
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newline
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bitfld.long 0x0 12.--14. "PUMP_DIV,Division ratio for PUMPCLK. Uses selected PUMP_SEL clock as the source." "0: Transparent mode feed through selected clock..,1: Divide selected clock source by 2,2: Divide selected clock source by 4,3: Divide selected clock source by 8,4: Divide selected clock source by 16,?,?,?"
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newline
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hexmask.long.byte 0x0 8.--11. 1. "PUMP_SEL,Selects clock PATH<k> where k=PUMP_SEL. The output of this mux goes to the PUMP_DIV to make PUMPCLK Each product has a specific number of available clock paths. Selecting a path that is not implemented on a product will result in undefined.."
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newline
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bitfld.long 0x0 0.--2. "LFCLK_SEL,Select source for LFCLK. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK.." "0: ILO0 - Internal Low-speed Oscillator #0.,1: WCO - Watch-Crystal Oscillator. Requires Backup..,2: ALTLF - Alternate Low-Frequency Clock.,3: PILO - Precision ILO. If present it works in..,4: ILO1 - Internal Low-speed Oscillator #1 if..,5: ECO_PRESCALER - External-Crystal Oscillator..,6: LPECO_PRESCALER - Low-Power External-Crystal..,?"
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line.long 0x4 "CLK_TIMER_CTL,Timer Clock Control Register"
|
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bitfld.long 0x4 31. "ENABLE,Obsolete. Do not use in new designs. Keep default value in new designs." "0,1"
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newline
|
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hexmask.long.byte 0x4 16.--23. 1. "TIMER_DIV,Obsolete. Do not use in new designs. Keep default value in new designs."
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newline
|
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bitfld.long 0x4 8.--9. "TIMER_HF0_DIV,Obsolete. Do not use in new designs. Keep default value in new designs." "0: Obsolete. Do not use in new designs. Keep..,1: Obsolete. Do not use in new designs.,2: Obsolete. Do not use in new designs.,3: Obsolete. Do not use in new designs."
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newline
|
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bitfld.long 0x4 0. "TIMER_SEL,Obsolete. Do not use in new designs. Keep default value in new designs." "0: Obsolete. Do not use in new designs. Keep..,1: Obsolete. Do not use in new designs."
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line.long 0x8 "CLK_ILO0_CONFIG,ILO0 Configuration"
|
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bitfld.long 0x8 31. "ENABLE,Master enable for ILO. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register." "0,1"
|
|
newline
|
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bitfld.long 0x8 30. "ILO0_MON_ENABLE,N/A" "0,1"
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|
newline
|
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bitfld.long 0x8 0. "ILO0_BACKUP,This register indicates that ILO0 should stay enabled during XRES and HIBERNATE modes. If backup voltage domain is implemented on the product this bit also indicates if ILO0 should stay enabled through power-related resets on other.." "0: ILO0 turns off during XRES,1: ILO0 stays enabled"
|
|
line.long 0xC "CLK_ILO1_CONFIG,ILO1 Configuration"
|
|
bitfld.long 0xC 31. "ENABLE,Master enable for ILO1." "0,1"
|
|
newline
|
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bitfld.long 0xC 30. "ILO1_MON_ENABLE,N/A" "0,1"
|
|
group.long 0x1518++0xB
|
|
line.long 0x0 "CLK_IMO_CONFIG,IMO Configuration"
|
|
bitfld.long 0x0 31. "ENABLE,Master enable for IMO oscillator. This bit must be high at all times for all functions to work properly. Hardware will automatically disable the IMO during DEEPSLEEP HIBERNATE and XRES." "0,1"
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line.long 0x4 "CLK_ECO_CONFIG,ECO Configuration Register"
|
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bitfld.long 0x4 31. "ECO_EN,Master enable for ECO oscillator. Configure the settings in CLK_ECO_CONFIG2 to work with the selected crystal before enabling ECO." "0,1"
|
|
newline
|
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bitfld.long 0x4 28. "ECO_DIV_ENABLE,ECO prescaler enable command (mutually exclusive with ECO_DIV_DISABLE). ECO Prescaler only works in ACTIVE and SLEEP modes. SW sets this field to '1' to enable the divider and HW sets this field to '0' to indicate that divider enabling.." "0: Disable the divider using the ECO_DIV_DISABLE..,1: Configure CLK_ECO_PRESCALE registers"
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|
newline
|
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bitfld.long 0x4 27. "ECO_DIV_DISABLE,ECO prescaler disable command (mutually exclusive with ECO_DIV_ENABLE). SW sets this field to '1' and HW sets this field to '0'." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "AGC_EN,Automatic Gain Control (AGC) enable. When set the oscillation amplitude is controlled to the level selected by CLK_ECO_CONFIG2.ATRIM. When low the amplitude is not explicitly controlled and can be as high as the vddd supply. WARNING: use care.." "0,1"
|
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line.long 0x8 "CLK_ECO_PRESCALE,ECO Prescaler Configuration Register"
|
|
hexmask.long.word 0x8 16.--25. 1. "ECO_INT_DIV,10-bit integer value allows for ECO frequencies up to 33.55MHz. Subtract one from the desired divide value when writing this field. For example to divide by 1 write ECO_INT_DIV=0. Do not change this setting when ECO Prescaler is enabled."
|
|
newline
|
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hexmask.long.byte 0x8 8.--15. 1. "ECO_FRAC_DIV,8-bit fractional value sufficient to get prescaler output within the +/-65ppm calibration range. Do not change this setting when ECO Prescaler is enabled."
|
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newline
|
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rbitfld.long 0x8 0. "ECO_DIV_ENABLED,ECO prescaler enabled. HW sets this field to '1' as a result of an CLK_ECO_CONFIG.ECO_DIV_ENABLE command. HW sets this field to '0' as a result on a CLK_ECO_CONFIG.ECO_DIV_DISABLE command." "0,1"
|
|
rgroup.long 0x1524++0x3
|
|
line.long 0x0 "CLK_ECO_STATUS,ECO Status Register"
|
|
bitfld.long 0x0 1. "ECO_READY,Indicates the ECO internal oscillator circuit has had enough time to fully stabilize. This is the output of a counter since ECO was enabled and it does not check the ECO output. It is recommended to also confirm ECO_OK==1." "0,1"
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|
newline
|
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bitfld.long 0x0 0. "ECO_OK,Indicates the ECO internal oscillator circuit has sufficient amplitude. It may not meet the PPM accuracy or duty cycle spec." "0,1"
|
|
group.long 0x1528++0x3
|
|
line.long 0x0 "CLK_PILO_CONFIG,Precision ILO Configuration Register"
|
|
bitfld.long 0x0 31. "PILO_EN,Enable PILO. When enabling PILO set PILO_EN=1 wait 1ms then PILO_RESET_N=1 and PILO_CLK_EN=1. When disabling PILO clear PILO_EN=0 PILO_RESET_N=0 and PLO_CLK_EN=0 in the same write cycle." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "PILO_RESET_N,Reset the PILO. See PILO_EN field for required sequencing." "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "PILO_CLK_EN,Enable the PILO clock output. See PILO_EN field for required sequencing." "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--9. 1. "PILO_FFREQ,Fine frequency trim allowing +/-250ppm accuracy with periodic calibration. The nominal step size of the LSB is 8Hz."
|
|
group.long 0x1530++0x17
|
|
line.long 0x0 "CLK_FLL_CONFIG,FLL Configuration Register"
|
|
bitfld.long 0x0 31. "FLL_ENABLE,Master enable for FLL. The FLL requires firmware sequencing when enabling and disabling. Hardware handles sequencing automatically when entering/exiting DEEPSLEEP." "0: Block is powered off,1: Block is powered on"
|
|
newline
|
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bitfld.long 0x0 24. "FLL_OUTPUT_DIV,Control bits for Output divider. Set the divide value before enabling the FLL and do not change it while FLL is enabled." "0: no division,1: divide by 2"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--17. 1. "FLL_MULT,Multiplier to determine CCO frequency in multiples of the frequency of the selected reference clock (Fref)."
|
|
line.long 0x4 "CLK_FLL_CONFIG2,FLL Configuration Register 2"
|
|
hexmask.long.byte 0x4 24.--31. 1. "UPDATE_TOL,Update tolerance sets the error threshold for when the FLL will update the CCO frequency settings. The update tolerance is the allowed difference between the count value for the ideal formula and the measured value. UPDATE_TOL should be less.."
|
|
newline
|
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hexmask.long.byte 0x4 16.--23. 1. "LOCK_TOL,Lock tolerance sets the error threshold for when the FLL output is considered locked to the reference input. A high tolerance can be used to lock more quickly or allow less accuracy. The tolerance is the allowed difference between the count.."
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|
newline
|
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hexmask.long.word 0x4 0.--12. 1. "FLL_REF_DIV,Control bits for reference divider. Set the divide value before enabling the FLL and do not change it while FLL is enabled."
|
|
line.long 0x8 "CLK_FLL_CONFIG3,FLL Configuration Register 3"
|
|
bitfld.long 0x8 28.--29. "BYPASS_SEL,Bypass mux located just after FLL output. This register can be written while the FLL is enabled. When changing BYPASS_SEL do not turn off the reference clock or CCO clock for five cycles (whichever is slower). Whenever BYPASS_SEL is.." "0: Automatic using lock indicator. When unlocked..,1: Similar to AUTO except the clock is gated off..,2: Select FLL reference input (bypass mode).,3: Select FLL output. Ignores lock indicator."
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|
newline
|
|
hexmask.long.word 0x8 8.--20. 1. "SETTLING_COUNT,Number of undivided reference clock cycles to wait after changing the CCO trim until the loop measurement restarts. A delay allows the CCO output to settle and gives a more accurate measurement. The default is tuned to an 8MHz reference.."
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|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "FLL_LF_PGAIN,FLL Loop Filter Gain Setting #2. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "FLL_LF_IGAIN,FLL Loop Filter Gain Setting #1. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN."
|
|
line.long 0xC "CLK_FLL_CONFIG4,FLL Configuration Register 4"
|
|
bitfld.long 0xC 31. "CCO_ENABLE,Enable the CCO. It is required to enable the CCO before using the FLL." "0: Block is powered off,1: Block is powered on"
|
|
newline
|
|
bitfld.long 0xC 30. "CCO_HW_UPDATE_DIS,Disable CCO frequency update by FLL hardware" "0: Hardware update of CCO settings is allowed,1: Hardware update of CCO settings is disabled"
|
|
newline
|
|
hexmask.long.word 0xC 16.--24. 1. "CCO_FREQ,CCO frequency code. This is updated by HW when the FLL is enabled. It can be manually updated to use the CCO in an open loop configuration. The meaning of each frequency code depends on the range."
|
|
newline
|
|
bitfld.long 0xC 8.--10. "CCO_RANGE,Frequency range of CCO" "0: Target frequency is in range [48 64) MHz,1: Target frequency is in range [64 85) MHz,2: Target frequency is in range [85 113) MHz,3: Target frequency is in range [113 150) MHz,4: Target frequency is in range [150 200] MHz,?,?,?"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CCO_LIMIT,Maximum CCO offset allowed (used to prevent FLL dynamics from selecting an CCO frequency that the logic cannot support)"
|
|
line.long 0x10 "CLK_FLL_STATUS,FLL Status Register"
|
|
rbitfld.long 0x10 2. "CCO_READY,This indicates that the CCO is internally settled and ready to use." "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "UNLOCK_OCCURRED,This bit sets whenever the FLL is enabled and goes out of lock. This bit stays set until cleared by firmware." "0,1"
|
|
newline
|
|
rbitfld.long 0x10 0. "LOCKED,FLL Lock Indicator" "0,1"
|
|
line.long 0x14 "CLK_ECO_CONFIG2,ECO Configuration Register 2"
|
|
bitfld.long 0x14 12.--14. "GTRIM,Gain Trim - Startup time." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x14 10.--11. "RTRIM,Feedback resistor Trim" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 8.--9. "FTRIM,Filter Trim - 3rd harmonic oscillation" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x14 4.--7. 1. "ATRIM,Amplitude trim to set the crystal drive level when ECO_CONFIG.AGC_EN=1. WARNING: use care when setting this field because driving a crystal beyond its rated limit can permanently damage the crystal."
|
|
newline
|
|
bitfld.long 0x14 0.--2. "WDTRIM,Watch Dog Trim - Delta voltage below steady state level" "0,1,2,3,4,5,6,7"
|
|
repeat 15. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1600)++0x3
|
|
line.long 0x0 "CLK_PLL_CONFIG[$1],PLL Configuration Register"
|
|
bitfld.long 0x0 31. "ENABLE,Master enable for PLL. Setup FEEDBACK_DIV REFERENCE_DIV and OUTPUT_DIV at least one cycle before setting ENABLE=1." "0: Block is disabled,1: Block is enabled"
|
|
newline
|
|
bitfld.long 0x0 28.--29. "BYPASS_SEL,Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. When changing BYPASS_SEL do not turn off the reference clock or PLL clock for five cycles (whichever is slower)." "0: Automatic using lock indicator. When unlocked..,1: Similar to AUTO except the clock is gated off..,2: Select PLL reference input (bypass mode).,3: Select PLL output. Ignores lock indicator. If.."
|
|
newline
|
|
bitfld.long 0x0 27. "PLL_LF_MODE,VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled." "0: VCO frequency is [200MHz,1: VCO frequency is [170MHz"
|
|
newline
|
|
bitfld.long 0x0 25.--26. "LOCK_DELAY,N/A" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "OUTPUT_DIV,Control bits for Output divider. Set the divide value before enabling the PLL and do not change it while PLL is enabled."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "REFERENCE_DIV,Control bits for reference divider. Set the divide value before enabling the PLL and do not change it while PLL is enabled."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "FEEDBACK_DIV,Control bits for feedback divider. Set the divide value before enabling the PLL and do not change it while PLL is enabled."
|
|
repeat.end
|
|
repeat 15. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1640)++0x3
|
|
line.long 0x0 "CLK_PLL_STATUS[$1],PLL Status Register"
|
|
bitfld.long 0x0 1. "UNLOCK_OCCURRED,This bit sets whenever the PLL Lock bit goes low and stays set until cleared by firmware." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 0. "LOCKED,PLL Lock Indicator" "0,1"
|
|
repeat.end
|
|
group.long 0x1700++0x3
|
|
line.long 0x0 "CSV_REF_SEL,Select CSV Reference clock for Active domain"
|
|
bitfld.long 0x0 0.--2. "REF_MUX,Selects a source for clock clk_ref_hf. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. It takes four cycles of the originally selected clock to switch.." "0: IMO - Internal R/C Oscillator,1: EXTCLK - External Clock Pin,2: ECO - External-Crystal Oscillator,3: ALTHF - Alternate High-Frequency clock input..,?,?,?,?"
|
|
tree "CSV_ILO (CSV registers for HVILO clock)"
|
|
base ad:0x40261730
|
|
tree "CSV (ILO0 clock DeepSleep domain Clock Supervisor registers)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "REF_CTL,Clock Supervision Reference Control"
|
|
bitfld.long 0x0 31. "CSV_EN,Enables clock supervision both frequency and loss." "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "STARTUP,Startup delay time -1 (in reference clock cycles) after enable from reference clock start to monitored clock start."
|
|
line.long 0x4 "REF_LIMIT,Clock Supervision Reference Limits"
|
|
hexmask.long.byte 0x4 16.--23. 1. "UPPER,Cycle time upper limit. Set the upper limit -1 in reference clock cycles before (or same time) the next monitored clock event must happen. If a monitored clock event does not happen before this limit is reached or does not happen at all (clock.."
|
|
hexmask.long.byte 0x4 0.--7. 1. "LOWER,Cycle time lower limit. Set the lower limit -1 in reference clock cycles before the next monitored clock event is allowed to happen. If a monitored clock event happens before this limit is reached a CSV error is detected."
|
|
line.long 0x8 "MON_CTL,Clock Supervision Monitor Control"
|
|
hexmask.long.byte 0x8 0.--7. 1. "PERIOD,Period time. Set the Period -1 in monitored clock cycles before the next monitored clock event happens."
|
|
tree.end
|
|
tree.end
|
|
tree "CSV_LF (CSV registers for LF clock)"
|
|
base ad:0x40261720
|
|
tree "CSV (LF clock Clock Supervisor registers)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "REF_CTL,Clock Supervision Reference Control"
|
|
bitfld.long 0x0 31. "CSV_EN,Enables clock supervision both frequency and loss." "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "STARTUP,Startup delay time -1 (in reference clock cycles) after enable from reference clock start to monitored clock start."
|
|
line.long 0x4 "REF_LIMIT,Clock Supervision Reference Limits"
|
|
hexmask.long.byte 0x4 16.--23. 1. "UPPER,Cycle time upper limit. Set the upper limit -1 in reference clock cycles before (or same time) the next monitored clock event must happen. If a monitored clock event does not happen before this limit is reached or does not happen at all (clock.."
|
|
hexmask.long.byte 0x4 0.--7. 1. "LOWER,Cycle time lower limit. Set the lower limit -1 in reference clock cycles before the next monitored clock event is allowed to happen. If a monitored clock event happens before this limit is reached a CSV error is detected."
|
|
line.long 0x8 "MON_CTL,Clock Supervision Monitor Control"
|
|
hexmask.long.byte 0x8 0.--7. 1. "PERIOD,Period time. Set the Period -1 in monitored clock cycles before the next monitored clock event happens."
|
|
tree.end
|
|
tree.end
|
|
tree "CSV_REF (CSV registers for the CSV Reference clock)"
|
|
base ad:0x40261710
|
|
tree "CSV (Active domain Clock Supervisor (CSV) registers for CSV Reference clock)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "REF_CTL,Clock Supervision Reference Control"
|
|
bitfld.long 0x0 31. "CSV_EN,Enables clock supervision both frequency and loss." "0,1"
|
|
bitfld.long 0x0 30. "CSV_ACTION,Specifies the action taken when an anomaly is detected on the monitored clock. CSV in DeepSleep domain always do a Fault report (which also wakes up the system)." "0: Do a Fault report.,1: Cause a power reset. This should only be used.."
|
|
hexmask.long.word 0x0 0.--15. 1. "STARTUP,Startup delay time -1 (in reference clock cycles) after enable or DeepSleep wakeup from reference clock start to monitored clock start."
|
|
line.long 0x4 "REF_LIMIT,Clock Supervision Reference Limits"
|
|
hexmask.long.word 0x4 16.--31. 1. "UPPER,Cycle time upper limit. Set the upper limit -1 in reference clock cycles before (or same time) the next monitored clock event must happen. If a monitored clock event does not happen before this limit is reached or does not happen at all (clock.."
|
|
hexmask.long.word 0x4 0.--15. 1. "LOWER,Cycle time lower limit. Set the lower limit -1 in reference clock cycles before the next monitored clock event is allowed to happen. If a monitored clock event happens before this limit is reached a CSV error is detected."
|
|
line.long 0x8 "MON_CTL,Clock Supervision Monitor Control"
|
|
hexmask.long.word 0x8 0.--15. 1. "PERIOD,Period time. Set the Period -1 in monitored clock cycles before the next monitored clock event happens."
|
|
tree.end
|
|
tree.end
|
|
base ad:0x40260000
|
|
group.long 0x1800++0x7
|
|
newline
|
|
line.long 0x0 "RES_CAUSE,Reset Cause Observation Register"
|
|
bitfld.long 0x0 30. "RESET_PORVDDD,Indicator that a POR occurred. This is a high-voltage cause bit and hardware clears the other bits when this one is set. It does not block further recording of other high-voltage causes." "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RESET_STRUCT_XRES,Structural reset was asserted. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD. Hardware clears this bit during POR. This bit is not blocked by other HV cause bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RESET_PXRES,PXRES triggered. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD. Hardware clears this bit during POR. This bit is not blocked by other HV cause bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "RESET_PMIC,PMIC status triggered a reset. If PMIC control is not present hardware will never set this bit. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD. Hardware clears this bit during.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RESET_OCD_REGHC,Overcurrent detection from REGHC (if present). If REGHC is not present hardware will never set this bit. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD. Hardware clears.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "RESET_OCD_DPSLP_LINREG,Overcurrent detection on the internal VCCD supply when supplied by the DEEPSLEEP power mode linear regulator. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD. Hardware.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "RESET_OCD_ACT_LINREG,Overcurrent detection on the internal VCCD supply when supplied by the ACTIVE power mode linear regulator. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD. Hardware.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "RESET_OVDVCCD,Overvoltage detection on the internal core VCCD supply. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD. Hardware clears this bit during POR." "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "RESET_OVDVDDA,Overvoltage detection on the external VDDA supply. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD. Hardware clears this bit during POR." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "RESET_OVDVDDD,Overvoltage detection on the external VDDD supply. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD. Hardware clears this bit during POR." "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RESET_BODVCCD,Internal VCCD core supply crossed the brown-out limit. Note that this detector will detect gross issues with the internal core supply but may not catch all brown-out conditions. Functional and timing supervision (CSV WDT) is provided to.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RESET_BODVDDA,External VDDA supply crossed the brown-out limit. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD. Hardware clears this bit during POR." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RESET_BODVDDD,External VDDD supply crossed brown-out limit. Note that this cause will only be observable as long as the VDDD supply does not go below the POR (power on reset) detection limit. Below this limit it is not possible to reliably retain.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RESET_XRES,External XRES pin was asserted. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD. Hardware clears this bit during POR. This bit is not blocked by other HV cause bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RESET_MCWDT3,Multi-Counter Watchdog timer reset #3. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RESET_MCWDT2,Multi-Counter Watchdog timer reset #2. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RESET_MCWDT1,Multi-Counter Watchdog timer reset #1. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RESET_MCWDT0,Multi-Counter Watchdog timer reset #0. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RESET_SOFT,A CPU requested a system reset through it's SYSRESETREQ. This can be done via a debugger probe or in firmware. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RESET_TC_DBGRESET,Test controller or debugger asserted reset. Only resets debug domain. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RESET_DPSLP_FAULT,Fault logging system requested a reset from its DeepSleep logic. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RESET_ACT_FAULT,Fault logging system requested a reset from its Active logic. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RESET_WDT,A basic WatchDog Timer (WDT) reset has occurred since last power cycle. ULP products: This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above)." "0,1"
|
|
line.long 0x4 "RES_CAUSE2,Reset Cause Observation Register 2"
|
|
bitfld.long 0x4 16. "RESET_CSV_REF,Clock supervision logic requested a reset due to loss or frequency violation of the reference clock source that is used to monitor the other HF clock sources." "0,1"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "RESET_CSV_HF,Clock supervision logic requested a reset due to loss or frequency violation of a high-frequency clock. Each bit index K corresponds to a HFCLK<K>. Unimplemented clock bits return zero."
|
|
repeat 15. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE)(list ad:0x40261900 ad:0x40261910 ad:0x40261920 ad:0x40261930 ad:0x40261940 ad:0x40261950 ad:0x40261960 ad:0x40261970 ad:0x40261980 ad:0x40261990 ad:0x402619A0 ad:0x402619B0 ad:0x402619C0 ad:0x402619D0 ad:0x402619E0)
|
|
tree "CLK_PLL400M[$1]"
|
|
base $2
|
|
group.long ($2)++0xF
|
|
line.long 0x0 "CONFIG,400MHz PLL Configuration Register"
|
|
bitfld.long 0x0 31. "ENABLE,Master enable for PLL. Setup FEEDBACK_DIV REFERENCE_DIV and OUTPUT_DIV at least one cycle before setting ENABLE=1." "0: Block is disabled,1: Block is enabled"
|
|
bitfld.long 0x0 28.--29. "BYPASS_SEL,Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. When changing BYPASS_SEL do not turn off the reference clock or PLL clock for five cycles (whichever is slower)." "0: Automatic using lock indicator. When unlocked..,1: Similar to AUTO except the clock is gated off..,2: Select PLL reference input (bypass mode).,3: Select PLL output. Ignores lock indicator. If.."
|
|
bitfld.long 0x0 25.--26. "LOCK_DELAY,N/A" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "OUTPUT_DIV,Control bits for Output divider. Set the divide value before enabling the PLL and do not change it while PLL is enabled."
|
|
hexmask.long.byte 0x0 8.--12. 1. "REFERENCE_DIV,Control bits for reference divider. Set the divide value before enabling the PLL and do not change it while PLL is enabled."
|
|
hexmask.long.byte 0x0 0.--7. 1. "FEEDBACK_DIV,Control bits for feedback divider. Set the divide value before enabling the PLL and do not change it while PLL is enabled."
|
|
line.long 0x4 "CONFIG2,400MHz PLL Configuration Register 2"
|
|
bitfld.long 0x4 31. "FRAC_EN,Enables fractional division mode. When using fractional division mode see CLK_PLL400M_CONFIG.LOCK_DELAY for an additional configuration requirement." "0,1"
|
|
bitfld.long 0x4 28.--30. "FRAC_DITHER_EN,N/A" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "FRAC_DIV,Control bits for fractional divider. This value is interpreted as a fraction of the PFD frequency i.e. fPFD * (FRAC_DIV/2^24). This field can be dynamically updated within the 1000ppm control limit. It takes up to 115 AHB cycles to transfer.."
|
|
line.long 0x8 "CONFIG3,400MHz PLL Configuration Register 3"
|
|
bitfld.long 0x8 31. "SSCG_EN,Enables spreading mode. When using spreading see CLK_PLL400M_CONFIG.LOCK_DELAY for an additional configuration requirement." "0,1"
|
|
bitfld.long 0x8 28. "SSCG_MODE,N/A" "0,1"
|
|
bitfld.long 0x8 24. "SSCG_DITHER_EN,Enables dithering during spreading." "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x8 16.--18. "SSCG_RATE,N/A" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x8 0.--9. 1. "SSCG_DEPTH,N/A"
|
|
line.long 0xC "STATUS,400MHz PLL Status Register"
|
|
bitfld.long 0xC 1. "UNLOCK_OCCURRED,This bit sets whenever the PLL Lock bit goes low and stays set until cleared by firmware." "0,1"
|
|
rbitfld.long 0xC 0. "LOCKED,PLL Lock Indicator" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40260000
|
|
group.long 0x2054++0x3
|
|
line.long 0x0 "TST_XRES_SECURE,SECURE TEST and FIRMWARE TEST Key control register"
|
|
bitfld.long 0x0 31. "SECURE_DISABLE,Disables the SECURE TEST key entry capability until next reset. Must not be set in the same write when any of the above *_WR bits are set or toggling." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 30. "SECURE_KEY_OK,Indicates that the 32-bit SECURE TEST key is observing the correct key. Secure key is not reset but it will establish low after a deep power cycle that causes it to lose its written state." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 29. "FW_KEY_OK,Indicates that the 32-bit FIRMWARE TEST key is observing the correct key. Firmware key is reset by (A)XRES and STRUCT_XRES." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "SECURE_WR,Latch enables for each of the 4 bytes in the 32-bit SECURE TEST key. Must be toggled high and then low while keeping DATA8 to the correct value."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "FW_WR,Latch enables for each of the 4 bytes in the 32-bit FIRMWARE TEST key. Must be toggled high and then low while keeping DATA8 to the correct value."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA8,Data byte to be set into either SECURE TEST or FIRMWARE TEST key. Must not be changed in the same write that is toggling any of the *_WR bits below "
|
|
wgroup.long 0x207C++0x3
|
|
line.long 0x0 "RES_PXRES_CTL,Programmable XRES Control Register"
|
|
bitfld.long 0x0 0. "PXRES_TRIGGER,Triggers PXRES. This causes a full-scope reset and reboot." "0,1"
|
|
group.long 0x3008++0x3
|
|
line.long 0x0 "PWR_TRIM_WAKE_CTL,Wakeup Trim Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "WAKE_DELAY,Wakeup holdoff specifies the number of IMO cycles for power system settling before continuing the wakeup sequence. Fastest wakeup is achieved by using the smallest number allowed for the product."
|
|
group.long 0x3014++0x3
|
|
line.long 0x0 "CLK_TRIM_ILO0_CTL,ILO0 Trim Register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "ILO0_MONTRIM,ILO0 internal monitor trim."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "ILO0_FTRIM,ILO0 frequency trims. LSB step size is 1.5 percent (typical) of the frequency."
|
|
group.long 0x3108++0x3
|
|
line.long 0x0 "PWR_TRIM_PWRSYS_CTL,Power System Trim Register"
|
|
bitfld.long 0x0 30.--31. "ACT_REG_BOOST,Controls the tradeoff between output current and internal operating current for the Active Regulator. The maximum output current depends on the silicon implementation but an application may limit its maximum current to less than that." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "ACT_REG_TRIM,Trim for the Active-Regulator. This sets the output voltage level. This register is only reset by XRES HIBERNATE wakeup or supply supervision reset. The nominal output voltage is vccd=812.5mV + ACT_REG_TRIM*12.5mV. The actual output.."
|
|
group.long 0x3114++0xB
|
|
line.long 0x0 "CLK_TRIM_PILO_CTL,PILO Trim Register"
|
|
bitfld.long 0x0 28.--30. "PILO_VTDIFF_TRIM,Trim for VT-DIFF output (internal power supply)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "PILO_ISLOPE_TRIM,Trim for beta-multiplier current slope" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--24. 1. "PILO_RES_TRIM,Trim for beta-multiplier branch current"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "PILO_NBIAS_TRIM,Trim for biasn by trimming sub-Vth NMOS width in beta-multiplier" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "PILO_COMP_TRIM,Trim for comparator bias current." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "PILO_OSC_TRIM,Trim for current in oscillator block." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "PILO_CFREQ,Coarse frequency trim to meet 32.768kHz +/-2 percent across PVT without calibration. The nominal step size of the LSB is 1kHz."
|
|
line.long 0x4 "CLK_TRIM_PILO_CTL2,PILO Trim Register 2"
|
|
hexmask.long.byte 0x4 16.--23. 1. "PILO_IREF_TRIM,Trim for current reference"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--12. 1. "PILO_IREFBM_TRIM,Trim for beta-multiplier current reference"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "PILO_VREF_TRIM,Trim for voltage reference"
|
|
line.long 0x8 "CLK_TRIM_PILO_CTL3,PILO Trim Register 3"
|
|
hexmask.long.word 0x8 0.--15. 1. "PILO_ENGOPT,Engineering options for PILO circuits"
|
|
group.long 0x3220++0x3
|
|
line.long 0x0 "CLK_TRIM_ILO1_CTL,ILO1 Trim Register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "ILO1_MONTRIM,ILO1 internal monitor trim."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "ILO1_FTRIM,ILO1 frequency trims. LSB step size is 1.5 percent (typical) of the frequency."
|
|
repeat 2. (list 0x0 0x1)(list ad:0x40268000 ad:0x40268100)
|
|
tree "MCWDT[$1]"
|
|
base $2
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x20)
|
|
tree "CTR[$1]"
|
|
group.long ($2)++0x17
|
|
line.long 0x0 "CTL,MCWDT Subcounter Control Register"
|
|
bitfld.long 0x0 31. "ENABLE,Enable subcounter. May take up to 2 clk_lf cycles to take effect. When ENABLE changes from 1->0 the counter is cleared." "0: Counter is disabled,1: Counter is enabled"
|
|
rbitfld.long 0x0 0. "ENABLED,Indicates actual state of this subcounter. May lag ENABLE by up to two clk_lf cycles." "0,1"
|
|
line.long 0x4 "LOWER_LIMIT,MCWDT Subcounter Lower Limit Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "LOWER_LIMIT,Lower limit for this MCWDT subcounter. See LOWER_ACTION."
|
|
line.long 0x8 "UPPER_LIMIT,MCWDT Subcounter Upper Limit Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "UPPER_LIMIT,Upper limit for this MCWDT subcounter. See UPPER_ACTION."
|
|
line.long 0xC "WARN_LIMIT,MCWDT Subcounter Warn Limit Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "WARN_LIMIT,Warn limit for this MCWDT subcounter. See WARN_ACTION."
|
|
line.long 0x10 "CONFIG,MCWDT Subcounter Configuration Register"
|
|
bitfld.long 0x10 31. "DEBUG_RUN,Pauses/runs this counter while a debugger is connected. Other behaviors are unchanged during debugging including service configuration updates and enable/disable. Note it may take up to two clk_lf cycles for the counter to pause due to.." "0: When debugger connected,1: When debugger connected"
|
|
bitfld.long 0x10 30. "SLEEPDEEP_PAUSE,Pauses/runs this counter when the corresponding processor is in SLEEPDEEP. Note it may take up to two clk_lf cycles for the counter to pause and up to two clk_lf cycles for it to unpause due to internal synchronization. After wakeup .." "0: Counter runs normally regardless of processor mode,1: Counter pauses when corresponding processor is.."
|
|
newline
|
|
bitfld.long 0x10 28. "DEBUG_TRIGGER_EN,Enables the trigger input for this MCWDT to pause the counter during debug mode. To pause at a breakpoint while debugging configure the trigger matrix to connect the related CPU halted signal to the trigger input for this MCWDT and.." "0: Pauses the counter whenever a debug probe is..,1: Pauses the counter whenever a debug probe is.."
|
|
bitfld.long 0x10 12. "AUTO_SERVICE,Automatically service when the count value reaches WARN_LIMIT. This allows creation of a periodic interrupt if this counter is not needed as a watchdog. This field is ignored when LOWER_ACTION<>NOTHING or when UPPER_ACTION<>NOTHING." "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "WARN_ACTION,Action taken when the count value reaches WARN_LIMIT. The minimum setting to achieve a periodic interrupt is WARN_LIMIT==1. A setting of zero will trigger once but not periodically." "0: Do nothing,1: Trigger an interrupt."
|
|
bitfld.long 0x10 4.--5. "UPPER_ACTION,Action taken if this watchdog is not serviced before UPPER_LIMIT is reached. The counter stops counting when UPPER_LIMIT is reached regardless of UPPER_ACTION setting. UPPER_ACTION is ignored (i.e. treated as NOTHING) when a debugger is.." "0: Do nothing,1: Trigger a fault. For UPPER_LIMIT >= 2: The..,2: Trigger a fault. Further trigger a system-wide..,?"
|
|
newline
|
|
bitfld.long 0x10 0.--1. "LOWER_ACTION,Action taken if this watchdog is serviced before LOWER_LIMIT is reached. LOWER_ACTION is ignored (i.e. treated as NOTHING) when a debugger is connected and/or when the corresponding processor is in SLEEPDEEP." "0: Do nothing,1: Trigger a fault. It can take up to 3 clk_lf..,2: Trigger a fault. Further trigger a system-wide..,?"
|
|
line.long 0x14 "CNT,MCWDT Subcounter Count Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "CNT,Current value of subcounter for this MCWDT. This field may lag the actual count value by up to one clk_lf cycle due to internal synchronization. When this subcounter is disabled and unlocked the count value can be written for verification and.."
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40268000
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "CPU_SELECT,MCWDT CPU selection register"
|
|
bitfld.long 0x0 0.--1. "CPU_SEL,Assigns this MCWDT to a CPU. This selects which CPU SLEEPDEEP signal is used for SLEEPDEEP_PAUSE." "0,1,2,3"
|
|
group.long ($2+0x80)++0xB
|
|
line.long 0x0 "CTR2_CTL,MCWDT Subcounter 2 Control register"
|
|
bitfld.long 0x0 31. "ENABLE,Enable subcounter. May take up to 2 clk_lf cycles to take effect. When ENABLE changes from 1->0 the counter is cleared." "0: Counter is disabled,1: Counter is enabled"
|
|
rbitfld.long 0x0 0. "ENABLED,Indicates actual state of this subcounter. May lag ENABLE by up to two clk_lf cycles." "0,1"
|
|
line.long 0x4 "CTR2_CONFIG,MCWDT Subcounter 2 Configuration register"
|
|
bitfld.long 0x4 31. "DEBUG_RUN,Pauses/runs this counter while a debugger is connected. Other behaviors are unchanged during debugging including service configuration updates and enable/disable. Note it may take up to two clk_lf cycles for the counter to pause and another.." "0: When debugger connected,1: When debugger connected"
|
|
bitfld.long 0x4 30. "SLEEPDEEP_PAUSE,Pauses/runs this counter when the corresponding processor is in SLEEPDEEP. Note it may take up to two clk_lf cycles for the counter to pause and up to two clk_lf cycles for it to unpause due to internal synchronization." "0: Counter runs normally regardless of processor mode,1: Counter pauses when corresponding processor is.."
|
|
newline
|
|
bitfld.long 0x4 28. "DEBUG_TRIGGER_EN,Enables the trigger input for this MCWDT to pause the counter during debug mode. To pause at a breakpoint while debugging configure the trigger matrix to connect the related CPU halted signal to the trigger input for this MCWDT and.." "0: Pauses the counter whenever a debug probe is..,1: Pauses the counter whenever a debug probe is.."
|
|
hexmask.long.byte 0x4 16.--20. 1. "BITS,Bit to observe for a toggle:"
|
|
newline
|
|
bitfld.long 0x4 0. "ACTION,Action taken when the specified BIT toggles." "0: Do nothing,1: Trigger an interrupt"
|
|
line.long 0x8 "CTR2_CNT,MCWDT Subcounter 2 Count Register"
|
|
hexmask.long 0x8 0.--31. 1. "CNT2,Current value of subcounter 2 for this MCWDT. This field may lag the actual count value by up to one clk_lf cycle due to internal synchronization. When this subcounter is disabled and unlocked the count value can be written for verification and.."
|
|
group.long ($2+0x90)++0x7
|
|
line.long 0x0 "LOCK,MCWDT Lock Register"
|
|
bitfld.long 0x0 0.--1. "MCWDT_LOCK,Prohibits writing control and configuration registers related to this MCWDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock." "0: No effect,1: Clears bit 0,2: Clears bit 1,3: Sets both bits 0 and 1"
|
|
line.long 0x4 "SERVICE,MCWDT Service Register"
|
|
bitfld.long 0x4 1. "CTR1_SERVICE,Services subcounter 1. This resets the count value for subcounter 1 to zero. This may take up to three clk_lf cycles to take effect. Hardware clears this bit after necessary synchronization. To ensure a pending CTR1_SERVICE write is.." "0,1"
|
|
bitfld.long 0x4 0. "CTR0_SERVICE,Services subcounter 0. This resets the count value for subcounter 0 to zero. This may take up to three clk_lf cycles to take effect. Hardware clears this bit after necessary synchronization. To ensure a pending CTR0_SERVICE write is.." "0,1"
|
|
group.long ($2+0xA0)++0xB
|
|
line.long 0x0 "INTR,MCWDT Interrupt Register"
|
|
bitfld.long 0x0 2. "CTR2_INT,MCWDT Interrupt Request for sub-counter 2. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware." "0,1"
|
|
bitfld.long 0x0 1. "CTR1_INT,MCWDT Interrupt Request for sub-counter 1. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CTR0_INT,MCWDT Interrupt Request for sub-counter 0. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware." "0,1"
|
|
line.long 0x4 "INTR_SET,MCWDT Interrupt Set Register"
|
|
bitfld.long 0x4 2. "CTR2_INT,Set interrupt for MCWDT_INT2" "0,1"
|
|
bitfld.long 0x4 1. "CTR1_INT,Set interrupt for MCWDT_INT1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CTR0_INT,Set interrupt for MCWDT_INT0" "0,1"
|
|
line.long 0x8 "INTR_MASK,MCWDT Interrupt Mask Register"
|
|
bitfld.long 0x8 2. "CTR2_INT,Mask for sub-counter 2" "0,1"
|
|
bitfld.long 0x8 1. "CTR1_INT,Mask for sub-counter 1 for warning interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "CTR0_INT,Mask for sub-counter 0 for warning interrupt" "0,1"
|
|
rgroup.long ($2+0xAC)++0x3
|
|
line.long 0x0 "INTR_MASKED,MCWDT Interrupt Masked Register"
|
|
bitfld.long 0x0 2. "CTR2_INT,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 1. "CTR1_INT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CTR0_INT,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base ad:0x4026C000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CTL,WDT Control Register"
|
|
bitfld.long 0x0 31. "ENABLE,Enable watchdog. May take up to three clk_ilo0 cycles to take effect. When ENABLE changes from 1->0 the counter is cleared. Do not enter DEEPSLEEP or HIBERNATE mode if ENABLE<>ENABLED. This can be done by waiting until ENABLE==ENABLED.." "0: Counter is disabled,1: Counter is enabled"
|
|
rbitfld.long 0x0 0. "ENABLED,Indicates actual state of watchdog. May lag ENABLE by up to three clk_ilo0 cycles." "0,1"
|
|
line.long 0x4 "LOWER_LIMIT,WDT Lower Limit Register"
|
|
hexmask.long 0x4 0.--31. 1. "LOWER_LIMIT,Lower limit for watchdog. See LOWER_ACTION."
|
|
line.long 0x8 "UPPER_LIMIT,WDT Upper Limit Register"
|
|
hexmask.long 0x8 0.--31. 1. "UPPER_LIMIT,Upper limit for watchdog. See UPPER_ACTION."
|
|
line.long 0xC "WARN_LIMIT,WDT Warn Limit Register"
|
|
hexmask.long 0xC 0.--31. 1. "WARN_LIMIT,Warn limit for watchdog. See WARN_ACTION."
|
|
line.long 0x10 "CONFIG,WDT Configuration Register"
|
|
bitfld.long 0x10 31. "DEBUG_RUN,Pauses/runs this counter while a debugger is connected. Other behaviors are unchanged during debugging including service configuration updates and enable/disable. Note it may take up to two clk_ilo0 cycles for the counter to pause and.." "0: When debugger connected,1: When debugger connected"
|
|
bitfld.long 0x10 30. "HIB_PAUSE,Pauses/runs this counter when the system is in HIBERNATE. Note it may take up to two clk_ilo0 cycles for the counter to pause due to internal synchronization. After wakeup the LOWER_ACTION is ignored until after the first service. This.." "0: Counter behaves normally during HIBERNATE,1: Counter pauses during HIBERNATE"
|
|
newline
|
|
bitfld.long 0x10 29. "DPSLP_PAUSE,Pauses/runs this counter when the system is in DEEPSLEEP. Note it may take up to two clk_ilo0 cycles for the counter to pause due to internal synchronization. During DEEPSLEEP wakeup the pause request is removed when clk_hf0 starts.." "0: Counter behaves normally during DEEPSLEEP,1: Counter pauses during DEEPSLEEP"
|
|
bitfld.long 0x10 28. "DEBUG_TRIGGER_EN,Enables the trigger input for WDT to pause the counter during debug mode. To pause at a breakpoint while debugging configure the trigger matrix to connect the related CPU halted signal to the trigger input for this WDT and then set.." "0: Pauses the counter whenever a debug probe is..,1: Pauses the counter whenever a debug probe is.."
|
|
newline
|
|
bitfld.long 0x10 12. "AUTO_SERVICE,Automatically service when the count value reaches WARN_LIMIT. This allows creation of a periodic interrupt if this counter is not needed as a watchdog. This field is ignored when LOWER_ACTION<>NOTHING or when UPPER_ACTION<>NOTHING." "0,1"
|
|
bitfld.long 0x10 8. "WARN_ACTION,Action taken when the count value reaches WARN_LIMIT. The minimum setting to achieve a periodic interrupt is WARN_LIMIT==1. A setting of zero will trigger once but not periodically." "0: Do nothing,1: Trigger an interrupt."
|
|
newline
|
|
bitfld.long 0x10 4. "UPPER_ACTION,Action taken if this watchdog is not serviced before UPPER_LIMIT is reached. The counter stops counting when UPPER_LIMIT is reached regardless of UPPER_ACTION setting. UPPER_ACTION is ignored (i.e. treated as NOTHING) when a debugger is.." "0: Do nothing,1: Trigger a reset."
|
|
bitfld.long 0x10 0. "LOWER_ACTION,Action taken if this watchdog is serviced before LOWER_LIMIT is reached. LOWER_ACTION is ignored (i.e. treated as NOTHING) when a debugger is connected and/or when the chip is in DEEPSLEEP/HIBERNATE modes." "0: No action is triggered,1: The action is triggered on same edge when it.."
|
|
line.long 0x14 "CNT,WDT Count Register"
|
|
hexmask.long 0x14 0.--31. 1. "CNT,Current value of subcounter for this WDT. This field may lag the actual count value by up to one clk_ilo0 cycle due to internal synchronization. When this subcounter is disabled and unlocked the count value can be written for verification and.."
|
|
group.long 0x40++0x7
|
|
line.long 0x0 "LOCK,WDT Lock register"
|
|
bitfld.long 0x0 0.--1. "WDT_LOCK,Prohibits writing control and configuration registers related to this WDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock." "0: No effect,1: Clears bit 0,2: Clears bit 1,3: Sets both bits 0 and 1"
|
|
line.long 0x4 "SERVICE,WDT Service register"
|
|
bitfld.long 0x4 0. "SERVICE,Services the watchdog. This resets the count value to zero. This may take up to three clk_ilo0 cycle to take effect. Hardware clears this bit after necessary synchronization. To ensure a pending SERVICE write is reflected firmware should.." "0,1"
|
|
group.long 0x50++0xB
|
|
line.long 0x0 "INTR,WDT Interrupt Register"
|
|
bitfld.long 0x0 0. "WDT,WDT Interrupt Request. This bit is set as configured by WDT action and limits. Due to internal synchronization it takes up to 8 SYSCLK cycles to update after a W1C or reading this register and during this time AHB bus is stalled." "0,1"
|
|
line.long 0x4 "INTR_SET,WDT Interrupt Set Register"
|
|
bitfld.long 0x4 0. "WDT,Set interrupt." "0,1"
|
|
line.long 0x8 "INTR_MASK,WDT Interrupt Mask Register"
|
|
bitfld.long 0x8 0. "WDT,Mask for watchdog timer. Clearing this bit will not forward the interrupt to the CPU." "0,1"
|
|
rgroup.long 0x5C++0x3
|
|
line.long 0x0 "INTR_MASKED,WDT Interrupt Masked Register"
|
|
bitfld.long 0x0 0. "WDT,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "TCPWM (Timer/Counter/PWM)"
|
|
base ad:0x40380000
|
|
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40380000 ad:0x40388000 ad:0x40390000)
|
|
tree "GRP[$1]"
|
|
base $2
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list 0x0 0x80 0x100 0x180 0x200 0x280 0x300 0x380 0x400 0x480 0x500 0x580 0x600 0x680 0x700 0x780)
|
|
tree "CNT[$1]"
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTRL,Counter control register"
|
|
bitfld.long 0x0 31. "ENABLED,Counter enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "MODE,Counter mode." "0: Timer mode,1: N/A,2: Capture mode,3: Quadrature mode Different encoding modes can be..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode."
|
|
newline
|
|
bitfld.long 0x0 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode." "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode. Input phiA.."
|
|
newline
|
|
bitfld.long 0x0 18. "ONE_SHOT,When '0' counter runs continuous. When '1' counter is turned off by hardware when a terminal count event is generated." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "UP_DOWN_MODE,Determines counter direction." "0: Count up (to PERIOD). An overflow event is..,1: Count down (to '0'). An underflow event is..,2: Count up (to PERIOD) then count down (to '0').,3: Count up (to PERIOD) then count down (to '0')."
|
|
newline
|
|
bitfld.long 0x0 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped." "0: The behavior is the same is in previous mxtcpwm..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
|
|
newline
|
|
bitfld.long 0x0 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values. This field has a function in PWM and PWM_PR modes." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM and PWM_DT modes." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,?"
|
|
newline
|
|
bitfld.long 0x0 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,?"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter. In PWM_DT mode this counter is used for dead time insertion."
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field. In PWM_DT mode this counter is used for dead time insertion (8bit dead time counter or low byte of 16-bit dead time counter)."
|
|
newline
|
|
bitfld.long 0x0 15. "RUNNING,When '0' the counter is NOT running. When '1' the counter is running." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "LINE_OUT,Indicates the actual level of the PWM line output signal." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TR_START,Indicates the actual level of the selected start trigger." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TR_STOP,Indicates the actual level of the selected stop trigger." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TR_COUNT,Indicates the actual level of the selected count trigger." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DOWN,When '0' counter is counting up. When '1' counter is counting down. In QUAD mode this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented." "0,1"
|
|
group.long ($2+0x8)++0x3
|
|
line.long 0x0 "COUNTER,Counter count register"
|
|
hexmask.long 0x0 0.--31. 1. "COUNTER,16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running."
|
|
group.long ($2+0x10)++0x23
|
|
line.long 0x0 "CC0,Counter compare/capture 0 register"
|
|
hexmask.long 0x0 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
|
|
line.long 0x4 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x4 0.--31. 1. "CC,Additional buffer for counter CC register."
|
|
line.long 0x8 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x8 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
|
|
line.long 0xC "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0xC 0.--31. 1. "CC,Additional buffer for counter CC1 register."
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line.long 0x10 "PERIOD,Counter period register"
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hexmask.long 0x10 0.--31. 1. "PERIOD,Period value: upper value of the counter. When the counter should count for n cycles this field should be set to n-1."
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line.long 0x14 "PERIOD_BUFF,Counter buffered period register"
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hexmask.long 0x14 0.--31. 1. "PERIOD,Additional buffer for counter PERIOD register."
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line.long 0x18 "LINE_SEL,Counter line selection register"
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bitfld.long 0x18 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'. Default setting is the inverted PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
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bitfld.long 0x18 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'. Default setting is the PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
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line.long 0x1C "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x1C 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL." "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL." "0,1,2,3,4,5,6,7"
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line.long 0x20 "DT,Counter PWM dead time register"
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hexmask.long.word 0x20 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain."
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hexmask.long.byte 0x20 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
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hexmask.long.byte 0x20 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
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group.long ($2+0x40)++0x17
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line.long 0x0 "TR_CMD,Counter trigger command register"
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bitfld.long 0x0 5. "CAPTURE1,SW capture 1 trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 4. "START,SW start trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 3. "STOP,SW stop trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 2. "RELOAD,SW reload trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 0. "CAPTURE0,SW capture 0 trigger. When written with '1' a capture 0 trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled.." "0,1"
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line.long 0x4 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x4 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger."
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hexmask.long.byte 0x4 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger."
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hexmask.long.byte 0x4 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger."
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hexmask.long.byte 0x4 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger. Input trigger 0 is always '0' and input trigger 1 is always '1'. If existing the one-to-one trigger inputs 'tr_one_cnt_in' (different to each counter) are selected by.."
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line.long 0x8 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x8 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger."
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hexmask.long.byte 0x8 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger. In QUAD mode this is the second phase (phi B)."
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line.long 0xC "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0xC 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 8.--9. "START_EDGE,A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 6.--7. "STOP_EDGE,A stop event will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 4.--5. "RELOAD_EDGE,A reload event will initialize the counter. When counting up the counter is initialized to '0'. When counting down the counter is initialized with PERIOD." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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line.long 0x10 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x10 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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line.long 0x14 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x14 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1. Default setting selects the compare match 0 event." "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
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bitfld.long 0x14 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0. Default setting selects the terminal count event." "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
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group.long ($2+0x70)++0xB
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line.long 0x0 "INTR,Interrupt request register"
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bitfld.long 0x0 2. "CC1_MATCH,Counter matches CC1 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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bitfld.long 0x0 1. "CC0_MATCH,Counter matches CC0 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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bitfld.long 0x0 0. "TC,Terminal count event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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line.long 0x4 "INTR_SET,Interrupt set request register"
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bitfld.long 0x4 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 0. "TC,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x8 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 0. "TC,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long ($2+0x7C)++0x3
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line.long 0x0 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x0 2. "CC1_MATCH,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 1. "CC0_MATCH,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "TC,Logical and of corresponding request and mask bits." "0,1"
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tree.end
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repeat.end
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repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list 0x800 0x880 0x900 0x980 0xA00 0xA80 0xB00 0xB80 0xC00 0xC80 0xD00 0xD80 0xE00 0xE80 0xF00 0xF80)
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tree "CNT[$1]"
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group.long ($2)++0x3
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line.long 0x0 "CTRL,Counter control register"
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bitfld.long 0x0 31. "ENABLED,Counter enable." "0,1"
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bitfld.long 0x0 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode." "0,1"
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bitfld.long 0x0 24.--26. "MODE,Counter mode." "0: Timer mode,1: N/A,2: Capture mode,3: Quadrature mode Different encoding modes can be..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode."
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bitfld.long 0x0 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode." "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode. Input phiA.."
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bitfld.long 0x0 18. "ONE_SHOT,When '0' counter runs continuous. When '1' counter is turned off by hardware when a terminal count event is generated." "0,1"
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bitfld.long 0x0 16.--17. "UP_DOWN_MODE,Determines counter direction." "0: Count up (to PERIOD). An overflow event is..,1: Count down (to '0'). An underflow event is..,2: Count up (to PERIOD) then count down (to '0').,3: Count up (to PERIOD) then count down (to '0')."
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bitfld.long 0x0 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped." "0: The behavior is the same is in previous mxtcpwm..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x0 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior:" "0,1"
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bitfld.long 0x0 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events:" "0,1"
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bitfld.long 0x0 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')." "0,1"
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bitfld.long 0x0 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values. This field has a function in PWM and PWM_PR modes." "0,1"
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bitfld.long 0x0 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM and PWM_DT modes." "0,1"
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bitfld.long 0x0 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,?"
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bitfld.long 0x0 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,?"
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rgroup.long ($2+0x4)++0x3
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line.long 0x0 "STATUS,Counter status register"
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hexmask.long.byte 0x0 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter. In PWM_DT mode this counter is used for dead time insertion."
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hexmask.long.byte 0x0 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field. In PWM_DT mode this counter is used for dead time insertion (8bit dead time counter or low byte of 16-bit dead time counter)."
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bitfld.long 0x0 15. "RUNNING,When '0' the counter is NOT running. When '1' the counter is running." "0,1"
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bitfld.long 0x0 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal." "0,1"
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bitfld.long 0x0 10. "LINE_OUT,Indicates the actual level of the PWM line output signal." "0,1"
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bitfld.long 0x0 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger." "0,1"
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bitfld.long 0x0 8. "TR_START,Indicates the actual level of the selected start trigger." "0,1"
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bitfld.long 0x0 7. "TR_STOP,Indicates the actual level of the selected stop trigger." "0,1"
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bitfld.long 0x0 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger." "0,1"
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bitfld.long 0x0 5. "TR_COUNT,Indicates the actual level of the selected count trigger." "0,1"
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bitfld.long 0x0 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger." "0,1"
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bitfld.long 0x0 0. "DOWN,When '0' counter is counting up. When '1' counter is counting down. In QUAD mode this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented." "0,1"
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group.long ($2+0x8)++0x3
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line.long 0x0 "COUNTER,Counter count register"
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hexmask.long 0x0 0.--31. 1. "COUNTER,16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running."
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group.long ($2+0x10)++0x23
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line.long 0x0 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x0 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
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line.long 0x4 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x4 0.--31. 1. "CC,Additional buffer for counter CC register."
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line.long 0x8 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x8 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
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line.long 0xC "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0xC 0.--31. 1. "CC,Additional buffer for counter CC1 register."
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line.long 0x10 "PERIOD,Counter period register"
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hexmask.long 0x10 0.--31. 1. "PERIOD,Period value: upper value of the counter. When the counter should count for n cycles this field should be set to n-1."
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line.long 0x14 "PERIOD_BUFF,Counter buffered period register"
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hexmask.long 0x14 0.--31. 1. "PERIOD,Additional buffer for counter PERIOD register."
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line.long 0x18 "LINE_SEL,Counter line selection register"
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bitfld.long 0x18 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'. Default setting is the inverted PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
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bitfld.long 0x18 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'. Default setting is the PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
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line.long 0x1C "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x1C 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL." "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL." "0,1,2,3,4,5,6,7"
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line.long 0x20 "DT,Counter PWM dead time register"
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hexmask.long.word 0x20 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain."
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hexmask.long.byte 0x20 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
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hexmask.long.byte 0x20 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
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group.long ($2+0x40)++0x17
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line.long 0x0 "TR_CMD,Counter trigger command register"
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bitfld.long 0x0 5. "CAPTURE1,SW capture 1 trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 4. "START,SW start trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 3. "STOP,SW stop trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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newline
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bitfld.long 0x0 2. "RELOAD,SW reload trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 0. "CAPTURE0,SW capture 0 trigger. When written with '1' a capture 0 trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled.." "0,1"
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line.long 0x4 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x4 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger."
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hexmask.long.byte 0x4 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger."
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hexmask.long.byte 0x4 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger."
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hexmask.long.byte 0x4 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger. Input trigger 0 is always '0' and input trigger 1 is always '1'. If existing the one-to-one trigger inputs 'tr_one_cnt_in' (different to each counter) are selected by.."
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line.long 0x8 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x8 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger."
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hexmask.long.byte 0x8 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger. In QUAD mode this is the second phase (phi B)."
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line.long 0xC "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0xC 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 8.--9. "START_EDGE,A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 6.--7. "STOP_EDGE,A stop event will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 4.--5. "RELOAD_EDGE,A reload event will initialize the counter. When counting up the counter is initialized to '0'. When counting down the counter is initialized with PERIOD." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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line.long 0x10 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x10 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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line.long 0x14 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x14 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1. Default setting selects the compare match 0 event." "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
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bitfld.long 0x14 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0. Default setting selects the terminal count event." "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
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group.long ($2+0x70)++0xB
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line.long 0x0 "INTR,Interrupt request register"
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bitfld.long 0x0 2. "CC1_MATCH,Counter matches CC1 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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bitfld.long 0x0 1. "CC0_MATCH,Counter matches CC0 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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bitfld.long 0x0 0. "TC,Terminal count event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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line.long 0x4 "INTR_SET,Interrupt set request register"
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bitfld.long 0x4 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 0. "TC,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x8 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 0. "TC,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long ($2+0x7C)++0x3
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line.long 0x0 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x0 2. "CC1_MATCH,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 1. "CC0_MATCH,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "TC,Logical and of corresponding request and mask bits." "0,1"
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tree.end
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repeat.end
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repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F)(list 0x1000 0x1080 0x1100 0x1180 0x1200 0x1280 0x1300 0x1380 0x1400 0x1480 0x1500 0x1580 0x1600 0x1680 0x1700 0x1780)
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tree "CNT[$1]"
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group.long ($2)++0x3
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line.long 0x0 "CTRL,Counter control register"
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bitfld.long 0x0 31. "ENABLED,Counter enable." "0,1"
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bitfld.long 0x0 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode." "0,1"
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bitfld.long 0x0 24.--26. "MODE,Counter mode." "0: Timer mode,1: N/A,2: Capture mode,3: Quadrature mode Different encoding modes can be..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode."
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bitfld.long 0x0 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode." "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode. Input phiA.."
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bitfld.long 0x0 18. "ONE_SHOT,When '0' counter runs continuous. When '1' counter is turned off by hardware when a terminal count event is generated." "0,1"
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bitfld.long 0x0 16.--17. "UP_DOWN_MODE,Determines counter direction." "0: Count up (to PERIOD). An overflow event is..,1: Count down (to '0'). An underflow event is..,2: Count up (to PERIOD) then count down (to '0').,3: Count up (to PERIOD) then count down (to '0')."
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bitfld.long 0x0 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped." "0: The behavior is the same is in previous mxtcpwm..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x0 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior:" "0,1"
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bitfld.long 0x0 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events:" "0,1"
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bitfld.long 0x0 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')." "0,1"
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bitfld.long 0x0 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values. This field has a function in PWM and PWM_PR modes." "0,1"
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bitfld.long 0x0 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM and PWM_DT modes." "0,1"
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bitfld.long 0x0 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,?"
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bitfld.long 0x0 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,?"
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rgroup.long ($2+0x4)++0x3
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line.long 0x0 "STATUS,Counter status register"
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hexmask.long.byte 0x0 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter. In PWM_DT mode this counter is used for dead time insertion."
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hexmask.long.byte 0x0 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field. In PWM_DT mode this counter is used for dead time insertion (8bit dead time counter or low byte of 16-bit dead time counter)."
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bitfld.long 0x0 15. "RUNNING,When '0' the counter is NOT running. When '1' the counter is running." "0,1"
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bitfld.long 0x0 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal." "0,1"
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bitfld.long 0x0 10. "LINE_OUT,Indicates the actual level of the PWM line output signal." "0,1"
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bitfld.long 0x0 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger." "0,1"
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bitfld.long 0x0 8. "TR_START,Indicates the actual level of the selected start trigger." "0,1"
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bitfld.long 0x0 7. "TR_STOP,Indicates the actual level of the selected stop trigger." "0,1"
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bitfld.long 0x0 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger." "0,1"
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bitfld.long 0x0 5. "TR_COUNT,Indicates the actual level of the selected count trigger." "0,1"
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bitfld.long 0x0 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger." "0,1"
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bitfld.long 0x0 0. "DOWN,When '0' counter is counting up. When '1' counter is counting down. In QUAD mode this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented." "0,1"
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group.long ($2+0x8)++0x3
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line.long 0x0 "COUNTER,Counter count register"
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hexmask.long 0x0 0.--31. 1. "COUNTER,16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running."
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group.long ($2+0x10)++0x23
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line.long 0x0 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x0 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
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line.long 0x4 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x4 0.--31. 1. "CC,Additional buffer for counter CC register."
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line.long 0x8 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x8 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
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line.long 0xC "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0xC 0.--31. 1. "CC,Additional buffer for counter CC1 register."
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line.long 0x10 "PERIOD,Counter period register"
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hexmask.long 0x10 0.--31. 1. "PERIOD,Period value: upper value of the counter. When the counter should count for n cycles this field should be set to n-1."
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line.long 0x14 "PERIOD_BUFF,Counter buffered period register"
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hexmask.long 0x14 0.--31. 1. "PERIOD,Additional buffer for counter PERIOD register."
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line.long 0x18 "LINE_SEL,Counter line selection register"
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bitfld.long 0x18 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'. Default setting is the inverted PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
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bitfld.long 0x18 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'. Default setting is the PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
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line.long 0x1C "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x1C 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL." "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL." "0,1,2,3,4,5,6,7"
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line.long 0x20 "DT,Counter PWM dead time register"
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hexmask.long.word 0x20 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain."
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hexmask.long.byte 0x20 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
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hexmask.long.byte 0x20 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
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group.long ($2+0x40)++0x17
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line.long 0x0 "TR_CMD,Counter trigger command register"
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bitfld.long 0x0 5. "CAPTURE1,SW capture 1 trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 4. "START,SW start trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 3. "STOP,SW stop trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 2. "RELOAD,SW reload trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 0. "CAPTURE0,SW capture 0 trigger. When written with '1' a capture 0 trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled.." "0,1"
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line.long 0x4 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x4 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger."
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hexmask.long.byte 0x4 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger."
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hexmask.long.byte 0x4 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger."
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hexmask.long.byte 0x4 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger. Input trigger 0 is always '0' and input trigger 1 is always '1'. If existing the one-to-one trigger inputs 'tr_one_cnt_in' (different to each counter) are selected by.."
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line.long 0x8 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x8 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger."
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hexmask.long.byte 0x8 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger. In QUAD mode this is the second phase (phi B)."
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line.long 0xC "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0xC 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 8.--9. "START_EDGE,A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 6.--7. "STOP_EDGE,A stop event will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 4.--5. "RELOAD_EDGE,A reload event will initialize the counter. When counting up the counter is initialized to '0'. When counting down the counter is initialized with PERIOD." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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line.long 0x10 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x10 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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line.long 0x14 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x14 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1. Default setting selects the compare match 0 event." "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
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bitfld.long 0x14 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0. Default setting selects the terminal count event." "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
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group.long ($2+0x70)++0xB
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line.long 0x0 "INTR,Interrupt request register"
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bitfld.long 0x0 2. "CC1_MATCH,Counter matches CC1 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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bitfld.long 0x0 1. "CC0_MATCH,Counter matches CC0 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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bitfld.long 0x0 0. "TC,Terminal count event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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line.long 0x4 "INTR_SET,Interrupt set request register"
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bitfld.long 0x4 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 0. "TC,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x8 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 0. "TC,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long ($2+0x7C)++0x3
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line.long 0x0 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x0 2. "CC1_MATCH,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "CC0_MATCH,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "TC,Logical and of corresponding request and mask bits." "0,1"
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tree.end
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repeat.end
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repeat 15. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E)(list 0x1800 0x1880 0x1900 0x1980 0x1A00 0x1A80 0x1B00 0x1B80 0x1C00 0x1C80 0x1D00 0x1D80 0x1E00 0x1E80 0x1F00)
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tree "CNT[$1]"
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group.long ($2)++0x3
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line.long 0x0 "CTRL,Counter control register"
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bitfld.long 0x0 31. "ENABLED,Counter enable." "0,1"
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bitfld.long 0x0 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode." "0,1"
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bitfld.long 0x0 24.--26. "MODE,Counter mode." "0: Timer mode,1: N/A,2: Capture mode,3: Quadrature mode Different encoding modes can be..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode."
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bitfld.long 0x0 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode." "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode. Input phiA.."
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bitfld.long 0x0 18. "ONE_SHOT,When '0' counter runs continuous. When '1' counter is turned off by hardware when a terminal count event is generated." "0,1"
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bitfld.long 0x0 16.--17. "UP_DOWN_MODE,Determines counter direction." "0: Count up (to PERIOD). An overflow event is..,1: Count down (to '0'). An underflow event is..,2: Count up (to PERIOD) then count down (to '0').,3: Count up (to PERIOD) then count down (to '0')."
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bitfld.long 0x0 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped." "0: The behavior is the same is in previous mxtcpwm..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x0 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior:" "0,1"
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bitfld.long 0x0 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events:" "0,1"
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bitfld.long 0x0 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')." "0,1"
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bitfld.long 0x0 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values. This field has a function in PWM and PWM_PR modes." "0,1"
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bitfld.long 0x0 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM and PWM_DT modes." "0,1"
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newline
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bitfld.long 0x0 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,?"
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newline
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bitfld.long 0x0 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,?"
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rgroup.long ($2+0x4)++0x3
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line.long 0x0 "STATUS,Counter status register"
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hexmask.long.byte 0x0 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter. In PWM_DT mode this counter is used for dead time insertion."
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hexmask.long.byte 0x0 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field. In PWM_DT mode this counter is used for dead time insertion (8bit dead time counter or low byte of 16-bit dead time counter)."
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bitfld.long 0x0 15. "RUNNING,When '0' the counter is NOT running. When '1' the counter is running." "0,1"
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bitfld.long 0x0 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal." "0,1"
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bitfld.long 0x0 10. "LINE_OUT,Indicates the actual level of the PWM line output signal." "0,1"
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bitfld.long 0x0 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger." "0,1"
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bitfld.long 0x0 8. "TR_START,Indicates the actual level of the selected start trigger." "0,1"
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bitfld.long 0x0 7. "TR_STOP,Indicates the actual level of the selected stop trigger." "0,1"
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bitfld.long 0x0 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger." "0,1"
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bitfld.long 0x0 5. "TR_COUNT,Indicates the actual level of the selected count trigger." "0,1"
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bitfld.long 0x0 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger." "0,1"
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bitfld.long 0x0 0. "DOWN,When '0' counter is counting up. When '1' counter is counting down. In QUAD mode this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented." "0,1"
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group.long ($2+0x8)++0x3
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line.long 0x0 "COUNTER,Counter count register"
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hexmask.long 0x0 0.--31. 1. "COUNTER,16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running."
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group.long ($2+0x10)++0x23
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line.long 0x0 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x0 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
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line.long 0x4 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x4 0.--31. 1. "CC,Additional buffer for counter CC register."
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line.long 0x8 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x8 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
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line.long 0xC "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0xC 0.--31. 1. "CC,Additional buffer for counter CC1 register."
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line.long 0x10 "PERIOD,Counter period register"
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hexmask.long 0x10 0.--31. 1. "PERIOD,Period value: upper value of the counter. When the counter should count for n cycles this field should be set to n-1."
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line.long 0x14 "PERIOD_BUFF,Counter buffered period register"
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hexmask.long 0x14 0.--31. 1. "PERIOD,Additional buffer for counter PERIOD register."
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line.long 0x18 "LINE_SEL,Counter line selection register"
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bitfld.long 0x18 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'. Default setting is the inverted PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
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bitfld.long 0x18 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'. Default setting is the PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
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line.long 0x1C "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x1C 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL." "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x1C 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL." "0,1,2,3,4,5,6,7"
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line.long 0x20 "DT,Counter PWM dead time register"
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hexmask.long.word 0x20 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain."
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hexmask.long.byte 0x20 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
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hexmask.long.byte 0x20 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
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group.long ($2+0x40)++0x17
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line.long 0x0 "TR_CMD,Counter trigger command register"
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bitfld.long 0x0 5. "CAPTURE1,SW capture 1 trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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newline
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bitfld.long 0x0 4. "START,SW start trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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newline
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bitfld.long 0x0 3. "STOP,SW stop trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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newline
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bitfld.long 0x0 2. "RELOAD,SW reload trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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newline
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bitfld.long 0x0 0. "CAPTURE0,SW capture 0 trigger. When written with '1' a capture 0 trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled.." "0,1"
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line.long 0x4 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x4 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger."
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newline
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hexmask.long.byte 0x4 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger."
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hexmask.long.byte 0x4 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger."
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hexmask.long.byte 0x4 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger. Input trigger 0 is always '0' and input trigger 1 is always '1'. If existing the one-to-one trigger inputs 'tr_one_cnt_in' (different to each counter) are selected by.."
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line.long 0x8 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x8 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger."
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newline
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hexmask.long.byte 0x8 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger. In QUAD mode this is the second phase (phi B)."
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line.long 0xC "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0xC 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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newline
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bitfld.long 0xC 8.--9. "START_EDGE,A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 6.--7. "STOP_EDGE,A stop event will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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newline
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bitfld.long 0xC 4.--5. "RELOAD_EDGE,A reload event will initialize the counter. When counting up the counter is initialized to '0'. When counting down the counter is initialized with PERIOD." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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newline
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bitfld.long 0xC 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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newline
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bitfld.long 0xC 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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line.long 0x10 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x10 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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newline
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bitfld.long 0x10 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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newline
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bitfld.long 0x10 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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line.long 0x14 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x14 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1. Default setting selects the compare match 0 event." "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
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newline
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bitfld.long 0x14 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0. Default setting selects the terminal count event." "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
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group.long ($2+0x70)++0xB
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line.long 0x0 "INTR,Interrupt request register"
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bitfld.long 0x0 2. "CC1_MATCH,Counter matches CC1 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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newline
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bitfld.long 0x0 1. "CC0_MATCH,Counter matches CC0 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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newline
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bitfld.long 0x0 0. "TC,Terminal count event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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line.long 0x4 "INTR_SET,Interrupt set request register"
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bitfld.long 0x4 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 0. "TC,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x8 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 0. "TC,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long ($2+0x7C)++0x3
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line.long 0x0 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x0 2. "CC1_MATCH,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "CC0_MATCH,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 0. "TC,Logical and of corresponding request and mask bits." "0,1"
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tree.end
|
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repeat.end
|
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tree.end
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repeat.end
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tree.end
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AUTOINDENT.OFF
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